gcc/config/arm/unspecs.md

   1 ;; Unspec defintions.
   2 ;; Copyright (C) 2012-2023 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 3, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; UNSPEC Usage:
  22 ;; Note: sin and cos are no-longer used.
  23 ;; Unspec enumerators for Neon are defined in neon.md.
  24 ;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
  25
  26 (define_c_enum "unspec" [
  27   UNSPEC_PUSH_MULT      ; `push multiple' operation:
  28                         ;   operand 0 is the first register,
  29                         ;   subsequent registers are in parallel (use ...)
  30                         ;   expressions.
  31   UNSPEC_PIC_SYM        ; A symbol that has been treated properly for pic
  32                         ; usage, that is, we will add the pic_register
  33                         ; value to it before trying to dereference it.
  34   UNSPEC_PIC_BASE       ; Add PC and all but the last operand together,
  35                         ; The last operand is the number of a PIC_LABEL
  36                         ; that points at the containing instruction.
  37   UNSPEC_PRLG_STK       ; A special barrier that prevents frame accesses
  38                         ; being scheduled before the stack adjustment insn.
  39   UNSPEC_REGISTER_USE   ; As USE insns are not meaningful after reload,
  40                         ; this unspec is used to prevent the deletion of
  41                         ; instructions setting registers for EH handling
  42                         ; and stack frame generation.  Operand 0 is the
  43                         ; register to "use".
  44   UNSPEC_CHECK_ARCH     ; Set CCs to indicate 26-bit or 32-bit mode.
  45   UNSPEC_WSHUFH         ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
  46   UNSPEC_WACC           ; Used by the intrinsic form of the iWMMXt WACC instruction.
  47   UNSPEC_TMOVMSK        ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
  48   UNSPEC_WSAD           ; Used by the intrinsic form of the iWMMXt WSAD instruction.
  49   UNSPEC_WSADZ          ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
  50   UNSPEC_WMACS          ; Used by the intrinsic form of the iWMMXt WMACS instruction.
  51   UNSPEC_WMACU          ; Used by the intrinsic form of the iWMMXt WMACU instruction.
  52   UNSPEC_WMACSZ         ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
  53   UNSPEC_WMACUZ         ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
  54   UNSPEC_CLRDI          ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
  55   UNSPEC_WALIGNI        ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
  56   UNSPEC_TLS            ; A symbol that has been treated properly for TLS usage.
  57   UNSPEC_PIC_LABEL      ; A label used for PIC access that does not appear in the
  58                         ; instruction stream.
  59   UNSPEC_PIC_OFFSET     ; A symbolic 12-bit OFFSET that has been treated
  60                         ; correctly for PIC usage.
  61   UNSPEC_GOTSYM_OFF     ; The offset of the start of the GOT from a
  62                         ; a given symbolic address.
  63   UNSPEC_THUMB1_CASESI  ; A Thumb1 compressed dispatch-table call.
  64   UNSPEC_RBIT           ; rbit operation.
  65   UNSPEC_SYMBOL_OFFSET  ; The offset of the start of the symbol from
  66                         ; another symbolic address.
  67   UNSPEC_MEMORY_BARRIER ; Represent a memory barrier.
  68   UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access
  69                         ; unaligned locations, on architectures which support
  70                         ; that.
  71   UNSPEC_UNALIGNED_STORE ; Same for str/strh.
  72   UNSPEC_PIC_UNIFIED    ; Create a common pic addressing form.
  73   UNSPEC_Q_SET          ; Represent setting the Q bit.
  74   UNSPEC_GE_SET         ; Represent setting the GE bits.
  75   UNSPEC_APSR_READ      ; Represent reading the APSR.
  76
  77   UNSPEC_LL             ; Represent an unpaired load-register-exclusive.
  78   UNSPEC_VRINTZ         ; Represent a float to integral float rounding
  79                         ; towards zero.
  80   UNSPEC_VRINTP         ; Represent a float to integral float rounding
  81                         ; towards +Inf.
  82   UNSPEC_VRINTM         ; Represent a float to integral float rounding
  83                         ; towards -Inf.
  84   UNSPEC_VRINTR         ; Represent a float to integral float rounding
  85                         ; FPSCR rounding mode.
  86   UNSPEC_VRINTX         ; Represent a float to integral float rounding
  87                         ; FPSCR rounding mode and signal inexactness.
  88   UNSPEC_VRINTA         ; Represent a float to integral float rounding
  89                         ; towards nearest, ties away from zero.
  90   UNSPEC_PROBE_STACK    ; Probe stack memory reference
  91   UNSPEC_NONSECURE_MEM  ; Represent non-secure memory in ARMv8-M with
  92                         ; security extension
  93   UNSPEC_SP_SET         ; Represent the setting of stack protector's canary
  94   UNSPEC_SP_TEST        ; Represent the testing of stack protector's canary
  95                         ; against the guard.
  96   UNSPEC_PIC_RESTORE    ; Use to restore fdpic register
  97
  98   UNSPEC_SXTAB16        ; Represent the SXTAB16 operation.
  99   UNSPEC_UXTAB16        ; Represent the UXTAB16 operation.
 100   UNSPEC_SXTB16         ; Represent the SXTB16 operation.
 101   UNSPEC_UXTB16         ; Represent the UXTB16 operation.
 102   UNSPEC_QADD8          ; Represent the QADD8 operation.
 103   UNSPEC_QSUB8          ; Represent the QSUB8 operation.
 104   UNSPEC_SHADD8         ; Represent the SHADD8 operation.
 105   UNSPEC_SHSUB8         ; Represent the SHSUB8 operation.
 106   UNSPEC_UHADD8         ; Represent the UHADD8 operation.
 107   UNSPEC_UHSUB8         ; Represent the UHSUB8 operation.
 108   UNSPEC_UQADD8         ; Represent the UQADD8 operation.
 109   UNSPEC_UQSUB8         ; Represent the UQSUB8 operation.
 110   UNSPEC_QADD16         ; Represent the QADD16 operation.
 111   UNSPEC_QASX           ; Represent the QASX operation.
 112   UNSPEC_QSAX           ; Represent the QSAX operation.
 113   UNSPEC_QSUB16         ; Represent the QSUB16 operation.
 114   UNSPEC_SHADD16        ; Represent the SHADD16 operation.
 115   UNSPEC_SHASX          ; Represent the SHASX operation.
 116   UNSPEC_SHSAX          ; Represent the SSAX operation.
 117   UNSPEC_SHSUB16        ; Represent the SHSUB16 operation.
 118   UNSPEC_UHADD16        ; Represent the UHADD16 operation.
 119   UNSPEC_UHASX          ; Represent the UHASX operation.
 120   UNSPEC_UHSAX          ; Represent the USAX operation.
 121   UNSPEC_UHSUB16        ; Represent the UHSUB16 operation.
 122   UNSPEC_UQADD16        ; Represent the UQADD16 operation.
 123   UNSPEC_UQASX          ; Represent the UQASX operation.
 124   UNSPEC_UQSAX          ; Represent the UQSAX operation.
 125   UNSPEC_UQSUB16        ; Represent the UQSUB16 operation.
 126   UNSPEC_SMUSD          ; Represent the SMUSD operation.
 127   UNSPEC_SMUSDX         ; Represent the SMUSDX operation.
 128   UNSPEC_USAD8          ; Represent the USAD8 operation.
 129   UNSPEC_USADA8         ; Represent the USADA8 operation.
 130   UNSPEC_SMLALD         ; Represent the SMLALD operation.
 131   UNSPEC_SMLALDX        ; Represent the SMLALDX operation.
 132   UNSPEC_SMLSLD         ; Represent the SMLSLD operation.
 133   UNSPEC_SMLSLDX        ; Represent the SMLSLDX operation.
 134   UNSPEC_SMLAWB         ; Represent the SMLAWB operation.
 135   UNSPEC_SMLAWT         ; Represent the SMLAWT operation.
 136   UNSPEC_SEL            ; Represent the SEL operation.
 137   UNSPEC_SADD8          ; Represent the SADD8 operation.
 138   UNSPEC_SSUB8          ; Represent the SSUB8 operation.
 139   UNSPEC_UADD8          ; Represent the UADD8 operation.
 140   UNSPEC_USUB8          ; Represent the USUB8 operation.
 141   UNSPEC_SADD16         ; Represent the SADD16 operation.
 142   UNSPEC_SASX           ; Represent the SASX operation.
 143   UNSPEC_SSAX           ; Represent the SSAX operation.
 144   UNSPEC_SSUB16         ; Represent the SSUB16 operation.
 145   UNSPEC_UADD16         ; Represent the UADD16 operation.
 146   UNSPEC_UASX           ; Represent the UASX operation.
 147   UNSPEC_USAX           ; Represent the USAX operation.
 148   UNSPEC_USUB16         ; Represent the USUB16 operation.
 149   UNSPEC_SMLAD          ; Represent the SMLAD operation.
 150   UNSPEC_SMLADX         ; Represent the SMLADX operation.
 151   UNSPEC_SMLSD          ; Represent the SMLSD operation.
 152   UNSPEC_SMLSDX         ; Represent the SMLSDX operation.
 153   UNSPEC_SMUAD          ; Represent the SMUAD operation.
 154   UNSPEC_SMUADX         ; Represent the SMUADX operation.
 155   UNSPEC_SSAT16         ; Represent the SSAT16 operation.
 156   UNSPEC_USAT16         ; Represent the USAT16 operation.
 157   UNSPEC_CDE            ; Custom Datapath Extension instruction.
 158   UNSPEC_CDEA           ; Custom Datapath Extension instruction.
 159   UNSPEC_VCDE           ; Custom Datapath Extension instruction.
 160   UNSPEC_VCDEA          ; Custom Datapath Extension instruction.
 161   UNSPEC_DLS            ; Used for DLS (Do Loop Start), Armv8.1-M Mainline instruction
 162   UNSPEC_PAC_NOP        ; Represents PAC signing LR
 163 ])
 164
 165
 166 (define_c_enum "unspec" [
 167   UNSPEC_WADDC          ; Used by the intrinsic form of the iWMMXt WADDC instruction.
 168   UNSPEC_WABS           ; Used by the intrinsic form of the iWMMXt WABS instruction.
 169   UNSPEC_WQMULWMR       ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
 170   UNSPEC_WQMULMR        ; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
 171   UNSPEC_WQMULWM        ; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
 172   UNSPEC_WQMULM         ; Used by the intrinsic form of the iWMMXt WQMULM instruction.
 173   UNSPEC_WQMIAxyn       ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
 174   UNSPEC_WQMIAxy        ; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
 175   UNSPEC_TANDC          ; Used by the intrinsic form of the iWMMXt TANDC instruction.
 176   UNSPEC_TORC           ; Used by the intrinsic form of the iWMMXt TORC instruction.
 177   UNSPEC_TORVSC         ; Used by the intrinsic form of the iWMMXt TORVSC instruction.
 178   UNSPEC_TEXTRC         ; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
 179   UNSPEC_GET_FPSCR_NZCVQC       ; Represent fetch of FPSCR_nzcvqc content.
 180 ])
 181
 182
 183 ;; UNSPEC_VOLATILE Usage:
 184
 185 (define_c_enum "unspecv" [
 186   VUNSPEC_BLOCKAGE      ; `blockage' insn to prevent scheduling across an
 187                         ;   insn in the code.
 188   VUNSPEC_EPILOGUE      ; `epilogue' insn, used to represent any part of the
 189                         ;   instruction epilogue sequence that isn't expanded
 190                         ;   into normal RTL.  Used for both normal and sibcall
 191                         ;   epilogues.
 192   VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap
 193                         ;   modes from arm to thumb.
 194   VUNSPEC_ALIGN         ; `align' insn.  Used at the head of a minipool table
 195                         ;   for inlined constants.
 196   VUNSPEC_POOL_END      ; `end-of-table'.  Used to mark the end of a minipool
 197                         ;   table.
 198   VUNSPEC_POOL_1        ; `pool-entry(1)'.  An entry in the constant pool for
 199                         ;   an 8-bit object.
 200   VUNSPEC_POOL_2        ; `pool-entry(2)'.  An entry in the constant pool for
 201                         ;   a 16-bit object.
 202   VUNSPEC_POOL_4        ; `pool-entry(4)'.  An entry in the constant pool for
 203                         ;   a 32-bit object.
 204   VUNSPEC_POOL_8        ; `pool-entry(8)'.  An entry in the constant pool for
 205                         ;   a 64-bit object.
 206   VUNSPEC_POOL_16       ; `pool-entry(16)'.  An entry in the constant pool for
 207                         ;   a 128-bit object.
 208   VUNSPEC_TMRC          ; Used by the iWMMXt TMRC instruction.
 209   VUNSPEC_TMCR          ; Used by the iWMMXt TMCR instruction.
 210   VUNSPEC_ALIGN8        ; 8-byte alignment version of VUNSPEC_ALIGN
 211   VUNSPEC_WCMP_EQ       ; Used by the iWMMXt WCMPEQ instructions
 212   VUNSPEC_WCMP_GTU      ; Used by the iWMMXt WCMPGTU instructions
 213   VUNSPEC_WCMP_GT       ; Used by the iwMMXT WCMPGT instructions
 214   VUNSPEC_EH_RETURN     ; Use to override the return address for exception
 215                         ; handling.
 216   VUNSPEC_ATOMIC_CAS    ; Represent an atomic compare swap.
 217   VUNSPEC_ATOMIC_XCHG   ; Represent an atomic exchange.
 218   VUNSPEC_ATOMIC_OP     ; Represent an atomic operation.
 219   VUNSPEC_LL            ; Represent a load-register-exclusive.
 220   VUNSPEC_LDRD_ATOMIC   ; Represent an LDRD used as an atomic DImode load.
 221   VUNSPEC_SC            ; Represent a store-register-exclusive.
 222   VUNSPEC_LAX           ; Represent a load-register-acquire-exclusive.
 223   VUNSPEC_SLX           ; Represent a store-register-release-exclusive.
 224   VUNSPEC_LDA           ; Represent a store-register-acquire.
 225   VUNSPEC_STL           ; Represent a store-register-release.
 226   VUNSPEC_GET_FPSCR     ; Represent fetch of FPSCR content.
 227   VUNSPEC_SET_FPSCR     ; Represent assign of FPSCR content.
 228   VUNSPEC_SET_FPSCR_NZCVQC      ; Represent assign of FPSCR_nzcvqc content.
 229   VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
 230   VUNSPEC_CDP           ; Represent the coprocessor cdp instruction.
 231   VUNSPEC_CDP2          ; Represent the coprocessor cdp2 instruction.
 232   VUNSPEC_LDC           ; Represent the coprocessor ldc instruction.
 233   VUNSPEC_LDC2          ; Represent the coprocessor ldc2 instruction.
 234   VUNSPEC_LDCL          ; Represent the coprocessor ldcl instruction.
 235   VUNSPEC_LDC2L         ; Represent the coprocessor ldc2l instruction.
 236   VUNSPEC_STC           ; Represent the coprocessor stc instruction.
 237   VUNSPEC_STC2          ; Represent the coprocessor stc2 instruction.
 238   VUNSPEC_STCL          ; Represent the coprocessor stcl instruction.
 239   VUNSPEC_STC2L         ; Represent the coprocessor stc2l instruction.
 240   VUNSPEC_MCR           ; Represent the coprocessor mcr instruction.
 241   VUNSPEC_MCR2          ; Represent the coprocessor mcr2 instruction.
 242   VUNSPEC_MRC           ; Represent the coprocessor mrc instruction.
 243   VUNSPEC_MRC2          ; Represent the coprocessor mrc2 instruction.
 244   VUNSPEC_MCRR          ; Represent the coprocessor mcrr instruction.
 245   VUNSPEC_MCRR2         ; Represent the coprocessor mcrr2 instruction.
 246   VUNSPEC_MRRC          ; Represent the coprocessor mrrc instruction.
 247   VUNSPEC_MRRC2         ; Represent the coprocessor mrrc2 instruction.
 248   VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier.
 249   VUNSPEC_APSR_WRITE     ; Represent writing the APSR.
 250   VUNSPEC_VSTR_VLDR     ; Represent the vstr/vldr instruction.
 251   VUNSPEC_CLRM_APSR     ; Represent the clearing of APSR with clrm instruction.
 252   VUNSPEC_VSCCLRM_VPR   ; Represent the clearing of VPR with vscclrm
 253                         ; instruction.
 254   VUNSPEC_VLSTM         ; Represent the lazy store multiple with vlstm
 255                         ; instruction.
 256   VUNSPEC_VLLDM         ; Represent the lazy load multiple with vlldm
 257                         ; instruction.
 258   VUNSPEC_PACBTI_NOP    ; Represents PAC signing LR + valid landing pad
 259   VUNSPEC_AUT_NOP       ; Represents PAC verifying LR
 260   VUNSPEC_BTI_NOP       ; Represent BTI
 261 ])
 262
 263 ;; Enumerators for NEON unspecs.
 264 (define_c_enum "unspec" [
 265   UNSPEC_ASHIFT_SIGNED
 266   UNSPEC_ASHIFT_UNSIGNED
 267   UNSPEC_CRC32B
 268   UNSPEC_CRC32H
 269   UNSPEC_CRC32W
 270   UNSPEC_CRC32CB
 271   UNSPEC_CRC32CH
 272   UNSPEC_CRC32CW
 273   UNSPEC_AESD
 274   UNSPEC_AESE
 275   UNSPEC_AESIMC
 276   UNSPEC_AESMC
 277   UNSPEC_AES_PROTECT
 278   UNSPEC_SHA1C
 279   UNSPEC_SHA1M
 280   UNSPEC_SHA1P
 281   UNSPEC_SHA1H
 282   UNSPEC_SHA1SU0
 283   UNSPEC_SHA1SU1
 284   UNSPEC_SHA256H
 285   UNSPEC_SHA256H2
 286   UNSPEC_SHA256SU0
 287   UNSPEC_SHA256SU1
 288   UNSPEC_VMULLP64
 289   UNSPEC_LOAD_COUNT
 290   UNSPEC_VABAL_S
 291   UNSPEC_VABAL_U
 292   UNSPEC_VABD_F
 293   UNSPEC_VABD_S
 294   UNSPEC_VABD_U
 295   UNSPEC_VABDL_S
 296   UNSPEC_VABDL_U
 297   UNSPEC_VADD
 298   UNSPEC_VADDHN
 299   UNSPEC_VRADDHN
 300   UNSPEC_VADDL_S
 301   UNSPEC_VADDL_U
 302   UNSPEC_VADDW_S
 303   UNSPEC_VADDW_U
 304   UNSPEC_VBSL
 305   UNSPEC_VCAGE
 306   UNSPEC_VCAGT
 307   UNSPEC_VCALE
 308   UNSPEC_VCALT
 309   UNSPEC_VCEQ
 310   UNSPEC_VCGE
 311   UNSPEC_VCGEU
 312   UNSPEC_VCGT
 313   UNSPEC_VCGTU
 314   UNSPEC_VCLS
 315   UNSPEC_VCONCAT
 316   UNSPEC_VCVT
 317   UNSPEC_VCVT_S
 318   UNSPEC_VCVT_U
 319   UNSPEC_VCVT_S_N
 320   UNSPEC_VCVT_U_N
 321   UNSPEC_VCVT_HF_S_N
 322   UNSPEC_VCVT_HF_U_N
 323   UNSPEC_VCVT_SI_S_N
 324   UNSPEC_VCVT_SI_U_N
 325   UNSPEC_VCVTH_S
 326   UNSPEC_VCVTH_U
 327   UNSPEC_VCVTA_S
 328   UNSPEC_VCVTA_U
 329   UNSPEC_VCVTM_S
 330   UNSPEC_VCVTM_U
 331   UNSPEC_VCVTN_S
 332   UNSPEC_VCVTN_U
 333   UNSPEC_VCVTP_S
 334   UNSPEC_VCVTP_U
 335   UNSPEC_VEXT
 336   UNSPEC_VHADD_S
 337   UNSPEC_VHADD_U
 338   UNSPEC_VRHADD_S
 339   UNSPEC_VRHADD_U
 340   UNSPEC_VHSUB_S
 341   UNSPEC_VHSUB_U
 342   UNSPEC_VLD1
 343   UNSPEC_VLD1_LANE
 344   UNSPEC_VLD2
 345   UNSPEC_VLD2_DUP
 346   UNSPEC_VLD2_LANE
 347   UNSPEC_VLD3
 348   UNSPEC_VLD3A
 349   UNSPEC_VLD3B
 350   UNSPEC_VLD3_DUP
 351   UNSPEC_VLD3_LANE
 352   UNSPEC_VLD4
 353   UNSPEC_VLD4A
 354   UNSPEC_VLD4B
 355   UNSPEC_VLD4_DUP
 356   UNSPEC_VLD4_LANE
 357   UNSPEC_VMAX
 358   UNSPEC_VMAX_U
 359   UNSPEC_VMAXNM
 360   UNSPEC_VMIN
 361   UNSPEC_VMIN_U
 362   UNSPEC_VMINNM
 363   UNSPEC_VMLA
 364   UNSPEC_VMLA_LANE
 365   UNSPEC_VMLAL_S
 366   UNSPEC_VMLAL_U
 367   UNSPEC_VMLAL_S_LANE
 368   UNSPEC_VMLAL_U_LANE
 369   UNSPEC_VMLS
 370   UNSPEC_VMLS_LANE
 371   UNSPEC_VMLSL_S
 372   UNSPEC_VMLSL_U
 373   UNSPEC_VMLSL_S_LANE
 374   UNSPEC_VMLSL_U_LANE
 375   UNSPEC_VMLSL_LANE
 376   UNSPEC_VFMA_LANE
 377   UNSPEC_VFMS_LANE
 378   UNSPEC_VMOVL_S
 379   UNSPEC_VMOVL_U
 380   UNSPEC_VMOVN
 381   UNSPEC_VMUL
 382   UNSPEC_VMULL_P
 383   UNSPEC_VMULL_S
 384   UNSPEC_VMULL_U
 385   UNSPEC_VMUL_LANE
 386   UNSPEC_VMULL_S_LANE
 387   UNSPEC_VMULL_U_LANE
 388   UNSPEC_VPADAL_S
 389   UNSPEC_VPADAL_U
 390   UNSPEC_VPADD
 391   UNSPEC_VPADDL_S
 392   UNSPEC_VPADDL_U
 393   UNSPEC_VPMAX
 394   UNSPEC_VPMAX_U
 395   UNSPEC_VPMIN
 396   UNSPEC_VPMIN_U
 397   UNSPEC_VPSMAX
 398   UNSPEC_VPSMIN
 399   UNSPEC_VPUMAX
 400   UNSPEC_VPUMIN
 401   UNSPEC_VQABS
 402   UNSPEC_VQADD_S
 403   UNSPEC_VQADD_U
 404   UNSPEC_VQDMLAL
 405   UNSPEC_VQDMLAL_LANE
 406   UNSPEC_VQDMLSL
 407   UNSPEC_VQDMLSL_LANE
 408   UNSPEC_VQDMULH
 409   UNSPEC_VQDMULH_LANE
 410   UNSPEC_VQRDMULH
 411   UNSPEC_VQRDMULH_LANE
 412   UNSPEC_VQDMULL
 413   UNSPEC_VQDMULL_LANE
 414   UNSPEC_VQMOVN_S
 415   UNSPEC_VQMOVN_U
 416   UNSPEC_VQMOVUN
 417   UNSPEC_VQNEG
 418   UNSPEC_VQSHL_S
 419   UNSPEC_VQSHL_U
 420   UNSPEC_VQRSHL_S
 421   UNSPEC_VQRSHL_U
 422   UNSPEC_VQSHL_S_N
 423   UNSPEC_VQSHL_U_N
 424   UNSPEC_VQSHLU_N
 425   UNSPEC_VQSHRN_S_N
 426   UNSPEC_VQSHRN_U_N
 427   UNSPEC_VQRSHRN_S_N
 428   UNSPEC_VQRSHRN_U_N
 429   UNSPEC_VQSHRUN_N
 430   UNSPEC_VQRSHRUN_N
 431   UNSPEC_VQSUB_S
 432   UNSPEC_VQSUB_U
 433   UNSPEC_VRECPE
 434   UNSPEC_VRECPS
 435   UNSPEC_VREV16
 436   UNSPEC_VREV32
 437   UNSPEC_VREV64
 438   UNSPEC_VRSQRTE
 439   UNSPEC_VRSQRTS
 440   UNSPEC_VSHL_S
 441   UNSPEC_VSHL_U
 442   UNSPEC_VRSHL_S
 443   UNSPEC_VRSHL_U
 444   UNSPEC_VSHLL_S_N
 445   UNSPEC_VSHLL_U_N
 446   UNSPEC_VSHL_N
 447   UNSPEC_VSHR_S_N
 448   UNSPEC_VSHR_U_N
 449   UNSPEC_VRSHR_S_N
 450   UNSPEC_VRSHR_U_N
 451   UNSPEC_VSHRN_N
 452   UNSPEC_VRSHRN_N
 453   UNSPEC_VSLI
 454   UNSPEC_VSRA_S_N
 455   UNSPEC_VSRA_U_N
 456   UNSPEC_VRSRA_S_N
 457   UNSPEC_VRSRA_U_N
 458   UNSPEC_VSRI
 459   UNSPEC_VST1
 460   UNSPEC_VST1_LANE
 461   UNSPEC_VST2
 462   UNSPEC_VST2_LANE
 463   UNSPEC_VST3
 464   UNSPEC_VST3A
 465   UNSPEC_VST3B
 466   UNSPEC_VST3_LANE
 467   UNSPEC_VST4
 468   UNSPEC_VST4A
 469   UNSPEC_VST4B
 470   UNSPEC_VST4_LANE
 471   UNSPEC_VSTRUCTDUMMY
 472   UNSPEC_VSUB
 473   UNSPEC_VSUBHN
 474   UNSPEC_VRSUBHN
 475   UNSPEC_VSUBL_S
 476   UNSPEC_VSUBL_U
 477   UNSPEC_VSUBW_S
 478   UNSPEC_VSUBW_U
 479   UNSPEC_VTBL
 480   UNSPEC_VTBX
 481   UNSPEC_VTRN1
 482   UNSPEC_VTRN2
 483   UNSPEC_VTST
 484   UNSPEC_VUZP1
 485   UNSPEC_VUZP2
 486   UNSPEC_VZIP1
 487   UNSPEC_VZIP2
 488   UNSPEC_MISALIGNED_ACCESS
 489   UNSPEC_VCLE
 490   UNSPEC_VCLT
 491   UNSPEC_NVRINTZ
 492   UNSPEC_NVRINTP
 493   UNSPEC_NVRINTM
 494   UNSPEC_NVRINTX
 495   UNSPEC_NVRINTA
 496   UNSPEC_NVRINTN
 497   UNSPEC_VQRDMLAH
 498   UNSPEC_VQRDMLSH
 499   UNSPEC_VRND
 500   UNSPEC_VRNDA
 501   UNSPEC_VRNDI
 502   UNSPEC_VRNDM
 503   UNSPEC_VRNDN
 504   UNSPEC_VRNDP
 505   UNSPEC_VRNDX
 506   UNSPEC_DOT_S
 507   UNSPEC_DOT_U
 508   UNSPEC_DOT_US
 509   UNSPEC_DOT_SU
 510   UNSPEC_VFML_LO
 511   UNSPEC_VFML_HI
 512   UNSPEC_VCADD90
 513   UNSPEC_VCADD270
 514   UNSPEC_VCMLA
 515   UNSPEC_VCMLA90
 516   UNSPEC_VCMLA180
 517   UNSPEC_VCMLA270
 518   UNSPEC_VCMLA_CONJ
 519   UNSPEC_VCMLA180_CONJ
 520   UNSPEC_VCMUL
 521   UNSPEC_VCMUL90
 522   UNSPEC_VCMUL180
 523   UNSPEC_VCMUL270
 524   UNSPEC_VCMUL_CONJ
 525   UNSPEC_MATMUL_S
 526   UNSPEC_MATMUL_U
 527   UNSPEC_MATMUL_US
 528   UNSPEC_BFCVT
 529   UNSPEC_BFCVT_HIGH
 530   UNSPEC_BFMMLA
 531   UNSPEC_BFMAB
 532   UNSPEC_BFMAT
 533 ])
 534
 535 ;; Enumerators for MVE unspecs.
 536 (define_c_enum "unspec" [
 537   VST4Q
 538   VRNDXQ_F
 539   VRNDQ_F
 540   VRNDPQ_F
 541   VRNDNQ_F
 542   VRNDMQ_F
 543   VRNDAQ_F
 544   VREV64Q_F
 545   VDUPQ_N_F
 546   VREV32Q_F
 547   VCVTTQ_F32_F16
 548   VCVTBQ_F32_F16
 549   VCVTQ_TO_F_S
 550   VQNEGQ_S
 551   VCVTQ_TO_F_U
 552   VREV16Q_S
 553   VREV16Q_U
 554   VADDLVQ_S
 555   VMVNQ_N_S
 556   VMVNQ_N_U
 557   VCVTAQ_S
 558   VCVTAQ_U
 559   VREV64Q_S
 560   VREV64Q_U
 561   VQABSQ_S
 562   VDUPQ_N_U
 563   VDUPQ_N_S
 564   VCLSQ_S
 565   VADDVQ_S
 566   VADDVQ_U
 567   VREV32Q_U
 568   VREV32Q_S
 569   VMOVLTQ_U
 570   VMOVLTQ_S
 571   VMOVLBQ_S
 572   VMOVLBQ_U
 573   VCVTQ_FROM_F_S
 574   VCVTQ_FROM_F_U
 575   VCVTPQ_S
 576   VCVTPQ_U
 577   VCVTNQ_S
 578   VCVTNQ_U
 579   VCVTMQ_S
 580   VCVTMQ_U
 581   VADDLVQ_U
 582   VCTP
 583   VCTP_M
 584   VPNOT
 585   VCREATEQ_F
 586   VCVTQ_N_TO_F_S
 587   VCVTQ_N_TO_F_U
 588   VBRSRQ_N_F
 589   VSUBQ_N_F
 590   VCREATEQ_U
 591   VCREATEQ_S
 592   VSHRQ_N_S
 593   VSHRQ_N_U
 594   VCVTQ_N_FROM_F_S
 595   VCVTQ_N_FROM_F_U
 596   VADDLVQ_P_S
 597   VADDLVQ_P_U
 598   VSHLQ_S
 599   VSHLQ_U
 600   VABDQ_S
 601   VADDQ_N_S
 602   VADDVAQ_S
 603   VADDVQ_P_S
 604   VBRSRQ_N_S
 605   VHADDQ_S
 606   VHADDQ_N_S
 607   VHSUBQ_S
 608   VHSUBQ_N_S
 609   VMAXQ_S
 610   VMAXVQ_S
 611   VMINQ_S
 612   VMINVQ_S
 613   VMLADAVQ_S
 614   VMULHQ_S
 615   VMULLBQ_INT_S
 616   VMULLTQ_INT_S
 617   VMULQ_S
 618   VMULQ_N_S
 619   VQADDQ_S
 620   VQADDQ_N_S
 621   VQRSHLQ_S
 622   VQRSHLQ_N_S
 623   VQSHLQ_S
 624   VQSHLQ_N_S
 625   VQSHLQ_R_S
 626   VQSUBQ_S
 627   VQSUBQ_N_S
 628   VRHADDQ_S
 629   VRMULHQ_S
 630   VRSHLQ_S
 631   VRSHLQ_N_S
 632   VRSHRQ_N_S
 633   VSHLQ_N_S
 634   VSHLQ_R_S
 635   VSUBQ_S
 636   VSUBQ_N_S
 637   VABDQ_U
 638   VADDQ_N_U
 639   VADDVAQ_U
 640   VADDVQ_P_U
 641   VBRSRQ_N_U
 642   VHADDQ_U
 643   VHADDQ_N_U
 644   VHSUBQ_U
 645   VHSUBQ_N_U
 646   VMAXQ_U
 647   VMAXVQ_U
 648   VMINQ_U
 649   VMINVQ_U
 650   VMLADAVQ_U
 651   VMULHQ_U
 652   VMULLBQ_INT_U
 653   VMULLTQ_INT_U
 654   VMULQ_U
 655   VMULQ_N_U
 656   VQADDQ_U
 657   VQADDQ_N_U
 658   VQRSHLQ_U
 659   VQRSHLQ_N_U
 660   VQSHLQ_U
 661   VQSHLQ_N_U
 662   VQSHLQ_R_U
 663   VQSUBQ_U
 664   VQSUBQ_N_U
 665   VRHADDQ_U
 666   VRMULHQ_U
 667   VRSHLQ_U
 668   VRSHLQ_N_U
 669   VRSHRQ_N_U
 670   VSHLQ_N_U
 671   VSHLQ_R_U
 672   VSUBQ_U
 673   VSUBQ_N_U
 674   VHCADDQ_ROT270_S
 675   VHCADDQ_ROT90_S
 676   VMAXAQ_S
 677   VMAXAVQ_S
 678   VMINAQ_S
 679   VMINAVQ_S
 680   VMLADAVXQ_S
 681   VMLSDAVQ_S
 682   VMLSDAVXQ_S
 683   VQDMULHQ_N_S
 684   VQDMULHQ_S
 685   VQRDMULHQ_N_S
 686   VQRDMULHQ_S
 687   VQSHLUQ_N_S
 688   VABDQ_M_S
 689   VABDQ_M_U
 690   VABDQ_F
 691   VADDQ_N_F
 692   VMAXNMAQ_F
 693   VMAXNMAVQ_F
 694   VMAXNMQ_F
 695   VMAXNMVQ_F
 696   VMINNMAQ_F
 697   VMINNMAVQ_F
 698   VMINNMQ_F
 699   VMINNMVQ_F
 700   VMULQ_F
 701   VMULQ_N_F
 702   VSUBQ_F
 703   VADDLVAQ_U
 704   VADDLVAQ_S
 705   VBICQ_N_U
 706   VBICQ_N_S
 707   VCVTBQ_F16_F32
 708   VCVTTQ_F16_F32
 709   VMLALDAVQ_U
 710   VMLALDAVXQ_U
 711   VMLALDAVXQ_S
 712   VMLALDAVQ_S
 713   VMLSLDAVQ_S
 714   VMLSLDAVXQ_S
 715   VMOVNBQ_U
 716   VMOVNBQ_S
 717   VMOVNTQ_U
 718   VMOVNTQ_S
 719   VORRQ_N_S
 720   VORRQ_N_U
 721   VQDMULLBQ_N_S
 722   VQDMULLBQ_S
 723   VQDMULLTQ_N_S
 724   VQDMULLTQ_S
 725   VQMOVNBQ_U
 726   VQMOVNBQ_S
 727   VQMOVUNBQ_S
 728   VQMOVUNTQ_S
 729   VRMLALDAVHXQ_S
 730   VRMLSLDAVHQ_S
 731   VRMLSLDAVHXQ_S
 732   VSHLLBQ_S
 733   VSHLLBQ_U
 734   VSHLLTQ_U
 735   VSHLLTQ_S
 736   VQMOVNTQ_U
 737   VQMOVNTQ_S
 738   VSHLLBQ_N_S
 739   VSHLLBQ_N_U
 740   VSHLLTQ_N_U
 741   VSHLLTQ_N_S
 742   VRMLALDAVHQ_U
 743   VRMLALDAVHQ_S
 744   VMULLTQ_POLY_P
 745   VMULLBQ_POLY_P
 746   VBICQ_M_N_S
 747   VBICQ_M_N_U
 748   VCMPEQQ_M_F
 749   VCVTAQ_M_S
 750   VCVTAQ_M_U
 751   VCVTQ_M_TO_F_S
 752   VCVTQ_M_TO_F_U
 753   VQRSHRNBQ_N_U
 754   VQRSHRNBQ_N_S
 755   VQRSHRUNBQ_N_S
 756   VRMLALDAVHAQ_S
 757   VABAVQ_S
 758   VABAVQ_U
 759   VSHLCQ_S
 760   VSHLCQ_U
 761   VRMLALDAVHAQ_U
 762   VABSQ_M_S
 763   VADDVAQ_P_S
 764   VADDVAQ_P_U
 765   VCLSQ_M_S
 766   VCLZQ_M_S
 767   VCLZQ_M_U
 768   VCMPCSQ_M_N_U
 769   VCMPCSQ_M_U
 770   VCMPEQQ_M_N_S
 771   VCMPEQQ_M_N_U
 772   VCMPEQQ_M_S
 773   VCMPEQQ_M_U
 774   VCMPGEQ_M_N_S
 775   VCMPGEQ_M_S
 776   VCMPGTQ_M_N_S
 777   VCMPGTQ_M_S
 778   VCMPHIQ_M_N_U
 779   VCMPHIQ_M_U
 780   VCMPLEQ_M_N_S
 781   VCMPLEQ_M_S
 782   VCMPLTQ_M_N_S
 783   VCMPLTQ_M_S
 784   VCMPNEQ_M_N_S
 785   VCMPNEQ_M_N_U
 786   VCMPNEQ_M_S
 787   VCMPNEQ_M_U
 788   VDUPQ_M_N_S
 789   VDUPQ_M_N_U
 790   VDWDUPQ_N_U
 791   VDWDUPQ_WB_U
 792   VIWDUPQ_N_U
 793   VIWDUPQ_WB_U
 794   VMAXAQ_M_S
 795   VMAXAVQ_P_S
 796   VMAXVQ_P_S
 797   VMAXVQ_P_U
 798   VMINAQ_M_S
 799   VMINAVQ_P_S
 800   VMINVQ_P_S
 801   VMINVQ_P_U
 802   VMLADAVAQ_S
 803   VMLADAVAQ_U
 804   VMLADAVQ_P_S
 805   VMLADAVQ_P_U
 806   VMLADAVXQ_P_S
 807   VMLAQ_N_S
 808   VMLAQ_N_U
 809   VMLASQ_N_S
 810   VMLASQ_N_U
 811   VMLSDAVQ_P_S
 812   VMLSDAVXQ_P_S
 813   VMVNQ_M_S
 814   VMVNQ_M_U
 815   VNEGQ_M_S
 816   VPSELQ_S
 817   VPSELQ_U
 818   VQABSQ_M_S
 819   VQDMLAHQ_N_S
 820   VQDMLASHQ_N_S
 821   VQNEGQ_M_S
 822   VQRDMLADHQ_S
 823   VQRDMLADHXQ_S
 824   VQRDMLAHQ_N_S
 825   VQRDMLASHQ_N_S
 826   VQRDMLSDHQ_S
 827   VQRDMLSDHXQ_S
 828   VQRSHLQ_M_N_S
 829   VQRSHLQ_M_N_U
 830   VQSHLQ_M_R_S
 831   VQSHLQ_M_R_U
 832   VREV64Q_M_S
 833   VREV64Q_M_U
 834   VRSHLQ_M_N_S
 835   VRSHLQ_M_N_U
 836   VSHLQ_M_R_S
 837   VSHLQ_M_R_U
 838   VSLIQ_N_S
 839   VSLIQ_N_U
 840   VSRIQ_N_S
 841   VSRIQ_N_U
 842   VQDMLSDHXQ_S
 843   VQDMLSDHQ_S
 844   VQDMLADHXQ_S
 845   VQDMLADHQ_S
 846   VMLSDAVAXQ_S
 847   VMLSDAVAQ_S
 848   VMLADAVAXQ_S
 849   VCMPGEQ_M_F
 850   VCMPGTQ_M_N_F
 851   VMLSLDAVQ_P_S
 852   VRMLALDAVHAXQ_S
 853   VMLSLDAVXQ_P_S
 854   VFMAQ_F
 855   VMLSLDAVAQ_S
 856   VQSHRUNBQ_N_S
 857   VQRSHRUNTQ_N_S
 858   VMINNMAQ_M_F
 859   VFMASQ_N_F
 860   VDUPQ_M_N_F
 861   VCMPGTQ_M_F
 862   VCMPLTQ_M_F
 863   VRMLSLDAVHQ_P_S
 864   VQSHRUNTQ_N_S
 865   VABSQ_M_F
 866   VMAXNMAVQ_P_F
 867   VFMAQ_N_F
 868   VRMLSLDAVHXQ_P_S
 869   VREV32Q_M_F
 870   VRMLSLDAVHAQ_S
 871   VRMLSLDAVHAXQ_S
 872   VCMPLTQ_M_N_F
 873   VCMPNEQ_M_F
 874   VRNDAQ_M_F
 875   VRNDPQ_M_F
 876   VADDLVAQ_P_S
 877   VQMOVUNBQ_M_S
 878   VCMPLEQ_M_F
 879   VMLSLDAVAXQ_S
 880   VRNDXQ_M_F
 881   VFMSQ_F
 882   VMINNMVQ_P_F
 883   VMAXNMVQ_P_F
 884   VPSELQ_F
 885   VQMOVUNTQ_M_S
 886   VREV64Q_M_F
 887   VNEGQ_M_F
 888   VRNDMQ_M_F
 889   VCMPLEQ_M_N_F
 890   VCMPGEQ_M_N_F
 891   VRNDNQ_M_F
 892   VMINNMAVQ_P_F
 893   VCMPNEQ_M_N_F
 894   VRMLALDAVHQ_P_S
 895   VRMLALDAVHXQ_P_S
 896   VCMPEQQ_M_N_F
 897   VMAXNMAQ_M_F
 898   VRNDQ_M_F
 899   VMLALDAVQ_P_U
 900   VMLALDAVQ_P_S
 901   VQMOVNBQ_M_S
 902   VQMOVNBQ_M_U
 903   VMOVLTQ_M_U
 904   VMOVLTQ_M_S
 905   VMOVNBQ_M_U
 906   VMOVNBQ_M_S
 907   VRSHRNTQ_N_U
 908   VRSHRNTQ_N_S
 909   VORRQ_M_N_S
 910   VORRQ_M_N_U
 911   VREV32Q_M_S
 912   VREV32Q_M_U
 913   VQRSHRNTQ_N_U
 914   VQRSHRNTQ_N_S
 915   VMOVNTQ_M_U
 916   VMOVNTQ_M_S
 917   VMOVLBQ_M_U
 918   VMOVLBQ_M_S
 919   VMLALDAVAQ_S
 920   VMLALDAVAQ_U
 921   VQSHRNBQ_N_U
 922   VQSHRNBQ_N_S
 923   VSHRNBQ_N_U
 924   VSHRNBQ_N_S
 925   VRSHRNBQ_N_S
 926   VRSHRNBQ_N_U
 927   VMLALDAVXQ_P_U
 928   VMLALDAVXQ_P_S
 929   VQMOVNTQ_M_U
 930   VQMOVNTQ_M_S
 931   VMVNQ_M_N_U
 932   VMVNQ_M_N_S
 933   VQSHRNTQ_N_U
 934   VQSHRNTQ_N_S
 935   VMLALDAVAXQ_S
 936   VMLALDAVAXQ_U
 937   VSHRNTQ_N_S
 938   VSHRNTQ_N_U
 939   VCVTBQ_M_F16_F32
 940   VCVTBQ_M_F32_F16
 941   VCVTTQ_M_F16_F32
 942   VCVTTQ_M_F32_F16
 943   VCVTMQ_M_S
 944   VCVTMQ_M_U
 945   VCVTNQ_M_S
 946   VCVTPQ_M_S
 947   VCVTPQ_M_U
 948   VCVTQ_M_N_FROM_F_S
 949   VCVTNQ_M_U
 950   VREV16Q_M_S
 951   VREV16Q_M_U
 952   VREV32Q_M
 953   VCVTQ_M_FROM_F_U
 954   VCVTQ_M_FROM_F_S
 955   VRMLALDAVHQ_P_U
 956   VADDLVAQ_P_U
 957   VCVTQ_M_N_FROM_F_U
 958   VQSHLUQ_M_N_S
 959   VABAVQ_P_S
 960   VABAVQ_P_U
 961   VSHLQ_M_S
 962   VSHLQ_M_U
 963   VSRIQ_M_N_S
 964   VSRIQ_M_N_U
 965   VSUBQ_M_U
 966   VSUBQ_M_S
 967   VCVTQ_M_N_TO_F_U
 968   VCVTQ_M_N_TO_F_S
 969   VQADDQ_M_U
 970   VQADDQ_M_S
 971   VRSHRQ_M_N_S
 972   VSUBQ_M_N_S
 973   VSUBQ_M_N_U
 974   VBRSRQ_M_N_S
 975   VSUBQ_M_N_F
 976   VBICQ_M_F
 977   VHADDQ_M_U
 978   VBICQ_M_U
 979   VBICQ_M_S
 980   VMULQ_M_N_U
 981   VHADDQ_M_S
 982   VORNQ_M_F
 983   VMLAQ_M_N_S
 984   VQSUBQ_M_U
 985   VQSUBQ_M_S
 986   VMLAQ_M_N_U
 987   VQSUBQ_M_N_U
 988   VQSUBQ_M_N_S
 989   VMULLTQ_INT_M_S
 990   VMULLTQ_INT_M_U
 991   VMULQ_M_N_S
 992   VMULQ_M_N_F
 993   VMLASQ_M_N_U
 994   VMLASQ_M_N_S
 995   VMAXQ_M_U
 996   VQRDMLAHQ_M_N_U
 997   VCADDQ_ROT270_M_F
 998   VCADDQ_ROT270_M_U
 999   VCADDQ_ROT270_M_S
1000   VQRSHLQ_M_S
1001   VMULQ_M_F
1002   VRHADDQ_M_U
1003   VSHRQ_M_N_U
1004   VRHADDQ_M_S
1005   VMULQ_M_S
1006   VMULQ_M_U
1007   VQDMLASHQ_M_N_S
1008   VQRDMLASHQ_M_N_S
1009   VRSHLQ_M_S
1010   VRSHLQ_M_U
1011   VRSHRQ_M_N_U
1012   VADDQ_M_N_F
1013   VADDQ_M_N_S
1014   VADDQ_M_N_U
1015   VQRDMLASHQ_M_N_U
1016   VMAXQ_M_S
1017   VQRDMLAHQ_M_N_S
1018   VORRQ_M_S
1019   VORRQ_M_U
1020   VORRQ_M_F
1021   VQRSHLQ_M_U
1022   VRMULHQ_M_U
1023   VRMULHQ_M_S
1024   VMINQ_M_S
1025   VMINQ_M_U
1026   VANDQ_M_F
1027   VANDQ_M_U
1028   VANDQ_M_S
1029   VHSUBQ_M_N_S
1030   VHSUBQ_M_N_U
1031   VMULHQ_M_S
1032   VMULHQ_M_U
1033   VMULLBQ_INT_M_U
1034   VMULLBQ_INT_M_S
1035   VCADDQ_ROT90_M_F
1036   VSHRQ_M_N_S
1037   VADDQ_M_U
1038   VSLIQ_M_N_U
1039   VQADDQ_M_N_S
1040   VBRSRQ_M_N_F
1041   VABDQ_M_F
1042   VBRSRQ_M_N_U
1043   VEORQ_M_F
1044   VSHLQ_M_N_S
1045   VQDMLAHQ_M_N_U
1046   VQDMLAHQ_M_N_S
1047   VSHLQ_M_N_U
1048   VMLADAVAQ_P_U
1049   VMLADAVAQ_P_S
1050   VSLIQ_M_N_S
1051   VQSHLQ_M_U
1052   VQSHLQ_M_S
1053   VCADDQ_ROT90_M_U
1054   VCADDQ_ROT90_M_S
1055   VORNQ_M_U
1056   VORNQ_M_S
1057   VQSHLQ_M_N_S
1058   VQSHLQ_M_N_U
1059   VADDQ_M_S
1060   VHADDQ_M_N_S
1061   VADDQ_M_F
1062   VQADDQ_M_N_U
1063   VEORQ_M_S
1064   VEORQ_M_U
1065   VHSUBQ_M_S
1066   VHSUBQ_M_U
1067   VHADDQ_M_N_U
1068   VHCADDQ_ROT90_M_S
1069   VQRDMLSDHQ_M_S
1070   VQRDMLSDHXQ_M_S
1071   VQRDMLADHXQ_M_S
1072   VQDMULHQ_M_S
1073   VMLADAVAXQ_P_S
1074   VQDMLADHXQ_M_S
1075   VQRDMULHQ_M_S
1076   VMLSDAVAXQ_P_S
1077   VQDMULHQ_M_N_S
1078   VHCADDQ_ROT270_M_S
1079   VQDMLSDHQ_M_S
1080   VQDMLSDHXQ_M_S
1081   VMLSDAVAQ_P_S
1082   VQRDMLADHQ_M_S
1083   VQDMLADHQ_M_S
1084   VMLALDAVAQ_P_U
1085   VMLALDAVAQ_P_S
1086   VQRSHRNBQ_M_N_U
1087   VQRSHRNBQ_M_N_S
1088   VQRSHRNTQ_M_N_S
1089   VQSHRNBQ_M_N_U
1090   VQSHRNBQ_M_N_S
1091   VQSHRNTQ_M_N_S
1092   VRSHRNBQ_M_N_U
1093   VRSHRNBQ_M_N_S
1094   VRSHRNTQ_M_N_U
1095   VSHLLBQ_M_N_U
1096   VSHLLBQ_M_N_S
1097   VSHLLTQ_M_N_U
1098   VSHLLTQ_M_N_S
1099   VSHRNBQ_M_N_S
1100   VSHRNBQ_M_N_U
1101   VSHRNTQ_M_N_S
1102   VSHRNTQ_M_N_U
1103   VMLALDAVAXQ_P_S
1104   VQRSHRNTQ_M_N_U
1105   VQSHRNTQ_M_N_U
1106   VRSHRNTQ_M_N_S
1107   VQRDMULHQ_M_N_S
1108   VRMLALDAVHAQ_P_S
1109   VMLSLDAVAQ_P_S
1110   VMLSLDAVAXQ_P_S
1111   VMULLBQ_POLY_M_P
1112   VMULLTQ_POLY_M_P
1113   VQDMULLBQ_M_N_S
1114   VQDMULLBQ_M_S
1115   VQDMULLTQ_M_N_S
1116   VQDMULLTQ_M_S
1117   VQRSHRUNBQ_M_N_S
1118   VQSHRUNBQ_M_N_S
1119   VQSHRUNTQ_M_N_S
1120   VRMLALDAVHAQ_P_U
1121   VRMLALDAVHAXQ_P_S
1122   VRMLSLDAVHAQ_P_S
1123   VRMLSLDAVHAXQ_P_S
1124   VQRSHRUNTQ_M_N_S
1125   VCMLAQ_M_F
1126   VCMLAQ_ROT180_M_F
1127   VCMLAQ_ROT270_M_F
1128   VCMLAQ_ROT90_M_F
1129   VCMULQ_M_F
1130   VCMULQ_ROT180_M_F
1131   VCMULQ_ROT270_M_F
1132   VCMULQ_ROT90_M_F
1133   VFMAQ_M_F
1134   VFMAQ_M_N_F
1135   VFMASQ_M_N_F
1136   VFMSQ_M_F
1137   VMAXNMQ_M_F
1138   VMINNMQ_M_F
1139   VSUBQ_M_F
1140   VSTRWQSB_S
1141   VSTRWQSB_U
1142   VSTRBQSO_S
1143   VSTRBQSO_U
1144   VSTRBQ_S
1145   VSTRBQ_U
1146   VLDRBQGO_S
1147   VLDRBQGO_U
1148   VLDRBQ_S
1149   VLDRBQ_U
1150   VLDRWQGB_S
1151   VLDRWQGB_U
1152   VLD1Q_F
1153   VLD1Q_S
1154   VLD1Q_U
1155   VLDRHQ_F
1156   VLDRHQGO_S
1157   VLDRHQGO_U
1158   VLDRHQGSO_S
1159   VLDRHQGSO_U
1160   VLDRHQ_S
1161   VLDRHQ_U
1162   VLDRWQ_F
1163   VLDRWQ_S
1164   VLDRWQ_U
1165   VLDRDQGB_S
1166   VLDRDQGB_U
1167   VLDRDQGO_S
1168   VLDRDQGO_U
1169   VLDRDQGSO_S
1170   VLDRDQGSO_U
1171   VLDRHQGO_F
1172   VLDRHQGSO_F
1173   VLDRWQGB_F
1174   VLDRWQGO_F
1175   VLDRWQGO_S
1176   VLDRWQGO_U
1177   VLDRWQGSO_F
1178   VLDRWQGSO_S
1179   VLDRWQGSO_U
1180   VSTRHQ_F
1181   VST1Q_S
1182   VST1Q_U
1183   VSTRHQSO_S
1184   VSTRHQ_U
1185   VSTRWQ_S
1186   VSTRWQ_U
1187   VSTRWQ_F
1188   VST1Q_F
1189   VSTRDQSB_S
1190   VSTRDQSB_U
1191   VSTRDQSO_S
1192   VSTRDQSO_U
1193   VSTRDQSSO_S
1194   VSTRDQSSO_U
1195   VSTRWQSO_S
1196   VSTRWQSO_U
1197   VSTRWQSSO_S
1198   VSTRWQSSO_U
1199   VSTRHQSO_F
1200   VSTRHQSSO_F
1201   VSTRWQSB_F
1202   VSTRWQSO_F
1203   VSTRWQSSO_F
1204   VDDUPQ
1205   VDDUPQ_M
1206   VDWDUPQ
1207   VDWDUPQ_M
1208   VIDUPQ
1209   VIDUPQ_M
1210   VIWDUPQ
1211   VIWDUPQ_M
1212   VSTRWQSBWB_S
1213   VSTRWQSBWB_U
1214   VLDRWQGBWB_S
1215   VLDRWQGBWB_U
1216   VSTRWQSBWB_F
1217   VLDRWQGBWB_F
1218   VSTRDQSBWB_S
1219   VSTRDQSBWB_U
1220   VLDRDQGBWB_S
1221   VLDRDQGBWB_U
1222   VADCQ_U
1223   VADCQ_M_U
1224   VADCQ_S
1225   VADCQ_M_S
1226   VSBCIQ_U
1227   VSBCIQ_S
1228   VSBCIQ_M_U
1229   VSBCIQ_M_S
1230   VSBCQ_U
1231   VSBCQ_S
1232   VSBCQ_M_U
1233   VSBCQ_M_S
1234   VADCIQ_U
1235   VADCIQ_M_U
1236   VADCIQ_S
1237   VADCIQ_M_S
1238   VLD2Q
1239   VLD4Q
1240   VST2Q
1241   VSHLCQ_M_U
1242   VSHLCQ_M_S
1243   VSTRHQSO_U
1244   VSTRHQSSO_S
1245   VSTRHQSSO_U
1246   VSTRHQ_S
1247   SRSHRL
1248   SRSHR
1249   URSHR
1250   URSHRL
1251   SQRSHR
1252   UQRSHL
1253   UQRSHLL_64
1254   UQRSHLL_48
1255   SQRSHRL_64
1256   SQRSHRL_48
1257   VSHLCQ_M_
1258 ])