libstdc++: Improve comment for _Hashtable::_M_insert_unique_node
[official-gcc.git] / gcc / config / arm / unspecs.md
blob01963d54cd4dbe719622d10e5ce69ee5c02b789f
1 ;; Unspec defintions.
2 ;; Copyright (C) 2012-2024 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3.  If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; UNSPEC Usage:
22 ;; Note: sin and cos are no-longer used.
23 ;; Unspec enumerators for Neon are defined in neon.md.
24 ;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
26 (define_c_enum "unspec" [
27   UNSPEC_PUSH_MULT      ; `push multiple' operation:
28                         ;   operand 0 is the first register,
29                         ;   subsequent registers are in parallel (use ...)
30                         ;   expressions.
31   UNSPEC_PIC_SYM        ; A symbol that has been treated properly for pic
32                         ; usage, that is, we will add the pic_register
33                         ; value to it before trying to dereference it.
34   UNSPEC_PIC_BASE       ; Add PC and all but the last operand together,
35                         ; The last operand is the number of a PIC_LABEL
36                         ; that points at the containing instruction.
37   UNSPEC_PRLG_STK       ; A special barrier that prevents frame accesses
38                         ; being scheduled before the stack adjustment insn.
39   UNSPEC_REGISTER_USE   ; As USE insns are not meaningful after reload,
40                         ; this unspec is used to prevent the deletion of
41                         ; instructions setting registers for EH handling
42                         ; and stack frame generation.  Operand 0 is the
43                         ; register to "use".
44   UNSPEC_CHECK_ARCH     ; Set CCs to indicate 26-bit or 32-bit mode.
45   UNSPEC_WSHUFH         ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
46   UNSPEC_WACC           ; Used by the intrinsic form of the iWMMXt WACC instruction.
47   UNSPEC_TMOVMSK        ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
48   UNSPEC_WSAD           ; Used by the intrinsic form of the iWMMXt WSAD instruction.
49   UNSPEC_WSADZ          ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
50   UNSPEC_WMACS          ; Used by the intrinsic form of the iWMMXt WMACS instruction.
51   UNSPEC_WMACU          ; Used by the intrinsic form of the iWMMXt WMACU instruction.
52   UNSPEC_WMACSZ         ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
53   UNSPEC_WMACUZ         ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
54   UNSPEC_CLRDI          ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
55   UNSPEC_WALIGNI        ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
56   UNSPEC_TLS            ; A symbol that has been treated properly for TLS usage.
57   UNSPEC_PIC_LABEL      ; A label used for PIC access that does not appear in the
58                         ; instruction stream.
59   UNSPEC_PIC_OFFSET     ; A symbolic 12-bit OFFSET that has been treated
60                         ; correctly for PIC usage.
61   UNSPEC_GOTSYM_OFF     ; The offset of the start of the GOT from a
62                         ; a given symbolic address.
63   UNSPEC_THUMB1_CASESI  ; A Thumb1 compressed dispatch-table call.
64   UNSPEC_RBIT           ; rbit operation.
65   UNSPEC_SYMBOL_OFFSET  ; The offset of the start of the symbol from
66                         ; another symbolic address.
67   UNSPEC_MEMORY_BARRIER ; Represent a memory barrier.
68   UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access
69                         ; unaligned locations, on architectures which support
70                         ; that.
71   UNSPEC_UNALIGNED_STORE ; Same for str/strh.
72   UNSPEC_PIC_UNIFIED    ; Create a common pic addressing form.
73   UNSPEC_Q_SET          ; Represent setting the Q bit.
74   UNSPEC_GE_SET         ; Represent setting the GE bits.
75   UNSPEC_APSR_READ      ; Represent reading the APSR.
77   UNSPEC_LL             ; Represent an unpaired load-register-exclusive.
78   UNSPEC_VRINTZ         ; Represent a float to integral float rounding
79                         ; towards zero.
80   UNSPEC_VRINTP         ; Represent a float to integral float rounding
81                         ; towards +Inf.
82   UNSPEC_VRINTM         ; Represent a float to integral float rounding
83                         ; towards -Inf.
84   UNSPEC_VRINTR         ; Represent a float to integral float rounding
85                         ; FPSCR rounding mode.
86   UNSPEC_VRINTX         ; Represent a float to integral float rounding
87                         ; FPSCR rounding mode and signal inexactness.
88   UNSPEC_VRINTA         ; Represent a float to integral float rounding
89                         ; towards nearest, ties away from zero.
90   UNSPEC_PROBE_STACK    ; Probe stack memory reference
91   UNSPEC_NONSECURE_MEM  ; Represent non-secure memory in ARMv8-M with
92                         ; security extension
93   UNSPEC_SP_SET         ; Represent the setting of stack protector's canary
94   UNSPEC_SP_TEST        ; Represent the testing of stack protector's canary
95                         ; against the guard.
96   UNSPEC_PIC_RESTORE    ; Use to restore fdpic register
98   UNSPEC_SXTAB16        ; Represent the SXTAB16 operation.
99   UNSPEC_UXTAB16        ; Represent the UXTAB16 operation.
100   UNSPEC_SXTB16         ; Represent the SXTB16 operation.
101   UNSPEC_UXTB16         ; Represent the UXTB16 operation.
102   UNSPEC_QADD8          ; Represent the QADD8 operation.
103   UNSPEC_QSUB8          ; Represent the QSUB8 operation.
104   UNSPEC_SHADD8         ; Represent the SHADD8 operation.
105   UNSPEC_SHSUB8         ; Represent the SHSUB8 operation.
106   UNSPEC_UHADD8         ; Represent the UHADD8 operation.
107   UNSPEC_UHSUB8         ; Represent the UHSUB8 operation.
108   UNSPEC_UQADD8         ; Represent the UQADD8 operation.
109   UNSPEC_UQSUB8         ; Represent the UQSUB8 operation.
110   UNSPEC_QADD16         ; Represent the QADD16 operation.
111   UNSPEC_QASX           ; Represent the QASX operation.
112   UNSPEC_QSAX           ; Represent the QSAX operation.
113   UNSPEC_QSUB16         ; Represent the QSUB16 operation.
114   UNSPEC_SHADD16        ; Represent the SHADD16 operation.
115   UNSPEC_SHASX          ; Represent the SHASX operation.
116   UNSPEC_SHSAX          ; Represent the SSAX operation.
117   UNSPEC_SHSUB16        ; Represent the SHSUB16 operation.
118   UNSPEC_UHADD16        ; Represent the UHADD16 operation.
119   UNSPEC_UHASX          ; Represent the UHASX operation.
120   UNSPEC_UHSAX          ; Represent the USAX operation.
121   UNSPEC_UHSUB16        ; Represent the UHSUB16 operation.
122   UNSPEC_UQADD16        ; Represent the UQADD16 operation.
123   UNSPEC_UQASX          ; Represent the UQASX operation.
124   UNSPEC_UQSAX          ; Represent the UQSAX operation.
125   UNSPEC_UQSUB16        ; Represent the UQSUB16 operation.
126   UNSPEC_SMUSD          ; Represent the SMUSD operation.
127   UNSPEC_SMUSDX         ; Represent the SMUSDX operation.
128   UNSPEC_USAD8          ; Represent the USAD8 operation.
129   UNSPEC_USADA8         ; Represent the USADA8 operation.
130   UNSPEC_SMLALD         ; Represent the SMLALD operation.
131   UNSPEC_SMLALDX        ; Represent the SMLALDX operation.
132   UNSPEC_SMLSLD         ; Represent the SMLSLD operation.
133   UNSPEC_SMLSLDX        ; Represent the SMLSLDX operation.
134   UNSPEC_SMLAWB         ; Represent the SMLAWB operation.
135   UNSPEC_SMLAWT         ; Represent the SMLAWT operation.
136   UNSPEC_SEL            ; Represent the SEL operation.
137   UNSPEC_SADD8          ; Represent the SADD8 operation.
138   UNSPEC_SSUB8          ; Represent the SSUB8 operation.
139   UNSPEC_UADD8          ; Represent the UADD8 operation.
140   UNSPEC_USUB8          ; Represent the USUB8 operation.
141   UNSPEC_SADD16         ; Represent the SADD16 operation.
142   UNSPEC_SASX           ; Represent the SASX operation.
143   UNSPEC_SSAX           ; Represent the SSAX operation.
144   UNSPEC_SSUB16         ; Represent the SSUB16 operation.
145   UNSPEC_UADD16         ; Represent the UADD16 operation.
146   UNSPEC_UASX           ; Represent the UASX operation.
147   UNSPEC_USAX           ; Represent the USAX operation.
148   UNSPEC_USUB16         ; Represent the USUB16 operation.
149   UNSPEC_SMLAD          ; Represent the SMLAD operation.
150   UNSPEC_SMLADX         ; Represent the SMLADX operation.
151   UNSPEC_SMLSD          ; Represent the SMLSD operation.
152   UNSPEC_SMLSDX         ; Represent the SMLSDX operation.
153   UNSPEC_SMUAD          ; Represent the SMUAD operation.
154   UNSPEC_SMUADX         ; Represent the SMUADX operation.
155   UNSPEC_SSAT16         ; Represent the SSAT16 operation.
156   UNSPEC_USAT16         ; Represent the USAT16 operation.
157   UNSPEC_CDE            ; Custom Datapath Extension instruction.
158   UNSPEC_CDEA           ; Custom Datapath Extension instruction.
159   UNSPEC_VCDE           ; Custom Datapath Extension instruction.
160   UNSPEC_VCDEA          ; Custom Datapath Extension instruction.
161   UNSPEC_DLS            ; Used for DLS (Do Loop Start), Armv8.1-M Mainline instruction
162   UNSPEC_PAC_NOP        ; Represents PAC signing LR
166 (define_c_enum "unspec" [
167   UNSPEC_WADDC          ; Used by the intrinsic form of the iWMMXt WADDC instruction.
168   UNSPEC_WABS           ; Used by the intrinsic form of the iWMMXt WABS instruction.
169   UNSPEC_WQMULWMR       ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
170   UNSPEC_WQMULMR        ; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
171   UNSPEC_WQMULWM        ; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
172   UNSPEC_WQMULM         ; Used by the intrinsic form of the iWMMXt WQMULM instruction.
173   UNSPEC_WQMIAxyn       ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
174   UNSPEC_WQMIAxy        ; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
175   UNSPEC_TANDC          ; Used by the intrinsic form of the iWMMXt TANDC instruction.
176   UNSPEC_TORC           ; Used by the intrinsic form of the iWMMXt TORC instruction.
177   UNSPEC_TORVSC         ; Used by the intrinsic form of the iWMMXt TORVSC instruction.
178   UNSPEC_TEXTRC         ; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
179   UNSPEC_GET_FPSCR_NZCVQC       ; Represent fetch of FPSCR_nzcvqc content.
183 ;; UNSPEC_VOLATILE Usage:
185 (define_c_enum "unspecv" [
186   VUNSPEC_BLOCKAGE      ; `blockage' insn to prevent scheduling across an
187                         ;   insn in the code.
188   VUNSPEC_EPILOGUE      ; `epilogue' insn, used to represent any part of the
189                         ;   instruction epilogue sequence that isn't expanded
190                         ;   into normal RTL.  Used for both normal and sibcall
191                         ;   epilogues.
192   VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap
193                         ;   modes from arm to thumb.
194   VUNSPEC_ALIGN         ; `align' insn.  Used at the head of a minipool table
195                         ;   for inlined constants.
196   VUNSPEC_POOL_END      ; `end-of-table'.  Used to mark the end of a minipool
197                         ;   table.
198   VUNSPEC_POOL_1        ; `pool-entry(1)'.  An entry in the constant pool for
199                         ;   an 8-bit object.
200   VUNSPEC_POOL_2        ; `pool-entry(2)'.  An entry in the constant pool for
201                         ;   a 16-bit object.
202   VUNSPEC_POOL_4        ; `pool-entry(4)'.  An entry in the constant pool for
203                         ;   a 32-bit object.
204   VUNSPEC_POOL_8        ; `pool-entry(8)'.  An entry in the constant pool for
205                         ;   a 64-bit object.
206   VUNSPEC_POOL_16       ; `pool-entry(16)'.  An entry in the constant pool for
207                         ;   a 128-bit object.
208   VUNSPEC_TMRC          ; Used by the iWMMXt TMRC instruction.
209   VUNSPEC_TMCR          ; Used by the iWMMXt TMCR instruction.
210   VUNSPEC_ALIGN8        ; 8-byte alignment version of VUNSPEC_ALIGN
211   VUNSPEC_WCMP_EQ       ; Used by the iWMMXt WCMPEQ instructions
212   VUNSPEC_WCMP_GTU      ; Used by the iWMMXt WCMPGTU instructions
213   VUNSPEC_WCMP_GT       ; Used by the iwMMXT WCMPGT instructions
214   VUNSPEC_EH_RETURN     ; Use to override the return address for exception
215                         ; handling.
216   VUNSPEC_ATOMIC_CAS    ; Represent an atomic compare swap.
217   VUNSPEC_ATOMIC_XCHG   ; Represent an atomic exchange.
218   VUNSPEC_ATOMIC_OP     ; Represent an atomic operation.
219   VUNSPEC_LL            ; Represent a load-register-exclusive.
220   VUNSPEC_LDRD_ATOMIC   ; Represent an LDRD used as an atomic DImode load.
221   VUNSPEC_SC            ; Represent a store-register-exclusive.
222   VUNSPEC_LAX           ; Represent a load-register-acquire-exclusive.
223   VUNSPEC_SLX           ; Represent a store-register-release-exclusive.
224   VUNSPEC_LDA           ; Represent a load-register-acquire.
225   VUNSPEC_LDR           ; Represent a load-register-relaxed.
226   VUNSPEC_STL           ; Represent a store-register-release.
227   VUNSPEC_STR           ; Represent a store-register-relaxed.
228   VUNSPEC_GET_FPSCR     ; Represent fetch of FPSCR content.
229   VUNSPEC_SET_FPSCR     ; Represent assign of FPSCR content.
230   VUNSPEC_SET_FPSCR_NZCVQC      ; Represent assign of FPSCR_nzcvqc content.
231   VUNSPEC_PROBE_STACK_RANGE ; Represent stack range probing.
232   VUNSPEC_CDP           ; Represent the coprocessor cdp instruction.
233   VUNSPEC_CDP2          ; Represent the coprocessor cdp2 instruction.
234   VUNSPEC_LDC           ; Represent the coprocessor ldc instruction.
235   VUNSPEC_LDC2          ; Represent the coprocessor ldc2 instruction.
236   VUNSPEC_LDCL          ; Represent the coprocessor ldcl instruction.
237   VUNSPEC_LDC2L         ; Represent the coprocessor ldc2l instruction.
238   VUNSPEC_STC           ; Represent the coprocessor stc instruction.
239   VUNSPEC_STC2          ; Represent the coprocessor stc2 instruction.
240   VUNSPEC_STCL          ; Represent the coprocessor stcl instruction.
241   VUNSPEC_STC2L         ; Represent the coprocessor stc2l instruction.
242   VUNSPEC_MCR           ; Represent the coprocessor mcr instruction.
243   VUNSPEC_MCR2          ; Represent the coprocessor mcr2 instruction.
244   VUNSPEC_MRC           ; Represent the coprocessor mrc instruction.
245   VUNSPEC_MRC2          ; Represent the coprocessor mrc2 instruction.
246   VUNSPEC_MCRR          ; Represent the coprocessor mcrr instruction.
247   VUNSPEC_MCRR2         ; Represent the coprocessor mcrr2 instruction.
248   VUNSPEC_MRRC          ; Represent the coprocessor mrrc instruction.
249   VUNSPEC_MRRC2         ; Represent the coprocessor mrrc2 instruction.
250   VUNSPEC_SPECULATION_BARRIER ; Represents an unconditional speculation barrier.
251   VUNSPEC_APSR_WRITE     ; Represent writing the APSR.
252   VUNSPEC_VSTR_VLDR     ; Represent the vstr/vldr instruction.
253   VUNSPEC_CLRM_APSR     ; Represent the clearing of APSR with clrm instruction.
254   VUNSPEC_VSCCLRM_VPR   ; Represent the clearing of VPR with vscclrm
255                         ; instruction.
256   VUNSPEC_VLSTM         ; Represent the lazy store multiple with vlstm
257                         ; instruction.
258   VUNSPEC_VLLDM         ; Represent the lazy load multiple with vlldm
259                         ; instruction.
260   VUNSPEC_PACBTI_NOP    ; Represents PAC signing LR + valid landing pad
261   VUNSPEC_AUT_NOP       ; Represents PAC verifying LR
262   VUNSPEC_BTI_NOP       ; Represent BTI
265 ;; Enumerators for NEON unspecs.
266 (define_c_enum "unspec" [
267   UNSPEC_ASHIFT_SIGNED
268   UNSPEC_ASHIFT_UNSIGNED
269   UNSPEC_CRC32B
270   UNSPEC_CRC32H
271   UNSPEC_CRC32W
272   UNSPEC_CRC32CB
273   UNSPEC_CRC32CH
274   UNSPEC_CRC32CW
275   UNSPEC_AESD
276   UNSPEC_AESE
277   UNSPEC_AESIMC
278   UNSPEC_AESMC
279   UNSPEC_AES_PROTECT
280   UNSPEC_SHA1C
281   UNSPEC_SHA1M
282   UNSPEC_SHA1P
283   UNSPEC_SHA1H
284   UNSPEC_SHA1SU0
285   UNSPEC_SHA1SU1
286   UNSPEC_SHA256H
287   UNSPEC_SHA256H2
288   UNSPEC_SHA256SU0
289   UNSPEC_SHA256SU1
290   UNSPEC_VMULLP64
291   UNSPEC_LOAD_COUNT
292   UNSPEC_VABAL_S
293   UNSPEC_VABAL_U
294   UNSPEC_VABD_F
295   UNSPEC_VABD_S
296   UNSPEC_VABD_U
297   UNSPEC_VABDL_S
298   UNSPEC_VABDL_U
299   UNSPEC_VADD
300   UNSPEC_VADDHN
301   UNSPEC_VRADDHN
302   UNSPEC_VADDL_S
303   UNSPEC_VADDL_U
304   UNSPEC_VADDW_S
305   UNSPEC_VADDW_U
306   UNSPEC_VBSL
307   UNSPEC_VCAGE
308   UNSPEC_VCAGT
309   UNSPEC_VCALE
310   UNSPEC_VCALT
311   UNSPEC_VCEQ
312   UNSPEC_VCGE
313   UNSPEC_VCGEU
314   UNSPEC_VCGT
315   UNSPEC_VCGTU
316   UNSPEC_VCLS
317   UNSPEC_VCONCAT
318   UNSPEC_VCVT
319   UNSPEC_VCVT_S
320   UNSPEC_VCVT_U
321   UNSPEC_VCVT_S_N
322   UNSPEC_VCVT_U_N
323   UNSPEC_VCVT_HF_S_N
324   UNSPEC_VCVT_HF_U_N
325   UNSPEC_VCVT_SI_S_N
326   UNSPEC_VCVT_SI_U_N
327   UNSPEC_VCVTH_S
328   UNSPEC_VCVTH_U
329   UNSPEC_VCVTA_S
330   UNSPEC_VCVTA_U
331   UNSPEC_VCVTM_S
332   UNSPEC_VCVTM_U
333   UNSPEC_VCVTN_S
334   UNSPEC_VCVTN_U
335   UNSPEC_VCVTP_S
336   UNSPEC_VCVTP_U
337   UNSPEC_VEXT
338   UNSPEC_VHADD_S
339   UNSPEC_VHADD_U
340   UNSPEC_VRHADD_S
341   UNSPEC_VRHADD_U
342   UNSPEC_VHSUB_S
343   UNSPEC_VHSUB_U
344   UNSPEC_VLD1
345   UNSPEC_VLD1X3A
346   UNSPEC_VLD1X3B
347   UNSPEC_VLD1X4A
348   UNSPEC_VLD1X4B
349   UNSPEC_VLD1_LANE
350   UNSPEC_VLD2
351   UNSPEC_VLD2_DUP
352   UNSPEC_VLD2_LANE
353   UNSPEC_VLD3
354   UNSPEC_VLD3A
355   UNSPEC_VLD3B
356   UNSPEC_VLD3_DUP
357   UNSPEC_VLD3_LANE
358   UNSPEC_VLD4
359   UNSPEC_VLD4A
360   UNSPEC_VLD4B
361   UNSPEC_VLD4_DUP
362   UNSPEC_VLD4_LANE
363   UNSPEC_VMAX
364   UNSPEC_VMAX_U
365   UNSPEC_VMAXNM
366   UNSPEC_VMIN
367   UNSPEC_VMIN_U
368   UNSPEC_VMINNM
369   UNSPEC_VMLA
370   UNSPEC_VMLA_LANE
371   UNSPEC_VMLAL_S
372   UNSPEC_VMLAL_U
373   UNSPEC_VMLAL_S_LANE
374   UNSPEC_VMLAL_U_LANE
375   UNSPEC_VMLS
376   UNSPEC_VMLS_LANE
377   UNSPEC_VMLSL_S
378   UNSPEC_VMLSL_U
379   UNSPEC_VMLSL_S_LANE
380   UNSPEC_VMLSL_U_LANE
381   UNSPEC_VMLSL_LANE
382   UNSPEC_VFMA_LANE
383   UNSPEC_VFMS_LANE
384   UNSPEC_VMOVL_S
385   UNSPEC_VMOVL_U
386   UNSPEC_VMOVN
387   UNSPEC_VMUL
388   UNSPEC_VMULL_P
389   UNSPEC_VMULL_S
390   UNSPEC_VMULL_U
391   UNSPEC_VMUL_LANE
392   UNSPEC_VMULL_S_LANE
393   UNSPEC_VMULL_U_LANE
394   UNSPEC_VPADAL_S
395   UNSPEC_VPADAL_U
396   UNSPEC_VPADD
397   UNSPEC_VPADDL_S
398   UNSPEC_VPADDL_U
399   UNSPEC_VPMAX
400   UNSPEC_VPMAX_U
401   UNSPEC_VPMIN
402   UNSPEC_VPMIN_U
403   UNSPEC_VPSMAX
404   UNSPEC_VPSMIN
405   UNSPEC_VPUMAX
406   UNSPEC_VPUMIN
407   UNSPEC_VQABS
408   UNSPEC_VQADD_S
409   UNSPEC_VQADD_U
410   UNSPEC_VQDMLAL
411   UNSPEC_VQDMLAL_LANE
412   UNSPEC_VQDMLSL
413   UNSPEC_VQDMLSL_LANE
414   UNSPEC_VQDMULH
415   UNSPEC_VQDMULH_LANE
416   UNSPEC_VQRDMULH
417   UNSPEC_VQRDMULH_LANE
418   UNSPEC_VQDMULL
419   UNSPEC_VQDMULL_LANE
420   UNSPEC_VQMOVN_S
421   UNSPEC_VQMOVN_U
422   UNSPEC_VQMOVUN
423   UNSPEC_VQNEG
424   UNSPEC_VQSHL_S
425   UNSPEC_VQSHL_U
426   UNSPEC_VQRSHL_S
427   UNSPEC_VQRSHL_U
428   UNSPEC_VQSHL_S_N
429   UNSPEC_VQSHL_U_N
430   UNSPEC_VQSHLU_N
431   UNSPEC_VQSHRN_S_N
432   UNSPEC_VQSHRN_U_N
433   UNSPEC_VQRSHRN_S_N
434   UNSPEC_VQRSHRN_U_N
435   UNSPEC_VQSHRUN_N
436   UNSPEC_VQRSHRUN_N
437   UNSPEC_VQSUB_S
438   UNSPEC_VQSUB_U
439   UNSPEC_VRECPE
440   UNSPEC_VRECPS
441   UNSPEC_VREV16
442   UNSPEC_VREV32
443   UNSPEC_VREV64
444   UNSPEC_VRSQRTE
445   UNSPEC_VRSQRTS
446   UNSPEC_VSHL_S
447   UNSPEC_VSHL_U
448   UNSPEC_VRSHL_S
449   UNSPEC_VRSHL_U
450   UNSPEC_VSHLL_S_N
451   UNSPEC_VSHLL_U_N
452   UNSPEC_VSHL_N
453   UNSPEC_VSHR_S_N
454   UNSPEC_VSHR_U_N
455   UNSPEC_VRSHR_S_N
456   UNSPEC_VRSHR_U_N
457   UNSPEC_VSHRN_N
458   UNSPEC_VRSHRN_N
459   UNSPEC_VSLI
460   UNSPEC_VSRA_S_N
461   UNSPEC_VSRA_U_N
462   UNSPEC_VRSRA_S_N
463   UNSPEC_VRSRA_U_N
464   UNSPEC_VSRI
465   UNSPEC_VST1
466   UNSPEC_VST1X3A
467   UNSPEC_VST1X3B
468   UNSPEC_VST1X4A
469   UNSPEC_VST1X4B
470   UNSPEC_VST1_LANE
471   UNSPEC_VST2
472   UNSPEC_VST2_LANE
473   UNSPEC_VST3
474   UNSPEC_VST3A
475   UNSPEC_VST3B
476   UNSPEC_VST3_LANE
477   UNSPEC_VST4
478   UNSPEC_VST4A
479   UNSPEC_VST4B
480   UNSPEC_VST4_LANE
481   UNSPEC_VSTRUCTDUMMY
482   UNSPEC_VSUB
483   UNSPEC_VSUBHN
484   UNSPEC_VRSUBHN
485   UNSPEC_VSUBL_S
486   UNSPEC_VSUBL_U
487   UNSPEC_VSUBW_S
488   UNSPEC_VSUBW_U
489   UNSPEC_VTBL
490   UNSPEC_VTBX
491   UNSPEC_VTRN1
492   UNSPEC_VTRN2
493   UNSPEC_VTST
494   UNSPEC_VUZP1
495   UNSPEC_VUZP2
496   UNSPEC_VZIP1
497   UNSPEC_VZIP2
498   UNSPEC_MISALIGNED_ACCESS
499   UNSPEC_VCLE
500   UNSPEC_VCLT
501   UNSPEC_NVRINTZ
502   UNSPEC_NVRINTP
503   UNSPEC_NVRINTM
504   UNSPEC_NVRINTX
505   UNSPEC_NVRINTA
506   UNSPEC_NVRINTN
507   UNSPEC_VQRDMLAH
508   UNSPEC_VQRDMLSH
509   UNSPEC_VRND
510   UNSPEC_VRNDA
511   UNSPEC_VRNDI
512   UNSPEC_VRNDM
513   UNSPEC_VRNDN
514   UNSPEC_VRNDP
515   UNSPEC_VRNDX
516   UNSPEC_DOT_S
517   UNSPEC_DOT_U
518   UNSPEC_DOT_US
519   UNSPEC_DOT_SU
520   UNSPEC_VFML_LO
521   UNSPEC_VFML_HI
522   UNSPEC_VCADD90
523   UNSPEC_VCADD270
524   UNSPEC_VCMLA
525   UNSPEC_VCMLA90
526   UNSPEC_VCMLA180
527   UNSPEC_VCMLA270
528   UNSPEC_VCMLA_CONJ
529   UNSPEC_VCMLA180_CONJ
530   UNSPEC_VCMUL
531   UNSPEC_VCMUL90
532   UNSPEC_VCMUL180
533   UNSPEC_VCMUL270
534   UNSPEC_VCMUL_CONJ
535   UNSPEC_MATMUL_S
536   UNSPEC_MATMUL_U
537   UNSPEC_MATMUL_US
538   UNSPEC_BFCVT
539   UNSPEC_BFCVT_HIGH
540   UNSPEC_BFMMLA
541   UNSPEC_BFMAB
542   UNSPEC_BFMAT
545 ;; Enumerators for MVE unspecs.
546 (define_c_enum "unspec" [
547   VST4Q
548   VRNDXQ_F
549   VRNDQ_F
550   VRNDPQ_F
551   VRNDNQ_F
552   VRNDMQ_F
553   VRNDAQ_F
554   VREV64Q_F
555   VDUPQ_N_F
556   VREV32Q_F
557   VCVTTQ_F32_F16
558   VCVTBQ_F32_F16
559   VCVTQ_TO_F_S
560   VQNEGQ_S
561   VCVTQ_TO_F_U
562   VREV16Q_S
563   VREV16Q_U
564   VADDLVQ_S
565   VMVNQ_N_S
566   VMVNQ_N_U
567   VCVTAQ_S
568   VCVTAQ_U
569   VREV64Q_S
570   VREV64Q_U
571   VQABSQ_S
572   VDUPQ_N_U
573   VDUPQ_N_S
574   VCLSQ_S
575   VADDVQ_S
576   VADDVQ_U
577   VREV32Q_U
578   VREV32Q_S
579   VMOVLTQ_U
580   VMOVLTQ_S
581   VMOVLBQ_S
582   VMOVLBQ_U
583   VCVTQ_FROM_F_S
584   VCVTQ_FROM_F_U
585   VCVTPQ_S
586   VCVTPQ_U
587   VCVTNQ_S
588   VCVTNQ_U
589   VCVTMQ_S
590   VCVTMQ_U
591   VADDLVQ_U
592   VCTP
593   VCTP_M
594   LETP8
595   LETP16
596   LETP32
597   LETP64
598   VPNOT
599   VCREATEQ_F
600   VCVTQ_N_TO_F_S
601   VCVTQ_N_TO_F_U
602   VBRSRQ_N_F
603   VSUBQ_N_F
604   VCREATEQ_U
605   VCREATEQ_S
606   VSHRQ_N_S
607   VSHRQ_N_U
608   VCVTQ_N_FROM_F_S
609   VCVTQ_N_FROM_F_U
610   VADDLVQ_P_S
611   VADDLVQ_P_U
612   VSHLQ_S
613   VSHLQ_U
614   VABDQ_S
615   VADDQ_N_S
616   VADDVAQ_S
617   VADDVQ_P_S
618   VBRSRQ_N_S
619   VHADDQ_S
620   VHADDQ_N_S
621   VHSUBQ_S
622   VHSUBQ_N_S
623   VMAXQ_S
624   VMAXVQ_S
625   VMINQ_S
626   VMINVQ_S
627   VMLADAVQ_S
628   VMULHQ_S
629   VMULLBQ_INT_S
630   VMULLTQ_INT_S
631   VMULQ_S
632   VMULQ_N_S
633   VQADDQ_S
634   VQADDQ_N_S
635   VQRSHLQ_S
636   VQRSHLQ_N_S
637   VQSHLQ_S
638   VQSHLQ_N_S
639   VQSHLQ_R_S
640   VQSUBQ_S
641   VQSUBQ_N_S
642   VRHADDQ_S
643   VRMULHQ_S
644   VRSHLQ_S
645   VRSHLQ_N_S
646   VRSHRQ_N_S
647   VSHLQ_N_S
648   VSHLQ_R_S
649   VSUBQ_S
650   VSUBQ_N_S
651   VABDQ_U
652   VADDQ_N_U
653   VADDVAQ_U
654   VADDVQ_P_U
655   VBRSRQ_N_U
656   VHADDQ_U
657   VHADDQ_N_U
658   VHSUBQ_U
659   VHSUBQ_N_U
660   VMAXQ_U
661   VMAXVQ_U
662   VMINQ_U
663   VMINVQ_U
664   VMLADAVQ_U
665   VMULHQ_U
666   VMULLBQ_INT_U
667   VMULLTQ_INT_U
668   VMULQ_U
669   VMULQ_N_U
670   VQADDQ_U
671   VQADDQ_N_U
672   VQRSHLQ_U
673   VQRSHLQ_N_U
674   VQSHLQ_U
675   VQSHLQ_N_U
676   VQSHLQ_R_U
677   VQSUBQ_U
678   VQSUBQ_N_U
679   VRHADDQ_U
680   VRMULHQ_U
681   VRSHLQ_U
682   VRSHLQ_N_U
683   VRSHRQ_N_U
684   VSHLQ_N_U
685   VSHLQ_R_U
686   VSUBQ_U
687   VSUBQ_N_U
688   VHCADDQ_ROT270_S
689   VHCADDQ_ROT90_S
690   VMAXAQ_S
691   VMAXAVQ_S
692   VMINAQ_S
693   VMINAVQ_S
694   VMLADAVXQ_S
695   VMLSDAVQ_S
696   VMLSDAVXQ_S
697   VQDMULHQ_N_S
698   VQDMULHQ_S
699   VQRDMULHQ_N_S
700   VQRDMULHQ_S
701   VQSHLUQ_N_S
702   VABDQ_M_S
703   VABDQ_M_U
704   VABDQ_F
705   VADDQ_N_F
706   VMAXNMAQ_F
707   VMAXNMAVQ_F
708   VMAXNMQ_F
709   VMAXNMVQ_F
710   VMINNMAQ_F
711   VMINNMAVQ_F
712   VMINNMQ_F
713   VMINNMVQ_F
714   VMULQ_F
715   VMULQ_N_F
716   VSUBQ_F
717   VADDLVAQ_U
718   VADDLVAQ_S
719   VBICQ_N_U
720   VBICQ_N_S
721   VCVTBQ_F16_F32
722   VCVTTQ_F16_F32
723   VMLALDAVQ_U
724   VMLALDAVXQ_S
725   VMLALDAVQ_S
726   VMLSLDAVQ_S
727   VMLSLDAVXQ_S
728   VMOVNBQ_U
729   VMOVNBQ_S
730   VMOVNTQ_U
731   VMOVNTQ_S
732   VORRQ_N_S
733   VORRQ_N_U
734   VQDMULLBQ_N_S
735   VQDMULLBQ_S
736   VQDMULLTQ_N_S
737   VQDMULLTQ_S
738   VQMOVNBQ_U
739   VQMOVNBQ_S
740   VQMOVUNBQ_S
741   VQMOVUNTQ_S
742   VRMLALDAVHXQ_S
743   VRMLSLDAVHQ_S
744   VRMLSLDAVHXQ_S
745   VSHLLBQ_S
746   VSHLLBQ_U
747   VSHLLTQ_U
748   VSHLLTQ_S
749   VQMOVNTQ_U
750   VQMOVNTQ_S
751   VSHLLBQ_N_S
752   VSHLLBQ_N_U
753   VSHLLTQ_N_U
754   VSHLLTQ_N_S
755   VRMLALDAVHQ_U
756   VRMLALDAVHQ_S
757   VMULLTQ_POLY_P
758   VMULLBQ_POLY_P
759   VBICQ_M_N_S
760   VBICQ_M_N_U
761   VCMPEQQ_M_F
762   VCVTAQ_M_S
763   VCVTAQ_M_U
764   VCVTQ_M_TO_F_S
765   VCVTQ_M_TO_F_U
766   VQRSHRNBQ_N_U
767   VQRSHRNBQ_N_S
768   VQRSHRUNBQ_N_S
769   VRMLALDAVHAQ_S
770   VABAVQ_S
771   VABAVQ_U
772   VSHLCQ_S
773   VSHLCQ_U
774   VRMLALDAVHAQ_U
775   VABSQ_M_S
776   VADDVAQ_P_S
777   VADDVAQ_P_U
778   VCLSQ_M_S
779   VCLZQ_M_S
780   VCLZQ_M_U
781   VCMPCSQ_M_N_U
782   VCMPCSQ_M_U
783   VCMPEQQ_M_N_S
784   VCMPEQQ_M_N_U
785   VCMPEQQ_M_S
786   VCMPEQQ_M_U
787   VCMPGEQ_M_N_S
788   VCMPGEQ_M_S
789   VCMPGTQ_M_N_S
790   VCMPGTQ_M_S
791   VCMPHIQ_M_N_U
792   VCMPHIQ_M_U
793   VCMPLEQ_M_N_S
794   VCMPLEQ_M_S
795   VCMPLTQ_M_N_S
796   VCMPLTQ_M_S
797   VCMPNEQ_M_N_S
798   VCMPNEQ_M_N_U
799   VCMPNEQ_M_S
800   VCMPNEQ_M_U
801   VDUPQ_M_N_S
802   VDUPQ_M_N_U
803   VDWDUPQ_N_U
804   VDWDUPQ_WB_U
805   VIWDUPQ_N_U
806   VIWDUPQ_WB_U
807   VMAXAQ_M_S
808   VMAXAVQ_P_S
809   VMAXVQ_P_S
810   VMAXVQ_P_U
811   VMINAQ_M_S
812   VMINAVQ_P_S
813   VMINVQ_P_S
814   VMINVQ_P_U
815   VMLADAVAQ_S
816   VMLADAVAQ_U
817   VMLADAVQ_P_S
818   VMLADAVQ_P_U
819   VMLADAVXQ_P_S
820   VMLAQ_N_S
821   VMLAQ_N_U
822   VMLASQ_N_S
823   VMLASQ_N_U
824   VMLSDAVQ_P_S
825   VMLSDAVXQ_P_S
826   VMVNQ_M_S
827   VMVNQ_M_U
828   VNEGQ_M_S
829   VPSELQ_S
830   VPSELQ_U
831   VQABSQ_M_S
832   VQDMLAHQ_N_S
833   VQDMLASHQ_N_S
834   VQNEGQ_M_S
835   VQRDMLADHQ_S
836   VQRDMLADHXQ_S
837   VQRDMLAHQ_N_S
838   VQRDMLASHQ_N_S
839   VQRDMLSDHQ_S
840   VQRDMLSDHXQ_S
841   VQRSHLQ_M_N_S
842   VQRSHLQ_M_N_U
843   VQSHLQ_M_R_S
844   VQSHLQ_M_R_U
845   VREV64Q_M_S
846   VREV64Q_M_U
847   VRSHLQ_M_N_S
848   VRSHLQ_M_N_U
849   VSHLQ_M_R_S
850   VSHLQ_M_R_U
851   VSLIQ_N_S
852   VSLIQ_N_U
853   VSRIQ_N_S
854   VSRIQ_N_U
855   VQDMLSDHXQ_S
856   VQDMLSDHQ_S
857   VQDMLADHXQ_S
858   VQDMLADHQ_S
859   VMLSDAVAXQ_S
860   VMLSDAVAQ_S
861   VMLADAVAXQ_S
862   VCMPGEQ_M_F
863   VCMPGTQ_M_N_F
864   VMLSLDAVQ_P_S
865   VRMLALDAVHAXQ_S
866   VMLSLDAVXQ_P_S
867   VFMAQ_F
868   VMLSLDAVAQ_S
869   VQSHRUNBQ_N_S
870   VQRSHRUNTQ_N_S
871   VMINNMAQ_M_F
872   VFMASQ_N_F
873   VDUPQ_M_N_F
874   VCMPGTQ_M_F
875   VCMPLTQ_M_F
876   VRMLSLDAVHQ_P_S
877   VQSHRUNTQ_N_S
878   VABSQ_M_F
879   VMAXNMAVQ_P_F
880   VFMAQ_N_F
881   VRMLSLDAVHXQ_P_S
882   VREV32Q_M_F
883   VRMLSLDAVHAQ_S
884   VRMLSLDAVHAXQ_S
885   VCMPLTQ_M_N_F
886   VCMPNEQ_M_F
887   VRNDAQ_M_F
888   VRNDPQ_M_F
889   VADDLVAQ_P_S
890   VQMOVUNBQ_M_S
891   VCMPLEQ_M_F
892   VMLSLDAVAXQ_S
893   VRNDXQ_M_F
894   VFMSQ_F
895   VMINNMVQ_P_F
896   VMAXNMVQ_P_F
897   VPSELQ_F
898   VQMOVUNTQ_M_S
899   VREV64Q_M_F
900   VNEGQ_M_F
901   VRNDMQ_M_F
902   VCMPLEQ_M_N_F
903   VCMPGEQ_M_N_F
904   VRNDNQ_M_F
905   VMINNMAVQ_P_F
906   VCMPNEQ_M_N_F
907   VRMLALDAVHQ_P_S
908   VRMLALDAVHXQ_P_S
909   VCMPEQQ_M_N_F
910   VMAXNMAQ_M_F
911   VRNDQ_M_F
912   VMLALDAVQ_P_U
913   VMLALDAVQ_P_S
914   VQMOVNBQ_M_S
915   VQMOVNBQ_M_U
916   VMOVLTQ_M_U
917   VMOVLTQ_M_S
918   VMOVNBQ_M_U
919   VMOVNBQ_M_S
920   VRSHRNTQ_N_U
921   VRSHRNTQ_N_S
922   VORRQ_M_N_S
923   VORRQ_M_N_U
924   VREV32Q_M_S
925   VREV32Q_M_U
926   VQRSHRNTQ_N_U
927   VQRSHRNTQ_N_S
928   VMOVNTQ_M_U
929   VMOVNTQ_M_S
930   VMOVLBQ_M_U
931   VMOVLBQ_M_S
932   VMLALDAVAQ_S
933   VMLALDAVAQ_U
934   VQSHRNBQ_N_U
935   VQSHRNBQ_N_S
936   VSHRNBQ_N_U
937   VSHRNBQ_N_S
938   VRSHRNBQ_N_S
939   VRSHRNBQ_N_U
940   VMLALDAVXQ_P_S
941   VQMOVNTQ_M_U
942   VQMOVNTQ_M_S
943   VMVNQ_M_N_U
944   VMVNQ_M_N_S
945   VQSHRNTQ_N_U
946   VQSHRNTQ_N_S
947   VMLALDAVAXQ_S
948   VSHRNTQ_N_S
949   VSHRNTQ_N_U
950   VCVTBQ_M_F16_F32
951   VCVTBQ_M_F32_F16
952   VCVTTQ_M_F16_F32
953   VCVTTQ_M_F32_F16
954   VCVTMQ_M_S
955   VCVTMQ_M_U
956   VCVTNQ_M_S
957   VCVTPQ_M_S
958   VCVTPQ_M_U
959   VCVTQ_M_N_FROM_F_S
960   VCVTNQ_M_U
961   VREV16Q_M_S
962   VREV16Q_M_U
963   VREV32Q_M
964   VCVTQ_M_FROM_F_U
965   VCVTQ_M_FROM_F_S
966   VRMLALDAVHQ_P_U
967   VADDLVAQ_P_U
968   VCVTQ_M_N_FROM_F_U
969   VQSHLUQ_M_N_S
970   VABAVQ_P_S
971   VABAVQ_P_U
972   VSHLQ_M_S
973   VSHLQ_M_U
974   VSRIQ_M_N_S
975   VSRIQ_M_N_U
976   VSUBQ_M_U
977   VSUBQ_M_S
978   VCVTQ_M_N_TO_F_U
979   VCVTQ_M_N_TO_F_S
980   VQADDQ_M_U
981   VQADDQ_M_S
982   VRSHRQ_M_N_S
983   VSUBQ_M_N_S
984   VSUBQ_M_N_U
985   VBRSRQ_M_N_S
986   VSUBQ_M_N_F
987   VBICQ_M_F
988   VHADDQ_M_U
989   VBICQ_M_U
990   VBICQ_M_S
991   VMULQ_M_N_U
992   VHADDQ_M_S
993   VORNQ_M_F
994   VMLAQ_M_N_S
995   VQSUBQ_M_U
996   VQSUBQ_M_S
997   VMLAQ_M_N_U
998   VQSUBQ_M_N_U
999   VQSUBQ_M_N_S
1000   VMULLTQ_INT_M_S
1001   VMULLTQ_INT_M_U
1002   VMULQ_M_N_S
1003   VMULQ_M_N_F
1004   VMLASQ_M_N_U
1005   VMLASQ_M_N_S
1006   VMAXQ_M_U
1007   VQRDMLAHQ_M_N_U
1008   VCADDQ_ROT270_M_F
1009   VCADDQ_ROT270_M
1010   VQRSHLQ_M_S
1011   VMULQ_M_F
1012   VRHADDQ_M_U
1013   VSHRQ_M_N_U
1014   VRHADDQ_M_S
1015   VMULQ_M_S
1016   VMULQ_M_U
1017   VQDMLASHQ_M_N_S
1018   VQRDMLASHQ_M_N_S
1019   VRSHLQ_M_S
1020   VRSHLQ_M_U
1021   VRSHRQ_M_N_U
1022   VADDQ_M_N_F
1023   VADDQ_M_N_S
1024   VADDQ_M_N_U
1025   VQRDMLASHQ_M_N_U
1026   VMAXQ_M_S
1027   VQRDMLAHQ_M_N_S
1028   VORRQ_M_S
1029   VORRQ_M_U
1030   VORRQ_M_F
1031   VQRSHLQ_M_U
1032   VRMULHQ_M_U
1033   VRMULHQ_M_S
1034   VMINQ_M_S
1035   VMINQ_M_U
1036   VANDQ_M_F
1037   VANDQ_M_U
1038   VANDQ_M_S
1039   VHSUBQ_M_N_S
1040   VHSUBQ_M_N_U
1041   VMULHQ_M_S
1042   VMULHQ_M_U
1043   VMULLBQ_INT_M_U
1044   VMULLBQ_INT_M_S
1045   VCADDQ_ROT90_M_F
1046   VSHRQ_M_N_S
1047   VADDQ_M_U
1048   VSLIQ_M_N_U
1049   VQADDQ_M_N_S
1050   VBRSRQ_M_N_F
1051   VABDQ_M_F
1052   VBRSRQ_M_N_U
1053   VEORQ_M_F
1054   VSHLQ_M_N_S
1055   VQDMLAHQ_M_N_U
1056   VQDMLAHQ_M_N_S
1057   VSHLQ_M_N_U
1058   VMLADAVAQ_P_U
1059   VMLADAVAQ_P_S
1060   VSLIQ_M_N_S
1061   VQSHLQ_M_U
1062   VQSHLQ_M_S
1063   VCADDQ_ROT90_M
1064   VORNQ_M_U
1065   VORNQ_M_S
1066   VQSHLQ_M_N_S
1067   VQSHLQ_M_N_U
1068   VADDQ_M_S
1069   VHADDQ_M_N_S
1070   VADDQ_M_F
1071   VQADDQ_M_N_U
1072   VEORQ_M_S
1073   VEORQ_M_U
1074   VHSUBQ_M_S
1075   VHSUBQ_M_U
1076   VHADDQ_M_N_U
1077   VHCADDQ_ROT90_M_S
1078   VQRDMLSDHQ_M_S
1079   VQRDMLSDHXQ_M_S
1080   VQRDMLADHXQ_M_S
1081   VQDMULHQ_M_S
1082   VMLADAVAXQ_P_S
1083   VQDMLADHXQ_M_S
1084   VQRDMULHQ_M_S
1085   VMLSDAVAXQ_P_S
1086   VQDMULHQ_M_N_S
1087   VHCADDQ_ROT270_M_S
1088   VQDMLSDHQ_M_S
1089   VQDMLSDHXQ_M_S
1090   VMLSDAVAQ_P_S
1091   VQRDMLADHQ_M_S
1092   VQDMLADHQ_M_S
1093   VMLALDAVAQ_P_U
1094   VMLALDAVAQ_P_S
1095   VQRSHRNBQ_M_N_U
1096   VQRSHRNBQ_M_N_S
1097   VQRSHRNTQ_M_N_S
1098   VQSHRNBQ_M_N_U
1099   VQSHRNBQ_M_N_S
1100   VQSHRNTQ_M_N_S
1101   VRSHRNBQ_M_N_U
1102   VRSHRNBQ_M_N_S
1103   VRSHRNTQ_M_N_U
1104   VSHLLBQ_M_N_U
1105   VSHLLBQ_M_N_S
1106   VSHLLTQ_M_N_U
1107   VSHLLTQ_M_N_S
1108   VSHRNBQ_M_N_S
1109   VSHRNBQ_M_N_U
1110   VSHRNTQ_M_N_S
1111   VSHRNTQ_M_N_U
1112   VMLALDAVAXQ_P_S
1113   VQRSHRNTQ_M_N_U
1114   VQSHRNTQ_M_N_U
1115   VRSHRNTQ_M_N_S
1116   VQRDMULHQ_M_N_S
1117   VRMLALDAVHAQ_P_S
1118   VMLSLDAVAQ_P_S
1119   VMLSLDAVAXQ_P_S
1120   VMULLBQ_POLY_M_P
1121   VMULLTQ_POLY_M_P
1122   VQDMULLBQ_M_N_S
1123   VQDMULLBQ_M_S
1124   VQDMULLTQ_M_N_S
1125   VQDMULLTQ_M_S
1126   VQRSHRUNBQ_M_N_S
1127   VQSHRUNBQ_M_N_S
1128   VQSHRUNTQ_M_N_S
1129   VRMLALDAVHAQ_P_U
1130   VRMLALDAVHAXQ_P_S
1131   VRMLSLDAVHAQ_P_S
1132   VRMLSLDAVHAXQ_P_S
1133   VQRSHRUNTQ_M_N_S
1134   VCMLAQ_M_F
1135   VCMLAQ_ROT180_M_F
1136   VCMLAQ_ROT270_M_F
1137   VCMLAQ_ROT90_M_F
1138   VCMULQ_M_F
1139   VCMULQ_ROT180_M_F
1140   VCMULQ_ROT270_M_F
1141   VCMULQ_ROT90_M_F
1142   VFMAQ_M_F
1143   VFMAQ_M_N_F
1144   VFMASQ_M_N_F
1145   VFMSQ_M_F
1146   VMAXNMQ_M_F
1147   VMINNMQ_M_F
1148   VSUBQ_M_F
1149   VSTRWQSB_S
1150   VSTRWQSB_U
1151   VSTRBQSO_S
1152   VSTRBQSO_U
1153   VLDRQ
1154   VLDRQ_Z
1155   VLDRQ_EXT
1156   VLDRQ_EXT_Z
1157   VLDRBQGO_S
1158   VLDRBQGO_U
1159   VLDRWQGB_S
1160   VLDRWQGB_U
1161   VLDRHQGO_S
1162   VLDRHQGO_U
1163   VLDRHQGSO_S
1164   VLDRHQGSO_U
1165   VLDRDQGB_S
1166   VLDRDQGB_U
1167   VLDRDQGO_S
1168   VLDRDQGO_U
1169   VLDRDQGSO_S
1170   VLDRDQGSO_U
1171   VLDRHQGO_F
1172   VLDRHQGSO_F
1173   VLDRWQGB_F
1174   VLDRWQGO_F
1175   VLDRWQGO_S
1176   VLDRWQGO_U
1177   VLDRWQGSO_F
1178   VLDRWQGSO_S
1179   VLDRWQGSO_U
1180   VSTRQ
1181   VSTRQ_P
1182   VSTRQ_TRUNC
1183   VSTRQ_TRUNC_P
1184   VSTRHQSO_S
1185   VSTRDQSB_S
1186   VSTRDQSB_U
1187   VSTRDQSO_S
1188   VSTRDQSO_U
1189   VSTRDQSSO_S
1190   VSTRDQSSO_U
1191   VSTRWQSO_S
1192   VSTRWQSO_U
1193   VSTRWQSSO_S
1194   VSTRWQSSO_U
1195   VSTRHQSO_F
1196   VSTRHQSSO_F
1197   VSTRWQSB_F
1198   VSTRWQSO_F
1199   VSTRWQSSO_F
1200   VDDUPQ
1201   VDDUPQ_M
1202   VDWDUPQ
1203   VDWDUPQ_M
1204   VIDUPQ
1205   VIDUPQ_M
1206   VIWDUPQ
1207   VIWDUPQ_M
1208   VSTRWQSBWB_S
1209   VSTRWQSBWB_U
1210   VLDRWQGBWB_S
1211   VLDRWQGBWB_U
1212   VSTRWQSBWB_F
1213   VLDRWQGBWB_F
1214   VSTRDQSBWB_S
1215   VSTRDQSBWB_U
1216   VLDRDQGBWB_S
1217   VLDRDQGBWB_U
1218   VADCQ_U
1219   VADCQ_M_U
1220   VADCQ_S
1221   VADCQ_M_S
1222   VSBCIQ_U
1223   VSBCIQ_S
1224   VSBCIQ_M_U
1225   VSBCIQ_M_S
1226   VSBCQ_U
1227   VSBCQ_S
1228   VSBCQ_M_U
1229   VSBCQ_M_S
1230   VADCIQ_U
1231   VADCIQ_M_U
1232   VADCIQ_S
1233   VADCIQ_M_S
1234   VLD2Q
1235   VLD4Q
1236   VST2Q
1237   VSHLCQ_M_U
1238   VSHLCQ_M_S
1239   VSTRHQSO_U
1240   VSTRHQSSO_S
1241   VSTRHQSSO_U
1242   VSTRHQ_S
1243   SRSHRL
1244   SRSHR
1245   URSHR
1246   URSHRL
1247   SQRSHR
1248   UQRSHL
1249   UQRSHLL_64
1250   UQRSHLL_48
1251   SQRSHRL_64
1252   SQRSHRL_48
1253   REINTERPRET
1256 ; DLSTP unspecs must be volatile to guarantee the scheduler does not reschedule
1257 ; these instructions within the loop preheader.
1258 (define_c_enum "unspecv" [
1259   DLSTP8
1260   DLSTP16
1261   DLSTP32
1262   DLSTP64