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2002-06-12 Eric Christopher <echristo@redhat.com>
[official-gcc.git] / gcc / config / mips / mips.h
blob7778361e8597046c8a48ed2ad6099fc497c8ed0d
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
34
35 /* MIPS external variables defined in mips.c. */
36
37 /* comparison type */
38 enum cmp_type {
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
44 };
45
46 /* types of delay slot */
47 enum delay_type {
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
52 };
53
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
58
59 enum processor_type {
60 PROCESSOR_DEFAULT,
61 PROCESSOR_R3000,
62 PROCESSOR_R3900,
63 PROCESSOR_R6000,
64 PROCESSOR_R4000,
65 PROCESSOR_R4100,
66 PROCESSOR_R4300,
67 PROCESSOR_R4600,
68 PROCESSOR_R4650,
69 PROCESSOR_R5000,
70 PROCESSOR_R8000,
71 PROCESSOR_R4KC,
72 PROCESSOR_R5KC,
73 PROCESSOR_R20KC
74 };
75
76 /* Recast the cpu class to be the cpu attribute. */
77 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
78
79 /* Which ABI to use. These are constants because abi64.h must check their
80 value at preprocessing time.
81
82 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
83 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
84
85 #define ABI_32 0
86 #define ABI_N32 1
87 #define ABI_64 2
88 #define ABI_EABI 3
89 #define ABI_O64 4
90 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
91 which is not the same as the above EABI (defined by Cygnus,
92 Greenhills, and Toshiba?). MEABI is not yet complete or published,
93 but at this point it looks like N32 as far as calling conventions go,
94 but allows for either 32 or 64 bit registers.
95
96 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
97 EABI the legacy EABI. In the end we may end up calling both ABI's
98 EABI but give them different version numbers, but for now I'm going
99 with different names. */
100 #define ABI_MEABI 5
101
102 /* Whether to emit abicalls code sequences or not. */
103
104 enum mips_abicalls_type {
105 MIPS_ABICALLS_NO,
106 MIPS_ABICALLS_YES
107 };
108
109 /* Recast the abicalls class to be the abicalls attribute. */
110 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
111
112 /* Which type of block move to do (whether or not the last store is
113 split out so it can fill a branch delay slot). */
114
115 enum block_move_type {
116 BLOCK_MOVE_NORMAL, /* generate complete block move */
117 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
118 BLOCK_MOVE_LAST /* generate just the last store */
119 };
120
121 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
122 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
123 extern const char *current_function_file; /* filename current function is in */
124 extern int num_source_filenames; /* current .file # */
125 extern int inside_function; /* != 0 if inside of a function */
126 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
127 extern int file_in_function_warning; /* warning given about .file in func */
128 extern int sdb_label_count; /* block start/end next label # */
129 extern int sdb_begin_function_line; /* Starting Line of current function */
130 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
131 extern int g_switch_value; /* value of the -G xx switch */
132 extern int g_switch_set; /* whether -G xx was passed. */
133 extern int sym_lineno; /* sgi next label # for each stmt */
134 extern int set_noreorder; /* # of nested .set noreorder's */
135 extern int set_nomacro; /* # of nested .set nomacro's */
136 extern int set_noat; /* # of nested .set noat's */
137 extern int set_volatile; /* # of nested .set volatile's */
138 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
139 extern int mips_dbx_regno[]; /* Map register # to debug register # */
140 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
141 extern enum cmp_type branch_type; /* what type of branch to use */
142 extern enum processor_type mips_arch; /* which cpu to codegen for */
143 extern enum processor_type mips_tune; /* which cpu to schedule for */
144 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
145 extern int mips_isa; /* architectural level */
146 extern int mips16; /* whether generating mips16 code */
147 extern int mips16_hard_float; /* mips16 without -msoft-float */
148 extern int mips_entry; /* generate entry/exit for mips16 */
149 extern const char *mips_cpu_string; /* for -mcpu=<xxx> */
150 extern const char *mips_arch_string; /* for -march=<xxx> */
151 extern const char *mips_tune_string; /* for -mtune=<xxx> */
152 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
153 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
154 extern const char *mips_entry_string; /* for -mentry */
155 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
156 extern const char *mips_explicit_type_size_string;/* for -mexplicit-type-size */
157 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
158 extern int mips_split_addresses; /* perform high/lo_sum support */
159 extern int dslots_load_total; /* total # load related delay slots */
160 extern int dslots_load_filled; /* # filled load delay slots */
161 extern int dslots_jump_total; /* total # jump related delay slots */
162 extern int dslots_jump_filled; /* # filled jump delay slots */
163 extern int dslots_number_nops; /* # of nops needed by previous insn */
164 extern int num_refs[3]; /* # 1/2/3 word references */
165 extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
166 extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
167 extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
168 extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
169 extern int mips_string_length; /* length of strings for mips16 */
170
171 /* Functions to change what output section we are using. */
172 extern void sdata_section PARAMS ((void));
173 extern void sbss_section PARAMS ((void));
174
175 /* Macros to silence warnings about numbers being signed in traditional
176 C and unsigned in ISO C when compiled on 32-bit hosts. */
177
178 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
179 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
180 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
181
182 \f
183 /* Run-time compilation parameters selecting different hardware subsets. */
184
185 /* Macros used in the machine description to test the flags. */
186
187 /* Bits for real switches */
188 #define MASK_INT64 0x00000001 /* ints are 64 bits */
189 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
190 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
191 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
192 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
193 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
194 #define MASK_STATS 0x00000040 /* print statistics to stderr */
195 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
196 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
197 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
198 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
199 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
200 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
201 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
202 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
203 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
204 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
205 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
206 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
207 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
208 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
209 #define MASK_NO_CHECK_ZERO_DIV \
210 0x00200000 /* divide by zero checking */
211 #define MASK_CHECK_RANGE_DIV \
212 0x00400000 /* divide result range checking */
213 #define MASK_UNINIT_CONST_IN_RODATA \
214 0x00800000 /* Store uninitialized
215 consts in rodata */
216 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
217 multiply-add operations. */
218
219 /* Debug switches, not documented */
220 #define MASK_DEBUG 0 /* unused */
221 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
222 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
223 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
224 #define MASK_DEBUG_D 0 /* don't do define_split's */
225 #define MASK_DEBUG_E 0 /* function_arg debug */
226 #define MASK_DEBUG_F 0 /* ??? */
227 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
228 #define MASK_DEBUG_H 0 /* allow ints in FP registers */
229 #define MASK_DEBUG_I 0 /* unused */
230
231 /* Dummy switches used only in specs */
232 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
233
234 /* r4000 64 bit sizes */
235 #define TARGET_INT64 (target_flags & MASK_INT64)
236 #define TARGET_LONG64 (target_flags & MASK_LONG64)
237 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
238 #define TARGET_64BIT (target_flags & MASK_64BIT)
239
240 /* Mips vs. GNU linker */
241 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
242
243 /* Mips vs. GNU assembler */
244 #define TARGET_GAS (target_flags & MASK_GAS)
245 #define TARGET_MIPS_AS (!TARGET_GAS)
246
247 /* Debug Modes */
248 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
249 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
250 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
251 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
252 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
253 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
254 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
255 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
256 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
257 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
258
259 /* Reg. Naming in .s ($21 vs. $a0) */
260 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
261
262 /* Optimize for Sdata/Sbss */
263 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
264
265 /* print program statistics */
266 #define TARGET_STATS (target_flags & MASK_STATS)
267
268 /* call memcpy instead of inline code */
269 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
270
271 /* .abicalls, etc from Pyramid V.4 */
272 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
273
274 /* software floating point */
275 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
276 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
277
278 /* always call through a register */
279 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
280
281 /* generate embedded PIC code;
282 requires gas. */
283 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
284
285 /* for embedded systems, optimize for
286 reduced RAM space instead of for
287 fastest code. */
288 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
289
290 /* always store uninitialized const
291 variables in rodata, requires
292 TARGET_EMBEDDED_DATA. */
293 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
294
295 /* generate big endian code. */
296 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
297
298 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
299 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
300
301 #define TARGET_MAD (target_flags & MASK_MAD)
302
303 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
304
305 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
306
307 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
308 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
309
310 /* This is true if we must enable the assembly language file switching
311 code. */
312
313 #define TARGET_FILE_SWITCHING \
314 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
315
316 /* We must disable the function end stabs when doing the file switching trick,
317 because the Lscope stabs end up in the wrong place, making it impossible
318 to debug the resulting code. */
319 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
320
321 /* Generate mips16 code */
322 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
323
324 /* Generic ISA defines. */
325 #define ISA_MIPS1 (mips_isa == 1)
326 #define ISA_MIPS2 (mips_isa == 2)
327 #define ISA_MIPS3 (mips_isa == 3)
328 #define ISA_MIPS4 (mips_isa == 4)
329 #define ISA_MIPS32 (mips_isa == 32)
330 #define ISA_MIPS64 (mips_isa == 64)
331
332 /* Architecture target defines. */
333 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
334 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
335 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
336 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
337 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
338 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
339
340 /* Scheduling target defines. */
341 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
342 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
343 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
344 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
345 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 builtin_assert ("cpu=mips"); \
352 builtin_define ("__mips__"); \
353 builtin_define ("_mips"); \
354 \
355 /* We do this here because __mips is defined below \
356 and so we can't use builtin_define_std. */ \
357 if (!flag_iso) \
358 builtin_define ("mips"); \
359 \
360 if (TARGET_64BIT) \
361 { \
362 builtin_define ("__mips64"); \
363 /* Silly, but will do until processor defines. */ \
364 builtin_define_std ("R4000"); \
365 builtin_define ("_R4000"); \
366 } \
367 else \
368 { \
369 /* Ditto. */ \
370 builtin_define_std ("R3000"); \
371 builtin_define ("_R3000"); \
372 } \
373 if (TARGET_FLOAT64) \
374 builtin_define ("__mips_fpr=64"); \
375 else \
376 builtin_define ("__mips_fpr=32"); \
377 \
378 if (TARGET_MIPS16) \
379 builtin_define ("__mips16"); \
380 \
381 if (ISA_MIPS1) \
382 { \
383 builtin_define ("__mips=1"); \
384 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
385 } \
386 else if (ISA_MIPS2) \
387 { \
388 builtin_define ("__mips=2"); \
389 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
390 } \
391 else if (ISA_MIPS3) \
392 { \
393 builtin_define ("__mips=3"); \
394 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
395 } \
396 else if (ISA_MIPS4) \
397 { \
398 builtin_define ("__mips=4"); \
399 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
400 } \
401 else if (ISA_MIPS32) \
402 { \
403 builtin_define ("__mips=32"); \
404 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
405 } \
406 else if (ISA_MIPS64) \
407 { \
408 builtin_define ("__mips=64"); \
409 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
410 } \
411 \
412 if (TARGET_HARD_FLOAT) \
413 builtin_define ("__mips_hard_float"); \
414 else if (TARGET_SOFT_FLOAT) \
415 builtin_define ("__mips_soft_float"); \
416 \
417 if (TARGET_SINGLE_FLOAT) \
418 builtin_define ("__mips_single_float"); \
419 \
420 if (TARGET_BIG_ENDIAN) \
421 { \
422 builtin_define_std ("MIPSEB"); \
423 builtin_define ("_MIPSEB"); \
424 } \
425 else \
426 { \
427 builtin_define_std ("MIPSEL"); \
428 builtin_define ("_MIPSEL"); \
429 } \
430 \
431 /* Macros dependent on the C dialect. */ \
432 if (preprocessing_asm_p ()) \
433 { \
434 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
435 builtin_define ("_LANGUAGE_ASSEMBLY"); \
436 } \
437 else if (c_language == clk_c) \
438 { \
439 builtin_define_std ("LANGUAGE_C"); \
440 builtin_define ("_LANGUAGE_C"); \
441 } \
442 else if (c_language == clk_cplusplus) \
443 { \
444 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
445 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
446 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
447 } \
448 else if (c_language == clk_objective_c) \
449 { \
450 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
451 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
452 /* Bizzare, but needed at least for Irix. */ \
453 builtin_define_std ("LANGUAGE_C"); \
454 builtin_define ("_LANGUAGE_C"); \
455 } \
456 \
457 if (mips_abi == ABI_EABI) \
458 builtin_define ("__mips_eabi"); \
459 \
460 } while (0)
461
462
463
464 /* Macro to define tables used to set the flags.
465 This is a list in braces of pairs in braces,
466 each pair being { "NAME", VALUE }
467 where VALUE is the bits to set or minus the bits to clear.
468 An empty string NAME is used to identify the default VALUE. */
469
470 #define TARGET_SWITCHES \
471 { \
472 {"no-crt0", 0, \
473 N_("No default crt0.o") }, \
474 {"int64", MASK_INT64 | MASK_LONG64, \
475 N_("Use 64-bit int type")}, \
476 {"long64", MASK_LONG64, \
477 N_("Use 64-bit long type")}, \
478 {"long32", -(MASK_LONG64 | MASK_INT64), \
479 N_("Use 32-bit long type")}, \
480 {"split-addresses", MASK_SPLIT_ADDR, \
481 N_("Optimize lui/addiu address loads")}, \
482 {"no-split-addresses", -MASK_SPLIT_ADDR, \
483 N_("Don't optimize lui/addiu address loads")}, \
484 {"mips-as", -MASK_GAS, \
485 N_("Use MIPS as")}, \
486 {"gas", MASK_GAS, \
487 N_("Use GNU as")}, \
488 {"rnames", MASK_NAME_REGS, \
489 N_("Use symbolic register names")}, \
490 {"no-rnames", -MASK_NAME_REGS, \
491 N_("Don't use symbolic register names")}, \
492 {"gpOPT", MASK_GPOPT, \
493 N_("Use GP relative sdata/sbss sections")}, \
494 {"gpopt", MASK_GPOPT, \
495 N_("Use GP relative sdata/sbss sections")}, \
496 {"no-gpOPT", -MASK_GPOPT, \
497 N_("Don't use GP relative sdata/sbss sections")}, \
498 {"no-gpopt", -MASK_GPOPT, \
499 N_("Don't use GP relative sdata/sbss sections")}, \
500 {"stats", MASK_STATS, \
501 N_("Output compiler statistics")}, \
502 {"no-stats", -MASK_STATS, \
503 N_("Don't output compiler statistics")}, \
504 {"memcpy", MASK_MEMCPY, \
505 N_("Don't optimize block moves")}, \
506 {"no-memcpy", -MASK_MEMCPY, \
507 N_("Optimize block moves")}, \
508 {"mips-tfile", MASK_MIPS_TFILE, \
509 N_("Use mips-tfile asm postpass")}, \
510 {"no-mips-tfile", -MASK_MIPS_TFILE, \
511 N_("Don't use mips-tfile asm postpass")}, \
512 {"soft-float", MASK_SOFT_FLOAT, \
513 N_("Use software floating point")}, \
514 {"hard-float", -MASK_SOFT_FLOAT, \
515 N_("Use hardware floating point")}, \
516 {"fp64", MASK_FLOAT64, \
517 N_("Use 64-bit FP registers")}, \
518 {"fp32", -MASK_FLOAT64, \
519 N_("Use 32-bit FP registers")}, \
520 {"gp64", MASK_64BIT, \
521 N_("Use 64-bit general registers")}, \
522 {"gp32", -MASK_64BIT, \
523 N_("Use 32-bit general registers")}, \
524 {"abicalls", MASK_ABICALLS, \
525 N_("Use Irix PIC")}, \
526 {"no-abicalls", -MASK_ABICALLS, \
527 N_("Don't use Irix PIC")}, \
528 {"long-calls", MASK_LONG_CALLS, \
529 N_("Use indirect calls")}, \
530 {"no-long-calls", -MASK_LONG_CALLS, \
531 N_("Don't use indirect calls")}, \
532 {"embedded-pic", MASK_EMBEDDED_PIC, \
533 N_("Use embedded PIC")}, \
534 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
535 N_("Don't use embedded PIC")}, \
536 {"embedded-data", MASK_EMBEDDED_DATA, \
537 N_("Use ROM instead of RAM")}, \
538 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
539 N_("Don't use ROM instead of RAM")}, \
540 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
541 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
542 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
543 N_("Don't put uninitialized constants in ROM")}, \
544 {"eb", MASK_BIG_ENDIAN, \
545 N_("Use big-endian byte order")}, \
546 {"el", -MASK_BIG_ENDIAN, \
547 N_("Use little-endian byte order")}, \
548 {"single-float", MASK_SINGLE_FLOAT, \
549 N_("Use single (32-bit) FP only")}, \
550 {"double-float", -MASK_SINGLE_FLOAT, \
551 N_("Don't use single (32-bit) FP only")}, \
552 {"mad", MASK_MAD, \
553 N_("Use multiply accumulate")}, \
554 {"no-mad", -MASK_MAD, \
555 N_("Don't use multiply accumulate")}, \
556 {"no-fused-madd", MASK_NO_FUSED_MADD, \
557 N_("Don't generate fused multiply/add instructions")}, \
558 {"fused-madd", -MASK_NO_FUSED_MADD, \
559 N_("Generate fused multiply/add instructions")}, \
560 {"fix4300", MASK_4300_MUL_FIX, \
561 N_("Work around early 4300 hardware bug")}, \
562 {"no-fix4300", -MASK_4300_MUL_FIX, \
563 N_("Don't work around early 4300 hardware bug")}, \
564 {"3900", 0, \
565 N_("Optimize for 3900")}, \
566 {"4650", 0, \
567 N_("Optimize for 4650")}, \
568 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
569 N_("Trap on integer divide by zero")}, \
570 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
571 N_("Don't trap on integer divide by zero")}, \
572 {"check-range-division",MASK_CHECK_RANGE_DIV, \
573 N_("Trap on integer divide overflow")}, \
574 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
575 N_("Don't trap on integer divide overflow")}, \
576 {"debug", MASK_DEBUG, \
577 NULL}, \
578 {"debuga", MASK_DEBUG_A, \
579 NULL}, \
580 {"debugb", MASK_DEBUG_B, \
581 NULL}, \
582 {"debugc", MASK_DEBUG_C, \
583 NULL}, \
584 {"debugd", MASK_DEBUG_D, \
585 NULL}, \
586 {"debuge", MASK_DEBUG_E, \
587 NULL}, \
588 {"debugf", MASK_DEBUG_F, \
589 NULL}, \
590 {"debugg", MASK_DEBUG_G, \
591 NULL}, \
592 {"debugh", MASK_DEBUG_H, \
593 NULL}, \
594 {"debugi", MASK_DEBUG_I, \
595 NULL}, \
596 {"", (TARGET_DEFAULT \
597 | TARGET_CPU_DEFAULT \
598 | TARGET_ENDIAN_DEFAULT), \
599 NULL}, \
600 }
601
602 /* Default target_flags if no switches are specified */
603
604 #ifndef TARGET_DEFAULT
605 #define TARGET_DEFAULT 0
606 #endif
607
608 #ifndef TARGET_CPU_DEFAULT
609 #define TARGET_CPU_DEFAULT 0
610 #endif
611
612 #ifndef TARGET_ENDIAN_DEFAULT
613 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
614 #endif
615
616 #ifndef MIPS_ISA_DEFAULT
617 #define MIPS_ISA_DEFAULT 1
618 #endif
619
620 #ifdef IN_LIBGCC2
621 #undef TARGET_64BIT
622 /* Make this compile time constant for libgcc2 */
623 #ifdef __mips64
624 #define TARGET_64BIT 1
625 #else
626 #define TARGET_64BIT 0
627 #endif
628 #endif /* IN_LIBGCC2 */
629
630 #ifndef MULTILIB_ENDIAN_DEFAULT
631 #if TARGET_ENDIAN_DEFAULT == 0
632 #define MULTILIB_ENDIAN_DEFAULT "EL"
633 #else
634 #define MULTILIB_ENDIAN_DEFAULT "EB"
635 #endif
636 #endif
637
638 #ifndef MULTILIB_ISA_DEFAULT
639 # if MIPS_ISA_DEFAULT == 1
640 # define MULTILIB_ISA_DEFAULT "mips1"
641 # else
642 # if MIPS_ISA_DEFAULT == 2
643 # define MULTILIB_ISA_DEFAULT "mips2"
644 # else
645 # if MIPS_ISA_DEFAULT == 3
646 # define MULTILIB_ISA_DEFAULT "mips3"
647 # else
648 # if MIPS_ISA_DEFAULT == 4
649 # define MULTILIB_ISA_DEFAULT "mips4"
650 # else
651 # if MIPS_ISA_DEFAULT == 32
652 # define MULTILIB_ISA_DEFAULT "mips32"
653 # else
654 # if MIPS_ISA_DEFAULT == 64
655 # define MULTILIB_ISA_DEFAULT "mips64"
656 # else
657 # define MULTILIB_ISA_DEFAULT "mips1"
658 # endif
659 # endif
660 # endif
661 # endif
662 # endif
663 # endif
664 #endif
665
666 #ifndef MULTILIB_DEFAULTS
667 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
668 #endif
669
670 /* We must pass -EL to the linker by default for little endian embedded
671 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
672 linker will default to using big-endian output files. The OUTPUT_FORMAT
673 line must be in the linker script, otherwise -EB/-EL will not work. */
674
675 #ifndef ENDIAN_SPEC
676 #if TARGET_ENDIAN_DEFAULT == 0
677 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
678 #else
679 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
680 #endif
681 #endif
682
683 #define TARGET_OPTIONS \
684 { \
685 SUBTARGET_TARGET_OPTIONS \
686 { "cpu=", &mips_cpu_string, \
687 N_("Specify CPU for scheduling purposes")}, \
688 { "tune=", &mips_tune_string, \
689 N_("Specify CPU for scheduling purposes")}, \
690 { "arch=", &mips_arch_string, \
691 N_("Specify CPU for code generation purposes")}, \
692 { "ips", &mips_isa_string, \
693 N_("Specify a Standard MIPS ISA")}, \
694 { "entry", &mips_entry_string, \
695 N_("Use mips16 entry/exit psuedo ops")}, \
696 { "no-mips16", &mips_no_mips16_string, \
697 N_("Don't use MIPS16 instructions")}, \
698 { "explicit-type-size", &mips_explicit_type_size_string, \
699 NULL}, \
700 { "no-flush-func", &mips_cache_flush_func, \
701 N_("Don't call any cache flush functions")}, \
702 { "flush-func=", &mips_cache_flush_func, \
703 N_("Specify cache flush function")}, \
704 }
705
706 /* This is meant to be redefined in the host dependent files. */
707 #define SUBTARGET_TARGET_OPTIONS
708
709 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
710
711 /* Generate three-operand multiply instructions for SImode. */
712 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
713 || ISA_MIPS32 \
714 || ISA_MIPS64) \
715 && !TARGET_MIPS16)
716
717 /* Generate three-operand multiply instructions for DImode. */
718 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
719 && !TARGET_MIPS16)
720
721 /* Macros to decide whether certain features are available or not,
722 depending on the instruction set architecture level. */
723
724 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
725 #define HAVE_SQRT_P() (!ISA_MIPS1)
726
727 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
728 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
729 || ISA_MIPS4 \
730 || ISA_MIPS64)
731
732 /* ISA has branch likely instructions (eg. mips2). */
733 /* Disable branchlikely for tx39 until compare rewrite. They haven't
734 been generated up to this point. */
735 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
736 && !TARGET_MIPS16)
737
738 /* ISA has the conditional move instructions introduced in mips4. */
739 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
740 || ISA_MIPS32 \
741 || ISA_MIPS64) \
742 && !TARGET_MIPS16)
743
744 /* ISA has just the integer condition move instructions (movn,movz) */
745 #define ISA_HAS_INT_CONDMOVE 0
746
747 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
748 branch on CC, and move (both FP and non-FP) on CC. */
749 #define ISA_HAS_8CC (ISA_MIPS4 \
750 || ISA_MIPS32 \
751 || ISA_MIPS64)
752
753 /* This is a catch all for the other new mips4 instructions: indexed load and
754 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub
755 instructions, and the FP recip and recip sqrt instructions */
756 #define ISA_HAS_FP4 ((ISA_MIPS4 \
757 || ISA_MIPS64) \
758 && !TARGET_MIPS16)
759
760 /* ISA has conditional trap instructions. */
761 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
762 && !TARGET_MIPS16)
763
764 /* ISA has integer multiply-accumulate instructions, madd and msub. */
765 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
766 || ISA_MIPS64 \
767 ) && !TARGET_MIPS16)
768
769 /* ISA has floating-point nmadd and nmsub instructions. */
770 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
771 || ISA_MIPS64) \
772 && ! TARGET_MIPS16)
773
774 /* ISA has count leading zeroes/ones instruction (not implemented). */
775 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
776 || ISA_MIPS64 \
777 ) && !TARGET_MIPS16)
778
779 /* ISA has double-word count leading zeroes/ones instruction (not
780 implemented). */
781 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
782 && !TARGET_MIPS16)
783
784 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
785 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
786 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
787 target_flags, and -mgp64 sets MASK_64BIT.
788
789 Setting MASK_64BIT in target_flags will cause gcc to assume that
790 registers are 64 bits wide. int, long and void * will be 32 bit;
791 this may be changed with -mint64 or -mlong64.
792
793 The gen* programs link code that refers to MASK_64BIT. They don't
794 actually use the information in target_flags; they just refer to
795 it. */
796 \f
797 /* Switch Recognition by gcc.c. Add -G xx support */
798
799 #undef SWITCH_TAKES_ARG
800 #define SWITCH_TAKES_ARG(CHAR) \
801 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
802
803 /* Sometimes certain combinations of command options do not make sense
804 on a particular target machine. You can define a macro
805 `OVERRIDE_OPTIONS' to take account of this. This macro, if
806 defined, is executed once just after all the command options have
807 been parsed.
808
809 On the MIPS, it is used to handle -G. We also use it to set up all
810 of the tables referenced in the other macros. */
811
812 #define OVERRIDE_OPTIONS override_options ()
813
814 /* Zero or more C statements that may conditionally modify two
815 variables `fixed_regs' and `call_used_regs' (both of type `char
816 []') after they have been initialized from the two preceding
817 macros.
818
819 This is necessary in case the fixed or call-clobbered registers
820 depend on target flags.
821
822 You need not define this macro if it has no work to do.
823
824 If the usage of an entire class of registers depends on the target
825 flags, you may indicate this to GCC by using this macro to modify
826 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
827 the classes which should not be used by GCC. Also define the macro
828 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
829 letter for a class that shouldn't be used.
830
831 (However, if this class is not included in `GENERAL_REGS' and all
832 of the insn patterns whose constraints permit this class are
833 controlled by target switches, then GCC will automatically avoid
834 using these registers when the target switches are opposed to
835 them.) */
836
837 #define CONDITIONAL_REGISTER_USAGE \
838 do \
839 { \
840 if (!TARGET_HARD_FLOAT) \
841 { \
842 int regno; \
843 \
844 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
845 fixed_regs[regno] = call_used_regs[regno] = 1; \
846 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
847 fixed_regs[regno] = call_used_regs[regno] = 1; \
848 } \
849 else if (! ISA_HAS_8CC) \
850 { \
851 int regno; \
852 \
853 /* We only have a single condition code register. We \
854 implement this by hiding all the condition code registers, \
855 and generating RTL that refers directly to ST_REG_FIRST. */ \
856 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
857 fixed_regs[regno] = call_used_regs[regno] = 1; \
858 } \
859 /* In mips16 mode, we permit the $t temporary registers to be used \
860 for reload. We prohibit the unused $s registers, since they \
861 are caller saved, and saving them via a mips16 register would \
862 probably waste more time than just reloading the value. */ \
863 if (TARGET_MIPS16) \
864 { \
865 fixed_regs[18] = call_used_regs[18] = 1; \
866 fixed_regs[19] = call_used_regs[19] = 1; \
867 fixed_regs[20] = call_used_regs[20] = 1; \
868 fixed_regs[21] = call_used_regs[21] = 1; \
869 fixed_regs[22] = call_used_regs[22] = 1; \
870 fixed_regs[23] = call_used_regs[23] = 1; \
871 fixed_regs[26] = call_used_regs[26] = 1; \
872 fixed_regs[27] = call_used_regs[27] = 1; \
873 fixed_regs[30] = call_used_regs[30] = 1; \
874 } \
875 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
876 } \
877 while (0)
878
879 /* This is meant to be redefined in the host dependent files. */
880 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
881
882 /* Show we can debug even without a frame pointer. */
883 #define CAN_DEBUG_WITHOUT_FP
884 \f
885 /* Tell collect what flags to pass to nm. */
886 #ifndef NM_FLAGS
887 #define NM_FLAGS "-Bn"
888 #endif
889
890 \f
891 /* Assembler specs. */
892
893 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
894 than gas. */
895
896 #define MIPS_AS_ASM_SPEC "\
897 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
898 %{pipe: %e-pipe is not supported} \
899 %{K} %(subtarget_mips_as_asm_spec)"
900
901 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
902 rather than gas. It may be overridden by subtargets. */
903
904 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
905 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
906 #endif
907
908 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
909 assembler. */
910
911 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64} %(abi_gas_asm_spec) %{mabi=32:%{!mips*:-mips1}}"
912
913
914 extern int mips_abi;
915
916 #ifndef MIPS_ABI_DEFAULT
917 #define MIPS_ABI_DEFAULT ABI_32
918 #endif
919
920 #ifndef ABI_GAS_ASM_SPEC
921 #define ABI_GAS_ASM_SPEC ""
922 #endif
923
924 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
925 GAS_ASM_SPEC as the default, depending upon the value of
926 TARGET_DEFAULT. */
927
928 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
929 /* GAS */
930
931 #define TARGET_ASM_SPEC "\
932 %{mmips-as: %(mips_as_asm_spec)} \
933 %{!mmips-as: %(gas_asm_spec)}"
934
935 #else /* not GAS */
936
937 #define TARGET_ASM_SPEC "\
938 %{!mgas: %(mips_as_asm_spec)} \
939 %{mgas: %(gas_asm_spec)}"
940
941 #endif /* not GAS */
942
943 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
944 to the assembler. It may be overridden by subtargets. */
945 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
946 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
947 %{noasmopt:-O0} \
948 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
949 #endif
950
951 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
952 the assembler. It may be overridden by subtargets. */
953 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
954 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
955 %{g} %{g0} %{g1} %{g2} %{g3} \
956 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
957 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
958 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
959 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
960 #endif
961
962 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
963 overridden by subtargets. */
964
965 #ifndef SUBTARGET_ASM_SPEC
966 #define SUBTARGET_ASM_SPEC ""
967 #endif
968
969 /* ASM_SPEC is the set of arguments to pass to the assembler. */
970
971 #undef ASM_SPEC
972 #define ASM_SPEC "\
973 %{G*} %{EB} %{EL} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
974 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
975 %(subtarget_asm_optimizing_spec) \
976 %(subtarget_asm_debugging_spec) \
977 %{membedded-pic} \
978 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
979 %(target_asm_spec) \
980 %(subtarget_asm_spec)"
981
982 /* Specify to run a post-processor, mips-tfile after the assembler
983 has run to stuff the mips debug information into the object file.
984 This is needed because the $#!%^ MIPS assembler provides no way
985 of specifying such information in the assembly file. If we are
986 cross compiling, disable mips-tfile unless the user specifies
987 -mmips-tfile. */
988
989 #ifndef ASM_FINAL_SPEC
990 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
991 /* GAS */
992 #define ASM_FINAL_SPEC "\
993 %{mmips-as: %{!mno-mips-tfile: \
994 \n mips-tfile %{v*: -v} \
995 %{K: -I %b.o~} \
996 %{!K: %{save-temps: -I %b.o~}} \
997 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
998 %{.s:%i} %{!.s:%g.s}}}"
999
1000 #else
1001 /* not GAS */
1002 #define ASM_FINAL_SPEC "\
1003 %{!mgas: %{!mno-mips-tfile: \
1004 \n mips-tfile %{v*: -v} \
1005 %{K: -I %b.o~} \
1006 %{!K: %{save-temps: -I %b.o~}} \
1007 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1008 %{.s:%i} %{!.s:%g.s}}}"
1009
1010 #endif
1011 #endif /* ASM_FINAL_SPEC */
1012
1013 /* Redefinition of libraries used. Mips doesn't support normal
1014 UNIX style profiling via calling _mcount. It does offer
1015 profiling that samples the PC, so do what we can... */
1016
1017 #ifndef LIB_SPEC
1018 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1019 #endif
1020
1021 /* Extra switches sometimes passed to the linker. */
1022 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1023 will interpret it as a -b option. */
1024
1025 #ifndef LINK_SPEC
1026 #define LINK_SPEC "\
1027 %(endian_spec) \
1028 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
1029 %{bestGnum} %{shared} %{non_shared}"
1030 #endif /* LINK_SPEC defined */
1031
1032
1033 /* Specs for the compiler proper */
1034
1035 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1036 overridden by subtargets. */
1037 #ifndef SUBTARGET_CC1_SPEC
1038 #define SUBTARGET_CC1_SPEC ""
1039 #endif
1040
1041 /* Deal with historic options. */
1042 #ifndef CC1_CPU_SPEC
1043 #define CC1_CPU_SPEC "\
1044 %{!mcpu*: \
1045 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
1046 %n`-m3900' is deprecated. Use `-march=r3900' instead.\n} \
1047 %{m4650:-march=r4650 -mmad -msingle-float \
1048 %n`-m4650' is deprecated. Use `-march=r4650' instead.\n}}"
1049 #endif
1050
1051 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1052 /* Note, we will need to adjust the following if we ever find a MIPS variant
1053 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1054 that show up in this case. */
1055
1056 #ifndef CC1_SPEC
1057 #define CC1_SPEC "\
1058 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1059 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
1060 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1061 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1062 %{mips32:-mfp32 -mgp32} \
1063 %{mips64:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
1064 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
1065 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
1066 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
1067 %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
1068 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1069 %{save-temps: } \
1070 %(subtarget_cc1_spec) \
1071 %(cc1_cpu_spec)"
1072 #endif
1073
1074 /* Preprocessor specs. */
1075
1076 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1077 overridden by subtargets. */
1078 #ifndef SUBTARGET_CPP_SPEC
1079 #define SUBTARGET_CPP_SPEC ""
1080 #endif
1081
1082 #define CPP_SPEC "%(subtarget_cpp_spec)"
1083
1084 /* This macro defines names of additional specifications to put in the specs
1085 that can be used in various specifications like CC1_SPEC. Its definition
1086 is an initializer with a subgrouping for each command option.
1087
1088 Each subgrouping contains a string constant, that defines the
1089 specification name, and a string constant that used by the GNU CC driver
1090 program.
1091
1092 Do not define this macro if it does not need to do anything. */
1093
1094 #define EXTRA_SPECS \
1095 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1096 { "cc1_cpu_spec", CC1_CPU_SPEC}, \
1097 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1098 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1099 { "gas_asm_spec", GAS_ASM_SPEC }, \
1100 { "abi_gas_asm_spec", ABI_GAS_ASM_SPEC }, \
1101 { "target_asm_spec", TARGET_ASM_SPEC }, \
1102 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1103 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1104 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1105 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1106 { "endian_spec", ENDIAN_SPEC }, \
1107 SUBTARGET_EXTRA_SPECS
1108
1109 #ifndef SUBTARGET_EXTRA_SPECS
1110 #define SUBTARGET_EXTRA_SPECS
1111 #endif
1112
1113 /* If defined, this macro is an additional prefix to try after
1114 `STANDARD_EXEC_PREFIX'. */
1115
1116 #ifndef MD_EXEC_PREFIX
1117 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1118 #endif
1119
1120 #ifndef MD_STARTFILE_PREFIX
1121 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1122 #endif
1123
1124 \f
1125 /* Print subsidiary information on the compiler version in use. */
1126
1127 #define MIPS_VERSION "[AL 1.1, MM 40]"
1128
1129 #ifndef MACHINE_TYPE
1130 #define MACHINE_TYPE "BSD Mips"
1131 #endif
1132
1133 #ifndef TARGET_VERSION_INTERNAL
1134 #define TARGET_VERSION_INTERNAL(STREAM) \
1135 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1136 #endif
1137
1138 #ifndef TARGET_VERSION
1139 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1140 #endif
1141
1142 \f
1143 #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
1144 #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
1145 #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
1146
1147 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1148 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1149 #endif
1150
1151 /* By default, turn on GDB extensions. */
1152 #define DEFAULT_GDB_EXTENSIONS 1
1153
1154 /* If we are passing smuggling stabs through the MIPS ECOFF object
1155 format, put a comment in front of the .stab<x> operation so
1156 that the MIPS assembler does not choke. The mips-tfile program
1157 will correctly put the stab into the object file. */
1158
1159 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1160 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1161 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1162
1163 /* Local compiler-generated symbols must have a prefix that the assembler
1164 understands. By default, this is $, although some targets (e.g.,
1165 NetBSD-ELF) need to override this. */
1166
1167 #ifndef LOCAL_LABEL_PREFIX
1168 #define LOCAL_LABEL_PREFIX "$"
1169 #endif
1170
1171 /* By default on the mips, external symbols do not have an underscore
1172 prepended, but some targets (e.g., NetBSD) require this. */
1173
1174 #ifndef USER_LABEL_PREFIX
1175 #define USER_LABEL_PREFIX ""
1176 #endif
1177
1178 /* Forward references to tags are allowed. */
1179 #define SDB_ALLOW_FORWARD_REFERENCES
1180
1181 /* Unknown tags are also allowed. */
1182 #define SDB_ALLOW_UNKNOWN_REFERENCES
1183
1184 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1185 since the length can run past this up to a continuation point. */
1186 #undef DBX_CONTIN_LENGTH
1187 #define DBX_CONTIN_LENGTH 1500
1188
1189 /* How to renumber registers for dbx and gdb. */
1190 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1191
1192 /* The mapping from gcc register number to DWARF 2 CFA column number.
1193 This mapping does not allow for tracking register 0, since SGI's broken
1194 dwarf reader thinks column 0 is used for the frame address, but since
1195 register 0 is fixed this is not a problem. */
1196 #define DWARF_FRAME_REGNUM(REG) \
1197 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1198
1199 /* The DWARF 2 CFA column which tracks the return address. */
1200 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1201
1202 /* Before the prologue, RA lives in r31. */
1203 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1204
1205 /* Describe how we implement __builtin_eh_return. */
1206 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1207 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1208
1209 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1210 The default for this in 64-bit mode is 8, which causes problems with
1211 SFmode register saves. */
1212 #define DWARF_CIE_DATA_ALIGNMENT 4
1213
1214 /* Overrides for the COFF debug format. */
1215 #define PUT_SDB_SCL(a) \
1216 do { \
1217 extern FILE *asm_out_text_file; \
1218 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1219 } while (0)
1220
1221 #define PUT_SDB_INT_VAL(a) \
1222 do { \
1223 extern FILE *asm_out_text_file; \
1224 fprintf (asm_out_text_file, "\t.val\t"); \
1225 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1226 fprintf (asm_out_text_file, ";"); \
1227 } while (0)
1228
1229 #define PUT_SDB_VAL(a) \
1230 do { \
1231 extern FILE *asm_out_text_file; \
1232 fputs ("\t.val\t", asm_out_text_file); \
1233 output_addr_const (asm_out_text_file, (a)); \
1234 fputc (';', asm_out_text_file); \
1235 } while (0)
1236
1237 #define PUT_SDB_DEF(a) \
1238 do { \
1239 extern FILE *asm_out_text_file; \
1240 fprintf (asm_out_text_file, "\t%s.def\t", \
1241 (TARGET_GAS) ? "" : "#"); \
1242 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1243 fputc (';', asm_out_text_file); \
1244 } while (0)
1245
1246 #define PUT_SDB_PLAIN_DEF(a) \
1247 do { \
1248 extern FILE *asm_out_text_file; \
1249 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1250 (TARGET_GAS) ? "" : "#", (a)); \
1251 } while (0)
1252
1253 #define PUT_SDB_ENDEF \
1254 do { \
1255 extern FILE *asm_out_text_file; \
1256 fprintf (asm_out_text_file, "\t.endef\n"); \
1257 } while (0)
1258
1259 #define PUT_SDB_TYPE(a) \
1260 do { \
1261 extern FILE *asm_out_text_file; \
1262 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1263 } while (0)
1264
1265 #define PUT_SDB_SIZE(a) \
1266 do { \
1267 extern FILE *asm_out_text_file; \
1268 fprintf (asm_out_text_file, "\t.size\t"); \
1269 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1270 fprintf (asm_out_text_file, ";"); \
1271 } while (0)
1272
1273 #define PUT_SDB_DIM(a) \
1274 do { \
1275 extern FILE *asm_out_text_file; \
1276 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1277 } while (0)
1278
1279 #ifndef PUT_SDB_START_DIM
1280 #define PUT_SDB_START_DIM \
1281 do { \
1282 extern FILE *asm_out_text_file; \
1283 fprintf (asm_out_text_file, "\t.dim\t"); \
1284 } while (0)
1285 #endif
1286
1287 #ifndef PUT_SDB_NEXT_DIM
1288 #define PUT_SDB_NEXT_DIM(a) \
1289 do { \
1290 extern FILE *asm_out_text_file; \
1291 fprintf (asm_out_text_file, "%d,", a); \
1292 } while (0)
1293 #endif
1294
1295 #ifndef PUT_SDB_LAST_DIM
1296 #define PUT_SDB_LAST_DIM(a) \
1297 do { \
1298 extern FILE *asm_out_text_file; \
1299 fprintf (asm_out_text_file, "%d;", a); \
1300 } while (0)
1301 #endif
1302
1303 #define PUT_SDB_TAG(a) \
1304 do { \
1305 extern FILE *asm_out_text_file; \
1306 fprintf (asm_out_text_file, "\t.tag\t"); \
1307 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1308 fputc (';', asm_out_text_file); \
1309 } while (0)
1310
1311 /* For block start and end, we create labels, so that
1312 later we can figure out where the correct offset is.
1313 The normal .ent/.end serve well enough for functions,
1314 so those are just commented out. */
1315
1316 #define PUT_SDB_BLOCK_START(LINE) \
1317 do { \
1318 extern FILE *asm_out_text_file; \
1319 fprintf (asm_out_text_file, \
1320 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1321 LOCAL_LABEL_PREFIX, \
1322 sdb_label_count, \
1323 (TARGET_GAS) ? "" : "#", \
1324 LOCAL_LABEL_PREFIX, \
1325 sdb_label_count, \
1326 (LINE)); \
1327 sdb_label_count++; \
1328 } while (0)
1329
1330 #define PUT_SDB_BLOCK_END(LINE) \
1331 do { \
1332 extern FILE *asm_out_text_file; \
1333 fprintf (asm_out_text_file, \
1334 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1335 LOCAL_LABEL_PREFIX, \
1336 sdb_label_count, \
1337 (TARGET_GAS) ? "" : "#", \
1338 LOCAL_LABEL_PREFIX, \
1339 sdb_label_count, \
1340 (LINE)); \
1341 sdb_label_count++; \
1342 } while (0)
1343
1344 #define PUT_SDB_FUNCTION_START(LINE)
1345
1346 #define PUT_SDB_FUNCTION_END(LINE) \
1347 do { \
1348 extern FILE *asm_out_text_file; \
1349 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1350 } while (0)
1351
1352 #define PUT_SDB_EPILOGUE_END(NAME)
1353
1354 #define PUT_SDB_SRC_FILE(FILENAME) \
1355 do { \
1356 extern FILE *asm_out_text_file; \
1357 output_file_directive (asm_out_text_file, (FILENAME)); \
1358 } while (0)
1359
1360 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1361 sprintf ((BUFFER), ".%dfake", (NUMBER));
1362
1363 /* Correct the offset of automatic variables and arguments. Note that
1364 the MIPS debug format wants all automatic variables and arguments
1365 to be in terms of the virtual frame pointer (stack pointer before
1366 any adjustment in the function), while the MIPS 3.0 linker wants
1367 the frame pointer to be the stack pointer after the initial
1368 adjustment. */
1369
1370 #define DEBUGGER_AUTO_OFFSET(X) \
1371 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1372 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1373 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1374
1375 /* Tell collect that the object format is ECOFF */
1376 #ifndef OBJECT_FORMAT_ROSE
1377 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1378 #define EXTENDED_COFF /* ECOFF, not normal coff */
1379 #endif
1380 \f
1381 /* Target machine storage layout */
1382
1383 /* Define this if most significant bit is lowest numbered
1384 in instructions that operate on numbered bit-fields.
1385 */
1386 #define BITS_BIG_ENDIAN 0
1387
1388 /* Define this if most significant byte of a word is the lowest numbered. */
1389 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1390
1391 /* Define this if most significant word of a multiword number is the lowest. */
1392 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1393
1394 /* Define this to set the endianness to use in libgcc2.c, which can
1395 not depend on target_flags. */
1396 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1397 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1398 #else
1399 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1400 #endif
1401
1402 #define MAX_BITS_PER_WORD 64
1403
1404 /* Width of a word, in units (bytes). */
1405 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1406 #define MIN_UNITS_PER_WORD 4
1407
1408 /* For MIPS, width of a floating point register. */
1409 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1410
1411 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1412 the next available register. */
1413 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1414
1415 /* The largest size of value that can be held in floating-point registers. */
1416 #define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1417
1418 /* The number of bytes in a double. */
1419 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1420
1421 /* A C expression for the size in bits of the type `int' on the
1422 target machine. If you don't define this, the default is one
1423 word. */
1424 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1425
1426 /* Tell the preprocessor the maximum size of wchar_t. */
1427 #ifndef MAX_WCHAR_TYPE_SIZE
1428 #ifndef WCHAR_TYPE_SIZE
1429 #define MAX_WCHAR_TYPE_SIZE 64
1430 #endif
1431 #endif
1432
1433 /* A C expression for the size in bits of the type `short' on the
1434 target machine. If you don't define this, the default is half a
1435 word. (If this would be less than one storage unit, it is
1436 rounded up to one unit.) */
1437 #define SHORT_TYPE_SIZE 16
1438
1439 /* A C expression for the size in bits of the type `long' on the
1440 target machine. If you don't define this, the default is one
1441 word. */
1442 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1443 #define MAX_LONG_TYPE_SIZE 64
1444
1445 /* A C expression for the size in bits of the type `long long' on the
1446 target machine. If you don't define this, the default is two
1447 words. */
1448 #define LONG_LONG_TYPE_SIZE 64
1449
1450 /* A C expression for the size in bits of the type `float' on the
1451 target machine. If you don't define this, the default is one
1452 word. */
1453 #define FLOAT_TYPE_SIZE 32
1454
1455 /* A C expression for the size in bits of the type `double' on the
1456 target machine. If you don't define this, the default is two
1457 words. */
1458 #define DOUBLE_TYPE_SIZE 64
1459
1460 /* A C expression for the size in bits of the type `long double' on
1461 the target machine. If you don't define this, the default is two
1462 words. */
1463 #define LONG_DOUBLE_TYPE_SIZE 64
1464
1465 /* Width in bits of a pointer.
1466 See also the macro `Pmode' defined below. */
1467 #ifndef POINTER_SIZE
1468 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1469 #endif
1470
1471 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1472 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1473
1474 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1475 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1476 || mips_abi == ABI_64 \
1477 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1478
1479 /* Allocation boundary (in *bits*) for the code of a function. */
1480 #define FUNCTION_BOUNDARY 32
1481
1482 /* Alignment of field after `int : 0' in a structure. */
1483 #define EMPTY_FIELD_BOUNDARY 32
1484
1485 /* Every structure's size must be a multiple of this. */
1486 /* 8 is observed right on a DECstation and on riscos 4.02. */
1487 #define STRUCTURE_SIZE_BOUNDARY 8
1488
1489 /* There is no point aligning anything to a rounder boundary than this. */
1490 #define BIGGEST_ALIGNMENT 64
1491
1492 /* Set this nonzero if move instructions will actually fail to work
1493 when given unaligned data. */
1494 #define STRICT_ALIGNMENT 1
1495
1496 /* Define this if you wish to imitate the way many other C compilers
1497 handle alignment of bitfields and the structures that contain
1498 them.
1499
1500 The behavior is that the type written for a bitfield (`int',
1501 `short', or other integer type) imposes an alignment for the
1502 entire structure, as if the structure really did contain an
1503 ordinary field of that type. In addition, the bitfield is placed
1504 within the structure so that it would fit within such a field,
1505 not crossing a boundary for it.
1506
1507 Thus, on most machines, a bitfield whose type is written as `int'
1508 would not cross a four-byte boundary, and would force four-byte
1509 alignment for the whole structure. (The alignment used may not
1510 be four bytes; it is controlled by the other alignment
1511 parameters.)
1512
1513 If the macro is defined, its definition should be a C expression;
1514 a nonzero value for the expression enables this behavior. */
1515
1516 #define PCC_BITFIELD_TYPE_MATTERS 1
1517
1518 /* If defined, a C expression to compute the alignment given to a
1519 constant that is being placed in memory. CONSTANT is the constant
1520 and ALIGN is the alignment that the object would ordinarily have.
1521 The value of this macro is used instead of that alignment to align
1522 the object.
1523
1524 If this macro is not defined, then ALIGN is used.
1525
1526 The typical use of this macro is to increase alignment for string
1527 constants to be word aligned so that `strcpy' calls that copy
1528 constants can be done inline. */
1529
1530 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1531 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1532 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1533
1534 /* If defined, a C expression to compute the alignment for a static
1535 variable. TYPE is the data type, and ALIGN is the alignment that
1536 the object would ordinarily have. The value of this macro is used
1537 instead of that alignment to align the object.
1538
1539 If this macro is not defined, then ALIGN is used.
1540
1541 One use of this macro is to increase alignment of medium-size
1542 data to make it all fit in fewer cache lines. Another is to
1543 cause character arrays to be word-aligned so that `strcpy' calls
1544 that copy constants to character arrays can be done inline. */
1545
1546 #undef DATA_ALIGNMENT
1547 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1548 ((((ALIGN) < BITS_PER_WORD) \
1549 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1550 || TREE_CODE (TYPE) == UNION_TYPE \
1551 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1552
1553
1554 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1555
1556 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1557 || mips_abi == ABI_MEABI \
1558 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1559
1560 /* Define this macro if an argument declared as `char' or `short' in a
1561 prototype should actually be passed as an `int'. In addition to
1562 avoiding errors in certain cases of mismatch, it also makes for
1563 better code on certain machines. */
1564
1565 #define PROMOTE_PROTOTYPES 1
1566
1567 /* Define if operations between registers always perform the operation
1568 on the full register even if a narrower mode is specified. */
1569 #define WORD_REGISTER_OPERATIONS
1570
1571 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1572 will either zero-extend or sign-extend. The value of this macro should
1573 be the code that says which one of the two operations is implicitly
1574 done, NIL if none.
1575
1576 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1577 moves. All other referces are zero extended. */
1578 #define LOAD_EXTEND_OP(MODE) \
1579 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1580 ? SIGN_EXTEND : ZERO_EXTEND)
1581
1582 /* Define this macro if it is advisable to hold scalars in registers
1583 in a wider mode than that declared by the program. In such cases,
1584 the value is constrained to be within the bounds of the declared
1585 type, but kept valid in the wider mode. The signedness of the
1586 extension may differ from that of the type.
1587
1588 We promote any value smaller than SImode up to SImode. We don't
1589 want to promote to DImode when in 64 bit mode, because that would
1590 prevent us from using the faster SImode multiply and divide
1591 instructions. */
1592
1593 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1594 if (GET_MODE_CLASS (MODE) == MODE_INT \
1595 && GET_MODE_SIZE (MODE) < 4) \
1596 (MODE) = SImode;
1597
1598 /* Define this if function arguments should also be promoted using the above
1599 procedure. */
1600
1601 #define PROMOTE_FUNCTION_ARGS
1602
1603 /* Likewise, if the function return value is promoted. */
1604
1605 #define PROMOTE_FUNCTION_RETURN
1606 \f
1607 /* Standard register usage. */
1608
1609 /* Number of actual hardware registers.
1610 The hardware registers are assigned numbers for the compiler
1611 from 0 to just below FIRST_PSEUDO_REGISTER.
1612 All registers that the compiler knows about must be given numbers,
1613 even those that are not normally considered general registers.
1614
1615 On the Mips, we have 32 integer registers, 32 floating point
1616 registers, 8 condition code registers, and the special registers
1617 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1618 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1619 processor.) The 8 condition code registers are only used if
1620 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1621 represents a 64 bit value stored as two 32 bit values in the hi and
1622 lo registers; this is the result of the mult instruction. rap is a
1623 pointer to the stack where the return address reg ($31) was stored.
1624 This is needed for C++ exception handling. */
1625
1626 #define FIRST_PSEUDO_REGISTER 176
1627
1628 /* 1 for registers that have pervasive standard uses
1629 and are not available for the register allocator.
1630
1631 On the MIPS, see conventions, page D-2 */
1632
1633 /* Regarding coprocessor registers: without evidence to the contrary,
1634 it's best to assume that each coprocessor register has a unique
1635 use. This can be overridden, in, e.g., override_options() or
1636 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1637 for a particular target. */
1638
1639 #define FIXED_REGISTERS \
1640 { \
1641 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1642 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1643 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1644 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1645 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
1646 /* COP0 registers */ \
1647 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1648 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1649 /* COP2 registers */ \
1650 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1651 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1652 /* COP3 registers */ \
1653 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1654 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1655 }
1656
1657
1658 /* 1 for registers not available across function calls.
1659 These must include the FIXED_REGISTERS and also any
1660 registers that can be used without being saved.
1661 The latter must include the registers where values are returned
1662 and the register where structure-value addresses are passed.
1663 Aside from that, you can include as many other registers as you like. */
1664
1665 #define CALL_USED_REGISTERS \
1666 { \
1667 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1668 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1669 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1670 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1671 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1672 /* COP0 registers */ \
1673 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1674 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1675 /* COP2 registers */ \
1676 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1677 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1678 /* COP3 registers */ \
1679 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1680 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1681 }
1682
1683 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1684 problem which makes CALL_USED_REGISTERS *always* include
1685 all the FIXED_REGISTERS. Until this problem has been
1686 resolved this macro can be used to overcome this situation.
1687 In particular, block_propagate() requires this list
1688 be acurate, or we can remove registers which should be live.
1689 This macro is used in regs_invalidated_by_call. */
1690
1691
1692 #define CALL_REALLY_USED_REGISTERS \
1693 { /* General registers. */ \
1694 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1695 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1696 /* Floating-point registers. */ \
1697 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1698 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1699 /* Others. */ \
1700 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1701 /* COP0 registers */ \
1702 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1703 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1704 /* COP2 registers */ \
1705 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1706 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1707 /* COP3 registers */ \
1708 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1709 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1710 }
1711
1712 /* Internal macros to classify a register number as to whether it's a
1713 general purpose register, a floating point register, a
1714 multiply/divide register, or a status register. */
1715
1716 #define GP_REG_FIRST 0
1717 #define GP_REG_LAST 31
1718 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1719 #define GP_DBX_FIRST 0
1720
1721 #define FP_REG_FIRST 32
1722 #define FP_REG_LAST 63
1723 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1724 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1725
1726 #define MD_REG_FIRST 64
1727 #define MD_REG_LAST 66
1728 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1729
1730 #define ST_REG_FIRST 67
1731 #define ST_REG_LAST 74
1732 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1733
1734 #define RAP_REG_NUM 75
1735
1736 #define COP0_REG_FIRST 80
1737 #define COP0_REG_LAST 111
1738 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1739
1740 #define COP2_REG_FIRST 112
1741 #define COP2_REG_LAST 143
1742 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1743
1744 #define COP3_REG_FIRST 144
1745 #define COP3_REG_LAST 175
1746 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1747 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1748 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1749
1750 #define AT_REGNUM (GP_REG_FIRST + 1)
1751 #define HI_REGNUM (MD_REG_FIRST + 0)
1752 #define LO_REGNUM (MD_REG_FIRST + 1)
1753 #define HILO_REGNUM (MD_REG_FIRST + 2)
1754
1755 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1756 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1757 should be used instead. */
1758 #define FPSW_REGNUM ST_REG_FIRST
1759
1760 #define GP_REG_P(REGNO) \
1761 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1762 #define M16_REG_P(REGNO) \
1763 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1764 #define FP_REG_P(REGNO) \
1765 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1766 #define MD_REG_P(REGNO) \
1767 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1768 #define ST_REG_P(REGNO) \
1769 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1770 #define COP0_REG_P(REGNO) \
1771 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1772 #define COP2_REG_P(REGNO) \
1773 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1774 #define COP3_REG_P(REGNO) \
1775 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1776 #define ALL_COP_REG_P(REGNO) \
1777 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1778
1779 /* Return coprocessor number from register number. */
1780
1781 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1782 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1783 : COP3_REG_P (REGNO) ? '3' : '?')
1784
1785 /* Return number of consecutive hard regs needed starting at reg REGNO
1786 to hold something of mode MODE.
1787 This is ordinarily the length in words of a value of mode MODE
1788 but can be less for certain modes in special long registers.
1789
1790 On the MIPS, all general registers are one word long. Except on
1791 the R4000 with the FR bit set, the floating point uses register
1792 pairs, with the second register not being allocable. */
1793
1794 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1795
1796 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1797 MODE. In 32 bit mode, require that DImode and DFmode be in even
1798 registers. For DImode, this makes some of the insns easier to
1799 write, since you don't have to worry about a DImode value in
1800 registers 3 & 4, producing a result in 4 & 5.
1801
1802 To make the code simpler HARD_REGNO_MODE_OK now just references an
1803 array built in override_options. Because machmodes.h is not yet
1804 included before this file is processed, the MODE bound can't be
1805 expressed here. */
1806
1807 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1808
1809 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1810 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1811
1812 /* Value is 1 if it is a good idea to tie two pseudo registers
1813 when one has mode MODE1 and one has mode MODE2.
1814 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1815 for any hard reg, then this must be 0 for correct output. */
1816 #define MODES_TIEABLE_P(MODE1, MODE2) \
1817 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1818 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1819 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1820 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1821
1822 /* MIPS pc is not overloaded on a register. */
1823 /* #define PC_REGNUM xx */
1824
1825 /* Register to use for pushing function arguments. */
1826 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1827
1828 /* Offset from the stack pointer to the first available location. Use
1829 the default value zero. */
1830 /* #define STACK_POINTER_OFFSET 0 */
1831
1832 /* Base register for access to local variables of the function. We
1833 pretend that the frame pointer is $1, and then eliminate it to
1834 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1835 a fixed register, and will not be used for anything else. */
1836 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1837
1838 /* Temporary scratch register for use by the assembler. */
1839 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1840
1841 /* $30 is not available on the mips16, so we use $17 as the frame
1842 pointer. */
1843 #define HARD_FRAME_POINTER_REGNUM \
1844 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1845
1846 /* Value should be nonzero if functions must have frame pointers.
1847 Zero means the frame pointer need not be set up (and parms
1848 may be accessed via the stack pointer) in functions that seem suitable.
1849 This is computed in `reload', in reload1.c. */
1850 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1851
1852 /* Base register for access to arguments of the function. */
1853 #define ARG_POINTER_REGNUM GP_REG_FIRST
1854
1855 /* Fake register that holds the address on the stack of the
1856 current function's return address. */
1857 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1858
1859 /* Register in which static-chain is passed to a function. */
1860 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1861
1862 /* If the structure value address is passed in a register, then
1863 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1864 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1865
1866 /* If the structure value address is not passed in a register, define
1867 `STRUCT_VALUE' as an expression returning an RTX for the place
1868 where the address is passed. If it returns 0, the address is
1869 passed as an "invisible" first argument. */
1870 #define STRUCT_VALUE 0
1871
1872 /* Mips registers used in prologue/epilogue code when the stack frame
1873 is larger than 32K bytes. These registers must come from the
1874 scratch register set, and not used for passing and returning
1875 arguments and any other information used in the calling sequence
1876 (such as pic). Must start at 12, since t0/t3 are parameter passing
1877 registers in the 64 bit ABI. */
1878
1879 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1880 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1881
1882 /* Define this macro if it is as good or better to call a constant
1883 function address than to call an address kept in a register. */
1884 #define NO_FUNCTION_CSE 1
1885
1886 /* Define this macro if it is as good or better for a function to
1887 call itself with an explicit address than to call an address
1888 kept in a register. */
1889 #define NO_RECURSIVE_FUNCTION_CSE 1
1890
1891 /* The register number of the register used to address a table of
1892 static data addresses in memory. In some cases this register is
1893 defined by a processor's "application binary interface" (ABI).
1894 When this macro is defined, RTL is generated for this register
1895 once, as with the stack pointer and frame pointer registers. If
1896 this macro is not defined, it is up to the machine-dependent
1897 files to allocate such a register (if necessary). */
1898 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1899
1900 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1901 \f
1902 /* Define the classes of registers for register constraints in the
1903 machine description. Also define ranges of constants.
1904
1905 One of the classes must always be named ALL_REGS and include all hard regs.
1906 If there is more than one class, another class must be named NO_REGS
1907 and contain no registers.
1908
1909 The name GENERAL_REGS must be the name of a class (or an alias for
1910 another name such as ALL_REGS). This is the class of registers
1911 that is allowed by "g" or "r" in a register constraint.
1912 Also, registers outside this class are allocated only when
1913 instructions express preferences for them.
1914
1915 The classes must be numbered in nondecreasing order; that is,
1916 a larger-numbered class must never be contained completely
1917 in a smaller-numbered class.
1918
1919 For any two classes, it is very desirable that there be another
1920 class that represents their union. */
1921
1922 enum reg_class
1923 {
1924 NO_REGS, /* no registers in set */
1925 M16_NA_REGS, /* mips16 regs not used to pass args */
1926 M16_REGS, /* mips16 directly accessible registers */
1927 T_REG, /* mips16 T register ($24) */
1928 M16_T_REGS, /* mips16 registers plus T register */
1929 GR_REGS, /* integer registers */
1930 FP_REGS, /* floating point registers */
1931 HI_REG, /* hi register */
1932 LO_REG, /* lo register */
1933 HILO_REG, /* hilo register pair for 64 bit mode mult */
1934 MD_REGS, /* multiply/divide registers (hi/lo) */
1935 COP0_REGS, /* generic coprocessor classes */
1936 COP2_REGS,
1937 COP3_REGS,
1938 HI_AND_GR_REGS, /* union classes */
1939 LO_AND_GR_REGS,
1940 HILO_AND_GR_REGS,
1941 HI_AND_FP_REGS,
1942 COP0_AND_GR_REGS,
1943 COP2_AND_GR_REGS,
1944 COP3_AND_GR_REGS,
1945 ALL_COP_REGS,
1946 ALL_COP_AND_GR_REGS,
1947 ST_REGS, /* status registers (fp status) */
1948 ALL_REGS, /* all registers */
1949 LIM_REG_CLASSES /* max value + 1 */
1950 };
1951
1952 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1953
1954 #define GENERAL_REGS GR_REGS
1955
1956 /* An initializer containing the names of the register classes as C
1957 string constants. These names are used in writing some of the
1958 debugging dumps. */
1959
1960 #define REG_CLASS_NAMES \
1961 { \
1962 "NO_REGS", \
1963 "M16_NA_REGS", \
1964 "M16_REGS", \
1965 "T_REG", \
1966 "M16_T_REGS", \
1967 "GR_REGS", \
1968 "FP_REGS", \
1969 "HI_REG", \
1970 "LO_REG", \
1971 "HILO_REG", \
1972 "MD_REGS", \
1973 /* coprocessor registers */ \
1974 "COP0_REGS", \
1975 "COP2_REGS", \
1976 "COP3_REGS", \
1977 "HI_AND_GR_REGS", \
1978 "LO_AND_GR_REGS", \
1979 "HILO_AND_GR_REGS", \
1980 "HI_AND_FP_REGS", \
1981 "COP0_AND_GR_REGS", \
1982 "COP2_AND_GR_REGS", \
1983 "COP3_AND_GR_REGS", \
1984 "ALL_COP_REGS", \
1985 "ALL_COP_AND_GR_REGS", \
1986 "ST_REGS", \
1987 "ALL_REGS" \
1988 }
1989
1990 /* An initializer containing the contents of the register classes,
1991 as integers which are bit masks. The Nth integer specifies the
1992 contents of class N. The way the integer MASK is interpreted is
1993 that register R is in the class if `MASK & (1 << R)' is 1.
1994
1995 When the machine has more than 32 registers, an integer does not
1996 suffice. Then the integers are replaced by sub-initializers,
1997 braced groupings containing several integers. Each
1998 sub-initializer must be suitable as an initializer for the type
1999 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2000
2001 #define REG_CLASS_CONTENTS \
2002 { \
2003 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2004 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2005 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2006 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2007 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2008 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2009 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2010 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2011 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2012 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2013 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2014 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2015 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2016 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2017 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2018 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2019 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2020 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2021 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2022 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2023 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2024 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2025 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2026 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2027 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2028 }
2029
2030
2031 /* A C expression whose value is a register class containing hard
2032 register REGNO. In general there is more that one such class;
2033 choose a class which is "minimal", meaning that no smaller class
2034 also contains the register. */
2035
2036 extern const enum reg_class mips_regno_to_class[];
2037
2038 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2039
2040 /* A macro whose definition is the name of the class to which a
2041 valid base register must belong. A base register is one used in
2042 an address which is the register value plus a displacement. */
2043
2044 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2045
2046 /* A macro whose definition is the name of the class to which a
2047 valid index register must belong. An index register is one used
2048 in an address where its value is either multiplied by a scale
2049 factor or added to another register (as well as added to a
2050 displacement). */
2051
2052 #define INDEX_REG_CLASS NO_REGS
2053
2054 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2055 registers explicitly used in the rtl to be used as spill registers
2056 but prevents the compiler from extending the lifetime of these
2057 registers. */
2058
2059 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2060
2061 /* This macro is used later on in the file. */
2062 #define GR_REG_CLASS_P(CLASS) \
2063 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2064 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2065
2066 /* This macro is also used later on in the file. */
2067 #define COP_REG_CLASS_P(CLASS) \
2068 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2069
2070 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2071 is the default value (allocate the registers in numeric order). We
2072 define it just so that we can override it for the mips16 target in
2073 ORDER_REGS_FOR_LOCAL_ALLOC. */
2074
2075 #define REG_ALLOC_ORDER \
2076 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2077 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2078 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2079 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2080 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2081 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2082 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2083 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2084 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2085 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2086 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2087 }
2088
2089 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2090 to be rearranged based on a particular function. On the mips16, we
2091 want to allocate $24 (T_REG) before other registers for
2092 instructions for which it is possible. */
2093
2094 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2095
2096 /* REGISTER AND CONSTANT CLASSES */
2097
2098 /* Get reg_class from a letter such as appears in the machine
2099 description.
2100
2101 DEFINED REGISTER CLASSES:
2102
2103 'd' General (aka integer) registers
2104 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2105 'y' General registers (in both mips16 and non mips16 mode)
2106 'e' mips16 non argument registers (M16_NA_REGS)
2107 't' mips16 temporary register ($24)
2108 'f' Floating point registers
2109 'h' Hi register
2110 'l' Lo register
2111 'x' Multiply/divide registers
2112 'a' HILO_REG
2113 'z' FP Status register
2114 'B' Cop0 register
2115 'C' Cop2 register
2116 'D' Cop3 register
2117 'b' All registers */
2118
2119 extern enum reg_class mips_char_to_class[256];
2120
2121 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2122
2123 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2124 string can be used to stand for particular ranges of immediate
2125 operands. This macro defines what the ranges are. C is the
2126 letter, and VALUE is a constant value. Return 1 if VALUE is
2127 in the range specified by C. */
2128
2129 /* For MIPS:
2130
2131 `I' is used for the range of constants an arithmetic insn can
2132 actually contain (16 bits signed integers).
2133
2134 `J' is used for the range which is just zero (ie, $r0).
2135
2136 `K' is used for the range of constants a logical insn can actually
2137 contain (16 bit zero-extended integers).
2138
2139 `L' is used for the range of constants that be loaded with lui
2140 (ie, the bottom 16 bits are zero).
2141
2142 `M' is used for the range of constants that take two words to load
2143 (ie, not matched by `I', `K', and `L').
2144
2145 `N' is used for negative 16 bit constants other than -65536.
2146
2147 `O' is a 15 bit signed integer.
2148
2149 `P' is used for positive 16 bit constants. */
2150
2151 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2152 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2153
2154 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2155 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2156 : (C) == 'J' ? ((VALUE) == 0) \
2157 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2158 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2159 && (((VALUE) & ~2147483647) == 0 \
2160 || ((VALUE) & ~2147483647) == ~2147483647)) \
2161 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2162 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2163 && (((VALUE) & 0x0000ffff) != 0 \
2164 || (((VALUE) & ~2147483647) != 0 \
2165 && ((VALUE) & ~2147483647) != ~2147483647))) \
2166 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2167 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2168 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2169 : 0)
2170
2171 /* Similar, but for floating constants, and defining letters G and H.
2172 Here VALUE is the CONST_DOUBLE rtx itself. */
2173
2174 /* For Mips
2175
2176 'G' : Floating point 0 */
2177
2178 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2179 ((C) == 'G' \
2180 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2181
2182 /* Letters in the range `Q' through `U' may be defined in a
2183 machine-dependent fashion to stand for arbitrary operand types.
2184 The machine description macro `EXTRA_CONSTRAINT' is passed the
2185 operand as its first argument and the constraint letter as its
2186 second operand.
2187
2188 `Q' is for mips16 GP relative constants
2189 `R' is for memory references which take 1 word for the instruction.
2190 `T' is for memory addresses that can be used to load two words. */
2191
2192 #define EXTRA_CONSTRAINT(OP,CODE) \
2193 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2194 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2195 && mips16_gp_offset_p (OP)) \
2196 : (GET_CODE (OP) != MEM) ? FALSE \
2197 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2198 : FALSE)
2199
2200 /* Given an rtx X being reloaded into a reg required to be
2201 in class CLASS, return the class of reg to actually use.
2202 In general this is just CLASS; but on some machines
2203 in some cases it is preferable to use a more restrictive class. */
2204
2205 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2206 ((CLASS) != ALL_REGS \
2207 ? (! TARGET_MIPS16 \
2208 ? (CLASS) \
2209 : ((CLASS) != GR_REGS \
2210 ? (CLASS) \
2211 : M16_REGS)) \
2212 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2213 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2214 ? (TARGET_SOFT_FLOAT \
2215 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2216 : FP_REGS) \
2217 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2218 || GET_MODE (X) == VOIDmode) \
2219 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2220 : (CLASS))))
2221
2222 /* Certain machines have the property that some registers cannot be
2223 copied to some other registers without using memory. Define this
2224 macro on those machines to be a C expression that is non-zero if
2225 objects of mode MODE in registers of CLASS1 can only be copied to
2226 registers of class CLASS2 by storing a register of CLASS1 into
2227 memory and loading that memory location into a register of CLASS2.
2228
2229 Do not define this macro if its value would always be zero. */
2230 #if 0
2231 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2232 ((!TARGET_DEBUG_H_MODE \
2233 && GET_MODE_CLASS (MODE) == MODE_INT \
2234 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2235 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2236 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2237 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2238 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2239 #endif
2240 /* The HI and LO registers can only be reloaded via the general
2241 registers. Condition code registers can only be loaded to the
2242 general registers, and from the floating point registers. */
2243
2244 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2245 mips_secondary_reload_class (CLASS, MODE, X, 1)
2246 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2247 mips_secondary_reload_class (CLASS, MODE, X, 0)
2248
2249 /* Return the maximum number of consecutive registers
2250 needed to represent mode MODE in a register of class CLASS. */
2251
2252 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2253
2254 /* If defined, gives a class of registers that cannot be used as the
2255 operand of a SUBREG that changes the mode of the object illegally.
2256 When FP regs are larger than integer regs... Er, anyone remember what
2257 goes wrong?
2258
2259 In little-endian mode, the hi-lo registers are numbered backwards,
2260 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
2261 word as intended. */
2262
2263 #define CLASS_CANNOT_CHANGE_MODE \
2264 (TARGET_BIG_ENDIAN \
2265 ? (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS) \
2266 : (TARGET_FLOAT64 && ! TARGET_64BIT ? HI_AND_FP_REGS : HI_REG))
2267
2268 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2269
2270 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2271 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2272 \f
2273 /* Stack layout; function entry, exit and calling. */
2274
2275 /* Define this if pushing a word on the stack
2276 makes the stack pointer a smaller address. */
2277 #define STACK_GROWS_DOWNWARD
2278
2279 /* Define this if the nominal address of the stack frame
2280 is at the high-address end of the local variables;
2281 that is, each additional local variable allocated
2282 goes at a more negative offset in the frame. */
2283 /* #define FRAME_GROWS_DOWNWARD */
2284
2285 /* Offset within stack frame to start allocating local variables at.
2286 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2287 first local allocated. Otherwise, it is the offset to the BEGINNING
2288 of the first local allocated. */
2289 #define STARTING_FRAME_OFFSET \
2290 (current_function_outgoing_args_size \
2291 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2292
2293 /* Offset from the stack pointer register to an item dynamically
2294 allocated on the stack, e.g., by `alloca'.
2295
2296 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2297 length of the outgoing arguments. The default is correct for most
2298 machines. See `function.c' for details.
2299
2300 The MIPS ABI states that functions which dynamically allocate the
2301 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2302 we are trying to create a second frame pointer to the function, so
2303 allocate some stack space to make it happy.
2304
2305 However, the linker currently complains about linking any code that
2306 dynamically allocates stack space, and there seems to be a bug in
2307 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2308
2309 #if 0
2310 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2311 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2312 ? 4*UNITS_PER_WORD \
2313 : current_function_outgoing_args_size)
2314 #endif
2315
2316 /* The return address for the current frame is in r31 if this is a leaf
2317 function. Otherwise, it is on the stack. It is at a variable offset
2318 from sp/fp/ap, so we define a fake hard register rap which is a
2319 poiner to the return address on the stack. This always gets eliminated
2320 during reload to be either the frame pointer or the stack pointer plus
2321 an offset. */
2322
2323 /* ??? This definition fails for leaf functions. There is currently no
2324 general solution for this problem. */
2325
2326 /* ??? There appears to be no way to get the return address of any previous
2327 frame except by disassembling instructions in the prologue/epilogue.
2328 So currently we support only the current frame. */
2329
2330 #define RETURN_ADDR_RTX(count, frame) \
2331 (((count) == 0) \
2332 ? (leaf_function_p () \
2333 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
2334 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
2335 RETURN_ADDRESS_POINTER_REGNUM))) \
2336 : (rtx) 0)
2337
2338 /* Since the mips16 ISA mode is encoded in the least-significant bit
2339 of the address, mask it off return addresses for purposes of
2340 finding exception handling regions. */
2341
2342 #define MASK_RETURN_ADDR GEN_INT (-2)
2343
2344 /* Similarly, don't use the least-significant bit to tell pointers to
2345 code from vtable index. */
2346
2347 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2348
2349 /* Structure to be filled in by compute_frame_size with register
2350 save masks, and offsets for the current function. */
2351
2352 struct mips_frame_info
2353 {
2354 long total_size; /* # bytes that the entire frame takes up */
2355 long var_size; /* # bytes that variables take up */
2356 long args_size; /* # bytes that outgoing arguments take up */
2357 long extra_size; /* # bytes of extra gunk */
2358 int gp_reg_size; /* # bytes needed to store gp regs */
2359 int fp_reg_size; /* # bytes needed to store fp regs */
2360 long mask; /* mask of saved gp registers */
2361 long fmask; /* mask of saved fp registers */
2362 long gp_save_offset; /* offset from vfp to store gp registers */
2363 long fp_save_offset; /* offset from vfp to store fp registers */
2364 long gp_sp_offset; /* offset from new sp to store gp registers */
2365 long fp_sp_offset; /* offset from new sp to store fp registers */
2366 int initialized; /* != 0 if frame size already calculated */
2367 int num_gp; /* number of gp registers saved */
2368 int num_fp; /* number of fp registers saved */
2369 long insns_len; /* length of insns; mips16 only */
2370 };
2371
2372 extern struct mips_frame_info current_frame_info;
2373
2374 /* If defined, this macro specifies a table of register pairs used to
2375 eliminate unneeded registers that point into the stack frame. If
2376 it is not defined, the only elimination attempted by the compiler
2377 is to replace references to the frame pointer with references to
2378 the stack pointer.
2379
2380 The definition of this macro is a list of structure
2381 initializations, each of which specifies an original and
2382 replacement register.
2383
2384 On some machines, the position of the argument pointer is not
2385 known until the compilation is completed. In such a case, a
2386 separate hard register must be used for the argument pointer.
2387 This register can be eliminated by replacing it with either the
2388 frame pointer or the argument pointer, depending on whether or not
2389 the frame pointer has been eliminated.
2390
2391 In this case, you might specify:
2392 #define ELIMINABLE_REGS \
2393 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2394 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2395 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2396
2397 Note that the elimination of the argument pointer with the stack
2398 pointer is specified first since that is the preferred elimination.
2399
2400 The eliminations to $17 are only used on the mips16. See the
2401 definition of HARD_FRAME_POINTER_REGNUM. */
2402
2403 #define ELIMINABLE_REGS \
2404 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2405 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2406 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2407 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2408 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2409 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2410 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2411 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2412 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2413
2414 /* A C expression that returns non-zero if the compiler is allowed to
2415 try to replace register number FROM-REG with register number
2416 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2417 defined, and will usually be the constant 1, since most of the
2418 cases preventing register elimination are things that the compiler
2419 already knows about.
2420
2421 When not in mips16 and mips64, we can always eliminate to the
2422 frame pointer. We can eliminate to the stack pointer unless
2423 a frame pointer is needed. In mips16 mode, we need a frame
2424 pointer for a large frame; otherwise, reload may be unable
2425 to compute the address of a local variable, since there is
2426 no way to add a large constant to the stack pointer
2427 without using a temporary register.
2428
2429 In mips16, for some instructions (eg lwu), we can't eliminate the
2430 frame pointer for the stack pointer. These instructions are
2431 only generated in TARGET_64BIT mode.
2432 */
2433
2434 #define CAN_ELIMINATE(FROM, TO) \
2435 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
2436 && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
2437 || (TO) == HARD_FRAME_POINTER_REGNUM)) \
2438 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2439 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2440 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2441 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2442 && (! TARGET_MIPS16 \
2443 || compute_frame_size (get_frame_size ()) < 32768)))))
2444
2445 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2446 specifies the initial difference between the specified pair of
2447 registers. This macro must be defined if `ELIMINABLE_REGS' is
2448 defined. */
2449
2450 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2451 { compute_frame_size (get_frame_size ()); \
2452 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2453 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2454 (OFFSET) = - current_function_outgoing_args_size; \
2455 else if ((FROM) == FRAME_POINTER_REGNUM) \
2456 (OFFSET) = 0; \
2457 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2458 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2459 (OFFSET) = (current_frame_info.total_size \
2460 - current_function_outgoing_args_size \
2461 - ((mips_abi != ABI_32 \
2462 && mips_abi != ABI_O64 \
2463 && mips_abi != ABI_EABI) \
2464 ? current_function_pretend_args_size \
2465 : 0)); \
2466 else if ((FROM) == ARG_POINTER_REGNUM) \
2467 (OFFSET) = (current_frame_info.total_size \
2468 - ((mips_abi != ABI_32 \
2469 && mips_abi != ABI_O64 \
2470 && mips_abi != ABI_EABI) \
2471 ? current_function_pretend_args_size \
2472 : 0)); \
2473 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2474 so we must add 4 bytes to the offset to get the right value. */ \
2475 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2476 { \
2477 (OFFSET) = current_frame_info.gp_sp_offset \
2478 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2479 * (BYTES_BIG_ENDIAN != 0)); \
2480 if (TARGET_MIPS16 && (TO) != STACK_POINTER_REGNUM) \
2481 (OFFSET) -= current_function_outgoing_args_size; \
2482 } \
2483 else \
2484 abort(); \
2485 }
2486
2487 /* If we generate an insn to push BYTES bytes,
2488 this says how many the stack pointer really advances by.
2489 On the VAX, sp@- in a byte insn really pushes a word. */
2490
2491 /* #define PUSH_ROUNDING(BYTES) 0 */
2492
2493 /* If defined, the maximum amount of space required for outgoing
2494 arguments will be computed and placed into the variable
2495 `current_function_outgoing_args_size'. No space will be pushed
2496 onto the stack for each call; instead, the function prologue
2497 should increase the stack frame size by this amount.
2498
2499 It is not proper to define both `PUSH_ROUNDING' and
2500 `ACCUMULATE_OUTGOING_ARGS'. */
2501 #define ACCUMULATE_OUTGOING_ARGS 1
2502
2503 /* Offset from the argument pointer register to the first argument's
2504 address. On some machines it may depend on the data type of the
2505 function.
2506
2507 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2508 the first argument's address.
2509
2510 On the MIPS, we must skip the first argument position if we are
2511 returning a structure or a union, to account for its address being
2512 passed in $4. However, at the current time, this produces a compiler
2513 that can't bootstrap, so comment it out for now. */
2514
2515 #if 0
2516 #define FIRST_PARM_OFFSET(FNDECL) \
2517 (FNDECL != 0 \
2518 && TREE_TYPE (FNDECL) != 0 \
2519 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2520 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2521 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2522 ? UNITS_PER_WORD \
2523 : 0)
2524 #else
2525 #define FIRST_PARM_OFFSET(FNDECL) 0
2526 #endif
2527
2528 /* When a parameter is passed in a register, stack space is still
2529 allocated for it. For the MIPS, stack space must be allocated, cf
2530 Asm Lang Prog Guide page 7-8.
2531
2532 BEWARE that some space is also allocated for non existing arguments
2533 in register. In case an argument list is of form GF used registers
2534 are a0 (a2,a3), but we should push over a1... */
2535
2536 #define REG_PARM_STACK_SPACE(FNDECL) \
2537 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2538
2539 /* Define this if it is the responsibility of the caller to
2540 allocate the area reserved for arguments passed in registers.
2541 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2542 of this macro is to determine whether the space is included in
2543 `current_function_outgoing_args_size'. */
2544 #define OUTGOING_REG_PARM_STACK_SPACE
2545
2546 /* Align stack frames on 64 bits (Double Word ). */
2547 #ifndef STACK_BOUNDARY
2548 #define STACK_BOUNDARY 64
2549 #endif
2550
2551 /* Make sure 4 words are always allocated on the stack. */
2552
2553 #ifndef STACK_ARGS_ADJUST
2554 #define STACK_ARGS_ADJUST(SIZE) \
2555 { \
2556 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2557 SIZE.constant = 4 * UNITS_PER_WORD; \
2558 }
2559 #endif
2560
2561 \f
2562 /* A C expression that should indicate the number of bytes of its
2563 own arguments that a function pops on returning, or 0
2564 if the function pops no arguments and the caller must therefore
2565 pop them all after the function returns.
2566
2567 FUNDECL is the declaration node of the function (as a tree).
2568
2569 FUNTYPE is a C variable whose value is a tree node that
2570 describes the function in question. Normally it is a node of
2571 type `FUNCTION_TYPE' that describes the data type of the function.
2572 From this it is possible to obtain the data types of the value
2573 and arguments (if known).
2574
2575 When a call to a library function is being considered, FUNTYPE
2576 will contain an identifier node for the library function. Thus,
2577 if you need to distinguish among various library functions, you
2578 can do so by their names. Note that "library function" in this
2579 context means a function used to perform arithmetic, whose name
2580 is known specially in the compiler and was not mentioned in the
2581 C code being compiled.
2582
2583 STACK-SIZE is the number of bytes of arguments passed on the
2584 stack. If a variable number of bytes is passed, it is zero, and
2585 argument popping will always be the responsibility of the
2586 calling function. */
2587
2588 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2589
2590
2591 /* Symbolic macros for the registers used to return integer and floating
2592 point values. */
2593
2594 #define GP_RETURN (GP_REG_FIRST + 2)
2595 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2596
2597 /* Symbolic macros for the first/last argument registers. */
2598
2599 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2600 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2601 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2602 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2603
2604 #define MAX_ARGS_IN_REGISTERS 4
2605
2606 /* Define how to find the value returned by a library function
2607 assuming the value has mode MODE. Because we define
2608 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2609 PROMOTE_MODE does. */
2610
2611 #define LIBCALL_VALUE(MODE) \
2612 mips_function_value (NULL_TREE, NULL, (MODE))
2613
2614 /* Define how to find the value returned by a function.
2615 VALTYPE is the data type of the value (as a tree).
2616 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2617 otherwise, FUNC is 0. */
2618
2619 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2620 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2621
2622 /* 1 if N is a possible register number for a function value.
2623 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2624 Currently, R2 and F0 are only implemented here (C has no complex type) */
2625
2626 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2627
2628 /* 1 if N is a possible register number for function argument passing.
2629 We have no FP argument registers when soft-float. When FP registers
2630 are 32 bits, we can't directly reference the odd numbered ones. */
2631 /* For o64 we should be checking the mode for SFmode as well. */
2632
2633 #define FUNCTION_ARG_REGNO_P(N) \
2634 ((((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2635 || ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST \
2636 && (((N) % FP_INC) == 0 \
2637 && (! mips_abi == ABI_O64))) \
2638 && !fixed_regs[N]))
2639
2640 /* A C expression which can inhibit the returning of certain function
2641 values in registers, based on the type of value. A nonzero value says
2642 to return the function value in memory, just as large structures are
2643 always returned. Here TYPE will be a C expression of type
2644 `tree', representing the data type of the value.
2645
2646 Note that values of mode `BLKmode' must be explicitly
2647 handled by this macro. Also, the option `-fpcc-struct-return'
2648 takes effect regardless of this macro. On most systems, it is
2649 possible to leave the macro undefined; this causes a default
2650 definition to be used, whose value is the constant 1 for BLKmode
2651 values, and 0 otherwise.
2652
2653 GCC normally converts 1 byte structures into chars, 2 byte
2654 structs into shorts, and 4 byte structs into ints, and returns
2655 them this way. Defining the following macro overrides this,
2656 to give us MIPS cc compatibility. */
2657
2658 #define RETURN_IN_MEMORY(TYPE) \
2659 mips_return_in_memory (TYPE)
2660
2661 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2662 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2663 (TYPE), (NO_RTL))
2664 \f
2665
2666 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2667
2668 \f
2669 /* Define a data type for recording info about an argument list
2670 during the scan of that argument list. This data type should
2671 hold all necessary information about the function itself
2672 and about the args processed so far, enough to enable macros
2673 such as FUNCTION_ARG to determine where the next arg should go.
2674
2675 This structure has to cope with two different argument allocation
2676 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2677 first N words go in registers and the rest go on the stack. If I < N,
2678 the Ith word might go in Ith integer argument register or the
2679 Ith floating-point one. In some cases, it has to go in both (see
2680 function_arg). For these ABIs, we only need to remember the number
2681 of words passed so far.
2682
2683 The EABI instead allocates the integer and floating-point arguments
2684 separately. The first N words of FP arguments go in FP registers,
2685 the rest go on the stack. Likewise, the first N words of the other
2686 arguments go in integer registers, and the rest go on the stack. We
2687 need to maintain three counts: the number of integer registers used,
2688 the number of floating-point registers used, and the number of words
2689 passed on the stack.
2690
2691 We could keep separate information for the two ABIs (a word count for
2692 the standard ABIs, and three separate counts for the EABI). But it
2693 seems simpler to view the standard ABIs as forms of EABI that do not
2694 allocate floating-point registers.
2695
2696 So for the standard ABIs, the first N words are allocated to integer
2697 registers, and function_arg decides on an argument-by-argument basis
2698 whether that argument should really go in an integer register, or in
2699 a floating-point one. */
2700
2701 typedef struct mips_args {
2702 /* Always true for varargs functions. Otherwise true if at least
2703 one argument has been passed in an integer register. */
2704 int gp_reg_found;
2705
2706 /* The number of arguments seen so far. */
2707 unsigned int arg_number;
2708
2709 /* For EABI, the number of integer registers used so far. For other
2710 ABIs, the number of words passed in registers (whether integer
2711 or floating-point). */
2712 unsigned int num_gprs;
2713
2714 /* For EABI, the number of floating-point registers used so far. */
2715 unsigned int num_fprs;
2716
2717 /* The number of words passed on the stack. */
2718 unsigned int stack_words;
2719
2720 /* On the mips16, we need to keep track of which floating point
2721 arguments were passed in general registers, but would have been
2722 passed in the FP regs if this were a 32 bit function, so that we
2723 can move them to the FP regs if we wind up calling a 32 bit
2724 function. We record this information in fp_code, encoded in base
2725 four. A zero digit means no floating point argument, a one digit
2726 means an SFmode argument, and a two digit means a DFmode argument,
2727 and a three digit is not used. The low order digit is the first
2728 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2729 an SFmode argument. ??? A more sophisticated approach will be
2730 needed if MIPS_ABI != ABI_32. */
2731 int fp_code;
2732
2733 /* True if the function has a prototype. */
2734 int prototype;
2735
2736 /* When a structure does not take up a full register, the argument
2737 should sometimes be shifted left so that it occupies the high part
2738 of the register. These two fields describe an array of ashl
2739 patterns for doing this. See function_arg_advance, which creates
2740 the shift patterns, and function_arg, which returns them when given
2741 a VOIDmode argument. */
2742 unsigned int num_adjusts;
2743 rtx adjust[MAX_ARGS_IN_REGISTERS];
2744 } CUMULATIVE_ARGS;
2745
2746 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2747 for a call to a function whose data type is FNTYPE.
2748 For a library call, FNTYPE is 0.
2749
2750 */
2751
2752 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2753 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2754
2755 /* Update the data in CUM to advance over an argument
2756 of mode MODE and data type TYPE.
2757 (TYPE is null for libcalls where that information may not be available.) */
2758
2759 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2760 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2761
2762 /* Determine where to put an argument to a function.
2763 Value is zero to push the argument on the stack,
2764 or a hard register in which to store the argument.
2765
2766 MODE is the argument's machine mode.
2767 TYPE is the data type of the argument (as a tree).
2768 This is null for libcalls where that information may
2769 not be available.
2770 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2771 the preceding args and about the function being called.
2772 NAMED is nonzero if this argument is a named parameter
2773 (otherwise it is an extra parameter matching an ellipsis). */
2774
2775 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2776 function_arg( &CUM, MODE, TYPE, NAMED)
2777
2778 /* For an arg passed partly in registers and partly in memory,
2779 this is the number of registers used.
2780 For args passed entirely in registers or entirely in memory, zero. */
2781
2782 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2783 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2784
2785 /* If defined, a C expression that gives the alignment boundary, in
2786 bits, of an argument with the specified mode and type. If it is
2787 not defined, `PARM_BOUNDARY' is used for all arguments. */
2788
2789 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2790 (((TYPE) != 0) \
2791 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2792 ? PARM_BOUNDARY \
2793 : TYPE_ALIGN(TYPE)) \
2794 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2795 ? PARM_BOUNDARY \
2796 : GET_MODE_ALIGNMENT(MODE)))
2797
2798 /* True if using EABI and varargs can be passed in floating-point
2799 registers. Under these conditions, we need a more complex form
2800 of va_list, which tracks GPR, FPR and stack arguments separately. */
2801 #define EABI_FLOAT_VARARGS_P \
2802 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2803
2804 \f
2805 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2806
2807 #define MUST_SAVE_REGISTER(regno) \
2808 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2809 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2810 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2811
2812 /* ALIGN FRAMES on double word boundaries */
2813 #ifndef MIPS_STACK_ALIGN
2814 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2815 #endif
2816
2817 \f
2818 /* Define the `__builtin_va_list' type for the ABI. */
2819 #define BUILD_VA_LIST_TYPE(VALIST) \
2820 (VALIST) = mips_build_va_list ()
2821
2822 /* Implement `va_start' for varargs and stdarg. */
2823 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2824 mips_va_start (stdarg, valist, nextarg)
2825
2826 /* Implement `va_arg'. */
2827 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2828 mips_va_arg (valist, type)
2829 \f
2830 /* Output assembler code to FILE to increment profiler label # LABELNO
2831 for profiling a function entry. */
2832
2833 #define FUNCTION_PROFILER(FILE, LABELNO) \
2834 { \
2835 if (TARGET_MIPS16) \
2836 sorry ("mips16 function profiling"); \
2837 fprintf (FILE, "\t.set\tnoat\n"); \
2838 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2839 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2840 fprintf (FILE, \
2841 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2842 TARGET_64BIT ? "dsubu" : "subu", \
2843 reg_names[STACK_POINTER_REGNUM], \
2844 reg_names[STACK_POINTER_REGNUM], \
2845 Pmode == DImode ? 16 : 8); \
2846 fprintf (FILE, "\tjal\t_mcount\n"); \
2847 fprintf (FILE, "\t.set\tat\n"); \
2848 }
2849
2850 /* Define this macro if the code for function profiling should come
2851 before the function prologue. Normally, the profiling code comes
2852 after. */
2853
2854 /* #define PROFILE_BEFORE_PROLOGUE */
2855
2856 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2857 the stack pointer does not matter. The value is tested only in
2858 functions that have frame pointers.
2859 No definition is equivalent to always zero. */
2860
2861 #define EXIT_IGNORE_STACK 1
2862
2863 \f
2864 /* A C statement to output, on the stream FILE, assembler code for a
2865 block of data that contains the constant parts of a trampoline.
2866 This code should not include a label--the label is taken care of
2867 automatically. */
2868
2869 #define TRAMPOLINE_TEMPLATE(STREAM) \
2870 { \
2871 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2872 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2873 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2874 if (Pmode == DImode) \
2875 { \
2876 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2877 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2878 } \
2879 else \
2880 { \
2881 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2882 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2883 } \
2884 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2885 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2886 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2887 if (Pmode == DImode) \
2888 { \
2889 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2890 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2891 } \
2892 else \
2893 { \
2894 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2895 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2896 } \
2897 }
2898
2899 /* A C expression for the size in bytes of the trampoline, as an
2900 integer. */
2901
2902 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2903
2904 /* Alignment required for trampolines, in bits. */
2905
2906 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2907
2908 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2909 program and data caches. */
2910
2911 #ifndef CACHE_FLUSH_FUNC
2912 #define CACHE_FLUSH_FUNC "_flush_cache"
2913 #endif
2914
2915 /* A C statement to initialize the variable parts of a trampoline.
2916 ADDR is an RTX for the address of the trampoline; FNADDR is an
2917 RTX for the address of the nested function; STATIC_CHAIN is an
2918 RTX for the static chain value that should be passed to the
2919 function when it is called. */
2920
2921 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2922 { \
2923 rtx addr = ADDR; \
2924 if (Pmode == DImode) \
2925 { \
2926 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2927 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2928 } \
2929 else \
2930 { \
2931 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2932 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2933 } \
2934 \
2935 /* Flush both caches. We need to flush the data cache in case \
2936 the system has a write-back cache. */ \
2937 /* ??? Should check the return value for errors. */ \
2938 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2939 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2940 0, VOIDmode, 3, addr, Pmode, \
2941 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2942 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2943 }
2944 \f
2945 /* Addressing modes, and classification of registers for them. */
2946
2947 /* #define HAVE_POST_INCREMENT 0 */
2948 /* #define HAVE_POST_DECREMENT 0 */
2949
2950 /* #define HAVE_PRE_DECREMENT 0 */
2951 /* #define HAVE_PRE_INCREMENT 0 */
2952
2953 /* These assume that REGNO is a hard or pseudo reg number.
2954 They give nonzero only if REGNO is a hard reg of the suitable class
2955 or a pseudo reg currently allocated to a suitable hard reg.
2956 These definitions are NOT overridden anywhere. */
2957
2958 #define BASE_REG_P(regno, mode) \
2959 (TARGET_MIPS16 \
2960 ? (M16_REG_P (regno) \
2961 || (regno) == FRAME_POINTER_REGNUM \
2962 || (regno) == ARG_POINTER_REGNUM \
2963 || ((regno) == STACK_POINTER_REGNUM \
2964 && (GET_MODE_SIZE (mode) == 4 \
2965 || GET_MODE_SIZE (mode) == 8))) \
2966 : GP_REG_P (regno))
2967
2968 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2969 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2970 (mode))
2971
2972 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2973 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2974
2975 #define REGNO_OK_FOR_INDEX_P(regno) 0
2976 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2977 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2978
2979 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2980 and check its validity for a certain class.
2981 We have two alternate definitions for each of them.
2982 The usual definition accepts all pseudo regs; the other rejects them all.
2983 The symbol REG_OK_STRICT causes the latter definition to be used.
2984
2985 Most source files want to accept pseudo regs in the hope that
2986 they will get allocated to the class that the insn wants them to be in.
2987 Some source files that are used after register allocation
2988 need to be strict. */
2989
2990 #ifndef REG_OK_STRICT
2991 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2992 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2993 #else
2994 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2995 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2996 #endif
2997
2998 #define REG_OK_FOR_INDEX_P(X) 0
2999
3000 \f
3001 /* Maximum number of registers that can appear in a valid memory address. */
3002
3003 #define MAX_REGS_PER_ADDRESS 1
3004
3005 /* A C compound statement with a conditional `goto LABEL;' executed
3006 if X (an RTX) is a legitimate memory address on the target
3007 machine for a memory operand of mode MODE. */
3008
3009 #if 1
3010 #define GO_PRINTF(x) fprintf(stderr, (x))
3011 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3012 #define GO_DEBUG_RTX(x) debug_rtx(x)
3013
3014 #else
3015 #define GO_PRINTF(x)
3016 #define GO_PRINTF2(x,y)
3017 #define GO_DEBUG_RTX(x)
3018 #endif
3019
3020 #ifdef REG_OK_STRICT
3021 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3022 { \
3023 if (mips_legitimate_address_p (MODE, X, 1)) \
3024 goto ADDR; \
3025 }
3026 #else
3027 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3028 { \
3029 if (mips_legitimate_address_p (MODE, X, 0)) \
3030 goto ADDR; \
3031 }
3032 #endif
3033
3034 /* A C expression that is 1 if the RTX X is a constant which is a
3035 valid address. This is defined to be the same as `CONSTANT_P (X)',
3036 but rejecting CONST_DOUBLE. */
3037 /* When pic, we must reject addresses of the form symbol+large int.
3038 This is because an instruction `sw $4,s+70000' needs to be converted
3039 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3040 assembler would use $at as a temp to load in the large offset. In this
3041 case $at is already in use. We convert such problem addresses to
3042 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3043 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
3044 #define CONSTANT_ADDRESS_P(X) \
3045 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3046 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3047 || (GET_CODE (X) == CONST \
3048 && ! (flag_pic && pic_address_needs_scratch (X)) \
3049 && (mips_abi == ABI_32 \
3050 || mips_abi == ABI_O64 \
3051 || mips_abi == ABI_EABI)))
3052
3053 /* Define this, so that when PIC, reload won't try to reload invalid
3054 addresses which require two reload registers. */
3055
3056 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3057
3058 /* Nonzero if the constant value X is a legitimate general operand.
3059 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3060
3061 At present, GAS doesn't understand li.[sd], so don't allow it
3062 to be generated at present. Also, the MIPS assembler does not
3063 grok li.d Infinity. */
3064
3065 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3066 Note that the Irix 6 assembler problem may already be fixed.
3067 Note also that the GET_CODE (X) == CONST test catches the mips16
3068 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3069 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3070 ABI_64 to work together, we'll need to fix this. */
3071 #define LEGITIMATE_CONSTANT_P(X) \
3072 ((GET_CODE (X) != CONST_DOUBLE \
3073 || mips_const_double_ok (X, GET_MODE (X))) \
3074 && ! (GET_CODE (X) == CONST \
3075 && ! TARGET_GAS \
3076 && (mips_abi == ABI_N32 \
3077 || mips_abi == ABI_64)) \
3078 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3079
3080 /* A C compound statement that attempts to replace X with a valid
3081 memory address for an operand of mode MODE. WIN will be a C
3082 statement label elsewhere in the code; the macro definition may
3083 use
3084
3085 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3086
3087 to avoid further processing if the address has become legitimate.
3088
3089 X will always be the result of a call to `break_out_memory_refs',
3090 and OLDX will be the operand that was given to that function to
3091 produce X.
3092
3093 The code generated by this macro should not alter the
3094 substructure of X. If it transforms X into a more legitimate
3095 form, it should assign X (which will always be a C variable) a
3096 new value.
3097
3098 It is not necessary for this macro to come up with a legitimate
3099 address. The compiler has standard ways of doing so in all
3100 cases. In fact, it is safe for this macro to do nothing. But
3101 often a machine-dependent strategy can generate better code.
3102
3103 For the MIPS, transform:
3104
3105 memory(X + <large int>)
3106
3107 into:
3108
3109 Y = <large int> & ~0x7fff;
3110 Z = X + Y
3111 memory (Z + (<large int> & 0x7fff));
3112
3113 This is for CSE to find several similar references, and only use one Z.
3114
3115 When PIC, convert addresses of the form memory (symbol+large int) to
3116 memory (reg+large int). */
3117
3118
3119 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3120 { \
3121 register rtx xinsn = (X); \
3122 \
3123 if (TARGET_DEBUG_B_MODE) \
3124 { \
3125 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3126 GO_DEBUG_RTX (xinsn); \
3127 } \
3128 \
3129 if (mips_split_addresses && mips_check_split (X, MODE)) \
3130 { \
3131 /* ??? Is this ever executed? */ \
3132 X = gen_rtx_LO_SUM (Pmode, \
3133 copy_to_mode_reg (Pmode, \
3134 gen_rtx (HIGH, Pmode, X)), \
3135 X); \
3136 goto WIN; \
3137 } \
3138 \
3139 if (GET_CODE (xinsn) == CONST \
3140 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3141 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3142 || (mips_abi != ABI_32 \
3143 && mips_abi != ABI_O64 \
3144 && mips_abi != ABI_EABI))) \
3145 { \
3146 rtx ptr_reg = gen_reg_rtx (Pmode); \
3147 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3148 \
3149 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3150 \
3151 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3152 if (SMALL_INT (constant)) \
3153 goto WIN; \
3154 /* Otherwise we fall through so the code below will fix the \
3155 constant. */ \
3156 xinsn = X; \
3157 } \
3158 \
3159 if (GET_CODE (xinsn) == PLUS) \
3160 { \
3161 register rtx xplus0 = XEXP (xinsn, 0); \
3162 register rtx xplus1 = XEXP (xinsn, 1); \
3163 register enum rtx_code code0 = GET_CODE (xplus0); \
3164 register enum rtx_code code1 = GET_CODE (xplus1); \
3165 \
3166 if (code0 != REG && code1 == REG) \
3167 { \
3168 xplus0 = XEXP (xinsn, 1); \
3169 xplus1 = XEXP (xinsn, 0); \
3170 code0 = GET_CODE (xplus0); \
3171 code1 = GET_CODE (xplus1); \
3172 } \
3173 \
3174 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3175 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3176 { \
3177 rtx int_reg = gen_reg_rtx (Pmode); \
3178 rtx ptr_reg = gen_reg_rtx (Pmode); \
3179 \
3180 emit_move_insn (int_reg, \
3181 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3182 \
3183 emit_insn (gen_rtx_SET (VOIDmode, \
3184 ptr_reg, \
3185 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3186 \
3187 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3188 goto WIN; \
3189 } \
3190 } \
3191 \
3192 if (TARGET_DEBUG_B_MODE) \
3193 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3194 }
3195
3196
3197 /* A C statement or compound statement with a conditional `goto
3198 LABEL;' executed if memory address X (an RTX) can have different
3199 meanings depending on the machine mode of the memory reference it
3200 is used for.
3201
3202 Autoincrement and autodecrement addresses typically have
3203 mode-dependent effects because the amount of the increment or
3204 decrement is the size of the operand being addressed. Some
3205 machines have other mode-dependent addresses. Many RISC machines
3206 have no mode-dependent addresses.
3207
3208 You may assume that ADDR is a valid address for the machine. */
3209
3210 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3211
3212 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3213 'the start of the function that this code is output in'. */
3214
3215 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3216 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3217 asm_fprintf ((FILE), "%U%s", \
3218 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3219 else \
3220 asm_fprintf ((FILE), "%U%s", (NAME))
3221
3222 /* The mips16 wants the constant pool to be after the function,
3223 because the PC relative load instructions use unsigned offsets. */
3224
3225 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3226
3227 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3228 mips_string_length = 0;
3229
3230 #if 0
3231 /* In mips16 mode, put most string constants after the function. */
3232 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3233 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3234 #endif
3235 \f
3236 /* Specify the machine mode that this machine uses
3237 for the index in the tablejump instruction.
3238 ??? Using HImode in mips16 mode can cause overflow. However, the
3239 overflow is no more likely than the overflow in a branch
3240 instruction. Large functions can currently break in both ways. */
3241 #define CASE_VECTOR_MODE \
3242 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3243
3244 /* Define as C expression which evaluates to nonzero if the tablejump
3245 instruction expects the table to contain offsets from the address of the
3246 table.
3247 Do not define this if the table should contain absolute addresses. */
3248 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3249
3250 /* Define this as 1 if `char' should by default be signed; else as 0. */
3251 #ifndef DEFAULT_SIGNED_CHAR
3252 #define DEFAULT_SIGNED_CHAR 1
3253 #endif
3254
3255 /* Max number of bytes we can move from memory to memory
3256 in one reasonably fast instruction. */
3257 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3258 #define MAX_MOVE_MAX 8
3259
3260 /* Define this macro as a C expression which is nonzero if
3261 accessing less than a word of memory (i.e. a `char' or a
3262 `short') is no faster than accessing a word of memory, i.e., if
3263 such access require more than one instruction or if there is no
3264 difference in cost between byte and (aligned) word loads.
3265
3266 On RISC machines, it tends to generate better code to define
3267 this as 1, since it avoids making a QI or HI mode register. */
3268 #define SLOW_BYTE_ACCESS 1
3269
3270 /* We assume that the store-condition-codes instructions store 0 for false
3271 and some other value for true. This is the value stored for true. */
3272
3273 #define STORE_FLAG_VALUE 1
3274
3275 /* Define this to be nonzero if shift instructions ignore all but the low-order
3276 few bits. */
3277 #define SHIFT_COUNT_TRUNCATED 1
3278
3279 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3280 is done just by pretending it is already truncated. */
3281 /* In 64 bit mode, 32 bit instructions require that register values be properly
3282 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3283 converts a value >32 bits to a value <32 bits. */
3284 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3285 Something needs to be done about this. Perhaps not use any 32 bit
3286 instructions? Perhaps use PROMOTE_MODE? */
3287 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3288 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3289
3290 /* Specify the machine mode that pointers have.
3291 After generation of rtl, the compiler makes no further distinction
3292 between pointers and any other objects of this machine mode.
3293
3294 For MIPS we make pointers are the smaller of longs and gp-registers. */
3295
3296 #ifndef Pmode
3297 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3298 #endif
3299
3300 /* A function address in a call instruction
3301 is a word address (for indexing purposes)
3302 so give the MEM rtx a words's mode. */
3303
3304 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3305
3306 \f
3307 /* A part of a C `switch' statement that describes the relative
3308 costs of constant RTL expressions. It must contain `case'
3309 labels for expression codes `const_int', `const', `symbol_ref',
3310 `label_ref' and `const_double'. Each case must ultimately reach
3311 a `return' statement to return the relative cost of the use of
3312 that kind of constant value in an expression. The cost may
3313 depend on the precise value of the constant, which is available
3314 for examination in X.
3315
3316 CODE is the expression code--redundant, since it can be obtained
3317 with `GET_CODE (X)'. */
3318
3319 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3320 case CONST_INT: \
3321 if (! TARGET_MIPS16) \
3322 { \
3323 /* Always return 0, since we don't have different sized \
3324 instructions, hence different costs according to Richard \
3325 Kenner */ \
3326 return 0; \
3327 } \
3328 if ((OUTER_CODE) == SET) \
3329 { \
3330 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3331 return 0; \
3332 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3333 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3334 return COSTS_N_INSNS (1); \
3335 else \
3336 return COSTS_N_INSNS (2); \
3337 } \
3338 /* A PLUS could be an address. We don't want to force an address \
3339 to use a register, so accept any signed 16 bit value without \
3340 complaint. */ \
3341 if ((OUTER_CODE) == PLUS \
3342 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3343 return 0; \
3344 /* A number between 1 and 8 inclusive is efficient for a shift. \
3345 Otherwise, we will need an extended instruction. */ \
3346 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3347 || (OUTER_CODE) == LSHIFTRT) \
3348 { \
3349 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3350 return 0; \
3351 return COSTS_N_INSNS (1); \
3352 } \
3353 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3354 if ((OUTER_CODE) == XOR \
3355 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3356 return 0; \
3357 /* We may be able to use slt or sltu for a comparison with a \
3358 signed 16 bit value. (The boundary conditions aren't quite \
3359 right, but this is just a heuristic anyhow.) */ \
3360 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3361 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3362 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3363 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3364 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3365 return 0; \
3366 /* Equality comparisons with 0 are cheap. */ \
3367 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3368 && INTVAL (X) == 0) \
3369 return 0; \
3370 \
3371 /* Otherwise, work out the cost to load the value into a \
3372 register. */ \
3373 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3374 return COSTS_N_INSNS (1); \
3375 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3376 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3377 return COSTS_N_INSNS (2); \
3378 else \
3379 return COSTS_N_INSNS (3); \
3380 \
3381 case LABEL_REF: \
3382 return COSTS_N_INSNS (2); \
3383 \
3384 case CONST: \
3385 { \
3386 rtx offset = const0_rtx; \
3387 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3388 \
3389 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3390 { \
3391 /* Treat this like a signed 16 bit CONST_INT. */ \
3392 if ((OUTER_CODE) == PLUS) \
3393 return 0; \
3394 else if ((OUTER_CODE) == SET) \
3395 return COSTS_N_INSNS (1); \
3396 else \
3397 return COSTS_N_INSNS (2); \
3398 } \
3399 \
3400 if (GET_CODE (symref) == LABEL_REF) \
3401 return COSTS_N_INSNS (2); \
3402 \
3403 if (GET_CODE (symref) != SYMBOL_REF) \
3404 return COSTS_N_INSNS (4); \
3405 \
3406 /* let's be paranoid.... */ \
3407 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3408 return COSTS_N_INSNS (2); \
3409 \
3410 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3411 } \
3412 \
3413 case SYMBOL_REF: \
3414 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3415 \
3416 case CONST_DOUBLE: \
3417 { \
3418 rtx high, low; \
3419 if (TARGET_MIPS16) \
3420 return COSTS_N_INSNS (4); \
3421 split_double (X, &high, &low); \
3422 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3423 || low == CONST0_RTX (GET_MODE (low))) \
3424 ? 2 : 4); \
3425 }
3426
3427 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3428 This can be used, for example, to indicate how costly a multiply
3429 instruction is. In writing this macro, you can use the construct
3430 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3431
3432 This macro is optional; do not define it if the default cost
3433 assumptions are adequate for the target machine.
3434
3435 If -mdebugd is used, change the multiply cost to 2, so multiply by
3436 a constant isn't converted to a series of shifts. This helps
3437 strength reduction, and also makes it easier to identify what the
3438 compiler is doing. */
3439
3440 /* ??? Fix this to be right for the R8000. */
3441 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3442 case MEM: \
3443 { \
3444 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3445 if (simple_memory_operand (X, GET_MODE (X))) \
3446 return COSTS_N_INSNS (num_words); \
3447 \
3448 return COSTS_N_INSNS (2*num_words); \
3449 } \
3450 \
3451 case FFS: \
3452 return COSTS_N_INSNS (6); \
3453 \
3454 case NOT: \
3455 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3456 \
3457 case AND: \
3458 case IOR: \
3459 case XOR: \
3460 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3461 return COSTS_N_INSNS (2); \
3462 \
3463 break; \
3464 \
3465 case ASHIFT: \
3466 case ASHIFTRT: \
3467 case LSHIFTRT: \
3468 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3469 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3470 \
3471 break; \
3472 \
3473 case ABS: \
3474 { \
3475 enum machine_mode xmode = GET_MODE (X); \
3476 if (xmode == SFmode || xmode == DFmode) \
3477 return COSTS_N_INSNS (1); \
3478 \
3479 return COSTS_N_INSNS (4); \
3480 } \
3481 \
3482 case PLUS: \
3483 case MINUS: \
3484 { \
3485 enum machine_mode xmode = GET_MODE (X); \
3486 if (xmode == SFmode || xmode == DFmode) \
3487 { \
3488 if (TUNE_MIPS3000 \
3489 || TUNE_MIPS3900) \
3490 return COSTS_N_INSNS (2); \
3491 else if (TUNE_MIPS6000) \
3492 return COSTS_N_INSNS (3); \
3493 else \
3494 return COSTS_N_INSNS (6); \
3495 } \
3496 \
3497 if (xmode == DImode && !TARGET_64BIT) \
3498 return COSTS_N_INSNS (4); \
3499 \
3500 break; \
3501 } \
3502 \
3503 case NEG: \
3504 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3505 return 4; \
3506 \
3507 break; \
3508 \
3509 case MULT: \
3510 { \
3511 enum machine_mode xmode = GET_MODE (X); \
3512 if (xmode == SFmode) \
3513 { \
3514 if (TUNE_MIPS3000 \
3515 || TUNE_MIPS3900 \
3516 || TUNE_MIPS5000) \
3517 return COSTS_N_INSNS (4); \
3518 else if (TUNE_MIPS6000) \
3519 return COSTS_N_INSNS (5); \
3520 else \
3521 return COSTS_N_INSNS (7); \
3522 } \
3523 \
3524 if (xmode == DFmode) \
3525 { \
3526 if (TUNE_MIPS3000 \
3527 || TUNE_MIPS3900 \
3528 || TUNE_MIPS5000) \
3529 return COSTS_N_INSNS (5); \
3530 else if (TUNE_MIPS6000) \
3531 return COSTS_N_INSNS (6); \
3532 else \
3533 return COSTS_N_INSNS (8); \
3534 } \
3535 \
3536 if (TUNE_MIPS3000) \
3537 return COSTS_N_INSNS (12); \
3538 else if (TUNE_MIPS3900) \
3539 return COSTS_N_INSNS (2); \
3540 else if (TUNE_MIPS6000) \
3541 return COSTS_N_INSNS (17); \
3542 else if (TUNE_MIPS5000) \
3543 return COSTS_N_INSNS (5); \
3544 else \
3545 return COSTS_N_INSNS (10); \
3546 } \
3547 \
3548 case DIV: \
3549 case MOD: \
3550 { \
3551 enum machine_mode xmode = GET_MODE (X); \
3552 if (xmode == SFmode) \
3553 { \
3554 if (TUNE_MIPS3000 \
3555 || TUNE_MIPS3900) \
3556 return COSTS_N_INSNS (12); \
3557 else if (TUNE_MIPS6000) \
3558 return COSTS_N_INSNS (15); \
3559 else \
3560 return COSTS_N_INSNS (23); \
3561 } \
3562 \
3563 if (xmode == DFmode) \
3564 { \
3565 if (TUNE_MIPS3000 \
3566 || TUNE_MIPS3900) \
3567 return COSTS_N_INSNS (19); \
3568 else if (TUNE_MIPS6000) \
3569 return COSTS_N_INSNS (16); \
3570 else \
3571 return COSTS_N_INSNS (36); \
3572 } \
3573 } \
3574 /* fall through */ \
3575 \
3576 case UDIV: \
3577 case UMOD: \
3578 if (TUNE_MIPS3000 \
3579 || TUNE_MIPS3900) \
3580 return COSTS_N_INSNS (35); \
3581 else if (TUNE_MIPS6000) \
3582 return COSTS_N_INSNS (38); \
3583 else if (TUNE_MIPS5000) \
3584 return COSTS_N_INSNS (36); \
3585 else \
3586 return COSTS_N_INSNS (69); \
3587 \
3588 case SIGN_EXTEND: \
3589 /* A sign extend from SImode to DImode in 64 bit mode is often \
3590 zero instructions, because the result can often be used \
3591 directly by another instruction; we'll call it one. */ \
3592 if (TARGET_64BIT && GET_MODE (X) == DImode \
3593 && GET_MODE (XEXP (X, 0)) == SImode) \
3594 return COSTS_N_INSNS (1); \
3595 else \
3596 return COSTS_N_INSNS (2); \
3597 \
3598 case ZERO_EXTEND: \
3599 if (TARGET_64BIT && GET_MODE (X) == DImode \
3600 && GET_MODE (XEXP (X, 0)) == SImode) \
3601 return COSTS_N_INSNS (2); \
3602 else \
3603 return COSTS_N_INSNS (1);
3604
3605 /* An expression giving the cost of an addressing mode that
3606 contains ADDRESS. If not defined, the cost is computed from the
3607 form of the ADDRESS expression and the `CONST_COSTS' values.
3608
3609 For most CISC machines, the default cost is a good approximation
3610 of the true cost of the addressing mode. However, on RISC
3611 machines, all instructions normally have the same length and
3612 execution time. Hence all addresses will have equal costs.
3613
3614 In cases where more than one form of an address is known, the
3615 form with the lowest cost will be used. If multiple forms have
3616 the same, lowest, cost, the one that is the most complex will be
3617 used.
3618
3619 For example, suppose an address that is equal to the sum of a
3620 register and a constant is used twice in the same basic block.
3621 When this macro is not defined, the address will be computed in
3622 a register and memory references will be indirect through that
3623 register. On machines where the cost of the addressing mode
3624 containing the sum is no higher than that of a simple indirect
3625 reference, this will produce an additional instruction and
3626 possibly require an additional register. Proper specification
3627 of this macro eliminates this overhead for such machines.
3628
3629 Similar use of this macro is made in strength reduction of loops.
3630
3631 ADDRESS need not be valid as an address. In such a case, the
3632 cost is not relevant and can be any value; invalid addresses
3633 need not be assigned a different cost.
3634
3635 On machines where an address involving more than one register is
3636 as cheap as an address computation involving only one register,
3637 defining `ADDRESS_COST' to reflect this can cause two registers
3638 to be live over a region of code where only one would have been
3639 if `ADDRESS_COST' were not defined in that manner. This effect
3640 should be considered in the definition of this macro.
3641 Equivalent costs should probably only be given to addresses with
3642 different numbers of registers on machines with lots of registers.
3643
3644 This macro will normally either not be defined or be defined as
3645 a constant. */
3646
3647 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3648
3649 /* A C expression for the cost of moving data from a register in
3650 class FROM to one in class TO. The classes are expressed using
3651 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3652 the default; other values are interpreted relative to that.
3653
3654 It is not required that the cost always equal 2 when FROM is the
3655 same as TO; on some machines it is expensive to move between
3656 registers if they are not general registers.
3657
3658 If reload sees an insn consisting of a single `set' between two
3659 hard registers, and if `REGISTER_MOVE_COST' applied to their
3660 classes returns a value of 2, reload does not check to ensure
3661 that the constraints of the insn are met. Setting a cost of
3662 other than 2 will allow reload to verify that the constraints are
3663 met. You should do this if the `movM' pattern's constraints do
3664 not allow such copying. */
3665
3666 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3667 mips_register_move_cost (MODE, FROM, TO)
3668
3669 /* ??? Fix this to be right for the R8000. */
3670 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3671 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3672 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3673
3674 /* Define if copies to/from condition code registers should be avoided.
3675
3676 This is needed for the MIPS because reload_outcc is not complete;
3677 it needs to handle cases where the source is a general or another
3678 condition code register. */
3679 #define AVOID_CCMODE_COPIES
3680
3681 /* A C expression for the cost of a branch instruction. A value of
3682 1 is the default; other values are interpreted relative to that. */
3683
3684 /* ??? Fix this to be right for the R8000. */
3685 #define BRANCH_COST \
3686 ((! TARGET_MIPS16 \
3687 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3688 ? 2 : 1)
3689
3690 /* If defined, modifies the length assigned to instruction INSN as a
3691 function of the context in which it is used. LENGTH is an lvalue
3692 that contains the initially computed length of the insn and should
3693 be updated with the correct length of the insn. */
3694 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3695 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3696
3697 \f
3698 /* Optionally define this if you have added predicates to
3699 `MACHINE.c'. This macro is called within an initializer of an
3700 array of structures. The first field in the structure is the
3701 name of a predicate and the second field is an array of rtl
3702 codes. For each predicate, list all rtl codes that can be in
3703 expressions matched by the predicate. The list should have a
3704 trailing comma. Here is an example of two entries in the list
3705 for a typical RISC machine:
3706
3707 #define PREDICATE_CODES \
3708 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3709 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3710
3711 Defining this macro does not affect the generated code (however,
3712 incorrect definitions that omit an rtl code that may be matched
3713 by the predicate can cause the compiler to malfunction).
3714 Instead, it allows the table built by `genrecog' to be more
3715 compact and efficient, thus speeding up the compiler. The most
3716 important predicates to include in the list specified by this
3717 macro are thoses used in the most insn patterns. */
3718
3719 #define PREDICATE_CODES \
3720 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3721 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3722 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3723 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3724 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3725 {"small_int", { CONST_INT }}, \
3726 {"large_int", { CONST_INT }}, \
3727 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3728 {"const_float_1_operand", { CONST_DOUBLE }}, \
3729 {"simple_memory_operand", { MEM, SUBREG }}, \
3730 {"equality_op", { EQ, NE }}, \
3731 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3732 LTU, LEU }}, \
3733 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3734 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3735 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3736 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3737 SYMBOL_REF, LABEL_REF, SUBREG, \
3738 REG, MEM}}, \
3739 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3740 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3741 MEM, SIGN_EXTEND }}, \
3742 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3743 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3744 SIGN_EXTEND }}, \
3745 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3746 SIGN_EXTEND }}, \
3747 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3748 SIGN_EXTEND }}, \
3749 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3750 SYMBOL_REF, LABEL_REF, SUBREG, \
3751 REG, SIGN_EXTEND }}, \
3752 {"se_nonimmediate_operand", { SUBREG, REG, MEM, SIGN_EXTEND }}, \
3753 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3754 CONST_DOUBLE, CONST }}, \
3755 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3756 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3757
3758 /* A list of predicates that do special things with modes, and so
3759 should not elicit warnings for VOIDmode match_operand. */
3760
3761 #define SPECIAL_MODE_PREDICATES \
3762 "pc_or_label_operand",
3763
3764 \f
3765 /* If defined, a C statement to be executed just prior to the
3766 output of assembler code for INSN, to modify the extracted
3767 operands so they will be output differently.
3768
3769 Here the argument OPVEC is the vector containing the operands
3770 extracted from INSN, and NOPERANDS is the number of elements of
3771 the vector which contain meaningful data for this insn. The
3772 contents of this vector are what will be used to convert the
3773 insn template into assembler code, so you can change the
3774 assembler output by changing the contents of the vector.
3775
3776 We use it to check if the current insn needs a nop in front of it
3777 because of load delays, and also to update the delay slot
3778 statistics. */
3779
3780 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3781 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3782
3783 \f
3784 /* Control the assembler format that we output. */
3785
3786 /* Output at beginning of assembler file.
3787 If we are optimizing to use the global pointer, create a temporary
3788 file to hold all of the text stuff, and write it out to the end.
3789 This is needed because the MIPS assembler is evidently one pass,
3790 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3791 declaration when the code is processed, it generates a two
3792 instruction sequence. */
3793
3794 #undef ASM_FILE_START
3795 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3796
3797 /* Output to assembler file text saying following lines
3798 may contain character constants, extra white space, comments, etc. */
3799
3800 #ifndef ASM_APP_ON
3801 #define ASM_APP_ON " #APP\n"
3802 #endif
3803
3804 /* Output to assembler file text saying following lines
3805 no longer contain unusual constructs. */
3806
3807 #ifndef ASM_APP_OFF
3808 #define ASM_APP_OFF " #NO_APP\n"
3809 #endif
3810
3811 /* How to refer to registers in assembler output.
3812 This sequence is indexed by compiler's hard-register-number (see above).
3813
3814 In order to support the two different conventions for register names,
3815 we use the name of a table set up in mips.c, which is overwritten
3816 if -mrnames is used. */
3817
3818 #define REGISTER_NAMES \
3819 { \
3820 &mips_reg_names[ 0][0], \
3821 &mips_reg_names[ 1][0], \
3822 &mips_reg_names[ 2][0], \
3823 &mips_reg_names[ 3][0], \
3824 &mips_reg_names[ 4][0], \
3825 &mips_reg_names[ 5][0], \
3826 &mips_reg_names[ 6][0], \
3827 &mips_reg_names[ 7][0], \
3828 &mips_reg_names[ 8][0], \
3829 &mips_reg_names[ 9][0], \
3830 &mips_reg_names[10][0], \
3831 &mips_reg_names[11][0], \
3832 &mips_reg_names[12][0], \
3833 &mips_reg_names[13][0], \
3834 &mips_reg_names[14][0], \
3835 &mips_reg_names[15][0], \
3836 &mips_reg_names[16][0], \
3837 &mips_reg_names[17][0], \
3838 &mips_reg_names[18][0], \
3839 &mips_reg_names[19][0], \
3840 &mips_reg_names[20][0], \
3841 &mips_reg_names[21][0], \
3842 &mips_reg_names[22][0], \
3843 &mips_reg_names[23][0], \
3844 &mips_reg_names[24][0], \
3845 &mips_reg_names[25][0], \
3846 &mips_reg_names[26][0], \
3847 &mips_reg_names[27][0], \
3848 &mips_reg_names[28][0], \
3849 &mips_reg_names[29][0], \
3850 &mips_reg_names[30][0], \
3851 &mips_reg_names[31][0], \
3852 &mips_reg_names[32][0], \
3853 &mips_reg_names[33][0], \
3854 &mips_reg_names[34][0], \
3855 &mips_reg_names[35][0], \
3856 &mips_reg_names[36][0], \
3857 &mips_reg_names[37][0], \
3858 &mips_reg_names[38][0], \
3859 &mips_reg_names[39][0], \
3860 &mips_reg_names[40][0], \
3861 &mips_reg_names[41][0], \
3862 &mips_reg_names[42][0], \
3863 &mips_reg_names[43][0], \
3864 &mips_reg_names[44][0], \
3865 &mips_reg_names[45][0], \
3866 &mips_reg_names[46][0], \
3867 &mips_reg_names[47][0], \
3868 &mips_reg_names[48][0], \
3869 &mips_reg_names[49][0], \
3870 &mips_reg_names[50][0], \
3871 &mips_reg_names[51][0], \
3872 &mips_reg_names[52][0], \
3873 &mips_reg_names[53][0], \
3874 &mips_reg_names[54][0], \
3875 &mips_reg_names[55][0], \
3876 &mips_reg_names[56][0], \
3877 &mips_reg_names[57][0], \
3878 &mips_reg_names[58][0], \
3879 &mips_reg_names[59][0], \
3880 &mips_reg_names[60][0], \
3881 &mips_reg_names[61][0], \
3882 &mips_reg_names[62][0], \
3883 &mips_reg_names[63][0], \
3884 &mips_reg_names[64][0], \
3885 &mips_reg_names[65][0], \
3886 &mips_reg_names[66][0], \
3887 &mips_reg_names[67][0], \
3888 &mips_reg_names[68][0], \
3889 &mips_reg_names[69][0], \
3890 &mips_reg_names[70][0], \
3891 &mips_reg_names[71][0], \
3892 &mips_reg_names[72][0], \
3893 &mips_reg_names[73][0], \
3894 &mips_reg_names[74][0], \
3895 &mips_reg_names[75][0], \
3896 &mips_reg_names[76][0], \
3897 &mips_reg_names[77][0], \
3898 &mips_reg_names[78][0], \
3899 &mips_reg_names[79][0], \
3900 &mips_reg_names[80][0], \
3901 &mips_reg_names[81][0], \
3902 &mips_reg_names[82][0], \
3903 &mips_reg_names[83][0], \
3904 &mips_reg_names[84][0], \
3905 &mips_reg_names[85][0], \
3906 &mips_reg_names[86][0], \
3907 &mips_reg_names[87][0], \
3908 &mips_reg_names[88][0], \
3909 &mips_reg_names[89][0], \
3910 &mips_reg_names[90][0], \
3911 &mips_reg_names[91][0], \
3912 &mips_reg_names[92][0], \
3913 &mips_reg_names[93][0], \
3914 &mips_reg_names[94][0], \
3915 &mips_reg_names[95][0], \
3916 &mips_reg_names[96][0], \
3917 &mips_reg_names[97][0], \
3918 &mips_reg_names[98][0], \
3919 &mips_reg_names[99][0], \
3920 &mips_reg_names[100][0], \
3921 &mips_reg_names[101][0], \
3922 &mips_reg_names[102][0], \
3923 &mips_reg_names[103][0], \
3924 &mips_reg_names[104][0], \
3925 &mips_reg_names[105][0], \
3926 &mips_reg_names[106][0], \
3927 &mips_reg_names[107][0], \
3928 &mips_reg_names[108][0], \
3929 &mips_reg_names[109][0], \
3930 &mips_reg_names[110][0], \
3931 &mips_reg_names[111][0], \
3932 &mips_reg_names[112][0], \
3933 &mips_reg_names[113][0], \
3934 &mips_reg_names[114][0], \
3935 &mips_reg_names[115][0], \
3936 &mips_reg_names[116][0], \
3937 &mips_reg_names[117][0], \
3938 &mips_reg_names[118][0], \
3939 &mips_reg_names[119][0], \
3940 &mips_reg_names[120][0], \
3941 &mips_reg_names[121][0], \
3942 &mips_reg_names[122][0], \
3943 &mips_reg_names[123][0], \
3944 &mips_reg_names[124][0], \
3945 &mips_reg_names[125][0], \
3946 &mips_reg_names[126][0], \
3947 &mips_reg_names[127][0], \
3948 &mips_reg_names[128][0], \
3949 &mips_reg_names[129][0], \
3950 &mips_reg_names[130][0], \
3951 &mips_reg_names[131][0], \
3952 &mips_reg_names[132][0], \
3953 &mips_reg_names[133][0], \
3954 &mips_reg_names[134][0], \
3955 &mips_reg_names[135][0], \
3956 &mips_reg_names[136][0], \
3957 &mips_reg_names[137][0], \
3958 &mips_reg_names[138][0], \
3959 &mips_reg_names[139][0], \
3960 &mips_reg_names[140][0], \
3961 &mips_reg_names[141][0], \
3962 &mips_reg_names[142][0], \
3963 &mips_reg_names[143][0], \
3964 &mips_reg_names[144][0], \
3965 &mips_reg_names[145][0], \
3966 &mips_reg_names[146][0], \
3967 &mips_reg_names[147][0], \
3968 &mips_reg_names[148][0], \
3969 &mips_reg_names[149][0], \
3970 &mips_reg_names[150][0], \
3971 &mips_reg_names[151][0], \
3972 &mips_reg_names[152][0], \
3973 &mips_reg_names[153][0], \
3974 &mips_reg_names[154][0], \
3975 &mips_reg_names[155][0], \
3976 &mips_reg_names[156][0], \
3977 &mips_reg_names[157][0], \
3978 &mips_reg_names[158][0], \
3979 &mips_reg_names[159][0], \
3980 &mips_reg_names[160][0], \
3981 &mips_reg_names[161][0], \
3982 &mips_reg_names[162][0], \
3983 &mips_reg_names[163][0], \
3984 &mips_reg_names[164][0], \
3985 &mips_reg_names[165][0], \
3986 &mips_reg_names[166][0], \
3987 &mips_reg_names[167][0], \
3988 &mips_reg_names[168][0], \
3989 &mips_reg_names[169][0], \
3990 &mips_reg_names[170][0], \
3991 &mips_reg_names[171][0], \
3992 &mips_reg_names[172][0], \
3993 &mips_reg_names[173][0], \
3994 &mips_reg_names[174][0], \
3995 &mips_reg_names[175][0] \
3996 }
3997
3998 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3999 So define this for it. */
4000 #define DEBUG_REGISTER_NAMES \
4001 { \
4002 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4003 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4004 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4005 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4006 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4007 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4008 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4009 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4010 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4011 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
4012 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
4013 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
4014 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
4015 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
4016 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
4017 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
4018 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
4019 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
4020 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
4021 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
4022 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
4023 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
4024 }
4025
4026 /* If defined, a C initializer for an array of structures
4027 containing a name and a register number. This macro defines
4028 additional names for hard registers, thus allowing the `asm'
4029 option in declarations to refer to registers using alternate
4030 names.
4031
4032 We define both names for the integer registers here. */
4033
4034 #define ADDITIONAL_REGISTER_NAMES \
4035 { \
4036 { "$0", 0 + GP_REG_FIRST }, \
4037 { "$1", 1 + GP_REG_FIRST }, \
4038 { "$2", 2 + GP_REG_FIRST }, \
4039 { "$3", 3 + GP_REG_FIRST }, \
4040 { "$4", 4 + GP_REG_FIRST }, \
4041 { "$5", 5 + GP_REG_FIRST }, \
4042 { "$6", 6 + GP_REG_FIRST }, \
4043 { "$7", 7 + GP_REG_FIRST }, \
4044 { "$8", 8 + GP_REG_FIRST }, \
4045 { "$9", 9 + GP_REG_FIRST }, \
4046 { "$10", 10 + GP_REG_FIRST }, \
4047 { "$11", 11 + GP_REG_FIRST }, \
4048 { "$12", 12 + GP_REG_FIRST }, \
4049 { "$13", 13 + GP_REG_FIRST }, \
4050 { "$14", 14 + GP_REG_FIRST }, \
4051 { "$15", 15 + GP_REG_FIRST }, \
4052 { "$16", 16 + GP_REG_FIRST }, \
4053 { "$17", 17 + GP_REG_FIRST }, \
4054 { "$18", 18 + GP_REG_FIRST }, \
4055 { "$19", 19 + GP_REG_FIRST }, \
4056 { "$20", 20 + GP_REG_FIRST }, \
4057 { "$21", 21 + GP_REG_FIRST }, \
4058 { "$22", 22 + GP_REG_FIRST }, \
4059 { "$23", 23 + GP_REG_FIRST }, \
4060 { "$24", 24 + GP_REG_FIRST }, \
4061 { "$25", 25 + GP_REG_FIRST }, \
4062 { "$26", 26 + GP_REG_FIRST }, \
4063 { "$27", 27 + GP_REG_FIRST }, \
4064 { "$28", 28 + GP_REG_FIRST }, \
4065 { "$29", 29 + GP_REG_FIRST }, \
4066 { "$30", 30 + GP_REG_FIRST }, \
4067 { "$31", 31 + GP_REG_FIRST }, \
4068 { "$sp", 29 + GP_REG_FIRST }, \
4069 { "$fp", 30 + GP_REG_FIRST }, \
4070 { "at", 1 + GP_REG_FIRST }, \
4071 { "v0", 2 + GP_REG_FIRST }, \
4072 { "v1", 3 + GP_REG_FIRST }, \
4073 { "a0", 4 + GP_REG_FIRST }, \
4074 { "a1", 5 + GP_REG_FIRST }, \
4075 { "a2", 6 + GP_REG_FIRST }, \
4076 { "a3", 7 + GP_REG_FIRST }, \
4077 { "t0", 8 + GP_REG_FIRST }, \
4078 { "t1", 9 + GP_REG_FIRST }, \
4079 { "t2", 10 + GP_REG_FIRST }, \
4080 { "t3", 11 + GP_REG_FIRST }, \
4081 { "t4", 12 + GP_REG_FIRST }, \
4082 { "t5", 13 + GP_REG_FIRST }, \
4083 { "t6", 14 + GP_REG_FIRST }, \
4084 { "t7", 15 + GP_REG_FIRST }, \
4085 { "s0", 16 + GP_REG_FIRST }, \
4086 { "s1", 17 + GP_REG_FIRST }, \
4087 { "s2", 18 + GP_REG_FIRST }, \
4088 { "s3", 19 + GP_REG_FIRST }, \
4089 { "s4", 20 + GP_REG_FIRST }, \
4090 { "s5", 21 + GP_REG_FIRST }, \
4091 { "s6", 22 + GP_REG_FIRST }, \
4092 { "s7", 23 + GP_REG_FIRST }, \
4093 { "t8", 24 + GP_REG_FIRST }, \
4094 { "t9", 25 + GP_REG_FIRST }, \
4095 { "k0", 26 + GP_REG_FIRST }, \
4096 { "k1", 27 + GP_REG_FIRST }, \
4097 { "gp", 28 + GP_REG_FIRST }, \
4098 { "sp", 29 + GP_REG_FIRST }, \
4099 { "fp", 30 + GP_REG_FIRST }, \
4100 { "ra", 31 + GP_REG_FIRST }, \
4101 { "$sp", 29 + GP_REG_FIRST }, \
4102 { "$fp", 30 + GP_REG_FIRST } \
4103 ALL_COP_ADDITIONAL_REGISTER_NAMES \
4104 }
4105
4106 /* This is meant to be redefined in the host dependent files. It is a
4107 set of alternative names and regnums for mips coprocessors. */
4108
4109 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
4110
4111 /* A C compound statement to output to stdio stream STREAM the
4112 assembler syntax for an instruction operand X. X is an RTL
4113 expression.
4114
4115 CODE is a value that can be used to specify one of several ways
4116 of printing the operand. It is used when identical operands
4117 must be printed differently depending on the context. CODE
4118 comes from the `%' specification that was used to request
4119 printing of the operand. If the specification was just `%DIGIT'
4120 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4121 is the ASCII code for LTR.
4122
4123 If X is a register, this macro should print the register's name.
4124 The names can be found in an array `reg_names' whose type is
4125 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4126
4127 When the machine description has a specification `%PUNCT' (a `%'
4128 followed by a punctuation character), this macro is called with
4129 a null pointer for X and the punctuation character for CODE.
4130
4131 See mips.c for the MIPS specific codes. */
4132
4133 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4134
4135 /* A C expression which evaluates to true if CODE is a valid
4136 punctuation character for use in the `PRINT_OPERAND' macro. If
4137 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4138 punctuation characters (except for the standard one, `%') are
4139 used in this way. */
4140
4141 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4142
4143 /* A C compound statement to output to stdio stream STREAM the
4144 assembler syntax for an instruction operand that is a memory
4145 reference whose address is ADDR. ADDR is an RTL expression. */
4146
4147 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4148
4149
4150 /* A C statement, to be executed after all slot-filler instructions
4151 have been output. If necessary, call `dbr_sequence_length' to
4152 determine the number of slots filled in a sequence (zero if not
4153 currently outputting a sequence), to decide how many no-ops to
4154 output, or whatever.
4155
4156 Don't define this macro if it has nothing to do, but it is
4157 helpful in reading assembly output if the extent of the delay
4158 sequence is made explicit (e.g. with white space).
4159
4160 Note that output routines for instructions with delay slots must
4161 be prepared to deal with not being output as part of a sequence
4162 (i.e. when the scheduling pass is not run, or when no slot
4163 fillers could be found.) The variable `final_sequence' is null
4164 when not processing a sequence, otherwise it contains the
4165 `sequence' rtx being output. */
4166
4167 #define DBR_OUTPUT_SEQEND(STREAM) \
4168 do \
4169 { \
4170 if (set_nomacro > 0 && --set_nomacro == 0) \
4171 fputs ("\t.set\tmacro\n", STREAM); \
4172 \
4173 if (set_noreorder > 0 && --set_noreorder == 0) \
4174 fputs ("\t.set\treorder\n", STREAM); \
4175 \
4176 dslots_jump_filled++; \
4177 fputs ("\n", STREAM); \
4178 } \
4179 while (0)
4180
4181
4182 /* How to tell the debugger about changes of source files. Note, the
4183 mips ECOFF format cannot deal with changes of files inside of
4184 functions, which means the output of parser generators like bison
4185 is generally not debuggable without using the -l switch. Lose,
4186 lose, lose. Silicon graphics seems to want all .file's hardwired
4187 to 1. */
4188
4189 #ifndef SET_FILE_NUMBER
4190 #define SET_FILE_NUMBER() ++num_source_filenames
4191 #endif
4192
4193 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4194 mips_output_filename (STREAM, NAME)
4195
4196 /* This is defined so that it can be overridden in iris6.h. */
4197 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4198 do \
4199 { \
4200 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4201 output_quoted_string (STREAM, NAME); \
4202 fputs ("\n", STREAM); \
4203 } \
4204 while (0)
4205
4206 /* This is how to output a note the debugger telling it the line number
4207 to which the following sequence of instructions corresponds.
4208 Silicon graphics puts a label after each .loc. */
4209
4210 #ifndef LABEL_AFTER_LOC
4211 #define LABEL_AFTER_LOC(STREAM)
4212 #endif
4213
4214 #ifndef ASM_OUTPUT_SOURCE_LINE
4215 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4216 mips_output_lineno (STREAM, LINE)
4217 #endif
4218
4219 /* The MIPS implementation uses some labels for its own purpose. The
4220 following lists what labels are created, and are all formed by the
4221 pattern $L[a-z].*. The machine independent portion of GCC creates
4222 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4223
4224 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4225 $Lb[0-9]+ Begin blocks for MIPS debug support
4226 $Lc[0-9]+ Label for use in s<xx> operation.
4227 $Le[0-9]+ End blocks for MIPS debug support */
4228
4229 /* This is how to output the definition of a user-level label named NAME,
4230 such as the label on a static function or variable NAME.
4231
4232 If we are optimizing the gp, remember that this label has been put
4233 out, so we know not to emit an .extern for it in mips_asm_file_end.
4234 We use one of the common bits in the IDENTIFIER tree node for this,
4235 since those bits seem to be unused, and we don't have any method
4236 of getting the decl nodes from the name. */
4237
4238 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4239 do { \
4240 assemble_name (STREAM, NAME); \
4241 fputs (":\n", STREAM); \
4242 } while (0)
4243
4244
4245 /* A C statement (sans semicolon) to output to the stdio stream
4246 STREAM any text necessary for declaring the name NAME of an
4247 initialized variable which is being defined. This macro must
4248 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4249 The argument DECL is the `VAR_DECL' tree node representing the
4250 variable.
4251
4252 If this macro is not defined, then the variable name is defined
4253 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4254
4255 #undef ASM_DECLARE_OBJECT_NAME
4256 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4257 do \
4258 { \
4259 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4260 } \
4261 while (0)
4262
4263
4264 /* This is how to output a command to make the user-level label named NAME
4265 defined for reference from other files. */
4266
4267 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4268 do { \
4269 fputs ("\t.globl\t", STREAM); \
4270 assemble_name (STREAM, NAME); \
4271 fputs ("\n", STREAM); \
4272 } while (0)
4273
4274 /* This says how to define a global common symbol. */
4275
4276 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4277 do { \
4278 /* If the target wants uninitialized const declarations in \
4279 .rdata then don't put them in .comm */ \
4280 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4281 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4282 && (DECL_INITIAL (DECL) == 0 \
4283 || DECL_INITIAL (DECL) == error_mark_node)) \
4284 { \
4285 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4286 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4287 \
4288 readonly_data_section (); \
4289 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4290 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4291 (SIZE)); \
4292 } \
4293 else \
4294 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4295 (SIZE)); \
4296 } while (0)
4297
4298
4299 /* This says how to define a local common symbol (ie, not visible to
4300 linker). */
4301
4302 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4303 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4304
4305
4306 /* This says how to output an external. It would be possible not to
4307 output anything and let undefined symbol become external. However
4308 the assembler uses length information on externals to allocate in
4309 data/sdata bss/sbss, thereby saving exec time. */
4310
4311 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4312 mips_output_external(STREAM,DECL,NAME)
4313
4314 /* This says what to print at the end of the assembly file */
4315 #undef ASM_FILE_END
4316 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4317
4318
4319 /* Play switch file games if we're optimizing the global pointer. */
4320
4321 #undef TEXT_SECTION
4322 #define TEXT_SECTION() \
4323 do { \
4324 extern FILE *asm_out_text_file; \
4325 if (TARGET_FILE_SWITCHING) \
4326 asm_out_file = asm_out_text_file; \
4327 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4328 fputc ('\n', asm_out_file); \
4329 } while (0)
4330
4331
4332 /* This is how to declare a function name. The actual work of
4333 emitting the label is moved to function_prologue, so that we can
4334 get the line number correctly emitted before the .ent directive,
4335 and after any .file directives. */
4336 /*
4337 #undef ASM_DECLARE_FUNCTION_NAME
4338 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4339 */
4340
4341 /* This is how to output an internal numbered label where
4342 PREFIX is the class of label and NUM is the number within the class. */
4343
4344 #undef ASM_OUTPUT_INTERNAL_LABEL
4345 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4346 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4347
4348 /* This is how to store into the string LABEL
4349 the symbol_ref name of an internal numbered label where
4350 PREFIX is the class of label and NUM is the number within the class.
4351 This is suitable for output with `assemble_name'. */
4352
4353 #undef ASM_GENERATE_INTERNAL_LABEL
4354 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4355 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4356
4357 /* This is how to output an element of a case-vector that is absolute. */
4358
4359 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4360 fprintf (STREAM, "\t%s\t%sL%d\n", \
4361 Pmode == DImode ? ".dword" : ".word", \
4362 LOCAL_LABEL_PREFIX, \
4363 VALUE)
4364
4365 /* This is how to output an element of a case-vector that is relative.
4366 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4367 TARGET_EMBEDDED_PIC). */
4368
4369 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4370 do { \
4371 if (TARGET_MIPS16) \
4372 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4373 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4374 else if (TARGET_EMBEDDED_PIC) \
4375 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4376 Pmode == DImode ? ".dword" : ".word", \
4377 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4378 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4379 fprintf (STREAM, "\t%s\t%sL%d\n", \
4380 Pmode == DImode ? ".gpdword" : ".gpword", \
4381 LOCAL_LABEL_PREFIX, VALUE); \
4382 else \
4383 fprintf (STREAM, "\t%s\t%sL%d\n", \
4384 Pmode == DImode ? ".dword" : ".word", \
4385 LOCAL_LABEL_PREFIX, VALUE); \
4386 } while (0)
4387
4388 /* When generating embedded PIC or mips16 code we want to put the jump
4389 table in the .text section. In all other cases, we want to put the
4390 jump table in the .rdata section. Unfortunately, we can't use
4391 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4392 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4393 section if appropriate. */
4394 #undef ASM_OUTPUT_CASE_LABEL
4395 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4396 do { \
4397 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4398 function_section (current_function_decl); \
4399 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4400 } while (0)
4401
4402 /* This is how to output an assembler line
4403 that says to advance the location counter
4404 to a multiple of 2**LOG bytes. */
4405
4406 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4407 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4408
4409 /* This is how to output an assembler line to advance the location
4410 counter by SIZE bytes. */
4411
4412 #undef ASM_OUTPUT_SKIP
4413 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4414 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4415
4416 /* This is how to output a string. */
4417 #undef ASM_OUTPUT_ASCII
4418 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4419 mips_output_ascii (STREAM, STRING, LEN)
4420
4421 /* Handle certain cpp directives used in header files on sysV. */
4422 #define SCCS_DIRECTIVE
4423
4424 /* Output #ident as a in the read-only data section. */
4425 #undef ASM_OUTPUT_IDENT
4426 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4427 { \
4428 const char *p = STRING; \
4429 int size = strlen (p) + 1; \
4430 readonly_data_section (); \
4431 assemble_string (p, size); \
4432 }
4433 \f
4434 /* Default to -G 8 */
4435 #ifndef MIPS_DEFAULT_GVALUE
4436 #define MIPS_DEFAULT_GVALUE 8
4437 #endif
4438
4439 /* Define the strings to put out for each section in the object file. */
4440 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4441 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4442 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4443 #ifndef READONLY_DATA_SECTION_ASM_OP
4444 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4445 #endif
4446 #define SMALL_DATA_SECTION sdata_section
4447
4448 /* What other sections we support other than the normal .data/.text. */
4449
4450 #undef EXTRA_SECTIONS
4451 #define EXTRA_SECTIONS in_sdata
4452
4453 /* Define the additional functions to select our additional sections. */
4454
4455 /* on the MIPS it is not a good idea to put constants in the text
4456 section, since this defeats the sdata/data mechanism. This is
4457 especially true when -O is used. In this case an effort is made to
4458 address with faster (gp) register relative addressing, which can
4459 only get at sdata and sbss items (there is no stext !!) However,
4460 if the constant is too large for sdata, and it's readonly, it
4461 will go into the .rdata section. */
4462
4463 #undef EXTRA_SECTION_FUNCTIONS
4464 #define EXTRA_SECTION_FUNCTIONS \
4465 void \
4466 sdata_section () \
4467 { \
4468 if (in_section != in_sdata) \
4469 { \
4470 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4471 in_section = in_sdata; \
4472 } \
4473 }
4474
4475 /* Given a decl node or constant node, choose the section to output it in
4476 and select that section. */
4477
4478 #undef TARGET_ASM_SELECT_SECTION
4479 #define TARGET_ASM_SELECT_SECTION mips_select_section
4480 \f
4481 /* Store in OUTPUT a string (made with alloca) containing
4482 an assembler-name for a local static variable named NAME.
4483 LABELNO is an integer which is different for each call. */
4484
4485 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4486 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4487 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4488
4489 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4490 do \
4491 { \
4492 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4493 TARGET_64BIT ? "dsubu" : "subu", \
4494 reg_names[STACK_POINTER_REGNUM], \
4495 reg_names[STACK_POINTER_REGNUM], \
4496 TARGET_64BIT ? "sd" : "sw", \
4497 reg_names[REGNO], \
4498 reg_names[STACK_POINTER_REGNUM]); \
4499 } \
4500 while (0)
4501
4502 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4503 do \
4504 { \
4505 if (! set_noreorder) \
4506 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4507 \
4508 dslots_load_total++; \
4509 dslots_load_filled++; \
4510 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4511 TARGET_64BIT ? "ld" : "lw", \
4512 reg_names[REGNO], \
4513 reg_names[STACK_POINTER_REGNUM], \
4514 TARGET_64BIT ? "daddu" : "addu", \
4515 reg_names[STACK_POINTER_REGNUM], \
4516 reg_names[STACK_POINTER_REGNUM]); \
4517 \
4518 if (! set_noreorder) \
4519 fprintf (STREAM, "\t.set\treorder\n"); \
4520 } \
4521 while (0)
4522
4523 /* How to start an assembler comment.
4524 The leading space is important (the mips native assembler requires it). */
4525 #ifndef ASM_COMMENT_START
4526 #define ASM_COMMENT_START " #"
4527 #endif
4528 \f
4529
4530 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4531 and mips-tdump.c to print them out.
4532
4533 These must match the corresponding definitions in gdb/mipsread.c.
4534 Unfortunately, gcc and gdb do not currently share any directories. */
4535
4536 #define CODE_MASK 0x8F300
4537 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4538 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4539 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4540
4541 \f
4542 /* Default definitions for size_t and ptrdiff_t. */
4543
4544 #ifndef SIZE_TYPE
4545 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4546 #endif
4547
4548 #ifndef PTRDIFF_TYPE
4549 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4550 #endif
4551
4552 /* See mips_expand_prologue's use of loadgp for when this should be
4553 true. */
4554
4555 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4556 && mips_abi != ABI_32 \
4557 && mips_abi != ABI_O64)
4558 \f
4559 /* In mips16 mode, we need to look through the function to check for
4560 PC relative loads that are out of range. */
4561 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4562
4563 /* We need to use a special set of functions to handle hard floating
4564 point code in mips16 mode. */
4565
4566 #ifndef INIT_SUBTARGET_OPTABS
4567 #define INIT_SUBTARGET_OPTABS
4568 #endif
4569
4570 #define INIT_TARGET_OPTABS \
4571 do \
4572 { \
4573 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4574 INIT_SUBTARGET_OPTABS; \
4575 else \
4576 { \
4577 add_optab->handlers[(int) SFmode].libfunc = \
4578 init_one_libfunc ("__mips16_addsf3"); \
4579 sub_optab->handlers[(int) SFmode].libfunc = \
4580 init_one_libfunc ("__mips16_subsf3"); \
4581 smul_optab->handlers[(int) SFmode].libfunc = \
4582 init_one_libfunc ("__mips16_mulsf3"); \
4583 sdiv_optab->handlers[(int) SFmode].libfunc = \
4584 init_one_libfunc ("__mips16_divsf3"); \
4585 \
4586 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4587 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4588 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4589 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4590 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4591 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4592 \
4593 floatsisf_libfunc = \
4594 init_one_libfunc ("__mips16_floatsisf"); \
4595 fixsfsi_libfunc = \
4596 init_one_libfunc ("__mips16_fixsfsi"); \
4597 \
4598 if (TARGET_DOUBLE_FLOAT) \
4599 { \
4600 add_optab->handlers[(int) DFmode].libfunc = \
4601 init_one_libfunc ("__mips16_adddf3"); \
4602 sub_optab->handlers[(int) DFmode].libfunc = \
4603 init_one_libfunc ("__mips16_subdf3"); \
4604 smul_optab->handlers[(int) DFmode].libfunc = \
4605 init_one_libfunc ("__mips16_muldf3"); \
4606 sdiv_optab->handlers[(int) DFmode].libfunc = \
4607 init_one_libfunc ("__mips16_divdf3"); \
4608 \
4609 extendsfdf2_libfunc = \
4610 init_one_libfunc ("__mips16_extendsfdf2"); \
4611 truncdfsf2_libfunc = \
4612 init_one_libfunc ("__mips16_truncdfsf2"); \
4613 \
4614 eqdf2_libfunc = \
4615 init_one_libfunc ("__mips16_eqdf2"); \
4616 nedf2_libfunc = \
4617 init_one_libfunc ("__mips16_nedf2"); \
4618 gtdf2_libfunc = \
4619 init_one_libfunc ("__mips16_gtdf2"); \
4620 gedf2_libfunc = \
4621 init_one_libfunc ("__mips16_gedf2"); \
4622 ltdf2_libfunc = \
4623 init_one_libfunc ("__mips16_ltdf2"); \
4624 ledf2_libfunc = \
4625 init_one_libfunc ("__mips16_ledf2"); \
4626 \
4627 floatsidf_libfunc = \
4628 init_one_libfunc ("__mips16_floatsidf"); \
4629 fixdfsi_libfunc = \
4630 init_one_libfunc ("__mips16_fixdfsi"); \
4631 } \
4632 } \
4633 } \
4634 while (0)
4635
4636 #define DFMODE_NAN \
4637 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4638 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4639 #define SFMODE_NAN \
4640 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4641 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
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