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RISC-V: Error if function declared with different interrupt modes.
[official-gcc.git] / gcc / config / rs6000 / rs6000.h
blobf44336ee90ab1b144d006d26985e3c69153e085f
1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
20
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
25
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
28
29 #ifndef RS6000_OPTS_H
30 #include "config/rs6000/rs6000-opts.h"
31 #endif
32
33 /* 128-bit floating point precision values. */
34 #ifndef RS6000_MODES_H
35 #include "config/rs6000/rs6000-modes.h"
36 #endif
37
38 /* Definitions for the object file format. These are set at
39 compile-time. */
40
41 #define OBJECT_XCOFF 1
42 #define OBJECT_ELF 2
43 #define OBJECT_PEF 3
44 #define OBJECT_MACHO 4
45
46 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
47 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
48 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
49 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
50
51 #ifndef TARGET_AIX
52 #define TARGET_AIX 0
53 #endif
54
55 #ifndef TARGET_AIX_OS
56 #define TARGET_AIX_OS 0
57 #endif
58
59 /* Control whether function entry points use a "dot" symbol when
60 ABI_AIX. */
61 #define DOT_SYMBOLS 1
62
63 /* Default string to use for cpu if not specified. */
64 #ifndef TARGET_CPU_DEFAULT
65 #define TARGET_CPU_DEFAULT ((char *)0)
66 #endif
67
68 /* If configured for PPC405, support PPC405CR Erratum77. */
69 #ifdef CONFIG_PPC405CR
70 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
71 #else
72 #define PPC405_ERRATUM77 0
73 #endif
74
75 #ifdef HAVE_AS_POPCNTB
76 #define ASM_CPU_POWER5_SPEC "-mpower5"
77 #else
78 #define ASM_CPU_POWER5_SPEC "-mpower4"
79 #endif
80
81 #ifdef HAVE_AS_DFP
82 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
83 #else
84 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
85 #endif
86
87 #ifdef HAVE_AS_POPCNTD
88 #define ASM_CPU_POWER7_SPEC "-mpower7"
89 #else
90 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
91 #endif
92
93 #ifdef HAVE_AS_POWER8
94 #define ASM_CPU_POWER8_SPEC "-mpower8"
95 #else
96 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC
97 #endif
98
99 #ifdef HAVE_AS_POWER9
100 #define ASM_CPU_POWER9_SPEC "-mpower9"
101 #else
102 #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC
103 #endif
104
105 #ifdef HAVE_AS_DCI
106 #define ASM_CPU_476_SPEC "-m476"
107 #else
108 #define ASM_CPU_476_SPEC "-mpower4"
109 #endif
110
111 /* Common ASM definitions used by ASM_SPEC among the various targets for
112 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
113 provide the default assembler options if the user uses -mcpu=native, so if
114 you make changes here, make them also there. PR63177: Do not pass -mpower8
115 to the assembler if -mpower9-vector was also used. */
116 #define ASM_CPU_SPEC \
117 "%{!mcpu*: \
118 %{mpowerpc64*: -mppc64} \
119 %{!mpowerpc64*: %(asm_default)}} \
120 %{mcpu=native: %(asm_cpu_native)} \
121 %{mcpu=cell: -mcell} \
122 %{mcpu=power3: -mppc64} \
123 %{mcpu=power4: -mpower4} \
124 %{mcpu=power5: %(asm_cpu_power5)} \
125 %{mcpu=power5+: %(asm_cpu_power5)} \
126 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
127 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
128 %{mcpu=power7: %(asm_cpu_power7)} \
129 %{mcpu=power8: %{!mpower9-vector: %(asm_cpu_power8)}} \
130 %{mcpu=power9: %(asm_cpu_power9)} \
131 %{mcpu=a2: -ma2} \
132 %{mcpu=powerpc: -mppc} \
133 %{mcpu=powerpc64le: %(asm_cpu_power8)} \
134 %{mcpu=rs64a: -mppc64} \
135 %{mcpu=401: -mppc} \
136 %{mcpu=403: -m403} \
137 %{mcpu=405: -m405} \
138 %{mcpu=405fp: -m405} \
139 %{mcpu=440: -m440} \
140 %{mcpu=440fp: -m440} \
141 %{mcpu=464: -m440} \
142 %{mcpu=464fp: -m440} \
143 %{mcpu=476: %(asm_cpu_476)} \
144 %{mcpu=476fp: %(asm_cpu_476)} \
145 %{mcpu=505: -mppc} \
146 %{mcpu=601: -m601} \
147 %{mcpu=602: -mppc} \
148 %{mcpu=603: -mppc} \
149 %{mcpu=603e: -mppc} \
150 %{mcpu=ec603e: -mppc} \
151 %{mcpu=604: -mppc} \
152 %{mcpu=604e: -mppc} \
153 %{mcpu=620: -mppc64} \
154 %{mcpu=630: -mppc64} \
155 %{mcpu=740: -mppc} \
156 %{mcpu=750: -mppc} \
157 %{mcpu=G3: -mppc} \
158 %{mcpu=7400: -mppc -maltivec} \
159 %{mcpu=7450: -mppc -maltivec} \
160 %{mcpu=G4: -mppc -maltivec} \
161 %{mcpu=801: -mppc} \
162 %{mcpu=821: -mppc} \
163 %{mcpu=823: -mppc} \
164 %{mcpu=860: -mppc} \
165 %{mcpu=970: -mpower4 -maltivec} \
166 %{mcpu=G5: -mpower4 -maltivec} \
167 %{mcpu=8540: -me500} \
168 %{mcpu=8548: -me500} \
169 %{mcpu=e300c2: -me300} \
170 %{mcpu=e300c3: -me300} \
171 %{mcpu=e500mc: -me500mc} \
172 %{mcpu=e500mc64: -me500mc64} \
173 %{mcpu=e5500: -me5500} \
174 %{mcpu=e6500: -me6500} \
175 %{maltivec: -maltivec} \
176 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
177 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
178 %{mpower9-vector: %{!mcpu*|mcpu=power8: %(asm_cpu_power9)}} \
179 -many"
180
181 #define CPP_DEFAULT_SPEC ""
182
183 #define ASM_DEFAULT_SPEC ""
184
185 /* This macro defines names of additional specifications to put in the specs
186 that can be used in various specifications like CC1_SPEC. Its definition
187 is an initializer with a subgrouping for each command option.
188
189 Each subgrouping contains a string constant, that defines the
190 specification name, and a string constant that used by the GCC driver
191 program.
192
193 Do not define this macro if it does not need to do anything. */
194
195 #define SUBTARGET_EXTRA_SPECS
196
197 #define EXTRA_SPECS \
198 { "cpp_default", CPP_DEFAULT_SPEC }, \
199 { "asm_cpu", ASM_CPU_SPEC }, \
200 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
201 { "asm_default", ASM_DEFAULT_SPEC }, \
202 { "cc1_cpu", CC1_CPU_SPEC }, \
203 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
204 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
205 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
206 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \
207 { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \
208 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
209 SUBTARGET_EXTRA_SPECS
210
211 /* -mcpu=native handling only makes sense with compiler running on
212 an PowerPC chip. If changing this condition, also change
213 the condition in driver-rs6000.c. */
214 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
215 /* In driver-rs6000.c. */
216 extern const char *host_detect_local_cpu (int argc, const char **argv);
217 #define EXTRA_SPEC_FUNCTIONS \
218 { "local_cpu_detect", host_detect_local_cpu },
219 #define HAVE_LOCAL_CPU_DETECT
220 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
221
222 #else
223 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
224 #endif
225
226 #ifndef CC1_CPU_SPEC
227 #ifdef HAVE_LOCAL_CPU_DETECT
228 #define CC1_CPU_SPEC \
229 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
230 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
231 #else
232 #define CC1_CPU_SPEC ""
233 #endif
234 #endif
235
236 /* Architecture type. */
237
238 /* Define TARGET_MFCRF if the target assembler does not support the
239 optional field operand for mfcr. */
240
241 #ifndef HAVE_AS_MFCRF
242 #undef TARGET_MFCRF
243 #define TARGET_MFCRF 0
244 #endif
245
246 /* Define TARGET_POPCNTB if the target assembler does not support the
247 popcount byte instruction. */
248
249 #ifndef HAVE_AS_POPCNTB
250 #undef TARGET_POPCNTB
251 #define TARGET_POPCNTB 0
252 #endif
253
254 /* Define TARGET_FPRND if the target assembler does not support the
255 fp rounding instructions. */
256
257 #ifndef HAVE_AS_FPRND
258 #undef TARGET_FPRND
259 #define TARGET_FPRND 0
260 #endif
261
262 /* Define TARGET_CMPB if the target assembler does not support the
263 cmpb instruction. */
264
265 #ifndef HAVE_AS_CMPB
266 #undef TARGET_CMPB
267 #define TARGET_CMPB 0
268 #endif
269
270 /* Define TARGET_MFPGPR if the target assembler does not support the
271 mffpr and mftgpr instructions. */
272
273 #ifndef HAVE_AS_MFPGPR
274 #undef TARGET_MFPGPR
275 #define TARGET_MFPGPR 0
276 #endif
277
278 /* Define TARGET_DFP if the target assembler does not support decimal
279 floating point instructions. */
280 #ifndef HAVE_AS_DFP
281 #undef TARGET_DFP
282 #define TARGET_DFP 0
283 #endif
284
285 /* Define TARGET_POPCNTD if the target assembler does not support the
286 popcount word and double word instructions. */
287
288 #ifndef HAVE_AS_POPCNTD
289 #undef TARGET_POPCNTD
290 #define TARGET_POPCNTD 0
291 #endif
292
293 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the
294 waitasecond instruction. Allow -mpower8-fusion, since it does not add new
295 instructions. */
296
297 #ifndef HAVE_AS_POWER8
298 #undef TARGET_DIRECT_MOVE
299 #undef TARGET_CRYPTO
300 #undef TARGET_HTM
301 #undef TARGET_P8_VECTOR
302 #define TARGET_DIRECT_MOVE 0
303 #define TARGET_CRYPTO 0
304 #define TARGET_HTM 0
305 #define TARGET_P8_VECTOR 0
306 #endif
307
308 /* Define the ISA 3.0 flags as 0 if the target assembler does not support
309 Power9 instructions. Allow -mpower9-fusion, since it does not add new
310 instructions. Allow -misel, since it predates ISA 3.0 and does
311 not require any Power9 features. */
312
313 #ifndef HAVE_AS_POWER9
314 #undef TARGET_FLOAT128_HW
315 #undef TARGET_MODULO
316 #undef TARGET_P9_VECTOR
317 #undef TARGET_P9_MINMAX
318 #undef TARGET_P9_MISC
319 #define TARGET_FLOAT128_HW 0
320 #define TARGET_MODULO 0
321 #define TARGET_P9_VECTOR 0
322 #define TARGET_P9_MINMAX 0
323 #define TARGET_P9_MISC 0
324 #endif
325
326 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
327 not, generate the lwsync code as an integer constant. */
328 #ifdef HAVE_AS_LWSYNC
329 #define TARGET_LWSYNC_INSTRUCTION 1
330 #else
331 #define TARGET_LWSYNC_INSTRUCTION 0
332 #endif
333
334 /* Define TARGET_TLS_MARKERS if the target assembler does not support
335 arg markers for __tls_get_addr calls. */
336 #ifndef HAVE_AS_TLS_MARKERS
337 #undef TARGET_TLS_MARKERS
338 #define TARGET_TLS_MARKERS 0
339 #else
340 #define TARGET_TLS_MARKERS tls_markers
341 #endif
342
343 #ifndef TARGET_SECURE_PLT
344 #define TARGET_SECURE_PLT 0
345 #endif
346
347 #ifndef TARGET_CMODEL
348 #define TARGET_CMODEL CMODEL_SMALL
349 #endif
350
351 #define TARGET_32BIT (! TARGET_64BIT)
352
353 #ifndef HAVE_AS_TLS
354 #define HAVE_AS_TLS 0
355 #endif
356
357 #ifndef TARGET_LINK_STACK
358 #define TARGET_LINK_STACK 0
359 #endif
360
361 #ifndef SET_TARGET_LINK_STACK
362 #define SET_TARGET_LINK_STACK(X) do { } while (0)
363 #endif
364
365 #ifndef TARGET_FLOAT128_ENABLE_TYPE
366 #define TARGET_FLOAT128_ENABLE_TYPE 0
367 #endif
368
369 /* Return 1 for a symbol ref for a thread-local storage symbol. */
370 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
371 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
372
373 #ifdef IN_LIBGCC2
374 /* For libgcc2 we make sure this is a compile time constant */
375 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
376 #undef TARGET_POWERPC64
377 #define TARGET_POWERPC64 1
378 #else
379 #undef TARGET_POWERPC64
380 #define TARGET_POWERPC64 0
381 #endif
382 #else
383 /* The option machinery will define this. */
384 #endif
385
386 #define TARGET_DEFAULT (MASK_MULTIPLE)
387
388 /* Define generic processor types based upon current deployment. */
389 #define PROCESSOR_COMMON PROCESSOR_PPC601
390 #define PROCESSOR_POWERPC PROCESSOR_PPC604
391 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
392
393 /* Define the default processor. This is overridden by other tm.h files. */
394 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
395 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
396
397 /* Specify the dialect of assembler to use. Only new mnemonics are supported
398 starting with GCC 4.8, i.e. just one dialect, but for backwards
399 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
400 defined. */
401 #define ASSEMBLER_DIALECT 1
402
403 /* Debug support */
404 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
405 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
406 #define MASK_DEBUG_REG 0x04 /* debug register handling */
407 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
408 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
409 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
410 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
411 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
412 | MASK_DEBUG_ARG \
413 | MASK_DEBUG_REG \
414 | MASK_DEBUG_ADDR \
415 | MASK_DEBUG_COST \
416 | MASK_DEBUG_TARGET \
417 | MASK_DEBUG_BUILTIN)
418
419 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
420 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
421 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
422 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
423 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
424 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
425 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
426
427 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
428 long double format that uses a pair of doubles, or IEEE 128-bit floating
429 point. KFmode was added as a way to represent IEEE 128-bit floating point,
430 even if the default for long double is the IBM long double format.
431 Similarly IFmode is the IBM long double format even if the default is IEEE
432 128-bit. Don't allow IFmode if -msoft-float. */
433 #define FLOAT128_IEEE_P(MODE) \
434 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
435 && ((MODE) == TFmode || (MODE) == TCmode)) \
436 || ((MODE) == KFmode) || ((MODE) == KCmode))
437
438 #define FLOAT128_IBM_P(MODE) \
439 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
440 && ((MODE) == TFmode || (MODE) == TCmode)) \
441 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
442
443 /* Helper macros to say whether a 128-bit floating point type can go in a
444 single vector register, or whether it needs paired scalar values. */
445 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
446
447 #define FLOAT128_2REG_P(MODE) \
448 (FLOAT128_IBM_P (MODE) \
449 || ((MODE) == TDmode) \
450 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
451
452 /* Return true for floating point that does not use a vector register. */
453 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
454 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
455
456 /* Describe the vector unit used for arithmetic operations. */
457 extern enum rs6000_vector rs6000_vector_unit[];
458
459 #define VECTOR_UNIT_NONE_P(MODE) \
460 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
461
462 #define VECTOR_UNIT_VSX_P(MODE) \
463 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
464
465 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
466 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
467
468 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
469 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
470
471 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
472 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
473 (int)VECTOR_VSX, \
474 (int)VECTOR_P8_VECTOR))
475
476 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
477 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
478 compatible, so allow it as well, rather than changing all of the uses of the
479 macro. */
480 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
481 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
482 (int)VECTOR_ALTIVEC, \
483 (int)VECTOR_P8_VECTOR))
484
485 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
486 same unit as the vector unit we are using, but we may want to migrate to
487 using VSX style loads even for types handled by altivec. */
488 extern enum rs6000_vector rs6000_vector_mem[];
489
490 #define VECTOR_MEM_NONE_P(MODE) \
491 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
492
493 #define VECTOR_MEM_VSX_P(MODE) \
494 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
495
496 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
497 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
498
499 #define VECTOR_MEM_ALTIVEC_P(MODE) \
500 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
501
502 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
503 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
504 (int)VECTOR_VSX, \
505 (int)VECTOR_P8_VECTOR))
506
507 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
508 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
509 (int)VECTOR_ALTIVEC, \
510 (int)VECTOR_P8_VECTOR))
511
512 /* Return the alignment of a given vector type, which is set based on the
513 vector unit use. VSX for instance can load 32 or 64 bit aligned words
514 without problems, while Altivec requires 128-bit aligned vectors. */
515 extern int rs6000_vector_align[];
516
517 #define VECTOR_ALIGN(MODE) \
518 ((rs6000_vector_align[(MODE)] != 0) \
519 ? rs6000_vector_align[(MODE)] \
520 : (int)GET_MODE_BITSIZE ((MODE)))
521
522 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
523 with scalar instructions. */
524 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
525
526 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
527 with the ISA 3.0 MFVSRLD instructions. */
528 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
529
530 /* Alignment options for fields in structures for sub-targets following
531 AIX-like ABI.
532 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
533 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
534
535 Override the macro definitions when compiling libobjc to avoid undefined
536 reference to rs6000_alignment_flags due to library's use of GCC alignment
537 macros which use the macros below. */
538
539 #ifndef IN_TARGET_LIBS
540 #define MASK_ALIGN_POWER 0x00000000
541 #define MASK_ALIGN_NATURAL 0x00000001
542 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
543 #else
544 #define TARGET_ALIGN_NATURAL 0
545 #endif
546
547 /* We use values 126..128 to pick the appropriate long double type (IFmode,
548 KFmode, TFmode). */
549 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
550 #define TARGET_IEEEQUAD rs6000_ieeequad
551 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
552 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
553
554 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
555 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
556 #define TARGET_FCFID (TARGET_POWERPC64 \
557 || TARGET_PPC_GPOPT /* 970/power4 */ \
558 || TARGET_POPCNTB /* ISA 2.02 */ \
559 || TARGET_CMPB /* ISA 2.05 */ \
560 || TARGET_POPCNTD) /* ISA 2.06 */
561
562 #define TARGET_FCTIDZ TARGET_FCFID
563 #define TARGET_STFIWX TARGET_PPC_GFXOPT
564 #define TARGET_LFIWAX TARGET_CMPB
565 #define TARGET_LFIWZX TARGET_POPCNTD
566 #define TARGET_FCFIDS TARGET_POPCNTD
567 #define TARGET_FCFIDU TARGET_POPCNTD
568 #define TARGET_FCFIDUS TARGET_POPCNTD
569 #define TARGET_FCTIDUZ TARGET_POPCNTD
570 #define TARGET_FCTIWUZ TARGET_POPCNTD
571 #define TARGET_CTZ TARGET_MODULO
572 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
573 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
574
575 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
576 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
577 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
578 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
579 && TARGET_POWERPC64)
580 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
581 && TARGET_POWERPC64)
582
583 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
584 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
585 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
586
587 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
588 loads are slow. */
589 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
590
591 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
592 in power7, so conditionalize them on p8 features. TImode syncs need quad
593 memory support. */
594 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
595 || TARGET_QUAD_MEMORY_ATOMIC \
596 || TARGET_DIRECT_MOVE)
597
598 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
599
600 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
601 to allocate the SDmode stack slot to get the value into the proper location
602 in the register. */
603 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
604
605 /* ISA 3.0 has new min/max functions that don't need fast math that are being
606 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
607 answers if the arguments are not in the normal range. */
608 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
609 && (TARGET_P9_MINMAX || !flag_trapping_math))
610
611 /* In switching from using target_flags to using rs6000_isa_flags, the options
612 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
613 OPTION_MASK_<xxx> back into MASK_<xxx>. */
614 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
615 #define MASK_CMPB OPTION_MASK_CMPB
616 #define MASK_CRYPTO OPTION_MASK_CRYPTO
617 #define MASK_DFP OPTION_MASK_DFP
618 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
619 #define MASK_DLMZB OPTION_MASK_DLMZB
620 #define MASK_EABI OPTION_MASK_EABI
621 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
622 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
623 #define MASK_FPRND OPTION_MASK_FPRND
624 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
625 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
626 #define MASK_HTM OPTION_MASK_HTM
627 #define MASK_ISEL OPTION_MASK_ISEL
628 #define MASK_MFCRF OPTION_MASK_MFCRF
629 #define MASK_MFPGPR OPTION_MASK_MFPGPR
630 #define MASK_MULHW OPTION_MASK_MULHW
631 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
632 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
633 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
634 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
635 #define MASK_P9_MISC OPTION_MASK_P9_MISC
636 #define MASK_POPCNTB OPTION_MASK_POPCNTB
637 #define MASK_POPCNTD OPTION_MASK_POPCNTD
638 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
639 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
640 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
641 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
642 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
643 #define MASK_UPDATE OPTION_MASK_UPDATE
644 #define MASK_VSX OPTION_MASK_VSX
645
646 #ifndef IN_LIBGCC2
647 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
648 #endif
649
650 #ifdef TARGET_64BIT
651 #define MASK_64BIT OPTION_MASK_64BIT
652 #endif
653
654 #ifdef TARGET_LITTLE_ENDIAN
655 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
656 #endif
657
658 #ifdef TARGET_REGNAMES
659 #define MASK_REGNAMES OPTION_MASK_REGNAMES
660 #endif
661
662 #ifdef TARGET_PROTOTYPE
663 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
664 #endif
665
666 #ifdef TARGET_MODULO
667 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
668 #endif
669
670
671 /* For power systems, we want to enable Altivec and VSX builtins even if the
672 user did not use -maltivec or -mvsx to allow the builtins to be used inside
673 of #pragma GCC target or the target attribute to change the code level for a
674 given system. */
675
676 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
677 || TARGET_PPC_GPOPT /* 970/power4 */ \
678 || TARGET_POPCNTB /* ISA 2.02 */ \
679 || TARGET_CMPB /* ISA 2.05 */ \
680 || TARGET_POPCNTD /* ISA 2.06 */ \
681 || TARGET_ALTIVEC \
682 || TARGET_VSX \
683 || TARGET_HARD_FLOAT)
684
685 /* E500 cores only support plain "sync", not lwsync. */
686 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
687 || rs6000_cpu == PROCESSOR_PPC8548)
688
689
690 /* Which machine supports the various reciprocal estimate instructions. */
691 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
692
693 #define TARGET_FRE (TARGET_HARD_FLOAT \
694 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
695
696 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
697 && TARGET_PPC_GFXOPT)
698
699 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
700 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
701
702 /* Conditions to allow TOC fusion for loading/storing integers. */
703 #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \
704 && TARGET_TOC_FUSION \
705 && (TARGET_CMODEL != CMODEL_SMALL) \
706 && TARGET_POWERPC64)
707
708 /* Conditions to allow TOC fusion for loading/storing floating point. */
709 #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \
710 && TARGET_TOC_FUSION \
711 && (TARGET_CMODEL != CMODEL_SMALL) \
712 && TARGET_POWERPC64 \
713 && TARGET_HARD_FLOAT)
714
715 /* Macro to say whether we can do optimizations where we need to do parts of
716 the calculation in 64-bit GPRs and then is transfered to the vector
717 registers. */
718 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
719 && TARGET_P8_VECTOR \
720 && TARGET_POWERPC64)
721
722 /* Whether the various reciprocal divide/square root estimate instructions
723 exist, and whether we should automatically generate code for the instruction
724 by default. */
725 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
726 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
727 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
728 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
729
730 extern unsigned char rs6000_recip_bits[];
731
732 #define RS6000_RECIP_HAVE_RE_P(MODE) \
733 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
734
735 #define RS6000_RECIP_AUTO_RE_P(MODE) \
736 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
737
738 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
739 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
740
741 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
742 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
743
744 /* The default CPU for TARGET_OPTION_OVERRIDE. */
745 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
746
747 /* Target pragma. */
748 #define REGISTER_TARGET_PRAGMAS() do { \
749 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
750 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
751 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
752 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
753 } while (0)
754
755 /* Target #defines. */
756 #define TARGET_CPU_CPP_BUILTINS() \
757 rs6000_cpu_cpp_builtins (pfile)
758
759 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
760 we're compiling for. Some configurations may need to override it. */
761 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
762 do \
763 { \
764 if (BYTES_BIG_ENDIAN) \
765 { \
766 builtin_define ("__BIG_ENDIAN__"); \
767 builtin_define ("_BIG_ENDIAN"); \
768 builtin_assert ("machine=bigendian"); \
769 } \
770 else \
771 { \
772 builtin_define ("__LITTLE_ENDIAN__"); \
773 builtin_define ("_LITTLE_ENDIAN"); \
774 builtin_assert ("machine=littleendian"); \
775 } \
776 } \
777 while (0)
778 \f
779 /* Target machine storage layout. */
780
781 /* Define this macro if it is advisable to hold scalars in registers
782 in a wider mode than that declared by the program. In such cases,
783 the value is constrained to be within the bounds of the declared
784 type, but kept valid in the wider mode. The signedness of the
785 extension may differ from that of the type. */
786
787 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
788 if (GET_MODE_CLASS (MODE) == MODE_INT \
789 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
790 (MODE) = TARGET_32BIT ? SImode : DImode;
791
792 /* Define this if most significant bit is lowest numbered
793 in instructions that operate on numbered bit-fields. */
794 /* That is true on RS/6000. */
795 #define BITS_BIG_ENDIAN 1
796
797 /* Define this if most significant byte of a word is the lowest numbered. */
798 /* That is true on RS/6000. */
799 #define BYTES_BIG_ENDIAN 1
800
801 /* Define this if most significant word of a multiword number is lowest
802 numbered.
803
804 For RS/6000 we can decide arbitrarily since there are no machine
805 instructions for them. Might as well be consistent with bits and bytes. */
806 #define WORDS_BIG_ENDIAN 1
807
808 /* This says that for the IBM long double the larger magnitude double
809 comes first. It's really a two element double array, and arrays
810 don't index differently between little- and big-endian. */
811 #define LONG_DOUBLE_LARGE_FIRST 1
812
813 #define MAX_BITS_PER_WORD 64
814
815 /* Width of a word, in units (bytes). */
816 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
817 #ifdef IN_LIBGCC2
818 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
819 #else
820 #define MIN_UNITS_PER_WORD 4
821 #endif
822 #define UNITS_PER_FP_WORD 8
823 #define UNITS_PER_ALTIVEC_WORD 16
824 #define UNITS_PER_VSX_WORD 16
825
826 /* Type used for ptrdiff_t, as a string used in a declaration. */
827 #define PTRDIFF_TYPE "int"
828
829 /* Type used for size_t, as a string used in a declaration. */
830 #define SIZE_TYPE "long unsigned int"
831
832 /* Type used for wchar_t, as a string used in a declaration. */
833 #define WCHAR_TYPE "short unsigned int"
834
835 /* Width of wchar_t in bits. */
836 #define WCHAR_TYPE_SIZE 16
837
838 /* A C expression for the size in bits of the type `short' on the
839 target machine. If you don't define this, the default is half a
840 word. (If this would be less than one storage unit, it is
841 rounded up to one unit.) */
842 #define SHORT_TYPE_SIZE 16
843
844 /* A C expression for the size in bits of the type `int' on the
845 target machine. If you don't define this, the default is one
846 word. */
847 #define INT_TYPE_SIZE 32
848
849 /* A C expression for the size in bits of the type `long' on the
850 target machine. If you don't define this, the default is one
851 word. */
852 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
853
854 /* A C expression for the size in bits of the type `long long' on the
855 target machine. If you don't define this, the default is two
856 words. */
857 #define LONG_LONG_TYPE_SIZE 64
858
859 /* A C expression for the size in bits of the type `float' on the
860 target machine. If you don't define this, the default is one
861 word. */
862 #define FLOAT_TYPE_SIZE 32
863
864 /* A C expression for the size in bits of the type `double' on the
865 target machine. If you don't define this, the default is two
866 words. */
867 #define DOUBLE_TYPE_SIZE 64
868
869 /* A C expression for the size in bits of the type `long double' on the target
870 machine. If you don't define this, the default is two words. */
871 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
872
873 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
874 #define WIDEST_HARDWARE_FP_SIZE 64
875
876 /* Width in bits of a pointer.
877 See also the macro `Pmode' defined below. */
878 extern unsigned rs6000_pointer_size;
879 #define POINTER_SIZE rs6000_pointer_size
880
881 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
882 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
883
884 /* Boundary (in *bits*) on which stack pointer should be aligned. */
885 #define STACK_BOUNDARY \
886 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
887 ? 64 : 128)
888
889 /* Allocation boundary (in *bits*) for the code of a function. */
890 #define FUNCTION_BOUNDARY 32
891
892 /* No data type wants to be aligned rounder than this. */
893 #define BIGGEST_ALIGNMENT 128
894
895 /* Alignment of field after `int : 0' in a structure. */
896 #define EMPTY_FIELD_BOUNDARY 32
897
898 /* Every structure's size must be a multiple of this. */
899 #define STRUCTURE_SIZE_BOUNDARY 8
900
901 /* A bit-field declared as `int' forces `int' alignment for the struct. */
902 #define PCC_BITFIELD_TYPE_MATTERS 1
903
904 enum data_align { align_abi, align_opt, align_both };
905
906 /* A C expression to compute the alignment for a variables in the
907 local store. TYPE is the data type, and ALIGN is the alignment
908 that the object would ordinarily have. */
909 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
910 rs6000_data_alignment (TYPE, ALIGN, align_both)
911
912 /* Make arrays of chars word-aligned for the same reasons. */
913 #define DATA_ALIGNMENT(TYPE, ALIGN) \
914 rs6000_data_alignment (TYPE, ALIGN, align_opt)
915
916 /* Align vectors to 128 bits. */
917 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
918 rs6000_data_alignment (TYPE, ALIGN, align_abi)
919
920 /* Nonzero if move instructions will actually fail to work
921 when given unaligned data. */
922 #define STRICT_ALIGNMENT 0
923 \f
924 /* Standard register usage. */
925
926 /* Number of actual hardware registers.
927 The hardware registers are assigned numbers for the compiler
928 from 0 to just below FIRST_PSEUDO_REGISTER.
929 All registers that the compiler knows about must be given numbers,
930 even those that are not normally considered general registers.
931
932 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
933 a count register, a link register, and 8 condition register fields,
934 which we view here as separate registers. AltiVec adds 32 vector
935 registers and a VRsave register.
936
937 In addition, the difference between the frame and argument pointers is
938 a function of the number of registers saved, so we need to have a
939 register for AP that will later be eliminated in favor of SP or FP.
940 This is a normal register, but it is fixed.
941
942 We also create a pseudo register for float/int conversions, that will
943 really represent the memory location used. It is represented here as
944 a register, in order to work around problems in allocating stack storage
945 in inline functions.
946
947 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
948 pointer, which is eventually eliminated in favor of SP or FP.
949
950 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
951
952 #define FIRST_PSEUDO_REGISTER 115
953
954 /* This must be included for pre gcc 3.0 glibc compatibility. */
955 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
956
957 /* The sfp register and 3 HTM registers
958 aren't included in DWARF_FRAME_REGISTERS. */
959 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
960
961 /* Use standard DWARF numbering for DWARF debugging information. */
962 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
963
964 /* Use gcc hard register numbering for eh_frame. */
965 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
966
967 /* Map register numbers held in the call frame info that gcc has
968 collected using DWARF_FRAME_REGNUM to those that should be output in
969 .debug_frame and .eh_frame. */
970 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
971 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1)
972
973 /* 1 for registers that have pervasive standard uses
974 and are not available for the register allocator.
975
976 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
977 as a local register; for all other OS's r2 is the TOC pointer.
978
979 On System V implementations, r13 is fixed and not available for use. */
980
981 #define FIXED_REGISTERS \
982 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
983 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
984 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
985 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
986 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
987 /* AltiVec registers. */ \
988 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
989 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
990 1, 1 \
991 , 1, 1, 1, 1 \
992 }
993
994 /* 1 for registers not available across function calls.
995 These must include the FIXED_REGISTERS and also any
996 registers that can be used without being saved.
997 The latter must include the registers where values are returned
998 and the register where structure-value addresses are passed.
999 Aside from that, you can include as many other registers as you like. */
1000
1001 #define CALL_USED_REGISTERS \
1002 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1003 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1004 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1005 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1006 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1007 /* AltiVec registers. */ \
1008 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1009 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1010 1, 1 \
1011 , 1, 1, 1, 1 \
1012 }
1013
1014 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
1015 the entire set of `FIXED_REGISTERS' be included.
1016 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
1017 This macro is optional. If not specified, it defaults to the value
1018 of `CALL_USED_REGISTERS'. */
1019
1020 #define CALL_REALLY_USED_REGISTERS \
1021 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1022 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1023 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1024 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1025 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1026 /* AltiVec registers. */ \
1027 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1028 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1029 0, 0 \
1030 , 0, 0, 0, 0 \
1031 }
1032
1033 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
1034
1035 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
1036 #define FIRST_SAVED_FP_REGNO (14+32)
1037 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
1038
1039 /* List the order in which to allocate registers. Each register must be
1040 listed once, even those in FIXED_REGISTERS.
1041
1042 We allocate in the following order:
1043 fp0 (not saved or used for anything)
1044 fp13 - fp2 (not saved; incoming fp arg registers)
1045 fp1 (not saved; return value)
1046 fp31 - fp14 (saved; order given to save least number)
1047 cr7, cr5 (not saved or special)
1048 cr6 (not saved, but used for vector operations)
1049 cr1 (not saved, but used for FP operations)
1050 cr0 (not saved, but used for arithmetic operations)
1051 cr4, cr3, cr2 (saved)
1052 r9 (not saved; best for TImode)
1053 r10, r8-r4 (not saved; highest first for less conflict with params)
1054 r3 (not saved; return value register)
1055 r11 (not saved; later alloc to help shrink-wrap)
1056 r0 (not saved; cannot be base reg)
1057 r31 - r13 (saved; order given to save least number)
1058 r12 (not saved; if used for DImode or DFmode would use r13)
1059 ctr (not saved; when we have the choice ctr is better)
1060 lr (saved)
1061 r1, r2, ap, ca (fixed)
1062 v0 - v1 (not saved or used for anything)
1063 v13 - v3 (not saved; incoming vector arg registers)
1064 v2 (not saved; incoming vector arg reg; return value)
1065 v19 - v14 (not saved or used for anything)
1066 v31 - v20 (saved; order given to save least number)
1067 vrsave, vscr (fixed)
1068 sfp (fixed)
1069 tfhar (fixed)
1070 tfiar (fixed)
1071 texasr (fixed)
1072 */
1073
1074 #if FIXED_R2 == 1
1075 #define MAYBE_R2_AVAILABLE
1076 #define MAYBE_R2_FIXED 2,
1077 #else
1078 #define MAYBE_R2_AVAILABLE 2,
1079 #define MAYBE_R2_FIXED
1080 #endif
1081
1082 #if FIXED_R13 == 1
1083 #define EARLY_R12 12,
1084 #define LATE_R12
1085 #else
1086 #define EARLY_R12
1087 #define LATE_R12 12,
1088 #endif
1089
1090 #define REG_ALLOC_ORDER \
1091 {32, \
1092 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
1093 /* not use fr14 which is a saved register. */ \
1094 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
1095 33, \
1096 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1097 50, 49, 48, 47, 46, \
1098 75, 73, 74, 69, 68, 72, 71, 70, \
1099 MAYBE_R2_AVAILABLE \
1100 9, 10, 8, 7, 6, 5, 4, \
1101 3, EARLY_R12 11, 0, \
1102 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1103 18, 17, 16, 15, 14, 13, LATE_R12 \
1104 66, 65, \
1105 1, MAYBE_R2_FIXED 67, 76, \
1106 /* AltiVec registers. */ \
1107 77, 78, \
1108 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
1109 79, \
1110 96, 95, 94, 93, 92, 91, \
1111 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1112 109, 110, \
1113 111, 112, 113, 114 \
1114 }
1115
1116 /* True if register is floating-point. */
1117 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1118
1119 /* True if register is a condition register. */
1120 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
1121
1122 /* True if register is a condition register, but not cr0. */
1123 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1124
1125 /* True if register is an integer register. */
1126 #define INT_REGNO_P(N) \
1127 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1128
1129 /* True if register is the CA register. */
1130 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1131
1132 /* True if register is an AltiVec register. */
1133 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1134
1135 /* True if register is a VSX register. */
1136 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1137
1138 /* Alternate name for any vector register supporting floating point, no matter
1139 which instruction set(s) are available. */
1140 #define VFLOAT_REGNO_P(N) \
1141 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1142
1143 /* Alternate name for any vector register supporting integer, no matter which
1144 instruction set(s) are available. */
1145 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1146
1147 /* Alternate name for any vector register supporting logical operations, no
1148 matter which instruction set(s) are available. Allow GPRs as well as the
1149 vector registers. */
1150 #define VLOGICAL_REGNO_P(N) \
1151 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1152 || (TARGET_VSX && FP_REGNO_P (N))) \
1153
1154 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1155 enough space to account for vectors in FP regs. However, TFmode/TDmode
1156 should not use VSX instructions to do a caller save. */
1157 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1158 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1159 ? (MODE) \
1160 : TARGET_VSX \
1161 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1162 && FP_REGNO_P (REGNO) \
1163 ? V2DFmode \
1164 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1165 ? DFmode \
1166 : (MODE) == TDmode && FP_REGNO_P (REGNO) \
1167 ? DImode \
1168 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1169
1170 #define VSX_VECTOR_MODE(MODE) \
1171 ((MODE) == V4SFmode \
1172 || (MODE) == V2DFmode) \
1173
1174 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1175 really a vector, but we want to treat it as a vector for moves, and
1176 such. */
1177
1178 #define ALTIVEC_VECTOR_MODE(MODE) \
1179 ((MODE) == V16QImode \
1180 || (MODE) == V8HImode \
1181 || (MODE) == V4SFmode \
1182 || (MODE) == V4SImode \
1183 || FLOAT128_VECTOR_P (MODE))
1184
1185 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1186 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1187 || (MODE) == V2DImode || (MODE) == V1TImode)
1188
1189 /* Post-reload, we can't use any new AltiVec registers, as we already
1190 emitted the vrsave mask. */
1191
1192 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1193 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1194
1195 /* Specify the cost of a branch insn; roughly the number of extra insns that
1196 should be added to avoid a branch.
1197
1198 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1199 unscheduled conditional branch. */
1200
1201 #define BRANCH_COST(speed_p, predictable_p) 3
1202
1203 /* Override BRANCH_COST heuristic which empirically produces worse
1204 performance for removing short circuiting from the logical ops. */
1205
1206 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1207
1208 /* Specify the registers used for certain standard purposes.
1209 The values of these macros are register numbers. */
1210
1211 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1212 /* #define PC_REGNUM */
1213
1214 /* Register to use for pushing function arguments. */
1215 #define STACK_POINTER_REGNUM 1
1216
1217 /* Base register for access to local variables of the function. */
1218 #define HARD_FRAME_POINTER_REGNUM 31
1219
1220 /* Base register for access to local variables of the function. */
1221 #define FRAME_POINTER_REGNUM 111
1222
1223 /* Base register for access to arguments of the function. */
1224 #define ARG_POINTER_REGNUM 67
1225
1226 /* Place to put static chain when calling a function that requires it. */
1227 #define STATIC_CHAIN_REGNUM 11
1228
1229 /* Base register for access to thread local storage variables. */
1230 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1231
1232 \f
1233 /* Define the classes of registers for register constraints in the
1234 machine description. Also define ranges of constants.
1235
1236 One of the classes must always be named ALL_REGS and include all hard regs.
1237 If there is more than one class, another class must be named NO_REGS
1238 and contain no registers.
1239
1240 The name GENERAL_REGS must be the name of a class (or an alias for
1241 another name such as ALL_REGS). This is the class of registers
1242 that is allowed by "g" or "r" in a register constraint.
1243 Also, registers outside this class are allocated only when
1244 instructions express preferences for them.
1245
1246 The classes must be numbered in nondecreasing order; that is,
1247 a larger-numbered class must never be contained completely
1248 in a smaller-numbered class.
1249
1250 For any two classes, it is very desirable that there be another
1251 class that represents their union. */
1252
1253 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1254 condition registers, plus three special registers, CTR, and the link
1255 register. AltiVec adds a vector register class. VSX registers overlap the
1256 FPR registers and the Altivec registers.
1257
1258 However, r0 is special in that it cannot be used as a base register.
1259 So make a class for registers valid as base registers.
1260
1261 Also, cr0 is the only condition code register that can be used in
1262 arithmetic insns, so make a separate class for it. */
1263
1264 enum reg_class
1265 {
1266 NO_REGS,
1267 BASE_REGS,
1268 GENERAL_REGS,
1269 FLOAT_REGS,
1270 ALTIVEC_REGS,
1271 VSX_REGS,
1272 VRSAVE_REGS,
1273 VSCR_REGS,
1274 SPR_REGS,
1275 NON_SPECIAL_REGS,
1276 LINK_REGS,
1277 CTR_REGS,
1278 LINK_OR_CTR_REGS,
1279 SPECIAL_REGS,
1280 SPEC_OR_GEN_REGS,
1281 CR0_REGS,
1282 CR_REGS,
1283 NON_FLOAT_REGS,
1284 CA_REGS,
1285 ALL_REGS,
1286 LIM_REG_CLASSES
1287 };
1288
1289 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1290
1291 /* Give names of register classes as strings for dump file. */
1292
1293 #define REG_CLASS_NAMES \
1294 { \
1295 "NO_REGS", \
1296 "BASE_REGS", \
1297 "GENERAL_REGS", \
1298 "FLOAT_REGS", \
1299 "ALTIVEC_REGS", \
1300 "VSX_REGS", \
1301 "VRSAVE_REGS", \
1302 "VSCR_REGS", \
1303 "SPR_REGS", \
1304 "NON_SPECIAL_REGS", \
1305 "LINK_REGS", \
1306 "CTR_REGS", \
1307 "LINK_OR_CTR_REGS", \
1308 "SPECIAL_REGS", \
1309 "SPEC_OR_GEN_REGS", \
1310 "CR0_REGS", \
1311 "CR_REGS", \
1312 "NON_FLOAT_REGS", \
1313 "CA_REGS", \
1314 "ALL_REGS" \
1315 }
1316
1317 /* Define which registers fit in which classes.
1318 This is an initializer for a vector of HARD_REG_SET
1319 of length N_REG_CLASSES. */
1320
1321 #define REG_CLASS_CONTENTS \
1322 { \
1323 /* NO_REGS. */ \
1324 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1325 /* BASE_REGS. */ \
1326 { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \
1327 /* GENERAL_REGS. */ \
1328 { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \
1329 /* FLOAT_REGS. */ \
1330 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
1331 /* ALTIVEC_REGS. */ \
1332 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \
1333 /* VSX_REGS. */ \
1334 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \
1335 /* VRSAVE_REGS. */ \
1336 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
1337 /* VSCR_REGS. */ \
1338 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
1339 /* SPR_REGS. */ \
1340 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
1341 /* NON_SPECIAL_REGS. */ \
1342 { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \
1343 /* LINK_REGS. */ \
1344 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
1345 /* CTR_REGS. */ \
1346 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \
1347 /* LINK_OR_CTR_REGS. */ \
1348 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \
1349 /* SPECIAL_REGS. */ \
1350 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \
1351 /* SPEC_OR_GEN_REGS. */ \
1352 { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \
1353 /* CR0_REGS. */ \
1354 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
1355 /* CR_REGS. */ \
1356 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
1357 /* NON_FLOAT_REGS. */ \
1358 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \
1359 /* CA_REGS. */ \
1360 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
1361 /* ALL_REGS. */ \
1362 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \
1363 }
1364
1365 /* The same information, inverted:
1366 Return the class number of the smallest class containing
1367 reg number REGNO. This could be a conditional expression
1368 or could index an array. */
1369
1370 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1371
1372 #define REGNO_REG_CLASS(REGNO) \
1373 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1374 rs6000_regno_regclass[(REGNO)])
1375
1376 /* Register classes for various constraints that are based on the target
1377 switches. */
1378 enum r6000_reg_class_enum {
1379 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1380 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1381 RS6000_CONSTRAINT_v, /* Altivec registers */
1382 RS6000_CONSTRAINT_wa, /* Any VSX register */
1383 RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */
1384 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1385 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
1386 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1387 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
1388 RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */
1389 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
1390 RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */
1391 RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
1392 RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
1393 RS6000_CONSTRAINT_wm, /* VSX register for direct move */
1394 RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */
1395 RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
1396 RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
1397 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
1398 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1399 RS6000_CONSTRAINT_wt, /* VSX register for TImode */
1400 RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */
1401 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
1402 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
1403 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
1404 RS6000_CONSTRAINT_wy, /* VSX register for SF */
1405 RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */
1406 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
1407 RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
1408 RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
1409 RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */
1410 RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */
1411 RS6000_CONSTRAINT_MAX
1412 };
1413
1414 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1415
1416 /* The class value for index registers, and the one for base regs. */
1417 #define INDEX_REG_CLASS GENERAL_REGS
1418 #define BASE_REG_CLASS BASE_REGS
1419
1420 /* Return whether a given register class can hold VSX objects. */
1421 #define VSX_REG_CLASS_P(CLASS) \
1422 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1423
1424 /* Return whether a given register class targets general purpose registers. */
1425 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1426
1427 /* Given an rtx X being reloaded into a reg required to be
1428 in class CLASS, return the class of reg to actually use.
1429 In general this is just CLASS; but on some machines
1430 in some cases it is preferable to use a more restrictive class.
1431
1432 On the RS/6000, we have to return NO_REGS when we want to reload a
1433 floating-point CONST_DOUBLE to force it to be copied to memory.
1434
1435 We also don't want to reload integer values into floating-point
1436 registers if we can at all help it. In fact, this can
1437 cause reload to die, if it tries to generate a reload of CTR
1438 into a FP register and discovers it doesn't have the memory location
1439 required.
1440
1441 ??? Would it be a good idea to have reload do the converse, that is
1442 try to reload floating modes into FP registers if possible?
1443 */
1444
1445 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1446 rs6000_preferred_reload_class_ptr (X, CLASS)
1447
1448 /* Return the register class of a scratch register needed to copy IN into
1449 or out of a register in CLASS in MODE. If it can be done directly,
1450 NO_REGS is returned. */
1451
1452 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1453 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1454
1455 /* Return the maximum number of consecutive registers
1456 needed to represent mode MODE in a register of class CLASS.
1457
1458 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1459 a single reg is enough for two words, unless we have VSX, where the FP
1460 registers can hold 128 bits. */
1461 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1462
1463 /* Stack layout; function entry, exit and calling. */
1464
1465 /* Define this if pushing a word on the stack
1466 makes the stack pointer a smaller address. */
1467 #define STACK_GROWS_DOWNWARD 1
1468
1469 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1470 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1471
1472 /* Define this to nonzero if the nominal address of the stack frame
1473 is at the high-address end of the local variables;
1474 that is, each additional local variable allocated
1475 goes at a more negative offset in the frame.
1476
1477 On the RS/6000, we grow upwards, from the area after the outgoing
1478 arguments. */
1479 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1480 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1481
1482 /* Size of the fixed area on the stack */
1483 #define RS6000_SAVE_AREA \
1484 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1485 << (TARGET_64BIT ? 1 : 0))
1486
1487 /* Stack offset for toc save slot. */
1488 #define RS6000_TOC_SAVE_SLOT \
1489 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1490
1491 /* Align an address */
1492 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1493
1494 /* Offset within stack frame to start allocating local variables at.
1495 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1496 first local allocated. Otherwise, it is the offset to the BEGINNING
1497 of the first local allocated.
1498
1499 On the RS/6000, the frame pointer is the same as the stack pointer,
1500 except for dynamic allocations. So we start after the fixed area and
1501 outgoing parameter area.
1502
1503 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1504 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1505 sizes of the fixed area and the parameter area must be a multiple of
1506 STACK_BOUNDARY. */
1507
1508 #define RS6000_STARTING_FRAME_OFFSET \
1509 (cfun->calls_alloca \
1510 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1511 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1512 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1513 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1514 + RS6000_SAVE_AREA))
1515
1516 /* Offset from the stack pointer register to an item dynamically
1517 allocated on the stack, e.g., by `alloca'.
1518
1519 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1520 length of the outgoing arguments. The default is correct for most
1521 machines. See `function.c' for details.
1522
1523 This value must be a multiple of STACK_BOUNDARY (hard coded in
1524 `emit-rtl.c'). */
1525 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1526 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1527 + STACK_POINTER_OFFSET, \
1528 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1529
1530 /* If we generate an insn to push BYTES bytes,
1531 this says how many the stack pointer really advances by.
1532 On RS/6000, don't define this because there are no push insns. */
1533 /* #define PUSH_ROUNDING(BYTES) */
1534
1535 /* Offset of first parameter from the argument pointer register value.
1536 On the RS/6000, we define the argument pointer to the start of the fixed
1537 area. */
1538 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1539
1540 /* Offset from the argument pointer register value to the top of
1541 stack. This is different from FIRST_PARM_OFFSET because of the
1542 register save area. */
1543 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1544
1545 /* Define this if stack space is still allocated for a parameter passed
1546 in a register. The value is the number of bytes allocated to this
1547 area. */
1548 #define REG_PARM_STACK_SPACE(FNDECL) \
1549 rs6000_reg_parm_stack_space ((FNDECL), false)
1550
1551 /* Define this macro if space guaranteed when compiling a function body
1552 is different to space required when making a call, a situation that
1553 can arise with K&R style function definitions. */
1554 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1555 rs6000_reg_parm_stack_space ((FNDECL), true)
1556
1557 /* Define this if the above stack space is to be considered part of the
1558 space allocated by the caller. */
1559 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1560
1561 /* This is the difference between the logical top of stack and the actual sp.
1562
1563 For the RS/6000, sp points past the fixed area. */
1564 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1565
1566 /* Define this if the maximum size of all the outgoing args is to be
1567 accumulated and pushed during the prologue. The amount can be
1568 found in the variable crtl->outgoing_args_size. */
1569 #define ACCUMULATE_OUTGOING_ARGS 1
1570
1571 /* Define how to find the value returned by a library function
1572 assuming the value has mode MODE. */
1573
1574 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1575
1576 /* DRAFT_V4_STRUCT_RET defaults off. */
1577 #define DRAFT_V4_STRUCT_RET 0
1578
1579 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1580 #define DEFAULT_PCC_STRUCT_RETURN 0
1581
1582 /* Mode of stack savearea.
1583 FUNCTION is VOIDmode because calling convention maintains SP.
1584 BLOCK needs Pmode for SP.
1585 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1586 #define STACK_SAVEAREA_MODE(LEVEL) \
1587 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1588 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1589
1590 /* Minimum and maximum general purpose registers used to hold arguments. */
1591 #define GP_ARG_MIN_REG 3
1592 #define GP_ARG_MAX_REG 10
1593 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1594
1595 /* Minimum and maximum floating point registers used to hold arguments. */
1596 #define FP_ARG_MIN_REG 33
1597 #define FP_ARG_AIX_MAX_REG 45
1598 #define FP_ARG_V4_MAX_REG 40
1599 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1600 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1601 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1602
1603 /* Minimum and maximum AltiVec registers used to hold arguments. */
1604 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1605 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1606 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1607
1608 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1609 #define AGGR_ARG_NUM_REG 8
1610
1611 /* Return registers */
1612 #define GP_ARG_RETURN GP_ARG_MIN_REG
1613 #define FP_ARG_RETURN FP_ARG_MIN_REG
1614 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1615 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1616 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1617 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1618 ? (ALTIVEC_ARG_RETURN \
1619 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1620 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1621
1622 /* Flags for the call/call_value rtl operations set up by function_arg */
1623 #define CALL_NORMAL 0x00000000 /* no special processing */
1624 /* Bits in 0x00000001 are unused. */
1625 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1626 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1627 #define CALL_LONG 0x00000008 /* always call indirect */
1628 #define CALL_LIBCALL 0x00000010 /* libcall */
1629
1630 /* We don't have prologue and epilogue functions to save/restore
1631 everything for most ABIs. */
1632 #define WORLD_SAVE_P(INFO) 0
1633
1634 /* 1 if N is a possible register number for a function value
1635 as seen by the caller.
1636
1637 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1638 #define FUNCTION_VALUE_REGNO_P(N) \
1639 ((N) == GP_ARG_RETURN \
1640 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1641 && TARGET_HARD_FLOAT) \
1642 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1643 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1644
1645 /* 1 if N is a possible register number for function argument passing.
1646 On RS/6000, these are r3-r10 and fp1-fp13.
1647 On AltiVec, v2 - v13 are used for passing vectors. */
1648 #define FUNCTION_ARG_REGNO_P(N) \
1649 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1650 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1651 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1652 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1653 && TARGET_HARD_FLOAT))
1654 \f
1655 /* Define a data type for recording info about an argument list
1656 during the scan of that argument list. This data type should
1657 hold all necessary information about the function itself
1658 and about the args processed so far, enough to enable macros
1659 such as FUNCTION_ARG to determine where the next arg should go.
1660
1661 On the RS/6000, this is a structure. The first element is the number of
1662 total argument words, the second is used to store the next
1663 floating-point register number, and the third says how many more args we
1664 have prototype types for.
1665
1666 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1667 the next available GP register, `fregno' is the next available FP
1668 register, and `words' is the number of words used on the stack.
1669
1670 The varargs/stdarg support requires that this structure's size
1671 be a multiple of sizeof(int). */
1672
1673 typedef struct rs6000_args
1674 {
1675 int words; /* # words used for passing GP registers */
1676 int fregno; /* next available FP register */
1677 int vregno; /* next available AltiVec register */
1678 int nargs_prototype; /* # args left in the current prototype */
1679 int prototype; /* Whether a prototype was defined */
1680 int stdarg; /* Whether function is a stdarg function. */
1681 int call_cookie; /* Do special things for this call */
1682 int sysv_gregno; /* next available GP register */
1683 int intoffset; /* running offset in struct (darwin64) */
1684 int use_stack; /* any part of struct on stack (darwin64) */
1685 int floats_in_gpr; /* count of SFmode floats taking up
1686 GPR space (darwin64) */
1687 int named; /* false for varargs params */
1688 int escapes; /* if function visible outside tu */
1689 int libcall; /* If this is a compiler generated call. */
1690 } CUMULATIVE_ARGS;
1691
1692 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1693 for a call to a function whose data type is FNTYPE.
1694 For a library call, FNTYPE is 0. */
1695
1696 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1697 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1698 N_NAMED_ARGS, FNDECL, VOIDmode)
1699
1700 /* Similar, but when scanning the definition of a procedure. We always
1701 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1702
1703 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1704 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1705 1000, current_function_decl, VOIDmode)
1706
1707 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1708
1709 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1710 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1711 0, NULL_TREE, MODE)
1712
1713 #define PAD_VARARGS_DOWN \
1714 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1715
1716 /* Output assembler code to FILE to increment profiler label # LABELNO
1717 for profiling a function entry. */
1718
1719 #define FUNCTION_PROFILER(FILE, LABELNO) \
1720 output_function_profiler ((FILE), (LABELNO));
1721
1722 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1723 the stack pointer does not matter. No definition is equivalent to
1724 always zero.
1725
1726 On the RS/6000, this is nonzero because we can restore the stack from
1727 its backpointer, which we maintain. */
1728 #define EXIT_IGNORE_STACK 1
1729
1730 /* Define this macro as a C expression that is nonzero for registers
1731 that are used by the epilogue or the return' pattern. The stack
1732 and frame pointer registers are already be assumed to be used as
1733 needed. */
1734
1735 #define EPILOGUE_USES(REGNO) \
1736 ((reload_completed && (REGNO) == LR_REGNO) \
1737 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1738 || (crtl->calls_eh_return \
1739 && TARGET_AIX \
1740 && (REGNO) == 2))
1741
1742 \f
1743 /* Length in units of the trampoline for entering a nested function. */
1744
1745 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1746 \f
1747 /* Definitions for __builtin_return_address and __builtin_frame_address.
1748 __builtin_return_address (0) should give link register (LR_REGNO), enable
1749 this. */
1750 /* This should be uncommented, so that the link register is used, but
1751 currently this would result in unmatched insns and spilling fixed
1752 registers so we'll leave it for another day. When these problems are
1753 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1754 (mrs) */
1755 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1756
1757 /* Number of bytes into the frame return addresses can be found. See
1758 rs6000_stack_info in rs6000.c for more information on how the different
1759 abi's store the return address. */
1760 #define RETURN_ADDRESS_OFFSET \
1761 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1762
1763 /* The current return address is in link register (65). The return address
1764 of anything farther back is accessed normally at an offset of 8 from the
1765 frame pointer. */
1766 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1767 (rs6000_return_addr (COUNT, FRAME))
1768
1769 \f
1770 /* Definitions for register eliminations.
1771
1772 We have two registers that can be eliminated on the RS/6000. First, the
1773 frame pointer register can often be eliminated in favor of the stack
1774 pointer register. Secondly, the argument pointer register can always be
1775 eliminated; it is replaced with either the stack or frame pointer.
1776
1777 In addition, we use the elimination mechanism to see if r30 is needed
1778 Initially we assume that it isn't. If it is, we spill it. This is done
1779 by making it an eliminable register. We replace it with itself so that
1780 if it isn't needed, then existing uses won't be modified. */
1781
1782 /* This is an array of structures. Each structure initializes one pair
1783 of eliminable registers. The "from" register number is given first,
1784 followed by "to". Eliminations of the same "from" register are listed
1785 in order of preference. */
1786 #define ELIMINABLE_REGS \
1787 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1788 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1789 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1790 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1791 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1792 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1793
1794 /* Define the offset between two registers, one to be eliminated, and the other
1795 its replacement, at the start of a routine. */
1796 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1797 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1798 \f
1799 /* Addressing modes, and classification of registers for them. */
1800
1801 #define HAVE_PRE_DECREMENT 1
1802 #define HAVE_PRE_INCREMENT 1
1803 #define HAVE_PRE_MODIFY_DISP 1
1804 #define HAVE_PRE_MODIFY_REG 1
1805
1806 /* Macros to check register numbers against specific register classes. */
1807
1808 /* These assume that REGNO is a hard or pseudo reg number.
1809 They give nonzero only if REGNO is a hard reg of the suitable class
1810 or a pseudo reg currently allocated to a suitable hard reg.
1811 Since they use reg_renumber, they are safe only once reg_renumber
1812 has been allocated, which happens in reginfo.c during register
1813 allocation. */
1814
1815 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1816 ((REGNO) < FIRST_PSEUDO_REGISTER \
1817 ? (REGNO) <= 31 || (REGNO) == 67 \
1818 || (REGNO) == FRAME_POINTER_REGNUM \
1819 : (reg_renumber[REGNO] >= 0 \
1820 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1821 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1822
1823 #define REGNO_OK_FOR_BASE_P(REGNO) \
1824 ((REGNO) < FIRST_PSEUDO_REGISTER \
1825 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1826 || (REGNO) == FRAME_POINTER_REGNUM \
1827 : (reg_renumber[REGNO] > 0 \
1828 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1829 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1830
1831 /* Nonzero if X is a hard reg that can be used as an index
1832 or if it is a pseudo reg in the non-strict case. */
1833 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1834 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1835 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1836
1837 /* Nonzero if X is a hard reg that can be used as a base reg
1838 or if it is a pseudo reg in the non-strict case. */
1839 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1840 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1841 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1842
1843 \f
1844 /* Maximum number of registers that can appear in a valid memory address. */
1845
1846 #define MAX_REGS_PER_ADDRESS 2
1847
1848 /* Recognize any constant value that is a valid address. */
1849
1850 #define CONSTANT_ADDRESS_P(X) \
1851 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1852 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1853 || GET_CODE (X) == HIGH)
1854
1855 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1856 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1857 && EASY_VECTOR_15((n) >> 1) \
1858 && ((n) & 1) == 0)
1859
1860 #define EASY_VECTOR_MSB(n,mode) \
1861 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1862 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1863
1864 \f
1865 /* Try a machine-dependent way of reloading an illegitimate address
1866 operand. If we find one, push the reload and jump to WIN. This
1867 macro is used in only one place: `find_reloads_address' in reload.c.
1868
1869 Implemented on rs6000 by rs6000_legitimize_reload_address.
1870 Note that (X) is evaluated twice; this is safe in current usage. */
1871
1872 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1873 do { \
1874 int win; \
1875 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1876 (int)(TYPE), (IND_LEVELS), &win); \
1877 if ( win ) \
1878 goto WIN; \
1879 } while (0)
1880
1881 #define FIND_BASE_TERM rs6000_find_base_term
1882 \f
1883 /* The register number of the register used to address a table of
1884 static data addresses in memory. In some cases this register is
1885 defined by a processor's "application binary interface" (ABI).
1886 When this macro is defined, RTL is generated for this register
1887 once, as with the stack pointer and frame pointer registers. If
1888 this macro is not defined, it is up to the machine-dependent files
1889 to allocate such a register (if necessary). */
1890
1891 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1892 #define PIC_OFFSET_TABLE_REGNUM \
1893 (TARGET_TOC ? TOC_REGISTER \
1894 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1895 : INVALID_REGNUM)
1896
1897 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1898
1899 /* Define this macro if the register defined by
1900 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1901 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1902
1903 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1904
1905 /* A C expression that is nonzero if X is a legitimate immediate
1906 operand on the target machine when generating position independent
1907 code. You can assume that X satisfies `CONSTANT_P', so you need
1908 not check this. You can also assume FLAG_PIC is true, so you need
1909 not check it either. You need not define this macro if all
1910 constants (including `SYMBOL_REF') can be immediate operands when
1911 generating position independent code. */
1912
1913 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1914 \f
1915 /* Specify the machine mode that this machine uses
1916 for the index in the tablejump instruction. */
1917 #define CASE_VECTOR_MODE SImode
1918
1919 /* Define as C expression which evaluates to nonzero if the tablejump
1920 instruction expects the table to contain offsets from the address of the
1921 table.
1922 Do not define this if the table should contain absolute addresses. */
1923 #define CASE_VECTOR_PC_RELATIVE 1
1924
1925 /* Define this as 1 if `char' should by default be signed; else as 0. */
1926 #define DEFAULT_SIGNED_CHAR 0
1927
1928 /* An integer expression for the size in bits of the largest integer machine
1929 mode that should actually be used. */
1930
1931 /* Allow pairs of registers to be used, which is the intent of the default. */
1932 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1933
1934 /* Max number of bytes we can move from memory to memory
1935 in one reasonably fast instruction. */
1936 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1937 #define MAX_MOVE_MAX 8
1938
1939 /* Nonzero if access to memory by bytes is no faster than for words.
1940 Also nonzero if doing byte operations (specifically shifts) in registers
1941 is undesirable. */
1942 #define SLOW_BYTE_ACCESS 1
1943
1944 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1945 will either zero-extend or sign-extend. The value of this macro should
1946 be the code that says which one of the two operations is implicitly
1947 done, UNKNOWN if none. */
1948 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1949
1950 /* Define if loading short immediate values into registers sign extends. */
1951 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1952 \f
1953 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1954 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1955 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1956
1957 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1958 zero. The hardware instructions added in Power9 and the sequences using
1959 popcount return 32 or 64. */
1960 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1961 (TARGET_CTZ || TARGET_POPCNTD \
1962 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1963 : ((VALUE) = -1, 2))
1964
1965 /* Specify the machine mode that pointers have.
1966 After generation of rtl, the compiler makes no further distinction
1967 between pointers and any other objects of this machine mode. */
1968 extern scalar_int_mode rs6000_pmode;
1969 #define Pmode rs6000_pmode
1970
1971 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1972 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1973
1974 /* Mode of a function address in a call instruction (for indexing purposes).
1975 Doesn't matter on RS/6000. */
1976 #define FUNCTION_MODE SImode
1977
1978 /* Define this if addresses of constant functions
1979 shouldn't be put through pseudo regs where they can be cse'd.
1980 Desirable on machines where ordinary constants are expensive
1981 but a CALL with constant address is cheap. */
1982 #define NO_FUNCTION_CSE 1
1983
1984 /* Define this to be nonzero if shift instructions ignore all but the low-order
1985 few bits.
1986
1987 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1988 have been dropped from the PowerPC architecture. */
1989 #define SHIFT_COUNT_TRUNCATED 0
1990
1991 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1992 should be adjusted to reflect any required changes. This macro is used when
1993 there is some systematic length adjustment required that would be difficult
1994 to express in the length attribute. */
1995
1996 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1997
1998 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1999 COMPARE, return the mode to be used for the comparison. For
2000 floating-point, CCFPmode should be used. CCUNSmode should be used
2001 for unsigned comparisons. CCEQmode should be used when we are
2002 doing an inequality comparison on the result of a
2003 comparison. CCmode should be used in all other cases. */
2004
2005 #define SELECT_CC_MODE(OP,X,Y) \
2006 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2007 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2008 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2009 ? CCEQmode : CCmode))
2010
2011 /* Can the condition code MODE be safely reversed? This is safe in
2012 all cases on this port, because at present it doesn't use the
2013 trapping FP comparisons (fcmpo). */
2014 #define REVERSIBLE_CC_MODE(MODE) 1
2015
2016 /* Given a condition code and a mode, return the inverse condition. */
2017 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2018
2019 \f
2020 /* Target cpu costs. */
2021
2022 struct processor_costs {
2023 const int mulsi; /* cost of SImode multiplication. */
2024 const int mulsi_const; /* cost of SImode multiplication by constant. */
2025 const int mulsi_const9; /* cost of SImode mult by short constant. */
2026 const int muldi; /* cost of DImode multiplication. */
2027 const int divsi; /* cost of SImode division. */
2028 const int divdi; /* cost of DImode division. */
2029 const int fp; /* cost of simple SFmode and DFmode insns. */
2030 const int dmul; /* cost of DFmode multiplication (and fmadd). */
2031 const int sdiv; /* cost of SFmode division (fdivs). */
2032 const int ddiv; /* cost of DFmode division (fdiv). */
2033 const int cache_line_size; /* cache line size in bytes. */
2034 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
2035 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
2036 const int simultaneous_prefetches; /* number of parallel prefetch
2037 operations. */
2038 const int sfdf_convert; /* cost of SF->DF conversion. */
2039 };
2040
2041 extern const struct processor_costs *rs6000_cost;
2042 \f
2043 /* Control the assembler format that we output. */
2044
2045 /* A C string constant describing how to begin a comment in the target
2046 assembler language. The compiler assumes that the comment will end at
2047 the end of the line. */
2048 #define ASM_COMMENT_START " #"
2049
2050 /* Flag to say the TOC is initialized */
2051 extern int toc_initialized;
2052
2053 /* Macro to output a special constant pool entry. Go to WIN if we output
2054 it. Otherwise, it is written the usual way.
2055
2056 On the RS/6000, toc entries are handled this way. */
2057
2058 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2059 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2060 { \
2061 output_toc (FILE, X, LABELNO, MODE); \
2062 goto WIN; \
2063 } \
2064 }
2065
2066 #ifdef HAVE_GAS_WEAK
2067 #define RS6000_WEAK 1
2068 #else
2069 #define RS6000_WEAK 0
2070 #endif
2071
2072 #if RS6000_WEAK
2073 /* Used in lieu of ASM_WEAKEN_LABEL. */
2074 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2075 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
2076 #endif
2077
2078 #if HAVE_GAS_WEAKREF
2079 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2080 do \
2081 { \
2082 fputs ("\t.weakref\t", (FILE)); \
2083 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2084 fputs (", ", (FILE)); \
2085 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2086 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2087 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2088 { \
2089 fputs ("\n\t.weakref\t.", (FILE)); \
2090 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2091 fputs (", .", (FILE)); \
2092 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2093 } \
2094 fputc ('\n', (FILE)); \
2095 } while (0)
2096 #endif
2097
2098 /* This implements the `alias' attribute. */
2099 #undef ASM_OUTPUT_DEF_FROM_DECLS
2100 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2101 do \
2102 { \
2103 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2104 const char *name = IDENTIFIER_POINTER (TARGET); \
2105 if (TREE_CODE (DECL) == FUNCTION_DECL \
2106 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2107 { \
2108 if (TREE_PUBLIC (DECL)) \
2109 { \
2110 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2111 { \
2112 fputs ("\t.globl\t.", FILE); \
2113 RS6000_OUTPUT_BASENAME (FILE, alias); \
2114 putc ('\n', FILE); \
2115 } \
2116 } \
2117 else if (TARGET_XCOFF) \
2118 { \
2119 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2120 { \
2121 fputs ("\t.lglobl\t.", FILE); \
2122 RS6000_OUTPUT_BASENAME (FILE, alias); \
2123 putc ('\n', FILE); \
2124 fputs ("\t.lglobl\t", FILE); \
2125 RS6000_OUTPUT_BASENAME (FILE, alias); \
2126 putc ('\n', FILE); \
2127 } \
2128 } \
2129 fputs ("\t.set\t.", FILE); \
2130 RS6000_OUTPUT_BASENAME (FILE, alias); \
2131 fputs (",.", FILE); \
2132 RS6000_OUTPUT_BASENAME (FILE, name); \
2133 fputc ('\n', FILE); \
2134 } \
2135 ASM_OUTPUT_DEF (FILE, alias, name); \
2136 } \
2137 while (0)
2138
2139 #define TARGET_ASM_FILE_START rs6000_file_start
2140
2141 /* Output to assembler file text saying following lines
2142 may contain character constants, extra white space, comments, etc. */
2143
2144 #define ASM_APP_ON ""
2145
2146 /* Output to assembler file text saying following lines
2147 no longer contain unusual constructs. */
2148
2149 #define ASM_APP_OFF ""
2150
2151 /* How to refer to registers in assembler output.
2152 This sequence is indexed by compiler's hard-register-number (see above). */
2153
2154 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2155
2156 #define REGISTER_NAMES \
2157 { \
2158 &rs6000_reg_names[ 0][0], /* r0 */ \
2159 &rs6000_reg_names[ 1][0], /* r1 */ \
2160 &rs6000_reg_names[ 2][0], /* r2 */ \
2161 &rs6000_reg_names[ 3][0], /* r3 */ \
2162 &rs6000_reg_names[ 4][0], /* r4 */ \
2163 &rs6000_reg_names[ 5][0], /* r5 */ \
2164 &rs6000_reg_names[ 6][0], /* r6 */ \
2165 &rs6000_reg_names[ 7][0], /* r7 */ \
2166 &rs6000_reg_names[ 8][0], /* r8 */ \
2167 &rs6000_reg_names[ 9][0], /* r9 */ \
2168 &rs6000_reg_names[10][0], /* r10 */ \
2169 &rs6000_reg_names[11][0], /* r11 */ \
2170 &rs6000_reg_names[12][0], /* r12 */ \
2171 &rs6000_reg_names[13][0], /* r13 */ \
2172 &rs6000_reg_names[14][0], /* r14 */ \
2173 &rs6000_reg_names[15][0], /* r15 */ \
2174 &rs6000_reg_names[16][0], /* r16 */ \
2175 &rs6000_reg_names[17][0], /* r17 */ \
2176 &rs6000_reg_names[18][0], /* r18 */ \
2177 &rs6000_reg_names[19][0], /* r19 */ \
2178 &rs6000_reg_names[20][0], /* r20 */ \
2179 &rs6000_reg_names[21][0], /* r21 */ \
2180 &rs6000_reg_names[22][0], /* r22 */ \
2181 &rs6000_reg_names[23][0], /* r23 */ \
2182 &rs6000_reg_names[24][0], /* r24 */ \
2183 &rs6000_reg_names[25][0], /* r25 */ \
2184 &rs6000_reg_names[26][0], /* r26 */ \
2185 &rs6000_reg_names[27][0], /* r27 */ \
2186 &rs6000_reg_names[28][0], /* r28 */ \
2187 &rs6000_reg_names[29][0], /* r29 */ \
2188 &rs6000_reg_names[30][0], /* r30 */ \
2189 &rs6000_reg_names[31][0], /* r31 */ \
2190 \
2191 &rs6000_reg_names[32][0], /* fr0 */ \
2192 &rs6000_reg_names[33][0], /* fr1 */ \
2193 &rs6000_reg_names[34][0], /* fr2 */ \
2194 &rs6000_reg_names[35][0], /* fr3 */ \
2195 &rs6000_reg_names[36][0], /* fr4 */ \
2196 &rs6000_reg_names[37][0], /* fr5 */ \
2197 &rs6000_reg_names[38][0], /* fr6 */ \
2198 &rs6000_reg_names[39][0], /* fr7 */ \
2199 &rs6000_reg_names[40][0], /* fr8 */ \
2200 &rs6000_reg_names[41][0], /* fr9 */ \
2201 &rs6000_reg_names[42][0], /* fr10 */ \
2202 &rs6000_reg_names[43][0], /* fr11 */ \
2203 &rs6000_reg_names[44][0], /* fr12 */ \
2204 &rs6000_reg_names[45][0], /* fr13 */ \
2205 &rs6000_reg_names[46][0], /* fr14 */ \
2206 &rs6000_reg_names[47][0], /* fr15 */ \
2207 &rs6000_reg_names[48][0], /* fr16 */ \
2208 &rs6000_reg_names[49][0], /* fr17 */ \
2209 &rs6000_reg_names[50][0], /* fr18 */ \
2210 &rs6000_reg_names[51][0], /* fr19 */ \
2211 &rs6000_reg_names[52][0], /* fr20 */ \
2212 &rs6000_reg_names[53][0], /* fr21 */ \
2213 &rs6000_reg_names[54][0], /* fr22 */ \
2214 &rs6000_reg_names[55][0], /* fr23 */ \
2215 &rs6000_reg_names[56][0], /* fr24 */ \
2216 &rs6000_reg_names[57][0], /* fr25 */ \
2217 &rs6000_reg_names[58][0], /* fr26 */ \
2218 &rs6000_reg_names[59][0], /* fr27 */ \
2219 &rs6000_reg_names[60][0], /* fr28 */ \
2220 &rs6000_reg_names[61][0], /* fr29 */ \
2221 &rs6000_reg_names[62][0], /* fr30 */ \
2222 &rs6000_reg_names[63][0], /* fr31 */ \
2223 \
2224 &rs6000_reg_names[64][0], /* was mq */ \
2225 &rs6000_reg_names[65][0], /* lr */ \
2226 &rs6000_reg_names[66][0], /* ctr */ \
2227 &rs6000_reg_names[67][0], /* ap */ \
2228 \
2229 &rs6000_reg_names[68][0], /* cr0 */ \
2230 &rs6000_reg_names[69][0], /* cr1 */ \
2231 &rs6000_reg_names[70][0], /* cr2 */ \
2232 &rs6000_reg_names[71][0], /* cr3 */ \
2233 &rs6000_reg_names[72][0], /* cr4 */ \
2234 &rs6000_reg_names[73][0], /* cr5 */ \
2235 &rs6000_reg_names[74][0], /* cr6 */ \
2236 &rs6000_reg_names[75][0], /* cr7 */ \
2237 \
2238 &rs6000_reg_names[76][0], /* ca */ \
2239 \
2240 &rs6000_reg_names[77][0], /* v0 */ \
2241 &rs6000_reg_names[78][0], /* v1 */ \
2242 &rs6000_reg_names[79][0], /* v2 */ \
2243 &rs6000_reg_names[80][0], /* v3 */ \
2244 &rs6000_reg_names[81][0], /* v4 */ \
2245 &rs6000_reg_names[82][0], /* v5 */ \
2246 &rs6000_reg_names[83][0], /* v6 */ \
2247 &rs6000_reg_names[84][0], /* v7 */ \
2248 &rs6000_reg_names[85][0], /* v8 */ \
2249 &rs6000_reg_names[86][0], /* v9 */ \
2250 &rs6000_reg_names[87][0], /* v10 */ \
2251 &rs6000_reg_names[88][0], /* v11 */ \
2252 &rs6000_reg_names[89][0], /* v12 */ \
2253 &rs6000_reg_names[90][0], /* v13 */ \
2254 &rs6000_reg_names[91][0], /* v14 */ \
2255 &rs6000_reg_names[92][0], /* v15 */ \
2256 &rs6000_reg_names[93][0], /* v16 */ \
2257 &rs6000_reg_names[94][0], /* v17 */ \
2258 &rs6000_reg_names[95][0], /* v18 */ \
2259 &rs6000_reg_names[96][0], /* v19 */ \
2260 &rs6000_reg_names[97][0], /* v20 */ \
2261 &rs6000_reg_names[98][0], /* v21 */ \
2262 &rs6000_reg_names[99][0], /* v22 */ \
2263 &rs6000_reg_names[100][0], /* v23 */ \
2264 &rs6000_reg_names[101][0], /* v24 */ \
2265 &rs6000_reg_names[102][0], /* v25 */ \
2266 &rs6000_reg_names[103][0], /* v26 */ \
2267 &rs6000_reg_names[104][0], /* v27 */ \
2268 &rs6000_reg_names[105][0], /* v28 */ \
2269 &rs6000_reg_names[106][0], /* v29 */ \
2270 &rs6000_reg_names[107][0], /* v30 */ \
2271 &rs6000_reg_names[108][0], /* v31 */ \
2272 &rs6000_reg_names[109][0], /* vrsave */ \
2273 &rs6000_reg_names[110][0], /* vscr */ \
2274 &rs6000_reg_names[111][0], /* sfp */ \
2275 &rs6000_reg_names[112][0], /* tfhar */ \
2276 &rs6000_reg_names[113][0], /* tfiar */ \
2277 &rs6000_reg_names[114][0], /* texasr */ \
2278 }
2279
2280 /* Table of additional register names to use in user input. */
2281
2282 #define ADDITIONAL_REGISTER_NAMES \
2283 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2284 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2285 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2286 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2287 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2288 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2289 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2290 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2291 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2292 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2293 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2294 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2295 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2296 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2297 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2298 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2299 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2300 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2301 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2302 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2303 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2304 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2305 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2306 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2307 {"vrsave", 109}, {"vscr", 110}, \
2308 /* no additional names for: lr, ctr, ap */ \
2309 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2310 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2311 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2312 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2313 {"xer", 76}, \
2314 /* VSX registers overlaid on top of FR, Altivec registers */ \
2315 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2316 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2317 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2318 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2319 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2320 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2321 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2322 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2323 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2324 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2325 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2326 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2327 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2328 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2329 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2330 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
2331 /* Transactional Memory Facility (HTM) Registers. */ \
2332 {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \
2333 }
2334
2335 /* This is how to output an element of a case-vector that is relative. */
2336
2337 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2338 do { char buf[100]; \
2339 fputs ("\t.long ", FILE); \
2340 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2341 assemble_name (FILE, buf); \
2342 putc ('-', FILE); \
2343 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2344 assemble_name (FILE, buf); \
2345 putc ('\n', FILE); \
2346 } while (0)
2347
2348 /* This is how to output an assembler line
2349 that says to advance the location counter
2350 to a multiple of 2**LOG bytes. */
2351
2352 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2353 if ((LOG) != 0) \
2354 fprintf (FILE, "\t.align %d\n", (LOG))
2355
2356 /* How to align the given loop. */
2357 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2358
2359 /* Alignment guaranteed by __builtin_malloc. */
2360 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2361 However, specifying the stronger guarantee currently leads to
2362 a regression in SPEC CPU2006 437.leslie3d. The stronger
2363 guarantee should be implemented here once that's fixed. */
2364 #define MALLOC_ABI_ALIGNMENT (64)
2365
2366 /* Pick up the return address upon entry to a procedure. Used for
2367 dwarf2 unwind information. This also enables the table driven
2368 mechanism. */
2369
2370 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2371 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2372
2373 /* Describe how we implement __builtin_eh_return. */
2374 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2375 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2376
2377 /* Print operand X (an rtx) in assembler syntax to file FILE.
2378 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2379 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2380
2381 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2382
2383 /* Define which CODE values are valid. */
2384
2385 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2386
2387 /* Print a memory address as an operand to reference that memory location. */
2388
2389 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2390
2391 /* For switching between functions with different target attributes. */
2392 #define SWITCHABLE_TARGET 1
2393
2394 /* uncomment for disabling the corresponding default options */
2395 /* #define MACHINE_no_sched_interblock */
2396 /* #define MACHINE_no_sched_speculative */
2397 /* #define MACHINE_no_sched_speculative_load */
2398
2399 /* General flags. */
2400 extern int frame_pointer_needed;
2401
2402 /* Classification of the builtin functions as to which switches enable the
2403 builtin, and what attributes it should have. We used to use the target
2404 flags macros, but we've run out of bits, so we now map the options into new
2405 settings used here. */
2406
2407 /* Builtin attributes. */
2408 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2409 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2410 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2411 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2412 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2413 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2414 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2415 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2416
2417 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2418 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor
2419 modifies global state. */
2420 #define RS6000_BTC_PURE 0x00000200 /* reads global
2421 state/mem and does
2422 not modify global state. */
2423 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2424 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2425
2426 /* Miscellaneous information. */
2427 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
2428 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
2429 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */
2430 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */
2431 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
2432
2433 /* Convenience macros to document the instruction type. */
2434 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2435 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2436
2437 /* Builtin targets. For now, we reuse the masks for those options that are in
2438 target flags, and pick a random bit for ldbl128, which isn't in
2439 target_flags. */
2440 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2441 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2442 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
2443 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2444 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2445 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
2446 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
2447 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2448 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2449 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2450 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2451 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2452 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2453 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2454 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2455 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2456 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2457 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2458 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
2459 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
2460 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
2461 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
2462
2463 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2464 | RS6000_BTM_VSX \
2465 | RS6000_BTM_P8_VECTOR \
2466 | RS6000_BTM_P9_VECTOR \
2467 | RS6000_BTM_P9_MISC \
2468 | RS6000_BTM_MODULO \
2469 | RS6000_BTM_CRYPTO \
2470 | RS6000_BTM_FRE \
2471 | RS6000_BTM_FRES \
2472 | RS6000_BTM_FRSQRTE \
2473 | RS6000_BTM_FRSQRTES \
2474 | RS6000_BTM_HTM \
2475 | RS6000_BTM_POPCNTD \
2476 | RS6000_BTM_CELL \
2477 | RS6000_BTM_DFP \
2478 | RS6000_BTM_HARD_FLOAT \
2479 | RS6000_BTM_LDBL128 \
2480 | RS6000_BTM_POWERPC64 \
2481 | RS6000_BTM_FLOAT128 \
2482 | RS6000_BTM_FLOAT128_HW)
2483
2484 /* Define builtin enum index. */
2485
2486 #undef RS6000_BUILTIN_0
2487 #undef RS6000_BUILTIN_1
2488 #undef RS6000_BUILTIN_2
2489 #undef RS6000_BUILTIN_3
2490 #undef RS6000_BUILTIN_A
2491 #undef RS6000_BUILTIN_D
2492 #undef RS6000_BUILTIN_H
2493 #undef RS6000_BUILTIN_P
2494 #undef RS6000_BUILTIN_X
2495
2496 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2497 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2498 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2499 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2500 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2501 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2502 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2503 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2504 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2505
2506 enum rs6000_builtins
2507 {
2508 #include "rs6000-builtin.def"
2509
2510 RS6000_BUILTIN_COUNT
2511 };
2512
2513 #undef RS6000_BUILTIN_0
2514 #undef RS6000_BUILTIN_1
2515 #undef RS6000_BUILTIN_2
2516 #undef RS6000_BUILTIN_3
2517 #undef RS6000_BUILTIN_A
2518 #undef RS6000_BUILTIN_D
2519 #undef RS6000_BUILTIN_H
2520 #undef RS6000_BUILTIN_P
2521 #undef RS6000_BUILTIN_X
2522
2523 enum rs6000_builtin_type_index
2524 {
2525 RS6000_BTI_NOT_OPAQUE,
2526 RS6000_BTI_opaque_V4SI,
2527 RS6000_BTI_V16QI, /* __vector signed char */
2528 RS6000_BTI_V1TI,
2529 RS6000_BTI_V2DI,
2530 RS6000_BTI_V2DF,
2531 RS6000_BTI_V4HI,
2532 RS6000_BTI_V4SI,
2533 RS6000_BTI_V4SF,
2534 RS6000_BTI_V8HI,
2535 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */
2536 RS6000_BTI_unsigned_V1TI,
2537 RS6000_BTI_unsigned_V8HI,
2538 RS6000_BTI_unsigned_V4SI,
2539 RS6000_BTI_unsigned_V2DI,
2540 RS6000_BTI_bool_char, /* __bool char */
2541 RS6000_BTI_bool_short, /* __bool short */
2542 RS6000_BTI_bool_int, /* __bool int */
2543 RS6000_BTI_bool_long_long, /* __bool long long */
2544 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4
2545 channels of 1, 5, 5, and 5 bits
2546 respectively as packed with the
2547 vpkpx insn. __pixel is only
2548 meaningful as a vector type.
2549 There is no corresponding scalar
2550 __pixel data type.) */
2551 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2552 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2553 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2554 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2555 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2556 RS6000_BTI_long, /* long_integer_type_node */
2557 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2558 RS6000_BTI_long_long, /* long_long_integer_type_node */
2559 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
2560 RS6000_BTI_INTQI, /* (signed) intQI_type_node */
2561 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2562 RS6000_BTI_INTHI, /* intHI_type_node */
2563 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2564 RS6000_BTI_INTSI, /* intSI_type_node (signed) */
2565 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2566 RS6000_BTI_INTDI, /* intDI_type_node */
2567 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2568 RS6000_BTI_INTTI, /* intTI_type_node */
2569 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */
2570 RS6000_BTI_float, /* float_type_node */
2571 RS6000_BTI_double, /* double_type_node */
2572 RS6000_BTI_long_double, /* long_double_type_node */
2573 RS6000_BTI_dfloat64, /* dfloat64_type_node */
2574 RS6000_BTI_dfloat128, /* dfloat128_type_node */
2575 RS6000_BTI_void, /* void_type_node */
2576 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */
2577 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */
2578 RS6000_BTI_const_str, /* pointer to const char * */
2579 RS6000_BTI_MAX
2580 };
2581
2582
2583 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2584 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2585 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2586 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2587 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2588 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2589 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2590 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2591 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2592 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2593 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2594 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2595 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2596 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2597 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2598 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2599 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2600 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2601 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2602 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2603 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2604 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2605 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2606 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2607
2608 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2609 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2610 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2611 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2612 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2613 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2614 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2615 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2616 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2617 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2618 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2619 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2620 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2621 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2622 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2623 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2624 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2625 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2626 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2627 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2628 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2629 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2630 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2631
2632 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2633 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
2634
2635 #define TARGET_SUPPORTS_WIDE_INT 1
2636
2637 #if (GCC_VERSION >= 3000)
2638 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128
2639 #endif
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