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2006-03-23 J"orn Rennecke <joern.rennecke@st.com>
[official-gcc.git] / gcc / config / sh / sh.h
blob1b7ff5dbe2c19ca55c02d15a5d2d0e49f7964a31
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
57 break; \
58 case PROCESSOR_SH3: \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
63 break; \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
66 break; \
67 case PROCESSOR_SH4: \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
69 break; \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
75 : "__SH4_NOFPU__"); \
76 break; \
77 case PROCESSOR_SH5: \
78 { \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
85 } \
86 } \
87 if (TARGET_FPU_ANY) \
88 builtin_define ("__SH_FPU_ANY__"); \
89 if (TARGET_FPU_DOUBLE) \
90 builtin_define ("__SH_FPU_DOUBLE__"); \
91 if (TARGET_HITACHI) \
92 builtin_define ("__HITACHI__"); \
93 builtin_define (TARGET_LITTLE_ENDIAN \
94 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
95 } while (0)
96
97 /* We can not debug without a frame pointer. */
98 /* #define CAN_DEBUG_WITHOUT_FP */
99
100 #define CONDITIONAL_REGISTER_USAGE do \
101 { \
102 int regno; \
103 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
104 if (! VALID_REGISTER_P (regno)) \
105 fixed_regs[regno] = call_used_regs[regno] = 1; \
106 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
107 if (TARGET_SH5) \
108 { \
109 call_used_regs[FIRST_GENERAL_REG + 8] \
110 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
111 call_really_used_regs[FIRST_GENERAL_REG + 8] \
112 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
113 } \
114 if (TARGET_SHMEDIA) \
115 { \
116 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
117 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
118 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
119 } \
120 if (flag_pic) \
121 { \
122 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
123 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 } \
125 /* Renesas saves and restores mac registers on call. */ \
126 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
127 { \
128 call_really_used_regs[MACH_REG] = 0; \
129 call_really_used_regs[MACL_REG] = 0; \
130 } \
131 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
132 regno <= LAST_FP_REG; regno += 2) \
133 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
134 if (TARGET_SHMEDIA) \
135 { \
136 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
137 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
138 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
139 } \
140 else \
141 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
142 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
143 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
144 } while (0)
145 \f
146 /* Nonzero if this is an ELF target - compile time only */
147 #define TARGET_ELF 0
148
149 /* Nonzero if we should generate code using type 2E insns. */
150 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
151
152 /* Nonzero if we should generate code using type 2A insns. */
153 #define TARGET_SH2A TARGET_HARD_SH2A
154 /* Nonzero if we should generate code using type 2A SF insns. */
155 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
156 /* Nonzero if we should generate code using type 2A DF insns. */
157 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
158
159 /* Nonzero if we should generate code using type 3E insns. */
160 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
161
162 /* Nonzero if the cache line size is 32. */
163 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
164
165 /* Nonzero if we schedule for a superscalar implementation. */
166 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
167
168 /* Nonzero if the target has separate instruction and data caches. */
169 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
170
171 /* Nonzero if a double-precision FPU is available. */
172 #define TARGET_FPU_DOUBLE \
173 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
174
175 /* Nonzero if an FPU is available. */
176 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
177
178 /* Nonzero if we should generate code using type 4 insns. */
179 #undef TARGET_SH4
180 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
181
182 /* Nonzero if we're generating code for the common subset of
183 instructions present on both SH4a and SH4al-dsp. */
184 #define TARGET_SH4A_ARCH TARGET_SH4A
185
186 /* Nonzero if we're generating code for SH4a, unless the use of the
187 FPU is disabled (which makes it compatible with SH4al-dsp). */
188 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
189
190 /* Nonzero if we should generate code using the SHcompact instruction
191 set and 32-bit ABI. */
192 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
193
194 /* Nonzero if we should generate code using the SHmedia instruction
195 set and ABI. */
196 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
197
198 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
199 ABI. */
200 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
201
202 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
203 ABI. */
204 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
205
206 /* Nonzero if we should generate code using SHmedia FPU instructions. */
207 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
208
209 /* This is not used by the SH2E calling convention */
210 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
211 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
212 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
213
214 #ifndef TARGET_CPU_DEFAULT
215 #define TARGET_CPU_DEFAULT SELECT_SH1
216 #define SUPPORT_SH1 1
217 #define SUPPORT_SH2E 1
218 #define SUPPORT_SH4 1
219 #define SUPPORT_SH4_SINGLE 1
220 #define SUPPORT_SH2A 1
221 #define SUPPORT_SH2A_SINGLE 1
222 #endif
223
224 #define TARGET_DIVIDE_INV \
225 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
226 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
227 || sh_div_strategy == SH_DIV_INV_CALL \
228 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
229 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
230 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
231 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
232 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
233 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
234 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
235 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
236 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
237 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
238 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
239 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
240
241 #define SELECT_SH1 (MASK_SH1)
242 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
243 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
244 | MASK_FPU_SINGLE)
245 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
246 | MASK_HARD_SH2A_DOUBLE \
247 | MASK_SH2 | MASK_SH1)
248 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
250 | MASK_SH1 | MASK_FPU_SINGLE)
251 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
252 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
253 | MASK_SH2 | MASK_SH1)
254 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
255 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
256 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
257 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
258 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
259 | SELECT_SH3)
260 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
261 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
262 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
263 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
264 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
265 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
266 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
267 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
268 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
269 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
270 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
271
272 #if SUPPORT_SH1
273 #define SUPPORT_SH2 1
274 #endif
275 #if SUPPORT_SH2
276 #define SUPPORT_SH3 1
277 #endif
278 #if SUPPORT_SH3
279 #define SUPPORT_SH4_NOFPU 1
280 #endif
281 #if SUPPORT_SH4_NOFPU
282 #define SUPPORT_SH4A_NOFPU 1
283 #define SUPPORT_SH4AL 1
284 #define SUPPORT_SH2A_NOFPU 1
285 #endif
286
287 #if SUPPORT_SH2E
288 #define SUPPORT_SH3E 1
289 #endif
290 #if SUPPORT_SH3E
291 #define SUPPORT_SH4_SINGLE_ONLY 1
292 #define SUPPORT_SH4A_SINGLE_ONLY 1
293 #define SUPPORT_SH2A_SINGLE_ONLY 1
294 #endif
295
296 #if SUPPORT_SH4
297 #define SUPPORT_SH4A 1
298 #endif
299
300 #if SUPPORT_SH4_SINGLE
301 #define SUPPORT_SH4A_SINGLE 1
302 #endif
303
304 #if SUPPORT_SH5_COMPAT
305 #define SUPPORT_SH5_32MEDIA 1
306 #endif
307
308 #if SUPPORT_SH5_COMPACT_NOFPU
309 #define SUPPORT_SH5_32MEDIA_NOFPU 1
310 #endif
311
312 #define SUPPORT_ANY_SH5_32MEDIA \
313 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
314 #define SUPPORT_ANY_SH5_64MEDIA \
315 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
316 #define SUPPORT_ANY_SH5 \
317 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
318
319 /* Reset all target-selection flags. */
320 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
321 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
322 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
323
324 /* This defaults us to big-endian. */
325 #ifndef TARGET_ENDIAN_DEFAULT
326 #define TARGET_ENDIAN_DEFAULT 0
327 #endif
328
329 #ifndef TARGET_OPT_DEFAULT
330 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
331 #endif
332
333 #define TARGET_DEFAULT \
334 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
335
336 #ifndef SH_MULTILIB_CPU_DEFAULT
337 #define SH_MULTILIB_CPU_DEFAULT "m1"
338 #endif
339
340 #if TARGET_ENDIAN_DEFAULT
341 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
342 #else
343 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
344 #endif
345
346 #define CPP_SPEC " %(subtarget_cpp_spec) "
347
348 #ifndef SUBTARGET_CPP_SPEC
349 #define SUBTARGET_CPP_SPEC ""
350 #endif
351
352 #ifndef SUBTARGET_EXTRA_SPECS
353 #define SUBTARGET_EXTRA_SPECS
354 #endif
355
356 #define EXTRA_SPECS \
357 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
358 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
359 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
360 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
361 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
362 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
363 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
364 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
365 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
366 SUBTARGET_EXTRA_SPECS
367
368 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
369 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
370 #else
371 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
372 #endif
373
374 #define SH_ASM_SPEC \
375 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
376 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
377 %{m2a:--isa=sh2a} \
378 %{m2a-single:--isa=sh2a} \
379 %{m2a-single-only:--isa=sh2a} \
380 %{m2a-nofpu:--isa=sh2a-nofpu} \
381 %{m5-compact*:--isa=SHcompact} \
382 %{m5-32media*:--isa=SHmedia --abi=32} \
383 %{m5-64media*:--isa=SHmedia --abi=64} \
384 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
385
386 #define ASM_SPEC SH_ASM_SPEC
387
388 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
389 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
390 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
391 #else
392 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
393 #endif
394 #endif
395
396 #if STRICT_NOFPU == 1
397 /* Strict nofpu means that the compiler should tell the assembler
398 to reject FPU instructions. E.g. from ASM inserts. */
399 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
400 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
401 #else
402 /* If there were an -isa option for sh5-nofpu then it would also go here. */
403 #define SUBTARGET_ASM_ISA_SPEC \
404 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
405 #endif
406 #else /* ! STRICT_NOFPU */
407 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
408 #endif
409
410 #ifndef SUBTARGET_ASM_SPEC
411 #define SUBTARGET_ASM_SPEC ""
412 #endif
413
414 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
415 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
416 #else
417 #define LINK_EMUL_PREFIX "sh%{ml:l}"
418 #endif
419
420 #if TARGET_CPU_DEFAULT & MASK_SH5
421 #if TARGET_CPU_DEFAULT & MASK_SH_E
422 #define LINK_DEFAULT_CPU_EMUL "32"
423 #if TARGET_CPU_DEFAULT & MASK_SH1
424 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
425 #else
426 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
427 #endif /* MASK_SH1 */
428 #else /* !MASK_SH_E */
429 #define LINK_DEFAULT_CPU_EMUL "64"
430 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
431 #endif /* MASK_SH_E */
432 #define ASM_ISA_DEFAULT_SPEC \
433 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
434 #else /* !MASK_SH5 */
435 #define LINK_DEFAULT_CPU_EMUL ""
436 #define ASM_ISA_DEFAULT_SPEC ""
437 #endif /* MASK_SH5 */
438
439 #define SUBTARGET_LINK_EMUL_SUFFIX ""
440 #define SUBTARGET_LINK_SPEC ""
441
442 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
443 so that we can undo the damage without code replication. */
444 #define LINK_SPEC SH_LINK_SPEC
445
446 #define SH_LINK_SPEC "\
447 -m %(link_emul_prefix)\
448 %{m5-compact*|m5-32media*:32}\
449 %{m5-64media*:64}\
450 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
451 %(subtarget_link_emul_suffix) \
452 %{mrelax:-relax} %(subtarget_link_spec)"
453
454 #ifndef SH_DIV_STR_FOR_SIZE
455 #define SH_DIV_STR_FOR_SIZE "call"
456 #endif
457
458 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
459 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
460 do { \
461 if (LEVEL) \
462 { \
463 flag_omit_frame_pointer = -1; \
464 if (! SIZE) \
465 sh_div_str = "inv:minlat"; \
466 } \
467 if (SIZE) \
468 { \
469 target_flags |= MASK_SMALLCODE; \
470 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
471 } \
472 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
473 haven't been parsed yet, hence we'd read only the default. \
474 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
475 it's OK to always set flag_branch_target_load_optimize. */ \
476 if (LEVEL > 1) \
477 { \
478 flag_branch_target_load_optimize = 1; \
479 if (! (SIZE)) \
480 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
481 } \
482 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
483 here, so leave it to OVERRIDE_OPTIONS to set \
484 flag_finite_math_only. We set it to 2 here so we know if the user \
485 explicitly requested this to be on or off. */ \
486 flag_finite_math_only = 2; \
487 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
488 the user explicitly requested this to be on or off. */ \
489 if (flag_schedule_insns > 0) \
490 flag_schedule_insns = 2; \
491 } while (0)
492
493 #define ASSEMBLER_DIALECT assembler_dialect
494
495 extern int assembler_dialect;
496
497 enum sh_divide_strategy_e {
498 /* SH5 strategies. */
499 SH_DIV_CALL,
500 SH_DIV_CALL2,
501 SH_DIV_FP, /* We could do this also for SH4. */
502 SH_DIV_INV,
503 SH_DIV_INV_MINLAT,
504 SH_DIV_INV20U,
505 SH_DIV_INV20L,
506 SH_DIV_INV_CALL,
507 SH_DIV_INV_CALL2,
508 SH_DIV_INV_FP,
509 /* SH1 .. SH4 strategies. Because of the small number of registers
510 available, the compiler uses knowledge of the actual et of registers
511 being clobbed by the different functions called. */
512 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
513 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
514 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
515 SH_DIV_INTRINSIC
516 };
517
518 extern enum sh_divide_strategy_e sh_div_strategy;
519
520 #ifndef SH_DIV_STRATEGY_DEFAULT
521 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
522 #endif
523
524 #define OVERRIDE_OPTIONS \
525 do { \
526 int regno; \
527 \
528 if (flag_finite_math_only == 2) \
529 flag_finite_math_only \
530 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
531 if (TARGET_SH2E && !flag_finite_math_only) \
532 target_flags |= MASK_IEEE; \
533 sh_cpu = CPU_SH1; \
534 assembler_dialect = 0; \
535 if (TARGET_SH2) \
536 sh_cpu = CPU_SH2; \
537 if (TARGET_SH2E) \
538 sh_cpu = CPU_SH2E; \
539 if (TARGET_SH2A) \
540 { \
541 sh_cpu = CPU_SH2A; \
542 if (TARGET_SH2A_DOUBLE) \
543 target_flags |= MASK_FMOVD; \
544 } \
545 if (TARGET_SH3) \
546 sh_cpu = CPU_SH3; \
547 if (TARGET_SH3E) \
548 sh_cpu = CPU_SH3E; \
549 if (TARGET_SH4) \
550 { \
551 assembler_dialect = 1; \
552 sh_cpu = CPU_SH4; \
553 } \
554 if (TARGET_SH4A_ARCH) \
555 { \
556 assembler_dialect = 1; \
557 sh_cpu = CPU_SH4A; \
558 } \
559 if (TARGET_SH5) \
560 { \
561 sh_cpu = CPU_SH5; \
562 target_flags |= MASK_ALIGN_DOUBLE; \
563 if (TARGET_SHMEDIA_FPU) \
564 target_flags |= MASK_FMOVD; \
565 if (TARGET_SHMEDIA) \
566 { \
567 /* There are no delay slots on SHmedia. */ \
568 flag_delayed_branch = 0; \
569 /* Relaxation isn't yet supported for SHmedia */ \
570 target_flags &= ~MASK_RELAX; \
571 /* After reload, if conversion does little good but can cause \
572 ICEs: \
573 - find_if_block doesn't do anything for SH because we don't\
574 have conditional execution patterns. (We use conditional\
575 move patterns, which are handled differently, and only \
576 before reload). \
577 - find_cond_trap doesn't do anything for the SH because we \
578 don't have conditional traps. \
579 - find_if_case_1 uses redirect_edge_and_branch_force in \
580 the only path that does an optimization, and this causes \
581 an ICE when branch targets are in registers. \
582 - find_if_case_2 doesn't do anything for the SHmedia after \
583 reload except when it can redirect a tablejump - and \
584 that's rather rare. */ \
585 flag_if_conversion2 = 0; \
586 if (! strcmp (sh_div_str, "call")) \
587 sh_div_strategy = SH_DIV_CALL; \
588 else if (! strcmp (sh_div_str, "call2")) \
589 sh_div_strategy = SH_DIV_CALL2; \
590 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
591 sh_div_strategy = SH_DIV_FP; \
592 else if (! strcmp (sh_div_str, "inv")) \
593 sh_div_strategy = SH_DIV_INV; \
594 else if (! strcmp (sh_div_str, "inv:minlat")) \
595 sh_div_strategy = SH_DIV_INV_MINLAT; \
596 else if (! strcmp (sh_div_str, "inv20u")) \
597 sh_div_strategy = SH_DIV_INV20U; \
598 else if (! strcmp (sh_div_str, "inv20l")) \
599 sh_div_strategy = SH_DIV_INV20L; \
600 else if (! strcmp (sh_div_str, "inv:call2")) \
601 sh_div_strategy = SH_DIV_INV_CALL2; \
602 else if (! strcmp (sh_div_str, "inv:call")) \
603 sh_div_strategy = SH_DIV_INV_CALL; \
604 else if (! strcmp (sh_div_str, "inv:fp")) \
605 { \
606 if (TARGET_FPU_ANY) \
607 sh_div_strategy = SH_DIV_INV_FP; \
608 else \
609 sh_div_strategy = SH_DIV_INV; \
610 } \
611 } \
612 /* -fprofile-arcs needs a working libgcov . In unified tree \
613 configurations with newlib, this requires to configure with \
614 --with-newlib --with-headers. But there is no way to check \
615 here we have a working libgcov, so just assume that we have. */\
616 if (profile_flag) \
617 warning (0, "profiling is still experimental for this target");\
618 } \
619 else \
620 { \
621 /* Only the sh64-elf assembler fully supports .quad properly. */\
622 targetm.asm_out.aligned_op.di = NULL; \
623 targetm.asm_out.unaligned_op.di = NULL; \
624 } \
625 if (TARGET_SH1) \
626 { \
627 if (! strcmp (sh_div_str, "call-div1")) \
628 sh_div_strategy = SH_DIV_CALL_DIV1; \
629 else if (! strcmp (sh_div_str, "call-fp") \
630 && (TARGET_FPU_DOUBLE \
631 || (TARGET_HARD_SH4 && TARGET_SH2E) \
632 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
633 sh_div_strategy = SH_DIV_CALL_FP; \
634 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH3) \
635 sh_div_strategy = SH_DIV_CALL_TABLE; \
636 else \
637 /* Pick one that makes most sense for the target in general. \
638 It is not much good to use different functions depending \
639 on -Os, since then we'll end up with two different functions \
640 when some of the code is compiled for size, and some for \
641 speed. */ \
642 \
643 /* SH4 tends to emphasize speed. */ \
644 if (TARGET_HARD_SH4) \
645 sh_div_strategy = SH_DIV_CALL_TABLE; \
646 /* These have their own way of doing things. */ \
647 else if (TARGET_SH2A) \
648 sh_div_strategy = SH_DIV_INTRINSIC; \
649 /* ??? Should we use the integer SHmedia function instead? */ \
650 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
651 sh_div_strategy = SH_DIV_CALL_FP; \
652 /* SH1 .. SH3 cores often go into small-footprint systems, so \
653 default to the smallest implementation available. */ \
654 else \
655 sh_div_strategy = SH_DIV_CALL_DIV1; \
656 } \
657 if (sh_divsi3_libfunc[0]) \
658 ; /* User supplied - leave it alone. */ \
659 else if (TARGET_DIVIDE_CALL_FP) \
660 sh_divsi3_libfunc = "__sdivsi3_i4"; \
661 else if (TARGET_DIVIDE_CALL_TABLE) \
662 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
663 else if (TARGET_SH5) \
664 sh_divsi3_libfunc = "__sdivsi3_1"; \
665 else \
666 sh_divsi3_libfunc = "__sdivsi3"; \
667 if (TARGET_FMOVD) \
668 reg_class_from_letter['e' - 'a'] = NO_REGS; \
669 \
670 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
671 if (! VALID_REGISTER_P (regno)) \
672 sh_register_names[regno][0] = '\0'; \
673 \
674 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
675 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
676 sh_additional_register_names[regno][0] = '\0'; \
677 \
678 if (flag_omit_frame_pointer < 0) \
679 { \
680 /* The debugging information is sufficient, \
681 but gdb doesn't implement this yet */ \
682 if (0) \
683 flag_omit_frame_pointer \
684 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
685 else \
686 flag_omit_frame_pointer = 0; \
687 } \
688 \
689 if ((flag_pic && ! TARGET_PREFERGOT) \
690 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
691 flag_no_function_cse = 1; \
692 \
693 if (SMALL_REGISTER_CLASSES) \
694 { \
695 /* Never run scheduling before reload, since that can \
696 break global alloc, and generates slower code anyway due \
697 to the pressure on R0. */ \
698 /* Enable sched1 for SH4; ready queue will be reordered by \
699 the target hooks when pressure is high. We can not do this for \
700 SH3 and lower as they give spill failures for R0. */ \
701 if (!TARGET_HARD_SH4) \
702 flag_schedule_insns = 0; \
703 /* ??? Current exception handling places basic block boundaries \
704 after call_insns. It causes the high pressure on R0 and gives \
705 spill failures for R0 in reload. See PR 22553 and the thread \
706 on gcc-patches \
707 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
708 else if (flag_exceptions) \
709 { \
710 if (flag_schedule_insns == 1) \
711 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
712 flag_schedule_insns = 0; \
713 } \
714 } \
715 \
716 if (align_loops == 0) \
717 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
718 if (align_jumps == 0) \
719 align_jumps = 1 << CACHE_LOG; \
720 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
721 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
722 \
723 /* Allocation boundary (in *bytes*) for the code of a function. \
724 SH1: 32 bit alignment is faster, because instructions are always \
725 fetched as a pair from a longword boundary. \
726 SH2 .. SH5 : align to cache line start. */ \
727 if (align_functions == 0) \
728 align_functions \
729 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
730 /* The linker relaxation code breaks when a function contains \
731 alignments that are larger than that at the start of a \
732 compilation unit. */ \
733 if (TARGET_RELAX) \
734 { \
735 int min_align \
736 = align_loops > align_jumps ? align_loops : align_jumps; \
737 \
738 /* Also take possible .long constants / mova tables int account. */\
739 if (min_align < 4) \
740 min_align = 4; \
741 if (align_functions < min_align) \
742 align_functions = min_align; \
743 } \
744 } while (0)
745 \f
746 /* Target machine storage layout. */
747
748 /* Define this if most significant bit is lowest numbered
749 in instructions that operate on numbered bit-fields. */
750
751 #define BITS_BIG_ENDIAN 0
752
753 /* Define this if most significant byte of a word is the lowest numbered. */
754 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
755
756 /* Define this if most significant word of a multiword number is the lowest
757 numbered. */
758 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
759
760 /* Define this to set the endianness to use in libgcc2.c, which can
761 not depend on target_flags. */
762 #if defined(__LITTLE_ENDIAN__)
763 #define LIBGCC2_WORDS_BIG_ENDIAN 0
764 #else
765 #define LIBGCC2_WORDS_BIG_ENDIAN 1
766 #endif
767
768 #define MAX_BITS_PER_WORD 64
769
770 /* Width in bits of an `int'. We want just 32-bits, even if words are
771 longer. */
772 #define INT_TYPE_SIZE 32
773
774 /* Width in bits of a `long'. */
775 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
776
777 /* Width in bits of a `long long'. */
778 #define LONG_LONG_TYPE_SIZE 64
779
780 /* Width in bits of a `long double'. */
781 #define LONG_DOUBLE_TYPE_SIZE 64
782
783 /* Width of a word, in units (bytes). */
784 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
785 #define MIN_UNITS_PER_WORD 4
786
787 /* Scaling factor for Dwarf data offsets for CFI information.
788 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
789 SHmedia; however, since we do partial register saves for the registers
790 visible to SHcompact, and for target registers for SHMEDIA32, we have
791 to allow saves that are only 4-byte aligned. */
792 #define DWARF_CIE_DATA_ALIGNMENT -4
793
794 /* Width in bits of a pointer.
795 See also the macro `Pmode' defined below. */
796 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
797
798 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
799 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
800
801 /* Boundary (in *bits*) on which stack pointer should be aligned. */
802 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
803
804 /* The log (base 2) of the cache line size, in bytes. Processors prior to
805 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
806 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
807 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
808
809 /* ABI given & required minimum allocation boundary (in *bits*) for the
810 code of a function. */
811 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
812
813 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
814 the vbit must go into the delta field of
815 pointers-to-member-functions. */
816 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
817 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
818
819 /* Alignment of field after `int : 0' in a structure. */
820 #define EMPTY_FIELD_BOUNDARY 32
821
822 /* No data type wants to be aligned rounder than this. */
823 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
824
825 /* The best alignment to use in cases where we have a choice. */
826 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
827
828 /* Make strings word-aligned so strcpy from constants will be faster. */
829 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
830 ((TREE_CODE (EXP) == STRING_CST \
831 && (ALIGN) < FASTEST_ALIGNMENT) \
832 ? FASTEST_ALIGNMENT : (ALIGN))
833
834 /* get_mode_alignment assumes complex values are always held in multiple
835 registers, but that is not the case on the SH; CQImode and CHImode are
836 held in a single integer register. SH5 also holds CSImode and SCmode
837 values in integer registers. This is relevant for argument passing on
838 SHcompact as we use a stack temp in order to pass CSImode by reference. */
839 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
840 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
841 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
842 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
843 : (unsigned) ALIGN)
844
845 /* Make arrays of chars word-aligned for the same reasons. */
846 #define DATA_ALIGNMENT(TYPE, ALIGN) \
847 (TREE_CODE (TYPE) == ARRAY_TYPE \
848 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
849 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
850
851 /* Number of bits which any structure or union's size must be a
852 multiple of. Each structure or union's size is rounded up to a
853 multiple of this. */
854 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
855
856 /* Set this nonzero if move instructions will actually fail to work
857 when given unaligned data. */
858 #define STRICT_ALIGNMENT 1
859
860 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
861 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
862 barrier_align (LABEL_AFTER_BARRIER)
863
864 #define LOOP_ALIGN(A_LABEL) \
865 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
866 ? 0 : sh_loop_align (A_LABEL))
867
868 #define LABEL_ALIGN(A_LABEL) \
869 ( \
870 (PREV_INSN (A_LABEL) \
871 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
872 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
873 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
874 /* explicit alignment insn in constant tables. */ \
875 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
876 : 0)
877
878 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
879 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
880
881 /* The base two logarithm of the known minimum alignment of an insn length. */
882 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
883 (GET_CODE (A_INSN) == INSN \
884 ? 1 << TARGET_SHMEDIA \
885 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
886 ? 1 << TARGET_SHMEDIA \
887 : CACHE_LOG)
888 \f
889 /* Standard register usage. */
890
891 /* Register allocation for the Renesas calling convention:
892
893 r0 arg return
894 r1..r3 scratch
895 r4..r7 args in
896 r8..r13 call saved
897 r14 frame pointer/call saved
898 r15 stack pointer
899 ap arg pointer (doesn't really exist, always eliminated)
900 pr subroutine return address
901 t t bit
902 mach multiply/accumulate result, high part
903 macl multiply/accumulate result, low part.
904 fpul fp/int communication register
905 rap return address pointer register
906 fr0 fp arg return
907 fr1..fr3 scratch floating point registers
908 fr4..fr11 fp args in
909 fr12..fr15 call saved floating point registers */
910
911 #define MAX_REGISTER_NAME_LENGTH 5
912 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
913
914 #define SH_REGISTER_NAMES_INITIALIZER \
915 { \
916 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
917 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
918 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
919 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
920 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
921 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
922 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
923 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
924 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
925 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
926 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
927 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
928 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
929 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
930 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
931 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
932 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
933 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
934 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
935 "rap", "sfp" \
936 }
937
938 #define REGNAMES_ARR_INDEX_1(index) \
939 (sh_register_names[index])
940 #define REGNAMES_ARR_INDEX_2(index) \
941 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
942 #define REGNAMES_ARR_INDEX_4(index) \
943 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
944 #define REGNAMES_ARR_INDEX_8(index) \
945 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
946 #define REGNAMES_ARR_INDEX_16(index) \
947 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
948 #define REGNAMES_ARR_INDEX_32(index) \
949 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
950 #define REGNAMES_ARR_INDEX_64(index) \
951 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
952
953 #define REGISTER_NAMES \
954 { \
955 REGNAMES_ARR_INDEX_64 (0), \
956 REGNAMES_ARR_INDEX_64 (64), \
957 REGNAMES_ARR_INDEX_8 (128), \
958 REGNAMES_ARR_INDEX_8 (136), \
959 REGNAMES_ARR_INDEX_8 (144), \
960 REGNAMES_ARR_INDEX_2 (152) \
961 }
962
963 #define ADDREGNAMES_SIZE 32
964 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
965 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
966 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
967
968 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
969 { \
970 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
971 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
972 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
973 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
974 }
975
976 #define ADDREGNAMES_REGNO(index) \
977 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
978 : (-1))
979
980 #define ADDREGNAMES_ARR_INDEX_1(index) \
981 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
982 #define ADDREGNAMES_ARR_INDEX_2(index) \
983 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
984 #define ADDREGNAMES_ARR_INDEX_4(index) \
985 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
986 #define ADDREGNAMES_ARR_INDEX_8(index) \
987 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
988 #define ADDREGNAMES_ARR_INDEX_16(index) \
989 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
990 #define ADDREGNAMES_ARR_INDEX_32(index) \
991 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
992
993 #define ADDITIONAL_REGISTER_NAMES \
994 { \
995 ADDREGNAMES_ARR_INDEX_32 (0) \
996 }
997
998 /* Number of actual hardware registers.
999 The hardware registers are assigned numbers for the compiler
1000 from 0 to just below FIRST_PSEUDO_REGISTER.
1001 All registers that the compiler knows about must be given numbers,
1002 even those that are not normally considered general registers. */
1003
1004 /* There are many other relevant definitions in sh.md's md_constants. */
1005
1006 #define FIRST_GENERAL_REG R0_REG
1007 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1008 #define FIRST_FP_REG DR0_REG
1009 #define LAST_FP_REG (FIRST_FP_REG + \
1010 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1011 #define FIRST_XD_REG XD0_REG
1012 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1013 #define FIRST_TARGET_REG TR0_REG
1014 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1015
1016 #define GENERAL_REGISTER_P(REGNO) \
1017 IN_RANGE ((REGNO), \
1018 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1019 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1020
1021 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1022 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1023 || ((REGNO) == FRAME_POINTER_REGNUM))
1024
1025 #define FP_REGISTER_P(REGNO) \
1026 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1027
1028 #define XD_REGISTER_P(REGNO) \
1029 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1030
1031 #define FP_OR_XD_REGISTER_P(REGNO) \
1032 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1033
1034 #define FP_ANY_REGISTER_P(REGNO) \
1035 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1036
1037 #define SPECIAL_REGISTER_P(REGNO) \
1038 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1039 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1040
1041 #define TARGET_REGISTER_P(REGNO) \
1042 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1043
1044 #define SHMEDIA_REGISTER_P(REGNO) \
1045 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1046 || TARGET_REGISTER_P (REGNO))
1047
1048 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1049 that should be fixed. */
1050 #define VALID_REGISTER_P(REGNO) \
1051 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1052 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1053 || (REGNO) == FRAME_POINTER_REGNUM \
1054 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1055 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1056
1057 /* The mode that should be generally used to store a register by
1058 itself in the stack, or to load it back. */
1059 #define REGISTER_NATURAL_MODE(REGNO) \
1060 (FP_REGISTER_P (REGNO) ? SFmode \
1061 : XD_REGISTER_P (REGNO) ? DFmode \
1062 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1063 ? DImode \
1064 : SImode)
1065
1066 #define FIRST_PSEUDO_REGISTER 154
1067
1068 /* Don't count soft frame pointer. */
1069 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1070
1071 /* 1 for registers that have pervasive standard uses
1072 and are not available for the register allocator.
1073
1074 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1075 It is 32 bits wide for SH2. */
1076
1077 #define FIXED_REGISTERS \
1078 { \
1079 /* Regular registers. */ \
1080 0, 0, 0, 0, 0, 0, 0, 0, \
1081 0, 0, 0, 0, 0, 0, 0, 1, \
1082 /* r16 is reserved, r18 is the former pr. */ \
1083 1, 0, 0, 0, 0, 0, 0, 0, \
1084 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1085 /* r26 is a global variable data pointer; r27 is for constants. */ \
1086 1, 1, 1, 1, 0, 0, 0, 0, \
1087 0, 0, 0, 0, 0, 0, 0, 0, \
1088 0, 0, 0, 0, 0, 0, 0, 0, \
1089 0, 0, 0, 0, 0, 0, 0, 0, \
1090 0, 0, 0, 0, 0, 0, 0, 1, \
1091 /* FP registers. */ \
1092 0, 0, 0, 0, 0, 0, 0, 0, \
1093 0, 0, 0, 0, 0, 0, 0, 0, \
1094 0, 0, 0, 0, 0, 0, 0, 0, \
1095 0, 0, 0, 0, 0, 0, 0, 0, \
1096 0, 0, 0, 0, 0, 0, 0, 0, \
1097 0, 0, 0, 0, 0, 0, 0, 0, \
1098 0, 0, 0, 0, 0, 0, 0, 0, \
1099 0, 0, 0, 0, 0, 0, 0, 0, \
1100 /* Branch target registers. */ \
1101 0, 0, 0, 0, 0, 0, 0, 0, \
1102 /* XD registers. */ \
1103 0, 0, 0, 0, 0, 0, 0, 0, \
1104 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1105 1, 1, 1, 1, 1, 1, 0, 1, \
1106 /*"rap", "sfp" */ \
1107 1, 1, \
1108 }
1109
1110 /* 1 for registers not available across function calls.
1111 These must include the FIXED_REGISTERS and also any
1112 registers that can be used without being saved.
1113 The latter must include the registers where values are returned
1114 and the register where structure-value addresses are passed.
1115 Aside from that, you can include as many other registers as you like. */
1116
1117 #define CALL_USED_REGISTERS \
1118 { \
1119 /* Regular registers. */ \
1120 1, 1, 1, 1, 1, 1, 1, 1, \
1121 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1122 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1123 across SH5 function calls. */ \
1124 0, 0, 0, 0, 0, 0, 0, 1, \
1125 1, 1, 1, 1, 1, 1, 1, 1, \
1126 1, 1, 1, 1, 0, 0, 0, 0, \
1127 0, 0, 0, 0, 1, 1, 1, 1, \
1128 1, 1, 1, 1, 0, 0, 0, 0, \
1129 0, 0, 0, 0, 0, 0, 0, 0, \
1130 0, 0, 0, 0, 1, 1, 1, 1, \
1131 /* FP registers. */ \
1132 1, 1, 1, 1, 1, 1, 1, 1, \
1133 1, 1, 1, 1, 0, 0, 0, 0, \
1134 1, 1, 1, 1, 1, 1, 1, 1, \
1135 1, 1, 1, 1, 1, 1, 1, 1, \
1136 1, 1, 1, 1, 0, 0, 0, 0, \
1137 0, 0, 0, 0, 0, 0, 0, 0, \
1138 0, 0, 0, 0, 0, 0, 0, 0, \
1139 0, 0, 0, 0, 0, 0, 0, 0, \
1140 /* Branch target registers. */ \
1141 1, 1, 1, 1, 1, 0, 0, 0, \
1142 /* XD registers. */ \
1143 1, 1, 1, 1, 1, 1, 0, 0, \
1144 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1145 1, 1, 1, 1, 1, 1, 1, 1, \
1146 /*"rap", "sfp" */ \
1147 1, 1, \
1148 }
1149
1150 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1151 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1152 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1153
1154 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1155 across SHcompact function calls. We can't tell whether a called
1156 function is SHmedia or SHcompact, so we assume it may be when
1157 compiling SHmedia code with the 32-bit ABI, since that's the only
1158 ABI that can be linked with SHcompact code. */
1159 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1160 (TARGET_SHMEDIA32 \
1161 && GET_MODE_SIZE (MODE) > 4 \
1162 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1163 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1164 || TARGET_REGISTER_P (REGNO) \
1165 || (REGNO) == PR_MEDIA_REG))
1166
1167 /* Return number of consecutive hard regs needed starting at reg REGNO
1168 to hold something of mode MODE.
1169 This is ordinarily the length in words of a value of mode MODE
1170 but can be less for certain modes in special long registers.
1171
1172 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1173
1174 #define HARD_REGNO_NREGS(REGNO, MODE) \
1175 (XD_REGISTER_P (REGNO) \
1176 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1177 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1178 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1179 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1180
1181 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1182 We can allow any mode in any general register. The special registers
1183 only allow SImode. Don't allow any mode in the PR. */
1184
1185 /* We cannot hold DCmode values in the XD registers because alter_reg
1186 handles subregs of them incorrectly. We could work around this by
1187 spacing the XD registers like the DR registers, but this would require
1188 additional memory in every compilation to hold larger register vectors.
1189 We could hold SFmode / SCmode values in XD registers, but that
1190 would require a tertiary reload when reloading from / to memory,
1191 and a secondary reload to reload from / to general regs; that
1192 seems to be a loosing proposition. */
1193 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1194 it won't be ferried through GP registers first. */
1195 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1196 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1197 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1198 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1199 ? 1 \
1200 : (MODE) == V2SFmode \
1201 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1202 || GENERAL_REGISTER_P (REGNO)) \
1203 : (MODE) == V4SFmode \
1204 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1205 || GENERAL_REGISTER_P (REGNO)) \
1206 : (MODE) == V16SFmode \
1207 ? (TARGET_SHMEDIA \
1208 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1209 : (REGNO) == FIRST_XD_REG) \
1210 : FP_REGISTER_P (REGNO) \
1211 ? ((MODE) == SFmode || (MODE) == SImode \
1212 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1213 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1214 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1215 || (MODE) == V2SFmode || (MODE) == TImode))) \
1216 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1217 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1218 && (MODE) == TImode \
1219 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1220 : XD_REGISTER_P (REGNO) \
1221 ? (MODE) == DFmode \
1222 : TARGET_REGISTER_P (REGNO) \
1223 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1224 : (REGNO) == PR_REG ? (MODE) == SImode \
1225 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1226 : 1)
1227
1228 /* Value is 1 if it is a good idea to tie two pseudo registers
1229 when one has mode MODE1 and one has mode MODE2.
1230 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1231 for any hard reg, then this must be 0 for correct output.
1232 That's the case for xd registers: we don't hold SFmode values in
1233 them, so we can't tie an SFmode pseudos with one in another
1234 floating-point mode. */
1235
1236 #define MODES_TIEABLE_P(MODE1, MODE2) \
1237 ((MODE1) == (MODE2) \
1238 || (TARGET_SHMEDIA \
1239 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1240 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1241 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1242 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1243 && (GET_MODE_SIZE (MODE2) <= 4)) \
1244 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1245
1246 /* A C expression that is nonzero if hard register NEW_REG can be
1247 considered for use as a rename register for OLD_REG register */
1248
1249 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1250 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1251
1252 /* Specify the registers used for certain standard purposes.
1253 The values of these macros are register numbers. */
1254
1255 /* Define this if the program counter is overloaded on a register. */
1256 /* #define PC_REGNUM 15*/
1257
1258 /* Register to use for pushing function arguments. */
1259 #define STACK_POINTER_REGNUM SP_REG
1260
1261 /* Base register for access to local variables of the function. */
1262 #define HARD_FRAME_POINTER_REGNUM FP_REG
1263
1264 /* Base register for access to local variables of the function. */
1265 #define FRAME_POINTER_REGNUM 153
1266
1267 /* Fake register that holds the address on the stack of the
1268 current function's return address. */
1269 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1270
1271 /* Register to hold the addressing base for position independent
1272 code access to data items. */
1273 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1274
1275 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1276
1277 /* Value should be nonzero if functions must have frame pointers.
1278 Zero means the frame pointer need not be set up (and parms may be accessed
1279 via the stack pointer) in functions that seem suitable. */
1280
1281 #define FRAME_POINTER_REQUIRED 0
1282
1283 /* Definitions for register eliminations.
1284
1285 We have three registers that can be eliminated on the SH. First, the
1286 frame pointer register can often be eliminated in favor of the stack
1287 pointer register. Secondly, the argument pointer register can always be
1288 eliminated; it is replaced with either the stack or frame pointer.
1289 Third, there is the return address pointer, which can also be replaced
1290 with either the stack or the frame pointer. */
1291
1292 /* This is an array of structures. Each structure initializes one pair
1293 of eliminable registers. The "from" register number is given first,
1294 followed by "to". Eliminations of the same "from" register are listed
1295 in order of preference. */
1296
1297 /* If you add any registers here that are not actually hard registers,
1298 and that have any alternative of elimination that doesn't always
1299 apply, you need to amend calc_live_regs to exclude it, because
1300 reload spills all eliminable registers where it sees an
1301 can_eliminate == 0 entry, thus making them 'live' .
1302 If you add any hard registers that can be eliminated in different
1303 ways, you have to patch reload to spill them only when all alternatives
1304 of elimination fail. */
1305
1306 #define ELIMINABLE_REGS \
1307 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1308 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1309 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1310 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1311 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1312 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1313 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1314
1315 /* Given FROM and TO register numbers, say whether this elimination
1316 is allowed. */
1317 #define CAN_ELIMINATE(FROM, TO) \
1318 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1319
1320 /* Define the offset between two registers, one to be eliminated, and the other
1321 its replacement, at the start of a routine. */
1322
1323 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1324 OFFSET = initial_elimination_offset ((FROM), (TO))
1325
1326 /* Base register for access to arguments of the function. */
1327 #define ARG_POINTER_REGNUM AP_REG
1328
1329 /* Register in which the static-chain is passed to a function. */
1330 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1331
1332 /* Don't default to pcc-struct-return, because we have already specified
1333 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1334 target hook. */
1335
1336 #define DEFAULT_PCC_STRUCT_RETURN 0
1337
1338 #define SHMEDIA_REGS_STACK_ADJUST() \
1339 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1340 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1341 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1342 : 0)
1343
1344 \f
1345 /* Define the classes of registers for register constraints in the
1346 machine description. Also define ranges of constants.
1347
1348 One of the classes must always be named ALL_REGS and include all hard regs.
1349 If there is more than one class, another class must be named NO_REGS
1350 and contain no registers.
1351
1352 The name GENERAL_REGS must be the name of a class (or an alias for
1353 another name such as ALL_REGS). This is the class of registers
1354 that is allowed by "g" or "r" in a register constraint.
1355 Also, registers outside this class are allocated only when
1356 instructions express preferences for them.
1357
1358 The classes must be numbered in nondecreasing order; that is,
1359 a larger-numbered class must never be contained completely
1360 in a smaller-numbered class.
1361
1362 For any two classes, it is very desirable that there be another
1363 class that represents their union. */
1364
1365 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1366 be used as the destination of some of the arithmetic ops. There are
1367 also some special purpose registers; the T bit register, the
1368 Procedure Return Register and the Multiply Accumulate Registers. */
1369 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1370 reg_class_subunion. We don't want to have an actual union class
1371 of these, because it would only be used when both classes are calculated
1372 to give the same cost, but there is only one FPUL register.
1373 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1374 applying to the actual instruction alternative considered. E.g., the
1375 y/r alternative of movsi_ie is considered to have no more cost that
1376 the r/r alternative, which is patently untrue. */
1377
1378 enum reg_class
1379 {
1380 NO_REGS,
1381 R0_REGS,
1382 PR_REGS,
1383 T_REGS,
1384 MAC_REGS,
1385 FPUL_REGS,
1386 SIBCALL_REGS,
1387 GENERAL_REGS,
1388 FP0_REGS,
1389 FP_REGS,
1390 DF_HI_REGS,
1391 DF_REGS,
1392 FPSCR_REGS,
1393 GENERAL_FP_REGS,
1394 GENERAL_DF_REGS,
1395 TARGET_REGS,
1396 ALL_REGS,
1397 LIM_REG_CLASSES
1398 };
1399
1400 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1401
1402 /* Give names of register classes as strings for dump file. */
1403 #define REG_CLASS_NAMES \
1404 { \
1405 "NO_REGS", \
1406 "R0_REGS", \
1407 "PR_REGS", \
1408 "T_REGS", \
1409 "MAC_REGS", \
1410 "FPUL_REGS", \
1411 "SIBCALL_REGS", \
1412 "GENERAL_REGS", \
1413 "FP0_REGS", \
1414 "FP_REGS", \
1415 "DF_HI_REGS", \
1416 "DF_REGS", \
1417 "FPSCR_REGS", \
1418 "GENERAL_FP_REGS", \
1419 "GENERAL_DF_REGS", \
1420 "TARGET_REGS", \
1421 "ALL_REGS", \
1422 }
1423
1424 /* Define which registers fit in which classes.
1425 This is an initializer for a vector of HARD_REG_SET
1426 of length N_REG_CLASSES. */
1427
1428 #define REG_CLASS_CONTENTS \
1429 { \
1430 /* NO_REGS: */ \
1431 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1432 /* R0_REGS: */ \
1433 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1434 /* PR_REGS: */ \
1435 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1436 /* T_REGS: */ \
1437 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1438 /* MAC_REGS: */ \
1439 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1440 /* FPUL_REGS: */ \
1441 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1442 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1443 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1444 /* GENERAL_REGS: */ \
1445 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1446 /* FP0_REGS: */ \
1447 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1448 /* FP_REGS: */ \
1449 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1450 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1451 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1452 /* DF_REGS: */ \
1453 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1454 /* FPSCR_REGS: */ \
1455 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1456 /* GENERAL_FP_REGS: */ \
1457 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1458 /* GENERAL_DF_REGS: */ \
1459 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1460 /* TARGET_REGS: */ \
1461 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1462 /* ALL_REGS: */ \
1463 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1464 }
1465
1466 /* The same information, inverted:
1467 Return the class number of the smallest class containing
1468 reg number REGNO. This could be a conditional expression
1469 or could index an array. */
1470
1471 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1472 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1473
1474 /* When defined, the compiler allows registers explicitly used in the
1475 rtl to be used as spill registers but prevents the compiler from
1476 extending the lifetime of these registers. */
1477
1478 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1479
1480 /* The order in which register should be allocated. */
1481 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1482 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1483 spilled or used otherwise, we better have the FP_REGS allocated first. */
1484 #define REG_ALLOC_ORDER \
1485 {/* Caller-saved FPRs */ \
1486 65, 66, 67, 68, 69, 70, 71, 64, \
1487 72, 73, 74, 75, 80, 81, 82, 83, \
1488 84, 85, 86, 87, 88, 89, 90, 91, \
1489 92, 93, 94, 95, 96, 97, 98, 99, \
1490 /* Callee-saved FPRs */ \
1491 76, 77, 78, 79,100,101,102,103, \
1492 104,105,106,107,108,109,110,111, \
1493 112,113,114,115,116,117,118,119, \
1494 120,121,122,123,124,125,126,127, \
1495 136,137,138,139,140,141,142,143, \
1496 /* FPSCR */ 151, \
1497 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1498 1, 2, 3, 7, 6, 5, 4, 0, \
1499 8, 9, 17, 19, 20, 21, 22, 23, \
1500 36, 37, 38, 39, 40, 41, 42, 43, \
1501 60, 61, 62, \
1502 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1503 10, 11, 12, 13, 14, 18, \
1504 /* SH5 callee-saved GPRs */ \
1505 28, 29, 30, 31, 32, 33, 34, 35, \
1506 44, 45, 46, 47, 48, 49, 50, 51, \
1507 52, 53, 54, 55, 56, 57, 58, 59, \
1508 /* FPUL */ 150, \
1509 /* SH5 branch target registers */ \
1510 128,129,130,131,132,133,134,135, \
1511 /* Fixed registers */ \
1512 15, 16, 24, 25, 26, 27, 63,144, \
1513 145,146,147,148,149,152,153 }
1514
1515 /* The class value for index registers, and the one for base regs. */
1516 #define INDEX_REG_CLASS \
1517 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1518 #define BASE_REG_CLASS GENERAL_REGS
1519
1520 /* Get reg_class from a letter such as appears in the machine
1521 description. */
1522 extern enum reg_class reg_class_from_letter[];
1523
1524 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1525 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1526 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1527 \f
1528 /* Overview of uppercase letter constraints:
1529 A: Addresses (constraint len == 3)
1530 Ac4: sh4 cache operations
1531 Ac5: sh5 cache operations
1532 Bxx: miscellaneous constraints
1533 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1534 fldi0 / fldi0 cases
1535 C: Constants other than only CONST_INT (constraint len == 3)
1536 Css: signed 16 bit constant, literal or symbolic
1537 Csu: unsigned 16 bit constant, literal or symbolic
1538 Csy: label or symbol
1539 Cpg: non-explicit constants that can be directly loaded into a general
1540 purpose register in PIC code. like 's' except we don't allow
1541 PIC_DIRECT_ADDR_P
1542 IJKLMNOP: CONT_INT constants
1543 Ixx: signed xx bit
1544 J16: 0xffffffff00000000 | 0x00000000ffffffff
1545 Kxx: unsigned xx bit
1546 M: 1
1547 N: 0
1548 P27: 1 | 2 | 8 | 16
1549 Q: pc relative load operand
1550 Rxx: reserved for exotic register classes.
1551 S: extra memory (storage) constraints (constraint len == 3)
1552 Sua: unaligned memory operations
1553 W: vector
1554 Z: zero in any mode
1555
1556 unused CONST_INT constraint letters: LO
1557 unused EXTRA_CONSTRAINT letters: D T U Y */
1558
1559 #define CONSTRAINT_LEN(C,STR) \
1560 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1561 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1562 || (C) == 'R' || (C) == 'S') \
1563 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1564
1565 /* The letters I, J, K, L and M in a register constraint string
1566 can be used to stand for particular ranges of immediate operands.
1567 This macro defines what the ranges are.
1568 C is the letter, and VALUE is a constant value.
1569 Return 1 if VALUE is in the range specified by C.
1570 I08: arithmetic operand -127..128, as used in add, sub, etc
1571 I16: arithmetic operand -32768..32767, as used in SHmedia movi
1572 K16: arithmetic operand 0..65535, as used in SHmedia shori
1573 P27: shift operand 1,2,8 or 16
1574 K08: logical operand 0..255, as used in and, or, etc.
1575 M: constant 1
1576 N: constant 0
1577 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1578 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1579 */
1580
1581 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1582 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1583 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1584 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1585 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1586 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1587 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1588 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1589 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1590 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1591 && TARGET_SH2A)
1592 #define CONST_OK_FOR_I(VALUE, STR) \
1593 ((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
1594 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1595 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1596 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1597 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1598 : 0)
1599
1600 #define CONST_OK_FOR_J16(VALUE) \
1601 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1602 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1603 #define CONST_OK_FOR_J(VALUE, STR) \
1604 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1605 : 0)
1606
1607 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1608 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1609 #define CONST_OK_FOR_K16(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1610 && ((HOST_WIDE_INT)(VALUE)) <= 65535)
1611 #define CONST_OK_FOR_K(VALUE, STR) \
1612 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1613 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_K16 (VALUE) \
1614 : 0)
1615 #define CONST_OK_FOR_P27(VALUE) \
1616 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1617 #define CONST_OK_FOR_P(VALUE, STR) \
1618 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1619 : 0)
1620 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1621 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1622 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1623 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1624 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1625 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1626 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1627 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1628 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1629 : 0)
1630
1631 /* Similar, but for floating constants, and defining letters G and H.
1632 Here VALUE is the CONST_DOUBLE rtx itself. */
1633
1634 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1635 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1636 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1637 : (C) == 'F')
1638
1639 /* Given an rtx X being reloaded into a reg required to be
1640 in class CLASS, return the class of reg to actually use.
1641 In general this is just CLASS; but on some machines
1642 in some cases it is preferable to use a more restrictive class. */
1643
1644 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1645 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1646 && (GET_CODE (X) == CONST_DOUBLE \
1647 || GET_CODE (X) == SYMBOL_REF \
1648 || PIC_DIRECT_ADDR_P (X)) \
1649 ? GENERAL_REGS \
1650 : (CLASS)) \
1651
1652 #if 0
1653 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1654 ((((REGCLASS_HAS_FP_REG (CLASS) \
1655 && (GET_CODE (X) == REG \
1656 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1657 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1658 && TARGET_FMOVD)))) \
1659 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1660 && GET_CODE (X) == REG \
1661 && FP_REGISTER_P (REGNO (X)))) \
1662 && ! TARGET_SHMEDIA \
1663 && ((MODE) == SFmode || (MODE) == SImode)) \
1664 ? FPUL_REGS \
1665 : (((CLASS) == FPUL_REGS \
1666 || (REGCLASS_HAS_FP_REG (CLASS) \
1667 && ! TARGET_SHMEDIA && MODE == SImode)) \
1668 && (GET_CODE (X) == MEM \
1669 || (GET_CODE (X) == REG \
1670 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1671 || REGNO (X) == T_REG \
1672 || system_reg_operand (X, VOIDmode))))) \
1673 ? GENERAL_REGS \
1674 : (((CLASS) == TARGET_REGS \
1675 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1676 && !EXTRA_CONSTRAINT_Csy (X) \
1677 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1678 ? GENERAL_REGS \
1679 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1680 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1681 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1682 ? GENERAL_REGS \
1683 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1684 && TARGET_REGISTER_P (REGNO (X))) \
1685 ? GENERAL_REGS : (ELSE))
1686
1687 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1688 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1689
1690 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1691 ((REGCLASS_HAS_FP_REG (CLASS) \
1692 && ! TARGET_SHMEDIA \
1693 && immediate_operand ((X), (MODE)) \
1694 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1695 && (MODE) == SFmode && fldi_ok ())) \
1696 ? R0_REGS \
1697 : ((CLASS) == FPUL_REGS \
1698 && ((GET_CODE (X) == REG \
1699 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1700 || REGNO (X) == T_REG)) \
1701 || GET_CODE (X) == PLUS)) \
1702 ? GENERAL_REGS \
1703 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1704 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1705 ? GENERAL_REGS \
1706 : R0_REGS) \
1707 : ((CLASS) == FPSCR_REGS \
1708 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1709 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1710 ? GENERAL_REGS \
1711 : (REGCLASS_HAS_FP_REG (CLASS) \
1712 && TARGET_SHMEDIA \
1713 && immediate_operand ((X), (MODE)) \
1714 && (X) != CONST0_RTX (GET_MODE (X)) \
1715 && GET_MODE (X) != V4SFmode) \
1716 ? GENERAL_REGS \
1717 : (((MODE) == QImode || (MODE) == HImode) \
1718 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1719 ? GENERAL_REGS \
1720 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1721 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1722 ? TARGET_REGS \
1723 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1724 #else
1725 #define HAVE_SECONDARY_RELOADS
1726 #endif
1727
1728 /* Return the maximum number of consecutive registers
1729 needed to represent mode MODE in a register of class CLASS.
1730
1731 If TARGET_SHMEDIA, we need two FP registers per word.
1732 Otherwise we will need at most one register per word. */
1733 #define CLASS_MAX_NREGS(CLASS, MODE) \
1734 (TARGET_SHMEDIA \
1735 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1736 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1737 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1738
1739 /* If defined, gives a class of registers that cannot be used as the
1740 operand of a SUBREG that changes the mode of the object illegally. */
1741 /* ??? We need to renumber the internal numbers for the frnn registers
1742 when in little endian in order to allow mode size changes. */
1743
1744 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1745 sh_cannot_change_mode_class (FROM, TO, CLASS)
1746 \f
1747 /* Stack layout; function entry, exit and calling. */
1748
1749 /* Define the number of registers that can hold parameters.
1750 These macros are used only in other macro definitions below. */
1751
1752 #define NPARM_REGS(MODE) \
1753 (TARGET_FPU_ANY && (MODE) == SFmode \
1754 ? (TARGET_SH5 ? 12 : 8) \
1755 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1756 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1757 ? (TARGET_SH5 ? 12 : 8) \
1758 : (TARGET_SH5 ? 8 : 4))
1759
1760 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1761 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1762
1763 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1764 #define FIRST_FP_RET_REG FIRST_FP_REG
1765
1766 /* Define this if pushing a word on the stack
1767 makes the stack pointer a smaller address. */
1768 #define STACK_GROWS_DOWNWARD
1769
1770 /* Define this macro to nonzero if the addresses of local variable slots
1771 are at negative offsets from the frame pointer. */
1772 #define FRAME_GROWS_DOWNWARD 1
1773
1774 /* Offset from the frame pointer to the first local variable slot to
1775 be allocated. */
1776 #define STARTING_FRAME_OFFSET 0
1777
1778 /* If we generate an insn to push BYTES bytes,
1779 this says how many the stack pointer really advances by. */
1780 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1781 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1782 do correct alignment. */
1783 #if 0
1784 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1785 #endif
1786
1787 /* Offset of first parameter from the argument pointer register value. */
1788 #define FIRST_PARM_OFFSET(FNDECL) 0
1789
1790 /* Value is the number of byte of arguments automatically
1791 popped when returning from a subroutine call.
1792 FUNDECL is the declaration node of the function (as a tree),
1793 FUNTYPE is the data type of the function (as a tree),
1794 or for a library call it is an identifier node for the subroutine name.
1795 SIZE is the number of bytes of arguments passed on the stack.
1796
1797 On the SH, the caller does not pop any of its arguments that were passed
1798 on the stack. */
1799 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1800
1801 /* Value is the number of bytes of arguments automatically popped when
1802 calling a subroutine.
1803 CUM is the accumulated argument list.
1804
1805 On SHcompact, the call trampoline pops arguments off the stack. */
1806 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1807
1808 /* Some subroutine macros specific to this machine. */
1809
1810 #define BASE_RETURN_VALUE_REG(MODE) \
1811 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1812 ? FIRST_FP_RET_REG \
1813 : TARGET_FPU_ANY && (MODE) == SCmode \
1814 ? FIRST_FP_RET_REG \
1815 : (TARGET_FPU_DOUBLE \
1816 && ((MODE) == DFmode || (MODE) == SFmode \
1817 || (MODE) == DCmode || (MODE) == SCmode )) \
1818 ? FIRST_FP_RET_REG \
1819 : FIRST_RET_REG)
1820
1821 #define BASE_ARG_REG(MODE) \
1822 ((TARGET_SH2E && ((MODE) == SFmode)) \
1823 ? FIRST_FP_PARM_REG \
1824 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1825 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1826 ? FIRST_FP_PARM_REG \
1827 : FIRST_PARM_REG)
1828
1829 /* Define how to find the value returned by a function.
1830 VALTYPE is the data type of the value (as a tree).
1831 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1832 otherwise, FUNC is 0.
1833 For the SH, this is like LIBCALL_VALUE, except that we must change the
1834 mode like PROMOTE_MODE does.
1835 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1836 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1837
1838 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1839 gen_rtx_REG ( \
1840 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1841 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1842 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1843 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1844 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1845 || TREE_CODE (VALTYPE) == REAL_TYPE \
1846 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1847 && sh_promote_prototypes (VALTYPE) \
1848 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1849 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1850
1851 /* Define how to find the value returned by a library function
1852 assuming the value has mode MODE. */
1853 #define LIBCALL_VALUE(MODE) \
1854 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1855
1856 /* 1 if N is a possible register number for a function value. */
1857 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1858 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1859 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1860
1861 /* 1 if N is a possible register number for function argument passing. */
1862 /* ??? There are some callers that pass REGNO as int, and others that pass
1863 it as unsigned. We get warnings unless we do casts everywhere. */
1864 #define FUNCTION_ARG_REGNO_P(REGNO) \
1865 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1866 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1867 || (TARGET_FPU_ANY \
1868 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1869 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1870 + NPARM_REGS (SFmode))))
1871 \f
1872 /* Define a data type for recording info about an argument list
1873 during the scan of that argument list. This data type should
1874 hold all necessary information about the function itself
1875 and about the args processed so far, enough to enable macros
1876 such as FUNCTION_ARG to determine where the next arg should go.
1877
1878 On SH, this is a single integer, which is a number of words
1879 of arguments scanned so far (including the invisible argument,
1880 if any, which holds the structure-value-address).
1881 Thus NARGREGS or more means all following args should go on the stack. */
1882
1883 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1884 struct sh_args {
1885 int arg_count[2];
1886 int force_mem;
1887 /* Nonzero if a prototype is available for the function. */
1888 int prototype_p;
1889 /* The number of an odd floating-point register, that should be used
1890 for the next argument of type float. */
1891 int free_single_fp_reg;
1892 /* Whether we're processing an outgoing function call. */
1893 int outgoing;
1894 /* The number of general-purpose registers that should have been
1895 used to pass partial arguments, that are passed totally on the
1896 stack. On SHcompact, a call trampoline will pop them off the
1897 stack before calling the actual function, and, if the called
1898 function is implemented in SHcompact mode, the incoming arguments
1899 decoder will push such arguments back onto the stack. For
1900 incoming arguments, STACK_REGS also takes into account other
1901 arguments passed by reference, that the decoder will also push
1902 onto the stack. */
1903 int stack_regs;
1904 /* The number of general-purpose registers that should have been
1905 used to pass arguments, if the arguments didn't have to be passed
1906 by reference. */
1907 int byref_regs;
1908 /* Set as by shcompact_byref if the current argument is to be passed
1909 by reference. */
1910 int byref;
1911
1912 /* call_cookie is a bitmask used by call expanders, as well as
1913 function prologue and epilogues, to allow SHcompact to comply
1914 with the SH5 32-bit ABI, that requires 64-bit registers to be
1915 used even though only the lower 32-bit half is visible in
1916 SHcompact mode. The strategy is to call SHmedia trampolines.
1917
1918 The alternatives for each of the argument-passing registers are
1919 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1920 contents from the address in it; (d) add 8 to it, storing the
1921 result in the next register, then (c); (e) copy it from some
1922 floating-point register,
1923
1924 Regarding copies from floating-point registers, r2 may only be
1925 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1926 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1927 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1928 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1929 dr10.
1930
1931 The bit mask is structured as follows:
1932
1933 - 1 bit to tell whether to set up a return trampoline.
1934
1935 - 3 bits to count the number consecutive registers to pop off the
1936 stack.
1937
1938 - 4 bits for each of r9, r8, r7 and r6.
1939
1940 - 3 bits for each of r5, r4, r3 and r2.
1941
1942 - 3 bits set to 0 (the most significant ones)
1943
1944 3 2 1 0
1945 1098 7654 3210 9876 5432 1098 7654 3210
1946 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1947 2223 3344 4555 6666 7777 8888 9999 SSS-
1948
1949 - If F is set, the register must be copied from an FP register,
1950 whose number is encoded in the remaining bits.
1951
1952 - Else, if L is set, the register must be loaded from the address
1953 contained in it. If the P bit is *not* set, the address of the
1954 following dword should be computed first, and stored in the
1955 following register.
1956
1957 - Else, if P is set, the register alone should be popped off the
1958 stack.
1959
1960 - After all this processing, the number of registers represented
1961 in SSS will be popped off the stack. This is an optimization
1962 for pushing/popping consecutive registers, typically used for
1963 varargs and large arguments partially passed in registers.
1964
1965 - If T is set, a return trampoline will be set up for 64-bit
1966 return values to be split into 2 32-bit registers. */
1967 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1968 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1969 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1970 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1971 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1972 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1973 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1974 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1975 #define CALL_COOKIE_INT_REG(REG, VAL) \
1976 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1977 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1978 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1979 long call_cookie;
1980
1981 /* This is set to nonzero when the call in question must use the Renesas ABI,
1982 even without the -mrenesas option. */
1983 int renesas_abi;
1984 };
1985
1986 #define CUMULATIVE_ARGS struct sh_args
1987
1988 #define GET_SH_ARG_CLASS(MODE) \
1989 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1990 ? SH_ARG_FLOAT \
1991 /* There's no mention of complex float types in the SH5 ABI, so we
1992 should presumably handle them as aggregate types. */ \
1993 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1994 ? SH_ARG_INT \
1995 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1996 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1997 ? SH_ARG_FLOAT : SH_ARG_INT)
1998
1999 #define ROUND_ADVANCE(SIZE) \
2000 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2001
2002 /* Round a register number up to a proper boundary for an arg of mode
2003 MODE.
2004
2005 The SH doesn't care about double alignment, so we only
2006 round doubles to even regs when asked to explicitly. */
2007
2008 #define ROUND_REG(CUM, MODE) \
2009 (((TARGET_ALIGN_DOUBLE \
2010 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
2011 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2012 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
2013 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2014 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
2015 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2016
2017 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2018 for a call to a function whose data type is FNTYPE.
2019 For a library call, FNTYPE is 0.
2020
2021 On SH, the offset always starts at 0: the first parm reg is always
2022 the same reg for a given argument class.
2023
2024 For TARGET_HITACHI, the structure value pointer is passed in memory. */
2025
2026 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2027 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
2028
2029 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2030 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
2031
2032 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2033 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2034 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2035 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2036
2037 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2038 This macro is only used in this file. */
2039
2040 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2041 (((TYPE) == 0 \
2042 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2043 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2044 || ! (AGGREGATE_TYPE_P (TYPE) \
2045 || (!TARGET_FPU_ANY \
2046 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2047 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2048 && ! (CUM).force_mem \
2049 && (TARGET_SH2E \
2050 ? ((MODE) == BLKmode \
2051 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2052 + int_size_in_bytes (TYPE)) \
2053 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2054 : ((ROUND_REG((CUM), (MODE)) \
2055 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2056 <= NPARM_REGS (MODE))) \
2057 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2058
2059 /* By accident we got stuck with passing SCmode on SH4 little endian
2060 in two registers that are nominally successive - which is different from
2061 two single SFmode values, where we take endianness translation into
2062 account. That does not work at all if an odd number of registers is
2063 already in use, so that got fixed, but library functions are still more
2064 likely to use complex numbers without mixing them with SFmode arguments
2065 (which in C would have to be structures), so for the sake of ABI
2066 compatibility the way SCmode values are passed when an even number of
2067 FP registers is in use remains different from a pair of SFmode values for
2068 now.
2069 I.e.:
2070 foo (double); a: fr5,fr4
2071 foo (float a, float b); a: fr5 b: fr4
2072 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2073 this should be the other way round...
2074 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2075 #define FUNCTION_ARG_SCmode_WART 1
2076
2077 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2078 register in SHcompact mode, it must be padded in the most
2079 significant end. This means that passing it by reference wouldn't
2080 pad properly on a big-endian machine. In this particular case, we
2081 pass this argument on the stack, in a way that the call trampoline
2082 will load its value into the appropriate register. */
2083 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2084 ((MODE) == BLKmode \
2085 && TARGET_SHCOMPACT \
2086 && ! TARGET_LITTLE_ENDIAN \
2087 && int_size_in_bytes (TYPE) > 4 \
2088 && int_size_in_bytes (TYPE) < 8)
2089
2090 /* Minimum alignment for an argument to be passed by callee-copy
2091 reference. We need such arguments to be aligned to 8 byte
2092 boundaries, because they'll be loaded using quad loads. */
2093 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2094
2095 /* The SH5 ABI requires floating-point arguments to be passed to
2096 functions without a prototype in both an FP register and a regular
2097 register or the stack. When passing the argument in both FP and
2098 general-purpose registers, list the FP register first. */
2099 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2100 (gen_rtx_PARALLEL \
2101 ((MODE), \
2102 gen_rtvec (2, \
2103 gen_rtx_EXPR_LIST \
2104 (VOIDmode, \
2105 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2106 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2107 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2108 : NULL_RTX), \
2109 const0_rtx), \
2110 gen_rtx_EXPR_LIST \
2111 (VOIDmode, \
2112 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2113 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2114 + (CUM).arg_count[(int) SH_ARG_INT]) \
2115 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2116 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2117 const0_rtx))))
2118
2119 /* The SH5 ABI requires regular registers or stack slots to be
2120 reserved for floating-point arguments. Registers are taken care of
2121 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2122 Unfortunately, there's no way to just reserve a stack slot, so
2123 we'll end up needlessly storing a copy of the argument in the
2124 stack. For incoming arguments, however, the PARALLEL will be
2125 optimized to the register-only form, and the value in the stack
2126 slot won't be used at all. */
2127 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2128 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2129 ? gen_rtx_REG ((MODE), (REG)) \
2130 : gen_rtx_PARALLEL ((MODE), \
2131 gen_rtvec (2, \
2132 gen_rtx_EXPR_LIST \
2133 (VOIDmode, NULL_RTX, \
2134 const0_rtx), \
2135 gen_rtx_EXPR_LIST \
2136 (VOIDmode, gen_rtx_REG ((MODE), \
2137 (REG)), \
2138 const0_rtx))))
2139
2140 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2141 (TARGET_SH5 \
2142 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2143 || (MODE) == DCmode) \
2144 && ((CUM).arg_count[(int) SH_ARG_INT] \
2145 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2146 : GET_MODE_SIZE (MODE)) \
2147 + 7) / 8) > NPARM_REGS (SImode))
2148
2149 /* Perform any needed actions needed for a function that is receiving a
2150 variable number of arguments. */
2151
2152 /* Implement `va_start' for varargs and stdarg. */
2153 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2154 sh_va_start (valist, nextarg)
2155
2156 /* Call the function profiler with a given profile label.
2157 We use two .aligns, so as to make sure that both the .long is aligned
2158 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2159 from the trapa instruction. */
2160
2161 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2162 { \
2163 if (TARGET_SHMEDIA) \
2164 { \
2165 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2166 fprintf((STREAM), "\ttrapa\tr0\n"); \
2167 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2168 } \
2169 else \
2170 { \
2171 fprintf((STREAM), "\t.align\t2\n"); \
2172 fprintf((STREAM), "\ttrapa\t#33\n"); \
2173 fprintf((STREAM), "\t.align\t2\n"); \
2174 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2175 } \
2176 }
2177
2178 /* Define this macro if the code for function profiling should come
2179 before the function prologue. Normally, the profiling code comes
2180 after. */
2181
2182 #define PROFILE_BEFORE_PROLOGUE
2183
2184 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2185 the stack pointer does not matter. The value is tested only in
2186 functions that have frame pointers.
2187 No definition is equivalent to always zero. */
2188
2189 #define EXIT_IGNORE_STACK 1
2190
2191 /*
2192 On the SH, the trampoline looks like
2193 2 0002 D202 mov.l l2,r2
2194 1 0000 D301 mov.l l1,r3
2195 3 0004 422B jmp @r2
2196 4 0006 0009 nop
2197 5 0008 00000000 l1: .long area
2198 6 000c 00000000 l2: .long function */
2199
2200 /* Length in units of the trampoline for entering a nested function. */
2201 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2202
2203 /* Alignment required for a trampoline in bits . */
2204 #define TRAMPOLINE_ALIGNMENT \
2205 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2206 : TARGET_SHMEDIA ? 256 : 64)
2207
2208 /* Emit RTL insns to initialize the variable parts of a trampoline.
2209 FNADDR is an RTX for the address of the function's pure code.
2210 CXT is an RTX for the static chain value for the function. */
2211
2212 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2213 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2214
2215 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2216
2217 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2218 { \
2219 if (TARGET_SHMEDIA) \
2220 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2221 gen_reg_rtx (Pmode), 0, \
2222 OPTAB_LIB_WIDEN); \
2223 } while (0)
2224
2225 /* A C expression whose value is RTL representing the value of the return
2226 address for the frame COUNT steps up from the current frame.
2227 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2228 can ignore COUNT. */
2229
2230 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2231 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2232
2233 /* A C expression whose value is RTL representing the location of the
2234 incoming return address at the beginning of any function, before the
2235 prologue. This RTL is either a REG, indicating that the return
2236 value is saved in REG, or a MEM representing a location in
2237 the stack. */
2238 #define INCOMING_RETURN_ADDR_RTX \
2239 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2240 \f
2241 /* Addressing modes, and classification of registers for them. */
2242 #define HAVE_POST_INCREMENT TARGET_SH1
2243 #define HAVE_PRE_DECREMENT TARGET_SH1
2244
2245 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2246 ? 0 : TARGET_SH1)
2247 #define USE_LOAD_PRE_DECREMENT(mode) 0
2248 #define USE_STORE_POST_INCREMENT(mode) 0
2249 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2250 ? 0 : TARGET_SH1)
2251
2252 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2253 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2254 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2255
2256 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2257 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2258 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2259
2260 /* Macros to check register numbers against specific register classes. */
2261
2262 /* These assume that REGNO is a hard or pseudo reg number.
2263 They give nonzero only if REGNO is a hard reg of the suitable class
2264 or a pseudo reg currently allocated to a suitable hard reg.
2265 Since they use reg_renumber, they are safe only once reg_renumber
2266 has been allocated, which happens in local-alloc.c. */
2267
2268 #define REGNO_OK_FOR_BASE_P(REGNO) \
2269 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2270 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2271 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2272 (TARGET_SHMEDIA \
2273 ? (GENERAL_REGISTER_P (REGNO) \
2274 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2275 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2276
2277 /* Maximum number of registers that can appear in a valid memory
2278 address. */
2279
2280 #define MAX_REGS_PER_ADDRESS 2
2281
2282 /* Recognize any constant value that is a valid address. */
2283
2284 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2285
2286 /* Nonzero if the constant value X is a legitimate general operand. */
2287
2288 #define LEGITIMATE_CONSTANT_P(X) \
2289 (TARGET_SHMEDIA \
2290 ? ((GET_MODE (X) != DFmode \
2291 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2292 || (X) == CONST0_RTX (GET_MODE (X)) \
2293 || ! TARGET_SHMEDIA_FPU \
2294 || TARGET_SHMEDIA64) \
2295 : (GET_CODE (X) != CONST_DOUBLE \
2296 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2297 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2298
2299 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2300 and check its validity for a certain class.
2301 We have two alternate definitions for each of them.
2302 The usual definition accepts all pseudo regs; the other rejects
2303 them unless they have been allocated suitable hard regs.
2304 The symbol REG_OK_STRICT causes the latter definition to be used. */
2305
2306 #ifndef REG_OK_STRICT
2307
2308 /* Nonzero if X is a hard reg that can be used as a base reg
2309 or if it is a pseudo reg. */
2310 #define REG_OK_FOR_BASE_P(X) \
2311 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2312
2313 /* Nonzero if X is a hard reg that can be used as an index
2314 or if it is a pseudo reg. */
2315 #define REG_OK_FOR_INDEX_P(X) \
2316 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2317 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2318
2319 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2320 or if X is a pseudo reg. */
2321 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2322 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2323 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2324
2325 #else
2326
2327 /* Nonzero if X is a hard reg that can be used as a base reg. */
2328 #define REG_OK_FOR_BASE_P(X) \
2329 REGNO_OK_FOR_BASE_P (REGNO (X))
2330
2331 /* Nonzero if X is a hard reg that can be used as an index. */
2332 #define REG_OK_FOR_INDEX_P(X) \
2333 REGNO_OK_FOR_INDEX_P (REGNO (X))
2334
2335 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2336 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2337 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2338
2339 #endif
2340
2341 /* The 'Q' constraint is a pc relative load operand. */
2342 #define EXTRA_CONSTRAINT_Q(OP) \
2343 (GET_CODE (OP) == MEM \
2344 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2345 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2346 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2347 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2348 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2349
2350 /* Extra address constraints. */
2351 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2352
2353 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2354 operand is not SCRATCH (i.e. REG) then R0 is probably being
2355 used, hence mova is being used, hence do not select this pattern */
2356 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2357 #define EXTRA_CONSTRAINT_B(OP, STR) \
2358 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2359 : 0)
2360
2361 /* The `Css' constraint is a signed 16-bit constant, literal or symbolic. */
2362 #define EXTRA_CONSTRAINT_Css(OP) \
2363 (GET_CODE (OP) == CONST \
2364 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2365 && (GET_MODE (XEXP ((OP), 0)) == DImode \
2366 || GET_MODE (XEXP ((OP), 0)) == SImode) \
2367 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2368 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2369 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2370 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2371 && (MOVI_SHORI_BASE_OPERAND_P \
2372 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2373 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2374 1)) == CONST_INT)))
2375
2376 /* The `Csu' constraint is an unsigned 16-bit constant, literal or symbolic. */
2377 #define EXTRA_CONSTRAINT_Csu(OP) \
2378 (GET_CODE (OP) == CONST \
2379 && GET_CODE (XEXP ((OP), 0)) == ZERO_EXTEND \
2380 && (GET_MODE (XEXP ((OP), 0)) == DImode \
2381 || GET_MODE (XEXP ((OP), 0)) == SImode) \
2382 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2383 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2384 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2385 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2386 && (MOVI_SHORI_BASE_OPERAND_P \
2387 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2388 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2389 1)) == CONST_INT)))
2390
2391 /* Check whether OP is a datalabel unspec. */
2392 #define DATALABEL_REF_NO_CONST_P(OP) \
2393 (GET_CODE (OP) == UNSPEC \
2394 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2395 && XVECLEN ((OP), 0) == 1 \
2396 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2397
2398 #define GOT_ENTRY_P(OP) \
2399 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2400 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2401
2402 #define GOTPLT_ENTRY_P(OP) \
2403 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2404 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2405
2406 #define UNSPEC_GOTOFF_P(OP) \
2407 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2408
2409 #define GOTOFF_P(OP) \
2410 (GET_CODE (OP) == CONST \
2411 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2412 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2413 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2414 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2415
2416 #define PIC_ADDR_P(OP) \
2417 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2418 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2419
2420 #define PIC_OFFSET_P(OP) \
2421 (PIC_ADDR_P (OP) \
2422 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2423 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2424
2425 #define PIC_DIRECT_ADDR_P(OP) \
2426 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2427
2428 #define NON_PIC_REFERENCE_P(OP) \
2429 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2430 || (GET_CODE (OP) == CONST \
2431 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2432 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2433 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2434 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2435 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2436 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2437 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2438 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2439
2440 #define PIC_REFERENCE_P(OP) \
2441 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2442 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2443
2444 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2445 (flag_pic \
2446 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2447 || PIC_OFFSET_P (OP)) \
2448 : NON_PIC_REFERENCE_P (OP))
2449
2450 /* The `Csy' constraint is a label or a symbol. */
2451 #define EXTRA_CONSTRAINT_Csy(OP) \
2452 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2453
2454 /* A zero in any shape or form. */
2455 #define EXTRA_CONSTRAINT_Z(OP) \
2456 ((OP) == CONST0_RTX (GET_MODE (OP)))
2457
2458 /* Any vector constant we can handle. */
2459 #define EXTRA_CONSTRAINT_W(OP) \
2460 (GET_CODE (OP) == CONST_VECTOR \
2461 && (sh_rep_vec ((OP), VOIDmode) \
2462 || (HOST_BITS_PER_WIDE_INT >= 64 \
2463 ? sh_const_vec ((OP), VOIDmode) \
2464 : sh_1el_vec ((OP), VOIDmode))))
2465
2466 /* A non-explicit constant that can be loaded directly into a general purpose
2467 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2468 #define EXTRA_CONSTRAINT_Cpg(OP) \
2469 (CONSTANT_P (OP) \
2470 && GET_CODE (OP) != CONST_INT \
2471 && GET_CODE (OP) != CONST_DOUBLE \
2472 && (!flag_pic \
2473 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2474 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2475 && GET_CODE (OP) != LABEL_REF)))
2476 #define EXTRA_CONSTRAINT_C(OP, STR) \
2477 ((STR)[1] == 's' && (STR)[2] == 's' ? EXTRA_CONSTRAINT_Css (OP) \
2478 : (STR)[1] == 's' && (STR)[2] == 'u' ? EXTRA_CONSTRAINT_Csu (OP) \
2479 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2480 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2481 : 0)
2482
2483 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2484 #define EXTRA_CONSTRAINT_Sr0(OP) \
2485 (memory_operand((OP), GET_MODE (OP)) \
2486 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2487 #define EXTRA_CONSTRAINT_Sua(OP) \
2488 (memory_operand((OP), GET_MODE (OP)) \
2489 && GET_CODE (XEXP (OP, 0)) != PLUS)
2490 #define EXTRA_CONSTRAINT_S(OP, STR) \
2491 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2492 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2493 : 0)
2494
2495 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2496 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2497 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2498 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2499 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2500 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2501 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2502 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2503 : 0)
2504 \f
2505 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2506 that is a valid memory address for an instruction.
2507 The MODE argument is the machine mode for the MEM expression
2508 that wants to use this address. */
2509
2510 #define MODE_DISP_OK_4(X,MODE) \
2511 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2512 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2513
2514 #define MODE_DISP_OK_8(X,MODE) \
2515 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2516 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2517
2518 #undef MODE_DISP_OK_4
2519 #define MODE_DISP_OK_4(X,MODE) \
2520 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2521 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2522 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2523 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2524
2525 #undef MODE_DISP_OK_8
2526 #define MODE_DISP_OK_8(X,MODE) \
2527 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2528 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2529 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2530 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2531
2532 #define BASE_REGISTER_RTX_P(X) \
2533 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2534 || (GET_CODE (X) == SUBREG \
2535 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2536 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2537 && GET_CODE (SUBREG_REG (X)) == REG \
2538 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2539
2540 /* Since this must be r0, which is a single register class, we must check
2541 SUBREGs more carefully, to be sure that we don't accept one that extends
2542 outside the class. */
2543 #define INDEX_REGISTER_RTX_P(X) \
2544 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2545 || (GET_CODE (X) == SUBREG \
2546 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2547 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2548 && GET_CODE (SUBREG_REG (X)) == REG \
2549 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2550
2551 /* Jump to LABEL if X is a valid address RTX. This must also take
2552 REG_OK_STRICT into account when deciding about valid registers, but it uses
2553 the above macros so we are in luck.
2554
2555 Allow REG
2556 REG+disp
2557 REG+r0
2558 REG++
2559 --REG */
2560
2561 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2562 into the FRx registers. We implement this by setting the maximum offset
2563 to zero when the value is SFmode. This also restricts loading of SFmode
2564 values into the integer registers, but that can't be helped. */
2565
2566 /* The SH allows a displacement in a QI or HI amode, but only when the
2567 other operand is R0. GCC doesn't handle this very well, so we forgo
2568 all of that.
2569
2570 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2571 DI can be any number 0..60. */
2572
2573 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2574 do { \
2575 if (GET_CODE (OP) == CONST_INT) \
2576 { \
2577 if (TARGET_SHMEDIA) \
2578 { \
2579 int MODE_SIZE; \
2580 /* Check if this the address of an unaligned load / store. */\
2581 if ((MODE) == VOIDmode) \
2582 { \
2583 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2584 goto LABEL; \
2585 break; \
2586 } \
2587 MODE_SIZE = GET_MODE_SIZE (MODE); \
2588 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2589 && INTVAL (OP) >= -512 * MODE_SIZE \
2590 && INTVAL (OP) < 512 * MODE_SIZE) \
2591 goto LABEL; \
2592 else \
2593 break; \
2594 } \
2595 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2596 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2597 } \
2598 } while(0)
2599
2600 #define ALLOW_INDEXED_ADDRESS \
2601 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2602
2603 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2604 { \
2605 if (BASE_REGISTER_RTX_P (X)) \
2606 goto LABEL; \
2607 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2608 && ! TARGET_SHMEDIA \
2609 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2610 goto LABEL; \
2611 else if (GET_CODE (X) == PLUS \
2612 && ((MODE) != PSImode || reload_completed)) \
2613 { \
2614 rtx xop0 = XEXP ((X), 0); \
2615 rtx xop1 = XEXP ((X), 1); \
2616 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2617 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2618 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2619 || ((xop0 == stack_pointer_rtx \
2620 || xop0 == hard_frame_pointer_rtx) \
2621 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2622 || ((xop1 == stack_pointer_rtx \
2623 || xop1 == hard_frame_pointer_rtx) \
2624 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2625 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2626 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2627 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2628 && TARGET_FMOVD && MODE == DFmode))) \
2629 { \
2630 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2631 goto LABEL; \
2632 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2633 goto LABEL; \
2634 } \
2635 } \
2636 }
2637 \f
2638 /* Try machine-dependent ways of modifying an illegitimate address
2639 to be legitimate. If we find one, return the new, valid address.
2640 This macro is used in only one place: `memory_address' in explow.c.
2641
2642 OLDX is the address as it was before break_out_memory_refs was called.
2643 In some cases it is useful to look at this to decide what needs to be done.
2644
2645 MODE and WIN are passed so that this macro can use
2646 GO_IF_LEGITIMATE_ADDRESS.
2647
2648 It is always safe for this macro to do nothing. It exists to recognize
2649 opportunities to optimize the output.
2650
2651 For the SH, if X is almost suitable for indexing, but the offset is
2652 out of range, convert it into a normal form so that cse has a chance
2653 of reducing the number of address registers used. */
2654
2655 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2656 { \
2657 if (flag_pic) \
2658 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2659 if (GET_CODE (X) == PLUS \
2660 && (GET_MODE_SIZE (MODE) == 4 \
2661 || GET_MODE_SIZE (MODE) == 8) \
2662 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2663 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2664 && ! TARGET_SHMEDIA \
2665 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2666 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2667 { \
2668 rtx index_rtx = XEXP ((X), 1); \
2669 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2670 rtx sum; \
2671 \
2672 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2673 /* On rare occasions, we might get an unaligned pointer \
2674 that is indexed in a way to give an aligned address. \
2675 Therefore, keep the lower two bits in offset_base. */ \
2676 /* Instead of offset_base 128..131 use 124..127, so that \
2677 simple add suffices. */ \
2678 if (offset > 127) \
2679 { \
2680 offset_base = ((offset + 4) & ~60) - 4; \
2681 } \
2682 else \
2683 offset_base = offset & ~60; \
2684 /* Sometimes the normal form does not suit DImode. We \
2685 could avoid that by using smaller ranges, but that \
2686 would give less optimized code when SImode is \
2687 prevalent. */ \
2688 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2689 { \
2690 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2691 GEN_INT (offset_base), NULL_RTX, 0, \
2692 OPTAB_LIB_WIDEN); \
2693 \
2694 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2695 goto WIN; \
2696 } \
2697 } \
2698 }
2699
2700 /* A C compound statement that attempts to replace X, which is an address
2701 that needs reloading, with a valid memory address for an operand of
2702 mode MODE. WIN is a C statement label elsewhere in the code.
2703
2704 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2705 of the address. That will allow inheritance of the address reloads. */
2706
2707 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2708 { \
2709 if (GET_CODE (X) == PLUS \
2710 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2711 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2712 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2713 && ! TARGET_SHMEDIA \
2714 && ! (TARGET_SH4 && (MODE) == DFmode) \
2715 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2716 && (ALLOW_INDEXED_ADDRESS \
2717 || XEXP ((X), 0) == stack_pointer_rtx \
2718 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2719 { \
2720 rtx index_rtx = XEXP (X, 1); \
2721 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2722 rtx sum; \
2723 \
2724 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2725 { \
2726 push_reload (X, NULL_RTX, &X, NULL, \
2727 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2728 (TYPE)); \
2729 goto WIN; \
2730 } \
2731 if (TARGET_SH2E && MODE == SFmode) \
2732 { \
2733 X = copy_rtx (X); \
2734 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2735 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2736 (TYPE)); \
2737 goto WIN; \
2738 } \
2739 /* Instead of offset_base 128..131 use 124..127, so that \
2740 simple add suffices. */ \
2741 if (offset > 127) \
2742 { \
2743 offset_base = ((offset + 4) & ~60) - 4; \
2744 } \
2745 else \
2746 offset_base = offset & ~60; \
2747 /* Sometimes the normal form does not suit DImode. We \
2748 could avoid that by using smaller ranges, but that \
2749 would give less optimized code when SImode is \
2750 prevalent. */ \
2751 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2752 { \
2753 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2754 GEN_INT (offset_base)); \
2755 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2756 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2757 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2758 (TYPE)); \
2759 goto WIN; \
2760 } \
2761 } \
2762 /* We must re-recognize what we created before. */ \
2763 else if (GET_CODE (X) == PLUS \
2764 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2765 && GET_CODE (XEXP (X, 0)) == PLUS \
2766 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2767 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2768 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2769 && ! TARGET_SHMEDIA \
2770 && ! (TARGET_SH2E && MODE == SFmode)) \
2771 { \
2772 /* Because this address is so complex, we know it must have \
2773 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2774 it is already unshared, and needs no further unsharing. */ \
2775 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2776 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2777 goto WIN; \
2778 } \
2779 }
2780
2781 /* Go to LABEL if ADDR (a legitimate address expression)
2782 has an effect that depends on the machine mode it is used for.
2783
2784 ??? Strictly speaking, we should also include all indexed addressing,
2785 because the index scale factor is the length of the operand.
2786 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2787 high if we did that. So we rely on reload to fix things up. */
2788
2789 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2790 { \
2791 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2792 goto LABEL; \
2793 }
2794 \f
2795 /* Specify the machine mode that this machine uses
2796 for the index in the tablejump instruction. */
2797 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2798
2799 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2800 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2801 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2802 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2803 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2804 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2805 : SImode)
2806
2807 /* Define as C expression which evaluates to nonzero if the tablejump
2808 instruction expects the table to contain offsets from the address of the
2809 table.
2810 Do not define this if the table should contain absolute addresses. */
2811 #define CASE_VECTOR_PC_RELATIVE 1
2812
2813 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2814 #define FLOAT_TYPE_SIZE 32
2815
2816 /* Since the SH2e has only `float' support, it is desirable to make all
2817 floating point types equivalent to `float'. */
2818 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2819
2820 /* 'char' is signed by default. */
2821 #define DEFAULT_SIGNED_CHAR 1
2822
2823 /* The type of size_t unsigned int. */
2824 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2825
2826 #undef PTRDIFF_TYPE
2827 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2828
2829 #define WCHAR_TYPE "short unsigned int"
2830 #define WCHAR_TYPE_SIZE 16
2831
2832 #define SH_ELF_WCHAR_TYPE "long int"
2833
2834 /* Max number of bytes we can move from memory to memory
2835 in one reasonably fast instruction. */
2836 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2837
2838 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2839 MOVE_MAX is not a compile-time constant. */
2840 #define MAX_MOVE_MAX 8
2841
2842 /* Max number of bytes we want move_by_pieces to be able to copy
2843 efficiently. */
2844 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2845
2846 /* Define if operations between registers always perform the operation
2847 on the full register even if a narrower mode is specified. */
2848 #define WORD_REGISTER_OPERATIONS
2849
2850 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2851 will either zero-extend or sign-extend. The value of this macro should
2852 be the code that says which one of the two operations is implicitly
2853 done, UNKNOWN if none. */
2854 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2855 /* FP registers can load SImode values, but don't implicitly sign-extend
2856 them to DImode. */
2857 #define LOAD_EXTEND_OP(MODE) \
2858 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2859 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2860
2861 /* Define if loading short immediate values into registers sign extends. */
2862 #define SHORT_IMMEDIATES_SIGN_EXTEND
2863
2864 /* Nonzero if access to memory by bytes is no faster than for words. */
2865 #define SLOW_BYTE_ACCESS 1
2866
2867 /* Immediate shift counts are truncated by the output routines (or was it
2868 the assembler?). Shift counts in a register are truncated by SH. Note
2869 that the native compiler puts too large (> 32) immediate shift counts
2870 into a register and shifts by the register, letting the SH decide what
2871 to do instead of doing that itself. */
2872 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2873 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2874 expects - the sign bit is significant - so it appears that we need to
2875 leave this zero for correct SH3 code. */
2876 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2877
2878 /* All integers have the same format so truncation is easy. */
2879 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2880 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2881 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2882
2883 /* Define this if addresses of constant functions
2884 shouldn't be put through pseudo regs where they can be cse'd.
2885 Desirable on machines where ordinary constants are expensive
2886 but a CALL with constant address is cheap. */
2887 /*#define NO_FUNCTION_CSE 1*/
2888
2889 /* The machine modes of pointers and functions. */
2890 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2891 #define FUNCTION_MODE Pmode
2892
2893 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2894 are actually function calls with some special constraints on arguments
2895 and register usage.
2896
2897 These macros tell reorg that the references to arguments and
2898 register clobbers for insns of type sfunc do not appear to happen
2899 until after the millicode call. This allows reorg to put insns
2900 which set the argument registers into the delay slot of the millicode
2901 call -- thus they act more like traditional CALL_INSNs.
2902
2903 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2904 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2905 in particular. */
2906
2907 #define INSN_SETS_ARE_DELAYED(X) \
2908 ((GET_CODE (X) == INSN \
2909 && GET_CODE (PATTERN (X)) != SEQUENCE \
2910 && GET_CODE (PATTERN (X)) != USE \
2911 && GET_CODE (PATTERN (X)) != CLOBBER \
2912 && get_attr_is_sfunc (X)))
2913
2914 #define INSN_REFERENCES_ARE_DELAYED(X) \
2915 ((GET_CODE (X) == INSN \
2916 && GET_CODE (PATTERN (X)) != SEQUENCE \
2917 && GET_CODE (PATTERN (X)) != USE \
2918 && GET_CODE (PATTERN (X)) != CLOBBER \
2919 && get_attr_is_sfunc (X)))
2920
2921 \f
2922 /* Position Independent Code. */
2923
2924 /* We can't directly access anything that contains a symbol,
2925 nor can we indirect via the constant pool. */
2926 #define LEGITIMATE_PIC_OPERAND_P(X) \
2927 ((! nonpic_symbol_mentioned_p (X) \
2928 && (GET_CODE (X) != SYMBOL_REF \
2929 || ! CONSTANT_POOL_ADDRESS_P (X) \
2930 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2931 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2932
2933 #define SYMBOLIC_CONST_P(X) \
2934 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2935 && nonpic_symbol_mentioned_p (X))
2936 \f
2937 /* Compute extra cost of moving data between one register class
2938 and another. */
2939
2940 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2941 uses this information. Hence, the general register <-> floating point
2942 register information here is not used for SFmode. */
2943
2944 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2945 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2946 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2947
2948 #define REGCLASS_HAS_FP_REG(CLASS) \
2949 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2950 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2951
2952 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2953 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2954
2955 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2956 would be so that people with slow memory systems could generate
2957 different code that does fewer memory accesses. */
2958
2959 /* A C expression for the cost of a branch instruction. A value of 1
2960 is the default; other values are interpreted relative to that.
2961 The SH1 does not have delay slots, hence we get a pipeline stall
2962 at every branch. The SH4 is superscalar, so the single delay slot
2963 is not sufficient to keep both pipelines filled. */
2964 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2965 \f
2966 /* Assembler output control. */
2967
2968 /* A C string constant describing how to begin a comment in the target
2969 assembler language. The compiler assumes that the comment will end at
2970 the end of the line. */
2971 #define ASM_COMMENT_START "!"
2972
2973 #define ASM_APP_ON ""
2974 #define ASM_APP_OFF ""
2975 #define FILE_ASM_OP "\t.file\n"
2976 #define SET_ASM_OP "\t.set\t"
2977
2978 /* How to change between sections. */
2979
2980 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2981 #define DATA_SECTION_ASM_OP "\t.data"
2982
2983 #if defined CRT_BEGIN || defined CRT_END
2984 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2985 # undef TEXT_SECTION_ASM_OP
2986 # if __SHMEDIA__ == 1 && __SH5__ == 32
2987 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2988 # else
2989 # define TEXT_SECTION_ASM_OP "\t.text"
2990 # endif
2991 #endif
2992
2993
2994 /* If defined, a C expression whose value is a string containing the
2995 assembler operation to identify the following data as
2996 uninitialized global data. If not defined, and neither
2997 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2998 uninitialized global data will be output in the data section if
2999 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3000 used. */
3001 #ifndef BSS_SECTION_ASM_OP
3002 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3003 #endif
3004
3005 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3006 separate, explicit argument. If you define this macro, it is used
3007 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3008 handling the required alignment of the variable. The alignment is
3009 specified as the number of bits.
3010
3011 Try to use function `asm_output_aligned_bss' defined in file
3012 `varasm.c' when defining this macro. */
3013 #ifndef ASM_OUTPUT_ALIGNED_BSS
3014 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3015 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3016 #endif
3017
3018 /* Define this so that jump tables go in same section as the current function,
3019 which could be text or it could be a user defined section. */
3020 #define JUMP_TABLES_IN_TEXT_SECTION 1
3021
3022 #undef DO_GLOBAL_CTORS_BODY
3023 #define DO_GLOBAL_CTORS_BODY \
3024 { \
3025 typedef (*pfunc)(); \
3026 extern pfunc __ctors[]; \
3027 extern pfunc __ctors_end[]; \
3028 pfunc *p; \
3029 for (p = __ctors_end; p > __ctors; ) \
3030 { \
3031 (*--p)(); \
3032 } \
3033 }
3034
3035 #undef DO_GLOBAL_DTORS_BODY
3036 #define DO_GLOBAL_DTORS_BODY \
3037 { \
3038 typedef (*pfunc)(); \
3039 extern pfunc __dtors[]; \
3040 extern pfunc __dtors_end[]; \
3041 pfunc *p; \
3042 for (p = __dtors; p < __dtors_end; p++) \
3043 { \
3044 (*p)(); \
3045 } \
3046 }
3047
3048 #define ASM_OUTPUT_REG_PUSH(file, v) \
3049 { \
3050 if (TARGET_SHMEDIA) \
3051 { \
3052 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
3053 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
3054 } \
3055 else \
3056 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
3057 }
3058
3059 #define ASM_OUTPUT_REG_POP(file, v) \
3060 { \
3061 if (TARGET_SHMEDIA) \
3062 { \
3063 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
3064 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
3065 } \
3066 else \
3067 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
3068 }
3069
3070 /* DBX register number for a given compiler register number. */
3071 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3072 to match gdb. */
3073 /* svr4.h undefines this macro, yet we really want to use the same numbers
3074 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3075 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3076 register exists, so we should return -1 for invalid register numbers. */
3077 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3078
3079 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3080 used to use the encodings 245..260, but that doesn't make sense:
3081 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3082 the FP registers stay the same when switching between compact and media
3083 mode. Hence, we also need to use the same dwarf frame columns.
3084 Likewise, we need to support unwind information for SHmedia registers
3085 even in compact code. */
3086 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3087 (IN_RANGE ((REGNO), \
3088 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3089 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3090 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3091 : ((int) (REGNO) >= FIRST_FP_REG \
3092 && ((int) (REGNO) \
3093 <= (FIRST_FP_REG + \
3094 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3095 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3096 + (TARGET_SH5 ? 77 : 25)) \
3097 : XD_REGISTER_P (REGNO) \
3098 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3099 : TARGET_REGISTER_P (REGNO) \
3100 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3101 : (REGNO) == PR_REG \
3102 ? (TARGET_SH5 ? 18 : 17) \
3103 : (REGNO) == PR_MEDIA_REG \
3104 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3105 : (REGNO) == T_REG \
3106 ? (TARGET_SH5 ? 242 : 18) \
3107 : (REGNO) == GBR_REG \
3108 ? (TARGET_SH5 ? 238 : 19) \
3109 : (REGNO) == MACH_REG \
3110 ? (TARGET_SH5 ? 239 : 20) \
3111 : (REGNO) == MACL_REG \
3112 ? (TARGET_SH5 ? 240 : 21) \
3113 : (REGNO) == FPUL_REG \
3114 ? (TARGET_SH5 ? 244 : 23) \
3115 : (unsigned) -1)
3116
3117 /* This is how to output a reference to a symbol_ref. On SH5,
3118 references to non-code symbols must be preceded by `datalabel'. */
3119 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3120 do \
3121 { \
3122 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3123 fputs ("datalabel ", (FILE)); \
3124 assemble_name ((FILE), XSTR ((SYM), 0)); \
3125 } \
3126 while (0)
3127
3128 /* This is how to output an assembler line
3129 that says to advance the location counter
3130 to a multiple of 2**LOG bytes. */
3131
3132 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3133 if ((LOG) != 0) \
3134 fprintf ((FILE), "\t.align %d\n", (LOG))
3135
3136 /* Globalizing directive for a label. */
3137 #define GLOBAL_ASM_OP "\t.global\t"
3138
3139 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3140
3141 /* Output a relative address table. */
3142
3143 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3144 switch (GET_MODE (BODY)) \
3145 { \
3146 case SImode: \
3147 if (TARGET_SH5) \
3148 { \
3149 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3150 (VALUE), (REL)); \
3151 break; \
3152 } \
3153 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3154 break; \
3155 case HImode: \
3156 if (TARGET_SH5) \
3157 { \
3158 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3159 (VALUE), (REL)); \
3160 break; \
3161 } \
3162 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3163 break; \
3164 case QImode: \
3165 if (TARGET_SH5) \
3166 { \
3167 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3168 (VALUE), (REL)); \
3169 break; \
3170 } \
3171 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3172 break; \
3173 default: \
3174 break; \
3175 }
3176
3177 /* Output an absolute table element. */
3178
3179 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3180 if (! optimize || TARGET_BIGTABLE) \
3181 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3182 else \
3183 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3184
3185 \f
3186 /* A C statement to be executed just prior to the output of
3187 assembler code for INSN, to modify the extracted operands so
3188 they will be output differently.
3189
3190 Here the argument OPVEC is the vector containing the operands
3191 extracted from INSN, and NOPERANDS is the number of elements of
3192 the vector which contain meaningful data for this insn.
3193 The contents of this vector are what will be used to convert the insn
3194 template into assembler code, so you can change the assembler output
3195 by changing the contents of the vector. */
3196
3197 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3198 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3199
3200 /* Print operand X (an rtx) in assembler syntax to file FILE.
3201 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3202 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3203
3204 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3205
3206 /* Print a memory address as an operand to reference that memory location. */
3207
3208 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3209
3210 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3211 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3212 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3213
3214 /* Recognize machine-specific patterns that may appear within
3215 constants. Used for PIC-specific UNSPECs. */
3216 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3217 do \
3218 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3219 { \
3220 switch (XINT ((X), 1)) \
3221 { \
3222 case UNSPEC_DATALABEL: \
3223 fputs ("datalabel ", (STREAM)); \
3224 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3225 break; \
3226 case UNSPEC_PIC: \
3227 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3228 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3229 break; \
3230 case UNSPEC_GOT: \
3231 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3232 fputs ("@GOT", (STREAM)); \
3233 break; \
3234 case UNSPEC_GOTOFF: \
3235 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3236 fputs ("@GOTOFF", (STREAM)); \
3237 break; \
3238 case UNSPEC_PLT: \
3239 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3240 fputs ("@PLT", (STREAM)); \
3241 break; \
3242 case UNSPEC_GOTPLT: \
3243 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3244 fputs ("@GOTPLT", (STREAM)); \
3245 break; \
3246 case UNSPEC_DTPOFF: \
3247 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3248 fputs ("@DTPOFF", (STREAM)); \
3249 break; \
3250 case UNSPEC_GOTTPOFF: \
3251 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3252 fputs ("@GOTTPOFF", (STREAM)); \
3253 break; \
3254 case UNSPEC_TPOFF: \
3255 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3256 fputs ("@TPOFF", (STREAM)); \
3257 break; \
3258 case UNSPEC_CALLER: \
3259 { \
3260 char name[32]; \
3261 /* LPCS stands for Label for PIC Call Site. */ \
3262 ASM_GENERATE_INTERNAL_LABEL \
3263 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3264 assemble_name ((STREAM), name); \
3265 } \
3266 break; \
3267 default: \
3268 goto FAIL; \
3269 } \
3270 break; \
3271 } \
3272 else \
3273 goto FAIL; \
3274 while (0)
3275
3276 \f
3277 extern struct rtx_def *sh_compare_op0;
3278 extern struct rtx_def *sh_compare_op1;
3279
3280 /* Which processor to schedule for. The elements of the enumeration must
3281 match exactly the cpu attribute in the sh.md file. */
3282
3283 enum processor_type {
3284 PROCESSOR_SH1,
3285 PROCESSOR_SH2,
3286 PROCESSOR_SH2E,
3287 PROCESSOR_SH2A,
3288 PROCESSOR_SH3,
3289 PROCESSOR_SH3E,
3290 PROCESSOR_SH4,
3291 PROCESSOR_SH4A,
3292 PROCESSOR_SH5
3293 };
3294
3295 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3296 extern enum processor_type sh_cpu;
3297
3298 extern int optimize; /* needed for gen_casesi. */
3299
3300 enum mdep_reorg_phase_e
3301 {
3302 SH_BEFORE_MDEP_REORG,
3303 SH_INSERT_USES_LABELS,
3304 SH_SHORTEN_BRANCHES0,
3305 SH_FIXUP_PCLOAD,
3306 SH_SHORTEN_BRANCHES1,
3307 SH_AFTER_MDEP_REORG
3308 };
3309
3310 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3311
3312 /* Handle Renesas compiler's pragmas. */
3313 #define REGISTER_TARGET_PRAGMAS() do { \
3314 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3315 c_register_pragma (0, "trapa", sh_pr_trapa); \
3316 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3317 } while (0)
3318
3319 extern tree sh_deferred_function_attributes;
3320 extern tree *sh_deferred_function_attributes_tail;
3321
3322 /* Set when processing a function with interrupt attribute. */
3323
3324 extern int current_function_interrupt;
3325
3326 \f
3327 /* Instructions with unfilled delay slots take up an
3328 extra two bytes for the nop in the delay slot.
3329 sh-dsp parallel processing insns are four bytes long. */
3330
3331 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3332 (LENGTH) += sh_insn_length_adjustment (X);
3333 \f
3334 /* Define this macro if it is advisable to hold scalars in registers
3335 in a wider mode than that declared by the program. In such cases,
3336 the value is constrained to be within the bounds of the declared
3337 type, but kept valid in the wider mode. The signedness of the
3338 extension may differ from that of the type.
3339
3340 Leaving the unsignedp unchanged gives better code than always setting it
3341 to 0. This is despite the fact that we have only signed char and short
3342 load instructions. */
3343 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3344 if (GET_MODE_CLASS (MODE) == MODE_INT \
3345 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3346 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3347 (MODE) = (TARGET_SH1 ? SImode \
3348 : TARGET_SHMEDIA32 ? SImode : DImode);
3349
3350 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3351
3352 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3353
3354 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3355 and popping arguments. However, we do have push/pop instructions, and
3356 rather limited offsets (4 bits) in load/store instructions, so it isn't
3357 clear if this would give better code. If implemented, should check for
3358 compatibility problems. */
3359
3360 #define SH_DYNAMIC_SHIFT_COST \
3361 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3362
3363
3364 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3365
3366 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3367
3368 #define ACTUAL_NORMAL_MODE(ENTITY) \
3369 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3370
3371 #define NORMAL_MODE(ENTITY) \
3372 (sh_cfun_interrupt_handler_p () \
3373 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3374 : ACTUAL_NORMAL_MODE (ENTITY))
3375
3376 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3377
3378 #define MODE_EXIT(ENTITY) \
3379 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3380
3381 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3382 && (REGNO) == FPSCR_REG)
3383
3384 #define MODE_NEEDED(ENTITY, INSN) \
3385 (recog_memoized (INSN) >= 0 \
3386 ? get_attr_fp_mode (INSN) \
3387 : FP_MODE_NONE)
3388
3389 #define MODE_AFTER(MODE, INSN) \
3390 (TARGET_HITACHI \
3391 && recog_memoized (INSN) >= 0 \
3392 && get_attr_fp_set (INSN) != FP_SET_NONE \
3393 ? (int) get_attr_fp_set (INSN) \
3394 : (MODE))
3395
3396 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3397 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3398
3399 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3400 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3401
3402 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3403 sh_can_redirect_branch ((INSN), (SEQ))
3404
3405 #define DWARF_FRAME_RETURN_COLUMN \
3406 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3407
3408 #define EH_RETURN_DATA_REGNO(N) \
3409 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3410
3411 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3412 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3413
3414 /* We have to distinguish between code and data, so that we apply
3415 datalabel where and only where appropriate. Use sdataN for data. */
3416 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3417 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3418 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3419 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3420
3421 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3422 indirect are handled automatically. */
3423 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3424 do { \
3425 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3426 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3427 { \
3428 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3429 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3430 if (0) goto DONE; \
3431 } \
3432 } while (0)
3433
3434 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3435 /* SH constant pool breaks the devices in crtstuff.c to control section
3436 in where code resides. We have to write it as asm code. */
3437 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3438 asm (SECTION_OP "\n\
3439 mov.l 1f,r1\n\
3440 mova 2f,r0\n\
3441 braf r1\n\
3442 lds r0,pr\n\
3443 0: .p2align 2\n\
3444 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3445 2:\n" TEXT_SECTION_ASM_OP);
3446 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3447
3448 #define SIMULTANEOUS_PREFETCHES 2
3449
3450 /* FIXME: middle-end support for highpart optimizations is missing. */
3451 #define high_life_started reload_in_progress
3452
3453 #endif /* ! GCC_SH_H */
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