gcc/config/arm/netbsd-elf.h

   1 /* Definitions of target machine for GNU compiler, NetBSD/arm ELF version.
   2    Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
   3    Contributed by Wasabi Systems, Inc.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 2, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING.  If not, write to
  19    the Free Software Foundation, 59 Temple Place - Suite 330,
  20    Boston, MA 02111-1307, USA.  */
  21
  22 /* Run-time Target Specification.  */
  23 #undef TARGET_VERSION
  24 #define TARGET_VERSION fputs (" (NetBSD/arm ELF)", stderr);
  25
  26 /* arm.h defaults to ARM6 CPU.  */
  27
  28 /* This defaults us to little-endian.  */
  29 #ifndef TARGET_ENDIAN_DEFAULT
  30 #define TARGET_ENDIAN_DEFAULT 0
  31 #endif
  32
  33 #undef MULTILIB_DEFAULTS
  34
  35 /* Default it to use ATPCS with soft-VFP.  */
  36 #undef TARGET_DEFAULT
  37 #define TARGET_DEFAULT                  \
  38   (ARM_FLAG_APCS_FRAME                  \
  39    | TARGET_ENDIAN_DEFAULT)
  40
  41 #undef ARM_DEFAULT_ABI
  42 #define ARM_DEFAULT_ABI ARM_ABI_ATPCS
  43
  44 #define TARGET_OS_CPP_BUILTINS()        \
  45   do                                    \
  46     {                                   \
  47       NETBSD_OS_CPP_BUILTINS_ELF();     \
  48     }                                   \
  49   while (0)
  50
  51 #undef SUBTARGET_CPP_SPEC
  52 #define SUBTARGET_CPP_SPEC NETBSD_CPP_SPEC
  53
  54 #undef SUBTARGET_EXTRA_ASM_SPEC
  55 #define SUBTARGET_EXTRA_ASM_SPEC        \
  56   "-matpcs %{fpic|fpie:-k} %{fPIC|fPIE:-k}"
  57
  58 /* Default to full VFP if -mhard-float is specified.  */
  59 #undef SUBTARGET_ASM_FLOAT_SPEC
  60 #define SUBTARGET_ASM_FLOAT_SPEC        \
  61   "%{mhard-float:{!mfpu=*:-mfpu=vfp}}   \
  62    %{mfloat-abi=hard:{!mfpu=*:-mfpu=vfp}}"
  63
  64 #undef SUBTARGET_EXTRA_SPECS
  65 #define SUBTARGET_EXTRA_SPECS                           \
  66   { "subtarget_extra_asm_spec", SUBTARGET_EXTRA_ASM_SPEC }, \
  67   { "subtarget_asm_float_spec", SUBTARGET_ASM_FLOAT_SPEC }, \
  68   { "netbsd_link_spec",         NETBSD_LINK_SPEC_ELF }, \
  69   { "netbsd_entry_point",       NETBSD_ENTRY_POINT },
  70
  71 #define NETBSD_ENTRY_POINT "__start"
  72
  73 #undef LINK_SPEC
  74 #define LINK_SPEC \
  75   "-X %{mbig-endian:-EB} %{mlittle-endian:-EL} \
  76    %(netbsd_link_spec)"
  77
  78 /* Make GCC agree with <machine/ansi.h>.  */
  79
  80 #undef SIZE_TYPE
  81 #define SIZE_TYPE "long unsigned int"
  82
  83 #undef PTRDIFF_TYPE
  84 #define PTRDIFF_TYPE "long int"
  85
  86 /* We don't have any limit on the length as out debugger is GDB.  */
  87 #undef DBX_CONTIN_LENGTH
  88
  89 /* NetBSD does its profiling differently to the Acorn compiler. We
  90    don't need a word following the mcount call; and to skip it
  91    requires either an assembly stub or use of fomit-frame-pointer when
  92    compiling the profiling functions.  Since we break Acorn CC
  93    compatibility below a little more won't hurt.  */
  94
  95 #undef ARM_FUNCTION_PROFILER
  96 #define ARM_FUNCTION_PROFILER(STREAM,LABELNO)           \
  97 {                                                       \
  98   asm_fprintf (STREAM, "\tmov\t%Rip, %Rlr\n");          \
  99   asm_fprintf (STREAM, "\tbl\t__mcount%s\n",            \
 100                (TARGET_ARM && NEED_PLT_RELOC)           \
 101                ? "(PLT)" : "");                         \
 102 }
 103
 104 /* VERY BIG NOTE: Change of structure alignment for NetBSD/arm.
 105    There are consequences you should be aware of...
 106
 107    Normally GCC/arm uses a structure alignment of 32 for compatibility
 108    with armcc.  This means that structures are padded to a word
 109    boundary.  However this causes problems with bugged NetBSD kernel
 110    code (possibly userland code as well - I have not checked every
 111    binary).  The nature of this bugged code is to rely on sizeof()
 112    returning the correct size of various structures rounded to the
 113    nearest byte (SCSI and ether code are two examples, the vm system
 114    is another).  This code breaks when the structure alignment is 32
 115    as sizeof() will report a word=rounded size.  By changing the
 116    structure alignment to 8. GCC will conform to what is expected by
 117    NetBSD.
 118
 119    This has several side effects that should be considered.
 120    1. Structures will only be aligned to the size of the largest member.
 121       i.e. structures containing only bytes will be byte aligned.
 122            structures containing shorts will be half word aligned.
 123            structures containing ints will be word aligned.
 124
 125       This means structures should be padded to a word boundary if
 126       alignment of 32 is required for byte structures etc.
 127
 128    2. A potential performance penalty may exist if strings are no longer
 129       word aligned.  GCC will not be able to use word load/stores to copy
 130       short strings.
 131
 132    This modification is not encouraged but with the present state of the
 133    NetBSD source tree it is currently the only solution that meets the
 134    requirements.  */
 135
 136 #undef DEFAULT_STRUCTURE_SIZE_BOUNDARY
 137 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 8
 138
 139 /* Emit code to set up a trampoline and synchronize the caches.  */
 140 #undef INITIALIZE_TRAMPOLINE
 141 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)                       \
 142 do                                                                      \
 143   {                                                                     \
 144     emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)),   \
 145                     (CXT));                                             \
 146     emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)),  \
 147                     (FNADDR));                                          \
 148     emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__clear_cache"),     \
 149                        0, VOIDmode, 2, TRAMP, Pmode,                    \
 150                        plus_constant (TRAMP, TRAMPOLINE_SIZE), Pmode);  \
 151   }                                                                     \
 152 while (0)
 153
 154 /* Clear the instruction cache from `BEG' to `END'.  This makes a
 155    call to the ARM_SYNC_ICACHE architecture specific syscall.  */
 156 #define CLEAR_INSN_CACHE(BEG, END)                                      \
 157 do                                                                      \
 158   {                                                                     \
 159     extern int sysarch(int number, void *args);                         \
 160     struct                                                              \
 161       {                                                                 \
 162         unsigned int addr;                                              \
 163         int          len;                                               \
 164       } s;                                                              \
 165     s.addr = (unsigned int)(BEG);                                       \
 166     s.len = (END) - (BEG);                                              \
 167     (void) sysarch (0, &s);                                             \
 168   }                                                                     \
 169 while (0)
 170
 171 #undef FPUTYPE_DEFAULT
 172 #define FPUTYPE_DEFAULT FPUTYPE_VFP
 173