| blob | c37b10c207e3da0ff3638e6b22cbb9a0a378f3f4 |
1 /* Definitions of target machine for GNU compiler for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
27 #define TARGET_VERSION \
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because hconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
44 break; \
45 case PROCESSOR_SH2: \
47 break; \
48 case PROCESSOR_SH3: \
51 if (TARGET_HARD_SH4) \
53 break; \
54 case PROCESSOR_SH3E: \
56 break; \
57 case PROCESSOR_SH4: \
59 break; \
60 case PROCESSOR_SH5: \
61 { \
66 if (! TARGET_FPU_DOUBLE) \
68 } \
69 } \
70 if (TARGET_HITACHI) \
72 builtin_define (TARGET_LITTLE_ENDIAN \
74 if (flag_pic) \
75 { \
78 } \
79 TARGET_OBJFMT_CPP_BUILTINS (); \
80 } while (0)
82 /* We can not debug without a frame pointer. */
83 /* #define CAN_DEBUG_WITHOUT_FP */
85 #define CONDITIONAL_REGISTER_USAGE do \
86 { \
87 int regno; \
88 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
89 if (! VALID_REGISTER_P (regno)) \
90 fixed_regs[regno] = call_used_regs[regno] = 1; \
92 if (TARGET_SH5) \
93 call_used_regs[FIRST_GENERAL_REG + 8] \
94 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
95 if (TARGET_SHMEDIA) \
96 { \
97 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
98 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
99 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
100 } \
101 if (flag_pic) \
102 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
104 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
105 { \
106 call_used_regs[MACH_REG] = 0; \
107 call_used_regs[MACL_REG] = 0; \
108 } \
109 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
110 regno <= LAST_FP_REG; regno += 2) \
111 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
112 if (TARGET_SHMEDIA) \
113 { \
114 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
115 if (! fixed_regs[regno] && call_used_regs[regno]) \
116 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
117 } \
118 else \
119 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
120 if (! fixed_regs[regno] && call_used_regs[regno]) \
121 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
122 } while (0)
123 \f
124 /* ??? Need to write documentation for all SH options and add it to the
125 invoke.texi file. */
127 /* Run-time compilation parameters selecting different hardware subsets. */
130 #define ISIZE_BIT (1<<1)
131 #define DALIGN_BIT (1<<6)
132 #define SH1_BIT (1<<8)
133 #define SH2_BIT (1<<9)
134 #define SH3_BIT (1<<10)
135 #define SH3E_BIT (1<<11)
136 #define HARD_SH4_BIT (1<<5)
137 #define FPU_SINGLE_BIT (1<<7)
138 #define SH4_BIT (1<<12)
139 #define FMOVD_BIT (1<<4)
140 #define SH5_BIT (1<<0)
141 #define SPACE_BIT (1<<13)
142 #define BIGTABLE_BIT (1<<14)
143 #define RELAX_BIT (1<<15)
144 #define USERMODE_BIT (1<<16)
145 #define HITACHI_BIT (1<<22)
146 #define NOMACSAVE_BIT (1<<23)
147 #define PREFERGOT_BIT (1<<24)
148 #define PADSTRUCT_BIT (1<<28)
149 #define LITTLE_ENDIAN_BIT (1<<29)
150 #define IEEE_BIT (1<<30)
152 /* Nonzero if we should dump out instruction size info. */
153 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
155 /* Nonzero to align doubles on 64 bit boundaries. */
156 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
158 /* Nonzero if we should generate code using type 1 insns. */
159 #define TARGET_SH1 (target_flags & SH1_BIT)
161 /* Nonzero if we should generate code using type 2 insns. */
162 #define TARGET_SH2 (target_flags & SH2_BIT)
164 /* Nonzero if we should generate code using type 3 insns. */
165 #define TARGET_SH3 (target_flags & SH3_BIT)
167 /* Nonzero if we should generate code using type 3E insns. */
168 #define TARGET_SH3E ((target_flags & SH3E_BIT) && (target_flags & SH1_BIT))
170 /* Nonzero if the cache line size is 32. */
171 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
173 /* Nonzero if we schedule for a superscalar implementation. */
174 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
176 /* Nonzero if the target has separate instruction and data caches. */
177 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
179 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
180 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
182 /* Nonzero if the default precision of th FPU is single */
183 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
185 /* Nonzero if a double-precision FPU is available. */
186 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
188 /* Nonzero if an FPU is available. */
189 #define TARGET_FPU_ANY (TARGET_SH3E || TARGET_FPU_DOUBLE)
191 /* Nonzero if we should generate code using type 4 insns. */
192 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
194 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
195 #define TARGET_SH5 (target_flags & SH5_BIT)
197 /* Nonzero if we should generate code using the SHcompact instruction
198 set and 32-bit ABI. */
199 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
201 /* Nonzero if we should generate code using the SHmedia instruction
202 set and ABI. */
203 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
205 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
206 ABI. */
207 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
208 && (target_flags & SH3E_BIT))
210 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
211 ABI. */
212 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
213 && ! (target_flags & SH3E_BIT))
215 /* Nonzero if we should generate code using SHmedia FPU instructions. */
216 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
217 /* Nonzero if we should generate fmovd. */
218 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
220 /* Nonzero if we respect NANs. */
221 #define TARGET_IEEE (target_flags & IEEE_BIT)
223 /* Nonzero if we should generate smaller code rather than faster code. */
224 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
226 /* Nonzero to use long jump tables. */
227 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
229 /* Nonzero to generate pseudo-ops needed by the assembler and linker
230 to do function call relaxing. */
231 #define TARGET_RELAX (target_flags & RELAX_BIT)
233 /* Nonzero if using Hitachi's calling convention. */
234 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
236 /* Nonzero if not saving macl/mach when using -mhitachi */
237 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
239 /* Nonzero if padding structures to a multiple of 4 bytes. This is
240 incompatible with Hitachi's compiler, and gives unusual structure layouts
241 which confuse programmers.
242 ??? This option is not useful, but is retained in case there are people
243 who are still relying on it. It may be deleted in the future. */
244 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
246 /* Nonzero if generating code for a little endian SH. */
247 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
249 /* Nonzero if we should do everything in userland. */
250 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
252 /* Nonzero if we should prefer @GOT calls when generating PIC. */
253 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
255 #define SELECT_SH1 (SH1_BIT)
256 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
257 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
258 #define SELECT_SH3E (SH3E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
259 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
260 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
261 #define SELECT_SH4 (SH4_BIT|SH3E_BIT|HARD_SH4_BIT | SELECT_SH3)
262 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
263 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
264 #define SELECT_SH5_64_NOFPU (SH5_BIT)
265 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH3E_BIT)
266 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH3E_BIT)
267 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
268 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
270 /* Reset all target-selection flags. */
271 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
272 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
274 #define TARGET_SWITCHES \
318 SUBTARGET_SWITCHES \
320 }
322 /* This are meant to be redefined in the host dependent files */
323 #define SUBTARGET_SWITCHES
325 /* This defaults us to big-endian. */
326 #ifndef TARGET_ENDIAN_DEFAULT
327 #define TARGET_ENDIAN_DEFAULT 0
328 #endif
330 #ifndef TARGET_CPU_DEFAULT
331 #define TARGET_CPU_DEFAULT SELECT_SH1
332 #endif
334 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
338 #ifndef SUBTARGET_CPP_SPEC
340 #endif
342 #ifndef SUBTARGET_EXTRA_SPECS
343 #define SUBTARGET_EXTRA_SPECS
344 #endif
346 #define EXTRA_SPECS \
353 SUBTARGET_EXTRA_SPECS
357 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
358 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
360 #else
362 #endif
363 #endif
367 #if TARGET_CPU_DEFAULT & SH5_BIT
368 #if TARGET_CPU_DEFAULT & SH3E_BIT
370 #else
373 #else
380 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
381 so that we can undo the damage without code replication. */
382 #define LINK_SPEC SH_LINK_SPEC
385 -m %(link_emul_prefix)\
386 %{m5-compact*|m5-32media*:32}\
387 %{m5-64media*:64}\
388 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
389 %(subtarget_link_emul_suffix) \
390 %{mrelax:-relax} %(subtarget_link_spec)"
392 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
393 do { \
394 if (LEVEL) \
395 flag_omit_frame_pointer = -1; \
396 if (SIZE) \
397 target_flags |= SPACE_BIT; \
398 } while (0)
400 #define ASSEMBLER_DIALECT assembler_dialect
404 #define OVERRIDE_OPTIONS \
405 do { \
406 int regno; \
407 \
408 sh_cpu = CPU_SH1; \
409 assembler_dialect = 0; \
410 if (TARGET_SH2) \
411 sh_cpu = CPU_SH2; \
412 if (TARGET_SH3) \
413 sh_cpu = CPU_SH3; \
414 if (TARGET_SH3E) \
415 sh_cpu = CPU_SH3E; \
416 if (TARGET_SH4) \
417 { \
418 assembler_dialect = 1; \
419 sh_cpu = CPU_SH4; \
420 } \
421 if (TARGET_SH5) \
422 { \
423 sh_cpu = CPU_SH5; \
424 target_flags |= DALIGN_BIT; \
425 if (TARGET_FPU_ANY) \
426 target_flags |= FMOVD_BIT; \
427 if (TARGET_SHMEDIA) \
428 { \
430 flag_delayed_branch = 0; \
432 target_flags &= ~RELAX_BIT; \
433 } \
434 if (profile_flag || profile_arc_flag) \
435 { \
437 profile_flag = profile_arc_flag = 0; \
438 } \
439 } \
440 else \
441 { \
443 targetm.asm_out.aligned_op.di = NULL; \
444 targetm.asm_out.unaligned_op.di = NULL; \
445 } \
446 \
447 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
448 if (! VALID_REGISTER_P (regno)) \
450 \
451 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
452 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
454 \
455 if (flag_omit_frame_pointer < 0) \
456 { \
457 /* The debugging information is sufficient, \
459 if (0) \
460 flag_omit_frame_pointer \
461 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
462 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
463 else \
464 flag_omit_frame_pointer = 0; \
465 } \
466 \
467 if (flag_pic && ! TARGET_PREFERGOT) \
468 flag_no_function_cse = 1; \
469 \
470 /* Never run scheduling before reload, since that can \
471 break global alloc, and generates slower code anyway due \
473 flag_schedule_insns = 0; \
474 } while (0)
475 \f
476 /* Target machine storage layout. */
478 /* Define this if most significant bit is lowest numbered
479 in instructions that operate on numbered bit-fields. */
481 #define BITS_BIG_ENDIAN 0
483 /* Define this if most significant byte of a word is the lowest numbered. */
484 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
486 /* Define this if most significant word of a multiword number is the lowest
487 numbered. */
488 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
490 /* Define this to set the endianness to use in libgcc2.c, which can
491 not depend on target_flags. */
492 #if defined(__LITTLE_ENDIAN__)
493 #define LIBGCC2_WORDS_BIG_ENDIAN 0
494 #else
495 #define LIBGCC2_WORDS_BIG_ENDIAN 1
496 #endif
498 #define MAX_BITS_PER_WORD 64
500 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
502 /* Width in bits of an `int'. We want just 32-bits, even if words are
503 longer. */
504 #define INT_TYPE_SIZE 32
506 /* Width in bits of a `long'. */
507 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
509 /* Width in bits of a `long long'. */
510 #define LONG_LONG_TYPE_SIZE 64
512 /* Width in bits of a `long double'. */
513 #define LONG_DOUBLE_TYPE_SIZE 64
515 /* Width of a word, in units (bytes). */
516 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
517 #define MIN_UNITS_PER_WORD 4
519 /* Width in bits of a pointer.
520 See also the macro `Pmode' defined below. */
521 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
523 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
524 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
526 /* Boundary (in *bits*) on which stack pointer should be aligned. */
527 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
529 /* The log (base 2) of the cache line size, in bytes. Processors prior to
530 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
531 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
532 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
534 /* Allocation boundary (in *bits*) for the code of a function.
535 32 bit alignment is faster, because instructions are always fetched as a
536 pair from a longword boundary. */
537 #define FUNCTION_BOUNDARY \
538 (TARGET_SMALLCODE ? 16 << TARGET_SHMEDIA : (1 << CACHE_LOG) * 8)
540 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
541 the vbit must go into the delta field of
542 pointers-to-member-functions. */
543 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
544 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
546 /* Alignment of field after `int : 0' in a structure. */
547 #define EMPTY_FIELD_BOUNDARY 32
549 /* No data type wants to be aligned rounder than this. */
550 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
552 /* The best alignment to use in cases where we have a choice. */
553 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
555 /* Make strings word-aligned so strcpy from constants will be faster. */
556 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
557 ((TREE_CODE (EXP) == STRING_CST \
558 && (ALIGN) < FASTEST_ALIGNMENT) \
559 ? FASTEST_ALIGNMENT : (ALIGN))
561 /* Make arrays of chars word-aligned for the same reasons. */
562 #define DATA_ALIGNMENT(TYPE, ALIGN) \
563 (TREE_CODE (TYPE) == ARRAY_TYPE \
564 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
565 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
567 /* Number of bits which any structure or union's size must be a
568 multiple of. Each structure or union's size is rounded up to a
569 multiple of this. */
570 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
572 /* Set this nonzero if move instructions will actually fail to work
573 when given unaligned data. */
574 #define STRICT_ALIGNMENT 1
576 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
577 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
578 barrier_align (LABEL_AFTER_BARRIER)
580 #define LOOP_ALIGN(A_LABEL) \
581 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
582 ? 0 : sh_loop_align (A_LABEL))
584 #define LABEL_ALIGN(A_LABEL) \
585 ( \
586 (PREV_INSN (A_LABEL) \
587 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
588 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
589 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
591 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
592 : 0)
594 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
595 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
597 /* The base two logarithm of the known minimum alignment of an insn length. */
598 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
599 (GET_CODE (A_INSN) == INSN \
600 ? 1 << TARGET_SHMEDIA \
601 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
602 ? 1 << TARGET_SHMEDIA \
603 : CACHE_LOG)
604 \f
605 /* Standard register usage. */
607 /* Register allocation for the Hitachi calling convention:
609 r0 arg return
610 r1..r3 scratch
611 r4..r7 args in
612 r8..r13 call saved
613 r14 frame pointer/call saved
614 r15 stack pointer
615 ap arg pointer (doesn't really exist, always eliminated)
616 pr subroutine return address
617 t t bit
618 mach multiply/accumulate result, high part
619 macl multiply/accumulate result, low part.
620 fpul fp/int communication register
621 rap return address pointer register
622 fr0 fp arg return
623 fr1..fr3 scratch floating point registers
624 fr4..fr11 fp args in
625 fr12..fr15 call saved floating point registers */
627 #define MAX_REGISTER_NAME_LENGTH 5
630 #define SH_REGISTER_NAMES_INITIALIZER \
631 { \
652 }
654 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
656 #define REGNAMES_ARR_INDEX_1(index) \
657 (sh_register_names[index])
658 #define REGNAMES_ARR_INDEX_2(index) \
659 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
660 #define REGNAMES_ARR_INDEX_4(index) \
661 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
662 #define REGNAMES_ARR_INDEX_8(index) \
663 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
664 #define REGNAMES_ARR_INDEX_16(index) \
665 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
666 #define REGNAMES_ARR_INDEX_32(index) \
667 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
668 #define REGNAMES_ARR_INDEX_64(index) \
669 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
671 #define REGISTER_NAMES \
672 { \
673 REGNAMES_ARR_INDEX_64 (0), \
674 REGNAMES_ARR_INDEX_64 (64), \
675 REGNAMES_ARR_INDEX_8 (128), \
676 REGNAMES_ARR_INDEX_8 (136), \
677 REGNAMES_ARR_INDEX_8 (144), \
678 REGNAMES_ARR_INDEX_1 (152) \
679 }
681 #define ADDREGNAMES_SIZE 32
682 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
686 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
687 { \
692 }
694 #define ADDREGNAMES_REGNO(index) \
695 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
696 : (-1))
698 #define ADDREGNAMES_ARR_INDEX_1(index) \
699 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
700 #define ADDREGNAMES_ARR_INDEX_2(index) \
701 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
702 #define ADDREGNAMES_ARR_INDEX_4(index) \
703 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
704 #define ADDREGNAMES_ARR_INDEX_8(index) \
705 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
706 #define ADDREGNAMES_ARR_INDEX_16(index) \
707 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
708 #define ADDREGNAMES_ARR_INDEX_32(index) \
709 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
711 #define ADDITIONAL_REGISTER_NAMES \
712 { \
713 ADDREGNAMES_ARR_INDEX_32 (0) \
714 }
716 /* Number of actual hardware registers.
717 The hardware registers are assigned numbers for the compiler
718 from 0 to just below FIRST_PSEUDO_REGISTER.
719 All registers that the compiler knows about must be given numbers,
720 even those that are not normally considered general registers. */
722 /* There are many other relevant definitions in sh.md's md_constants. */
724 #define FIRST_GENERAL_REG R0_REG
725 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
726 #define FIRST_FP_REG DR0_REG
727 #define LAST_FP_REG (FIRST_FP_REG + \
728 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH3E ? 15 : -1))
729 #define FIRST_XD_REG XD0_REG
730 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
731 #define FIRST_TARGET_REG TR0_REG
732 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
734 #define GENERAL_REGISTER_P(REGNO) \
735 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
737 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
738 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
740 #define FP_REGISTER_P(REGNO) \
741 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
743 #define XD_REGISTER_P(REGNO) \
744 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
746 #define FP_OR_XD_REGISTER_P(REGNO) \
747 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
749 #define FP_ANY_REGISTER_P(REGNO) \
750 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
752 #define SPECIAL_REGISTER_P(REGNO) \
753 ((REGNO) == GBR_REG || (REGNO) == T_REG \
754 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
756 #define TARGET_REGISTER_P(REGNO) \
757 ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG)
759 #define SHMEDIA_REGISTER_P(REGNO) \
760 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
761 || TARGET_REGISTER_P (REGNO))
763 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
764 that should be fixed. */
765 #define VALID_REGISTER_P(REGNO) \
766 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
767 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
768 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
769 || (TARGET_SH3E && (REGNO) == FPUL_REG))
771 /* The mode that should be generally used to store a register by
772 itself in the stack, or to load it back. */
773 #define REGISTER_NATURAL_MODE(REGNO) \
774 (FP_REGISTER_P (REGNO) ? SFmode \
775 : XD_REGISTER_P (REGNO) ? DFmode \
776 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
777 ? DImode \
778 : SImode)
780 #define FIRST_PSEUDO_REGISTER 153
782 /* 1 for registers that have pervasive standard uses
783 and are not available for the register allocator.
785 Mach register is fixed 'cause it's only 10 bits wide for SH1.
786 It is 32 bits wide for SH2. */
788 #define FIXED_REGISTERS \
789 { \
791 0, 0, 0, 0, 0, 0, 0, 0, \
792 0, 0, 0, 0, 0, 0, 0, 1, \
794 1, 0, 0, 0, 0, 0, 0, 0, \
797 1, 1, 1, 1, 0, 0, 0, 0, \
798 0, 0, 0, 0, 0, 0, 0, 0, \
799 0, 0, 0, 0, 0, 0, 0, 0, \
800 0, 0, 0, 0, 0, 0, 0, 0, \
801 0, 0, 0, 0, 0, 0, 0, 1, \
803 0, 0, 0, 0, 0, 0, 0, 0, \
804 0, 0, 0, 0, 0, 0, 0, 0, \
805 0, 0, 0, 0, 0, 0, 0, 0, \
806 0, 0, 0, 0, 0, 0, 0, 0, \
807 0, 0, 0, 0, 0, 0, 0, 0, \
808 0, 0, 0, 0, 0, 0, 0, 0, \
809 0, 0, 0, 0, 0, 0, 0, 0, \
810 0, 0, 0, 0, 0, 0, 0, 0, \
812 0, 0, 0, 0, 0, 0, 0, 0, \
814 0, 0, 0, 0, 0, 0, 0, 0, \
816 1, 1, 1, 1, 1, 1, 0, 1, \
818 1, \
819 }
821 /* 1 for registers not available across function calls.
822 These must include the FIXED_REGISTERS and also any
823 registers that can be used without being saved.
824 The latter must include the registers where values are returned
825 and the register where structure-value addresses are passed.
826 Aside from that, you can include as many other registers as you like. */
828 #define CALL_USED_REGISTERS \
829 { \
831 1, 1, 1, 1, 1, 1, 1, 1, \
832 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
833 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
835 0, 0, 0, 0, 0, 0, 0, 1, \
836 1, 1, 0, 1, 1, 1, 1, 1, \
837 1, 1, 1, 1, 0, 0, 0, 0, \
838 0, 0, 0, 0, 1, 1, 1, 1, \
839 1, 1, 1, 1, 0, 0, 0, 0, \
840 0, 0, 0, 0, 0, 0, 0, 0, \
841 0, 0, 0, 0, 1, 1, 1, 1, \
843 1, 1, 1, 1, 1, 1, 1, 1, \
844 1, 1, 1, 1, 0, 0, 0, 0, \
845 1, 1, 1, 1, 1, 1, 1, 1, \
846 1, 1, 1, 1, 1, 1, 1, 1, \
847 1, 1, 1, 1, 0, 0, 0, 0, \
848 0, 0, 0, 0, 0, 0, 0, 0, \
849 0, 0, 0, 0, 0, 0, 0, 0, \
850 0, 0, 0, 0, 0, 0, 0, 0, \
852 1, 1, 1, 1, 1, 0, 0, 0, \
854 1, 1, 1, 1, 1, 1, 0, 0, \
856 1, 1, 0, 1, 1, 1, 1, 1, \
858 1, \
859 }
861 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
862 across SHcompact function calls. We can't tell whether a called
863 function is SHmedia or SHcompact, so we assume it may be when
864 compiling SHmedia code with the 32-bit ABI, since that's the only
865 ABI that can be linked with SHcompact code. */
866 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
867 (TARGET_SHMEDIA32 \
868 && GET_MODE_SIZE (MODE) > 4 \
869 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
870 && (REGNO) <= FIRST_GENERAL_REG + 14) \
871 || (REGNO) == PR_MEDIA_REG))
873 /* Return number of consecutive hard regs needed starting at reg REGNO
874 to hold something of mode MODE.
875 This is ordinarily the length in words of a value of mode MODE
876 but can be less for certain modes in special long registers.
878 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
880 #define HARD_REGNO_NREGS(REGNO, MODE) \
881 (XD_REGISTER_P (REGNO) \
882 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
883 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
884 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
885 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
887 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
888 We can allow any mode in any general register. The special registers
889 only allow SImode. Don't allow any mode in the PR. */
891 /* We cannot hold DCmode values in the XD registers because alter_reg
892 handles subregs of them incorrectly. We could work around this by
893 spacing the XD registers like the DR registers, but this would require
894 additional memory in every compilation to hold larger register vectors.
895 We could hold SFmode / SCmode values in XD registers, but that
896 would require a tertiary reload when reloading from / to memory,
897 and a secondary reload to reload from / to general regs; that
898 seems to be a loosing proposition. */
899 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
900 it won't be ferried through GP registers first. */
901 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
902 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
903 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
904 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
905 ? 1 \
906 : (MODE) == V2SFmode \
907 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
908 || (TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
909 : (MODE) == V4SFmode \
910 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
911 : (MODE) == V16SFmode \
912 ? (TARGET_SHMEDIA \
913 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
914 : (REGNO) == FIRST_XD_REG) \
915 : FP_REGISTER_P (REGNO) \
916 ? ((MODE) == SFmode \
917 || (TARGET_SHMEDIA && (MODE) == SImode) \
918 || ((TARGET_SH3E || TARGET_SHMEDIA) && (MODE) == SCmode) \
919 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
920 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
921 || (MODE) == V2SFmode || (MODE) == TImode))) \
922 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
923 : XD_REGISTER_P (REGNO) \
924 ? (MODE) == DFmode \
925 : TARGET_REGISTER_P (REGNO) \
926 ? ((MODE) == DImode || (MODE) == SImode) \
927 : (REGNO) == PR_REG ? 0 \
928 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
929 : 1)
931 /* Value is 1 if MODE is a supported vector mode. */
932 #define VECTOR_MODE_SUPPORTED_P(MODE) \
933 ((TARGET_FPU_ANY \
934 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
935 || (TARGET_SHMEDIA \
936 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
937 || (MODE) == V2SImode)))
939 /* Value is 1 if it is a good idea to tie two pseudo registers
940 when one has mode MODE1 and one has mode MODE2.
941 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
942 for any hard reg, then this must be 0 for correct output.
943 That's the case for xd registers: we don't hold SFmode values in
944 them, so we can't tie an SFmode pseudos with one in another
945 floating-point mode. */
947 #define MODES_TIEABLE_P(MODE1, MODE2) \
948 ((MODE1) == (MODE2) \
949 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
950 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
951 && (GET_MODE_SIZE (MODE2) <= 4)) \
952 : ((MODE1) != SFmode && (MODE2) != SFmode))))
954 /* A C expression that is nonzero if hard register NEW_REG can be
955 considered for use as a rename register for OLD_REG register */
957 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
958 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
960 /* Specify the registers used for certain standard purposes.
961 The values of these macros are register numbers. */
963 /* Define this if the program counter is overloaded on a register. */
964 /* #define PC_REGNUM 15*/
966 /* Register to use for pushing function arguments. */
967 #define STACK_POINTER_REGNUM SP_REG
969 /* Base register for access to local variables of the function. */
970 #define FRAME_POINTER_REGNUM FP_REG
972 /* Fake register that holds the address on the stack of the
973 current function's return address. */
974 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
976 /* Register to hold the addressing base for position independent
977 code access to data items. */
978 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
982 /* Value should be nonzero if functions must have frame pointers.
983 Zero means the frame pointer need not be set up (and parms may be accessed
984 via the stack pointer) in functions that seem suitable. */
986 #define FRAME_POINTER_REQUIRED 0
988 /* Definitions for register eliminations.
990 We have three registers that can be eliminated on the SH. First, the
991 frame pointer register can often be eliminated in favor of the stack
992 pointer register. Secondly, the argument pointer register can always be
993 eliminated; it is replaced with either the stack or frame pointer.
994 Third, there is the return address pointer, which can also be replaced
995 with either the stack or the frame pointer. */
997 /* This is an array of structures. Each structure initializes one pair
998 of eliminable registers. The "from" register number is given first,
999 followed by "to". Eliminations of the same "from" register are listed
1000 in order of preference. */
1002 /* If you add any registers here that are not actually hard registers,
1003 and that have any alternative of elimination that doesn't always
1004 apply, you need to amend calc_live_regs to exclude it, because
1005 reload spills all eliminable registers where it sees an
1006 can_eliminate == 0 entry, thus making them 'live' .
1007 If you add any hard registers that can be eliminated in different
1008 ways, you have to patch reload to spill them only when all alternatives
1009 of elimination fail. */
1011 #define ELIMINABLE_REGS \
1012 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1013 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1014 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1015 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1016 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1018 /* Given FROM and TO register numbers, say whether this elimination
1019 is allowed. */
1020 #define CAN_ELIMINATE(FROM, TO) \
1021 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1023 /* Define the offset between two registers, one to be eliminated, and the other
1024 its replacement, at the start of a routine. */
1026 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1027 OFFSET = initial_elimination_offset ((FROM), (TO))
1029 /* Base register for access to arguments of the function. */
1030 #define ARG_POINTER_REGNUM AP_REG
1032 /* Register in which the static-chain is passed to a function. */
1033 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1035 /* The register in which a struct value address is passed. */
1037 #define STRUCT_VALUE_REGNUM 2
1039 /* If the structure value address is not passed in a register, define
1040 `STRUCT_VALUE' as an expression returning an RTX for the place
1041 where the address is passed. If it returns 0, the address is
1042 passed as an "invisible" first argument. */
1044 /* The Hitachi calling convention doesn't quite fit into this scheme since
1045 the address is passed like an invisible argument, but one that is always
1046 passed in memory. */
1047 #define STRUCT_VALUE \
1048 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
1050 #define RETURN_IN_MEMORY(TYPE) \
1051 (TARGET_SH5 \
1052 ? ((TYPE_MODE (TYPE) == BLKmode \
1053 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1054 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
1055 : (TYPE_MODE (TYPE) == BLKmode \
1056 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE))
1058 /* Don't default to pcc-struct-return, because we have already specified
1059 exactly how to return structures in the RETURN_IN_MEMORY macro. */
1061 #define DEFAULT_PCC_STRUCT_RETURN 0
1063 #define SHMEDIA_REGS_STACK_ADJUST() \
1064 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1067 : 0)
1069 \f
1070 /* Define the classes of registers for register constraints in the
1071 machine description. Also define ranges of constants.
1073 One of the classes must always be named ALL_REGS and include all hard regs.
1074 If there is more than one class, another class must be named NO_REGS
1075 and contain no registers.
1077 The name GENERAL_REGS must be the name of a class (or an alias for
1078 another name such as ALL_REGS). This is the class of registers
1079 that is allowed by "g" or "r" in a register constraint.
1080 Also, registers outside this class are allocated only when
1081 instructions express preferences for them.
1083 The classes must be numbered in nondecreasing order; that is,
1084 a larger-numbered class must never be contained completely
1085 in a smaller-numbered class.
1087 For any two classes, it is very desirable that there be another
1088 class that represents their union. */
1090 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1091 be used as the destination of some of the arithmetic ops. There are
1092 also some special purpose registers; the T bit register, the
1093 Procedure Return Register and the Multiply Accumulate Registers. */
1094 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1095 reg_class_subunion. We don't want to have an actual union class
1096 of these, because it would only be used when both classes are calculated
1097 to give the same cost, but there is only one FPUL register.
1098 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1099 applying to the actual instruction alternative considered. E.g., the
1100 y/r alternative of movsi_ie is considered to have no more cost that
1101 the r/r alternative, which is patently untrue. */
1103 enum reg_class
1104 {
1105 NO_REGS,
1106 R0_REGS,
1107 PR_REGS,
1108 T_REGS,
1109 MAC_REGS,
1110 FPUL_REGS,
1111 SIBCALL_REGS,
1112 GENERAL_REGS,
1113 FP0_REGS,
1114 FP_REGS,
1115 DF_HI_REGS,
1116 DF_REGS,
1117 FPSCR_REGS,
1118 GENERAL_FP_REGS,
1119 TARGET_REGS,
1120 ALL_REGS,
1121 LIM_REG_CLASSES
1122 };
1124 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1126 /* Give names of register classes as strings for dump file. */
1127 #define REG_CLASS_NAMES \
1128 { \
1145 }
1147 /* Define which registers fit in which classes.
1148 This is an initializer for a vector of HARD_REG_SET
1149 of length N_REG_CLASSES. */
1151 #define REG_CLASS_CONTENTS \
1152 { \
1154 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1156 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1158 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1160 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1162 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1164 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1166 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1168 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1170 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1172 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1174 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1176 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1178 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1180 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1182 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1184 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1185 }
1187 /* The same information, inverted:
1188 Return the class number of the smallest class containing
1189 reg number REGNO. This could be a conditional expression
1190 or could index an array. */
1193 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1195 /* When defined, the compiler allows registers explicitly used in the
1196 rtl to be used as spill registers but prevents the compiler from
1197 extending the lifetime of these registers. */
1199 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1201 /* The order in which register should be allocated. */
1202 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1203 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1204 spilled or used otherwise, we better have the FP_REGS allocated first. */
1205 #define REG_ALLOC_ORDER \
1206 { 65, 66, 67, 68, 69, 70, 71, 64, \
1207 72, 73, 74, 75, 76, 77, 78, 79, \
1208 136,137,138,139,140,141,142,143, \
1209 80, 81, 82, 83, 84, 85, 86, 87, \
1210 88, 89, 90, 91, 92, 93, 94, 95, \
1211 96, 97, 98, 99,100,101,102,103, \
1212 104,105,106,107,108,109,110,111, \
1213 112,113,114,115,116,117,118,119, \
1214 120,121,122,123,124,125,126,127, \
1215 151, 1, 2, 3, 7, 6, 5, 4, \
1216 0, 8, 9, 10, 11, 12, 13, 14, \
1217 16, 17, 18, 19, 20, 21, 22, 23, \
1218 24, 25, 26, 27, 28, 29, 30, 31, \
1219 32, 33, 34, 35, 36, 37, 38, 39, \
1220 40, 41, 42, 43, 44, 45, 46, 47, \
1221 48, 49, 50, 51, 52, 53, 54, 55, \
1222 56, 57, 58, 59, 60, 61, 62, 63, \
1223 150, 15,145,146,147,144,148,149, \
1224 128,129,130,131,132,133,134,135, \
1225 152 }
1227 /* The class value for index registers, and the one for base regs. */
1228 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1229 #define BASE_REG_CLASS GENERAL_REGS
1231 /* Get reg_class from a letter such as appears in the machine
1232 description. */
1235 #define REG_CLASS_FROM_LETTER(C) \
1237 \f
1238 /* The letters I, J, K, L and M in a register constraint string
1239 can be used to stand for particular ranges of immediate operands.
1240 This macro defines what the ranges are.
1241 C is the letter, and VALUE is a constant value.
1242 Return 1 if VALUE is in the range specified by C.
1243 I: arithmetic operand -127..128, as used in add, sub, etc
1244 J: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1245 K: shift operand 1,2,8 or 16
1246 L: logical operand 0..255, as used in and, or, etc.
1247 M: constant 1
1248 N: constant 0
1249 O: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1250 P: arithmetic operand -512..511, as used in SHmedia andi, ori
1251 */
1253 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1254 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1255 #define CONST_OK_FOR_J(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1256 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1257 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1258 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1259 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1260 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1261 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1262 #define CONST_OK_FOR_O(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1263 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1264 #define CONST_OK_FOR_P(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1265 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1266 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1275 : 0)
1277 /* Similar, but for floating constants, and defining letters G and H.
1278 Here VALUE is the CONST_DOUBLE rtx itself. */
1280 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1285 /* Given an rtx X being reloaded into a reg required to be
1286 in class CLASS, return the class of reg to actually use.
1287 In general this is just CLASS; but on some machines
1288 in some cases it is preferable to use a more restrictive class. */
1290 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1291 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1292 && (GET_CODE (X) == CONST_DOUBLE \
1293 || GET_CODE (X) == SYMBOL_REF) \
1294 ? GENERAL_REGS \
1295 : (CLASS)) \
1297 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1298 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
1299 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS) \
1300 && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
1301 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
1302 && GET_CODE (X) == REG \
1303 && FP_REGISTER_P (REGNO (X)))) \
1304 && ! TARGET_SHMEDIA \
1305 && MODE == SFmode) \
1306 ? FPUL_REGS \
1307 : ((CLASS) == FPUL_REGS \
1308 && (GET_CODE (X) == MEM \
1309 || (GET_CODE (X) == REG \
1310 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1311 || REGNO (X) == T_REG \
1312 || system_reg_operand (X, VOIDmode))))) \
1313 ? GENERAL_REGS \
1314 : ((CLASS) == TARGET_REGS \
1315 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1316 ? ((target_operand ((X), (MODE)) \
1317 && ! target_reg_operand ((X), (MODE))) \
1318 ? NO_REGS : GENERAL_REGS) \
1319 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1320 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1321 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1322 ? GENERAL_REGS \
1323 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1324 && TARGET_REGISTER_P (REGNO (X))) \
1325 ? GENERAL_REGS : NO_REGS)
1327 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1328 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS \
1329 || (CLASS) == DF_HI_REGS) \
1330 && ! TARGET_SHMEDIA \
1331 && immediate_operand ((X), (MODE)) \
1332 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1333 && (MODE) == SFmode && fldi_ok ())) \
1334 ? R0_REGS \
1335 : (CLASS == FPUL_REGS \
1336 && ((GET_CODE (X) == REG \
1337 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1338 || REGNO (X) == T_REG)))) \
1339 ? GENERAL_REGS \
1340 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1341 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
1342 ? GENERAL_REGS \
1343 : R0_REGS) \
1344 : (CLASS == FPSCR_REGS \
1345 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1346 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1347 ? GENERAL_REGS \
1348 : (((CLASS) == FP_REGS || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)\
1349 && TARGET_SHMEDIA \
1350 && immediate_operand ((X), (MODE)) \
1351 && (X) != CONST0_RTX (GET_MODE (X)) \
1352 && GET_MODE (X) != V4SFmode) \
1353 ? GENERAL_REGS \
1354 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1356 /* Return the maximum number of consecutive registers
1357 needed to represent mode MODE in a register of class CLASS.
1359 On SH this is the size of MODE in words. */
1360 #define CLASS_MAX_NREGS(CLASS, MODE) \
1361 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1363 /* If defined, gives a class of registers that cannot be used as the
1364 operand of a SUBREG that changes the mode of the object illegally. */
1365 /* ??? We need to renumber the internal numbers for the frnn registers
1366 when in little endian in order to allow mode size changes. */
1368 #define CLASS_CANNOT_CHANGE_MODE (TARGET_LITTLE_ENDIAN ? DF_REGS : DF_HI_REGS)
1370 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1372 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1373 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1374 && ((TARGET_LITTLE_ENDIAN && GET_MODE_SIZE (TO) < 8) \
1375 || GET_MODE_SIZE (FROM) < 8))
1376 \f
1377 /* Stack layout; function entry, exit and calling. */
1379 /* Define the number of registers that can hold parameters.
1380 These macros are used only in other macro definitions below. */
1382 #define NPARM_REGS(MODE) \
1383 (TARGET_FPU_ANY && (MODE) == SFmode \
1384 ? (TARGET_SH5 ? 12 : 8) \
1385 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1386 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1387 ? (TARGET_SH5 ? 12 : 8) \
1388 : (TARGET_SH5 ? 8 : 4))
1390 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1391 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1393 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1394 #define FIRST_FP_RET_REG FIRST_FP_REG
1396 /* Define this if pushing a word on the stack
1397 makes the stack pointer a smaller address. */
1398 #define STACK_GROWS_DOWNWARD
1400 /* Define this macro if the addresses of local variable slots are at
1401 negative offsets from the frame pointer.
1403 The SH only has positive indexes, so grow the frame up. */
1404 /* #define FRAME_GROWS_DOWNWARD */
1406 /* Offset from the frame pointer to the first local variable slot to
1407 be allocated. */
1408 #define STARTING_FRAME_OFFSET 0
1410 /* If we generate an insn to push BYTES bytes,
1411 this says how many the stack pointer really advances by. */
1412 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1413 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1414 do correct alignment. */
1415 #if 0
1416 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1417 #endif
1419 /* Offset of first parameter from the argument pointer register value. */
1420 #define FIRST_PARM_OFFSET(FNDECL) 0
1422 /* Value is the number of byte of arguments automatically
1423 popped when returning from a subroutine call.
1424 FUNDECL is the declaration node of the function (as a tree),
1425 FUNTYPE is the data type of the function (as a tree),
1426 or for a library call it is an identifier node for the subroutine name.
1427 SIZE is the number of bytes of arguments passed on the stack.
1429 On the SH, the caller does not pop any of its arguments that were passed
1430 on the stack. */
1431 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1433 /* Value is the number of bytes of arguments automatically popped when
1434 calling a subroutine.
1435 CUM is the accumulated argument list.
1437 On SHcompact, the call trampoline pops arguments off the stack. */
1438 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1440 /* Nonzero if we do not know how to pass TYPE solely in registers.
1441 Values that come in registers with inconvenient padding are stored
1442 to memory at the function start. */
1444 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1445 ((TYPE) != 0 \
1446 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1447 || TREE_ADDRESSABLE (TYPE)))
1448 /* Some subroutine macros specific to this machine. */
1450 #define BASE_RETURN_VALUE_REG(MODE) \
1451 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1452 ? FIRST_FP_RET_REG \
1453 : TARGET_FPU_ANY && (MODE) == SCmode \
1454 ? FIRST_FP_RET_REG \
1455 : (TARGET_FPU_DOUBLE \
1456 && ((MODE) == DFmode || (MODE) == SFmode \
1457 || (MODE) == DCmode || (MODE) == SCmode )) \
1458 ? FIRST_FP_RET_REG \
1459 : FIRST_RET_REG)
1461 #define BASE_ARG_REG(MODE) \
1462 ((TARGET_SH3E && ((MODE) == SFmode)) \
1463 ? FIRST_FP_PARM_REG \
1464 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1465 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1466 ? FIRST_FP_PARM_REG \
1467 : FIRST_PARM_REG)
1469 /* Define how to find the value returned by a function.
1470 VALTYPE is the data type of the value (as a tree).
1471 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1472 otherwise, FUNC is 0.
1473 For the SH, this is like LIBCALL_VALUE, except that we must change the
1474 mode like PROMOTE_MODE does.
1475 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1476 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1478 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1479 gen_rtx (REG, \
1480 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1481 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1482 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1483 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1484 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1485 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1486 || TREE_CODE (VALTYPE) == REAL_TYPE \
1487 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1488 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1489 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1491 /* Define how to find the value returned by a library function
1492 assuming the value has mode MODE. */
1493 #define LIBCALL_VALUE(MODE) \
1494 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1496 /* 1 if N is a possible register number for a function value. */
1497 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1498 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG) \
1499 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1501 /* 1 if N is a possible register number for function argument passing. */
1502 #define FUNCTION_ARG_REGNO_P(REGNO) \
1503 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG \
1504 + NPARM_REGS (SImode))) \
1505 || (TARGET_FPU_ANY \
1506 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG \
1507 + NPARM_REGS (SFmode))))
1508 \f
1509 /* Define a data type for recording info about an argument list
1510 during the scan of that argument list. This data type should
1511 hold all necessary information about the function itself
1512 and about the args processed so far, enough to enable macros
1513 such as FUNCTION_ARG to determine where the next arg should go.
1515 On SH, this is a single integer, which is a number of words
1516 of arguments scanned so far (including the invisible argument,
1517 if any, which holds the structure-value-address).
1518 Thus NARGREGS or more means all following args should go on the stack. */
1524 /* Non-zero if a prototype is available for the function. */
1526 /* The number of an odd floating-point register, that should be used
1527 for the next argument of type float. */
1529 /* Whether we're processing an outgoing function call. */
1531 /* The number of general-purpose registers that should have been
1532 used to pass partial arguments, that are passed totally on the
1533 stack. On SHcompact, a call trampoline will pop them off the
1534 stack before calling the actual function, and, if the called
1535 function is implemented in SHcompact mode, the incoming arguments
1536 decoder will push such arguments back onto the stack. For
1537 incoming arguments, STACK_REGS also takes into account other
1538 arguments passed by reference, that the decoder will also push
1539 onto the stack. */
1541 /* The number of general-purpose registers that should have been
1542 used to pass arguments, if the arguments didn't have to be passed
1543 by reference. */
1545 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1546 reference. */
1549 /* call_cookie is a bitmask used by call expanders, as well as
1550 function prologue and epilogues, to allow SHcompact to comply
1551 with the SH5 32-bit ABI, that requires 64-bit registers to be
1552 used even though only the lower 32-bit half is visible in
1553 SHcompact mode. The strategy is to call SHmedia trampolines.
1555 The alternatives for each of the argument-passing registers are
1556 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1557 contents from the address in it; (d) add 8 to it, storing the
1558 result in the next register, then (c); (e) copy it from some
1559 floating-point register,
1561 Regarding copies from floating-point registers, r2 may only be
1562 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1563 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1564 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1565 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1566 dr10.
1568 The bit mask is structured as follows:
1570 - 1 bit to tell whether to set up a return trampoline.
1572 - 3 bits to count the number consecutive registers to pop off the
1573 stack.
1575 - 4 bits for each of r9, r8, r7 and r6.
1577 - 3 bits for each of r5, r4, r3 and r2.
1579 - 3 bits set to 0 (the most significant ones)
1581 3 2 1 0
1582 1098 7654 3210 9876 5432 1098 7654 3210
1583 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1584 2223 3344 4555 6666 7777 8888 9999 SSS-
1586 - If F is set, the register must be copied from an FP register,
1587 whose number is encoded in the remaining bits.
1589 - Else, if L is set, the register must be loaded from the address
1590 contained in it. If the P bit is *not* set, the address of the
1591 following dword should be computed first, and stored in the
1592 following register.
1594 - Else, if P is set, the register alone should be popped off the
1595 stack.
1597 - After all this processing, the number of registers represented
1598 in SSS will be popped off the stack. This is an optimization
1599 for pushing/popping consecutive registers, typically used for
1600 varargs and large arguments partially passed in registers.
1602 - If T is set, a return trampoline will be set up for 64-bit
1603 return values to be split into 2 32-bit registers. */
1604 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1605 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1606 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1607 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1608 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1609 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1610 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1611 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1612 #define CALL_COOKIE_INT_REG(REG, VAL) \
1613 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1614 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1615 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1617 };
1619 #define CUMULATIVE_ARGS struct sh_args
1621 #define GET_SH_ARG_CLASS(MODE) \
1622 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1623 ? SH_ARG_FLOAT \
1624 /* There's no mention of complex float types in the SH5 ABI, so we
1626 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1627 ? SH_ARG_INT \
1628 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1629 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1630 ? SH_ARG_FLOAT : SH_ARG_INT)
1632 #define ROUND_ADVANCE(SIZE) \
1633 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1635 /* Round a register number up to a proper boundary for an arg of mode
1636 MODE.
1638 The SH doesn't care about double alignment, so we only
1639 round doubles to even regs when asked to explicitly. */
1641 #define ROUND_REG(CUM, MODE) \
1642 (((TARGET_ALIGN_DOUBLE \
1643 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1644 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1645 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1646 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1647 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1648 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1650 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1651 for a call to a function whose data type is FNTYPE.
1652 For a library call, FNTYPE is 0.
1654 On SH, the offset always starts at 0: the first parm reg is always
1655 the same reg for a given argument class.
1657 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1659 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1660 do { \
1661 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1662 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1663 (CUM).force_mem \
1664 = (TARGET_HITACHI && FNTYPE \
1665 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1666 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1667 (CUM).arg_count[(int) SH_ARG_INT] \
1668 = (TARGET_SH5 && (FNTYPE) \
1669 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1670 (CUM).free_single_fp_reg = 0; \
1671 (CUM).outgoing = 1; \
1672 (CUM).stack_regs = 0; \
1673 (CUM).byref_regs = 0; \
1674 (CUM).byref = 0; \
1675 (CUM).call_cookie \
1676 = (CALL_COOKIE_RET_TRAMP \
1677 (TARGET_SHCOMPACT && (FNTYPE) \
1678 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1679 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1680 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1681 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1682 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1683 (FNTYPE))) \
1684 == FIRST_RET_REG))); \
1685 } while (0)
1687 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1688 do { \
1689 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1690 (CUM).call_cookie \
1691 = (CALL_COOKIE_RET_TRAMP \
1692 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1693 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1694 } while (0)
1696 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1697 do { \
1698 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1699 (CUM).outgoing = 0; \
1700 } while (0)
1702 /* FIXME: This is overly conservative. A SHcompact function that
1703 receives arguments ``by reference'' will have them stored in its
1704 own stack frame, so it must not pass pointers or references to
1705 these arguments to other functions by means of sibling calls. */
1706 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1707 (! TARGET_SHCOMPACT || current_function_args_info.stack_regs == 0)
1709 /* Update the data in CUM to advance over an argument
1710 of mode MODE and data type TYPE.
1711 (TYPE is null for libcalls where that information may not be
1712 available.) */
1714 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1715 if ((CUM).force_mem) \
1716 (CUM).force_mem = 0; \
1717 else if (TARGET_SH5) \
1718 { \
1719 tree TYPE_ = ((CUM).byref && (TYPE) \
1720 ? TREE_TYPE (TYPE) \
1721 : (TYPE)); \
1722 enum machine_mode MODE_ = ((CUM).byref && (TYPE) \
1723 ? TYPE_MODE (TYPE_) \
1724 : (MODE)); \
1725 int dwords = (((CUM).byref \
1726 ? (CUM).byref \
1727 : (MODE_) == BLKmode \
1728 ? int_size_in_bytes (TYPE_) \
1729 : GET_MODE_SIZE (MODE_)) + 7) / 8; \
1730 int numregs = MIN (dwords, NPARM_REGS (SImode) \
1731 - (CUM).arg_count[(int) SH_ARG_INT]); \
1732 \
1733 if (numregs) \
1734 { \
1735 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \
1736 if (TARGET_SHCOMPACT \
1737 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
1738 { \
1739 (CUM).call_cookie \
1740 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1741 - numregs), 1); \
1743 (CUM).stack_regs += numregs; \
1744 } \
1745 else if ((CUM).byref) \
1746 { \
1747 if (! (CUM).outgoing) \
1748 (CUM).stack_regs += numregs; \
1749 (CUM).byref_regs += numregs; \
1750 (CUM).byref = 0; \
1751 do \
1752 (CUM).call_cookie \
1753 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1754 - numregs), 2); \
1755 while (--numregs); \
1756 (CUM).call_cookie \
1757 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1758 - 1), 1); \
1759 } \
1760 else if (dwords > numregs) \
1761 { \
1762 int pushregs = numregs; \
1763 \
1764 if (TARGET_SHCOMPACT) \
1765 (CUM).stack_regs += numregs; \
1766 while (pushregs < NPARM_REGS (SImode) - 1 \
1767 && (CALL_COOKIE_INT_REG_GET \
1768 ((CUM).call_cookie, \
1769 NPARM_REGS (SImode) - pushregs) \
1770 == 1)) \
1771 { \
1772 (CUM).call_cookie \
1773 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
1774 - pushregs, 1); \
1775 pushregs++; \
1776 } \
1777 if (numregs == NPARM_REGS (SImode)) \
1778 (CUM).call_cookie \
1779 |= CALL_COOKIE_INT_REG (0, 1) \
1780 | CALL_COOKIE_STACKSEQ (numregs - 1); \
1781 else \
1782 (CUM).call_cookie \
1783 |= CALL_COOKIE_STACKSEQ (numregs); \
1784 } \
1785 } \
1786 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \
1787 && ((NAMED) || ! (CUM).prototype_p)) \
1788 { \
1789 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
1790 (CUM).free_single_fp_reg = 0; \
1791 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1792 < NPARM_REGS (SFmode)) \
1793 { \
1794 int numfpregs \
1795 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
1796 NPARM_REGS (SFmode) \
1797 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
1798 \
1799 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
1800 \
1801 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
1802 { \
1803 if ((CUM).outgoing && numregs > 0) \
1804 do \
1805 { \
1806 (CUM).call_cookie \
1807 |= (CALL_COOKIE_INT_REG \
1808 ((CUM).arg_count[(int) SH_ARG_INT] \
1809 - numregs + ((numfpregs - 2) / 2), \
1810 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1811 - numfpregs) / 2)); \
1812 } \
1813 while (numfpregs -= 2); \
1814 } \
1815 else if ((MODE_) == SFmode && (NAMED) \
1816 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1817 < NPARM_REGS (SFmode))) \
1818 (CUM).free_single_fp_reg \
1819 = FIRST_FP_PARM_REG - numfpregs \
1820 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
1821 } \
1822 } \
1823 } \
1824 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1825 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1826 = (ROUND_REG ((CUM), (MODE)) \
1827 + ((MODE) == BLKmode \
1828 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1829 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1831 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1832 This macro is only used in this file. */
1834 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1835 (((TYPE) == 0 \
1836 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1837 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1838 && ! (CUM).force_mem \
1839 && (TARGET_SH3E \
1840 ? ((MODE) == BLKmode \
1841 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1842 + int_size_in_bytes (TYPE)) \
1843 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1844 : ((ROUND_REG((CUM), (MODE)) \
1845 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1846 <= NPARM_REGS (MODE))) \
1847 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1849 /* Define where to put the arguments to a function.
1850 Value is zero to push the argument on the stack,
1851 or a hard register in which to store the argument.
1853 MODE is the argument's machine mode.
1854 TYPE is the data type of the argument (as a tree).
1855 This is null for libcalls where that information may
1856 not be available.
1857 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1858 the preceding args and about the function being called.
1859 NAMED is nonzero if this argument is a named parameter
1860 (otherwise it is an extra parameter matching an ellipsis).
1862 On SH the first args are normally in registers
1863 and the rest are pushed. Any arg that starts within the first
1864 NPARM_REGS words is at least partially passed in a register unless
1865 its data type forbids. */
1867 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1868 ((! TARGET_SH5 \
1869 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1870 && ((NAMED) || !TARGET_HITACHI)) \
1871 ? gen_rtx_REG ((MODE), \
1872 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1873 ^ ((MODE) == SFmode && TARGET_SH4 \
1874 && TARGET_LITTLE_ENDIAN != 0))) \
1875 : TARGET_SH5 \
1876 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \
1877 ? GEN_INT ((CUM).call_cookie) \
1878 /* The following test assumes unnamed arguments are promoted to \
1880 : (MODE) == SFmode && (CUM).free_single_fp_reg \
1881 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \
1882 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1883 && ((NAMED) || ! (CUM).prototype_p) \
1884 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \
1885 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \
1886 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE)) \
1887 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), \
1888 FIRST_FP_PARM_REG \
1889 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
1890 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1891 && (! TARGET_SHCOMPACT \
1892 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1893 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1894 (TYPE), (NAMED))))) \
1895 ? gen_rtx_REG ((MODE), (FIRST_PARM_REG \
1896 + (CUM).arg_count[(int) SH_ARG_INT])) \
1897 : 0) \
1898 : 0)
1900 /* Whether an argument must be passed by reference. On SHcompact, we
1901 pretend arguments wider than 32-bits that would have been passed in
1902 registers are passed by reference, so that an SHmedia trampoline
1903 loads them into the full 64-bits registers. */
1904 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
1905 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
1906 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
1908 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
1909 ((CUM).byref \
1910 = (TARGET_SHCOMPACT \
1911 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1912 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
1913 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1914 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1915 >= NPARM_REGS (SFmode)))) \
1916 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1917 : GET_MODE_SIZE (MODE)) > 4 \
1918 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1919 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1920 (TYPE), (NAMED))) \
1921 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1922 : GET_MODE_SIZE (MODE)) \
1923 : 0)
1925 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1926 register in SHcompact mode, it must be padded in the most
1927 significant end. This means that passing it by reference wouldn't
1928 pad properly on a big-endian machine. In this particular case, we
1929 pass this argument on the stack, in a way that the call trampoline
1930 will load its value into the appropriate register. */
1931 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1932 ((MODE) == BLKmode \
1933 && TARGET_SHCOMPACT \
1934 && ! TARGET_LITTLE_ENDIAN \
1935 && int_size_in_bytes (TYPE) > 4 \
1936 && int_size_in_bytes (TYPE) < 8)
1938 /* Minimum alignment for an argument to be passed by callee-copy
1939 reference. We need such arguments to be aligned to 8 byte
1940 boundaries, because they'll be loaded using quad loads. */
1941 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1943 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
1944 ((CUM).outgoing \
1945 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
1946 : GET_MODE_ALIGNMENT (MODE)) \
1947 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
1949 /* The SH5 ABI requires floating-point arguments to be passed to
1950 functions without a prototype in both an FP register and a regular
1951 register or the stack. When passing the argument in both FP and
1952 general-purpose registers, list the FP register first. */
1953 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1954 (gen_rtx_PARALLEL \
1955 ((MODE), \
1956 gen_rtvec (2, \
1957 gen_rtx_EXPR_LIST \
1958 (VOIDmode, \
1959 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1960 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1961 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1962 : NULL_RTX), \
1963 const0_rtx), \
1964 gen_rtx_EXPR_LIST \
1965 (VOIDmode, \
1966 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1967 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1968 + (CUM).arg_count[(int) SH_ARG_INT]) \
1969 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1970 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1971 const0_rtx))))
1973 /* The SH5 ABI requires regular registers or stack slots to be
1974 reserved for floating-point arguments. Registers are taken care of
1975 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1976 Unfortunately, there's no way to just reserve a stack slot, so
1977 we'll end up needlessly storing a copy of the argument in the
1978 stack. For incoming arguments, however, the PARALLEL will be
1979 optimized to the register-only form, and the value in the stack
1980 slot won't be used at all. */
1981 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1982 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1983 ? gen_rtx_REG ((MODE), (REG)) \
1984 : gen_rtx_PARALLEL ((MODE), \
1985 gen_rtvec (2, \
1986 gen_rtx_EXPR_LIST \
1987 (VOIDmode, NULL_RTX, \
1988 const0_rtx), \
1989 gen_rtx_EXPR_LIST \
1990 (VOIDmode, gen_rtx_REG ((MODE), \
1991 (REG)), \
1992 const0_rtx))))
1994 #define STRICT_ARGUMENT_NAMING TARGET_SH5
1996 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
1998 /* For an arg passed partly in registers and partly in memory,
1999 this is the number of registers used.
2000 For args passed entirely in registers or entirely in memory, zero.
2002 We sometimes split args. */
2004 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2005 ((! TARGET_SH5 \
2006 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2007 && ! TARGET_SH4 \
2008 && (ROUND_REG ((CUM), (MODE)) \
2009 + ((MODE) != BLKmode \
2010 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2011 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2012 > NPARM_REGS (MODE))) \
2013 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2014 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2015 && ! TARGET_SHCOMPACT) \
2016 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2017 : 0)
2019 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2020 (TARGET_SH5 && (MODE) == BLKmode \
2021 && ((CUM).arg_count[(int) SH_ARG_INT] \
2022 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2024 /* Perform any needed actions needed for a function that is receiving a
2025 variable number of arguments. */
2027 /* We actually emit the code in sh_expand_prologue. We used to use
2028 a static variable to flag that we need to emit this code, but that
2029 doesn't when inlining, when functions are deferred and then emitted
2030 later. Fortunately, we already have two flags that are part of struct
2031 function that tell if a function uses varargs or stdarg. */
2032 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
2033 if (! current_function_stdarg) \
2034 abort (); \
2035 while (0)
2037 /* Define the `__builtin_va_list' type for the ABI. */
2038 #define BUILD_VA_LIST_TYPE(VALIST) \
2039 (VALIST) = sh_build_va_list ()
2041 /* Implement `va_start' for varargs and stdarg. */
2042 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2043 sh_va_start (valist, nextarg)
2045 /* Implement `va_arg'. */
2046 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2047 sh_va_arg (valist, type)
2049 /* Call the function profiler with a given profile label.
2050 We use two .aligns, so as to make sure that both the .long is aligned
2051 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2052 from the trapa instruction. */
2054 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2055 { \
2060 }
2062 /* Define this macro if the code for function profiling should come
2063 before the function prologue. Normally, the profiling code comes
2064 after. */
2066 #define PROFILE_BEFORE_PROLOGUE
2068 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2069 the stack pointer does not matter. The value is tested only in
2070 functions that have frame pointers.
2071 No definition is equivalent to always zero. */
2073 #define EXIT_IGNORE_STACK 1
2075 /*
2076 On the SH, the trampoline looks like
2077 2 0002 D202 mov.l l2,r2
2078 1 0000 D301 mov.l l1,r3
2079 3 0004 422B jmp @r2
2080 4 0006 0009 nop
2081 5 0008 00000000 l1: .long area
2082 6 000c 00000000 l2: .long function */
2084 /* Length in units of the trampoline for entering a nested function. */
2085 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 32 : 16)
2087 /* Alignment required for a trampoline in bits . */
2088 #define TRAMPOLINE_ALIGNMENT \
2089 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 : 64)
2091 /* Emit RTL insns to initialize the variable parts of a trampoline.
2092 FNADDR is an RTX for the address of the function's pure code.
2093 CXT is an RTX for the static chain value for the function. */
2095 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) do \
2096 { \
2097 if (TARGET_SH5) \
2098 { \
2099 rtx tramp_templ = gen_rtx_SYMBOL_REF (Pmode, \
2101 int fixed_len = TRAMPOLINE_SIZE - 2 * GET_MODE_SIZE (Pmode); \
2102 \
2103 tramp_templ = gen_datalabel_ref (tramp_templ); \
2104 emit_block_move (gen_rtx_MEM (BLKmode, (TRAMP)), \
2105 gen_rtx_MEM (BLKmode, tramp_templ), \
2106 GEN_INT (fixed_len)); \
2107 emit_move_insn (gen_rtx_MEM (Pmode, plus_constant ((TRAMP), \
2108 fixed_len)), \
2109 (FNADDR)); \
2110 emit_move_insn (gen_rtx_MEM (Pmode, \
2111 plus_constant ((TRAMP), \
2112 fixed_len \
2113 + GET_MODE_SIZE (Pmode))), \
2114 (CXT)); \
2115 emit_insn (gen_ic_invalidate_line (TRAMP)); \
2116 break; \
2117 } \
2118 emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \
2119 GEN_INT (trunc_int_for_mode \
2120 (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,\
2121 SImode))); \
2122 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \
2123 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009));\
2124 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
2125 (CXT)); \
2126 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
2127 (FNADDR)); \
2128 if (TARGET_HARVARD) \
2129 { \
2130 if (TARGET_USERMODE) \
2132 0, VOIDmode, 1, (TRAMP), SImode); \
2133 else \
2134 emit_insn (gen_ic_invalidate_line (TRAMP)); \
2135 } \
2136 } while (0)
2138 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2140 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2141 { \
2142 if (TARGET_SH5) \
2143 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2144 gen_reg_rtx (Pmode), 0, \
2145 OPTAB_LIB_WIDEN); \
2146 } while (0)
2148 /* A C expression whose value is RTL representing the value of the return
2149 address for the frame COUNT steps up from the current frame.
2150 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2151 can ignore COUNT. */
2153 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2154 (((COUNT) == 0) \
2155 ? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
2156 : (rtx) 0)
2158 /* A C expression whose value is RTL representing the location of the
2159 incoming return address at the beginning of any function, before the
2160 prologue. This RTL is either a REG, indicating that the return
2161 value is saved in REG, or a MEM representing a location in
2162 the stack. */
2163 #define INCOMING_RETURN_ADDR_RTX \
2164 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2165 \f
2166 /* Generate necessary RTL for __builtin_saveregs(). */
2167 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
2168 \f
2169 /* Addressing modes, and classification of registers for them. */
2170 #define HAVE_POST_INCREMENT TARGET_SH1
2171 /*#define HAVE_PRE_INCREMENT 1*/
2172 /*#define HAVE_POST_DECREMENT 1*/
2173 #define HAVE_PRE_DECREMENT TARGET_SH1
2175 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2176 ? 0 : TARGET_SH1)
2177 #define USE_LOAD_PRE_DECREMENT(mode) 0
2178 #define USE_STORE_POST_INCREMENT(mode) 0
2179 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2180 ? 0 : TARGET_SH1)
2182 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2183 < (TARGET_SMALLCODE ? 2 : \
2184 ((ALIGN >= 32) ? 16 : 2)))
2186 /* Macros to check register numbers against specific register classes. */
2188 /* These assume that REGNO is a hard or pseudo reg number.
2189 They give nonzero only if REGNO is a hard reg of the suitable class
2190 or a pseudo reg currently allocated to a suitable hard reg.
2191 Since they use reg_renumber, they are safe only once reg_renumber
2192 has been allocated, which happens in local-alloc.c. */
2194 #define REGNO_OK_FOR_BASE_P(REGNO) \
2195 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2196 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2197 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2198 (TARGET_SHMEDIA \
2199 ? (GENERAL_REGISTER_P (REGNO) \
2200 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2201 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2203 /* Maximum number of registers that can appear in a valid memory
2204 address. */
2206 #define MAX_REGS_PER_ADDRESS 2
2208 /* Recognize any constant value that is a valid address. */
2210 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2212 /* Nonzero if the constant value X is a legitimate general operand. */
2214 #define LEGITIMATE_CONSTANT_P(X) \
2215 (TARGET_SHMEDIA \
2216 ? ((GET_MODE (X) != DFmode \
2217 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2218 || (X) == CONST0_RTX (GET_MODE (X)) \
2219 || ! TARGET_SHMEDIA_FPU \
2220 || TARGET_SHMEDIA64) \
2221 : (GET_CODE (X) != CONST_DOUBLE \
2222 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2223 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X)))))
2225 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2226 and check its validity for a certain class.
2227 We have two alternate definitions for each of them.
2228 The usual definition accepts all pseudo regs; the other rejects
2229 them unless they have been allocated suitable hard regs.
2230 The symbol REG_OK_STRICT causes the latter definition to be used. */
2232 #ifndef REG_OK_STRICT
2234 /* Nonzero if X is a hard reg that can be used as a base reg
2235 or if it is a pseudo reg. */
2236 #define REG_OK_FOR_BASE_P(X) \
2237 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2239 /* Nonzero if X is a hard reg that can be used as an index
2240 or if it is a pseudo reg. */
2241 #define REG_OK_FOR_INDEX_P(X) \
2242 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2243 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2245 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2246 or if X is a pseudo reg. */
2247 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2248 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2249 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2251 #else
2253 /* Nonzero if X is a hard reg that can be used as a base reg. */
2254 #define REG_OK_FOR_BASE_P(X) \
2255 REGNO_OK_FOR_BASE_P (REGNO (X))
2257 /* Nonzero if X is a hard reg that can be used as an index. */
2258 #define REG_OK_FOR_INDEX_P(X) \
2259 REGNO_OK_FOR_INDEX_P (REGNO (X))
2261 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2262 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2263 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2265 #endif
2267 /* The 'Q' constraint is a pc relative load operand. */
2268 #define EXTRA_CONSTRAINT_Q(OP) \
2269 (GET_CODE (OP) == MEM \
2270 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2271 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2272 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2273 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2274 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2276 /* The `S' constraint is a 16-bit constant, literal or symbolic. */
2277 #define EXTRA_CONSTRAINT_S(OP) \
2278 (GET_CODE (OP) == CONST \
2279 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2280 && GET_MODE (XEXP ((OP), 0)) == DImode \
2281 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2282 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2283 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2284 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2285 && (MOVI_SHORI_BASE_OPERAND_P \
2286 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2287 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2288 1)) == CONST_INT)))
2290 /* Check whether OP is a datalabel unspec. */
2291 #define DATALABEL_REF_NO_CONST_P(OP) \
2292 (GET_CODE (OP) == UNSPEC \
2293 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2294 && XVECLEN ((OP), 0) == 1 \
2295 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2296 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2298 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2299 CONST. */
2300 #define DATALABEL_REF_P(OP) \
2301 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2302 || DATALABEL_REF_NO_CONST_P (OP))
2304 #define GOT_ENTRY_P(OP) \
2305 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2306 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2308 #define GOTPLT_ENTRY_P(OP) \
2309 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2310 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2312 #define GOTOFF_P(OP) \
2313 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2314 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTOFF)
2316 #define PIC_ADDR_P(OP) \
2317 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2318 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2320 #define NON_PIC_REFERENCE_P(OP) \
2321 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2322 || DATALABEL_REF_P (OP) \
2323 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2324 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2325 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2326 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2328 #define PIC_REFERENCE_P(OP) \
2329 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2330 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2332 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2333 (flag_pic ? PIC_REFERENCE_P (OP) : NON_PIC_REFERENCE_P (OP))
2335 /* The `T' constraint is a label or a symbol. */
2336 #define EXTRA_CONSTRAINT_T(OP) \
2337 (NON_PIC_REFERENCE_P (OP))
2339 /* A zero in any shape or form. */
2340 #define EXTRA_CONSTRAINT_U(OP) \
2341 ((OP) == CONST0_RTX (GET_MODE (OP)))
2343 /* Any vector constant we can handle. */
2344 #define EXTRA_CONSTRAINT_W(OP) \
2345 (GET_CODE (OP) == CONST_VECTOR \
2346 && (sh_rep_vec ((OP), VOIDmode) \
2347 || (HOST_BITS_PER_WIDE_INT >= 64 \
2348 ? sh_const_vec ((OP), VOIDmode) \
2349 : sh_1el_vec ((OP), VOIDmode))))
2351 #define EXTRA_CONSTRAINT(OP, C) \
2357 : 0)
2358 \f
2359 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2360 that is a valid memory address for an instruction.
2361 The MODE argument is the machine mode for the MEM expression
2362 that wants to use this address. */
2364 #define MODE_DISP_OK_4(X,MODE) \
2365 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2366 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
2368 #define MODE_DISP_OK_8(X,MODE) \
2369 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2370 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2372 #define BASE_REGISTER_RTX_P(X) \
2373 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2374 || (GET_CODE (X) == SUBREG \
2375 && GET_CODE (SUBREG_REG (X)) == REG \
2376 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2378 /* Since this must be r0, which is a single register class, we must check
2379 SUBREGs more carefully, to be sure that we don't accept one that extends
2380 outside the class. */
2381 #define INDEX_REGISTER_RTX_P(X) \
2382 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2383 || (GET_CODE (X) == SUBREG \
2384 && GET_CODE (SUBREG_REG (X)) == REG \
2385 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2387 /* Jump to LABEL if X is a valid address RTX. This must also take
2388 REG_OK_STRICT into account when deciding about valid registers, but it uses
2389 the above macros so we are in luck.
2391 Allow REG
2392 REG+disp
2393 REG+r0
2394 REG++
2395 --REG */
2397 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
2398 into the FRx registers. We implement this by setting the maximum offset
2399 to zero when the value is SFmode. This also restricts loading of SFmode
2400 values into the integer registers, but that can't be helped. */
2402 /* The SH allows a displacement in a QI or HI amode, but only when the
2403 other operand is R0. GCC doesn't handle this very well, so we forgo
2404 all of that.
2406 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2407 DI can be any number 0..60. */
2409 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2410 do { \
2411 if (GET_CODE (OP) == CONST_INT) \
2412 { \
2413 if (TARGET_SHMEDIA) \
2414 { \
2415 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2416 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2417 && INTVAL (OP) >= -512 * MODE_SIZE \
2418 && INTVAL (OP) < 512 * MODE_SIZE) \
2419 goto LABEL; \
2420 else \
2421 break; \
2422 } \
2423 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2424 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2425 } \
2426 } while(0)
2428 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2429 { \
2430 if (BASE_REGISTER_RTX_P (X)) \
2431 goto LABEL; \
2432 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2433 && ! TARGET_SHMEDIA \
2434 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2435 goto LABEL; \
2436 else if (GET_CODE (X) == PLUS \
2437 && ((MODE) != PSImode || reload_completed)) \
2438 { \
2439 rtx xop0 = XEXP ((X), 0); \
2440 rtx xop1 = XEXP ((X), 1); \
2441 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2442 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2443 if (GET_MODE_SIZE (MODE) <= 4 \
2444 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2445 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2446 { \
2447 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2448 goto LABEL; \
2449 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2450 goto LABEL; \
2451 } \
2452 } \
2453 }
2454 \f
2455 /* Try machine-dependent ways of modifying an illegitimate address
2456 to be legitimate. If we find one, return the new, valid address.
2457 This macro is used in only one place: `memory_address' in explow.c.
2459 OLDX is the address as it was before break_out_memory_refs was called.
2460 In some cases it is useful to look at this to decide what needs to be done.
2462 MODE and WIN are passed so that this macro can use
2463 GO_IF_LEGITIMATE_ADDRESS.
2465 It is always safe for this macro to do nothing. It exists to recognize
2466 opportunities to optimize the output.
2468 For the SH, if X is almost suitable for indexing, but the offset is
2469 out of range, convert it into a normal form so that cse has a chance
2470 of reducing the number of address registers used. */
2472 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2473 { \
2474 if (flag_pic) \
2475 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2476 if (GET_CODE (X) == PLUS \
2477 && (GET_MODE_SIZE (MODE) == 4 \
2478 || GET_MODE_SIZE (MODE) == 8) \
2479 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2480 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2481 && ! TARGET_SHMEDIA \
2482 && ! (TARGET_SH4 && (MODE) == DFmode) \
2483 && ! (TARGET_SH3E && (MODE) == SFmode)) \
2484 { \
2485 rtx index_rtx = XEXP ((X), 1); \
2486 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2487 rtx sum; \
2488 \
2489 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2490 /* On rare occasions, we might get an unaligned pointer \
2491 that is indexed in a way to give an aligned address. \
2493 /* Instead of offset_base 128..131 use 124..127, so that \
2495 if (offset > 127) \
2496 { \
2497 offset_base = ((offset + 4) & ~60) - 4; \
2498 } \
2499 else \
2500 offset_base = offset & ~60; \
2501 /* Sometimes the normal form does not suit DImode. We \
2502 could avoid that by using smaller ranges, but that \
2503 would give less optimized code when SImode is \
2505 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2506 { \
2507 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2508 GEN_INT (offset_base), NULL_RTX, 0, \
2509 OPTAB_LIB_WIDEN); \
2510 \
2511 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2512 goto WIN; \
2513 } \
2514 } \
2515 }
2517 /* A C compound statement that attempts to replace X, which is an address
2518 that needs reloading, with a valid memory address for an operand of
2519 mode MODE. WIN is a C statement label elsewhere in the code.
2521 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2522 of the address. That will allow inheritance of the address reloads. */
2524 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2525 { \
2526 if (GET_CODE (X) == PLUS \
2527 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2528 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2529 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2530 && ! TARGET_SHMEDIA \
2531 && ! (TARGET_SH4 && (MODE) == DFmode) \
2532 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2533 { \
2534 rtx index_rtx = XEXP (X, 1); \
2535 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2536 rtx sum; \
2537 \
2538 if (TARGET_SH3E && MODE == SFmode) \
2539 { \
2540 X = copy_rtx (X); \
2541 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2542 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2543 (TYPE)); \
2544 goto WIN; \
2545 } \
2546 /* Instead of offset_base 128..131 use 124..127, so that \
2548 if (offset > 127) \
2549 { \
2550 offset_base = ((offset + 4) & ~60) - 4; \
2551 } \
2552 else \
2553 offset_base = offset & ~60; \
2554 /* Sometimes the normal form does not suit DImode. We \
2555 could avoid that by using smaller ranges, but that \
2556 would give less optimized code when SImode is \
2558 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2559 { \
2560 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2561 GEN_INT (offset_base)); \
2562 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
2563 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2564 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2565 (TYPE)); \
2566 goto WIN; \
2567 } \
2568 } \
2570 else if (GET_CODE (X) == PLUS \
2571 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2572 && GET_CODE (XEXP (X, 0)) == PLUS \
2573 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2574 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2575 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2576 && ! TARGET_SHMEDIA \
2577 && ! (TARGET_SH3E && MODE == SFmode)) \
2578 { \
2579 /* Because this address is so complex, we know it must have \
2580 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2582 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2583 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2584 goto WIN; \
2585 } \
2586 }
2588 /* Go to LABEL if ADDR (a legitimate address expression)
2589 has an effect that depends on the machine mode it is used for.
2591 ??? Strictly speaking, we should also include all indexed addressing,
2592 because the index scale factor is the length of the operand.
2593 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2594 high if we did that. So we rely on reload to fix things up. */
2596 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2597 { \
2598 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2599 goto LABEL; \
2600 }
2601 \f
2602 /* Specify the machine mode that this machine uses
2603 for the index in the tablejump instruction. */
2604 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
2606 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2607 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2608 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2609 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2610 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2611 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2612 : SImode)
2614 /* Define as C expression which evaluates to nonzero if the tablejump
2615 instruction expects the table to contain offsets from the address of the
2616 table.
2617 Do not define this if the table should contain absolute addresses. */
2618 #define CASE_VECTOR_PC_RELATIVE 1
2620 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2621 #define FLOAT_TYPE_SIZE 32
2623 /* Since the SH3e has only `float' support, it is desirable to make all
2624 floating point types equivalent to `float'. */
2625 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
2627 /* 'char' is signed by default. */
2628 #define DEFAULT_SIGNED_CHAR 1
2630 /* The type of size_t unsigned int. */
2633 #undef PTRDIFF_TYPE
2637 #define WCHAR_TYPE_SIZE 16
2641 /* Don't cse the address of the function being compiled. */
2642 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2644 /* Max number of bytes we can move from memory to memory
2645 in one reasonably fast instruction. */
2646 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2648 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2649 MOVE_MAX is not a compile-time constant. */
2650 #define MAX_MOVE_MAX 8
2652 /* Max number of bytes we want move_by_pieces to be able to copy
2653 efficiently. */
2654 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2656 /* Define if operations between registers always perform the operation
2657 on the full register even if a narrower mode is specified. */
2658 #define WORD_REGISTER_OPERATIONS
2660 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2661 will either zero-extend or sign-extend. The value of this macro should
2662 be the code that says which one of the two operations is implicitly
2663 done, NIL if none. */
2664 /* FP registers can load SImode values, but don't implicitly sign-extend
2665 them to DImode. */
2666 #define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : NIL)
2668 /* Define if loading short immediate values into registers sign extends. */
2669 #define SHORT_IMMEDIATES_SIGN_EXTEND
2671 /* Nonzero if access to memory by bytes is no faster than for words. */
2672 #define SLOW_BYTE_ACCESS 1
2674 /* We assume that the store-condition-codes instructions store 0 for false
2675 and some other value for true. This is the value stored for true. */
2677 #define STORE_FLAG_VALUE 1
2679 /* Immediate shift counts are truncated by the output routines (or was it
2680 the assembler?). Shift counts in a register are truncated by SH. Note
2681 that the native compiler puts too large (> 32) immediate shift counts
2682 into a register and shifts by the register, letting the SH decide what
2683 to do instead of doing that itself. */
2684 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2685 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2686 expects - the sign bit is significant - so it appears that we need to
2687 leave this zero for correct SH3 code. */
2688 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2690 /* All integers have the same format so truncation is easy. */
2691 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2693 /* Define this if addresses of constant functions
2694 shouldn't be put through pseudo regs where they can be cse'd.
2695 Desirable on machines where ordinary constants are expensive
2696 but a CALL with constant address is cheap. */
2697 /*#define NO_FUNCTION_CSE 1*/
2699 /* Chars and shorts should be passed as ints. */
2700 #define PROMOTE_PROTOTYPES 1
2702 /* The machine modes of pointers and functions. */
2703 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2704 #define FUNCTION_MODE Pmode
2706 /* The relative costs of various types of constants. */
2708 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
2709 case CONST_INT: \
2710 if (TARGET_SHMEDIA) \
2711 { \
2712 if (INTVAL (RTX) == 0) \
2713 return 0; \
2714 if ((OUTER_CODE) == AND && and_operand ((RTX), DImode)) \
2715 return 0; \
2716 if (((OUTER_CODE) == IOR || (OUTER_CODE) == XOR \
2717 || (OUTER_CODE) == PLUS) \
2718 && CONST_OK_FOR_P (INTVAL (RTX))) \
2719 return 0; \
2720 if (CONST_OK_FOR_J (INTVAL (RTX))) \
2721 return COSTS_N_INSNS ((OUTER_CODE) != SET); \
2722 else if (CONST_OK_FOR_J (INTVAL (RTX) >> 16)) \
2723 return COSTS_N_INSNS (2); \
2724 else if (CONST_OK_FOR_J ((INTVAL (RTX) >> 16) >> 16)) \
2725 return COSTS_N_INSNS (3); \
2726 else \
2727 return COSTS_N_INSNS (4); \
2728 } \
2729 if (CONST_OK_FOR_I (INTVAL (RTX))) \
2730 return 0; \
2731 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
2732 && CONST_OK_FOR_L (INTVAL (RTX))) \
2733 return 1; \
2734 else \
2735 return 8; \
2736 case CONST: \
2737 case LABEL_REF: \
2738 case SYMBOL_REF: \
2739 if (TARGET_SHMEDIA64) \
2740 return COSTS_N_INSNS (4); \
2741 if (TARGET_SHMEDIA32) \
2742 return COSTS_N_INSNS (2); \
2743 return 5; \
2744 case CONST_DOUBLE: \
2745 if (TARGET_SHMEDIA) \
2746 return COSTS_N_INSNS (4); \
2747 else \
2748 return 10;
2750 #define RTX_COSTS(X, CODE, OUTER_CODE) \
2751 case PLUS: \
2752 return COSTS_N_INSNS (addsubcosts (X)); \
2753 case AND: \
2754 return COSTS_N_INSNS (andcosts (X)); \
2755 case MULT: \
2756 return COSTS_N_INSNS (multcosts (X)); \
2757 case ASHIFT: \
2758 case ASHIFTRT: \
2759 case LSHIFTRT: \
2760 return COSTS_N_INSNS (shiftcosts (X)); \
2761 case DIV: \
2762 case UDIV: \
2763 case MOD: \
2764 case UMOD: \
2765 return COSTS_N_INSNS (20); \
2766 case FLOAT: \
2767 case FIX: \
2768 return 100;
2770 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2771 are actually function calls with some special constraints on arguments
2772 and register usage.
2774 These macros tell reorg that the references to arguments and
2775 register clobbers for insns of type sfunc do not appear to happen
2776 until after the millicode call. This allows reorg to put insns
2777 which set the argument registers into the delay slot of the millicode
2778 call -- thus they act more like traditional CALL_INSNs.
2780 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2781 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2782 in particular. */
2784 #define INSN_SETS_ARE_DELAYED(X) \
2785 ((GET_CODE (X) == INSN \
2786 && GET_CODE (PATTERN (X)) != SEQUENCE \
2787 && GET_CODE (PATTERN (X)) != USE \
2788 && GET_CODE (PATTERN (X)) != CLOBBER \
2789 && get_attr_is_sfunc (X)))
2791 #define INSN_REFERENCES_ARE_DELAYED(X) \
2792 ((GET_CODE (X) == INSN \
2793 && GET_CODE (PATTERN (X)) != SEQUENCE \
2794 && GET_CODE (PATTERN (X)) != USE \
2795 && GET_CODE (PATTERN (X)) != CLOBBER \
2796 && get_attr_is_sfunc (X)))
2798 \f
2799 /* Position Independent Code. */
2801 /* The prefix used to mark SYMBOL_REFs that refer to data symbols. */
2804 /* Return true if SYM_NAME starts with SH_DATALABEL_ENCODING. */
2805 #define DATALABEL_SYMNAME_P(SYM_NAME) \
2806 (SH_DATALABEL_ENCODING[1] ? (abort (), 0) : \
2807 (SYM_NAME)[0] == SH_DATALABEL_ENCODING[0])
2809 /* Skip an optional SH_DATALABEL_ENCODING in the beginning of
2810 SYM_NAME. Then, remove a leading *, like the default definition in
2811 output.h. */
2812 #define STRIP_DATALABEL_ENCODING(VAR, SYM_NAME) \
2813 (VAR) = (SYM_NAME) + (DATALABEL_SYMNAME_P (SYM_NAME) \
2814 ? strlen (SH_DATALABEL_ENCODING) : 0)
2816 /* We can't directly access anything that contains a symbol,
2817 nor can we indirect via the constant pool. */
2818 #define LEGITIMATE_PIC_OPERAND_P(X) \
2819 (! nonpic_symbol_mentioned_p (X) \
2820 && (GET_CODE (X) != SYMBOL_REF \
2821 || ! CONSTANT_POOL_ADDRESS_P (X) \
2822 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
2824 #define SYMBOLIC_CONST_P(X) \
2825 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2826 && nonpic_symbol_mentioned_p (X))
2827 \f
2828 /* Compute the cost of an address. For the SH, all valid addresses are
2829 the same cost. Use a slightly higher cost for reg + reg addressing,
2830 since it increases pressure on r0. */
2832 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \
2833 && ! TARGET_SHMEDIA \
2834 ? 1 : 0)
2836 /* Compute extra cost of moving data between one register class
2837 and another. */
2839 /* Regclass always uses 2 for moves in the same register class;
2840 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
2841 it uses this information. Hence, the general register <-> floating point
2842 register information here is not used for SFmode. */
2843 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2844 (((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
2845 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS \
2846 || (DSTCLASS) == DF_REGS || (DSTCLASS) == DF_HI_REGS) \
2847 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2848 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
2849 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
2850 || (SRCCLASS) == DF_REGS || (SRCCLASS) == DF_HI_REGS))) \
2851 ? (TARGET_SHMEDIA ? 4 \
2852 : TARGET_FMOVD ? 8 : 12) \
2853 : (((DSTCLASS) == FPUL_REGS \
2854 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
2855 || (SRCCLASS == FPUL_REGS \
2856 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
2857 ? 5 \
2858 : (((DSTCLASS) == FPUL_REGS \
2859 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
2860 || (SRCCLASS) == T_REGS)) \
2861 || ((SRCCLASS) == FPUL_REGS \
2862 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
2863 ? 7 \
2864 : (((SRCCLASS) == TARGET_REGS && (DSTCLASS) != GENERAL_REGS) \
2865 || ((DSTCLASS) == TARGET_REGS && (SRCCLASS) != GENERAL_REGS)) \
2866 ? 20 \
2867 : (((SRCCLASS) == FPSCR_REGS && (DSTCLASS) != GENERAL_REGS) \
2868 || ((DSTCLASS) == FPSCR_REGS && (SRCCLASS) != GENERAL_REGS)) \
2869 ? 4 \
2870 : 2) * ((MODE) == V16SFmode ? 8 : (MODE) == V4SFmode ? 2 : 1))
2872 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2873 would be so that people with slow memory systems could generate
2874 different code that does fewer memory accesses. */
2876 /* A C expression for the cost of a branch instruction. A value of 1
2877 is the default; other values are interpreted relative to that.
2878 The SH1 does not have delay slots, hence we get a pipeline stall
2879 at every branch. The SH4 is superscalar, so the single delay slot
2880 is not sufficient to keep both pipelines filled. */
2881 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2882 \f
2883 /* Assembler output control. */
2885 /* A C string constant describing how to begin a comment in the target
2886 assembler language. The compiler assumes that the comment will end at
2887 the end of the line. */
2890 /* The text to go at the start of the assembler file. */
2891 #define ASM_FILE_START(STREAM) \
2892 output_file_start (STREAM)
2899 /* How to change between sections. */
2901 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2904 #if defined CRT_BEGIN || defined CRT_END
2905 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2906 # undef TEXT_SECTION_ASM_OP
2907 # if __SHMEDIA__ == 1 && __SH5__ == 32
2909 # else
2911 # endif
2912 #endif
2915 /* If defined, a C expression whose value is a string containing the
2916 assembler operation to identify the following data as
2917 uninitialized global data. If not defined, and neither
2918 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2919 uninitialized global data will be output in the data section if
2920 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2921 used. */
2922 #ifndef BSS_SECTION_ASM_OP
2924 #endif
2926 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2927 separate, explicit argument. If you define this macro, it is used
2928 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2929 handling the required alignment of the variable. The alignment is
2930 specified as the number of bits.
2932 Try to use function `asm_output_aligned_bss' defined in file
2933 `varasm.c' when defining this macro. */
2934 #ifndef ASM_OUTPUT_ALIGNED_BSS
2935 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2936 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2937 #endif
2939 /* Define this so that jump tables go in same section as the current function,
2940 which could be text or it could be a user defined section. */
2941 #define JUMP_TABLES_IN_TEXT_SECTION 1
2943 #undef DO_GLOBAL_CTORS_BODY
2944 #define DO_GLOBAL_CTORS_BODY \
2945 { \
2946 typedef (*pfunc)(); \
2947 extern pfunc __ctors[]; \
2948 extern pfunc __ctors_end[]; \
2949 pfunc *p; \
2950 for (p = __ctors_end; p > __ctors; ) \
2951 { \
2952 (*--p)(); \
2953 } \
2954 }
2956 #undef DO_GLOBAL_DTORS_BODY
2957 #define DO_GLOBAL_DTORS_BODY \
2958 { \
2959 typedef (*pfunc)(); \
2960 extern pfunc __dtors[]; \
2961 extern pfunc __dtors_end[]; \
2962 pfunc *p; \
2963 for (p = __dtors; p < __dtors_end; p++) \
2964 { \
2965 (*p)(); \
2966 } \
2967 }
2969 #define ASM_OUTPUT_REG_PUSH(file, v) \
2972 #define ASM_OUTPUT_REG_POP(file, v) \
2975 /* DBX register number for a given compiler register number. */
2976 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2977 to match gdb. */
2978 /* svr4.h undefines this macro, yet we really want to use the same numbers
2979 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2980 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2982 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2983 (GENERAL_REGISTER_P (REGNO) \
2984 ? ((REGNO) - FIRST_GENERAL_REG) \
2985 : FP_REGISTER_P (REGNO) \
2986 ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \
2987 : 77) : 25)) \
2988 : XD_REGISTER_P (REGNO) \
2989 ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2990 : TARGET_REGISTER_P (REGNO) \
2991 ? ((REGNO) - FIRST_TARGET_REG + 68) \
2992 : (REGNO) == PR_REG \
2993 ? (TARGET_SH5 ? 241 : 17) \
2994 : (REGNO) == T_REG \
2995 ? (TARGET_SH5 ? 242 : 18) \
2996 : (REGNO) == GBR_REG \
2997 ? (TARGET_SH5 ? 238 : 19) \
2998 : (REGNO) == MACH_REG \
2999 ? (TARGET_SH5 ? 239 : 20) \
3000 : (REGNO) == MACL_REG \
3001 ? (TARGET_SH5 ? 240 : 21) \
3002 : (REGNO) == FPUL_REG \
3003 ? (TARGET_SH5 ? 244 : 23) \
3004 : (abort(), -1))
3006 /* This is how to output a reference to a user-level label named NAME. */
3007 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
3008 do \
3009 { \
3010 char * lname; \
3011 \
3012 STRIP_DATALABEL_ENCODING (lname, (NAME)); \
3014 fputs (lname + 1, (FILE)); \
3015 else \
3017 } \
3018 while (0)
3020 /* This is how to output a reference to a symbol_ref. On SH5,
3021 references to non-code symbols must be preceded by `datalabel'. */
3022 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3023 do \
3024 { \
3025 if (TARGET_SH5 \
3026 && (DATALABEL_SYMNAME_P (XSTR ((SYM), 0)) \
3027 || CONSTANT_POOL_ADDRESS_P (SYM))) \
3029 assemble_name ((FILE), XSTR ((SYM), 0)); \
3030 } \
3031 while (0)
3033 /* Output a label definition. */
3034 #define ASM_OUTPUT_LABEL(FILE,NAME) \
3037 /* This is how to output an assembler line
3038 that says to advance the location counter
3039 to a multiple of 2**LOG bytes. */
3041 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3042 if ((LOG) != 0) \
3045 /* Output a globalising directive for a label. */
3046 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
3048 assemble_name ((STREAM), (NAME)), \
3051 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3053 /* Construct a private name. */
3054 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
3055 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
3058 /* Output a relative address table. */
3060 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3061 switch (GET_MODE (BODY)) \
3062 { \
3063 case SImode: \
3064 if (TARGET_SH5) \
3065 { \
3067 (VALUE), (REL)); \
3068 break; \
3069 } \
3071 break; \
3072 case HImode: \
3073 if (TARGET_SH5) \
3074 { \
3076 (VALUE), (REL)); \
3077 break; \
3078 } \
3080 break; \
3081 case QImode: \
3082 if (TARGET_SH5) \
3083 { \
3085 (VALUE), (REL)); \
3086 break; \
3087 } \
3089 break; \
3090 default: \
3091 break; \
3092 }
3094 /* Output an absolute table element. */
3096 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3097 if (TARGET_BIGTABLE) \
3099 else \
3102 \f
3103 /* A C statement to be executed just prior to the output of
3104 assembler code for INSN, to modify the extracted operands so
3105 they will be output differently.
3107 Here the argument OPVEC is the vector containing the operands
3108 extracted from INSN, and NOPERANDS is the number of elements of
3109 the vector which contain meaningful data for this insn.
3110 The contents of this vector are what will be used to convert the insn
3111 template into assembler code, so you can change the assembler output
3112 by changing the contents of the vector. */
3114 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3115 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3117 /* Print operand X (an rtx) in assembler syntax to file FILE.
3118 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3119 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3121 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3123 /* Print a memory address as an operand to reference that memory location. */
3125 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3127 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3131 /* Recognize machine-specific patterns that may appear within
3132 constants. Used for PIC-specific UNSPECs. */
3133 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3134 do \
3135 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3136 { \
3137 switch (XINT ((X), 1)) \
3138 { \
3139 case UNSPEC_DATALABEL: \
3141 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3142 break; \
3143 case UNSPEC_PIC: \
3145 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3146 break; \
3147 case UNSPEC_GOT: \
3148 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3150 break; \
3151 case UNSPEC_GOTOFF: \
3152 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3154 break; \
3155 case UNSPEC_PLT: \
3156 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3158 break; \
3159 case UNSPEC_GOTPLT: \
3160 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3162 break; \
3163 case UNSPEC_CALLER: \
3164 { \
3165 char name[32]; \
3167 ASM_GENERATE_INTERNAL_LABEL \
3169 assemble_name ((STREAM), name); \
3170 } \
3171 break; \
3172 default: \
3173 goto FAIL; \
3174 } \
3175 break; \
3176 } \
3177 else \
3178 goto FAIL; \
3179 while (0)
3181 \f
3185 /* Which processor to schedule for. The elements of the enumeration must
3186 match exactly the cpu attribute in the sh.md file. */
3189 PROCESSOR_SH1,
3190 PROCESSOR_SH2,
3191 PROCESSOR_SH3,
3192 PROCESSOR_SH3E,
3193 PROCESSOR_SH4,
3194 PROCESSOR_SH5
3195 };
3197 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3202 enum mdep_reorg_phase_e
3203 {
3204 SH_BEFORE_MDEP_REORG,
3205 SH_INSERT_USES_LABELS,
3206 SH_SHORTEN_BRANCHES0,
3207 SH_FIXUP_PCLOAD,
3208 SH_SHORTEN_BRANCHES1,
3209 SH_AFTER_MDEP_REORG
3210 };
3214 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
3216 /* Generate calls to memcpy, memcmp and memset. */
3218 #define TARGET_MEM_FUNCTIONS
3220 /* Handle Hitachi compiler's pragmas. */
3221 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
3225 } while (0)
3227 /* Set when processing a function with pragma interrupt turned on. */
3231 /* Set when processing a function with interrupt attribute. */
3235 /* Set to an RTX containing the address of the stack to switch to
3236 for interrupt functions. */
3241 \f
3242 /* Instructions with unfilled delay slots take up an
3243 extra two bytes for the nop in the delay slot.
3244 sh-dsp parallel processing insns are four bytes long. */
3246 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3247 (LENGTH) += sh_insn_length_adjustment (X);
3248 \f
3249 /* Define the codes that are matched by predicates in sh.c. */
3250 #define PREDICATE_CODES \
3283 /* Define this macro if it is advisable to hold scalars in registers
3284 in a wider mode than that declared by the program. In such cases,
3285 the value is constrained to be within the bounds of the declared
3286 type, but kept valid in the wider mode. The signedness of the
3287 extension may differ from that of the type.
3289 Leaving the unsignedp unchanged gives better code than always setting it
3290 to 0. This is despite the fact that we have only signed char and short
3291 load instructions. */
3292 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3293 if (GET_MODE_CLASS (MODE) == MODE_INT \
3294 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3295 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3296 (MODE) = (TARGET_SH1 ? SImode : DImode);
3298 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
3299 extensions applied to char/short functions arguments. Defining
3300 PROMOTE_FUNCTION_RETURN does the same for function returns. */
3302 #define PROMOTE_FUNCTION_ARGS
3303 #define PROMOTE_FUNCTION_RETURN
3305 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3306 and poping arguments. However, we do have push/pop instructions, and
3307 rather limited offsets (4 bits) in load/store instructions, so it isn't
3308 clear if this would give better code. If implemented, should check for
3309 compatibility problems. */
3311 #define SH_DYNAMIC_SHIFT_COST \
3312 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3315 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3317 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3319 #define NORMAL_MODE(ENTITY) \
3320 (sh_cfun_interrupt_handler_p () ? FP_MODE_NONE \
3321 : TARGET_FPU_SINGLE ? FP_MODE_SINGLE \
3322 : FP_MODE_DOUBLE)
3324 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
3325 && (REGNO) == FPSCR_REG)
3327 #define MODE_NEEDED(ENTITY, INSN) \
3328 (recog_memoized (INSN) >= 0 \
3329 ? get_attr_fp_mode (INSN) \
3330 : FP_MODE_NONE)
3332 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3333 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3335 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3336 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3338 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3339 sh_can_redirect_branch ((INSN), (SEQ))
3341 #define DWARF_FRAME_RETURN_COLUMN (TARGET_SH5 ? PR_MEDIA_REG : PR_REG)
3343 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3344 /* SH constant pool breaks the devices in crtstuff.c to control section
3345 in where code resides. We have to write it as asm code. */
3346 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3357 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3358 (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \
3359 ? (current_function_is_leaf && ! sh_pr_n_sets () \
3360 ? (hard_reg) \
3361 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3362 ? (plus_constant (arg_pointer_rtx, \
3363 TARGET_SHMEDIA64 ? -8 : -4)) \
3364 : frame_pointer_rtx)) \
3365 : NULL_RTX)