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1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
27 #define TARGET_VERSION \
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because hconfig.h is also included by gencodes.c . */
34 /* Generate SDB debugging information. */
36 #define SDB_DEBUGGING_INFO
38 /* Output DBX (stabs) debugging information if doing -gstabs. */
45 %{m1:-D__sh1__} \
46 %{m2:-D__sh2__} \
47 %{m3:-D__sh3__} \
48 %{m3e:-D__SH3E__} \
49 %{m4-single-only:-D__SH4_SINGLE_ONLY__} \
50 %{m4-single:-D__SH4_SINGLE__} \
51 %{m4-nofpu:-D__sh3__ -D__SH4_NOFPU__} \
52 %{m4:-D__SH4__} \
53 %{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:%{!m4-nofpu:-D__sh1__}}}}}}}} \
54 %{mnomacsave:-D__NOMACSAVE__} \
55 %{mhitachi:-D__HITACHI__}"
63 /* We can not debug without a frame pointer. */
64 /* #define CAN_DEBUG_WITHOUT_FP */
66 #define CONDITIONAL_REGISTER_USAGE do \
67 { \
68 int regno; \
69 if (! TARGET_SH4 || ! TARGET_FMOVD) \
70 { \
71 for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \
72 fixed_regs[regno] = call_used_regs[regno] = 1; \
73 if (! TARGET_SH4) \
74 { \
75 if (! TARGET_SH3E) \
76 { \
77 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
78 fixed_regs[regno] = call_used_regs[regno] = 1; \
79 fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
80 } \
81 } \
82 } \
83 if (flag_pic) \
84 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
86 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
87 { \
88 call_used_regs[MACH_REG] = 0; \
89 call_used_regs[MACL_REG] = 0; \
90 } \
91 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
92 if (! fixed_regs[regno] && call_used_regs[regno]) \
93 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
94 } while (0)
95 \f
96 /* ??? Need to write documentation for all SH options and add it to the
97 invoke.texi file. */
99 /* Run-time compilation parameters selecting different hardware subsets. */
102 #define ISIZE_BIT (1<<1)
103 #define DALIGN_BIT (1<<6)
104 #define SH1_BIT (1<<8)
105 #define SH2_BIT (1<<9)
106 #define SH3_BIT (1<<10)
107 #define SH3E_BIT (1<<11)
108 #define HARD_SH4_BIT (1<<5)
109 #define FPU_SINGLE_BIT (1<<7)
110 #define SH4_BIT (1<<12)
111 #define FMOVD_BIT (1<<4)
112 #define SPACE_BIT (1<<13)
113 #define BIGTABLE_BIT (1<<14)
114 #define RELAX_BIT (1<<15)
115 #define USERMODE_BIT (1<<16)
116 #define HITACHI_BIT (1<<22)
117 #define NOMACSAVE_BIT (1<<23)
118 #define PREFERGOT_BIT (1<<24)
119 #define PADSTRUCT_BIT (1<<28)
120 #define LITTLE_ENDIAN_BIT (1<<29)
121 #define IEEE_BIT (1<<30)
123 /* Nonzero if we should dump out instruction size info. */
124 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
126 /* Nonzero to align doubles on 64 bit boundaries. */
127 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
129 /* Nonzero if we should generate code using type 1 insns. */
130 #define TARGET_SH1 (target_flags & SH1_BIT)
132 /* Nonzero if we should generate code using type 2 insns. */
133 #define TARGET_SH2 (target_flags & SH2_BIT)
135 /* Nonzero if we should generate code using type 3 insns. */
136 #define TARGET_SH3 (target_flags & SH3_BIT)
138 /* Nonzero if we should generate code using type 3E insns. */
139 #define TARGET_SH3E (target_flags & SH3E_BIT)
141 /* Nonzero if the cache line size is 32. */
142 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT)
144 /* Nonzero if we schedule for a superscalar implementation. */
145 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
147 /* Nonzero if the target has separate instruction and data caches. */
148 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
150 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
151 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
153 /* Nonzero if the default precision of th FPU is single */
154 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
156 /* Nonzero if we should generate code using type 4 insns. */
157 #define TARGET_SH4 (target_flags & SH4_BIT)
159 /* Nonzero if we should generate fmovd. */
160 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
162 /* Nonzero if we respect NANs. */
163 #define TARGET_IEEE (target_flags & IEEE_BIT)
165 /* Nonzero if we should generate smaller code rather than faster code. */
166 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
168 /* Nonzero to use long jump tables. */
169 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
171 /* Nonzero to generate pseudo-ops needed by the assembler and linker
172 to do function call relaxing. */
173 #define TARGET_RELAX (target_flags & RELAX_BIT)
175 /* Nonzero if using Hitachi's calling convention. */
176 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
178 /* Nonzero if not saving macl/mach when using -mhitachi */
179 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
181 /* Nonzero if padding structures to a multiple of 4 bytes. This is
182 incompatible with Hitachi's compiler, and gives unusual structure layouts
183 which confuse programmers.
184 ??? This option is not useful, but is retained in case there are people
185 who are still relying on it. It may be deleted in the future. */
186 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
188 /* Nonzero if generating code for a little endian SH. */
189 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
191 /* Nonzero if we should do everything in userland. */
192 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
194 /* Nonzero if we should prefer @GOT calls when generating PIC. */
195 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
197 /* Reset all target-selection flags. */
198 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH3E_BIT | SH4_BIT \
199 | HARD_SH4_BIT | FPU_SINGLE_BIT)
201 #define TARGET_SWITCHES \
233 SUBTARGET_SWITCHES \
235 }
237 /* This are meant to be redefined in the host dependent files */
238 #define SUBTARGET_SWITCHES
240 #define TARGET_DEFAULT (SH1_BIT)
242 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
243 do { \
244 if (LEVEL) \
245 flag_omit_frame_pointer = -1; \
246 if (SIZE) \
247 target_flags |= SPACE_BIT; \
248 } while (0)
250 #define ASSEMBLER_DIALECT assembler_dialect
254 #define OVERRIDE_OPTIONS \
255 do { \
256 sh_cpu = CPU_SH1; \
257 assembler_dialect = 0; \
258 if (TARGET_SH2) \
259 sh_cpu = CPU_SH2; \
260 if (TARGET_SH3) \
261 sh_cpu = CPU_SH3; \
262 if (TARGET_SH3E) \
263 sh_cpu = CPU_SH3E; \
264 if (TARGET_SH4) \
265 { \
266 assembler_dialect = 1; \
267 sh_cpu = CPU_SH4; \
268 } \
269 if (! TARGET_SH4 || ! TARGET_FMOVD) \
270 { \
271 /* Prevent usage of explicit register names for variables \
272 for registers not present / not addressable in the \
274 int regno; \
275 for (regno = (TARGET_SH3E) ? 17 : 0; \
276 regno <= 24; regno++) \
277 fp_reg_names[regno][0] = 0; \
278 } \
279 if (flag_omit_frame_pointer < 0) \
280 /* The debugging information is sufficient, \
282 if (0) \
283 flag_omit_frame_pointer \
284 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
285 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
286 else \
287 flag_omit_frame_pointer = 0; \
288 \
289 if (flag_pic && ! TARGET_PREFERGOT) \
290 flag_no_function_cse = 1; \
291 \
292 /* Never run scheduling before reload, since that can \
293 break global alloc, and generates slower code anyway due \
295 flag_schedule_insns = 0; \
296 } while (0)
297 \f
298 /* Target machine storage layout. */
300 /* Define to use software floating point emulator for REAL_ARITHMETIC and
301 decimal <-> binary conversion. */
302 #define REAL_ARITHMETIC
304 /* Define this if most significant bit is lowest numbered
305 in instructions that operate on numbered bit-fields. */
307 #define BITS_BIG_ENDIAN 0
309 /* Define this if most significant byte of a word is the lowest numbered. */
310 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
312 /* Define this if most significant word of a multiword number is the lowest
313 numbered. */
314 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
316 /* Define this to set the endianness to use in libgcc2.c, which can
317 not depend on target_flags. */
318 #if defined(__LITTLE_ENDIAN__)
319 #define LIBGCC2_WORDS_BIG_ENDIAN 0
320 #else
321 #define LIBGCC2_WORDS_BIG_ENDIAN 1
322 #endif
324 /* Number of bits in an addressable storage unit. */
325 #define BITS_PER_UNIT 8
327 /* Width in bits of a "word", which is the contents of a machine register.
328 Note that this is not necessarily the width of data type `int';
329 if using 16-bit ints on a 68000, this would still be 32.
330 But on a machine with 16-bit registers, this would be 16. */
331 #define BITS_PER_WORD 32
332 #define MAX_BITS_PER_WORD 32
334 /* Width of a word, in units (bytes). */
335 #define UNITS_PER_WORD 4
337 /* Width in bits of a pointer.
338 See also the macro `Pmode' defined below. */
339 #define POINTER_SIZE 32
341 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
342 #define PARM_BOUNDARY 32
344 /* Boundary (in *bits*) on which stack pointer should be aligned. */
345 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
347 /* The log (base 2) of the cache line size, in bytes. Processors prior to
348 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
349 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
350 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
352 /* Allocation boundary (in *bits*) for the code of a function.
353 32 bit alignment is faster, because instructions are always fetched as a
354 pair from a longword boundary. */
355 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8)
357 /* Alignment of field after `int : 0' in a structure. */
358 #define EMPTY_FIELD_BOUNDARY 32
360 /* No data type wants to be aligned rounder than this. */
361 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
363 /* The best alignment to use in cases where we have a choice. */
364 #define FASTEST_ALIGNMENT 32
366 /* Make strings word-aligned so strcpy from constants will be faster. */
367 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
368 ((TREE_CODE (EXP) == STRING_CST \
369 && (ALIGN) < FASTEST_ALIGNMENT) \
370 ? FASTEST_ALIGNMENT : (ALIGN))
372 #ifndef MAX_OFILE_ALIGNMENT
373 #define MAX_OFILE_ALIGNMENT 128
374 #endif
376 /* Make arrays of chars word-aligned for the same reasons. */
377 #define DATA_ALIGNMENT(TYPE, ALIGN) \
378 (TREE_CODE (TYPE) == ARRAY_TYPE \
379 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
380 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
382 /* Number of bits which any structure or union's size must be a
383 multiple of. Each structure or union's size is rounded up to a
384 multiple of this. */
385 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
387 /* Set this nonzero if move instructions will actually fail to work
388 when given unaligned data. */
389 #define STRICT_ALIGNMENT 1
391 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
392 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
393 barrier_align (LABEL_AFTER_BARRIER)
395 #define LOOP_ALIGN(A_LABEL) \
396 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
397 ? 0 : sh_loop_align (A_LABEL))
399 #define LABEL_ALIGN(A_LABEL) \
400 ( \
401 (PREV_INSN (A_LABEL) \
402 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
403 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
404 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
406 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
407 : 0)
409 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
410 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
412 /* The base two logarithm of the known minimum alignment of an insn length. */
413 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
414 (GET_CODE (A_INSN) == INSN \
415 ? 1 \
416 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
417 ? 1 \
418 : CACHE_LOG)
419 \f
420 /* Standard register usage. */
422 /* Register allocation for the Hitachi calling convention:
424 r0 arg return
425 r1..r3 scratch
426 r4..r7 args in
427 r8..r13 call saved
428 r14 frame pointer/call saved
429 r15 stack pointer
430 ap arg pointer (doesn't really exist, always eliminated)
431 pr subroutine return address
432 t t bit
433 mach multiply/accumulate result, high part
434 macl multiply/accumulate result, low part.
435 fpul fp/int communication register
436 rap return address pointer register
437 fr0 fp arg return
438 fr1..fr3 scratch floating point registers
439 fr4..fr11 fp args in
440 fr12..fr15 call saved floating point registers */
442 /* Number of actual hardware registers.
443 The hardware registers are assigned numbers for the compiler
444 from 0 to just below FIRST_PSEUDO_REGISTER.
445 All registers that the compiler knows about must be given numbers,
446 even those that are not normally considered general registers. */
448 /* There are many other relevant definitions in sh.md's md_constants. */
450 #define FIRST_GENERAL_REG R0_REG
451 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + 15)
452 #define FIRST_FP_REG DR0_REG
453 #define LAST_FP_REG (FIRST_FP_REG + 15)
454 #define FIRST_XD_REG XD0_REG
455 #define LAST_XD_REG (FIRST_XD_REG + 7)
457 #define GENERAL_REGISTER_P(REGNO) \
458 ((REGNO) >= FIRST_GENERAL_REG && (REGNO) <= LAST_GENERAL_REG)
460 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
461 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
463 #define FP_REGISTER_P(REGNO) \
464 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
466 #define XD_REGISTER_P(REGNO) \
467 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
469 #define FP_OR_XD_REGISTER_P(REGNO) \
470 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
472 #define FP_ANY_REGISTER_P(REGNO) \
473 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
475 #define SPECIAL_REGISTER_P(REGNO) \
476 ((REGNO) == GBR_REG || (REGNO) == T_REG \
477 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
479 #define FIRST_PSEUDO_REGISTER 49
481 /* 1 for registers that have pervasive standard uses
482 and are not available for the register allocator.
484 Mach register is fixed 'cause it's only 10 bits wide for SH1.
485 It is 32 bits wide for SH2. */
487 #define FIXED_REGISTERS \
488 { 0, 0, 0, 0, \
489 0, 0, 0, 0, \
490 0, 0, 0, 0, \
491 0, 0, 0, 1, \
492 1, 1, 1, 1, \
493 1, 1, 0, 1, \
494 0, 0, 0, 0, \
495 0, 0, 0, 0, \
496 0, 0, 0, 0, \
497 0, 0, 0, 0, \
498 0, 0, 0, 0, \
499 0, 0, 0, 0, \
500 1, \
501 }
503 /* 1 for registers not available across function calls.
504 These must include the FIXED_REGISTERS and also any
505 registers that can be used without being saved.
506 The latter must include the registers where values are returned
507 and the register where structure-value addresses are passed.
508 Aside from that, you can include as many other registers as you like. */
510 #define CALL_USED_REGISTERS \
511 { 1, 1, 1, 1, \
512 1, 1, 1, 1, \
513 0, 0, 0, 0, \
514 0, 0, 0, 1, \
515 1, 0, 1, 1, \
516 1, 1, 1, 1, \
517 1, 1, 1, 1, \
518 1, 1, 1, 1, \
519 1, 1, 1, 1, \
520 0, 0, 0, 0, \
521 1, 1, 1, 1, \
522 1, 1, 0, 0, \
523 1, \
524 }
526 /* Return number of consecutive hard regs needed starting at reg REGNO
527 to hold something of mode MODE.
528 This is ordinarily the length in words of a value of mode MODE
529 but can be less for certain modes in special long registers.
531 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
533 #define HARD_REGNO_NREGS(REGNO, MODE) \
534 (XD_REGISTER_P (REGNO) \
535 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
536 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
538 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
539 We can allow any mode in any general register. The special registers
540 only allow SImode. Don't allow any mode in the PR. */
542 /* We cannot hold DCmode values in the XD registers because alter_reg
543 handles subregs of them incorrectly. We could work around this by
544 spacing the XD registers like the DR registers, but this would require
545 additional memory in every compilation to hold larger register vectors.
546 We could hold SFmode / SCmode values in XD registers, but that
547 would require a tertiary reload when reloading from / to memory,
548 and a secondary reload to reload from / to general regs; that
549 seems to be a loosing proposition. */
550 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
551 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
552 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
553 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
554 ? 1 \
555 : FP_REGISTER_P (REGNO) \
556 ? ((MODE) == SFmode \
557 || (TARGET_SH3E && (MODE) == SCmode) \
558 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \
559 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
560 : XD_REGISTER_P (REGNO) \
561 ? (MODE) == DFmode \
562 : (REGNO) == PR_REG ? 0 \
563 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
564 : 1)
566 /* Value is 1 if it is a good idea to tie two pseudo registers
567 when one has mode MODE1 and one has mode MODE2.
568 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
569 for any hard reg, then this must be 0 for correct output.
570 That's the case for xd registers: we don't hold SFmode values in
571 them, so we can't tie an SFmode pseudos with one in another
572 floating-point mode. */
574 #define MODES_TIEABLE_P(MODE1, MODE2) \
575 ((MODE1) == (MODE2) \
576 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
577 && (MODE1) != SFmode && (MODE2) != SFmode))
579 /* Specify the registers used for certain standard purposes.
580 The values of these macros are register numbers. */
582 /* Define this if the program counter is overloaded on a register. */
583 /* #define PC_REGNUM 15*/
585 /* Register to use for pushing function arguments. */
586 #define STACK_POINTER_REGNUM SP_REG
588 /* Base register for access to local variables of the function. */
589 #define FRAME_POINTER_REGNUM FP_REG
591 /* Fake register that holds the address on the stack of the
592 current function's return address. */
593 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
595 /* Register to hold the addressing base for position independent
596 code access to data items. */
597 #define PIC_OFFSET_TABLE_REGNUM PIC_REG
601 /* Value should be nonzero if functions must have frame pointers.
602 Zero means the frame pointer need not be set up (and parms may be accessed
603 via the stack pointer) in functions that seem suitable. */
605 #define FRAME_POINTER_REQUIRED 0
607 /* Definitions for register eliminations.
609 We have three registers that can be eliminated on the SH. First, the
610 frame pointer register can often be eliminated in favor of the stack
611 pointer register. Secondly, the argument pointer register can always be
612 eliminated; it is replaced with either the stack or frame pointer.
613 Third, there is the return address pointer, which can also be replaced
614 with either the stack or the frame pointer. */
616 /* This is an array of structures. Each structure initializes one pair
617 of eliminable registers. The "from" register number is given first,
618 followed by "to". Eliminations of the same "from" register are listed
619 in order of preference. */
621 /* If you add any registers here that are not actually hard registers,
622 and that have any alternative of elimination that doesn't always
623 apply, you need to amend calc_live_regs to exclude it, because
624 reload spills all eliminable registers where it sees an
625 can_eliminate == 0 entry, thus making them 'live' .
626 If you add any hard registers that can be eliminated in different
627 ways, you have to patch reload to spill them only when all alternatives
628 of elimination fail. */
630 #define ELIMINABLE_REGS \
631 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
632 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
633 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
634 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
635 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
637 /* Given FROM and TO register numbers, say whether this elimination
638 is allowed. */
639 #define CAN_ELIMINATE(FROM, TO) \
640 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
642 /* Define the offset between two registers, one to be eliminated, and the other
643 its replacement, at the start of a routine. */
645 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
646 OFFSET = initial_elimination_offset ((FROM), (TO))
648 /* Base register for access to arguments of the function. */
649 #define ARG_POINTER_REGNUM AP_REG
651 /* Register in which the static-chain is passed to a function. */
652 #define STATIC_CHAIN_REGNUM 3
654 /* The register in which a struct value address is passed. */
656 #define STRUCT_VALUE_REGNUM 2
658 /* If the structure value address is not passed in a register, define
659 `STRUCT_VALUE' as an expression returning an RTX for the place
660 where the address is passed. If it returns 0, the address is
661 passed as an "invisible" first argument. */
663 /* The Hitachi calling convention doesn't quite fit into this scheme since
664 the address is passed like an invisible argument, but one that is always
665 passed in memory. */
666 #define STRUCT_VALUE \
667 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
669 #define RETURN_IN_MEMORY(TYPE) \
670 (TYPE_MODE (TYPE) == BLKmode \
671 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE)
673 /* Don't default to pcc-struct-return, because we have already specified
674 exactly how to return structures in the RETURN_IN_MEMORY macro. */
676 #define DEFAULT_PCC_STRUCT_RETURN 0
677 \f
678 /* Define the classes of registers for register constraints in the
679 machine description. Also define ranges of constants.
681 One of the classes must always be named ALL_REGS and include all hard regs.
682 If there is more than one class, another class must be named NO_REGS
683 and contain no registers.
685 The name GENERAL_REGS must be the name of a class (or an alias for
686 another name such as ALL_REGS). This is the class of registers
687 that is allowed by "g" or "r" in a register constraint.
688 Also, registers outside this class are allocated only when
689 instructions express preferences for them.
691 The classes must be numbered in nondecreasing order; that is,
692 a larger-numbered class must never be contained completely
693 in a smaller-numbered class.
695 For any two classes, it is very desirable that there be another
696 class that represents their union. */
698 /* The SH has two sorts of general registers, R0 and the rest. R0 can
699 be used as the destination of some of the arithmetic ops. There are
700 also some special purpose registers; the T bit register, the
701 Procedure Return Register and the Multiply Accumulate Registers. */
702 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
703 reg_class_subunion. We don't want to have an actual union class
704 of these, because it would only be used when both classes are calculated
705 to give the same cost, but there is only one FPUL register.
706 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
707 applying to the actual instruction alternative considered. E.g., the
708 y/r alternative of movsi_ie is considered to have no more cost that
709 the r/r alternative, which is patently untrue. */
711 enum reg_class
712 {
713 NO_REGS,
714 R0_REGS,
715 PR_REGS,
716 T_REGS,
717 MAC_REGS,
718 FPUL_REGS,
719 SIBCALL_REGS,
720 GENERAL_REGS,
721 FP0_REGS,
722 FP_REGS,
723 DF_REGS,
724 FPSCR_REGS,
725 GENERAL_FP_REGS,
726 ALL_REGS,
727 LIM_REG_CLASSES
728 };
730 #define N_REG_CLASSES (int) LIM_REG_CLASSES
732 /* Give names of register classes as strings for dump file. */
733 #define REG_CLASS_NAMES \
734 { \
749 }
751 /* Define which registers fit in which classes.
752 This is an initializer for a vector of HARD_REG_SET
753 of length N_REG_CLASSES. */
755 #define REG_CLASS_CONTENTS \
756 { \
772 }
774 /* The same information, inverted:
775 Return the class number of the smallest class containing
776 reg number REGNO. This could be a conditional expression
777 or could index an array. */
780 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
782 /* When defined, the compiler allows registers explicitly used in the
783 rtl to be used as spill registers but prevents the compiler from
784 extending the lifetime of these registers. */
786 #define SMALL_REGISTER_CLASSES 1
788 /* The order in which register should be allocated. */
789 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
790 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
791 spilled or used otherwise, we better have the FP_REGS allocated first. */
792 #define REG_ALLOC_ORDER \
793 { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \
794 40,41,42,43,44,45,46,47,48, \
795 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
796 22,15,16,17,18,19,20,21,23 }
798 /* The class value for index registers, and the one for base regs. */
799 #define INDEX_REG_CLASS R0_REGS
800 #define BASE_REG_CLASS GENERAL_REGS
802 /* Get reg_class from a letter such as appears in the machine
803 description. */
806 #define REG_CLASS_FROM_LETTER(C) \
808 \f
809 /* The letters I, J, K, L and M in a register constraint string
810 can be used to stand for particular ranges of immediate operands.
811 This macro defines what the ranges are.
812 C is the letter, and VALUE is a constant value.
813 Return 1 if VALUE is in the range specified by C.
814 I: arithmetic operand -127..128, as used in add, sub, etc
815 K: shift operand 1,2,8 or 16
816 L: logical operand 0..255, as used in and, or, etc.
817 M: constant 1
818 N: constant 0 */
820 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
821 && ((HOST_WIDE_INT)(VALUE)) <= 127)
822 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
823 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
824 && ((HOST_WIDE_INT)(VALUE)) <= 255)
825 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
826 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
827 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
833 : 0)
835 /* Similar, but for floating constants, and defining letters G and H.
836 Here VALUE is the CONST_DOUBLE rtx itself. */
838 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
843 /* Given an rtx X being reloaded into a reg required to be
844 in class CLASS, return the class of reg to actually use.
845 In general this is just CLASS; but on some machines
846 in some cases it is preferable to use a more restrictive class. */
848 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
850 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
851 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
852 || (CLASS) == DF_REGS) \
853 && (GET_CODE (X) == REG && GENERAL_OR_AP_REGISTER_P (REGNO (X)))) \
854 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
855 && GET_CODE (X) == REG \
856 && FP_REGISTER_P (REGNO (X)))) \
857 && MODE == SFmode) \
858 ? FPUL_REGS \
859 : ((CLASS) == FPUL_REGS \
860 && (GET_CODE (X) == MEM \
861 || (GET_CODE (X) == REG \
862 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
863 || REGNO (X) == T_REG \
864 || system_reg_operand (X, VOIDmode))))) \
865 ? GENERAL_REGS \
866 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
867 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
868 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
869 ? GENERAL_REGS : NO_REGS)
871 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
872 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \
873 && immediate_operand ((X), (MODE)) \
874 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
875 && (MODE) == SFmode && fldi_ok ())) \
876 ? R0_REGS \
877 : (CLASS == FPUL_REGS \
878 && ((GET_CODE (X) == REG \
879 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
880 || REGNO (X) == T_REG)))) \
881 ? GENERAL_REGS \
882 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
883 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
884 ? GENERAL_REGS \
885 : R0_REGS) \
886 : (CLASS == FPSCR_REGS \
887 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
888 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
889 ? GENERAL_REGS \
890 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
892 /* Return the maximum number of consecutive registers
893 needed to represent mode MODE in a register of class CLASS.
895 On SH this is the size of MODE in words. */
896 #define CLASS_MAX_NREGS(CLASS, MODE) \
897 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
899 /* If defined, gives a class of registers that cannot be used as the
900 operand of a SUBREG that changes the mode of the object illegally. */
902 #define CLASS_CANNOT_CHANGE_MODE DF_REGS
904 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
906 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
907 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
908 \f
909 /* Stack layout; function entry, exit and calling. */
911 /* Define the number of registers that can hold parameters.
912 These macros are used only in other macro definitions below. */
914 #define NPARM_REGS(MODE) \
915 (TARGET_SH3E && (MODE) == SFmode \
916 ? 8 \
917 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
918 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
919 ? 8 \
920 : 4)
922 #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4)
923 #define FIRST_RET_REG FIRST_GENERAL_REG
925 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
926 #define FIRST_FP_RET_REG FIRST_FP_REG
928 /* Define this if pushing a word on the stack
929 makes the stack pointer a smaller address. */
930 #define STACK_GROWS_DOWNWARD
932 /* Define this macro if the addresses of local variable slots are at
933 negative offsets from the frame pointer.
935 The SH only has positive indexes, so grow the frame up. */
936 /* #define FRAME_GROWS_DOWNWARD */
938 /* Offset from the frame pointer to the first local variable slot to
939 be allocated. */
940 #define STARTING_FRAME_OFFSET 0
942 /* If we generate an insn to push BYTES bytes,
943 this says how many the stack pointer really advances by. */
944 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
945 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
946 do correct alignment. */
947 #if 0
948 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
949 #endif
951 /* Offset of first parameter from the argument pointer register value. */
952 #define FIRST_PARM_OFFSET(FNDECL) 0
954 /* Value is the number of byte of arguments automatically
955 popped when returning from a subroutine call.
956 FUNDECL is the declaration node of the function (as a tree),
957 FUNTYPE is the data type of the function (as a tree),
958 or for a library call it is an identifier node for the subroutine name.
959 SIZE is the number of bytes of arguments passed on the stack.
961 On the SH, the caller does not pop any of its arguments that were passed
962 on the stack. */
963 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
965 /* Nonzero if we do not know how to pass TYPE solely in registers.
966 Values that come in registers with inconvenient padding are stored
967 to memory at the function start. */
969 #define MUST_PASS_IN_STACK(MODE,TYPE) \
970 ((TYPE) != 0 \
971 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
972 || TREE_ADDRESSABLE (TYPE)))
973 /* Some subroutine macros specific to this machine. */
975 #define BASE_RETURN_VALUE_REG(MODE) \
976 ((TARGET_SH3E && ((MODE) == SFmode)) \
977 ? FIRST_FP_RET_REG \
978 : TARGET_SH3E && (MODE) == SCmode \
979 ? FIRST_FP_RET_REG \
980 : (TARGET_SH4 \
981 && ((MODE) == DFmode || (MODE) == SFmode \
982 || (MODE) == DCmode || (MODE) == SCmode )) \
983 ? FIRST_FP_RET_REG \
984 : FIRST_RET_REG)
986 #define BASE_ARG_REG(MODE) \
987 ((TARGET_SH3E && ((MODE) == SFmode)) \
988 ? FIRST_FP_PARM_REG \
989 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
990 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
991 ? FIRST_FP_PARM_REG \
992 : FIRST_PARM_REG)
994 /* Define how to find the value returned by a function.
995 VALTYPE is the data type of the value (as a tree).
996 If the precise function being called is known, FUNC is its FUNCTION_DECL;
997 otherwise, FUNC is 0.
998 For the SH, this is like LIBCALL_VALUE, except that we must change the
999 mode like PROMOTE_MODE does.
1000 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1001 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1003 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1004 gen_rtx (REG, \
1005 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1006 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1007 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1008 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1009 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1010 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1011 || TREE_CODE (VALTYPE) == REAL_TYPE \
1012 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1013 ? SImode : TYPE_MODE (VALTYPE)), \
1014 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1016 /* Define how to find the value returned by a library function
1017 assuming the value has mode MODE. */
1018 #define LIBCALL_VALUE(MODE) \
1019 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1021 /* 1 if N is a possible register number for a function value. */
1022 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1023 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
1025 /* 1 if N is a possible register number for function argument passing. */
1026 #define FUNCTION_ARG_REGNO_P(REGNO) \
1027 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
1028 || (TARGET_SH3E \
1029 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
1030 \f
1031 /* Define a data type for recording info about an argument list
1032 during the scan of that argument list. This data type should
1033 hold all necessary information about the function itself
1034 and about the args processed so far, enough to enable macros
1035 such as FUNCTION_ARG to determine where the next arg should go.
1037 On SH, this is a single integer, which is a number of words
1038 of arguments scanned so far (including the invisible argument,
1039 if any, which holds the structure-value-address).
1040 Thus NARGREGS or more means all following args should go on the stack. */
1046 };
1048 #define CUMULATIVE_ARGS struct sh_args
1050 #define GET_SH_ARG_CLASS(MODE) \
1051 ((TARGET_SH3E && (MODE) == SFmode) \
1052 ? SH_ARG_FLOAT \
1053 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1054 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1055 ? SH_ARG_FLOAT : SH_ARG_INT)
1057 #define ROUND_ADVANCE(SIZE) \
1058 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1060 /* Round a register number up to a proper boundary for an arg of mode
1061 MODE.
1063 The SH doesn't care about double alignment, so we only
1064 round doubles to even regs when asked to explicitly. */
1066 #define ROUND_REG(CUM, MODE) \
1067 (((TARGET_ALIGN_DOUBLE \
1068 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1069 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1070 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1071 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1072 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1073 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1075 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1076 for a call to a function whose data type is FNTYPE.
1077 For a library call, FNTYPE is 0.
1079 On SH, the offset always starts at 0: the first parm reg is always
1080 the same reg for a given argument class.
1082 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1084 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1085 do { \
1086 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1087 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1088 (CUM).force_mem \
1089 = (TARGET_HITACHI && FNTYPE \
1090 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1091 } while (0)
1093 /* Update the data in CUM to advance over an argument
1094 of mode MODE and data type TYPE.
1095 (TYPE is null for libcalls where that information may not be
1096 available.) */
1098 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1099 if ((CUM).force_mem) \
1100 (CUM).force_mem = 0; \
1101 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1102 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1103 = (ROUND_REG ((CUM), (MODE)) \
1104 + ((MODE) == BLKmode \
1105 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1106 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1108 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1109 This macro is only used in this file. */
1111 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1112 (((TYPE) == 0 \
1113 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1114 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1115 && ! (CUM).force_mem \
1116 && (TARGET_SH3E \
1117 ? ((MODE) == BLKmode \
1118 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1119 + int_size_in_bytes (TYPE)) \
1120 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1121 : ((ROUND_REG((CUM), (MODE)) \
1122 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1123 <= NPARM_REGS (MODE))) \
1124 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1126 /* Define where to put the arguments to a function.
1127 Value is zero to push the argument on the stack,
1128 or a hard register in which to store the argument.
1130 MODE is the argument's machine mode.
1131 TYPE is the data type of the argument (as a tree).
1132 This is null for libcalls where that information may
1133 not be available.
1134 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1135 the preceding args and about the function being called.
1136 NAMED is nonzero if this argument is a named parameter
1137 (otherwise it is an extra parameter matching an ellipsis).
1139 On SH the first args are normally in registers
1140 and the rest are pushed. Any arg that starts within the first
1141 NPARM_REGS words is at least partially passed in a register unless
1142 its data type forbids. */
1144 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1145 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1146 && ((NAMED) \
1147 || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \
1148 ? gen_rtx_REG ((MODE), \
1149 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1150 ^ ((MODE) == SFmode && TARGET_SH4 \
1151 && TARGET_LITTLE_ENDIAN != 0))) \
1152 : 0)
1154 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI)
1156 /* For an arg passed partly in registers and partly in memory,
1157 this is the number of registers used.
1158 For args passed entirely in registers or entirely in memory, zero.
1160 We sometimes split args. */
1162 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1163 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1164 && ! TARGET_SH4 \
1165 && (ROUND_REG ((CUM), (MODE)) \
1166 + ((MODE) != BLKmode \
1167 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1168 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
1169 > NPARM_REGS (MODE))) \
1170 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
1171 : 0)
1175 /* Perform any needed actions needed for a function that is receiving a
1176 variable number of arguments. */
1178 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
1179 current_function_anonymous_args = 1;
1181 /* Define the `__builtin_va_list' type for the ABI. */
1182 #define BUILD_VA_LIST_TYPE(VALIST) \
1183 (VALIST) = sh_build_va_list ()
1185 /* Implement `va_start' for varargs and stdarg. */
1186 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1187 sh_va_start (stdarg, valist, nextarg)
1189 /* Implement `va_arg'. */
1190 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1191 sh_va_arg (valist, type)
1193 /* Call the function profiler with a given profile label.
1194 We use two .aligns, so as to make sure that both the .long is aligned
1195 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1196 from the trapa instruction. */
1198 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1199 { \
1204 }
1206 /* Define this macro if the code for function profiling should come
1207 before the function prologue. Normally, the profiling code comes
1208 after. */
1210 #define PROFILE_BEFORE_PROLOGUE
1212 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1213 the stack pointer does not matter. The value is tested only in
1214 functions that have frame pointers.
1215 No definition is equivalent to always zero. */
1217 #define EXIT_IGNORE_STACK 1
1219 /* Generate the assembly code for function exit
1220 Just dump out any accumulated constant table. */
1222 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue ((STREAM), (SIZE))
1224 /*
1225 On the SH, the trampoline looks like
1226 2 0002 D202 mov.l l2,r2
1227 1 0000 D301 mov.l l1,r3
1228 3 0004 422B jmp @r2
1229 4 0006 0009 nop
1230 5 0008 00000000 l1: .long area
1231 6 000c 00000000 l2: .long function */
1233 /* Length in units of the trampoline for entering a nested function. */
1234 #define TRAMPOLINE_SIZE 16
1236 /* Alignment required for a trampoline in bits . */
1237 #define TRAMPOLINE_ALIGNMENT \
1238 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 : 64)
1240 /* Emit RTL insns to initialize the variable parts of a trampoline.
1241 FNADDR is an RTX for the address of the function's pure code.
1242 CXT is an RTX for the static chain value for the function. */
1244 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) do \
1245 { \
1246 emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \
1247 GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301));\
1248 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \
1249 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009));\
1250 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1251 (CXT)); \
1252 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1253 (FNADDR)); \
1254 if (TARGET_HARVARD) \
1255 { \
1256 if (TARGET_USERMODE) \
1258 0, VOIDmode, 1, (TRAMP), SImode); \
1259 else \
1260 emit_insn (gen_ic_invalidate_line (TRAMP)); \
1261 } \
1262 } while (0)
1264 /* A C expression whose value is RTL representing the value of the return
1265 address for the frame COUNT steps up from the current frame.
1266 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1267 can ignore COUNT. */
1269 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1270 (((COUNT) == 0) \
1271 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
1272 : (rtx) 0)
1273 \f
1274 /* Generate necessary RTL for __builtin_saveregs(). */
1275 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
1276 \f
1277 /* Addressing modes, and classification of registers for them. */
1278 #define HAVE_POST_INCREMENT 1
1279 /*#define HAVE_PRE_INCREMENT 1*/
1280 /*#define HAVE_POST_DECREMENT 1*/
1281 #define HAVE_PRE_DECREMENT 1
1283 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1284 ? 0 : 1)
1285 #define USE_LOAD_PRE_DECREMENT(mode) 0
1286 #define USE_STORE_POST_INCREMENT(mode) 0
1287 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1288 ? 0 : 1)
1290 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
1291 < (TARGET_SMALLCODE ? 2 : \
1292 ((ALIGN >= 32) ? 16 : 2)))
1294 /* Macros to check register numbers against specific register classes. */
1296 /* These assume that REGNO is a hard or pseudo reg number.
1297 They give nonzero only if REGNO is a hard reg of the suitable class
1298 or a pseudo reg currently allocated to a suitable hard reg.
1299 Since they use reg_renumber, they are safe only once reg_renumber
1300 has been allocated, which happens in local-alloc.c. */
1302 #define REGNO_OK_FOR_BASE_P(REGNO) \
1303 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1304 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1305 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1306 ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1308 /* Maximum number of registers that can appear in a valid memory
1309 address. */
1311 #define MAX_REGS_PER_ADDRESS 2
1313 /* Recognize any constant value that is a valid address. */
1315 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1317 /* Nonzero if the constant value X is a legitimate general operand. */
1319 #define LEGITIMATE_CONSTANT_P(X) \
1320 (GET_CODE (X) != CONST_DOUBLE \
1321 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1322 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
1324 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1325 and check its validity for a certain class.
1326 We have two alternate definitions for each of them.
1327 The usual definition accepts all pseudo regs; the other rejects
1328 them unless they have been allocated suitable hard regs.
1329 The symbol REG_OK_STRICT causes the latter definition to be used. */
1331 #ifndef REG_OK_STRICT
1333 /* Nonzero if X is a hard reg that can be used as a base reg
1334 or if it is a pseudo reg. */
1335 #define REG_OK_FOR_BASE_P(X) \
1336 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1338 /* Nonzero if X is a hard reg that can be used as an index
1339 or if it is a pseudo reg. */
1340 #define REG_OK_FOR_INDEX_P(X) \
1341 (REGNO (X) == R0_REG || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1343 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
1344 or if X is a pseudo reg. */
1345 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1346 ((REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1348 #else
1350 /* Nonzero if X is a hard reg that can be used as a base reg. */
1351 #define REG_OK_FOR_BASE_P(X) \
1352 REGNO_OK_FOR_BASE_P (REGNO (X))
1354 /* Nonzero if X is a hard reg that can be used as an index. */
1355 #define REG_OK_FOR_INDEX_P(X) \
1356 REGNO_OK_FOR_INDEX_P (REGNO (X))
1358 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
1359 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1360 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
1362 #endif
1364 /* The 'Q' constraint is a pc relative load operand. */
1365 #define EXTRA_CONSTRAINT_Q(OP) \
1366 (GET_CODE (OP) == MEM \
1367 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
1368 || (GET_CODE (XEXP ((OP), 0)) == CONST \
1369 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
1370 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
1371 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
1373 #define EXTRA_CONSTRAINT(OP, C) \
1375 : 0)
1376 \f
1377 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1378 that is a valid memory address for an instruction.
1379 The MODE argument is the machine mode for the MEM expression
1380 that wants to use this address. */
1382 #define MODE_DISP_OK_4(X,MODE) \
1383 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
1384 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
1386 #define MODE_DISP_OK_8(X,MODE) \
1387 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
1388 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
1390 #define BASE_REGISTER_RTX_P(X) \
1391 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1392 || (GET_CODE (X) == SUBREG \
1393 && GET_CODE (SUBREG_REG (X)) == REG \
1394 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1396 /* Since this must be r0, which is a single register class, we must check
1397 SUBREGs more carefully, to be sure that we don't accept one that extends
1398 outside the class. */
1399 #define INDEX_REGISTER_RTX_P(X) \
1400 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1401 || (GET_CODE (X) == SUBREG \
1402 && GET_CODE (SUBREG_REG (X)) == REG \
1403 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
1405 /* Jump to LABEL if X is a valid address RTX. This must also take
1406 REG_OK_STRICT into account when deciding about valid registers, but it uses
1407 the above macros so we are in luck.
1409 Allow REG
1410 REG+disp
1411 REG+r0
1412 REG++
1413 --REG */
1415 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
1416 into the FRx registers. We implement this by setting the maximum offset
1417 to zero when the value is SFmode. This also restricts loading of SFmode
1418 values into the integer registers, but that can't be helped. */
1420 /* The SH allows a displacement in a QI or HI amode, but only when the
1421 other operand is R0. GCC doesn't handle this very well, so we forgo
1422 all of that.
1424 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
1425 DI can be any number 0..60. */
1427 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
1428 do { \
1429 if (GET_CODE (OP) == CONST_INT) \
1430 { \
1431 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
1432 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
1433 } \
1434 } while(0)
1436 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1437 { \
1438 if (BASE_REGISTER_RTX_P (X)) \
1439 goto LABEL; \
1440 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1441 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
1442 goto LABEL; \
1443 else if (GET_CODE (X) == PLUS \
1444 && ((MODE) != PSImode || reload_completed)) \
1445 { \
1446 rtx xop0 = XEXP ((X), 0); \
1447 rtx xop1 = XEXP ((X), 1); \
1448 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1449 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
1450 if (GET_MODE_SIZE (MODE) <= 4 \
1451 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
1452 { \
1453 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1454 goto LABEL; \
1455 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1456 goto LABEL; \
1457 } \
1458 } \
1459 }
1460 \f
1461 /* Try machine-dependent ways of modifying an illegitimate address
1462 to be legitimate. If we find one, return the new, valid address.
1463 This macro is used in only one place: `memory_address' in explow.c.
1465 OLDX is the address as it was before break_out_memory_refs was called.
1466 In some cases it is useful to look at this to decide what needs to be done.
1468 MODE and WIN are passed so that this macro can use
1469 GO_IF_LEGITIMATE_ADDRESS.
1471 It is always safe for this macro to do nothing. It exists to recognize
1472 opportunities to optimize the output.
1474 For the SH, if X is almost suitable for indexing, but the offset is
1475 out of range, convert it into a normal form so that cse has a chance
1476 of reducing the number of address registers used. */
1478 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1479 { \
1480 if (flag_pic) \
1481 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
1482 if (GET_CODE (X) == PLUS \
1483 && (GET_MODE_SIZE (MODE) == 4 \
1484 || GET_MODE_SIZE (MODE) == 8) \
1485 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
1486 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
1487 && ! (TARGET_SH4 && (MODE) == DFmode) \
1488 && ! (TARGET_SH3E && (MODE) == SFmode)) \
1489 { \
1490 rtx index_rtx = XEXP ((X), 1); \
1491 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1492 rtx sum; \
1493 \
1494 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
1495 /* On rare occasions, we might get an unaligned pointer \
1496 that is indexed in a way to give an aligned address. \
1498 /* Instead of offset_base 128..131 use 124..127, so that \
1500 if (offset > 127) \
1501 { \
1502 offset_base = ((offset + 4) & ~60) - 4; \
1503 } \
1504 else \
1505 offset_base = offset & ~60; \
1506 /* Sometimes the normal form does not suit DImode. We \
1507 could avoid that by using smaller ranges, but that \
1508 would give less optimized code when SImode is \
1510 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1511 { \
1512 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
1513 GEN_INT (offset_base), NULL_RTX, 0, \
1514 OPTAB_LIB_WIDEN); \
1515 \
1516 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
1517 goto WIN; \
1518 } \
1519 } \
1520 }
1522 /* A C compound statement that attempts to replace X, which is an address
1523 that needs reloading, with a valid memory address for an operand of
1524 mode MODE. WIN is a C statement label elsewhere in the code.
1526 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
1527 of the address. That will allow inheritance of the address reloads. */
1529 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1530 { \
1531 if (GET_CODE (X) == PLUS \
1532 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1533 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1534 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1535 && ! (TARGET_SH4 && (MODE) == DFmode) \
1536 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
1537 { \
1538 rtx index_rtx = XEXP (X, 1); \
1539 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1540 rtx sum; \
1541 \
1542 if (TARGET_SH3E && MODE == SFmode) \
1543 { \
1544 X = copy_rtx (X); \
1545 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL_PTR, \
1546 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1547 (TYPE)); \
1548 goto WIN; \
1549 } \
1550 /* Instead of offset_base 128..131 use 124..127, so that \
1552 if (offset > 127) \
1553 { \
1554 offset_base = ((offset + 4) & ~60) - 4; \
1555 } \
1556 else \
1557 offset_base = offset & ~60; \
1558 /* Sometimes the normal form does not suit DImode. We \
1559 could avoid that by using smaller ranges, but that \
1560 would give less optimized code when SImode is \
1562 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1563 { \
1564 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1565 GEN_INT (offset_base)); \
1566 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
1567 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1568 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1569 (TYPE)); \
1570 goto WIN; \
1571 } \
1572 } \
1574 else if (GET_CODE (X) == PLUS \
1575 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1576 && GET_CODE (XEXP (X, 0)) == PLUS \
1577 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1578 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
1579 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1580 && ! (TARGET_SH3E && MODE == SFmode)) \
1581 { \
1582 /* Because this address is so complex, we know it must have \
1583 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
1585 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL_PTR, \
1586 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
1587 goto WIN; \
1588 } \
1589 }
1591 /* Go to LABEL if ADDR (a legitimate address expression)
1592 has an effect that depends on the machine mode it is used for.
1594 ??? Strictly speaking, we should also include all indexed addressing,
1595 because the index scale factor is the length of the operand.
1596 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
1597 high if we did that. So we rely on reload to fix things up. */
1599 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1600 { \
1601 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1602 goto LABEL; \
1603 }
1604 \f
1605 /* Specify the machine mode that this machine uses
1606 for the index in the tablejump instruction. */
1607 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1609 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1610 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1611 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1612 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1613 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1614 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1615 : SImode)
1617 /* Define as C expression which evaluates to nonzero if the tablejump
1618 instruction expects the table to contain offsets from the address of the
1619 table.
1620 Do not define this if the table should contain absolute addresses. */
1621 #define CASE_VECTOR_PC_RELATIVE 1
1623 /* Specify the tree operation to be used to convert reals to integers. */
1624 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1626 /* This is the kind of divide that is easiest to do in the general case. */
1627 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1629 /* Since the SH3e has only `float' support, it is desirable to make all
1630 floating point types equivalent to `float'. */
1631 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
1633 /* 'char' is signed by default. */
1634 #define DEFAULT_SIGNED_CHAR 1
1636 /* The type of size_t unsigned int. */
1640 #define WCHAR_TYPE_SIZE 16
1642 /* Don't cse the address of the function being compiled. */
1643 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1645 /* Max number of bytes we can move from memory to memory
1646 in one reasonably fast instruction. */
1647 #define MOVE_MAX 4
1649 /* Max number of bytes we want move_by_pieces to be able to copy
1650 efficiently. */
1651 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
1653 /* Define if operations between registers always perform the operation
1654 on the full register even if a narrower mode is specified. */
1655 #define WORD_REGISTER_OPERATIONS
1657 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1658 will either zero-extend or sign-extend. The value of this macro should
1659 be the code that says which one of the two operations is implicitly
1660 done, NIL if none. */
1661 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1663 /* Define if loading short immediate values into registers sign extends. */
1664 #define SHORT_IMMEDIATES_SIGN_EXTEND
1666 /* Define this if zero-extension is slow (more than one real instruction).
1667 On the SH, it's only one instruction. */
1668 /* #define SLOW_ZERO_EXTEND */
1670 /* Nonzero if access to memory by bytes is no faster than for words. */
1671 #define SLOW_BYTE_ACCESS 1
1673 /* We assume that the store-condition-codes instructions store 0 for false
1674 and some other value for true. This is the value stored for true. */
1676 #define STORE_FLAG_VALUE 1
1678 /* Immediate shift counts are truncated by the output routines (or was it
1679 the assembler?). Shift counts in a register are truncated by SH. Note
1680 that the native compiler puts too large (> 32) immediate shift counts
1681 into a register and shifts by the register, letting the SH decide what
1682 to do instead of doing that itself. */
1683 /* ??? The library routines in lib1funcs.asm truncate the shift count.
1684 However, the SH3 has hardware shifts that do not truncate exactly as gcc
1685 expects - the sign bit is significant - so it appears that we need to
1686 leave this zero for correct SH3 code. */
1687 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
1689 /* All integers have the same format so truncation is easy. */
1690 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1692 /* Define this if addresses of constant functions
1693 shouldn't be put through pseudo regs where they can be cse'd.
1694 Desirable on machines where ordinary constants are expensive
1695 but a CALL with constant address is cheap. */
1696 /*#define NO_FUNCTION_CSE 1*/
1698 /* Chars and shorts should be passed as ints. */
1699 #define PROMOTE_PROTOTYPES 1
1701 /* The machine modes of pointers and functions. */
1702 #define Pmode SImode
1703 #define FUNCTION_MODE Pmode
1705 /* The relative costs of various types of constants. */
1707 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1708 case CONST_INT: \
1709 if (CONST_OK_FOR_I (INTVAL (RTX))) \
1710 return 0; \
1711 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
1712 && CONST_OK_FOR_L (INTVAL (RTX))) \
1713 return 1; \
1714 else \
1715 return 8; \
1716 case CONST: \
1717 case LABEL_REF: \
1718 case SYMBOL_REF: \
1719 return 5; \
1720 case CONST_DOUBLE: \
1721 return 10;
1723 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1724 case PLUS: \
1725 return COSTS_N_INSNS (addsubcosts (X)); \
1726 case AND: \
1727 return COSTS_N_INSNS (andcosts (X)); \
1728 case MULT: \
1729 return COSTS_N_INSNS (multcosts (X)); \
1730 case ASHIFT: \
1731 case ASHIFTRT: \
1732 case LSHIFTRT: \
1733 return COSTS_N_INSNS (shiftcosts (X)); \
1734 case DIV: \
1735 case UDIV: \
1736 case MOD: \
1737 case UMOD: \
1738 return COSTS_N_INSNS (20); \
1739 case FLOAT: \
1740 case FIX: \
1741 return 100;
1743 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1744 are actually function calls with some special constraints on arguments
1745 and register usage.
1747 These macros tell reorg that the references to arguments and
1748 register clobbers for insns of type sfunc do not appear to happen
1749 until after the millicode call. This allows reorg to put insns
1750 which set the argument registers into the delay slot of the millicode
1751 call -- thus they act more like traditional CALL_INSNs.
1753 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1754 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1755 in particular. */
1757 #define INSN_SETS_ARE_DELAYED(X) \
1758 ((GET_CODE (X) == INSN \
1759 && GET_CODE (PATTERN (X)) != SEQUENCE \
1760 && GET_CODE (PATTERN (X)) != USE \
1761 && GET_CODE (PATTERN (X)) != CLOBBER \
1762 && get_attr_is_sfunc (X)))
1764 #define INSN_REFERENCES_ARE_DELAYED(X) \
1765 ((GET_CODE (X) == INSN \
1766 && GET_CODE (PATTERN (X)) != SEQUENCE \
1767 && GET_CODE (PATTERN (X)) != USE \
1768 && GET_CODE (PATTERN (X)) != CLOBBER \
1769 && get_attr_is_sfunc (X)))
1771 \f
1772 /* Position Independent Code. */
1773 /* Define this macro if references to a symbol must be treated
1774 differently depending on something about the variable or function
1775 named by the symbol (such as what section it is in).
1777 On SH, if using PIC, mark a SYMBOL_REF for a non-global symbol
1778 so that we may access it using GOTOFF instead of GOT. */
1780 #define ENCODE_SECTION_INFO(DECL) \
1781 do \
1782 { \
1783 if (flag_pic) \
1784 { \
1786 ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \
1787 \
1788 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = \
1790 || ! TREE_PUBLIC (DECL)); \
1791 } \
1792 } \
1793 while (0)
1795 /* We can't directly access anything that contains a symbol,
1796 nor can we indirect via the constant pool. */
1797 #define LEGITIMATE_PIC_OPERAND_P(X) \
1798 (! nonpic_symbol_mentioned_p (X) \
1799 && (! CONSTANT_POOL_ADDRESS_P (X) \
1800 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
1802 #define SYMBOLIC_CONST_P(X) \
1803 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1804 && nonpic_symbol_mentioned_p (X))
1805 \f
1806 /* Compute the cost of an address. For the SH, all valid addresses are
1807 the same cost. Use a slightly higher cost for reg + reg addressing,
1808 since it increases pressure on r0. */
1810 #define ADDRESS_COST(X) (GET_CODE (X) == PLUS && ! CONSTANT_P (XEXP (X, 1)) \
1811 ? 1 : 0)
1813 /* Compute extra cost of moving data between one register class
1814 and another. */
1816 /* Regclass always uses 2 for moves in the same register class;
1817 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
1818 it uses this information. Hence, the general register <-> floating point
1819 register information here is not used for SFmode. */
1820 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
1821 ((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
1822 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \
1823 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1824 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
1825 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
1826 || (SRCCLASS) == DF_REGS))) \
1827 ? TARGET_FMOVD ? 8 : 12 \
1828 : (((DSTCLASS) == FPUL_REGS \
1829 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1830 || (SRCCLASS == FPUL_REGS \
1831 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
1832 ? 5 \
1833 : (((DSTCLASS) == FPUL_REGS \
1834 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
1835 || (SRCCLASS) == T_REGS)) \
1836 || ((SRCCLASS) == FPUL_REGS \
1837 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
1838 ? 7 \
1839 : 2)
1841 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1842 would be so that people with slow memory systems could generate
1843 different code that does fewer memory accesses. */
1845 /* A C expression for the cost of a branch instruction. A value of 1
1846 is the default; other values are interpreted relative to that.
1847 The SH1 does not have delay slots, hence we get a pipeline stall
1848 at every branch. The SH4 is superscalar, so the single delay slot
1849 is not sufficient to keep both pipelines filled. */
1850 #define BRANCH_COST (! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
1851 \f
1852 /* Assembler output control. */
1854 /* A C string constant describing how to begin a comment in the target
1855 assembler language. The compiler assumes that the comment will end at
1856 the end of the line. */
1859 /* The text to go at the start of the assembler file. */
1860 #define ASM_FILE_START(STREAM) \
1861 output_file_start (STREAM)
1863 #define ASM_FILE_END(STREAM)
1871 /* How to change between sections. */
1877 #define EXTRA_SECTIONS in_ctors, in_dtors
1878 #define EXTRA_SECTION_FUNCTIONS \
1879 void \
1880 ctors_section() \
1881 { \
1882 if (in_section != in_ctors) \
1883 { \
1885 in_section = in_ctors; \
1886 } \
1887 } \
1888 void \
1889 dtors_section() \
1890 { \
1891 if (in_section != in_dtors) \
1892 { \
1894 in_section = in_dtors; \
1895 } \
1896 }
1898 /* If defined, a C expression whose value is a string containing the
1899 assembler operation to identify the following data as
1900 uninitialized global data. If not defined, and neither
1901 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
1902 uninitialized global data will be output in the data section if
1903 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
1904 used. */
1905 #ifndef BSS_SECTION_ASM_OP
1907 #endif
1909 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1910 separate, explicit argument. If you define this macro, it is used
1911 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1912 handling the required alignment of the variable. The alignment is
1913 specified as the number of bits.
1915 Try to use function `asm_output_aligned_bss' defined in file
1916 `varasm.c' when defining this macro. */
1917 #ifndef ASM_OUTPUT_ALIGNED_BSS
1918 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1919 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1920 #endif
1922 /* Define this so that jump tables go in same section as the current function,
1923 which could be text or it could be a user defined section. */
1924 #define JUMP_TABLES_IN_TEXT_SECTION 1
1926 /* A C statement to output something to the assembler file to switch to section
1927 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1928 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1929 define this macro in such cases. */
1931 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
1934 /* This is the pseudo-op used to generate a reference to a specific
1935 symbol in some section. */
1939 /* A C statement (sans semicolon) to output an
1940 element in the table of global constructors. */
1941 #define ASM_OUTPUT_CONSTRUCTOR(FILE, NAME) \
1942 do \
1943 { \
1944 ctors_section (); \
1946 assemble_name (FILE, NAME); \
1948 } \
1949 while (0)
1951 /* A C statement (sans semicolon) to output an
1952 element in the table of global destructors. */
1953 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1954 do \
1955 { \
1956 dtors_section (); \
1958 assemble_name (FILE, NAME); \
1960 } \
1961 while (0)
1963 #undef DO_GLOBAL_CTORS_BODY
1965 #define DO_GLOBAL_CTORS_BODY \
1966 { \
1967 typedef (*pfunc)(); \
1968 extern pfunc __ctors[]; \
1969 extern pfunc __ctors_end[]; \
1970 pfunc *p; \
1971 for (p = __ctors_end; p > __ctors; ) \
1972 { \
1973 (*--p)(); \
1974 } \
1975 }
1977 #undef DO_GLOBAL_DTORS_BODY
1978 #define DO_GLOBAL_DTORS_BODY \
1979 { \
1980 typedef (*pfunc)(); \
1981 extern pfunc __dtors[]; \
1982 extern pfunc __dtors_end[]; \
1983 pfunc *p; \
1984 for (p = __dtors; p < __dtors_end; p++) \
1985 { \
1986 (*p)(); \
1987 } \
1988 }
1990 #define ASM_OUTPUT_REG_PUSH(file, v) \
1993 #define ASM_OUTPUT_REG_POP(file, v) \
1996 /* The assembler's names for the registers. RFP need not always be used as
1997 the Real framepointer; it can also be used as a normal general register.
1998 Note that the name `fp' is horribly misleading since `fp' is in fact only
1999 the argument-and-return-context pointer. */
2003 #define REGISTER_NAMES \
2004 { \
2008 fp_reg_names[0], fp_reg_names[1] , fp_reg_names[2], fp_reg_names[3], \
2009 fp_reg_names[4], fp_reg_names[5], fp_reg_names[6], fp_reg_names[7], \
2010 fp_reg_names[8], fp_reg_names[9], fp_reg_names[10], fp_reg_names[11], \
2011 fp_reg_names[12], fp_reg_names[13], fp_reg_names[14], fp_reg_names[15], \
2012 fp_reg_names[17], fp_reg_names[18], fp_reg_names[19], fp_reg_names[20], \
2013 fp_reg_names[21], fp_reg_names[22], fp_reg_names[23], fp_reg_names[24], \
2015 }
2017 #define DEBUG_REGISTER_NAMES \
2018 { \
2026 }
2028 /* DBX register number for a given compiler register number. */
2029 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2030 to match gdb. */
2031 #define DBX_REGISTER_NUMBER(REGNO) \
2032 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
2034 /* Output a label definition. */
2035 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2038 /* This is how to output an assembler line
2039 that says to advance the location counter
2040 to a multiple of 2**LOG bytes. */
2042 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2043 if ((LOG) != 0) \
2046 /* Output a function label definition. */
2047 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
2048 ASM_OUTPUT_LABEL((STREAM), (NAME))
2050 /* Output a globalising directive for a label. */
2051 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2053 assemble_name ((STREAM), (NAME)), \
2056 /* The prefix to add to user-visible assembler symbols. */
2060 /* The prefix to add to an internally generated label. */
2064 /* Make an internal label into a string. */
2065 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
2068 /* Output an internal label definition. */
2069 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2072 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2074 /* Construct a private name. */
2075 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
2076 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
2079 /* Output a relative address table. */
2081 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2082 switch (GET_MODE (BODY)) \
2083 { \
2084 case SImode: \
2086 break; \
2087 case HImode: \
2089 break; \
2090 case QImode: \
2092 break; \
2093 default: \
2094 break; \
2095 }
2097 /* Output an absolute table element. */
2099 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2100 if (TARGET_BIGTABLE) \
2102 else \
2105 /* Output various types of constants. */
2107 /* This is how to output an assembler line defining a `double'. */
2109 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2110 do { char dstr[30]; \
2113 } while (0)
2115 /* This is how to output an assembler line defining a `float' constant. */
2116 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2117 do { char dstr[30]; \
2120 } while (0)
2122 #define ASM_OUTPUT_INT(STREAM, EXP) \
2124 output_addr_const ((STREAM), (EXP)), \
2127 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
2129 output_addr_const ((STREAM), (EXP)), \
2132 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
2134 output_addr_const ((STREAM), (EXP)), \
2137 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
2140 /* The next two are used for debug info when compiling with -gdwarf. */
2144 /* Loop alignment is now done in machine_dependent_reorg, so that
2145 branch shortening can know about it. */
2147 /* This is how to output an assembler line
2148 that says to advance the location counter by SIZE bytes. */
2150 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2153 /* This says how to output an assembler line
2154 to define a global common symbol. */
2156 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2158 assemble_name ((FILE), (NAME)), \
2161 /* This says how to output an assembler line
2162 to define a local common symbol. */
2164 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2166 assemble_name ((FILE), (NAME)), \
2169 /* The assembler's parentheses characters. */
2173 /* Target characters. */
2174 #define TARGET_BELL 007
2175 #define TARGET_BS 010
2176 #define TARGET_TAB 011
2177 #define TARGET_NEWLINE 012
2178 #define TARGET_VT 013
2179 #define TARGET_FF 014
2180 #define TARGET_CR 015
2181 \f
2182 /* A C statement to be executed just prior to the output of
2183 assembler code for INSN, to modify the extracted operands so
2184 they will be output differently.
2186 Here the argument OPVEC is the vector containing the operands
2187 extracted from INSN, and NOPERANDS is the number of elements of
2188 the vector which contain meaningful data for this insn.
2189 The contents of this vector are what will be used to convert the insn
2190 template into assembler code, so you can change the assembler output
2191 by changing the contents of the vector. */
2193 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2194 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2196 /* Print operand X (an rtx) in assembler syntax to file FILE.
2197 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2198 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2200 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2202 /* Print a memory address as an operand to reference that memory location. */
2204 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2206 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2210 /* Recognize machine-specific patterns that may appear within
2211 constants. Used for PIC-specific UNSPECs. */
2212 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
2213 do \
2214 if (flag_pic && GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
2215 { \
2216 switch (XINT ((X), 1)) \
2217 { \
2218 case UNSPEC_PIC: \
2220 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2221 break; \
2222 case UNSPEC_GOT: \
2223 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2225 break; \
2226 case UNSPEC_GOTOFF: \
2227 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2229 break; \
2230 case UNSPEC_PLT: \
2231 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
2233 break; \
2234 case UNSPEC_CALLER: \
2235 { \
2236 char name[32]; \
2238 ASM_GENERATE_INTERNAL_LABEL \
2240 assemble_name ((STREAM), name); \
2241 } \
2242 break; \
2243 default: \
2244 goto FAIL; \
2245 } \
2246 break; \
2247 } \
2248 else \
2249 goto FAIL; \
2250 while (0)
2252 \f
2256 /* Which processor to schedule for. The elements of the enumeration must
2257 match exactly the cpu attribute in the sh.md file. */
2260 PROCESSOR_SH1,
2261 PROCESSOR_SH2,
2262 PROCESSOR_SH3,
2263 PROCESSOR_SH3E,
2264 PROCESSOR_SH4
2265 };
2267 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2272 enum mdep_reorg_phase_e
2273 {
2274 SH_BEFORE_MDEP_REORG,
2275 SH_INSERT_USES_LABELS,
2276 SH_SHORTEN_BRANCHES0,
2277 SH_FIXUP_PCLOAD,
2278 SH_SHORTEN_BRANCHES1,
2279 SH_AFTER_MDEP_REORG
2280 };
2284 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
2286 /* Generate calls to memcpy, memcmp and memset. */
2288 #define TARGET_MEM_FUNCTIONS
2290 /* Handle Hitachi compiler's pragmas. */
2291 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2295 } while (0)
2297 /* Set when processing a function with pragma interrupt turned on. */
2301 /* Set to an RTX containing the address of the stack to switch to
2302 for interrupt functions. */
2305 /* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
2306 is a valid machine specific attribute for DECL.
2307 The attributes in ATTRIBUTES have previously been assigned to DECL. */
2308 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
2309 sh_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
2311 #define PRAGMA_INSERT_ATTRIBUTES(node, pattr, prefix_attr) \
2312 sh_pragma_insert_attributes (node, pattr, prefix_attr)
2317 \f
2318 /* Instructions with unfilled delay slots take up an
2319 extra two bytes for the nop in the delay slot.
2320 sh-dsp parallel processing insns are four bytes long. */
2322 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2323 (LENGTH) += sh_insn_length_adjustment (X);
2324 \f
2325 /* Define the codes that are matched by predicates in sh.c. */
2326 #define PREDICATE_CODES \
2342 /* Define this macro if it is advisable to hold scalars in registers
2343 in a wider mode than that declared by the program. In such cases,
2344 the value is constrained to be within the bounds of the declared
2345 type, but kept valid in the wider mode. The signedness of the
2346 extension may differ from that of the type.
2348 Leaving the unsignedp unchanged gives better code than always setting it
2349 to 0. This is despite the fact that we have only signed char and short
2350 load instructions. */
2351 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2352 if (GET_MODE_CLASS (MODE) == MODE_INT \
2353 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
2354 (MODE) = SImode;
2356 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
2357 extensions applied to char/short functions arguments. Defining
2358 PROMOTE_FUNCTION_RETURN does the same for function returns. */
2360 #define PROMOTE_FUNCTION_ARGS
2361 #define PROMOTE_FUNCTION_RETURN
2363 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
2364 and poping arguments. However, we do have push/pop instructions, and
2365 rather limited offsets (4 bits) in load/store instructions, so it isn't
2366 clear if this would give better code. If implemented, should check for
2367 compatibility problems. */
2369 /* A C statement (sans semicolon) to update the integer variable COST
2370 based on the relationship between INSN that is dependent on
2371 DEP_INSN through the dependence LINK. The default is to make no
2372 adjustment to COST. This can be used for example to specify to
2373 the scheduler that an output- or anti-dependence does not incur
2374 the same cost as a data-dependence. */
2376 #define ADJUST_COST(insn,link,dep_insn,cost) \
2377 do { \
2378 rtx reg; \
2379 \
2380 if (GET_CODE(insn) == CALL_INSN) \
2381 { \
2382 /* The only input for a call that is timing-critical is the \
2384 rtx call = PATTERN (insn); \
2385 \
2386 if (GET_CODE (call) == PARALLEL) \
2387 call = XVECEXP (call, 0 ,0); \
2388 if (GET_CODE (call) == SET) \
2389 call = SET_SRC (call); \
2390 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM \
2391 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) \
2392 (cost) = 0; \
2393 } \
2394 /* All sfunc calls are parallels with at least four components. \
2396 else if (GET_CODE (PATTERN (insn)) == PARALLEL \
2397 && XVECLEN (PATTERN (insn), 0) >= 4 \
2398 && (reg = sfunc_uses_reg (insn))) \
2399 { \
2400 /* Likewise, the most timing critical input for an sfuncs call \
2401 is the function address. However, sfuncs typically start \
2402 using their arguments pretty quickly. \
2404 if (! reg_set_p (reg, dep_insn)) \
2405 cost -= TARGET_SUPERSCALAR ? 40 : 4; \
2406 } \
2407 /* Adjust load_si / pcload_si type insns latency. Use the known \
2409 else if (cost == 3 \
2410 && GET_CODE (PATTERN (dep_insn)) == SET \
2411 /* Latency for dmpy type insns is also 3, so check the that \
2413 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\
2414 cost = 2; \
2415 else if (cost == 30 \
2416 && GET_CODE (PATTERN (dep_insn)) == SET \
2417 && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode) \
2418 cost = 20; \
2419 } while (0) \
2421 #define SH_DYNAMIC_SHIFT_COST \
2422 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
2425 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2427 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
2429 #define NORMAL_MODE(ENTITY) \
2430 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2432 #define EPILOGUE_USES(REGNO) ((TARGET_SH3E || TARGET_SH4) \
2433 && (REGNO) == FPSCR_REG)
2435 #define MODE_NEEDED(ENTITY, INSN) \
2436 (recog_memoized (INSN) >= 0 \
2437 ? get_attr_fp_mode (INSN) \
2438 : FP_MODE_NONE)
2440 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2441 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2443 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2444 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2446 #define DWARF_LINE_MIN_INSTR_LENGTH 2
2448 /* SH constant pool breaks the devices in crtstuff.c to control section
2449 in where code resides. We have to write it as asm code. */
2450 #define CRT_CALL_STATIC_FUNCTION(func) \
2451 if (0) \
2453 func (); \
2454 else \
2455 /* We should be passing FUNC to the asm statement as an asm input \
2457 asm \