gcc/config/m32c/m32c.h

   1 /* Target Definitions for R8C/M16C/M32C
   2    Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011
   3    Free Software Foundation, Inc.
   4    Contributed by Red Hat.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published
  10    by the Free Software Foundation; either version 3, or (at your
  11    option) any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but WITHOUT
  14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16    License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_M32C_H
  23 #define GCC_M32C_H
  24
  25 /* Controlling the Compilation Driver, `gcc'.  */
  26
  27 #undef  STARTFILE_SPEC
  28 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
  29
  30 #undef  ENDFILE_SPEC
  31 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  32
  33 #undef  LINK_SPEC
  34 #define LINK_SPEC "%{h*} %{v:-V} \
  35                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  36
  37 /* There are four CPU series we support, but they basically break down
  38    into two families - the R8C/M16C families, with 16-bit address
  39    registers and one set of opcodes, and the M32CM/M32C group, with
  40    24-bit address registers and a different set of opcodes.  The
  41    assembler doesn't care except for which opcode set is needed; the
  42    big difference is in the memory maps, which we cover in
  43    LIB_SPEC.  */
  44
  45 #undef  ASM_SPEC
  46 #define ASM_SPEC "\
  47 %{mcpu=r8c:--m16c} \
  48 %{mcpu=m16c:--m16c} \
  49 %{mcpu=m32cm:--m32c} \
  50 %{mcpu=m32c:--m32c} "
  51
  52 /* The default is R8C hardware.  We support a simulator, which has its
  53    own libgloss and link map, plus one default link map for each chip
  54    family.  Most of the logic here is making sure we do the right
  55    thing when no CPU is specified, which defaults to R8C.  */
  56 #undef  LIB_SPEC
  57 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:-lnosys} -) \
  58 %{msim:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \
  59        %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \
  60 %{!T*:%{!msim: %{mcpu=m16c:%Tm16c.ld} \
  61                %{mcpu=m32cm:%Tm32cm.ld} \
  62                %{mcpu=m32c:%Tm32c.ld} \
  63                %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \
  64 "
  65
  66 /* Run-time Target Specification */
  67
  68 /* Nothing unusual here.  */
  69 #define TARGET_CPU_CPP_BUILTINS() \
  70   { \
  71     builtin_assert ("cpu=m32c"); \
  72     builtin_assert ("machine=m32c"); \
  73     builtin_define ("__m32c__=1"); \
  74     if (TARGET_R8C) \
  75       builtin_define ("__r8c_cpu__=1"); \
  76     if (TARGET_M16C) \
  77       builtin_define ("__m16c_cpu__=1"); \
  78     if (TARGET_M32CM) \
  79       builtin_define ("__m32cm_cpu__=1"); \
  80     if (TARGET_M32C) \
  81       builtin_define ("__m32c_cpu__=1"); \
  82   }
  83
  84 /* The pragma handlers need to know if we've started processing
  85    functions yet, as the memregs pragma should only be given at the
  86    beginning of the file.  This variable starts off TRUE and later
  87    becomes FALSE.  */
  88 extern int ok_to_change_target_memregs;
  89 extern int target_memregs;
  90
  91 /* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
  92    use enums or defines for this, this and m32c.opt are the only
  93    places that know (or care) what values are being used.  */
  94 #define TARGET_R8C      (target_cpu == 'r')
  95 #define TARGET_M16C     (target_cpu == '6')
  96 #define TARGET_M32CM    (target_cpu == 'm')
  97 #define TARGET_M32C     (target_cpu == '3')
  98
  99 /* Address register sizes.  Warning: these are used all over the place
 100    to select between the two CPU families in general.  */
 101 #define TARGET_A16      (TARGET_R8C || TARGET_M16C)
 102 #define TARGET_A24      (TARGET_M32CM || TARGET_M32C)
 103
 104 #define TARGET_VERSION fprintf (stderr, " (m32c)");
 105
 106 /* Defining data structures for per-function information */
 107
 108 typedef struct GTY (()) machine_function
 109 {
 110   /* How much we adjust the stack when returning from an exception
 111      handler.  */
 112   rtx eh_stack_adjust;
 113
 114   /* TRUE if the current function is an interrupt handler.  */
 115   int is_interrupt;
 116
 117   /* TRUE if the current function is a leaf function.  Currently, this
 118      only affects saving $a0 in interrupt functions.  */
 119   int is_leaf;
 120
 121   /* Bitmask that keeps track of which registers are used in an
 122      interrupt function, so we know which ones need to be saved and
 123      restored.  */
 124   int intr_pushm;
 125   /* Likewise, one element for each memreg that needs to be saved.  */
 126   char intr_pushmem[16];
 127
 128   /* TRUE if the current function can use a simple RTS to return, instead
 129      of the longer ENTER/EXIT pair.  */
 130   int use_rts;
 131 }
 132 machine_function;
 133
 134 #define INIT_EXPANDERS m32c_init_expanders ()
 135
 136 /* Storage Layout */
 137
 138 #define BITS_BIG_ENDIAN 0
 139 #define BYTES_BIG_ENDIAN 0
 140 #define WORDS_BIG_ENDIAN 0
 141
 142 /* We can do QI, HI, and SI operations pretty much equally well, but
 143    GCC expects us to have a "native" format, so we pick the one that
 144    matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
 145    is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
 146    24-bit pointers are stored in 32-bit words.  */
 147 #define BITS_PER_UNIT 8
 148 #define UNITS_PER_WORD 2
 149 #define POINTER_SIZE (TARGET_A16 ? 16 : 32)
 150 #define POINTERS_EXTEND_UNSIGNED 1
 151 /* We have a problem with libgcc2.  It only defines two versions of
 152    each function, one for "int" and one for "long long".  Ie it assumes
 153    that "sizeof (int) == sizeof (long)".  For the M32C this is not true
 154    and we need a third set of functions.  We explicitly define
 155    LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
 156    to get the SI and DI versions from the libgcc2.c sources, and we
 157    provide our own set of HI functions in m32c-lib2.c, which is why this
 158    definition is surrounded by #ifndef..#endif.  */
 159 #ifndef LIBGCC2_UNITS_PER_WORD
 160 #define LIBGCC2_UNITS_PER_WORD 4
 161 #endif
 162
 163 /* These match the alignment enforced by the two types of stack operations.  */
 164 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
 165 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
 166
 167 /* We do this because we care more about space than about speed.  For
 168    the chips with 16-bit busses, we could set these to 16 if
 169    desired.  */
 170 #define FUNCTION_BOUNDARY 8
 171 #define BIGGEST_ALIGNMENT 8
 172
 173 /* Since we have a maximum structure alignment of 8 there
 174    is no need to enforce any alignment of bitfield types.  */
 175 #undef  PCC_BITFIELD_TYPE_MATTERS
 176 #define PCC_BITFIELD_TYPE_MATTERS 0
 177
 178 #define STRICT_ALIGNMENT 0
 179 #define SLOW_BYTE_ACCESS 1
 180
 181 /* Layout of Source Language Data Types */
 182
 183 #define INT_TYPE_SIZE 16
 184 #define SHORT_TYPE_SIZE 16
 185 #define LONG_TYPE_SIZE 32
 186 #define LONG_LONG_TYPE_SIZE 64
 187
 188 #define FLOAT_TYPE_SIZE 32
 189 #define DOUBLE_TYPE_SIZE 64
 190 #define LONG_DOUBLE_TYPE_SIZE 64
 191
 192 #define DEFAULT_SIGNED_CHAR 1
 193
 194 #undef PTRDIFF_TYPE
 195 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
 196
 197 #undef UINTPTR_TYPE
 198 #define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int")
 199
 200 #undef  SIZE_TYPE
 201 #define SIZE_TYPE "unsigned int"
 202
 203 #undef  WCHAR_TYPE
 204 #define WCHAR_TYPE "long int"
 205
 206 #undef  WCHAR_TYPE_SIZE
 207 #define WCHAR_TYPE_SIZE BITS_PER_WORD
 208
 209 /* REGISTER USAGE */
 210
 211 /* Register Basics */
 212
 213 /* Register layout:
 214
 215         [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
 216         [--------]  $r2  (16 bits)
 217         [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
 218         [--------]  $r3  (16 bits)
 219    [---][--------]  $a0  (might be 24 bits)
 220    [---][--------]  $a1  (might be 24 bits)
 221    [---][--------]  $sb  (might be 24 bits)
 222    [---][--------]  $fb  (might be 24 bits)
 223    [---][--------]  $sp  (might be 24 bits)
 224    [-------------]  $pc  (20 or 24 bits)
 225              [---]  $flg (CPU flags)
 226    [---][--------]  $argp (virtual)
 227         [--------]  $mem0 (all 16 bits)
 228           . . .
 229         [--------]  $mem14
 230 */
 231
 232 #define FIRST_PSEUDO_REGISTER   20
 233
 234 /* Note that these two tables are modified based on which CPU family
 235    you select; see m32c_conditional_register_usage for details.  */
 236
 237 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
 238 #define FIXED_REGISTERS     { 0, 0, 0, 0, \
 239                               0, 0, 1, 0, \
 240                               1, 1, 0, 1, \
 241                               0, 0, 0, 0, 0, 0, 0, 0 }
 242 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
 243                               1, 1, 1, 0, \
 244                               1, 1, 1, 1, \
 245                               1, 1, 1, 1, 1, 1, 1, 1 }
 246
 247 /* The *_REGNO theme matches m32c.md and most register number
 248    arguments; the PC_REGNUM is the odd one out.  */
 249 #ifndef PC_REGNO
 250 #define PC_REGNO 9
 251 #endif
 252 #define PC_REGNUM PC_REGNO
 253
 254 /* Order of Allocation of Registers */
 255
 256 #define REG_ALLOC_ORDER { \
 257         0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
 258         12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */        \
 259         6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
 260
 261 /* How Values Fit in Registers */
 262
 263 #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M)
 264 #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M)
 265 #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2)
 266 #define AVOID_CCMODE_COPIES
 267
 268 /* Register Classes */
 269
 270 /* Most registers are special purpose in some form or another, so this
 271    table is pretty big.  Class names are used for constraints also;
 272    for example the HL_REGS class (HL below) is "Rhl" in the md files.
 273    See m32c_reg_class_from_constraint for the mapping.  There's some
 274    duplication so that we can better isolate the reason for using
 275    constraints in the md files from the actual registers used; for
 276    example we may want to exclude a1a0 from SI_REGS in the future,
 277    without precluding their use as HImode registers.  */
 278
 279 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
 280 /*       mmPAR */
 281 #define REG_CLASS_CONTENTS \
 282 { { 0x00000000 }, /* NO */\
 283   { 0x00000100 }, /* SP  - sp */\
 284   { 0x00000080 }, /* FB  - fb */\
 285   { 0x00000040 }, /* SB  - sb */\
 286   { 0x000001c0 }, /* CR  - sb fb sp */\
 287   { 0x00000001 }, /* R0  - r0 */\
 288   { 0x00000004 }, /* R1  - r1 */\
 289   { 0x00000002 }, /* R2  - r2 */\
 290   { 0x00000008 }, /* R3  - r3 */\
 291   { 0x00000003 }, /* R02 - r0r2 */\
 292   { 0x0000000c }, /* R13 - r1r3 */\
 293   { 0x00000005 }, /* HL  - r0 r1 */\
 294   { 0x00000005 }, /* QI  - r0 r1 */\
 295   { 0x0000000a }, /* R23 - r2 r3 */\
 296   { 0x0000000f }, /* R03 - r0r2 r1r3 */\
 297   { 0x0000000f }, /* DI  - r0r2r1r3 + mems */\
 298   { 0x00000010 }, /* A0  - a0 */\
 299   { 0x00000020 }, /* A1  - a1 */\
 300   { 0x00000030 }, /* A   - a0 a1 */\
 301   { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
 302   { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
 303   { 0x0000000f }, /* SI  - r0r2 r1r3 a0a1 */\
 304   { 0x0000003f }, /* HI  - r0 r1 r2 r3 a0 a1 */\
 305   { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
 306   { 0x0000003f }, /* RA  - r0..r3 a0 a1 */\
 307   { 0x0000007f }, /* GENERAL */\
 308   { 0x00000400 }, /* FLG */\
 309   { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
 310   { 0x000ff000 }, /* MEM */\
 311   { 0x000ff003 }, /* R02_A_MEM */\
 312   { 0x000ff005 }, /* A_HL_MEM */\
 313   { 0x000ff00c }, /* R1_R3_A_MEM */\
 314   { 0x000ff00f }, /* R03_MEM */\
 315   { 0x000ff03f }, /* A_HI_MEM */\
 316   { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
 317   { 0x000ff1ff }, /* ALL */\
 318 }
 319
 320 enum reg_class
 321 {
 322   NO_REGS,
 323   SP_REGS,
 324   FB_REGS,
 325   SB_REGS,
 326   CR_REGS,
 327   R0_REGS,
 328   R1_REGS,
 329   R2_REGS,
 330   R3_REGS,
 331   R02_REGS,
 332   R13_REGS,
 333   HL_REGS,
 334   QI_REGS,
 335   R23_REGS,
 336   R03_REGS,
 337   DI_REGS,
 338   A0_REGS,
 339   A1_REGS,
 340   A_REGS,
 341   AD_REGS,
 342   PS_REGS,
 343   SI_REGS,
 344   HI_REGS,
 345   R02A_REGS,
 346   RA_REGS,
 347   GENERAL_REGS,
 348   FLG_REGS,
 349   HC_REGS,
 350   MEM_REGS,
 351   R02_A_MEM_REGS,
 352   A_HL_MEM_REGS,
 353   R1_R3_A_MEM_REGS,
 354   R03_MEM_REGS,
 355   A_HI_MEM_REGS,
 356   A_AD_CR_MEM_SI_REGS,
 357   ALL_REGS,
 358   LIM_REG_CLASSES
 359 };
 360
 361 #define N_REG_CLASSES LIM_REG_CLASSES
 362
 363 #define REG_CLASS_NAMES {\
 364 "NO_REGS", \
 365 "SP_REGS", \
 366 "FB_REGS", \
 367 "SB_REGS", \
 368 "CR_REGS", \
 369 "R0_REGS", \
 370 "R1_REGS", \
 371 "R2_REGS", \
 372 "R3_REGS", \
 373 "R02_REGS", \
 374 "R13_REGS", \
 375 "HL_REGS", \
 376 "QI_REGS", \
 377 "R23_REGS", \
 378 "R03_REGS", \
 379 "DI_REGS", \
 380 "A0_REGS", \
 381 "A1_REGS", \
 382 "A_REGS", \
 383 "AD_REGS", \
 384 "PS_REGS", \
 385 "SI_REGS", \
 386 "HI_REGS", \
 387 "R02A_REGS", \
 388 "RA_REGS", \
 389 "GENERAL_REGS", \
 390 "FLG_REGS", \
 391 "HC_REGS", \
 392 "MEM_REGS", \
 393 "R02_A_MEM_REGS", \
 394 "A_HL_MEM_REGS", \
 395 "R1_R3_A_MEM_REGS", \
 396 "R03_MEM_REGS", \
 397 "A_HI_MEM_REGS", \
 398 "A_AD_CR_MEM_SI_REGS", \
 399 "ALL_REGS", \
 400 }
 401
 402 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
 403
 404 /* We support simple displacements off address registers, nothing else.  */
 405 #define BASE_REG_CLASS A_REGS
 406 #define INDEX_REG_CLASS NO_REGS
 407
 408 /* We primarily use the new "long" constraint names, with the initial
 409    letter classifying the constraint type and following letters
 410    specifying which.  The types are:
 411
 412    I - integer values
 413    R - register classes
 414    S - memory references (M was used)
 415    A - addresses (currently unused)
 416 */
 417
 418 #define CONSTRAINT_LEN(CHAR,STR) \
 419         ((CHAR) == 'I' ? 3 \
 420          : (CHAR) == 'R' ? 3 \
 421          : (CHAR) == 'S' ? 2 \
 422          : (CHAR) == 'A' ? 2 \
 423          : DEFAULT_CONSTRAINT_LEN(CHAR,STR))
 424 #define REG_CLASS_FROM_CONSTRAINT(CHAR,STR) \
 425         (enum reg_class) m32c_reg_class_from_constraint (CHAR, STR)
 426
 427 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
 428 #define REGNO_OK_FOR_INDEX_P(NUM) 0
 429
 430 #define PREFERRED_RELOAD_CLASS(X,CLASS) m32c_preferred_reload_class (X, CLASS)
 431 #define PREFERRED_OUTPUT_RELOAD_CLASS(X,CLASS) m32c_preferred_output_reload_class (X, CLASS)
 432 #define LIMIT_RELOAD_CLASS(MODE,CLASS) \
 433   (enum reg_class) m32c_limit_reload_class (MODE, CLASS)
 434
 435 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
 436   (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X)
 437
 438 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 439
 440 #define CLASS_MAX_NREGS(C,M) m32c_class_max_nregs (C, M)
 441
 442 #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C)
 443
 444 #define CONST_OK_FOR_CONSTRAINT_P(VALUE,C,STR) \
 445         m32c_const_ok_for_constraint_p (VALUE, C, STR)
 446 #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE,C,STR) 0
 447 #define EXTRA_CONSTRAINT_STR(VALUE,C,STR) \
 448         m32c_extra_constraint_p (VALUE, C, STR)
 449 #define EXTRA_MEMORY_CONSTRAINT(C,STR) \
 450         m32c_extra_memory_constraint (C, STR)
 451 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) \
 452         m32c_extra_address_constraint (C, STR)
 453
 454 /* STACK AND CALLING */
 455
 456 /* Frame Layout */
 457
 458 /* Standard push/pop stack, no surprises here.  */
 459
 460 #define STACK_GROWS_DOWNWARD 1
 461 #define STACK_PUSH_CODE PRE_DEC
 462 #define FRAME_GROWS_DOWNWARD 1
 463
 464 #define STARTING_FRAME_OFFSET 0
 465 #define FIRST_PARM_OFFSET(F) 0
 466
 467 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
 468
 469 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
 470 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
 471
 472 /* Exception Handling Support */
 473
 474 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
 475 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
 476
 477 /* Registers That Address the Stack Frame */
 478
 479 #ifndef FP_REGNO
 480 #define FP_REGNO 7
 481 #endif
 482 #ifndef SP_REGNO
 483 #define SP_REGNO 8
 484 #endif
 485 #define AP_REGNO 11
 486
 487 #define STACK_POINTER_REGNUM    SP_REGNO
 488 #define FRAME_POINTER_REGNUM    FP_REGNO
 489 #define ARG_POINTER_REGNUM      AP_REGNO
 490
 491 /* The static chain must be pointer-capable.  */
 492 #define STATIC_CHAIN_REGNUM A0_REGNO
 493
 494 #define DWARF_FRAME_REGISTERS 20
 495 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
 496 #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N)
 497
 498 #undef ASM_PREFERRED_EH_DATA_FORMAT
 499 /* This is the same as the default in practice, except that by making
 500    it explicit we tell binutils what size pointers to use.  */
 501 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 502   (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
 503
 504 /* Eliminating Frame Pointer and Arg Pointer */
 505
 506 #define ELIMINABLE_REGS \
 507   {{AP_REGNO, SP_REGNO}, \
 508    {AP_REGNO, FB_REGNO}, \
 509    {FB_REGNO, SP_REGNO}}
 510
 511 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
 512         (VAR) = m32c_initial_elimination_offset(FROM,TO)
 513
 514 /* Passing Function Arguments on the Stack */
 515
 516 #define PUSH_ARGS 1
 517 #define PUSH_ROUNDING(N) m32c_push_rounding (N)
 518 #define CALL_POPS_ARGS(C) 0
 519
 520 /* Passing Arguments in Registers */
 521
 522 typedef struct m32c_cumulative_args
 523 {
 524   /* For address of return value buffer (structures are returned by
 525      passing the address of a buffer as an invisible first argument.
 526      This identifies it).  If set, the current parameter will be put
 527      on the stack, regardless of type.  */
 528   int force_mem;
 529   /* First parm is 1, parm 0 is hidden pointer for returning
 530      aggregates.  */
 531   int parm_num;
 532 } m32c_cumulative_args;
 533
 534 #define CUMULATIVE_ARGS m32c_cumulative_args
 535 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
 536         m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
 537 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
 538
 539 /* How Large Values Are Returned */
 540
 541 #define DEFAULT_PCC_STRUCT_RETURN 1
 542
 543 /* Function Entry and Exit */
 544
 545 #define EXIT_IGNORE_STACK 0
 546 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
 547 #define EH_USES(REGNO) 0        /* FIXME */
 548
 549 /* Generating Code for Profiling */
 550
 551 #define FUNCTION_PROFILER(FILE,LABELNO)
 552
 553 /* Implementing the Varargs Macros */
 554
 555 /* Trampolines for Nested Functions */
 556
 557 #define TRAMPOLINE_SIZE m32c_trampoline_size ()
 558 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
 559
 560 /* Addressing Modes */
 561
 562 #define HAVE_PRE_DECREMENT 1
 563 #define HAVE_POST_INCREMENT 1
 564 #define MAX_REGS_PER_ADDRESS 1
 565
 566 /* This is passed to the macros below, so that they can be implemented
 567    in m32c.c.  */
 568 #ifdef REG_OK_STRICT
 569 #define REG_OK_STRICT_V 1
 570 #else
 571 #define REG_OK_STRICT_V 0
 572 #endif
 573
 574 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
 575 #define REG_OK_FOR_INDEX_P(X) 0
 576
 577 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
 578
 579 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
 580         if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
 581           goto WIN;
 582
 583 #define LEGITIMATE_CONSTANT_P(X) m32c_legitimate_constant_p (X)
 584
 585 /* Address spaces.  */
 586 #define ADDR_SPACE_FAR  1
 587
 588
 589 /* Condition Code Status */
 590
 591 #define REVERSIBLE_CC_MODE(MODE) 1
 592
 593 /* Dividing the Output into Sections (Texts, Data, ...) */
 594
 595 #define TEXT_SECTION_ASM_OP ".text"
 596 #define DATA_SECTION_ASM_OP ".data"
 597 #define BSS_SECTION_ASM_OP ".bss"
 598
 599 #define CTOR_LIST_BEGIN
 600 #define CTOR_LIST_END
 601 #define DTOR_LIST_BEGIN
 602 #define DTOR_LIST_END
 603 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 604 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 605 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 606 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 607
 608 /* The Overall Framework of an Assembler File */
 609
 610 #define ASM_COMMENT_START ";"
 611 #define ASM_APP_ON ""
 612 #define ASM_APP_OFF ""
 613
 614 /* Output and Generation of Labels */
 615
 616 #define GLOBAL_ASM_OP "\t.global\t"
 617
 618 /* Output of Assembler Instructions */
 619
 620 #define REGISTER_NAMES {        \
 621   "r0", "r2", "r1", "r3", \
 622   "a0", "a1", "sb", "fb", "sp", \
 623   "pc", "flg", "argp", \
 624   "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
 625 }
 626
 627 #define ADDITIONAL_REGISTER_NAMES { \
 628   {"r0l", 0}, \
 629   {"r1l", 2}, \
 630   {"r0r2", 0}, \
 631   {"r1r3", 2}, \
 632   {"a0a1", 4}, \
 633   {"r0r2r1r3", 0} }
 634
 635 #define PRINT_OPERAND(S,X,C) m32c_print_operand (S, X, C)
 636 #define PRINT_OPERAND_PUNCT_VALID_P(C) m32c_print_operand_punct_valid_p (C)
 637 #define PRINT_OPERAND_ADDRESS(S,X) m32c_print_operand_address (S, X)
 638
 639 #undef USER_LABEL_PREFIX
 640 #define USER_LABEL_PREFIX "_"
 641
 642 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
 643 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
 644
 645 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 646         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
 647
 648 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 649         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
 650
 651
 652 /* Output of Dispatch Tables */
 653
 654 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
 655         fprintf (S, "\t.word L%d\n", V)
 656
 657 /* Assembler Commands for Exception Regions */
 658
 659 #define DWARF_CIE_DATA_ALIGNMENT -1
 660
 661 /* Assembler Commands for Alignment */
 662
 663 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 664         fprintf (STREAM, "\t.p2align\t%d\n", POWER);
 665
 666 /* Controlling Debugging Information Format */
 667
 668 #define DWARF2_ADDR_SIZE        4
 669
 670 /* Miscellaneous Parameters */
 671
 672 #define HAS_LONG_COND_BRANCH false
 673 #define HAS_LONG_UNCOND_BRANCH true
 674 #define CASE_VECTOR_MODE SImode
 675 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
 676
 677 #define MOVE_MAX 4
 678 #define TRULY_NOOP_TRUNCATION(op,ip) 1
 679
 680 #define STORE_FLAG_VALUE 1
 681
 682 /* 16- or 24-bit pointers */
 683 #define Pmode (TARGET_A16 ? HImode : PSImode)
 684 #define FUNCTION_MODE QImode
 685
 686 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
 687
 688 #endif