gcc/config/m32c/m32c.h

   1 /* Target Definitions for R8C/M16C/M32C
   2    Copyright (C) 2005-2024 Free Software Foundation, Inc.
   3    Contributed by Red Hat.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef GCC_M32C_H
  22 #define GCC_M32C_H
  23
  24 /* Controlling the Compilation Driver, `gcc'.  */
  25
  26 #undef  STARTFILE_SPEC
  27 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s"
  28
  29 #undef  ENDFILE_SPEC
  30 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
  31
  32 #undef  LINK_SPEC
  33 #define LINK_SPEC "%{h*} %{v:-V} \
  34                    %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}"
  35
  36 /* There are four CPU series we support, but they basically break down
  37    into two families - the R8C/M16C families, with 16-bit address
  38    registers and one set of opcodes, and the M32CM/M32C group, with
  39    24-bit address registers and a different set of opcodes.  The
  40    assembler doesn't care except for which opcode set is needed; the
  41    big difference is in the memory maps, which we cover in
  42    LIB_SPEC.  */
  43
  44 #undef  ASM_SPEC
  45 #define ASM_SPEC "\
  46 %{mcpu=r8c:--m16c} \
  47 %{mcpu=m16c:--m16c} \
  48 %{mcpu=m32cm:--m32c} \
  49 %{mcpu=m32c:--m32c} "
  50
  51 /* The default is R8C hardware.  We support a simulator, which has its
  52    own libgloss and link map, plus one default link map for each chip
  53    family.  Most of the logic here is making sure we do the right
  54    thing when no CPU is specified, which defaults to R8C.  */
  55 #undef  LIB_SPEC
  56 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:-lnosys} -) \
  57 %{msim:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \
  58        %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \
  59 %{!T*:%{!msim: %{mcpu=m16c:%Tm16c.ld} \
  60                %{mcpu=m32cm:%Tm32cm.ld} \
  61                %{mcpu=m32c:%Tm32c.ld} \
  62                %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \
  63 "
  64
  65 /* Run-time Target Specification */
  66
  67 /* Nothing unusual here.  */
  68 #define TARGET_CPU_CPP_BUILTINS() \
  69   { \
  70     builtin_assert ("cpu=m32c"); \
  71     builtin_assert ("machine=m32c"); \
  72     builtin_define ("__m32c__=1"); \
  73     if (TARGET_R8C) \
  74       builtin_define ("__r8c_cpu__=1"); \
  75     if (TARGET_M16C) \
  76       builtin_define ("__m16c_cpu__=1"); \
  77     if (TARGET_M32CM) \
  78       builtin_define ("__m32cm_cpu__=1"); \
  79     if (TARGET_M32C) \
  80       builtin_define ("__m32c_cpu__=1"); \
  81   }
  82
  83 /* The pragma handlers need to know if we've started processing
  84    functions yet, as the memregs pragma should only be given at the
  85    beginning of the file.  This variable starts off TRUE and later
  86    becomes FALSE.  */
  87 extern int ok_to_change_target_memregs;
  88
  89 /* TARGET_CPU is a multi-way option set in m32c.opt.  While we could
  90    use enums or defines for this, this and m32c.opt are the only
  91    places that know (or care) what values are being used.  */
  92 #define TARGET_R8C      (target_cpu == 'r')
  93 #define TARGET_M16C     (target_cpu == '6')
  94 #define TARGET_M32CM    (target_cpu == 'm')
  95 #define TARGET_M32C     (target_cpu == '3')
  96
  97 /* Address register sizes.  Warning: these are used all over the place
  98    to select between the two CPU families in general.  */
  99 #define TARGET_A16      (TARGET_R8C || TARGET_M16C)
 100 #define TARGET_A24      (TARGET_M32CM || TARGET_M32C)
 101
 102 /* Defining data structures for per-function information */
 103
 104 typedef struct GTY (()) machine_function
 105 {
 106   /* How much we adjust the stack when returning from an exception
 107      handler.  */
 108   rtx eh_stack_adjust;
 109
 110   /* TRUE if the current function is an interrupt handler.  */
 111   int is_interrupt;
 112
 113   /* TRUE if the current function is a leaf function.  Currently, this
 114      only affects saving $a0 in interrupt functions.  */
 115   int is_leaf;
 116
 117   /* Bitmask that keeps track of which registers are used in an
 118      interrupt function, so we know which ones need to be saved and
 119      restored.  */
 120   int intr_pushm;
 121   /* Likewise, one element for each memreg that needs to be saved.  */
 122   char intr_pushmem[16];
 123
 124   /* TRUE if the current function can use a simple RTS to return, instead
 125      of the longer ENTER/EXIT pair.  */
 126   int use_rts;
 127 }
 128 machine_function;
 129
 130 #define INIT_EXPANDERS m32c_init_expanders ()
 131
 132 /* Storage Layout */
 133
 134 #define BITS_BIG_ENDIAN 0
 135 #define BYTES_BIG_ENDIAN 0
 136 #define WORDS_BIG_ENDIAN 0
 137
 138 /* We can do QI, HI, and SI operations pretty much equally well, but
 139    GCC expects us to have a "native" format, so we pick the one that
 140    matches "int".  Pointers are 16 bits for R8C/M16C (when TARGET_A16
 141    is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but
 142    24-bit pointers are stored in 32-bit words.  */
 143 #define UNITS_PER_WORD 2
 144 #define POINTER_SIZE (TARGET_A16 ? 16 : 32)
 145 #define POINTERS_EXTEND_UNSIGNED 1
 146 /* We have a problem with libgcc2.  It only defines two versions of
 147    each function, one for "int" and one for "long long".  Ie it assumes
 148    that "sizeof (int) == sizeof (long)".  For the M32C this is not true
 149    and we need a third set of functions.  We explicitly define
 150    LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting
 151    to get the SI and DI versions from the libgcc2.c sources, and we
 152    provide our own set of HI functions in m32c-lib2.c, which is why this
 153    definition is surrounded by #ifndef..#endif.  */
 154 #ifndef LIBGCC2_UNITS_PER_WORD
 155 #define LIBGCC2_UNITS_PER_WORD 4
 156 #endif
 157
 158 /* These match the alignment enforced by the two types of stack operations.  */
 159 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16)
 160 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16)
 161
 162 /* We do this because we care more about space than about speed.  For
 163    the chips with 16-bit busses, we could set these to 16 if
 164    desired.  */
 165 #define FUNCTION_BOUNDARY 8
 166 #define BIGGEST_ALIGNMENT 8
 167
 168 /* Since we have a maximum structure alignment of 8 there
 169    is no need to enforce any alignment of bitfield types.  */
 170 #undef  PCC_BITFIELD_TYPE_MATTERS
 171 #define PCC_BITFIELD_TYPE_MATTERS 0
 172
 173 #define STRICT_ALIGNMENT 0
 174 #define SLOW_BYTE_ACCESS 1
 175
 176 /* Layout of Source Language Data Types */
 177
 178 #define INT_TYPE_SIZE 16
 179 #define SHORT_TYPE_SIZE 16
 180 #define LONG_TYPE_SIZE 32
 181 #define LONG_LONG_TYPE_SIZE 64
 182
 183 #define DEFAULT_SIGNED_CHAR 1
 184
 185 #undef PTRDIFF_TYPE
 186 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int")
 187
 188 #undef UINTPTR_TYPE
 189 #define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int")
 190
 191 #undef  SIZE_TYPE
 192 #define SIZE_TYPE "unsigned int"
 193
 194 #undef  WCHAR_TYPE
 195 #define WCHAR_TYPE "long int"
 196
 197 #undef  WCHAR_TYPE_SIZE
 198 #define WCHAR_TYPE_SIZE 32
 199
 200 /* REGISTER USAGE */
 201
 202 /* Register Basics */
 203
 204 /* Register layout:
 205
 206         [r0h][r0l]  $r0  (16 bits, or two 8-bit halves)
 207         [--------]  $r2  (16 bits)
 208         [r1h][r1l]  $r1  (16 bits, or two 8-bit halves)
 209         [--------]  $r3  (16 bits)
 210    [---][--------]  $a0  (might be 24 bits)
 211    [---][--------]  $a1  (might be 24 bits)
 212    [---][--------]  $sb  (might be 24 bits)
 213    [---][--------]  $fb  (might be 24 bits)
 214    [---][--------]  $sp  (might be 24 bits)
 215    [-------------]  $pc  (20 or 24 bits)
 216              [---]  $flg (CPU flags)
 217    [---][--------]  $argp (virtual)
 218         [--------]  $mem0 (all 16 bits)
 219           . . .
 220         [--------]  $mem14
 221 */
 222
 223 #define FIRST_PSEUDO_REGISTER   20
 224
 225 /* Note that these two tables are modified based on which CPU family
 226    you select; see m32c_conditional_register_usage for details.  */
 227
 228 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */
 229 #define FIXED_REGISTERS     { 0, 0, 0, 0, \
 230                               0, 0, 1, 0, \
 231                               1, 1, 0, 1, \
 232                               0, 0, 0, 0, 0, 0, 0, 0 }
 233 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \
 234                               1, 1, 1, 0, \
 235                               1, 1, 1, 1, \
 236                               1, 1, 1, 1, 1, 1, 1, 1 }
 237
 238 /* The *_REGNO theme matches m32c.md and most register number
 239    arguments; the PC_REGNUM is the odd one out.  */
 240 #ifndef PC_REGNO
 241 #define PC_REGNO 9
 242 #endif
 243 #define PC_REGNUM PC_REGNO
 244
 245 /* Order of Allocation of Registers */
 246
 247 #define REG_ALLOC_ORDER { \
 248         0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \
 249         12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */        \
 250         6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ }
 251
 252 /* How Values Fit in Registers */
 253
 254 #define AVOID_CCMODE_COPIES
 255
 256 /* Register Classes */
 257
 258 /* Most registers are special purpose in some form or another, so this
 259    table is pretty big.  Class names are used for constraints also;
 260    for example the HL_REGS class (HL below) is "Rhl" in the md files.
 261    See m32c_reg_class_from_constraint for the mapping.  There's some
 262    duplication so that we can better isolate the reason for using
 263    constraints in the md files from the actual registers used; for
 264    example we may want to exclude a1a0 from SI_REGS in the future,
 265    without precluding their use as HImode registers.  */
 266
 267 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */
 268 /*       mmPAR */
 269 #define REG_CLASS_CONTENTS \
 270 { { 0x00000000 }, /* NO */\
 271   { 0x00000100 }, /* SP  - sp */\
 272   { 0x00000080 }, /* FB  - fb */\
 273   { 0x00000040 }, /* SB  - sb */\
 274   { 0x000001c0 }, /* CR  - sb fb sp */\
 275   { 0x00000001 }, /* R0  - r0 */\
 276   { 0x00000004 }, /* R1  - r1 */\
 277   { 0x00000002 }, /* R2  - r2 */\
 278   { 0x00000008 }, /* R3  - r3 */\
 279   { 0x00000003 }, /* R02 - r0r2 */\
 280   { 0x0000000c }, /* R13 - r1r3 */\
 281   { 0x00000005 }, /* HL  - r0 r1 */\
 282   { 0x0000000a }, /* R23 - r2 r3 */\
 283   { 0x0000000f }, /* R03 - r0r2 r1r3 */\
 284   { 0x00000010 }, /* A0  - a0 */\
 285   { 0x00000020 }, /* A1  - a1 */\
 286   { 0x00000030 }, /* A   - a0 a1 */\
 287   { 0x000000f0 }, /* AD  - a0 a1 sb fp */\
 288   { 0x000001f0 }, /* PS  - a0 a1 sb fp sp */\
 289   { 0x00000033 }, /* R02A  - r0r2 a0 a1 */ \
 290   { 0x0000003f }, /* RA  - r0 r1 r2 r3 a0 a1 */\
 291   { 0x0000007f }, /* GENERAL */\
 292   { 0x00000400 }, /* FLG */\
 293   { 0x000001ff }, /* HC  - r0l r1 r2 r3 a0 a1 sb fb sp */\
 294   { 0x000ff000 }, /* MEM */\
 295   { 0x000ff003 }, /* R02_A_MEM */\
 296   { 0x000ff005 }, /* A_HL_MEM */\
 297   { 0x000ff00c }, /* R1_R3_A_MEM */\
 298   { 0x000ff00f }, /* R03_MEM */\
 299   { 0x000ff03f }, /* A_HI_MEM */\
 300   { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\
 301   { 0x000ff5ff }, /* ALL */\
 302 }
 303
 304 #define QI_REGS HL_REGS
 305 #define HI_REGS RA_REGS
 306 #define SI_REGS R03_REGS
 307 #define DI_REGS R03_REGS
 308
 309 enum reg_class
 310 {
 311   NO_REGS,
 312   SP_REGS,
 313   FB_REGS,
 314   SB_REGS,
 315   CR_REGS,
 316   R0_REGS,
 317   R1_REGS,
 318   R2_REGS,
 319   R3_REGS,
 320   R02_REGS,
 321   R13_REGS,
 322   HL_REGS,
 323   R23_REGS,
 324   R03_REGS,
 325   A0_REGS,
 326   A1_REGS,
 327   A_REGS,
 328   AD_REGS,
 329   PS_REGS,
 330   R02A_REGS,
 331   RA_REGS,
 332   GENERAL_REGS,
 333   FLG_REGS,
 334   HC_REGS,
 335   MEM_REGS,
 336   R02_A_MEM_REGS,
 337   A_HL_MEM_REGS,
 338   R1_R3_A_MEM_REGS,
 339   R03_MEM_REGS,
 340   A_HI_MEM_REGS,
 341   A_AD_CR_MEM_SI_REGS,
 342   ALL_REGS,
 343   LIM_REG_CLASSES
 344 };
 345
 346 #define N_REG_CLASSES LIM_REG_CLASSES
 347
 348 #define REG_CLASS_NAMES {\
 349 "NO_REGS", \
 350 "SP_REGS", \
 351 "FB_REGS", \
 352 "SB_REGS", \
 353 "CR_REGS", \
 354 "R0_REGS", \
 355 "R1_REGS", \
 356 "R2_REGS", \
 357 "R3_REGS", \
 358 "R02_REGS", \
 359 "R13_REGS", \
 360 "HL_REGS", \
 361 "R23_REGS", \
 362 "R03_REGS", \
 363 "A0_REGS", \
 364 "A1_REGS", \
 365 "A_REGS", \
 366 "AD_REGS", \
 367 "PS_REGS", \
 368 "R02A_REGS", \
 369 "RA_REGS", \
 370 "GENERAL_REGS", \
 371 "FLG_REGS", \
 372 "HC_REGS", \
 373 "MEM_REGS", \
 374 "R02_A_MEM_REGS", \
 375 "A_HL_MEM_REGS", \
 376 "R1_R3_A_MEM_REGS", \
 377 "R03_MEM_REGS", \
 378 "A_HI_MEM_REGS", \
 379 "A_AD_CR_MEM_SI_REGS", \
 380 "ALL_REGS", \
 381 }
 382
 383 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R)
 384
 385 /* We support simple displacements off address registers, nothing else.  */
 386 #define BASE_REG_CLASS A_REGS
 387 #define INDEX_REG_CLASS NO_REGS
 388
 389 /* We primarily use the new "long" constraint names, with the initial
 390    letter classifying the constraint type and following letters
 391    specifying which.  The types are:
 392
 393    I - integer values
 394    R - register classes
 395    S - memory references (M was used)
 396    A - addresses (currently unused)
 397 */
 398
 399 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM)
 400 #define REGNO_OK_FOR_INDEX_P(NUM) 0
 401
 402 #define LIMIT_RELOAD_CLASS(MODE,CLASS) \
 403   (enum reg_class) m32c_limit_reload_class (MODE, CLASS)
 404
 405 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \
 406   (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X)
 407
 408 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
 409
 410 /* STACK AND CALLING */
 411
 412 /* Frame Layout */
 413
 414 /* Standard push/pop stack, no surprises here.  */
 415
 416 #define STACK_GROWS_DOWNWARD 1
 417 #define STACK_PUSH_CODE PRE_DEC
 418 #define FRAME_GROWS_DOWNWARD 1
 419
 420 #define FIRST_PARM_OFFSET(F) 0
 421
 422 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT)
 423
 424 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx()
 425 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3)
 426
 427 /* Exception Handling Support */
 428
 429 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N)
 430 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx ()
 431
 432 /* Registers That Address the Stack Frame */
 433
 434 #ifndef FP_REGNO
 435 #define FP_REGNO 7
 436 #endif
 437 #ifndef SP_REGNO
 438 #define SP_REGNO 8
 439 #endif
 440 #define AP_REGNO 11
 441
 442 #define STACK_POINTER_REGNUM    SP_REGNO
 443 #define FRAME_POINTER_REGNUM    FP_REGNO
 444 #define ARG_POINTER_REGNUM      AP_REGNO
 445
 446 /* The static chain must be pointer-capable.  */
 447 #define STATIC_CHAIN_REGNUM A0_REGNO
 448
 449 #define DWARF_FRAME_REGISTERS 20
 450 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N)
 451 #define DEBUGGER_REGNO(N) m32c_dwarf_frame_regnum (N)
 452
 453 #undef ASM_PREFERRED_EH_DATA_FORMAT
 454 /* This is the same as the default in practice, except that by making
 455    it explicit we tell binutils what size pointers to use.  */
 456 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 457   (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4)
 458
 459 /* Eliminating Frame Pointer and Arg Pointer */
 460
 461 #define ELIMINABLE_REGS \
 462   {{AP_REGNO, SP_REGNO}, \
 463    {AP_REGNO, FB_REGNO}, \
 464    {FB_REGNO, SP_REGNO}}
 465
 466 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \
 467         (VAR) = m32c_initial_elimination_offset(FROM,TO)
 468
 469 /* Passing Function Arguments on the Stack */
 470
 471 #define PUSH_ROUNDING(N) m32c_push_rounding (N)
 472 #define CALL_POPS_ARGS(C) 0
 473
 474 /* Passing Arguments in Registers */
 475
 476 typedef struct m32c_cumulative_args
 477 {
 478   /* For address of return value buffer (structures are returned by
 479      passing the address of a buffer as an invisible first argument.
 480      This identifies it).  If set, the current parameter will be put
 481      on the stack, regardless of type.  */
 482   int force_mem;
 483   /* First parm is 1, parm 0 is hidden pointer for returning
 484      aggregates.  */
 485   int parm_num;
 486 } m32c_cumulative_args;
 487
 488 #define CUMULATIVE_ARGS m32c_cumulative_args
 489 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
 490         m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS)
 491 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r)
 492
 493 /* How Large Values Are Returned */
 494
 495 #define DEFAULT_PCC_STRUCT_RETURN 1
 496
 497 /* Function Entry and Exit */
 498
 499 #define EXIT_IGNORE_STACK 0
 500 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO)
 501 #define EH_USES(REGNO) 0        /* FIXME */
 502
 503 /* Generating Code for Profiling */
 504
 505 #define FUNCTION_PROFILER(FILE,LABELNO)
 506
 507 /* Implementing the Varargs Macros */
 508
 509 /* Trampolines for Nested Functions */
 510
 511 #define TRAMPOLINE_SIZE m32c_trampoline_size ()
 512 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment ()
 513
 514 /* Addressing Modes */
 515
 516 #define HAVE_PRE_DECREMENT 1
 517 #define HAVE_POST_INCREMENT 1
 518 #define MAX_REGS_PER_ADDRESS 1
 519
 520 /* This is passed to the macros below, so that they can be implemented
 521    in m32c.cc.  */
 522 #ifdef REG_OK_STRICT
 523 #define REG_OK_STRICT_V 1
 524 #else
 525 #define REG_OK_STRICT_V 0
 526 #endif
 527
 528 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V)
 529 #define REG_OK_FOR_INDEX_P(X) 0
 530
 531 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */
 532
 533 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
 534         if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \
 535           goto WIN;
 536
 537 /* Address spaces.  */
 538 #define ADDR_SPACE_FAR  1
 539
 540
 541 /* Condition Code Status */
 542
 543 #define REVERSIBLE_CC_MODE(MODE) 1
 544
 545 /* Dividing the Output into Sections (Texts, Data, ...) */
 546
 547 #define TEXT_SECTION_ASM_OP ".text"
 548 #define DATA_SECTION_ASM_OP ".data"
 549 #define BSS_SECTION_ASM_OP ".bss"
 550
 551 #define CTOR_LIST_BEGIN
 552 #define CTOR_LIST_END
 553 #define DTOR_LIST_BEGIN
 554 #define DTOR_LIST_END
 555 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 556 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 557 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array"
 558 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array"
 559
 560 /* The Overall Framework of an Assembler File */
 561
 562 #define ASM_COMMENT_START ";"
 563 #define ASM_APP_ON ""
 564 #define ASM_APP_OFF ""
 565
 566 /* Output and Generation of Labels */
 567
 568 #define GLOBAL_ASM_OP "\t.global\t"
 569
 570 /* Output of Assembler Instructions */
 571
 572 #define REGISTER_NAMES {        \
 573   "r0", "r2", "r1", "r3", \
 574   "a0", "a1", "sb", "fb", "sp", \
 575   "pc", "flg", "argp", \
 576   "mem0",  "mem2",  "mem4",  "mem6",  "mem8",  "mem10",  "mem12",  "mem14", \
 577 }
 578
 579 #define ADDITIONAL_REGISTER_NAMES { \
 580   {"r0l", 0}, \
 581   {"r1l", 2}, \
 582   {"r0r2", 0}, \
 583   {"r1r3", 2}, \
 584   {"a0a1", 4}, \
 585   {"r0r2r1r3", 0} }
 586
 587 #undef USER_LABEL_PREFIX
 588 #define USER_LABEL_PREFIX "_"
 589
 590 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R)
 591 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R)
 592
 593 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 594         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1)
 595
 596 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
 597         m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0)
 598
 599
 600 /* Output of Dispatch Tables */
 601
 602 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \
 603         fprintf (S, "\t.word L%d\n", V)
 604
 605 /* Assembler Commands for Exception Regions */
 606
 607 #define DWARF_CIE_DATA_ALIGNMENT -1
 608
 609 /* Assembler Commands for Alignment */
 610
 611 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \
 612         fprintf (STREAM, "\t.p2align\t%d\n", POWER);
 613
 614 /* Controlling Debugging Information Format */
 615
 616 #define DWARF2_ADDR_SIZE        4
 617
 618 /* Miscellaneous Parameters */
 619
 620 #define HAS_LONG_COND_BRANCH false
 621 #define HAS_LONG_UNCOND_BRANCH true
 622 #define CASE_VECTOR_MODE SImode
 623 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND
 624
 625 #define MOVE_MAX 4
 626
 627 #define STORE_FLAG_VALUE 1
 628
 629 /* 16- or 24-bit pointers */
 630 #define Pmode (TARGET_A16 ? HImode : PSImode)
 631 #define FUNCTION_MODE QImode
 632
 633 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas()
 634
 635 #endif