?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
* config/mips/mips-protos.h (mips16_gp_pseudo_reg): Remove.
[official-gcc.git] / gcc / config / mips / mips.h
blob30ddcc41d1505f3d24314fb895bc9ee2e7b46d0d
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* comparison type */
34 enum cmp_type {
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
40 };
41
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
46
47 enum processor_type {
48 PROCESSOR_DEFAULT,
49 PROCESSOR_4KC,
50 PROCESSOR_5KC,
51 PROCESSOR_20KC,
52 PROCESSOR_M4K,
53 PROCESSOR_R3000,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4300,
61 PROCESSOR_R4600,
62 PROCESSOR_R4650,
63 PROCESSOR_R5000,
64 PROCESSOR_R5400,
65 PROCESSOR_R5500,
66 PROCESSOR_R7000,
67 PROCESSOR_R8000,
68 PROCESSOR_R9000,
69 PROCESSOR_SB1,
70 PROCESSOR_SR71000
71 };
72
73 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
74 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
75 to work on a 64 bit machine. */
76
77 #define ABI_32 0
78 #define ABI_N32 1
79 #define ABI_64 2
80 #define ABI_EABI 3
81 #define ABI_O64 4
82
83 /* Information about one recognized processor. Defined here for the
84 benefit of TARGET_CPU_CPP_BUILTINS. */
85 struct mips_cpu_info {
86 /* The 'canonical' name of the processor as far as GCC is concerned.
87 It's typically a manufacturer's prefix followed by a numerical
88 designation. It should be lower case. */
89 const char *name;
90
91 /* The internal processor number that most closely matches this
92 entry. Several processors can have the same value, if there's no
93 difference between them from GCC's point of view. */
94 enum processor_type cpu;
95
96 /* The ISA level that the processor implements. */
97 int isa;
98 };
99
100 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern int mips_entry; /* generate entry/exit for mips16 */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_entry_string; /* for -mentry */
125 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
126 extern int mips_string_length; /* length of strings for mips16 */
127 extern const struct mips_cpu_info mips_cpu_info_table[];
128 extern const struct mips_cpu_info *mips_arch_info;
129 extern const struct mips_cpu_info *mips_tune_info;
130
131 /* Macros to silence warnings about numbers being signed in traditional
132 C and unsigned in ISO C when compiled on 32-bit hosts. */
133
134 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
135 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
136 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
137
138 \f
139 /* Run-time compilation parameters selecting different hardware subsets. */
140
141 /* Macros used in the machine description to test the flags. */
142
143 /* Bits for real switches */
144 #define MASK_INT64 0x00000001 /* ints are 64 bits */
145 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
146 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
147 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
148 multiply-add operations. */
149 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
150 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
151 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
152 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
153 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
154 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
155 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
156 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
157 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
158 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
159 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
160 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
161 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
162 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
163 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
164 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
165 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
166 #define MASK_NO_CHECK_ZERO_DIV \
167 0x00200000 /* divide by zero checking */
168 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
169 instructions. */
170 #define MASK_UNINIT_CONST_IN_RODATA \
171 0x00800000 /* Store uninitialized
172 consts in rodata */
173 #define MASK_FIX_SB1 0x01000000 /* Work around SB-1 errata. */
174
175 /* Debug switches, not documented */
176 #define MASK_DEBUG 0 /* unused */
177 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
178 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
179 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
180 #define MASK_DEBUG_D 0 /* don't do define_split's */
181 #define MASK_DEBUG_E 0 /* function_arg debug */
182 #define MASK_DEBUG_F 0 /* ??? */
183 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
184 #define MASK_DEBUG_I 0 /* unused */
185
186 /* Dummy switches used only in specs */
187 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
188
189 /* r4000 64 bit sizes */
190 #define TARGET_INT64 (target_flags & MASK_INT64)
191 #define TARGET_LONG64 (target_flags & MASK_LONG64)
192 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
193 #define TARGET_64BIT (target_flags & MASK_64BIT)
194
195 /* Mips vs. GNU linker */
196 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
197
198 /* Mips vs. GNU assembler */
199 #define TARGET_GAS (target_flags & MASK_GAS)
200 #define TARGET_MIPS_AS (!TARGET_GAS)
201
202 /* Debug Modes */
203 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
204 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
205 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
206 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
207 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
208 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
209 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
210 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
211 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
212
213 /* Reg. Naming in .s ($21 vs. $a0) */
214 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
215
216 /* call memcpy instead of inline code */
217 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
218
219 /* .abicalls, etc from Pyramid V.4 */
220 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
221 #define TARGET_XGOT (target_flags & MASK_XGOT)
222
223 /* software floating point */
224 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
225 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
226
227 /* always call through a register */
228 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
229
230 /* generate embedded PIC code;
231 requires gas. */
232 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
233
234 /* for embedded systems, optimize for
235 reduced RAM space instead of for
236 fastest code. */
237 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
238
239 /* always store uninitialized const
240 variables in rodata, requires
241 TARGET_EMBEDDED_DATA. */
242 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
243
244 /* generate big endian code. */
245 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
246
247 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
248 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
249
250 #define TARGET_MAD (target_flags & MASK_MAD)
251
252 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
253
254 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
255
256 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
257
258 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
259
260 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
261
262 /* True if we should use NewABI-style relocation operators for
263 symbolic addresses. This is never true for mips16 code,
264 which has its own conventions. */
265
266 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
267
268
269 /* True if the call patterns should be split into a jalr followed by
270 an instruction to restore $gp. This is only ever true for SVR4 PIC,
271 in which $gp is call-clobbered. It is only safe to split the load
272 from the call when every use of $gp is explicit. */
273
274 #define TARGET_SPLIT_CALLS \
275 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
276
277 /* True if we can optimize sibling calls. For simplicity, we only
278 handle cases in which call_insn_operand will reject invalid
279 sibcall addresses. There are two cases in which this isn't true:
280
281 - TARGET_MIPS16. call_insn_operand accepts constant addresses
282 but there is no direct jump instruction. It isn't worth
283 using sibling calls in this case anyway; they would usually
284 be longer than normal calls.
285
286 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
287 accepts global constants, but "jr $25" is the only allowed
288 sibcall. */
289
290 #define TARGET_SIBCALLS \
291 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
292
293 /* True if .gpword or .gpdword should be used for switch tables.
294 Not all SGI assemblers support this. */
295
296 #define TARGET_GPWORD (TARGET_ABICALLS && (!TARGET_NEWABI || TARGET_GAS))
297
298 /* Generate mips16 code */
299 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
300
301 /* Generic ISA defines. */
302 #define ISA_MIPS1 (mips_isa == 1)
303 #define ISA_MIPS2 (mips_isa == 2)
304 #define ISA_MIPS3 (mips_isa == 3)
305 #define ISA_MIPS4 (mips_isa == 4)
306 #define ISA_MIPS32 (mips_isa == 32)
307 #define ISA_MIPS32R2 (mips_isa == 33)
308 #define ISA_MIPS64 (mips_isa == 64)
309
310 /* Architecture target defines. */
311 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
312 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
313 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
314 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
315 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
316 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_4KC)
317 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_5KC)
318 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
319 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
320 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
321 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
322 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
323 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
324
325 /* Scheduling target defines. */
326 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
327 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
328 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
329 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
330 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
331 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
332 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
333 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
334 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
335 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
336 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
337
338 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
339
340 /* Define preprocessor macros for the -march and -mtune options.
341 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
342 processor. If INFO's canonical name is "foo", define PREFIX to
343 be "foo", and define an additional macro PREFIX_FOO. */
344 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
345 do \
346 { \
347 char *macro, *p; \
348 \
349 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
350 for (p = macro; *p != 0; p++) \
351 *p = TOUPPER (*p); \
352 \
353 builtin_define (macro); \
354 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
355 free (macro); \
356 } \
357 while (0)
358
359 /* Target CPU builtins. */
360 #define TARGET_CPU_CPP_BUILTINS() \
361 do \
362 { \
363 builtin_assert ("cpu=mips"); \
364 builtin_define ("__mips__"); \
365 builtin_define ("_mips"); \
366 \
367 /* We do this here because __mips is defined below \
368 and so we can't use builtin_define_std. */ \
369 if (!flag_iso) \
370 builtin_define ("mips"); \
371 \
372 /* Treat _R3000 and _R4000 like register-size defines, \
373 which is how they've historically been used. */ \
374 if (TARGET_64BIT) \
375 { \
376 builtin_define ("__mips64"); \
377 builtin_define_std ("R4000"); \
378 builtin_define ("_R4000"); \
379 } \
380 else \
381 { \
382 builtin_define_std ("R3000"); \
383 builtin_define ("_R3000"); \
384 } \
385 if (TARGET_FLOAT64) \
386 builtin_define ("__mips_fpr=64"); \
387 else \
388 builtin_define ("__mips_fpr=32"); \
389 \
390 if (TARGET_MIPS16) \
391 builtin_define ("__mips16"); \
392 \
393 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
394 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
395 \
396 if (ISA_MIPS1) \
397 { \
398 builtin_define ("__mips=1"); \
399 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
400 } \
401 else if (ISA_MIPS2) \
402 { \
403 builtin_define ("__mips=2"); \
404 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
405 } \
406 else if (ISA_MIPS3) \
407 { \
408 builtin_define ("__mips=3"); \
409 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
410 } \
411 else if (ISA_MIPS4) \
412 { \
413 builtin_define ("__mips=4"); \
414 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
415 } \
416 else if (ISA_MIPS32) \
417 { \
418 builtin_define ("__mips=32"); \
419 builtin_define ("__mips_isa_rev=1"); \
420 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
421 } \
422 else if (ISA_MIPS32R2) \
423 { \
424 builtin_define ("__mips=32"); \
425 builtin_define ("__mips_isa_rev=2"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
427 } \
428 else if (ISA_MIPS64) \
429 { \
430 builtin_define ("__mips=64"); \
431 builtin_define ("__mips_isa_rev=1"); \
432 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
433 } \
434 \
435 if (TARGET_HARD_FLOAT) \
436 builtin_define ("__mips_hard_float"); \
437 else if (TARGET_SOFT_FLOAT) \
438 builtin_define ("__mips_soft_float"); \
439 \
440 if (TARGET_SINGLE_FLOAT) \
441 builtin_define ("__mips_single_float"); \
442 \
443 if (TARGET_BIG_ENDIAN) \
444 { \
445 builtin_define_std ("MIPSEB"); \
446 builtin_define ("_MIPSEB"); \
447 } \
448 else \
449 { \
450 builtin_define_std ("MIPSEL"); \
451 builtin_define ("_MIPSEL"); \
452 } \
453 \
454 /* Macros dependent on the C dialect. */ \
455 if (preprocessing_asm_p ()) \
456 { \
457 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
458 builtin_define ("_LANGUAGE_ASSEMBLY"); \
459 } \
460 else if (c_dialect_cxx ()) \
461 { \
462 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
463 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
464 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
465 } \
466 else \
467 { \
468 builtin_define_std ("LANGUAGE_C"); \
469 builtin_define ("_LANGUAGE_C"); \
470 } \
471 if (c_dialect_objc ()) \
472 { \
473 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
474 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
475 /* Bizzare, but needed at least for Irix. */ \
476 builtin_define_std ("LANGUAGE_C"); \
477 builtin_define ("_LANGUAGE_C"); \
478 } \
479 \
480 if (mips_abi == ABI_EABI) \
481 builtin_define ("__mips_eabi"); \
482 \
483 } while (0)
484
485
486
487 /* Macro to define tables used to set the flags.
488 This is a list in braces of pairs in braces,
489 each pair being { "NAME", VALUE }
490 where VALUE is the bits to set or minus the bits to clear.
491 An empty string NAME is used to identify the default VALUE. */
492
493 #define TARGET_SWITCHES \
494 { \
495 SUBTARGET_TARGET_SWITCHES \
496 {"int64", MASK_INT64 | MASK_LONG64, \
497 N_("Use 64-bit int type")}, \
498 {"long64", MASK_LONG64, \
499 N_("Use 64-bit long type")}, \
500 {"long32", -(MASK_LONG64 | MASK_INT64), \
501 N_("Use 32-bit long type")}, \
502 {"split-addresses", MASK_SPLIT_ADDR, \
503 N_("Optimize lui/addiu address loads")}, \
504 {"no-split-addresses", -MASK_SPLIT_ADDR, \
505 N_("Don't optimize lui/addiu address loads")}, \
506 {"mips-as", -MASK_GAS, \
507 N_("Use MIPS as")}, \
508 {"gas", MASK_GAS, \
509 N_("Use GNU as")}, \
510 {"rnames", MASK_NAME_REGS, \
511 N_("Use symbolic register names")}, \
512 {"no-rnames", -MASK_NAME_REGS, \
513 N_("Don't use symbolic register names")}, \
514 {"gpOPT", 0, \
515 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
516 {"gpopt", 0, \
517 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
518 {"no-gpOPT", 0, \
519 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
520 {"no-gpopt", 0, \
521 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
522 {"stats", 0, \
523 N_("Output compiler statistics (now ignored)")}, \
524 {"no-stats", 0, \
525 N_("Don't output compiler statistics")}, \
526 {"memcpy", MASK_MEMCPY, \
527 N_("Don't optimize block moves")}, \
528 {"no-memcpy", -MASK_MEMCPY, \
529 N_("Optimize block moves")}, \
530 {"mips-tfile", MASK_MIPS_TFILE, \
531 N_("Use mips-tfile asm postpass")}, \
532 {"no-mips-tfile", -MASK_MIPS_TFILE, \
533 N_("Don't use mips-tfile asm postpass")}, \
534 {"soft-float", MASK_SOFT_FLOAT, \
535 N_("Use software floating point")}, \
536 {"hard-float", -MASK_SOFT_FLOAT, \
537 N_("Use hardware floating point")}, \
538 {"fp64", MASK_FLOAT64, \
539 N_("Use 64-bit FP registers")}, \
540 {"fp32", -MASK_FLOAT64, \
541 N_("Use 32-bit FP registers")}, \
542 {"gp64", MASK_64BIT, \
543 N_("Use 64-bit general registers")}, \
544 {"gp32", -MASK_64BIT, \
545 N_("Use 32-bit general registers")}, \
546 {"abicalls", MASK_ABICALLS, \
547 N_("Use Irix PIC")}, \
548 {"no-abicalls", -MASK_ABICALLS, \
549 N_("Don't use Irix PIC")}, \
550 {"long-calls", MASK_LONG_CALLS, \
551 N_("Use indirect calls")}, \
552 {"no-long-calls", -MASK_LONG_CALLS, \
553 N_("Don't use indirect calls")}, \
554 {"embedded-pic", MASK_EMBEDDED_PIC, \
555 N_("Use embedded PIC")}, \
556 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
557 N_("Don't use embedded PIC")}, \
558 {"embedded-data", MASK_EMBEDDED_DATA, \
559 N_("Use ROM instead of RAM")}, \
560 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
561 N_("Don't use ROM instead of RAM")}, \
562 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
563 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
564 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
565 N_("Don't put uninitialized constants in ROM")}, \
566 {"eb", MASK_BIG_ENDIAN, \
567 N_("Use big-endian byte order")}, \
568 {"el", -MASK_BIG_ENDIAN, \
569 N_("Use little-endian byte order")}, \
570 {"single-float", MASK_SINGLE_FLOAT, \
571 N_("Use single (32-bit) FP only")}, \
572 {"double-float", -MASK_SINGLE_FLOAT, \
573 N_("Don't use single (32-bit) FP only")}, \
574 {"mad", MASK_MAD, \
575 N_("Use multiply accumulate")}, \
576 {"no-mad", -MASK_MAD, \
577 N_("Don't use multiply accumulate")}, \
578 {"no-fused-madd", MASK_NO_FUSED_MADD, \
579 N_("Don't generate fused multiply/add instructions")}, \
580 {"fused-madd", -MASK_NO_FUSED_MADD, \
581 N_("Generate fused multiply/add instructions")}, \
582 {"fix4300", MASK_4300_MUL_FIX, \
583 N_("Work around early 4300 hardware bug")}, \
584 {"no-fix4300", -MASK_4300_MUL_FIX, \
585 N_("Don't work around early 4300 hardware bug")}, \
586 {"fix-sb1", MASK_FIX_SB1, \
587 N_("Work around errata for early SB-1 revision 2 cores")}, \
588 {"no-fix-sb1", -MASK_FIX_SB1, \
589 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
590 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
591 N_("Trap on integer divide by zero")}, \
592 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
593 N_("Don't trap on integer divide by zero")}, \
594 { "branch-likely", MASK_BRANCHLIKELY, \
595 N_("Use Branch Likely instructions, overriding default for arch")}, \
596 { "no-branch-likely", -MASK_BRANCHLIKELY, \
597 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
598 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
599 N_("Use NewABI-style %reloc() assembly operators")}, \
600 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
601 N_("Use assembler macros instead of relocation operators")}, \
602 {"ips16", MASK_MIPS16, \
603 N_("Generate mips16 code") }, \
604 {"no-mips16", -MASK_MIPS16, \
605 N_("Generate normal-mode code") }, \
606 {"xgot", MASK_XGOT, \
607 N_("Lift restrictions on GOT size") }, \
608 {"no-xgot", -MASK_XGOT, \
609 N_("Do not lift restrictions on GOT size") }, \
610 {"debug", MASK_DEBUG, \
611 NULL}, \
612 {"debuga", MASK_DEBUG_A, \
613 NULL}, \
614 {"debugb", MASK_DEBUG_B, \
615 NULL}, \
616 {"debugc", MASK_DEBUG_C, \
617 NULL}, \
618 {"debugd", MASK_DEBUG_D, \
619 NULL}, \
620 {"debuge", MASK_DEBUG_E, \
621 NULL}, \
622 {"debugf", MASK_DEBUG_F, \
623 NULL}, \
624 {"debugg", MASK_DEBUG_G, \
625 NULL}, \
626 {"debugi", MASK_DEBUG_I, \
627 NULL}, \
628 {"", (TARGET_DEFAULT \
629 | TARGET_CPU_DEFAULT \
630 | TARGET_ENDIAN_DEFAULT), \
631 NULL}, \
632 }
633
634 /* Default target_flags if no switches are specified */
635
636 #ifndef TARGET_DEFAULT
637 #define TARGET_DEFAULT 0
638 #endif
639
640 #ifndef TARGET_CPU_DEFAULT
641 #define TARGET_CPU_DEFAULT 0
642 #endif
643
644 #ifndef TARGET_ENDIAN_DEFAULT
645 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
646 #endif
647
648 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
649 #ifndef MIPS_ISA_DEFAULT
650 #ifndef MIPS_CPU_STRING_DEFAULT
651 #define MIPS_CPU_STRING_DEFAULT "from-abi"
652 #endif
653 #endif
654
655 #ifdef IN_LIBGCC2
656 #undef TARGET_64BIT
657 /* Make this compile time constant for libgcc2 */
658 #ifdef __mips64
659 #define TARGET_64BIT 1
660 #else
661 #define TARGET_64BIT 0
662 #endif
663 #endif /* IN_LIBGCC2 */
664
665 #ifndef MULTILIB_ENDIAN_DEFAULT
666 #if TARGET_ENDIAN_DEFAULT == 0
667 #define MULTILIB_ENDIAN_DEFAULT "EL"
668 #else
669 #define MULTILIB_ENDIAN_DEFAULT "EB"
670 #endif
671 #endif
672
673 #ifndef MULTILIB_ISA_DEFAULT
674 # if MIPS_ISA_DEFAULT == 1
675 # define MULTILIB_ISA_DEFAULT "mips1"
676 # else
677 # if MIPS_ISA_DEFAULT == 2
678 # define MULTILIB_ISA_DEFAULT "mips2"
679 # else
680 # if MIPS_ISA_DEFAULT == 3
681 # define MULTILIB_ISA_DEFAULT "mips3"
682 # else
683 # if MIPS_ISA_DEFAULT == 4
684 # define MULTILIB_ISA_DEFAULT "mips4"
685 # else
686 # if MIPS_ISA_DEFAULT == 32
687 # define MULTILIB_ISA_DEFAULT "mips32"
688 # else
689 # if MIPS_ISA_DEFAULT == 33
690 # define MULTILIB_ISA_DEFAULT "mips32r2"
691 # else
692 # if MIPS_ISA_DEFAULT == 64
693 # define MULTILIB_ISA_DEFAULT "mips64"
694 # else
695 # define MULTILIB_ISA_DEFAULT "mips1"
696 # endif
697 # endif
698 # endif
699 # endif
700 # endif
701 # endif
702 # endif
703 #endif
704
705 #ifndef MULTILIB_DEFAULTS
706 #define MULTILIB_DEFAULTS \
707 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
708 #endif
709
710 /* We must pass -EL to the linker by default for little endian embedded
711 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
712 linker will default to using big-endian output files. The OUTPUT_FORMAT
713 line must be in the linker script, otherwise -EB/-EL will not work. */
714
715 #ifndef ENDIAN_SPEC
716 #if TARGET_ENDIAN_DEFAULT == 0
717 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
718 #else
719 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
720 #endif
721 #endif
722
723 #define TARGET_OPTIONS \
724 { \
725 SUBTARGET_TARGET_OPTIONS \
726 { "tune=", &mips_tune_string, \
727 N_("Specify CPU for scheduling purposes"), 0}, \
728 { "arch=", &mips_arch_string, \
729 N_("Specify CPU for code generation purposes"), 0}, \
730 { "abi=", &mips_abi_string, \
731 N_("Specify an ABI"), 0}, \
732 { "ips", &mips_isa_string, \
733 N_("Specify a Standard MIPS ISA"), 0}, \
734 { "entry", &mips_entry_string, \
735 N_("Use mips16 entry/exit psuedo ops"), 0}, \
736 { "no-flush-func", &mips_cache_flush_func, \
737 N_("Don't call any cache flush functions"), 0}, \
738 { "flush-func=", &mips_cache_flush_func, \
739 N_("Specify cache flush function"), 0}, \
740 }
741
742 /* This is meant to be redefined in the host dependent files. */
743 #define SUBTARGET_TARGET_OPTIONS
744
745 /* Support for a compile-time default CPU, et cetera. The rules are:
746 --with-arch is ignored if -march is specified or a -mips is specified
747 (other than -mips16).
748 --with-tune is ignored if -mtune is specified.
749 --with-abi is ignored if -mabi is specified.
750 --with-float is ignored if -mhard-float or -msoft-float are
751 specified. */
752 #define OPTION_DEFAULT_SPECS \
753 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
754 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
755 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
756 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
757
758
759 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
760 && !TARGET_SR71K \
761 && !TARGET_MIPS16)
762
763 /* Generate three-operand multiply instructions for SImode. */
764 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
765 || TARGET_MIPS5400 \
766 || TARGET_MIPS5500 \
767 || TARGET_MIPS7000 \
768 || TARGET_MIPS9000 \
769 || ISA_MIPS32 \
770 || ISA_MIPS32R2 \
771 || ISA_MIPS64) \
772 && !TARGET_MIPS16)
773
774 /* Generate three-operand multiply instructions for DImode. */
775 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
776 && !TARGET_MIPS16)
777
778 /* Macros to decide whether certain features are available or not,
779 depending on the instruction set architecture level. */
780
781 #define HAVE_SQRT_P() (!ISA_MIPS1)
782
783 /* True if the ABI can only work with 64-bit integer registers. We
784 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
785 otherwise floating-point registers must also be 64-bit. */
786 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
787 || mips_abi == ABI_O64 \
788 || mips_abi == ABI_N32)
789
790 /* Likewise for 32-bit regs. */
791 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
792
793 /* True if symbols are 64 bits wide. At present, n64 is the only
794 ABI for which this is true. */
795 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
796
797 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
798 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
799 || ISA_MIPS4 \
800 || ISA_MIPS64)
801
802 /* ISA has branch likely instructions (eg. mips2). */
803 /* Disable branchlikely for tx39 until compare rewrite. They haven't
804 been generated up to this point. */
805 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
806 && !TARGET_MIPS5500)
807
808 /* ISA has the conditional move instructions introduced in mips4. */
809 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
810 || ISA_MIPS32 \
811 || ISA_MIPS32R2 \
812 || ISA_MIPS64) \
813 && !TARGET_MIPS5500 \
814 && !TARGET_MIPS16)
815
816 /* ISA has just the integer condition move instructions (movn,movz) */
817 #define ISA_HAS_INT_CONDMOVE 0
818
819 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
820 branch on CC, and move (both FP and non-FP) on CC. */
821 #define ISA_HAS_8CC (ISA_MIPS4 \
822 || ISA_MIPS32 \
823 || ISA_MIPS32R2 \
824 || ISA_MIPS64)
825
826 /* This is a catch all for the other new mips4 instructions: indexed load and
827 indexed prefetch instructions, the FP madd and msub instructions,
828 and the FP recip and recip sqrt instructions */
829 #define ISA_HAS_FP4 ((ISA_MIPS4 \
830 || ISA_MIPS64) \
831 && !TARGET_MIPS16)
832
833 /* ISA has conditional trap instructions. */
834 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
835 && !TARGET_MIPS16)
836
837 /* ISA has integer multiply-accumulate instructions, madd and msub. */
838 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
839 || ISA_MIPS32R2 \
840 || ISA_MIPS64 \
841 ) && !TARGET_MIPS16)
842
843 /* ISA has floating-point nmadd and nmsub instructions. */
844 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
845 || ISA_MIPS64) \
846 && (!TARGET_MIPS5400 || TARGET_MAD) \
847 && ! TARGET_MIPS16)
848
849 /* ISA has count leading zeroes/ones instruction (not implemented). */
850 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
851 || ISA_MIPS32R2 \
852 || ISA_MIPS64 \
853 ) && !TARGET_MIPS16)
854
855 /* ISA has double-word count leading zeroes/ones instruction (not
856 implemented). */
857 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
858 && !TARGET_MIPS16)
859
860 /* ISA has three operand multiply instructions that put
861 the high part in an accumulator: mulhi or mulhiu. */
862 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
863 || TARGET_MIPS5500 \
864 || TARGET_SR71K \
865 )
866
867 /* ISA has three operand multiply instructions that
868 negates the result and puts the result in an accumulator. */
869 #define ISA_HAS_MULS (TARGET_MIPS5400 \
870 || TARGET_MIPS5500 \
871 || TARGET_SR71K \
872 )
873
874 /* ISA has three operand multiply instructions that subtracts the
875 result from a 4th operand and puts the result in an accumulator. */
876 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
877 || TARGET_MIPS5500 \
878 || TARGET_SR71K \
879 )
880 /* ISA has three operand multiply instructions that the result
881 from a 4th operand and puts the result in an accumulator. */
882 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
883 || TARGET_MIPS5400 \
884 || TARGET_MIPS5500 \
885 || TARGET_SR71K \
886 )
887
888 /* ISA has 32-bit rotate right instruction. */
889 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
890 && (ISA_MIPS32R2 \
891 || TARGET_MIPS5400 \
892 || TARGET_MIPS5500 \
893 || TARGET_SR71K \
894 ))
895
896 /* ISA has 64-bit rotate right instruction. */
897 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
898 && !TARGET_MIPS16 \
899 && (TARGET_MIPS5400 \
900 || TARGET_MIPS5500 \
901 || TARGET_SR71K \
902 ))
903
904 /* ISA has data prefetch instruction. */
905 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
906 || ISA_MIPS32 \
907 || ISA_MIPS32R2 \
908 || ISA_MIPS64) \
909 && !TARGET_MIPS16)
910
911 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
912 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
913 also requires TARGET_DOUBLE_FLOAT. */
914 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
915
916 /* ISA includes the MIPS32r2 seb and seh instructions. */
917 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
918 && (ISA_MIPS32R2 \
919 ))
920
921 /* True if the result of a load is not available to the next instruction.
922 A nop will then be needed between instructions like "lw $4,..."
923 and "addiu $4,$4,1". */
924 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
925 && !TARGET_MIPS3900 \
926 && !TARGET_MIPS16)
927
928 /* Likewise mtc1 and mfc1. */
929 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
930
931 /* Likewise floating-point comparisons. */
932 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
933
934 /* True if mflo and mfhi can be immediately followed by instructions
935 which write to the HI and LO registers. Most targets require a
936 two-instruction gap. */
937 #define ISA_HAS_HILO_INTERLOCKS (TARGET_MIPS5500 || TARGET_SB1)
938 \f
939 /* Add -G xx support. */
940
941 #undef SWITCH_TAKES_ARG
942 #define SWITCH_TAKES_ARG(CHAR) \
943 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
944
945 #define OVERRIDE_OPTIONS override_options ()
946
947 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
948
949 /* Show we can debug even without a frame pointer. */
950 #define CAN_DEBUG_WITHOUT_FP
951 \f
952 /* Tell collect what flags to pass to nm. */
953 #ifndef NM_FLAGS
954 #define NM_FLAGS "-Bn"
955 #endif
956
957 \f
958 /* Assembler specs. */
959
960 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
961 than gas. */
962
963 #define MIPS_AS_ASM_SPEC "\
964 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
965 %{pipe: %e-pipe is not supported} \
966 %{K} %(subtarget_mips_as_asm_spec)"
967
968 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
969 rather than gas. It may be overridden by subtargets. */
970
971 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
972 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
973 #endif
974
975 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
976 assembler. */
977
978 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
979
980 #define SUBTARGET_TARGET_SWITCHES
981
982 #ifndef MIPS_ABI_DEFAULT
983 #define MIPS_ABI_DEFAULT ABI_32
984 #endif
985
986 /* Use the most portable ABI flag for the ASM specs. */
987
988 #if MIPS_ABI_DEFAULT == ABI_32
989 #define MULTILIB_ABI_DEFAULT "mabi=32"
990 #define ASM_ABI_DEFAULT_SPEC "-32"
991 #endif
992
993 #if MIPS_ABI_DEFAULT == ABI_O64
994 #define MULTILIB_ABI_DEFAULT "mabi=o64"
995 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
996 #endif
997
998 #if MIPS_ABI_DEFAULT == ABI_N32
999 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1000 #define ASM_ABI_DEFAULT_SPEC "-n32"
1001 #endif
1002
1003 #if MIPS_ABI_DEFAULT == ABI_64
1004 #define MULTILIB_ABI_DEFAULT "mabi=64"
1005 #define ASM_ABI_DEFAULT_SPEC "-64"
1006 #endif
1007
1008 #if MIPS_ABI_DEFAULT == ABI_EABI
1009 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1010 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1011 #endif
1012
1013 /* Only ELF targets can switch the ABI. */
1014 #ifndef OBJECT_FORMAT_ELF
1015 #undef ASM_ABI_DEFAULT_SPEC
1016 #define ASM_ABI_DEFAULT_SPEC ""
1017 #endif
1018
1019 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1020 GAS_ASM_SPEC as the default, depending upon the value of
1021 TARGET_DEFAULT. */
1022
1023 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1024 /* GAS */
1025
1026 #define TARGET_ASM_SPEC "\
1027 %{mmips-as: %(mips_as_asm_spec)} \
1028 %{!mmips-as: %(gas_asm_spec)}"
1029
1030 #else /* not GAS */
1031
1032 #define TARGET_ASM_SPEC "\
1033 %{!mgas: %(mips_as_asm_spec)} \
1034 %{mgas: %(gas_asm_spec)}"
1035
1036 #endif /* not GAS */
1037
1038 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1039 to the assembler. It may be overridden by subtargets. */
1040 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1041 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1042 %{noasmopt:-O0} \
1043 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1044 #endif
1045
1046 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1047 the assembler. It may be overridden by subtargets. */
1048 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1049 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1050 %{g} %{g0} %{g1} %{g2} %{g3} \
1051 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1052 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1053 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1054 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1055 %(mdebug_asm_spec)"
1056 #endif
1057
1058 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1059 and stabs debugging info. */
1060 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1061 /* GAS */
1062 #define MDEBUG_ASM_SPEC "%{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1063 #else /* not GAS */
1064 #define MDEBUG_ASM_SPEC ""
1065 #endif /* not GAS */
1066
1067 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1068 overridden by subtargets. */
1069
1070 #ifndef SUBTARGET_ASM_SPEC
1071 #define SUBTARGET_ASM_SPEC ""
1072 #endif
1073
1074 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1075 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1076 whether we're using GAS. These options can only be used properly
1077 with GAS, and it is better to get an error from a non-GAS assembler
1078 than to silently generate bad code. */
1079
1080 #undef ASM_SPEC
1081 #define ASM_SPEC "\
1082 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1083 %{mips32} %{mips32r2} %{mips64} \
1084 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1085 %(subtarget_asm_optimizing_spec) \
1086 %(subtarget_asm_debugging_spec) \
1087 %{membedded-pic} \
1088 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1089 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1090 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1091 %(target_asm_spec) \
1092 %(subtarget_asm_spec)"
1093
1094 /* Extra switches sometimes passed to the linker. */
1095 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1096 will interpret it as a -b option. */
1097
1098 #ifndef LINK_SPEC
1099 #define LINK_SPEC "\
1100 %(endian_spec) \
1101 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1102 %{bestGnum} %{shared} %{non_shared}"
1103 #endif /* LINK_SPEC defined */
1104
1105
1106 /* Specs for the compiler proper */
1107
1108 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1109 overridden by subtargets. */
1110 #ifndef SUBTARGET_CC1_SPEC
1111 #define SUBTARGET_CC1_SPEC ""
1112 #endif
1113
1114 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1115
1116 #ifndef CC1_SPEC
1117 #define CC1_SPEC "\
1118 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1119 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1120 %{save-temps: } \
1121 %(subtarget_cc1_spec)"
1122 #endif
1123
1124 /* Preprocessor specs. */
1125
1126 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1127 overridden by subtargets. */
1128 #ifndef SUBTARGET_CPP_SPEC
1129 #define SUBTARGET_CPP_SPEC ""
1130 #endif
1131
1132 #define CPP_SPEC "%(subtarget_cpp_spec)"
1133
1134 /* This macro defines names of additional specifications to put in the specs
1135 that can be used in various specifications like CC1_SPEC. Its definition
1136 is an initializer with a subgrouping for each command option.
1137
1138 Each subgrouping contains a string constant, that defines the
1139 specification name, and a string constant that used by the GCC driver
1140 program.
1141
1142 Do not define this macro if it does not need to do anything. */
1143
1144 #define EXTRA_SPECS \
1145 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1146 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1147 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1148 { "gas_asm_spec", GAS_ASM_SPEC }, \
1149 { "target_asm_spec", TARGET_ASM_SPEC }, \
1150 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1151 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1152 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1153 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1154 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1155 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1156 { "endian_spec", ENDIAN_SPEC }, \
1157 SUBTARGET_EXTRA_SPECS
1158
1159 #ifndef SUBTARGET_EXTRA_SPECS
1160 #define SUBTARGET_EXTRA_SPECS
1161 #endif
1162
1163 /* If defined, this macro is an additional prefix to try after
1164 `STANDARD_EXEC_PREFIX'. */
1165
1166 #ifndef MD_EXEC_PREFIX
1167 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1168 #endif
1169
1170 #ifndef MD_STARTFILE_PREFIX
1171 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1172 #endif
1173
1174 \f
1175 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1176 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1177
1178 /* By default, turn on GDB extensions. */
1179 #define DEFAULT_GDB_EXTENSIONS 1
1180
1181 /* If we are passing smuggling stabs through the MIPS ECOFF object
1182 format, put a comment in front of the .stab<x> operation so
1183 that the MIPS assembler does not choke. The mips-tfile program
1184 will correctly put the stab into the object file. */
1185
1186 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1187 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1188 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1189
1190 /* Local compiler-generated symbols must have a prefix that the assembler
1191 understands. By default, this is $, although some targets (e.g.,
1192 NetBSD-ELF) need to override this. */
1193
1194 #ifndef LOCAL_LABEL_PREFIX
1195 #define LOCAL_LABEL_PREFIX "$"
1196 #endif
1197
1198 /* By default on the mips, external symbols do not have an underscore
1199 prepended, but some targets (e.g., NetBSD) require this. */
1200
1201 #ifndef USER_LABEL_PREFIX
1202 #define USER_LABEL_PREFIX ""
1203 #endif
1204
1205 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1206 since the length can run past this up to a continuation point. */
1207 #undef DBX_CONTIN_LENGTH
1208 #define DBX_CONTIN_LENGTH 1500
1209
1210 /* How to renumber registers for dbx and gdb. */
1211 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1212
1213 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1214 #define DWARF_FRAME_REGNUM(REG) \
1215 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1216
1217 /* The DWARF 2 CFA column which tracks the return address. */
1218 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1219
1220 /* Before the prologue, RA lives in r31. */
1221 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1222
1223 /* Describe how we implement __builtin_eh_return. */
1224 #define EH_RETURN_DATA_REGNO(N) \
1225 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1226
1227 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1228
1229 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1230 The default for this in 64-bit mode is 8, which causes problems with
1231 SFmode register saves. */
1232 #define DWARF_CIE_DATA_ALIGNMENT 4
1233
1234 #define FIND_BASE_TERM(X) mips_delegitimize_address (X)
1235
1236 /* Correct the offset of automatic variables and arguments. Note that
1237 the MIPS debug format wants all automatic variables and arguments
1238 to be in terms of the virtual frame pointer (stack pointer before
1239 any adjustment in the function), while the MIPS 3.0 linker wants
1240 the frame pointer to be the stack pointer after the initial
1241 adjustment. */
1242
1243 #define DEBUGGER_AUTO_OFFSET(X) \
1244 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1245 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1246 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1247 \f
1248 /* Target machine storage layout */
1249
1250 #define BITS_BIG_ENDIAN 0
1251 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1252 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1253
1254 /* Define this to set the endianness to use in libgcc2.c, which can
1255 not depend on target_flags. */
1256 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1257 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1258 #else
1259 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1260 #endif
1261
1262 #define MAX_BITS_PER_WORD 64
1263
1264 /* Width of a word, in units (bytes). */
1265 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1266 #define MIN_UNITS_PER_WORD 4
1267
1268 /* For MIPS, width of a floating point register. */
1269 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1270
1271 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1272 the next available register. */
1273 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1274
1275 /* The largest size of value that can be held in floating-point
1276 registers and moved with a single instruction. */
1277 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1278
1279 /* The largest size of value that can be held in floating-point
1280 registers. */
1281 #define UNITS_PER_FPVALUE \
1282 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1283
1284 /* The number of bytes in a double. */
1285 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1286
1287 /* Tell the preprocessor the maximum size of wchar_t. */
1288 #ifndef MAX_WCHAR_TYPE_SIZE
1289 #ifndef WCHAR_TYPE_SIZE
1290 #define MAX_WCHAR_TYPE_SIZE 64
1291 #endif
1292 #endif
1293
1294 /* Set the sizes of the core types. */
1295 #define SHORT_TYPE_SIZE 16
1296 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1297 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1298 #define LONG_LONG_TYPE_SIZE 64
1299
1300 #define MAX_LONG_TYPE_SIZE 64
1301
1302 #define FLOAT_TYPE_SIZE 32
1303 #define DOUBLE_TYPE_SIZE 64
1304 #define LONG_DOUBLE_TYPE_SIZE \
1305 (mips_abi == ABI_N32 || mips_abi == ABI_64 ? 128 : 64)
1306
1307 /* long double is not a fixed mode, but the idea is that, if we
1308 support long double, we also want a 128-bit integer type. */
1309 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1310
1311 #ifdef IN_LIBGCC2
1312 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1313 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1314 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1315 # else
1316 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1317 # endif
1318 #endif
1319
1320 /* Width in bits of a pointer. */
1321 #ifndef POINTER_SIZE
1322 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1323 #endif
1324
1325 #define POINTERS_EXTEND_UNSIGNED 0
1326
1327 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1328 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1329 || mips_abi == ABI_64 \
1330 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1331
1332
1333 /* Allocation boundary (in *bits*) for the code of a function. */
1334 #define FUNCTION_BOUNDARY 32
1335
1336 /* Alignment of field after `int : 0' in a structure. */
1337 #define EMPTY_FIELD_BOUNDARY 32
1338
1339 /* Every structure's size must be a multiple of this. */
1340 /* 8 is observed right on a DECstation and on riscos 4.02. */
1341 #define STRUCTURE_SIZE_BOUNDARY 8
1342
1343 /* There is no point aligning anything to a rounder boundary than this. */
1344 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1345
1346 /* All accesses must be aligned. */
1347 #define STRICT_ALIGNMENT 1
1348
1349 /* Define this if you wish to imitate the way many other C compilers
1350 handle alignment of bitfields and the structures that contain
1351 them.
1352
1353 The behavior is that the type written for a bit-field (`int',
1354 `short', or other integer type) imposes an alignment for the
1355 entire structure, as if the structure really did contain an
1356 ordinary field of that type. In addition, the bit-field is placed
1357 within the structure so that it would fit within such a field,
1358 not crossing a boundary for it.
1359
1360 Thus, on most machines, a bit-field whose type is written as `int'
1361 would not cross a four-byte boundary, and would force four-byte
1362 alignment for the whole structure. (The alignment used may not
1363 be four bytes; it is controlled by the other alignment
1364 parameters.)
1365
1366 If the macro is defined, its definition should be a C expression;
1367 a nonzero value for the expression enables this behavior. */
1368
1369 #define PCC_BITFIELD_TYPE_MATTERS 1
1370
1371 /* If defined, a C expression to compute the alignment given to a
1372 constant that is being placed in memory. CONSTANT is the constant
1373 and ALIGN is the alignment that the object would ordinarily have.
1374 The value of this macro is used instead of that alignment to align
1375 the object.
1376
1377 If this macro is not defined, then ALIGN is used.
1378
1379 The typical use of this macro is to increase alignment for string
1380 constants to be word aligned so that `strcpy' calls that copy
1381 constants can be done inline. */
1382
1383 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1384 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1385 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1386
1387 /* If defined, a C expression to compute the alignment for a static
1388 variable. TYPE is the data type, and ALIGN is the alignment that
1389 the object would ordinarily have. The value of this macro is used
1390 instead of that alignment to align the object.
1391
1392 If this macro is not defined, then ALIGN is used.
1393
1394 One use of this macro is to increase alignment of medium-size
1395 data to make it all fit in fewer cache lines. Another is to
1396 cause character arrays to be word-aligned so that `strcpy' calls
1397 that copy constants to character arrays can be done inline. */
1398
1399 #undef DATA_ALIGNMENT
1400 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1401 ((((ALIGN) < BITS_PER_WORD) \
1402 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1403 || TREE_CODE (TYPE) == UNION_TYPE \
1404 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1405
1406
1407 #define PAD_VARARGS_DOWN \
1408 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1409
1410 /* Arguments declared as 'char' or 'short' in a prototype should be
1411 passed as 'int's. */
1412 #define PROMOTE_PROTOTYPES 1
1413
1414 /* Define if operations between registers always perform the operation
1415 on the full register even if a narrower mode is specified. */
1416 #define WORD_REGISTER_OPERATIONS
1417
1418 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1419 moves. All other references are zero extended. */
1420 #define LOAD_EXTEND_OP(MODE) \
1421 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1422 ? SIGN_EXTEND : ZERO_EXTEND)
1423
1424 /* Define this macro if it is advisable to hold scalars in registers
1425 in a wider mode than that declared by the program. In such cases,
1426 the value is constrained to be within the bounds of the declared
1427 type, but kept valid in the wider mode. The signedness of the
1428 extension may differ from that of the type. */
1429
1430 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1431 if (GET_MODE_CLASS (MODE) == MODE_INT \
1432 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1433 { \
1434 if ((MODE) == SImode) \
1435 (UNSIGNEDP) = 0; \
1436 (MODE) = Pmode; \
1437 }
1438
1439 /* Define if loading short immediate values into registers sign extends. */
1440 #define SHORT_IMMEDIATES_SIGN_EXTEND
1441
1442
1443 /* Define this if function arguments should also be promoted using the above
1444 procedure. */
1445 #define PROMOTE_FUNCTION_ARGS
1446
1447 /* Likewise, if the function return value is promoted. */
1448 #define PROMOTE_FUNCTION_RETURN
1449
1450 \f
1451 /* Standard register usage. */
1452
1453 /* Number of hardware registers. We have:
1454
1455 - 32 integer registers
1456 - 32 floating point registers
1457 - 8 condition code registers
1458 - 2 accumulator registers (hi and lo)
1459 - 32 registers each for coprocessors 0, 2 and 3
1460 - 6 dummy entries that were used at various times in the past. */
1461
1462 #define FIRST_PSEUDO_REGISTER 176
1463
1464 /* By default, fix the kernel registers ($26 and $27), the global
1465 pointer ($28) and the stack pointer ($29). This can change
1466 depending on the command-line options.
1467
1468 Regarding coprocessor registers: without evidence to the contrary,
1469 it's best to assume that each coprocessor register has a unique
1470 use. This can be overridden, in, e.g., override_options() or
1471 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1472 for a particular target. */
1473
1474 #define FIXED_REGISTERS \
1475 { \
1476 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1477 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1478 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1479 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1480 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1481 /* COP0 registers */ \
1482 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1483 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1484 /* COP2 registers */ \
1485 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1486 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1487 /* COP3 registers */ \
1488 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1489 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1490 }
1491
1492
1493 /* Set up this array for o32 by default.
1494
1495 Note that we don't mark $31 as a call-clobbered register. The idea is
1496 that it's really the call instructions themselves which clobber $31.
1497 We don't care what the called function does with it afterwards.
1498
1499 This approach makes it easier to implement sibcalls. Unlike normal
1500 calls, sibcalls don't clobber $31, so the register reaches the
1501 called function in tact. EPILOGUE_USES says that $31 is useful
1502 to the called function. */
1503
1504 #define CALL_USED_REGISTERS \
1505 { \
1506 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1507 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1508 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1509 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1510 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1511 /* COP0 registers */ \
1512 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1513 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1514 /* COP2 registers */ \
1515 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1516 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1517 /* COP3 registers */ \
1518 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1520 }
1521
1522
1523 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1524
1525 #define CALL_REALLY_USED_REGISTERS \
1526 { /* General registers. */ \
1527 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1528 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1529 /* Floating-point registers. */ \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1532 /* Others. */ \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 /* COP0 registers */ \
1535 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1536 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1537 /* COP2 registers */ \
1538 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1540 /* COP3 registers */ \
1541 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1542 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1543 }
1544
1545 /* Internal macros to classify a register number as to whether it's a
1546 general purpose register, a floating point register, a
1547 multiply/divide register, or a status register. */
1548
1549 #define GP_REG_FIRST 0
1550 #define GP_REG_LAST 31
1551 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1552 #define GP_DBX_FIRST 0
1553
1554 #define FP_REG_FIRST 32
1555 #define FP_REG_LAST 63
1556 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1557 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1558
1559 #define MD_REG_FIRST 64
1560 #define MD_REG_LAST 65
1561 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1562 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1563
1564 #define ST_REG_FIRST 67
1565 #define ST_REG_LAST 74
1566 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1567
1568
1569 /* FIXME: renumber. */
1570 #define COP0_REG_FIRST 80
1571 #define COP0_REG_LAST 111
1572 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1573
1574 #define COP2_REG_FIRST 112
1575 #define COP2_REG_LAST 143
1576 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1577
1578 #define COP3_REG_FIRST 144
1579 #define COP3_REG_LAST 175
1580 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1581 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1582 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1583
1584 #define AT_REGNUM (GP_REG_FIRST + 1)
1585 #define HI_REGNUM (MD_REG_FIRST + 0)
1586 #define LO_REGNUM (MD_REG_FIRST + 1)
1587
1588 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1589 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1590 should be used instead. */
1591 #define FPSW_REGNUM ST_REG_FIRST
1592
1593 #define GP_REG_P(REGNO) \
1594 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1595 #define M16_REG_P(REGNO) \
1596 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1597 #define FP_REG_P(REGNO) \
1598 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1599 #define MD_REG_P(REGNO) \
1600 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1601 #define ST_REG_P(REGNO) \
1602 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1603 #define COP0_REG_P(REGNO) \
1604 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1605 #define COP2_REG_P(REGNO) \
1606 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1607 #define COP3_REG_P(REGNO) \
1608 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1609 #define ALL_COP_REG_P(REGNO) \
1610 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1611
1612 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1613
1614 /* Return coprocessor number from register number. */
1615
1616 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1617 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1618 : COP3_REG_P (REGNO) ? '3' : '?')
1619
1620
1621 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1622
1623 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1624 array built in override_options. Because machmodes.h is not yet
1625 included before this file is processed, the MODE bound can't be
1626 expressed here. */
1627
1628 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1629
1630 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1631 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1632
1633 /* Value is 1 if it is a good idea to tie two pseudo registers
1634 when one has mode MODE1 and one has mode MODE2.
1635 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1636 for any hard reg, then this must be 0 for correct output. */
1637 #define MODES_TIEABLE_P(MODE1, MODE2) \
1638 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1639 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1640 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1641 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1642
1643 /* Register to use for pushing function arguments. */
1644 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1645
1646 /* Base register for access to local variables of the function. We
1647 pretend that the frame pointer is $1, and then eliminate it to
1648 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1649 a fixed register, and will not be used for anything else. */
1650 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1651
1652 /* $30 is not available on the mips16, so we use $17 as the frame
1653 pointer. */
1654 #define HARD_FRAME_POINTER_REGNUM \
1655 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1656
1657 /* Value should be nonzero if functions must have frame pointers.
1658 Zero means the frame pointer need not be set up (and parms
1659 may be accessed via the stack pointer) in functions that seem suitable.
1660 This is computed in `reload', in reload1.c. */
1661 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1662
1663 /* Base register for access to arguments of the function. */
1664 #define ARG_POINTER_REGNUM GP_REG_FIRST
1665
1666 /* Register in which static-chain is passed to a function. */
1667 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1668
1669 /* Pass structure addresses as an "invisible" first argument. */
1670 #define STRUCT_VALUE 0
1671
1672 /* Mips registers used in prologue/epilogue code when the stack frame
1673 is larger than 32K bytes. These registers must come from the
1674 scratch register set, and not used for passing and returning
1675 arguments and any other information used in the calling sequence
1676 (such as pic). Must start at 12, since t0/t3 are parameter passing
1677 registers in the 64 bit ABI. */
1678
1679 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1680 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1681
1682 /* Define this macro if it is as good or better to call a constant
1683 function address than to call an address kept in a register. */
1684 #define NO_FUNCTION_CSE 1
1685
1686 /* Define this macro if it is as good or better for a function to
1687 call itself with an explicit address than to call an address
1688 kept in a register. */
1689 #define NO_RECURSIVE_FUNCTION_CSE 1
1690
1691 /* The ABI-defined global pointer. Sometimes we use a different
1692 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1693 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1694
1695 /* We normally use $28 as the global pointer. However, when generating
1696 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1697 register instead. They can then avoid saving and restoring $28
1698 and perhaps avoid using a frame at all.
1699
1700 When a leaf function uses something other than $28, mips_expand_prologue
1701 will modify pic_offset_table_rtx in place. Take the register number
1702 from there after reload. */
1703 #define PIC_OFFSET_TABLE_REGNUM \
1704 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1705
1706 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1707 \f
1708 /* Define the classes of registers for register constraints in the
1709 machine description. Also define ranges of constants.
1710
1711 One of the classes must always be named ALL_REGS and include all hard regs.
1712 If there is more than one class, another class must be named NO_REGS
1713 and contain no registers.
1714
1715 The name GENERAL_REGS must be the name of a class (or an alias for
1716 another name such as ALL_REGS). This is the class of registers
1717 that is allowed by "g" or "r" in a register constraint.
1718 Also, registers outside this class are allocated only when
1719 instructions express preferences for them.
1720
1721 The classes must be numbered in nondecreasing order; that is,
1722 a larger-numbered class must never be contained completely
1723 in a smaller-numbered class.
1724
1725 For any two classes, it is very desirable that there be another
1726 class that represents their union. */
1727
1728 enum reg_class
1729 {
1730 NO_REGS, /* no registers in set */
1731 M16_NA_REGS, /* mips16 regs not used to pass args */
1732 M16_REGS, /* mips16 directly accessible registers */
1733 T_REG, /* mips16 T register ($24) */
1734 M16_T_REGS, /* mips16 registers plus T register */
1735 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1736 LEA_REGS, /* Every GPR except $25 */
1737 GR_REGS, /* integer registers */
1738 FP_REGS, /* floating point registers */
1739 HI_REG, /* hi register */
1740 LO_REG, /* lo register */
1741 MD_REGS, /* multiply/divide registers (hi/lo) */
1742 COP0_REGS, /* generic coprocessor classes */
1743 COP2_REGS,
1744 COP3_REGS,
1745 HI_AND_GR_REGS, /* union classes */
1746 LO_AND_GR_REGS,
1747 HI_AND_FP_REGS,
1748 COP0_AND_GR_REGS,
1749 COP2_AND_GR_REGS,
1750 COP3_AND_GR_REGS,
1751 ALL_COP_REGS,
1752 ALL_COP_AND_GR_REGS,
1753 ST_REGS, /* status registers (fp status) */
1754 ALL_REGS, /* all registers */
1755 LIM_REG_CLASSES /* max value + 1 */
1756 };
1757
1758 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1759
1760 #define GENERAL_REGS GR_REGS
1761
1762 /* An initializer containing the names of the register classes as C
1763 string constants. These names are used in writing some of the
1764 debugging dumps. */
1765
1766 #define REG_CLASS_NAMES \
1767 { \
1768 "NO_REGS", \
1769 "M16_NA_REGS", \
1770 "M16_REGS", \
1771 "T_REG", \
1772 "M16_T_REGS", \
1773 "PIC_FN_ADDR_REG", \
1774 "LEA_REGS", \
1775 "GR_REGS", \
1776 "FP_REGS", \
1777 "HI_REG", \
1778 "LO_REG", \
1779 "MD_REGS", \
1780 /* coprocessor registers */ \
1781 "COP0_REGS", \
1782 "COP2_REGS", \
1783 "COP3_REGS", \
1784 "HI_AND_GR_REGS", \
1785 "LO_AND_GR_REGS", \
1786 "HI_AND_FP_REGS", \
1787 "COP0_AND_GR_REGS", \
1788 "COP2_AND_GR_REGS", \
1789 "COP3_AND_GR_REGS", \
1790 "ALL_COP_REGS", \
1791 "ALL_COP_AND_GR_REGS", \
1792 "ST_REGS", \
1793 "ALL_REGS" \
1794 }
1795
1796 /* An initializer containing the contents of the register classes,
1797 as integers which are bit masks. The Nth integer specifies the
1798 contents of class N. The way the integer MASK is interpreted is
1799 that register R is in the class if `MASK & (1 << R)' is 1.
1800
1801 When the machine has more than 32 registers, an integer does not
1802 suffice. Then the integers are replaced by sub-initializers,
1803 braced groupings containing several integers. Each
1804 sub-initializer must be suitable as an initializer for the type
1805 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1806
1807 #define REG_CLASS_CONTENTS \
1808 { \
1809 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1810 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1811 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1812 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1813 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1814 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1815 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1816 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1817 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1818 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1819 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1820 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1821 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1822 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1823 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1824 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1825 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1826 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1827 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1828 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1829 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1830 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1831 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1832 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1833 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1834 }
1835
1836
1837 /* A C expression whose value is a register class containing hard
1838 register REGNO. In general there is more that one such class;
1839 choose a class which is "minimal", meaning that no smaller class
1840 also contains the register. */
1841
1842 extern const enum reg_class mips_regno_to_class[];
1843
1844 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1845
1846 /* A macro whose definition is the name of the class to which a
1847 valid base register must belong. A base register is one used in
1848 an address which is the register value plus a displacement. */
1849
1850 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1851
1852 /* A macro whose definition is the name of the class to which a
1853 valid index register must belong. An index register is one used
1854 in an address where its value is either multiplied by a scale
1855 factor or added to another register (as well as added to a
1856 displacement). */
1857
1858 #define INDEX_REG_CLASS NO_REGS
1859
1860 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1861 registers explicitly used in the rtl to be used as spill registers
1862 but prevents the compiler from extending the lifetime of these
1863 registers. */
1864
1865 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1866
1867 /* This macro is used later on in the file. */
1868 #define GR_REG_CLASS_P(CLASS) \
1869 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1870 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1871 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1872
1873 /* This macro is also used later on in the file. */
1874 #define COP_REG_CLASS_P(CLASS) \
1875 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1876
1877 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1878 is the default value (allocate the registers in numeric order). We
1879 define it just so that we can override it for the mips16 target in
1880 ORDER_REGS_FOR_LOCAL_ALLOC. */
1881
1882 #define REG_ALLOC_ORDER \
1883 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1884 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1885 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1886 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1887 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1888 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1889 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1890 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1891 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1892 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1893 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1894 }
1895
1896 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1897 to be rearranged based on a particular function. On the mips16, we
1898 want to allocate $24 (T_REG) before other registers for
1899 instructions for which it is possible. */
1900
1901 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1902
1903 /* REGISTER AND CONSTANT CLASSES */
1904
1905 /* Get reg_class from a letter such as appears in the machine
1906 description.
1907
1908 DEFINED REGISTER CLASSES:
1909
1910 'd' General (aka integer) registers
1911 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1912 'y' General registers (in both mips16 and non mips16 mode)
1913 'e' mips16 non argument registers (M16_NA_REGS)
1914 't' mips16 temporary register ($24)
1915 'f' Floating point registers
1916 'h' Hi register
1917 'l' Lo register
1918 'x' Multiply/divide registers
1919 'z' FP Status register
1920 'B' Cop0 register
1921 'C' Cop2 register
1922 'D' Cop3 register
1923 'b' All registers */
1924
1925 extern enum reg_class mips_char_to_class[256];
1926
1927 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1928
1929 /* True if VALUE is a signed 16-bit number. */
1930
1931 #define SMALL_OPERAND(VALUE) \
1932 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1933
1934 /* True if VALUE is an unsigned 16-bit number. */
1935
1936 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1937 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1938
1939 /* True if VALUE can be loaded into a register using LUI. */
1940
1941 #define LUI_OPERAND(VALUE) \
1942 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1943 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1944
1945 /* Return a value X with the low 16 bits clear, and such that
1946 VALUE - X is a signed 16-bit value. */
1947
1948 #define CONST_HIGH_PART(VALUE) \
1949 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1950
1951 #define CONST_LOW_PART(VALUE) \
1952 ((VALUE) - CONST_HIGH_PART (VALUE))
1953
1954 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1955 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1956 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1957
1958 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1959 string can be used to stand for particular ranges of immediate
1960 operands. This macro defines what the ranges are. C is the
1961 letter, and VALUE is a constant value. Return 1 if VALUE is
1962 in the range specified by C. */
1963
1964 /* For MIPS:
1965
1966 `I' is used for the range of constants an arithmetic insn can
1967 actually contain (16 bits signed integers).
1968
1969 `J' is used for the range which is just zero (ie, $r0).
1970
1971 `K' is used for the range of constants a logical insn can actually
1972 contain (16 bit zero-extended integers).
1973
1974 `L' is used for the range of constants that be loaded with lui
1975 (ie, the bottom 16 bits are zero).
1976
1977 `M' is used for the range of constants that take two words to load
1978 (ie, not matched by `I', `K', and `L').
1979
1980 `N' is used for negative 16 bit constants other than -65536.
1981
1982 `O' is a 15 bit signed integer.
1983
1984 `P' is used for positive 16 bit constants. */
1985
1986 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1987 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1988 : (C) == 'J' ? ((VALUE) == 0) \
1989 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1990 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1991 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1992 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1993 && !LUI_OPERAND (VALUE)) \
1994 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1995 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1996 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1997 : 0)
1998
1999 /* Similar, but for floating constants, and defining letters G and H.
2000 Here VALUE is the CONST_DOUBLE rtx itself. */
2001
2002 /* For Mips
2003
2004 'G' : Floating point 0 */
2005
2006 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2007 ((C) == 'G' \
2008 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2009
2010 /* True if OP is a constant that should not be moved into $25.
2011 We need this because many versions of gas treat 'la $25,foo' as
2012 part of a call sequence and allow a global 'foo' to be lazily bound. */
2013
2014 #define DANGEROUS_FOR_LA25_P(OP) \
2015 (TARGET_ABICALLS \
2016 && !TARGET_EXPLICIT_RELOCS \
2017 && mips_global_pic_constant_p (OP))
2018
2019 /* Letters in the range `Q' through `U' may be defined in a
2020 machine-dependent fashion to stand for arbitrary operand types.
2021 The machine description macro `EXTRA_CONSTRAINT' is passed the
2022 operand as its first argument and the constraint letter as its
2023 second operand.
2024
2025 `Q' is for signed 16-bit constants.
2026 `R' is for single-instruction memory references. Note that this
2027 constraint has often been used in linux and glibc code.
2028 `S' is for legitimate constant call addresses.
2029 `T' is for constant move_operands that cannot be safely loaded into $25.
2030 `U' is for constant move_operands that can be safely loaded into $25. */
2031
2032 #define EXTRA_CONSTRAINT(OP,CODE) \
2033 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2034 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2035 && mips_fetch_insns (OP) == 1) \
2036 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2037 && call_insn_operand (OP, VOIDmode)) \
2038 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2039 && move_operand (OP, VOIDmode) \
2040 && DANGEROUS_FOR_LA25_P (OP)) \
2041 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2042 && move_operand (OP, VOIDmode) \
2043 && !DANGEROUS_FOR_LA25_P (OP)) \
2044 : FALSE)
2045
2046 /* Given an rtx X being reloaded into a reg required to be
2047 in class CLASS, return the class of reg to actually use.
2048 In general this is just CLASS; but on some machines
2049 in some cases it is preferable to use a more restrictive class. */
2050
2051 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2052 ((CLASS) != ALL_REGS \
2053 ? (! TARGET_MIPS16 \
2054 ? (CLASS) \
2055 : ((CLASS) != GR_REGS \
2056 ? (CLASS) \
2057 : M16_REGS)) \
2058 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2059 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2060 ? (TARGET_SOFT_FLOAT \
2061 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2062 : FP_REGS) \
2063 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2064 || GET_MODE (X) == VOIDmode) \
2065 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2066 : (CLASS))))
2067
2068 /* Certain machines have the property that some registers cannot be
2069 copied to some other registers without using memory. Define this
2070 macro on those machines to be a C expression that is nonzero if
2071 objects of mode MODE in registers of CLASS1 can only be copied to
2072 registers of class CLASS2 by storing a register of CLASS1 into
2073 memory and loading that memory location into a register of CLASS2.
2074
2075 Do not define this macro if its value would always be zero. */
2076 #if 0
2077 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2078 ((!TARGET_DEBUG_H_MODE \
2079 && GET_MODE_CLASS (MODE) == MODE_INT \
2080 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2081 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2082 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2083 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2084 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2085 #endif
2086 /* The HI and LO registers can only be reloaded via the general
2087 registers. Condition code registers can only be loaded to the
2088 general registers, and from the floating point registers. */
2089
2090 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2091 mips_secondary_reload_class (CLASS, MODE, X, 1)
2092 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2093 mips_secondary_reload_class (CLASS, MODE, X, 0)
2094
2095 /* Return the maximum number of consecutive registers
2096 needed to represent mode MODE in a register of class CLASS. */
2097
2098 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2099
2100 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2101 mips_cannot_change_mode_class (FROM, TO, CLASS)
2102 \f
2103 /* Stack layout; function entry, exit and calling. */
2104
2105 #define STACK_GROWS_DOWNWARD
2106
2107 /* The offset of the first local variable from the beginning of the frame.
2108 See compute_frame_size for details about the frame layout. */
2109 #define STARTING_FRAME_OFFSET \
2110 (current_function_outgoing_args_size \
2111 + (TARGET_ABICALLS && !TARGET_NEWABI \
2112 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2113
2114 #define RETURN_ADDR_RTX mips_return_addr
2115
2116 /* Since the mips16 ISA mode is encoded in the least-significant bit
2117 of the address, mask it off return addresses for purposes of
2118 finding exception handling regions. */
2119
2120 #define MASK_RETURN_ADDR GEN_INT (-2)
2121
2122
2123 /* Similarly, don't use the least-significant bit to tell pointers to
2124 code from vtable index. */
2125
2126 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2127
2128 /* The eliminations to $17 are only used for mips16 code. See the
2129 definition of HARD_FRAME_POINTER_REGNUM. */
2130
2131 #define ELIMINABLE_REGS \
2132 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2133 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2134 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2135 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2136 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2137 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2138
2139 /* We can always eliminate to the hard frame pointer. We can eliminate
2140 to the stack pointer unless a frame pointer is needed.
2141
2142 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2143 reload may be unable to compute the address of a local variable,
2144 since there is no way to add a large constant to the stack pointer
2145 without using a temporary register.
2146
2147 Also, for some mips16 instructions (eg lwu), we can't eliminate the
2148 frame pointer for the stack pointer. These instructions are
2149 only generated in TARGET_64BIT mode. */
2150 #define CAN_ELIMINATE(FROM, TO) \
2151 ((TO) == HARD_FRAME_POINTER_REGNUM \
2152 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2153 && !(TARGET_MIPS16 && TARGET_64BIT) \
2154 && (!TARGET_MIPS16 \
2155 || compute_frame_size (get_frame_size ()) < 32768)))
2156
2157 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2158 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2159
2160 /* Allocate stack space for arguments at the beginning of each function. */
2161 #define ACCUMULATE_OUTGOING_ARGS 1
2162
2163 /* The argument pointer always points to the first argument. */
2164 #define FIRST_PARM_OFFSET(FNDECL) 0
2165
2166 /* o32 and o64 reserve stack space for all argument registers. */
2167 #define REG_PARM_STACK_SPACE(FNDECL) \
2168 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2169 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2170 : 0)
2171
2172 /* Define this if it is the responsibility of the caller to
2173 allocate the area reserved for arguments passed in registers.
2174 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2175 of this macro is to determine whether the space is included in
2176 `current_function_outgoing_args_size'. */
2177 #define OUTGOING_REG_PARM_STACK_SPACE
2178
2179 #define STACK_BOUNDARY \
2180 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2181 ? 64 : 128)
2182
2183 \f
2184 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2185
2186 /* Symbolic macros for the registers used to return integer and floating
2187 point values. */
2188
2189 #define GP_RETURN (GP_REG_FIRST + 2)
2190 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2191
2192 #define MAX_ARGS_IN_REGISTERS \
2193 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2194
2195 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2196
2197 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2198
2199 /* Symbolic macros for the first/last argument registers. */
2200
2201 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2202 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2203 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2204 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2205
2206 #define LIBCALL_VALUE(MODE) \
2207 mips_function_value (NULL_TREE, NULL, (MODE))
2208
2209 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2210 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2211
2212 /* 1 if N is a possible register number for a function value.
2213 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2214 Currently, R2 and F0 are only implemented here (C has no complex type) */
2215
2216 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2217 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2218 && (N) == FP_RETURN + 2))
2219
2220 /* 1 if N is a possible register number for function argument passing.
2221 We have no FP argument registers when soft-float. When FP registers
2222 are 32 bits, we can't directly reference the odd numbered ones. */
2223
2224 #define FUNCTION_ARG_REGNO_P(N) \
2225 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2226 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2227 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2228 && !fixed_regs[N])
2229
2230 #define RETURN_IN_MEMORY(TYPE) mips_return_in_memory (TYPE)
2231
2232 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2233 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2234 (TYPE), (NO_RTL))
2235 \f
2236 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2237
2238 /* This structure has to cope with two different argument allocation
2239 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2240 first N words go in registers and the rest go on the stack. If I < N,
2241 the Ith word might go in Ith integer argument register or the
2242 Ith floating-point one. For these ABIs, we only need to remember
2243 the number of words passed so far.
2244
2245 The EABI instead allocates the integer and floating-point arguments
2246 separately. The first N words of FP arguments go in FP registers,
2247 the rest go on the stack. Likewise, the first N words of the other
2248 arguments go in integer registers, and the rest go on the stack. We
2249 need to maintain three counts: the number of integer registers used,
2250 the number of floating-point registers used, and the number of words
2251 passed on the stack.
2252
2253 We could keep separate information for the two ABIs (a word count for
2254 the standard ABIs, and three separate counts for the EABI). But it
2255 seems simpler to view the standard ABIs as forms of EABI that do not
2256 allocate floating-point registers.
2257
2258 So for the standard ABIs, the first N words are allocated to integer
2259 registers, and function_arg decides on an argument-by-argument basis
2260 whether that argument should really go in an integer register, or in
2261 a floating-point one. */
2262
2263 typedef struct mips_args {
2264 /* Always true for varargs functions. Otherwise true if at least
2265 one argument has been passed in an integer register. */
2266 int gp_reg_found;
2267
2268 /* The number of arguments seen so far. */
2269 unsigned int arg_number;
2270
2271 /* For EABI, the number of integer registers used so far. For other
2272 ABIs, the number of words passed in registers (whether integer
2273 or floating-point). */
2274 unsigned int num_gprs;
2275
2276 /* For EABI, the number of floating-point registers used so far. */
2277 unsigned int num_fprs;
2278
2279 /* The number of words passed on the stack. */
2280 unsigned int stack_words;
2281
2282 /* On the mips16, we need to keep track of which floating point
2283 arguments were passed in general registers, but would have been
2284 passed in the FP regs if this were a 32 bit function, so that we
2285 can move them to the FP regs if we wind up calling a 32 bit
2286 function. We record this information in fp_code, encoded in base
2287 four. A zero digit means no floating point argument, a one digit
2288 means an SFmode argument, and a two digit means a DFmode argument,
2289 and a three digit is not used. The low order digit is the first
2290 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2291 an SFmode argument. ??? A more sophisticated approach will be
2292 needed if MIPS_ABI != ABI_32. */
2293 int fp_code;
2294
2295 /* True if the function has a prototype. */
2296 int prototype;
2297 } CUMULATIVE_ARGS;
2298
2299 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2300 for a call to a function whose data type is FNTYPE.
2301 For a library call, FNTYPE is 0.
2302
2303 */
2304
2305 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2306 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2307
2308 /* Update the data in CUM to advance over an argument
2309 of mode MODE and data type TYPE.
2310 (TYPE is null for libcalls where that information may not be available.) */
2311
2312 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2313 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2314
2315 /* Determine where to put an argument to a function.
2316 Value is zero to push the argument on the stack,
2317 or a hard register in which to store the argument.
2318
2319 MODE is the argument's machine mode.
2320 TYPE is the data type of the argument (as a tree).
2321 This is null for libcalls where that information may
2322 not be available.
2323 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2324 the preceding args and about the function being called.
2325 NAMED is nonzero if this argument is a named parameter
2326 (otherwise it is an extra parameter matching an ellipsis). */
2327
2328 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2329 function_arg( &CUM, MODE, TYPE, NAMED)
2330
2331 /* For an arg passed partly in registers and partly in memory,
2332 this is the number of registers used.
2333 For args passed entirely in registers or entirely in memory, zero. */
2334
2335 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2336 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2337
2338 /* If defined, a C expression that gives the alignment boundary, in
2339 bits, of an argument with the specified mode and type. If it is
2340 not defined, `PARM_BOUNDARY' is used for all arguments. */
2341
2342 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2343 (((TYPE) != 0) \
2344 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2345 ? PARM_BOUNDARY \
2346 : TYPE_ALIGN(TYPE)) \
2347 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2348 ? PARM_BOUNDARY \
2349 : GET_MODE_ALIGNMENT(MODE)))
2350
2351 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2352 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2353
2354 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2355 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2356
2357 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2358 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2359
2360 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2361 (mips_abi == ABI_EABI && (NAMED) \
2362 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2363
2364 /* Modified version of the macro in expr.h. Only return true if
2365 the type has a variable size or if the front end requires it
2366 to be passed by reference. */
2367 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2368 ((TYPE) != 0 \
2369 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2370 || TREE_ADDRESSABLE (TYPE)))
2371
2372 /* True if using EABI and varargs can be passed in floating-point
2373 registers. Under these conditions, we need a more complex form
2374 of va_list, which tracks GPR, FPR and stack arguments separately. */
2375 #define EABI_FLOAT_VARARGS_P \
2376 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2377
2378 \f
2379 /* Say that the epilogue uses the return address register. Note that
2380 in the case of sibcalls, the values "used by the epilogue" are
2381 considered live at the start of the called function. */
2382 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2383
2384 /* Treat LOC as a byte offset from the stack pointer and round it up
2385 to the next fully-aligned offset. */
2386 #define MIPS_STACK_ALIGN(LOC) \
2387 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2388 ? ((LOC) + 7) & ~7 \
2389 : ((LOC) + 15) & ~15)
2390
2391 \f
2392 /* Define the `__builtin_va_list' type for the ABI. */
2393 #define BUILD_VA_LIST_TYPE(VALIST) \
2394 (VALIST) = mips_build_va_list ()
2395
2396 /* Implement `va_start' for varargs and stdarg. */
2397 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2398 mips_va_start (valist, nextarg)
2399
2400 /* Implement `va_arg'. */
2401 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2402 mips_va_arg (valist, type)
2403 \f
2404 /* Output assembler code to FILE to increment profiler label # LABELNO
2405 for profiling a function entry. */
2406
2407 #define FUNCTION_PROFILER(FILE, LABELNO) \
2408 { \
2409 if (TARGET_MIPS16) \
2410 sorry ("mips16 function profiling"); \
2411 fprintf (FILE, "\t.set\tnoat\n"); \
2412 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2413 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2414 if (mips_abi != ABI_N32 && mips_abi != ABI_64) \
2415 { \
2416 fprintf (FILE, \
2417 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2418 TARGET_64BIT ? "dsubu" : "subu", \
2419 reg_names[STACK_POINTER_REGNUM], \
2420 reg_names[STACK_POINTER_REGNUM], \
2421 Pmode == DImode ? 16 : 8); \
2422 } \
2423 fprintf (FILE, "\tjal\t_mcount\n"); \
2424 fprintf (FILE, "\t.set\tat\n"); \
2425 }
2426
2427 /* Define this macro if the code for function profiling should come
2428 before the function prologue. Normally, the profiling code comes
2429 after. */
2430
2431 /* #define PROFILE_BEFORE_PROLOGUE */
2432
2433 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2434 the stack pointer does not matter. The value is tested only in
2435 functions that have frame pointers.
2436 No definition is equivalent to always zero. */
2437
2438 #define EXIT_IGNORE_STACK 1
2439
2440 \f
2441 /* A C statement to output, on the stream FILE, assembler code for a
2442 block of data that contains the constant parts of a trampoline.
2443 This code should not include a label--the label is taken care of
2444 automatically. */
2445
2446 #define TRAMPOLINE_TEMPLATE(STREAM) \
2447 { \
2448 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2449 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2450 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2451 if (ptr_mode == DImode) \
2452 { \
2453 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2454 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2455 } \
2456 else \
2457 { \
2458 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2459 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2460 } \
2461 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2462 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2463 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2464 if (ptr_mode == DImode) \
2465 { \
2466 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2467 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2468 } \
2469 else \
2470 { \
2471 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2472 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2473 } \
2474 }
2475
2476 /* A C expression for the size in bytes of the trampoline, as an
2477 integer. */
2478
2479 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2480
2481 /* Alignment required for trampolines, in bits. */
2482
2483 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2484
2485 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2486 program and data caches. */
2487
2488 #ifndef CACHE_FLUSH_FUNC
2489 #define CACHE_FLUSH_FUNC "_flush_cache"
2490 #endif
2491
2492 /* A C statement to initialize the variable parts of a trampoline.
2493 ADDR is an RTX for the address of the trampoline; FNADDR is an
2494 RTX for the address of the nested function; STATIC_CHAIN is an
2495 RTX for the static chain value that should be passed to the
2496 function when it is called. */
2497
2498 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2499 { \
2500 rtx func_addr, chain_addr; \
2501 \
2502 func_addr = plus_constant (ADDR, 32); \
2503 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2504 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), \
2505 gen_lowpart (ptr_mode, force_reg (Pmode, FUNC))); \
2506 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), \
2507 gen_lowpart (ptr_mode, force_reg (Pmode, CHAIN))); \
2508 \
2509 /* Flush both caches. We need to flush the data cache in case \
2510 the system has a write-back cache. */ \
2511 /* ??? Should check the return value for errors. */ \
2512 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2513 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2514 0, VOIDmode, 3, ADDR, Pmode, \
2515 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2516 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2517 }
2518 \f
2519 /* Addressing modes, and classification of registers for them. */
2520
2521 /* These assume that REGNO is a hard or pseudo reg number.
2522 They give nonzero only if REGNO is a hard reg of the suitable class
2523 or a pseudo reg currently allocated to a suitable hard reg.
2524 These definitions are NOT overridden anywhere. */
2525
2526 #define BASE_REG_P(regno, mode) \
2527 (TARGET_MIPS16 \
2528 ? (M16_REG_P (regno) \
2529 || (regno) == FRAME_POINTER_REGNUM \
2530 || (regno) == ARG_POINTER_REGNUM \
2531 || ((regno) == STACK_POINTER_REGNUM \
2532 && (GET_MODE_SIZE (mode) == 4 \
2533 || GET_MODE_SIZE (mode) == 8))) \
2534 : GP_REG_P (regno))
2535
2536 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2537 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2538 (mode))
2539
2540 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2541 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2542
2543 #define REGNO_OK_FOR_INDEX_P(regno) 0
2544 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2545 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2546
2547 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2548 and check its validity for a certain class.
2549 We have two alternate definitions for each of them.
2550 The usual definition accepts all pseudo regs; the other rejects them all.
2551 The symbol REG_OK_STRICT causes the latter definition to be used.
2552
2553 Most source files want to accept pseudo regs in the hope that
2554 they will get allocated to the class that the insn wants them to be in.
2555 Some source files that are used after register allocation
2556 need to be strict. */
2557
2558 #ifndef REG_OK_STRICT
2559 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2560 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2561 #else
2562 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2563 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2564 #endif
2565
2566 #define REG_OK_FOR_INDEX_P(X) 0
2567
2568 \f
2569 /* Maximum number of registers that can appear in a valid memory address. */
2570
2571 #define MAX_REGS_PER_ADDRESS 1
2572
2573 /* A C compound statement with a conditional `goto LABEL;' executed
2574 if X (an RTX) is a legitimate memory address on the target
2575 machine for a memory operand of mode MODE. */
2576
2577 #if 1
2578 #define GO_PRINTF(x) fprintf(stderr, (x))
2579 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2580 #define GO_DEBUG_RTX(x) debug_rtx(x)
2581
2582 #else
2583 #define GO_PRINTF(x)
2584 #define GO_PRINTF2(x,y)
2585 #define GO_DEBUG_RTX(x)
2586 #endif
2587
2588 #ifdef REG_OK_STRICT
2589 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2590 { \
2591 if (mips_legitimate_address_p (MODE, X, 1)) \
2592 goto ADDR; \
2593 }
2594 #else
2595 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2596 { \
2597 if (mips_legitimate_address_p (MODE, X, 0)) \
2598 goto ADDR; \
2599 }
2600 #endif
2601
2602 /* Check for constness inline but use mips_legitimate_address_p
2603 to check whether a constant really is an address. */
2604
2605 #define CONSTANT_ADDRESS_P(X) \
2606 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2607
2608 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2609
2610 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2611 do { \
2612 if (mips_legitimize_address (&(X), MODE)) \
2613 goto WIN; \
2614 } while (0)
2615
2616
2617 /* A C statement or compound statement with a conditional `goto
2618 LABEL;' executed if memory address X (an RTX) can have different
2619 meanings depending on the machine mode of the memory reference it
2620 is used for.
2621
2622 Autoincrement and autodecrement addresses typically have
2623 mode-dependent effects because the amount of the increment or
2624 decrement is the size of the operand being addressed. Some
2625 machines have other mode-dependent addresses. Many RISC machines
2626 have no mode-dependent addresses.
2627
2628 You may assume that ADDR is a valid address for the machine. */
2629
2630 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2631
2632 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2633 'the start of the function that this code is output in'. */
2634
2635 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2636 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2637 asm_fprintf ((FILE), "%U%s", \
2638 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2639 else \
2640 asm_fprintf ((FILE), "%U%s", (NAME))
2641
2642 /* The mips16 wants the constant pool to be after the function,
2643 because the PC relative load instructions use unsigned offsets. */
2644
2645 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
2646
2647 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
2648 mips_string_length = 0;
2649 \f
2650 /* Specify the machine mode that this machine uses
2651 for the index in the tablejump instruction.
2652 ??? Using HImode in mips16 mode can cause overflow. */
2653 #define CASE_VECTOR_MODE \
2654 (TARGET_MIPS16 ? HImode : ptr_mode)
2655
2656 /* Define as C expression which evaluates to nonzero if the tablejump
2657 instruction expects the table to contain offsets from the address of the
2658 table.
2659 Do not define this if the table should contain absolute addresses. */
2660 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2661
2662 /* Define this as 1 if `char' should by default be signed; else as 0. */
2663 #ifndef DEFAULT_SIGNED_CHAR
2664 #define DEFAULT_SIGNED_CHAR 1
2665 #endif
2666
2667 /* Max number of bytes we can move from memory to memory
2668 in one reasonably fast instruction. */
2669 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2670 #define MAX_MOVE_MAX 8
2671
2672 /* Define this macro as a C expression which is nonzero if
2673 accessing less than a word of memory (i.e. a `char' or a
2674 `short') is no faster than accessing a word of memory, i.e., if
2675 such access require more than one instruction or if there is no
2676 difference in cost between byte and (aligned) word loads.
2677
2678 On RISC machines, it tends to generate better code to define
2679 this as 1, since it avoids making a QI or HI mode register. */
2680 #define SLOW_BYTE_ACCESS 1
2681
2682 /* Define this to be nonzero if shift instructions ignore all but the low-order
2683 few bits. */
2684 #define SHIFT_COUNT_TRUNCATED 1
2685
2686 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2687 is done just by pretending it is already truncated. */
2688 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2689 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2690
2691
2692 /* Specify the machine mode that pointers have.
2693 After generation of rtl, the compiler makes no further distinction
2694 between pointers and any other objects of this machine mode. */
2695
2696 #ifndef Pmode
2697 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2698 #endif
2699
2700 /* Give call MEMs SImode since it is the "most permissive" mode
2701 for both 32-bit and 64-bit targets. */
2702
2703 #define FUNCTION_MODE SImode
2704
2705 \f
2706 /* The cost of loading values from the constant pool. It should be
2707 larger than the cost of any constant we want to synthesize in-line. */
2708
2709 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2710
2711 /* A C expression for the cost of moving data from a register in
2712 class FROM to one in class TO. The classes are expressed using
2713 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2714 the default; other values are interpreted relative to that.
2715
2716 It is not required that the cost always equal 2 when FROM is the
2717 same as TO; on some machines it is expensive to move between
2718 registers if they are not general registers.
2719
2720 If reload sees an insn consisting of a single `set' between two
2721 hard registers, and if `REGISTER_MOVE_COST' applied to their
2722 classes returns a value of 2, reload does not check to ensure
2723 that the constraints of the insn are met. Setting a cost of
2724 other than 2 will allow reload to verify that the constraints are
2725 met. You should do this if the `movM' pattern's constraints do
2726 not allow such copying. */
2727
2728 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2729 mips_register_move_cost (MODE, FROM, TO)
2730
2731 /* ??? Fix this to be right for the R8000. */
2732 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2733 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2734 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2735
2736 /* Define if copies to/from condition code registers should be avoided.
2737
2738 This is needed for the MIPS because reload_outcc is not complete;
2739 it needs to handle cases where the source is a general or another
2740 condition code register. */
2741 #define AVOID_CCMODE_COPIES
2742
2743 /* A C expression for the cost of a branch instruction. A value of
2744 1 is the default; other values are interpreted relative to that. */
2745
2746 /* ??? Fix this to be right for the R8000. */
2747 #define BRANCH_COST \
2748 ((! TARGET_MIPS16 \
2749 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2750 ? 2 : 1)
2751
2752 /* If defined, modifies the length assigned to instruction INSN as a
2753 function of the context in which it is used. LENGTH is an lvalue
2754 that contains the initially computed length of the insn and should
2755 be updated with the correct length of the insn. */
2756 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2757 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2758
2759 \f
2760 /* Optionally define this if you have added predicates to
2761 `MACHINE.c'. This macro is called within an initializer of an
2762 array of structures. The first field in the structure is the
2763 name of a predicate and the second field is an array of rtl
2764 codes. For each predicate, list all rtl codes that can be in
2765 expressions matched by the predicate. The list should have a
2766 trailing comma. Here is an example of two entries in the list
2767 for a typical RISC machine:
2768
2769 #define PREDICATE_CODES \
2770 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2771 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2772
2773 Defining this macro does not affect the generated code (however,
2774 incorrect definitions that omit an rtl code that may be matched
2775 by the predicate can cause the compiler to malfunction).
2776 Instead, it allows the table built by `genrecog' to be more
2777 compact and efficient, thus speeding up the compiler. The most
2778 important predicates to include in the list specified by this
2779 macro are thoses used in the most insn patterns. */
2780
2781 #define PREDICATE_CODES \
2782 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2783 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2784 {"const_arith_operand", { CONST, CONST_INT }}, \
2785 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2786 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2787 {"small_int", { CONST_INT }}, \
2788 {"mips_const_double_ok", { CONST_DOUBLE }}, \
2789 {"const_float_1_operand", { CONST_DOUBLE }}, \
2790 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2791 {"simple_memory_operand", { MEM, SUBREG }}, \
2792 {"equality_op", { EQ, NE }}, \
2793 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2794 LTU, LEU }}, \
2795 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2796 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2797 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2798 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2799 SYMBOL_REF, LABEL_REF, SUBREG, \
2800 REG, MEM}}, \
2801 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2802 CONST_DOUBLE, CONST }}, \
2803 {"fcc_register_operand", { REG, SUBREG }}, \
2804 {"hilo_operand", { REG }}, \
2805 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2806
2807 /* A list of predicates that do special things with modes, and so
2808 should not elicit warnings for VOIDmode match_operand. */
2809
2810 #define SPECIAL_MODE_PREDICATES \
2811 "pc_or_label_operand",
2812 \f
2813 /* Control the assembler format that we output. */
2814
2815 /* Output to assembler file text saying following lines
2816 may contain character constants, extra white space, comments, etc. */
2817
2818 #ifndef ASM_APP_ON
2819 #define ASM_APP_ON " #APP\n"
2820 #endif
2821
2822 /* Output to assembler file text saying following lines
2823 no longer contain unusual constructs. */
2824
2825 #ifndef ASM_APP_OFF
2826 #define ASM_APP_OFF " #NO_APP\n"
2827 #endif
2828
2829 /* How to refer to registers in assembler output.
2830 This sequence is indexed by compiler's hard-register-number (see above).
2831
2832 In order to support the two different conventions for register names,
2833 we use the name of a table set up in mips.c, which is overwritten
2834 if -mrnames is used. */
2835
2836 #define REGISTER_NAMES \
2837 { \
2838 &mips_reg_names[ 0][0], \
2839 &mips_reg_names[ 1][0], \
2840 &mips_reg_names[ 2][0], \
2841 &mips_reg_names[ 3][0], \
2842 &mips_reg_names[ 4][0], \
2843 &mips_reg_names[ 5][0], \
2844 &mips_reg_names[ 6][0], \
2845 &mips_reg_names[ 7][0], \
2846 &mips_reg_names[ 8][0], \
2847 &mips_reg_names[ 9][0], \
2848 &mips_reg_names[10][0], \
2849 &mips_reg_names[11][0], \
2850 &mips_reg_names[12][0], \
2851 &mips_reg_names[13][0], \
2852 &mips_reg_names[14][0], \
2853 &mips_reg_names[15][0], \
2854 &mips_reg_names[16][0], \
2855 &mips_reg_names[17][0], \
2856 &mips_reg_names[18][0], \
2857 &mips_reg_names[19][0], \
2858 &mips_reg_names[20][0], \
2859 &mips_reg_names[21][0], \
2860 &mips_reg_names[22][0], \
2861 &mips_reg_names[23][0], \
2862 &mips_reg_names[24][0], \
2863 &mips_reg_names[25][0], \
2864 &mips_reg_names[26][0], \
2865 &mips_reg_names[27][0], \
2866 &mips_reg_names[28][0], \
2867 &mips_reg_names[29][0], \
2868 &mips_reg_names[30][0], \
2869 &mips_reg_names[31][0], \
2870 &mips_reg_names[32][0], \
2871 &mips_reg_names[33][0], \
2872 &mips_reg_names[34][0], \
2873 &mips_reg_names[35][0], \
2874 &mips_reg_names[36][0], \
2875 &mips_reg_names[37][0], \
2876 &mips_reg_names[38][0], \
2877 &mips_reg_names[39][0], \
2878 &mips_reg_names[40][0], \
2879 &mips_reg_names[41][0], \
2880 &mips_reg_names[42][0], \
2881 &mips_reg_names[43][0], \
2882 &mips_reg_names[44][0], \
2883 &mips_reg_names[45][0], \
2884 &mips_reg_names[46][0], \
2885 &mips_reg_names[47][0], \
2886 &mips_reg_names[48][0], \
2887 &mips_reg_names[49][0], \
2888 &mips_reg_names[50][0], \
2889 &mips_reg_names[51][0], \
2890 &mips_reg_names[52][0], \
2891 &mips_reg_names[53][0], \
2892 &mips_reg_names[54][0], \
2893 &mips_reg_names[55][0], \
2894 &mips_reg_names[56][0], \
2895 &mips_reg_names[57][0], \
2896 &mips_reg_names[58][0], \
2897 &mips_reg_names[59][0], \
2898 &mips_reg_names[60][0], \
2899 &mips_reg_names[61][0], \
2900 &mips_reg_names[62][0], \
2901 &mips_reg_names[63][0], \
2902 &mips_reg_names[64][0], \
2903 &mips_reg_names[65][0], \
2904 &mips_reg_names[66][0], \
2905 &mips_reg_names[67][0], \
2906 &mips_reg_names[68][0], \
2907 &mips_reg_names[69][0], \
2908 &mips_reg_names[70][0], \
2909 &mips_reg_names[71][0], \
2910 &mips_reg_names[72][0], \
2911 &mips_reg_names[73][0], \
2912 &mips_reg_names[74][0], \
2913 &mips_reg_names[75][0], \
2914 &mips_reg_names[76][0], \
2915 &mips_reg_names[77][0], \
2916 &mips_reg_names[78][0], \
2917 &mips_reg_names[79][0], \
2918 &mips_reg_names[80][0], \
2919 &mips_reg_names[81][0], \
2920 &mips_reg_names[82][0], \
2921 &mips_reg_names[83][0], \
2922 &mips_reg_names[84][0], \
2923 &mips_reg_names[85][0], \
2924 &mips_reg_names[86][0], \
2925 &mips_reg_names[87][0], \
2926 &mips_reg_names[88][0], \
2927 &mips_reg_names[89][0], \
2928 &mips_reg_names[90][0], \
2929 &mips_reg_names[91][0], \
2930 &mips_reg_names[92][0], \
2931 &mips_reg_names[93][0], \
2932 &mips_reg_names[94][0], \
2933 &mips_reg_names[95][0], \
2934 &mips_reg_names[96][0], \
2935 &mips_reg_names[97][0], \
2936 &mips_reg_names[98][0], \
2937 &mips_reg_names[99][0], \
2938 &mips_reg_names[100][0], \
2939 &mips_reg_names[101][0], \
2940 &mips_reg_names[102][0], \
2941 &mips_reg_names[103][0], \
2942 &mips_reg_names[104][0], \
2943 &mips_reg_names[105][0], \
2944 &mips_reg_names[106][0], \
2945 &mips_reg_names[107][0], \
2946 &mips_reg_names[108][0], \
2947 &mips_reg_names[109][0], \
2948 &mips_reg_names[110][0], \
2949 &mips_reg_names[111][0], \
2950 &mips_reg_names[112][0], \
2951 &mips_reg_names[113][0], \
2952 &mips_reg_names[114][0], \
2953 &mips_reg_names[115][0], \
2954 &mips_reg_names[116][0], \
2955 &mips_reg_names[117][0], \
2956 &mips_reg_names[118][0], \
2957 &mips_reg_names[119][0], \
2958 &mips_reg_names[120][0], \
2959 &mips_reg_names[121][0], \
2960 &mips_reg_names[122][0], \
2961 &mips_reg_names[123][0], \
2962 &mips_reg_names[124][0], \
2963 &mips_reg_names[125][0], \
2964 &mips_reg_names[126][0], \
2965 &mips_reg_names[127][0], \
2966 &mips_reg_names[128][0], \
2967 &mips_reg_names[129][0], \
2968 &mips_reg_names[130][0], \
2969 &mips_reg_names[131][0], \
2970 &mips_reg_names[132][0], \
2971 &mips_reg_names[133][0], \
2972 &mips_reg_names[134][0], \
2973 &mips_reg_names[135][0], \
2974 &mips_reg_names[136][0], \
2975 &mips_reg_names[137][0], \
2976 &mips_reg_names[138][0], \
2977 &mips_reg_names[139][0], \
2978 &mips_reg_names[140][0], \
2979 &mips_reg_names[141][0], \
2980 &mips_reg_names[142][0], \
2981 &mips_reg_names[143][0], \
2982 &mips_reg_names[144][0], \
2983 &mips_reg_names[145][0], \
2984 &mips_reg_names[146][0], \
2985 &mips_reg_names[147][0], \
2986 &mips_reg_names[148][0], \
2987 &mips_reg_names[149][0], \
2988 &mips_reg_names[150][0], \
2989 &mips_reg_names[151][0], \
2990 &mips_reg_names[152][0], \
2991 &mips_reg_names[153][0], \
2992 &mips_reg_names[154][0], \
2993 &mips_reg_names[155][0], \
2994 &mips_reg_names[156][0], \
2995 &mips_reg_names[157][0], \
2996 &mips_reg_names[158][0], \
2997 &mips_reg_names[159][0], \
2998 &mips_reg_names[160][0], \
2999 &mips_reg_names[161][0], \
3000 &mips_reg_names[162][0], \
3001 &mips_reg_names[163][0], \
3002 &mips_reg_names[164][0], \
3003 &mips_reg_names[165][0], \
3004 &mips_reg_names[166][0], \
3005 &mips_reg_names[167][0], \
3006 &mips_reg_names[168][0], \
3007 &mips_reg_names[169][0], \
3008 &mips_reg_names[170][0], \
3009 &mips_reg_names[171][0], \
3010 &mips_reg_names[172][0], \
3011 &mips_reg_names[173][0], \
3012 &mips_reg_names[174][0], \
3013 &mips_reg_names[175][0] \
3014 }
3015
3016 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3017 So define this for it. */
3018 #define DEBUG_REGISTER_NAMES \
3019 { \
3020 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
3021 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
3022 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
3023 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
3024 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
3025 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
3026 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
3027 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
3028 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
3029 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
3030 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
3031 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
3032 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
3033 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
3034 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
3035 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
3036 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
3037 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
3038 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
3039 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
3040 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
3041 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
3042 }
3043
3044 /* If defined, a C initializer for an array of structures
3045 containing a name and a register number. This macro defines
3046 additional names for hard registers, thus allowing the `asm'
3047 option in declarations to refer to registers using alternate
3048 names.
3049
3050 We define both names for the integer registers here. */
3051
3052 #define ADDITIONAL_REGISTER_NAMES \
3053 { \
3054 { "$0", 0 + GP_REG_FIRST }, \
3055 { "$1", 1 + GP_REG_FIRST }, \
3056 { "$2", 2 + GP_REG_FIRST }, \
3057 { "$3", 3 + GP_REG_FIRST }, \
3058 { "$4", 4 + GP_REG_FIRST }, \
3059 { "$5", 5 + GP_REG_FIRST }, \
3060 { "$6", 6 + GP_REG_FIRST }, \
3061 { "$7", 7 + GP_REG_FIRST }, \
3062 { "$8", 8 + GP_REG_FIRST }, \
3063 { "$9", 9 + GP_REG_FIRST }, \
3064 { "$10", 10 + GP_REG_FIRST }, \
3065 { "$11", 11 + GP_REG_FIRST }, \
3066 { "$12", 12 + GP_REG_FIRST }, \
3067 { "$13", 13 + GP_REG_FIRST }, \
3068 { "$14", 14 + GP_REG_FIRST }, \
3069 { "$15", 15 + GP_REG_FIRST }, \
3070 { "$16", 16 + GP_REG_FIRST }, \
3071 { "$17", 17 + GP_REG_FIRST }, \
3072 { "$18", 18 + GP_REG_FIRST }, \
3073 { "$19", 19 + GP_REG_FIRST }, \
3074 { "$20", 20 + GP_REG_FIRST }, \
3075 { "$21", 21 + GP_REG_FIRST }, \
3076 { "$22", 22 + GP_REG_FIRST }, \
3077 { "$23", 23 + GP_REG_FIRST }, \
3078 { "$24", 24 + GP_REG_FIRST }, \
3079 { "$25", 25 + GP_REG_FIRST }, \
3080 { "$26", 26 + GP_REG_FIRST }, \
3081 { "$27", 27 + GP_REG_FIRST }, \
3082 { "$28", 28 + GP_REG_FIRST }, \
3083 { "$29", 29 + GP_REG_FIRST }, \
3084 { "$30", 30 + GP_REG_FIRST }, \
3085 { "$31", 31 + GP_REG_FIRST }, \
3086 { "$sp", 29 + GP_REG_FIRST }, \
3087 { "$fp", 30 + GP_REG_FIRST }, \
3088 { "at", 1 + GP_REG_FIRST }, \
3089 { "v0", 2 + GP_REG_FIRST }, \
3090 { "v1", 3 + GP_REG_FIRST }, \
3091 { "a0", 4 + GP_REG_FIRST }, \
3092 { "a1", 5 + GP_REG_FIRST }, \
3093 { "a2", 6 + GP_REG_FIRST }, \
3094 { "a3", 7 + GP_REG_FIRST }, \
3095 { "t0", 8 + GP_REG_FIRST }, \
3096 { "t1", 9 + GP_REG_FIRST }, \
3097 { "t2", 10 + GP_REG_FIRST }, \
3098 { "t3", 11 + GP_REG_FIRST }, \
3099 { "t4", 12 + GP_REG_FIRST }, \
3100 { "t5", 13 + GP_REG_FIRST }, \
3101 { "t6", 14 + GP_REG_FIRST }, \
3102 { "t7", 15 + GP_REG_FIRST }, \
3103 { "s0", 16 + GP_REG_FIRST }, \
3104 { "s1", 17 + GP_REG_FIRST }, \
3105 { "s2", 18 + GP_REG_FIRST }, \
3106 { "s3", 19 + GP_REG_FIRST }, \
3107 { "s4", 20 + GP_REG_FIRST }, \
3108 { "s5", 21 + GP_REG_FIRST }, \
3109 { "s6", 22 + GP_REG_FIRST }, \
3110 { "s7", 23 + GP_REG_FIRST }, \
3111 { "t8", 24 + GP_REG_FIRST }, \
3112 { "t9", 25 + GP_REG_FIRST }, \
3113 { "k0", 26 + GP_REG_FIRST }, \
3114 { "k1", 27 + GP_REG_FIRST }, \
3115 { "gp", 28 + GP_REG_FIRST }, \
3116 { "sp", 29 + GP_REG_FIRST }, \
3117 { "fp", 30 + GP_REG_FIRST }, \
3118 { "ra", 31 + GP_REG_FIRST }, \
3119 { "$sp", 29 + GP_REG_FIRST }, \
3120 { "$fp", 30 + GP_REG_FIRST } \
3121 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3122 }
3123
3124 /* This is meant to be redefined in the host dependent files. It is a
3125 set of alternative names and regnums for mips coprocessors. */
3126
3127 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3128
3129 /* A C compound statement to output to stdio stream STREAM the
3130 assembler syntax for an instruction operand X. X is an RTL
3131 expression.
3132
3133 CODE is a value that can be used to specify one of several ways
3134 of printing the operand. It is used when identical operands
3135 must be printed differently depending on the context. CODE
3136 comes from the `%' specification that was used to request
3137 printing of the operand. If the specification was just `%DIGIT'
3138 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3139 is the ASCII code for LTR.
3140
3141 If X is a register, this macro should print the register's name.
3142 The names can be found in an array `reg_names' whose type is
3143 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3144
3145 When the machine description has a specification `%PUNCT' (a `%'
3146 followed by a punctuation character), this macro is called with
3147 a null pointer for X and the punctuation character for CODE.
3148
3149 See mips.c for the MIPS specific codes. */
3150
3151 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3152
3153 /* A C expression which evaluates to true if CODE is a valid
3154 punctuation character for use in the `PRINT_OPERAND' macro. If
3155 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3156 punctuation characters (except for the standard one, `%') are
3157 used in this way. */
3158
3159 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3160
3161 /* A C compound statement to output to stdio stream STREAM the
3162 assembler syntax for an instruction operand that is a memory
3163 reference whose address is ADDR. ADDR is an RTL expression. */
3164
3165 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3166
3167
3168 /* A C statement, to be executed after all slot-filler instructions
3169 have been output. If necessary, call `dbr_sequence_length' to
3170 determine the number of slots filled in a sequence (zero if not
3171 currently outputting a sequence), to decide how many no-ops to
3172 output, or whatever.
3173
3174 Don't define this macro if it has nothing to do, but it is
3175 helpful in reading assembly output if the extent of the delay
3176 sequence is made explicit (e.g. with white space).
3177
3178 Note that output routines for instructions with delay slots must
3179 be prepared to deal with not being output as part of a sequence
3180 (i.e. when the scheduling pass is not run, or when no slot
3181 fillers could be found.) The variable `final_sequence' is null
3182 when not processing a sequence, otherwise it contains the
3183 `sequence' rtx being output. */
3184
3185 #define DBR_OUTPUT_SEQEND(STREAM) \
3186 do \
3187 { \
3188 if (set_nomacro > 0 && --set_nomacro == 0) \
3189 fputs ("\t.set\tmacro\n", STREAM); \
3190 \
3191 if (set_noreorder > 0 && --set_noreorder == 0) \
3192 fputs ("\t.set\treorder\n", STREAM); \
3193 \
3194 fputs ("\n", STREAM); \
3195 } \
3196 while (0)
3197
3198
3199 /* How to tell the debugger about changes of source files. */
3200
3201 #ifndef SET_FILE_NUMBER
3202 #define SET_FILE_NUMBER() ++num_source_filenames
3203 #endif
3204
3205 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3206 mips_output_filename (STREAM, NAME)
3207
3208 /* This is defined so that it can be overridden in iris6.h. */
3209 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3210 do \
3211 { \
3212 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3213 output_quoted_string (STREAM, NAME); \
3214 fputs ("\n", STREAM); \
3215 } \
3216 while (0)
3217
3218 /* This is how to output a note the debugger telling it the line number
3219 to which the following sequence of instructions corresponds.
3220 Silicon graphics puts a label after each .loc. */
3221
3222 #ifndef LABEL_AFTER_LOC
3223 #define LABEL_AFTER_LOC(STREAM)
3224 #endif
3225
3226 #ifndef ASM_OUTPUT_SOURCE_LINE
3227 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3228 mips_output_lineno (STREAM, LINE)
3229 #endif
3230
3231 /* The MIPS implementation uses some labels for its own purpose. The
3232 following lists what labels are created, and are all formed by the
3233 pattern $L[a-z].*. The machine independent portion of GCC creates
3234 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3235
3236 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3237 $Lb[0-9]+ Begin blocks for MIPS debug support
3238 $Lc[0-9]+ Label for use in s<xx> operation.
3239 $Le[0-9]+ End blocks for MIPS debug support */
3240
3241 #undef ASM_DECLARE_OBJECT_NAME
3242 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3243 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3244
3245 /* Globalizing directive for a label. */
3246 #define GLOBAL_ASM_OP "\t.globl\t"
3247
3248 /* This says how to define a global common symbol. */
3249
3250 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
3251 do { \
3252 /* If the target wants uninitialized const declarations in \
3253 .rdata then don't put them in .comm */ \
3254 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
3255 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
3256 && (DECL_INITIAL (DECL) == 0 \
3257 || DECL_INITIAL (DECL) == error_mark_node)) \
3258 { \
3259 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
3260 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
3261 \
3262 readonly_data_section (); \
3263 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
3264 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
3265 (SIZE)); \
3266 } \
3267 else \
3268 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
3269 (SIZE)); \
3270 } while (0)
3271
3272
3273 /* This says how to define a local common symbol (ie, not visible to
3274 linker). */
3275
3276 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3277 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3278
3279
3280 /* This says how to output an external. It would be possible not to
3281 output anything and let undefined symbol become external. However
3282 the assembler uses length information on externals to allocate in
3283 data/sdata bss/sbss, thereby saving exec time. */
3284
3285 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3286 mips_output_external(STREAM,DECL,NAME)
3287
3288
3289 /* This is how to declare a function name. The actual work of
3290 emitting the label is moved to function_prologue, so that we can
3291 get the line number correctly emitted before the .ent directive,
3292 and after any .file directives. Define as empty so that the function
3293 is not declared before the .ent directive elsewhere. */
3294
3295 #undef ASM_DECLARE_FUNCTION_NAME
3296 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3297
3298 /* This is how to store into the string LABEL
3299 the symbol_ref name of an internal numbered label where
3300 PREFIX is the class of label and NUM is the number within the class.
3301 This is suitable for output with `assemble_name'. */
3302
3303 #undef ASM_GENERATE_INTERNAL_LABEL
3304 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3305 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3306
3307 /* This is how to output an element of a case-vector that is absolute. */
3308
3309 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3310 fprintf (STREAM, "\t%s\t%sL%d\n", \
3311 ptr_mode == DImode ? ".dword" : ".word", \
3312 LOCAL_LABEL_PREFIX, \
3313 VALUE)
3314
3315 /* This is how to output an element of a case-vector that is relative.
3316 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3317 TARGET_EMBEDDED_PIC). */
3318
3319 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3320 do { \
3321 if (TARGET_MIPS16) \
3322 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3323 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3324 else if (TARGET_EMBEDDED_PIC) \
3325 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3326 ptr_mode == DImode ? ".dword" : ".word", \
3327 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3328 else if (TARGET_GPWORD) \
3329 fprintf (STREAM, "\t%s\t%sL%d\n", \
3330 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3331 LOCAL_LABEL_PREFIX, VALUE); \
3332 else \
3333 fprintf (STREAM, "\t%s\t%sL%d\n", \
3334 ptr_mode == DImode ? ".dword" : ".word", \
3335 LOCAL_LABEL_PREFIX, VALUE); \
3336 } while (0)
3337
3338 /* When generating embedded PIC or mips16 code we want to put the jump
3339 table in the .text section. In all other cases, we want to put the
3340 jump table in the .rdata section. Unfortunately, we can't use
3341 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3342 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3343 section if appropriate. */
3344 #undef ASM_OUTPUT_CASE_LABEL
3345 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3346 do { \
3347 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3348 function_section (current_function_decl); \
3349 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3350 } while (0)
3351
3352 /* This is how to output an assembler line
3353 that says to advance the location counter
3354 to a multiple of 2**LOG bytes. */
3355
3356 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3357 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3358
3359 /* This is how to output an assembler line to advance the location
3360 counter by SIZE bytes. */
3361
3362 #undef ASM_OUTPUT_SKIP
3363 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3364 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3365
3366 /* This is how to output a string. */
3367 #undef ASM_OUTPUT_ASCII
3368 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3369 mips_output_ascii (STREAM, STRING, LEN)
3370
3371 /* Output #ident as a in the read-only data section. */
3372 #undef ASM_OUTPUT_IDENT
3373 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3374 { \
3375 const char *p = STRING; \
3376 int size = strlen (p) + 1; \
3377 readonly_data_section (); \
3378 assemble_string (p, size); \
3379 }
3380 \f
3381 /* Default to -G 8 */
3382 #ifndef MIPS_DEFAULT_GVALUE
3383 #define MIPS_DEFAULT_GVALUE 8
3384 #endif
3385
3386 /* Define the strings to put out for each section in the object file. */
3387 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3388 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3389 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3390
3391 #undef READONLY_DATA_SECTION_ASM_OP
3392 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3393
3394 /* Given a decl node or constant node, choose the section to output it in
3395 and select that section. */
3396
3397 #undef TARGET_ASM_SELECT_SECTION
3398 #define TARGET_ASM_SELECT_SECTION mips_select_section
3399 \f
3400 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3401 do \
3402 { \
3403 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3404 TARGET_64BIT ? "dsubu" : "subu", \
3405 reg_names[STACK_POINTER_REGNUM], \
3406 reg_names[STACK_POINTER_REGNUM], \
3407 TARGET_64BIT ? "sd" : "sw", \
3408 reg_names[REGNO], \
3409 reg_names[STACK_POINTER_REGNUM]); \
3410 } \
3411 while (0)
3412
3413 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3414 do \
3415 { \
3416 if (! set_noreorder) \
3417 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3418 \
3419 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3420 TARGET_64BIT ? "ld" : "lw", \
3421 reg_names[REGNO], \
3422 reg_names[STACK_POINTER_REGNUM], \
3423 TARGET_64BIT ? "daddu" : "addu", \
3424 reg_names[STACK_POINTER_REGNUM], \
3425 reg_names[STACK_POINTER_REGNUM]); \
3426 \
3427 if (! set_noreorder) \
3428 fprintf (STREAM, "\t.set\treorder\n"); \
3429 } \
3430 while (0)
3431
3432 /* How to start an assembler comment.
3433 The leading space is important (the mips native assembler requires it). */
3434 #ifndef ASM_COMMENT_START
3435 #define ASM_COMMENT_START " #"
3436 #endif
3437 \f
3438 /* Default definitions for size_t and ptrdiff_t. We must override the
3439 definitions from ../svr4.h on mips-*-linux-gnu. */
3440
3441 #undef SIZE_TYPE
3442 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3443
3444 #undef PTRDIFF_TYPE
3445 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3446
3447 /* See mips_expand_prologue's use of loadgp for when this should be
3448 true. */
3449
3450 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
3451 && mips_abi != ABI_32 \
3452 && mips_abi != ABI_O64)
3453 \f
3454 /* We need to use a special set of functions to handle hard floating
3455 point code in mips16 mode. */
3456
3457 #ifndef INIT_SUBTARGET_OPTABS
3458 #define INIT_SUBTARGET_OPTABS
3459 #endif
3460
3461 #define INIT_TARGET_OPTABS \
3462 do \
3463 { \
3464 if (! TARGET_MIPS16 || ! mips16_hard_float) \
3465 INIT_SUBTARGET_OPTABS; \
3466 else \
3467 { \
3468 add_optab->handlers[(int) SFmode].libfunc = \
3469 init_one_libfunc ("__mips16_addsf3"); \
3470 sub_optab->handlers[(int) SFmode].libfunc = \
3471 init_one_libfunc ("__mips16_subsf3"); \
3472 smul_optab->handlers[(int) SFmode].libfunc = \
3473 init_one_libfunc ("__mips16_mulsf3"); \
3474 sdiv_optab->handlers[(int) SFmode].libfunc = \
3475 init_one_libfunc ("__mips16_divsf3"); \
3476 \
3477 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
3478 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
3479 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
3480 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
3481 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
3482 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
3483 \
3484 floatsisf_libfunc = \
3485 init_one_libfunc ("__mips16_floatsisf"); \
3486 fixsfsi_libfunc = \
3487 init_one_libfunc ("__mips16_fixsfsi"); \
3488 \
3489 if (TARGET_DOUBLE_FLOAT) \
3490 { \
3491 add_optab->handlers[(int) DFmode].libfunc = \
3492 init_one_libfunc ("__mips16_adddf3"); \
3493 sub_optab->handlers[(int) DFmode].libfunc = \
3494 init_one_libfunc ("__mips16_subdf3"); \
3495 smul_optab->handlers[(int) DFmode].libfunc = \
3496 init_one_libfunc ("__mips16_muldf3"); \
3497 sdiv_optab->handlers[(int) DFmode].libfunc = \
3498 init_one_libfunc ("__mips16_divdf3"); \
3499 \
3500 extendsfdf2_libfunc = \
3501 init_one_libfunc ("__mips16_extendsfdf2"); \
3502 truncdfsf2_libfunc = \
3503 init_one_libfunc ("__mips16_truncdfsf2"); \
3504 \
3505 eqdf2_libfunc = \
3506 init_one_libfunc ("__mips16_eqdf2"); \
3507 nedf2_libfunc = \
3508 init_one_libfunc ("__mips16_nedf2"); \
3509 gtdf2_libfunc = \
3510 init_one_libfunc ("__mips16_gtdf2"); \
3511 gedf2_libfunc = \
3512 init_one_libfunc ("__mips16_gedf2"); \
3513 ltdf2_libfunc = \
3514 init_one_libfunc ("__mips16_ltdf2"); \
3515 ledf2_libfunc = \
3516 init_one_libfunc ("__mips16_ledf2"); \
3517 \
3518 floatsidf_libfunc = \
3519 init_one_libfunc ("__mips16_floatsidf"); \
3520 fixdfsi_libfunc = \
3521 init_one_libfunc ("__mips16_fixdfsi"); \
3522 } \
3523 } \
3524 } \
3525 while (0)
3526
3527 #define DFMODE_NAN \
3528 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
3529 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
3530 #define SFMODE_NAN \
3531 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
3532 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
3533
3534 /* Generate calls to memcpy, etc., not bcopy, etc. */
3535 #define TARGET_MEM_FUNCTIONS
3536
3537 #ifndef __mips16
3538 /* Since the bits of the _init and _fini function is spread across
3539 many object files, each potentially with its own GP, we must assume
3540 we need to load our GP. We don't preserve $gp or $ra, since each
3541 init/fini chunk is supposed to initialize $gp, and crti/crtn
3542 already take care of preserving $ra and, when appropriate, $gp. */
3543 #if _MIPS_SIM == _MIPS_SIM_ABI32
3544 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3545 asm (SECTION_OP "\n\
3546 .set noreorder\n\
3547 bal 1f\n\
3548 nop\n\
3549 1: .cpload $31\n\
3550 .set reorder\n\
3551 jal " USER_LABEL_PREFIX #FUNC "\n\
3552 " TEXT_SECTION_ASM_OP);
3553 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3554 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3555 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3556 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3557 asm (SECTION_OP "\n\
3558 .set noreorder\n\
3559 bal 1f\n\
3560 nop\n\
3561 1: .set reorder\n\
3562 .cpsetup $31, $2, 1b\n\
3563 jal " USER_LABEL_PREFIX #FUNC "\n\
3564 " TEXT_SECTION_ASM_OP);
3565 #endif
3566 #endif
Mirror of the offical gcc git repository hosted at gcc.gnu.org