| blob | 8b1c24c5d79fec0cad65f767d1b78017dd90383b |
1 ;; Machine description for RISC-V 'V' Extension for GNU compiler.
2 ;; Copyright (C) 2022-2024 Free Software Foundation, Inc.
3 ;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; This file describes the RISC-V 'V' Extension, Version 1.0.
22 ;;
23 ;; This file include :
24 ;;
25 ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
26 ;; - Auto-vectorization (autovec.md)
27 ;; - Optimization (autovec-opt.md)
29 (include "vector-iterators.md")
31 (define_constants [
32 (INVALID_ATTRIBUTE 255)
33 (X0_REGNUM 0)
34 ])
36 ;; True if the type is RVV instructions that include VTYPE
37 ;; global status register in the use op list.
38 ;; We known VTYPE has 4 fields: SEW, LMUL, TA, MA.
39 ;; The instruction need any of VTYPE field is set as true
40 ;; in this attribute.
41 (define_attr "has_vtype_op" "false,true"
42 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
43 vldux,vldox,vstux,vstox,vldff,\
44 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
45 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
46 vsalu,vaalu,vsmul,vsshift,vnclip,\
47 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
48 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
49 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
50 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
51 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
52 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,\
53 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
54 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
55 vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\
56 vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
57 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
58 (const_string "true")]
59 (const_string "false")))
61 ;; True if the type is RVV instructions that include VL
62 ;; global status register in the use op list.
63 ;; The instruction need vector length to be specified is set
64 ;; in this attribute.
65 (define_attr "has_vl_op" "false,true"
66 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
67 vldux,vldox,vstux,vstox,vldff,\
68 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
69 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
70 vsalu,vaalu,vsmul,vsshift,vnclip,\
71 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
72 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
73 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
74 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
75 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
76 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovxv,vfmovfv,\
77 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
78 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
79 vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,\
80 vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
81 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
82 (const_string "true")]
83 (const_string "false")))
85 ;; The default SEW of RVV instruction. This attribute doesn't mean the instruction
86 ;; is necessary to require SEW check for example vlm.v which require ratio to
87 ;; check. However, we need default value of SEW for vsetvl instruction since there
88 ;; is no field for ratio in the vsetvl instruction encoding.
89 (define_attr "sew" ""
90 (cond [(eq_attr "mode" "RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\
91 RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,\
92 RVVM1x8QI,RVVMF2x8QI,RVVMF4x8QI,RVVMF8x8QI,\
93 RVVM1x7QI,RVVMF2x7QI,RVVMF4x7QI,RVVMF8x7QI,\
94 RVVM1x6QI,RVVMF2x6QI,RVVMF4x6QI,RVVMF8x6QI,\
95 RVVM1x5QI,RVVMF2x5QI,RVVMF4x5QI,RVVMF8x5QI,\
96 RVVM2x4QI,RVVM1x4QI,RVVMF2x4QI,RVVMF4x4QI,RVVMF8x4QI,\
97 RVVM2x3QI,RVVM1x3QI,RVVMF2x3QI,RVVMF4x3QI,RVVMF8x3QI,\
98 RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4x2QI,RVVMF8x2QI,\
99 V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,\
100 V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI")
101 (const_int 8)
102 (eq_attr "mode" "RVVMF16BI")
103 (if_then_else (match_test "TARGET_XTHEADVECTOR")
104 (const_int 16)
105 (const_int 8))
106 (eq_attr "mode" "RVVMF32BI")
107 (if_then_else (match_test "TARGET_XTHEADVECTOR")
108 (const_int 32)
109 (const_int 8))
110 (eq_attr "mode" "RVVMF64BI")
111 (if_then_else (match_test "TARGET_XTHEADVECTOR")
112 (const_int 64)
113 (const_int 8))
114 (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,\
115 RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\
116 RVVM1x7HI,RVVMF2x7HI,RVVMF4x7HI,\
117 RVVM1x6HI,RVVMF2x6HI,RVVMF4x6HI,\
118 RVVM1x5HI,RVVMF2x5HI,RVVMF4x5HI,\
119 RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,\
120 RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,\
121 RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,\
122 RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,\
123 RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,\
124 RVVM1x7HF,RVVMF2x7HF,RVVMF4x7HF,\
125 RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,\
126 RVVM1x5HF,RVVMF2x5HF,RVVMF4x5HF,\
127 RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF,RVVMF4x4HF,\
128 RVVM2x3HF,RVVM1x3HF,RVVMF2x3HF,RVVMF4x3HF,\
129 RVVM4x2HF,RVVM2x2HF,RVVM1x2HF,RVVMF2x2HF,RVVMF4x2HF,\
130 V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI,\
131 V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V2048HF")
132 (const_int 16)
133 (eq_attr "mode" "RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI,\
134 RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF,\
135 RVVM1x8SI,RVVMF2x8SI,\
136 RVVM1x7SI,RVVMF2x7SI,\
137 RVVM1x6SI,RVVMF2x6SI,\
138 RVVM1x5SI,RVVMF2x5SI,\
139 RVVMF2x4SI,RVVMF2x3SI,\
140 RVVM2x4SI,RVVM1x4SI,\
141 RVVM2x3SI,RVVM1x3SI,\
142 RVVM4x2SI,RVVM2x2SI,RVVM1x2SI,RVVMF2x2SI,\
143 RVVM1x8SF,RVVMF2x8SF,\
144 RVVM1x7SF,RVVMF2x7SF,\
145 RVVM1x6SF,RVVMF2x6SF,\
146 RVVM1x5SF,RVVMF2x5SF,\
147 RVVM2x4SF,RVVM1x4SF,RVVMF2x4SF,\
148 RVVM2x3SF,RVVM1x3SF,RVVMF2x3SF,\
149 RVVM4x2SF,RVVM2x2SF,RVVM1x2SF,RVVMF2x2SF,\
150 V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI,\
151 V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF")
152 (const_int 32)
153 (eq_attr "mode" "RVVM8DI,RVVM4DI,RVVM2DI,RVVM1DI,\
154 RVVM8DF,RVVM4DF,RVVM2DF,RVVM1DF,\
155 RVVM1x8DI,RVVM1x7DI,RVVM1x6DI,RVVM1x5DI,\
156 RVVM2x4DI,RVVM1x4DI,\
157 RVVM2x3DI,RVVM1x3DI,\
158 RVVM4x2DI,RVVM2x2DI,RVVM1x2DI,\
159 RVVM1x8DF,RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,\
160 RVVM2x4DF,RVVM1x4DF,\
161 RVVM2x3DF,RVVM1x3DF,\
162 RVVM4x2DF,RVVM2x2DF,RVVM1x2DF,\
163 V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,\
164 V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF")
165 (const_int 64)]
166 (const_int INVALID_ATTRIBUTE)))
168 ;; Ditto to LMUL.
169 (define_attr "vlmul" ""
170 (cond [(eq_attr "mode" "RVVM8QI,RVVM1BI") (symbol_ref "riscv_vector::LMUL_8")
171 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (symbol_ref "riscv_vector::LMUL_4")
172 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (symbol_ref "riscv_vector::LMUL_2")
173 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (symbol_ref "riscv_vector::LMUL_1")
174 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F2")
175 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F4")
176 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F8")
177 (eq_attr "mode" "RVVM8HI") (symbol_ref "riscv_vector::LMUL_8")
178 (eq_attr "mode" "RVVM4HI") (symbol_ref "riscv_vector::LMUL_4")
179 (eq_attr "mode" "RVVM2HI") (symbol_ref "riscv_vector::LMUL_2")
180 (eq_attr "mode" "RVVM1HI") (symbol_ref "riscv_vector::LMUL_1")
181 (eq_attr "mode" "RVVMF2HI") (symbol_ref "riscv_vector::LMUL_F2")
182 (eq_attr "mode" "RVVMF4HI") (symbol_ref "riscv_vector::LMUL_F4")
183 (eq_attr "mode" "RVVM8HF") (symbol_ref "riscv_vector::LMUL_8")
184 (eq_attr "mode" "RVVM4HF") (symbol_ref "riscv_vector::LMUL_4")
185 (eq_attr "mode" "RVVM2HF") (symbol_ref "riscv_vector::LMUL_2")
186 (eq_attr "mode" "RVVM1HF") (symbol_ref "riscv_vector::LMUL_1")
187 (eq_attr "mode" "RVVMF2HF") (symbol_ref "riscv_vector::LMUL_F2")
188 (eq_attr "mode" "RVVMF4HF") (symbol_ref "riscv_vector::LMUL_F4")
189 (eq_attr "mode" "RVVM8SI") (symbol_ref "riscv_vector::LMUL_8")
190 (eq_attr "mode" "RVVM4SI") (symbol_ref "riscv_vector::LMUL_4")
191 (eq_attr "mode" "RVVM2SI") (symbol_ref "riscv_vector::LMUL_2")
192 (eq_attr "mode" "RVVM1SI") (symbol_ref "riscv_vector::LMUL_1")
193 (eq_attr "mode" "RVVMF2SI") (symbol_ref "riscv_vector::LMUL_F2")
194 (eq_attr "mode" "RVVM8SF") (symbol_ref "riscv_vector::LMUL_8")
195 (eq_attr "mode" "RVVM4SF") (symbol_ref "riscv_vector::LMUL_4")
196 (eq_attr "mode" "RVVM2SF") (symbol_ref "riscv_vector::LMUL_2")
197 (eq_attr "mode" "RVVM1SF") (symbol_ref "riscv_vector::LMUL_1")
198 (eq_attr "mode" "RVVMF2SF") (symbol_ref "riscv_vector::LMUL_F2")
199 (eq_attr "mode" "RVVM8DI") (symbol_ref "riscv_vector::LMUL_8")
200 (eq_attr "mode" "RVVM4DI") (symbol_ref "riscv_vector::LMUL_4")
201 (eq_attr "mode" "RVVM2DI") (symbol_ref "riscv_vector::LMUL_2")
202 (eq_attr "mode" "RVVM1DI") (symbol_ref "riscv_vector::LMUL_1")
203 (eq_attr "mode" "RVVM8DF") (symbol_ref "riscv_vector::LMUL_8")
204 (eq_attr "mode" "RVVM4DF") (symbol_ref "riscv_vector::LMUL_4")
205 (eq_attr "mode" "RVVM2DF") (symbol_ref "riscv_vector::LMUL_2")
206 (eq_attr "mode" "RVVM1DF") (symbol_ref "riscv_vector::LMUL_1")
207 (eq_attr "mode" "RVVM1x8QI") (symbol_ref "riscv_vector::LMUL_1")
208 (eq_attr "mode" "RVVMF2x8QI") (symbol_ref "riscv_vector::LMUL_F2")
209 (eq_attr "mode" "RVVMF4x8QI") (symbol_ref "riscv_vector::LMUL_F4")
210 (eq_attr "mode" "RVVMF8x8QI") (symbol_ref "riscv_vector::LMUL_F8")
211 (eq_attr "mode" "RVVM1x7QI") (symbol_ref "riscv_vector::LMUL_1")
212 (eq_attr "mode" "RVVMF2x7QI") (symbol_ref "riscv_vector::LMUL_F2")
213 (eq_attr "mode" "RVVMF4x7QI") (symbol_ref "riscv_vector::LMUL_F4")
214 (eq_attr "mode" "RVVMF8x7QI") (symbol_ref "riscv_vector::LMUL_F8")
215 (eq_attr "mode" "RVVM1x6QI") (symbol_ref "riscv_vector::LMUL_1")
216 (eq_attr "mode" "RVVMF2x6QI") (symbol_ref "riscv_vector::LMUL_F2")
217 (eq_attr "mode" "RVVMF4x6QI") (symbol_ref "riscv_vector::LMUL_F4")
218 (eq_attr "mode" "RVVMF8x6QI") (symbol_ref "riscv_vector::LMUL_F8")
219 (eq_attr "mode" "RVVM1x5QI") (symbol_ref "riscv_vector::LMUL_1")
220 (eq_attr "mode" "RVVMF2x5QI") (symbol_ref "riscv_vector::LMUL_F2")
221 (eq_attr "mode" "RVVMF4x5QI") (symbol_ref "riscv_vector::LMUL_F4")
222 (eq_attr "mode" "RVVMF8x5QI") (symbol_ref "riscv_vector::LMUL_F8")
223 (eq_attr "mode" "RVVM2x4QI") (symbol_ref "riscv_vector::LMUL_2")
224 (eq_attr "mode" "RVVM1x4QI") (symbol_ref "riscv_vector::LMUL_1")
225 (eq_attr "mode" "RVVMF2x4QI") (symbol_ref "riscv_vector::LMUL_F2")
226 (eq_attr "mode" "RVVMF4x4QI") (symbol_ref "riscv_vector::LMUL_F4")
227 (eq_attr "mode" "RVVMF8x4QI") (symbol_ref "riscv_vector::LMUL_F8")
228 (eq_attr "mode" "RVVM2x3QI") (symbol_ref "riscv_vector::LMUL_2")
229 (eq_attr "mode" "RVVM1x3QI") (symbol_ref "riscv_vector::LMUL_1")
230 (eq_attr "mode" "RVVMF2x3QI") (symbol_ref "riscv_vector::LMUL_F2")
231 (eq_attr "mode" "RVVMF4x3QI") (symbol_ref "riscv_vector::LMUL_F4")
232 (eq_attr "mode" "RVVMF8x3QI") (symbol_ref "riscv_vector::LMUL_F8")
233 (eq_attr "mode" "RVVM4x2QI") (symbol_ref "riscv_vector::LMUL_4")
234 (eq_attr "mode" "RVVM2x2QI") (symbol_ref "riscv_vector::LMUL_2")
235 (eq_attr "mode" "RVVM1x2QI") (symbol_ref "riscv_vector::LMUL_1")
236 (eq_attr "mode" "RVVMF2x2QI") (symbol_ref "riscv_vector::LMUL_F2")
237 (eq_attr "mode" "RVVMF4x2QI") (symbol_ref "riscv_vector::LMUL_F4")
238 (eq_attr "mode" "RVVMF8x2QI") (symbol_ref "riscv_vector::LMUL_F8")
239 (eq_attr "mode" "RVVM1x8HI") (symbol_ref "riscv_vector::LMUL_1")
240 (eq_attr "mode" "RVVMF2x8HI") (symbol_ref "riscv_vector::LMUL_F2")
241 (eq_attr "mode" "RVVMF4x8HI") (symbol_ref "riscv_vector::LMUL_F4")
242 (eq_attr "mode" "RVVM1x7HI") (symbol_ref "riscv_vector::LMUL_1")
243 (eq_attr "mode" "RVVMF2x7HI") (symbol_ref "riscv_vector::LMUL_F2")
244 (eq_attr "mode" "RVVMF4x7HI") (symbol_ref "riscv_vector::LMUL_F4")
245 (eq_attr "mode" "RVVM1x6HI") (symbol_ref "riscv_vector::LMUL_1")
246 (eq_attr "mode" "RVVMF2x6HI") (symbol_ref "riscv_vector::LMUL_F2")
247 (eq_attr "mode" "RVVMF4x6HI") (symbol_ref "riscv_vector::LMUL_F4")
248 (eq_attr "mode" "RVVM1x5HI") (symbol_ref "riscv_vector::LMUL_1")
249 (eq_attr "mode" "RVVMF2x5HI") (symbol_ref "riscv_vector::LMUL_F2")
250 (eq_attr "mode" "RVVMF4x5HI") (symbol_ref "riscv_vector::LMUL_F4")
251 (eq_attr "mode" "RVVM2x4HI") (symbol_ref "riscv_vector::LMUL_2")
252 (eq_attr "mode" "RVVM1x4HI") (symbol_ref "riscv_vector::LMUL_1")
253 (eq_attr "mode" "RVVMF2x4HI") (symbol_ref "riscv_vector::LMUL_F2")
254 (eq_attr "mode" "RVVMF4x4HI") (symbol_ref "riscv_vector::LMUL_F4")
255 (eq_attr "mode" "RVVM2x3HI") (symbol_ref "riscv_vector::LMUL_2")
256 (eq_attr "mode" "RVVM1x3HI") (symbol_ref "riscv_vector::LMUL_1")
257 (eq_attr "mode" "RVVMF2x3HI") (symbol_ref "riscv_vector::LMUL_F2")
258 (eq_attr "mode" "RVVMF4x3HI") (symbol_ref "riscv_vector::LMUL_F4")
259 (eq_attr "mode" "RVVM4x2HI") (symbol_ref "riscv_vector::LMUL_4")
260 (eq_attr "mode" "RVVM2x2HI") (symbol_ref "riscv_vector::LMUL_2")
261 (eq_attr "mode" "RVVM1x2HI") (symbol_ref "riscv_vector::LMUL_1")
262 (eq_attr "mode" "RVVMF2x2HI") (symbol_ref "riscv_vector::LMUL_F2")
263 (eq_attr "mode" "RVVMF4x2HI") (symbol_ref "riscv_vector::LMUL_F4")
264 (eq_attr "mode" "RVVM1x8HF") (symbol_ref "riscv_vector::LMUL_1")
265 (eq_attr "mode" "RVVMF2x8HF") (symbol_ref "riscv_vector::LMUL_F2")
266 (eq_attr "mode" "RVVMF4x8HF") (symbol_ref "riscv_vector::LMUL_F4")
267 (eq_attr "mode" "RVVM1x7HF") (symbol_ref "riscv_vector::LMUL_1")
268 (eq_attr "mode" "RVVMF2x7HF") (symbol_ref "riscv_vector::LMUL_F2")
269 (eq_attr "mode" "RVVMF4x7HF") (symbol_ref "riscv_vector::LMUL_F4")
270 (eq_attr "mode" "RVVM1x6HF") (symbol_ref "riscv_vector::LMUL_1")
271 (eq_attr "mode" "RVVMF2x6HF") (symbol_ref "riscv_vector::LMUL_F2")
272 (eq_attr "mode" "RVVMF4x6HF") (symbol_ref "riscv_vector::LMUL_F4")
273 (eq_attr "mode" "RVVM1x5HF") (symbol_ref "riscv_vector::LMUL_1")
274 (eq_attr "mode" "RVVMF2x5HF") (symbol_ref "riscv_vector::LMUL_F2")
275 (eq_attr "mode" "RVVMF4x5HF") (symbol_ref "riscv_vector::LMUL_F4")
276 (eq_attr "mode" "RVVM2x4HF") (symbol_ref "riscv_vector::LMUL_2")
277 (eq_attr "mode" "RVVM1x4HF") (symbol_ref "riscv_vector::LMUL_1")
278 (eq_attr "mode" "RVVMF2x4HF") (symbol_ref "riscv_vector::LMUL_F2")
279 (eq_attr "mode" "RVVMF4x4HF") (symbol_ref "riscv_vector::LMUL_F4")
280 (eq_attr "mode" "RVVM2x3HF") (symbol_ref "riscv_vector::LMUL_2")
281 (eq_attr "mode" "RVVM1x3HF") (symbol_ref "riscv_vector::LMUL_1")
282 (eq_attr "mode" "RVVMF2x3HF") (symbol_ref "riscv_vector::LMUL_F2")
283 (eq_attr "mode" "RVVMF4x3HF") (symbol_ref "riscv_vector::LMUL_F4")
284 (eq_attr "mode" "RVVM4x2HF") (symbol_ref "riscv_vector::LMUL_4")
285 (eq_attr "mode" "RVVM2x2HF") (symbol_ref "riscv_vector::LMUL_2")
286 (eq_attr "mode" "RVVM1x2HF") (symbol_ref "riscv_vector::LMUL_1")
287 (eq_attr "mode" "RVVMF2x2HF") (symbol_ref "riscv_vector::LMUL_F2")
288 (eq_attr "mode" "RVVMF4x2HF") (symbol_ref "riscv_vector::LMUL_F4")
289 (eq_attr "mode" "RVVM1x8SI") (symbol_ref "riscv_vector::LMUL_1")
290 (eq_attr "mode" "RVVMF2x8SI") (symbol_ref "riscv_vector::LMUL_F2")
291 (eq_attr "mode" "RVVM1x7SI") (symbol_ref "riscv_vector::LMUL_1")
292 (eq_attr "mode" "RVVMF2x7SI") (symbol_ref "riscv_vector::LMUL_F2")
293 (eq_attr "mode" "RVVM1x6SI") (symbol_ref "riscv_vector::LMUL_1")
294 (eq_attr "mode" "RVVMF2x6SI") (symbol_ref "riscv_vector::LMUL_F2")
295 (eq_attr "mode" "RVVM1x5SI") (symbol_ref "riscv_vector::LMUL_1")
296 (eq_attr "mode" "RVVMF2x5SI") (symbol_ref "riscv_vector::LMUL_F2")
297 (eq_attr "mode" "RVVM2x4SI") (symbol_ref "riscv_vector::LMUL_2")
298 (eq_attr "mode" "RVVM1x4SI") (symbol_ref "riscv_vector::LMUL_1")
299 (eq_attr "mode" "RVVMF2x4SI") (symbol_ref "riscv_vector::LMUL_F2")
300 (eq_attr "mode" "RVVM2x3SI") (symbol_ref "riscv_vector::LMUL_2")
301 (eq_attr "mode" "RVVM1x3SI") (symbol_ref "riscv_vector::LMUL_1")
302 (eq_attr "mode" "RVVMF2x3SI") (symbol_ref "riscv_vector::LMUL_F2")
303 (eq_attr "mode" "RVVM4x2SI") (symbol_ref "riscv_vector::LMUL_4")
304 (eq_attr "mode" "RVVM2x2SI") (symbol_ref "riscv_vector::LMUL_2")
305 (eq_attr "mode" "RVVM1x2SI") (symbol_ref "riscv_vector::LMUL_1")
306 (eq_attr "mode" "RVVMF2x2SI") (symbol_ref "riscv_vector::LMUL_F2")
307 (eq_attr "mode" "RVVM1x8SF") (symbol_ref "riscv_vector::LMUL_1")
308 (eq_attr "mode" "RVVMF2x8SF") (symbol_ref "riscv_vector::LMUL_F2")
309 (eq_attr "mode" "RVVM1x7SF") (symbol_ref "riscv_vector::LMUL_1")
310 (eq_attr "mode" "RVVMF2x7SF") (symbol_ref "riscv_vector::LMUL_F2")
311 (eq_attr "mode" "RVVM1x6SF") (symbol_ref "riscv_vector::LMUL_1")
312 (eq_attr "mode" "RVVMF2x6SF") (symbol_ref "riscv_vector::LMUL_F2")
313 (eq_attr "mode" "RVVM1x5SF") (symbol_ref "riscv_vector::LMUL_1")
314 (eq_attr "mode" "RVVMF2x5SF") (symbol_ref "riscv_vector::LMUL_F2")
315 (eq_attr "mode" "RVVM2x4SF") (symbol_ref "riscv_vector::LMUL_2")
316 (eq_attr "mode" "RVVM1x4SF") (symbol_ref "riscv_vector::LMUL_1")
317 (eq_attr "mode" "RVVMF2x4SF") (symbol_ref "riscv_vector::LMUL_F2")
318 (eq_attr "mode" "RVVM2x3SF") (symbol_ref "riscv_vector::LMUL_2")
319 (eq_attr "mode" "RVVM1x3SF") (symbol_ref "riscv_vector::LMUL_1")
320 (eq_attr "mode" "RVVMF2x3SF") (symbol_ref "riscv_vector::LMUL_F2")
321 (eq_attr "mode" "RVVM4x2SF") (symbol_ref "riscv_vector::LMUL_4")
322 (eq_attr "mode" "RVVM2x2SF") (symbol_ref "riscv_vector::LMUL_2")
323 (eq_attr "mode" "RVVM1x2SF") (symbol_ref "riscv_vector::LMUL_1")
324 (eq_attr "mode" "RVVMF2x2SF") (symbol_ref "riscv_vector::LMUL_F2")
325 (eq_attr "mode" "RVVM1x8DI") (symbol_ref "riscv_vector::LMUL_1")
326 (eq_attr "mode" "RVVM1x7DI") (symbol_ref "riscv_vector::LMUL_1")
327 (eq_attr "mode" "RVVM1x6DI") (symbol_ref "riscv_vector::LMUL_1")
328 (eq_attr "mode" "RVVM1x5DI") (symbol_ref "riscv_vector::LMUL_1")
329 (eq_attr "mode" "RVVM2x4DI") (symbol_ref "riscv_vector::LMUL_2")
330 (eq_attr "mode" "RVVM1x4DI") (symbol_ref "riscv_vector::LMUL_1")
331 (eq_attr "mode" "RVVM2x3DI") (symbol_ref "riscv_vector::LMUL_2")
332 (eq_attr "mode" "RVVM1x3DI") (symbol_ref "riscv_vector::LMUL_1")
333 (eq_attr "mode" "RVVM4x2DI") (symbol_ref "riscv_vector::LMUL_4")
334 (eq_attr "mode" "RVVM2x2DI") (symbol_ref "riscv_vector::LMUL_2")
335 (eq_attr "mode" "RVVM1x2DI") (symbol_ref "riscv_vector::LMUL_1")
336 (eq_attr "mode" "RVVM1x8DF") (symbol_ref "riscv_vector::LMUL_1")
337 (eq_attr "mode" "RVVM1x7DF") (symbol_ref "riscv_vector::LMUL_1")
338 (eq_attr "mode" "RVVM1x6DF") (symbol_ref "riscv_vector::LMUL_1")
339 (eq_attr "mode" "RVVM1x5DF") (symbol_ref "riscv_vector::LMUL_1")
340 (eq_attr "mode" "RVVM2x4DF") (symbol_ref "riscv_vector::LMUL_2")
341 (eq_attr "mode" "RVVM1x4DF") (symbol_ref "riscv_vector::LMUL_1")
342 (eq_attr "mode" "RVVM2x3DF") (symbol_ref "riscv_vector::LMUL_2")
343 (eq_attr "mode" "RVVM1x3DF") (symbol_ref "riscv_vector::LMUL_1")
344 (eq_attr "mode" "RVVM4x2DF") (symbol_ref "riscv_vector::LMUL_4")
345 (eq_attr "mode" "RVVM2x2DF") (symbol_ref "riscv_vector::LMUL_2")
346 (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1")
348 ;; VLS modes.
349 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_vlmul(E_V1QImode)")
350 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_vlmul(E_V2QImode)")
351 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_vlmul(E_V4QImode)")
352 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_vlmul(E_V8QImode)")
353 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
354 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_vlmul(E_V32QImode)")
355 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_vlmul(E_V64QImode)")
356 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_vlmul(E_V128QImode)")
357 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_vlmul(E_V256QImode)")
358 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_vlmul(E_V512QImode)")
359 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_vlmul(E_V1024QImode)")
360 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_vlmul(E_V2048QImode)")
361 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_vlmul(E_V4096QImode)")
362 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_vlmul(E_V1HImode)")
363 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_vlmul(E_V2HImode)")
364 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_vlmul(E_V4HImode)")
365 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_vlmul(E_V8HImode)")
366 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_vlmul(E_V16HImode)")
367 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_vlmul(E_V32HImode)")
368 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_vlmul(E_V64HImode)")
369 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_vlmul(E_V128HImode)")
370 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_vlmul(E_V256HImode)")
371 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_vlmul(E_V512HImode)")
372 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_vlmul(E_V1024HImode)")
373 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_vlmul(E_V2048HImode)")
374 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_vlmul(E_V1SImode)")
375 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_vlmul(E_V2SImode)")
376 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_vlmul(E_V4SImode)")
377 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_vlmul(E_V8SImode)")
378 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_vlmul(E_V16SImode)")
379 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_vlmul(E_V32SImode)")
380 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_vlmul(E_V64SImode)")
381 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_vlmul(E_V128SImode)")
382 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_vlmul(E_V256SImode)")
383 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_vlmul(E_V512SImode)")
384 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_vlmul(E_V1024SImode)")
385 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_vlmul(E_V1DImode)")
386 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_vlmul(E_V2DImode)")
387 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_vlmul(E_V4DImode)")
388 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_vlmul(E_V8DImode)")
389 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_vlmul(E_V16DImode)")
390 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_vlmul(E_V32DImode)")
391 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_vlmul(E_V64DImode)")
392 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_vlmul(E_V128DImode)")
393 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_vlmul(E_V256DImode)")
394 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_vlmul(E_V512DImode)")
395 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_vlmul(E_V1HFmode)")
396 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_vlmul(E_V2HFmode)")
397 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_vlmul(E_V4HFmode)")
398 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_vlmul(E_V8HFmode)")
399 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_vlmul(E_V16HFmode)")
400 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_vlmul(E_V32HFmode)")
401 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_vlmul(E_V64HFmode)")
402 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_vlmul(E_V128HFmode)")
403 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_vlmul(E_V256HFmode)")
404 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_vlmul(E_V512HFmode)")
405 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_vlmul(E_V1024HFmode)")
406 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_vlmul(E_V2048HFmode)")
407 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_vlmul(E_V1SFmode)")
408 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_vlmul(E_V2SFmode)")
409 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_vlmul(E_V4SFmode)")
410 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_vlmul(E_V8SFmode)")
411 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_vlmul(E_V16SFmode)")
412 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_vlmul(E_V32SFmode)")
413 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_vlmul(E_V64SFmode)")
414 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_vlmul(E_V128SFmode)")
415 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_vlmul(E_V256SFmode)")
416 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_vlmul(E_V512SFmode)")
417 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_vlmul(E_V1024SFmode)")
418 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_vlmul(E_V1DFmode)")
419 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_vlmul(E_V2DFmode)")
420 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_vlmul(E_V4DFmode)")
421 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_vlmul(E_V8DFmode)")
422 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_vlmul(E_V16DFmode)")
423 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_vlmul(E_V32DFmode)")
424 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_vlmul(E_V64DFmode)")
425 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_vlmul(E_V128DFmode)")
426 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_vlmul(E_V256DFmode)")
427 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_vlmul(E_V512DFmode)")]
428 (const_int INVALID_ATTRIBUTE)))
430 ;; It is valid for instruction that require sew/lmul ratio.
431 (define_attr "ratio" ""
432 (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\
433 vialu,vshift,vicmp,vimul,vidiv,vsalu,\
434 vext,viwalu,viwmul,vicalu,vnshift,\
435 vimuladd,vimerge,vaalu,vsmul,vsshift,\
436 vnclip,viminmax,viwmuladd,\
437 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\
438 vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\
439 vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
440 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
441 vfncvtftof,vfmuladd,vfwmuladd,vfclass,vired,\
442 viwred,vfredu,vfredo,vfwredu,vfwredo,vimovvx,\
443 vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\
444 vislide1up,vislide1down,vfslide1up,vfslide1down,\
445 vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox,\
446 vandn,vbrev,vbrev8,vrev8,vclz,vctz,vrol,vror,vwsll,\
447 vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
448 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\
449 vsm3me,vsm3c")
450 (const_int INVALID_ATTRIBUTE)
451 (and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\
452 vlsegdff,vssegtux,vlsegdox,vlsegdux")
453 (match_test "TARGET_XTHEADVECTOR"))
454 (const_int INVALID_ATTRIBUTE)
455 (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
456 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (const_int 2)
457 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (const_int 4)
458 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (const_int 8)
459 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (const_int 16)
460 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (const_int 32)
461 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (const_int 64)
462 (eq_attr "mode" "RVVM8HI") (const_int 2)
463 (eq_attr "mode" "RVVM4HI") (const_int 4)
464 (eq_attr "mode" "RVVM2HI") (const_int 8)
465 (eq_attr "mode" "RVVM1HI") (const_int 16)
466 (eq_attr "mode" "RVVMF2HI") (const_int 32)
467 (eq_attr "mode" "RVVMF4HI") (const_int 64)
468 (eq_attr "mode" "RVVM8HF") (const_int 2)
469 (eq_attr "mode" "RVVM4HF") (const_int 4)
470 (eq_attr "mode" "RVVM2HF") (const_int 8)
471 (eq_attr "mode" "RVVM1HF") (const_int 16)
472 (eq_attr "mode" "RVVMF2HF") (const_int 32)
473 (eq_attr "mode" "RVVMF4HF") (const_int 64)
474 (eq_attr "mode" "RVVM8SI") (const_int 4)
475 (eq_attr "mode" "RVVM4SI") (const_int 8)
476 (eq_attr "mode" "RVVM2SI") (const_int 16)
477 (eq_attr "mode" "RVVM1SI") (const_int 32)
478 (eq_attr "mode" "RVVMF2SI") (const_int 64)
479 (eq_attr "mode" "RVVM8SF") (const_int 4)
480 (eq_attr "mode" "RVVM4SF") (const_int 8)
481 (eq_attr "mode" "RVVM2SF") (const_int 16)
482 (eq_attr "mode" "RVVM1SF") (const_int 32)
483 (eq_attr "mode" "RVVMF2SF") (const_int 64)
484 (eq_attr "mode" "RVVM8DI") (const_int 8)
485 (eq_attr "mode" "RVVM4DI") (const_int 16)
486 (eq_attr "mode" "RVVM2DI") (const_int 32)
487 (eq_attr "mode" "RVVM1DI") (const_int 64)
488 (eq_attr "mode" "RVVM8DF") (const_int 8)
489 (eq_attr "mode" "RVVM4DF") (const_int 16)
490 (eq_attr "mode" "RVVM2DF") (const_int 32)
491 (eq_attr "mode" "RVVM1DF") (const_int 64)
492 (eq_attr "mode" "RVVM1x8QI") (const_int 8)
493 (eq_attr "mode" "RVVMF2x8QI") (const_int 16)
494 (eq_attr "mode" "RVVMF4x8QI") (const_int 32)
495 (eq_attr "mode" "RVVMF8x8QI") (const_int 64)
496 (eq_attr "mode" "RVVM1x7QI") (const_int 8)
497 (eq_attr "mode" "RVVMF2x7QI") (const_int 16)
498 (eq_attr "mode" "RVVMF4x7QI") (const_int 32)
499 (eq_attr "mode" "RVVMF8x7QI") (const_int 64)
500 (eq_attr "mode" "RVVM1x6QI") (const_int 8)
501 (eq_attr "mode" "RVVMF2x6QI") (const_int 16)
502 (eq_attr "mode" "RVVMF4x6QI") (const_int 32)
503 (eq_attr "mode" "RVVMF8x6QI") (const_int 64)
504 (eq_attr "mode" "RVVM1x5QI") (const_int 8)
505 (eq_attr "mode" "RVVMF2x5QI") (const_int 16)
506 (eq_attr "mode" "RVVMF4x5QI") (const_int 32)
507 (eq_attr "mode" "RVVMF8x5QI") (const_int 64)
508 (eq_attr "mode" "RVVM2x4QI") (const_int 4)
509 (eq_attr "mode" "RVVM1x4QI") (const_int 8)
510 (eq_attr "mode" "RVVMF2x4QI") (const_int 16)
511 (eq_attr "mode" "RVVMF4x4QI") (const_int 32)
512 (eq_attr "mode" "RVVMF8x4QI") (const_int 64)
513 (eq_attr "mode" "RVVM2x3QI") (const_int 4)
514 (eq_attr "mode" "RVVM1x3QI") (const_int 8)
515 (eq_attr "mode" "RVVMF2x3QI") (const_int 16)
516 (eq_attr "mode" "RVVMF4x3QI") (const_int 32)
517 (eq_attr "mode" "RVVMF8x3QI") (const_int 64)
518 (eq_attr "mode" "RVVM4x2QI") (const_int 2)
519 (eq_attr "mode" "RVVM2x2QI") (const_int 4)
520 (eq_attr "mode" "RVVM1x2QI") (const_int 8)
521 (eq_attr "mode" "RVVMF2x2QI") (const_int 16)
522 (eq_attr "mode" "RVVMF4x2QI") (const_int 32)
523 (eq_attr "mode" "RVVMF8x2QI") (const_int 64)
524 (eq_attr "mode" "RVVM1x8HI") (const_int 16)
525 (eq_attr "mode" "RVVMF2x8HI") (const_int 32)
526 (eq_attr "mode" "RVVMF4x8HI") (const_int 64)
527 (eq_attr "mode" "RVVM1x7HI") (const_int 16)
528 (eq_attr "mode" "RVVMF2x7HI") (const_int 32)
529 (eq_attr "mode" "RVVMF4x7HI") (const_int 64)
530 (eq_attr "mode" "RVVM1x6HI") (const_int 16)
531 (eq_attr "mode" "RVVMF2x6HI") (const_int 32)
532 (eq_attr "mode" "RVVMF4x6HI") (const_int 64)
533 (eq_attr "mode" "RVVM1x5HI") (const_int 16)
534 (eq_attr "mode" "RVVMF2x5HI") (const_int 32)
535 (eq_attr "mode" "RVVMF4x5HI") (const_int 64)
536 (eq_attr "mode" "RVVM2x4HI") (const_int 8)
537 (eq_attr "mode" "RVVM1x4HI") (const_int 16)
538 (eq_attr "mode" "RVVMF2x4HI") (const_int 32)
539 (eq_attr "mode" "RVVMF4x4HI") (const_int 64)
540 (eq_attr "mode" "RVVM2x3HI") (const_int 8)
541 (eq_attr "mode" "RVVM1x3HI") (const_int 16)
542 (eq_attr "mode" "RVVMF2x3HI") (const_int 32)
543 (eq_attr "mode" "RVVMF4x3HI") (const_int 64)
544 (eq_attr "mode" "RVVM4x2HI") (const_int 4)
545 (eq_attr "mode" "RVVM2x2HI") (const_int 8)
546 (eq_attr "mode" "RVVM1x2HI") (const_int 16)
547 (eq_attr "mode" "RVVMF2x2HI") (const_int 32)
548 (eq_attr "mode" "RVVMF4x2HI") (const_int 64)
549 (eq_attr "mode" "RVVM1x8HF") (const_int 16)
550 (eq_attr "mode" "RVVMF2x8HF") (const_int 32)
551 (eq_attr "mode" "RVVMF4x8HF") (const_int 64)
552 (eq_attr "mode" "RVVM1x7HF") (const_int 16)
553 (eq_attr "mode" "RVVMF2x7HF") (const_int 32)
554 (eq_attr "mode" "RVVMF4x7HF") (const_int 64)
555 (eq_attr "mode" "RVVM1x6HF") (const_int 16)
556 (eq_attr "mode" "RVVMF2x6HF") (const_int 32)
557 (eq_attr "mode" "RVVMF4x6HF") (const_int 64)
558 (eq_attr "mode" "RVVM1x5HF") (const_int 16)
559 (eq_attr "mode" "RVVMF2x5HF") (const_int 32)
560 (eq_attr "mode" "RVVMF4x5HF") (const_int 64)
561 (eq_attr "mode" "RVVM2x4HF") (const_int 8)
562 (eq_attr "mode" "RVVM1x4HF") (const_int 16)
563 (eq_attr "mode" "RVVMF2x4HF") (const_int 32)
564 (eq_attr "mode" "RVVMF4x4HF") (const_int 64)
565 (eq_attr "mode" "RVVM2x3HF") (const_int 8)
566 (eq_attr "mode" "RVVM1x3HF") (const_int 16)
567 (eq_attr "mode" "RVVMF2x3HF") (const_int 32)
568 (eq_attr "mode" "RVVMF4x3HF") (const_int 64)
569 (eq_attr "mode" "RVVM4x2HF") (const_int 4)
570 (eq_attr "mode" "RVVM2x2HF") (const_int 8)
571 (eq_attr "mode" "RVVM1x2HF") (const_int 16)
572 (eq_attr "mode" "RVVMF2x2HF") (const_int 32)
573 (eq_attr "mode" "RVVMF4x2HF") (const_int 64)
574 (eq_attr "mode" "RVVM1x8SI") (const_int 32)
575 (eq_attr "mode" "RVVMF2x8SI") (const_int 64)
576 (eq_attr "mode" "RVVM1x7SI") (const_int 32)
577 (eq_attr "mode" "RVVMF2x7SI") (const_int 64)
578 (eq_attr "mode" "RVVM1x6SI") (const_int 32)
579 (eq_attr "mode" "RVVMF2x6SI") (const_int 64)
580 (eq_attr "mode" "RVVM1x5SI") (const_int 32)
581 (eq_attr "mode" "RVVMF2x5SI") (const_int 64)
582 (eq_attr "mode" "RVVM2x4SI") (const_int 16)
583 (eq_attr "mode" "RVVM1x4SI") (const_int 32)
584 (eq_attr "mode" "RVVMF2x4SI") (const_int 64)
585 (eq_attr "mode" "RVVM2x3SI") (const_int 16)
586 (eq_attr "mode" "RVVM1x3SI") (const_int 32)
587 (eq_attr "mode" "RVVMF2x3SI") (const_int 64)
588 (eq_attr "mode" "RVVM4x2SI") (const_int 8)
589 (eq_attr "mode" "RVVM2x2SI") (const_int 16)
590 (eq_attr "mode" "RVVM1x2SI") (const_int 32)
591 (eq_attr "mode" "RVVMF2x2SI") (const_int 64)
592 (eq_attr "mode" "RVVM1x8SF") (const_int 32)
593 (eq_attr "mode" "RVVMF2x8SF") (const_int 64)
594 (eq_attr "mode" "RVVM1x7SF") (const_int 32)
595 (eq_attr "mode" "RVVMF2x7SF") (const_int 64)
596 (eq_attr "mode" "RVVM1x6SF") (const_int 32)
597 (eq_attr "mode" "RVVMF2x6SF") (const_int 64)
598 (eq_attr "mode" "RVVM1x5SF") (const_int 32)
599 (eq_attr "mode" "RVVMF2x5SF") (const_int 64)
600 (eq_attr "mode" "RVVM2x4SF") (const_int 16)
601 (eq_attr "mode" "RVVM1x4SF") (const_int 32)
602 (eq_attr "mode" "RVVMF2x4SF") (const_int 64)
603 (eq_attr "mode" "RVVM2x3SF") (const_int 16)
604 (eq_attr "mode" "RVVM1x3SF") (const_int 32)
605 (eq_attr "mode" "RVVMF2x3SF") (const_int 64)
606 (eq_attr "mode" "RVVM4x2SF") (const_int 8)
607 (eq_attr "mode" "RVVM2x2SF") (const_int 16)
608 (eq_attr "mode" "RVVM1x2SF") (const_int 32)
609 (eq_attr "mode" "RVVMF2x2SF") (const_int 64)
610 (eq_attr "mode" "RVVM1x8DI") (const_int 64)
611 (eq_attr "mode" "RVVM1x7DI") (const_int 64)
612 (eq_attr "mode" "RVVM1x6DI") (const_int 64)
613 (eq_attr "mode" "RVVM1x5DI") (const_int 64)
614 (eq_attr "mode" "RVVM2x4DI") (const_int 32)
615 (eq_attr "mode" "RVVM1x4DI") (const_int 64)
616 (eq_attr "mode" "RVVM2x3DI") (const_int 32)
617 (eq_attr "mode" "RVVM1x3DI") (const_int 64)
618 (eq_attr "mode" "RVVM4x2DI") (const_int 16)
619 (eq_attr "mode" "RVVM2x2DI") (const_int 32)
620 (eq_attr "mode" "RVVM1x2DI") (const_int 64)
621 (eq_attr "mode" "RVVM1x8DF") (const_int 64)
622 (eq_attr "mode" "RVVM1x7DF") (const_int 64)
623 (eq_attr "mode" "RVVM1x6DF") (const_int 64)
624 (eq_attr "mode" "RVVM1x5DF") (const_int 64)
625 (eq_attr "mode" "RVVM2x4DF") (const_int 32)
626 (eq_attr "mode" "RVVM1x4DF") (const_int 64)
627 (eq_attr "mode" "RVVM2x3DF") (const_int 32)
628 (eq_attr "mode" "RVVM1x3DF") (const_int 64)
629 (eq_attr "mode" "RVVM4x2DF") (const_int 16)
630 (eq_attr "mode" "RVVM2x2DF") (const_int 32)
631 (eq_attr "mode" "RVVM1x2DF") (const_int 64)
633 ;; VLS modes.
634 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_ratio(E_V1QImode)")
635 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_ratio(E_V2QImode)")
636 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_ratio(E_V4QImode)")
637 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_ratio(E_V8QImode)")
638 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_ratio(E_V16QImode)")
639 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_ratio(E_V32QImode)")
640 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_ratio(E_V64QImode)")
641 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_ratio(E_V128QImode)")
642 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_ratio(E_V256QImode)")
643 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_ratio(E_V512QImode)")
644 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_ratio(E_V1024QImode)")
645 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_ratio(E_V2048QImode)")
646 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_ratio(E_V4096QImode)")
647 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_ratio(E_V1HImode)")
648 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_ratio(E_V2HImode)")
649 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_ratio(E_V4HImode)")
650 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_ratio(E_V8HImode)")
651 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_ratio(E_V16HImode)")
652 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_ratio(E_V32HImode)")
653 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_ratio(E_V64HImode)")
654 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_ratio(E_V128HImode)")
655 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_ratio(E_V256HImode)")
656 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_ratio(E_V512HImode)")
657 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_ratio(E_V1024HImode)")
658 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_ratio(E_V2048HImode)")
659 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_ratio(E_V1SImode)")
660 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_ratio(E_V2SImode)")
661 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_ratio(E_V4SImode)")
662 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_ratio(E_V8SImode)")
663 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_ratio(E_V16SImode)")
664 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_ratio(E_V32SImode)")
665 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_ratio(E_V64SImode)")
666 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_ratio(E_V128SImode)")
667 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_ratio(E_V256SImode)")
668 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_ratio(E_V512SImode)")
669 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_ratio(E_V1024SImode)")
670 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_ratio(E_V1DImode)")
671 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_ratio(E_V2DImode)")
672 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_ratio(E_V4DImode)")
673 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_ratio(E_V8DImode)")
674 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_ratio(E_V16DImode)")
675 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_ratio(E_V32DImode)")
676 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_ratio(E_V64DImode)")
677 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_ratio(E_V128DImode)")
678 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_ratio(E_V256DImode)")
679 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_ratio(E_V512DImode)")
680 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_ratio(E_V1HFmode)")
681 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_ratio(E_V2HFmode)")
682 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_ratio(E_V4HFmode)")
683 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_ratio(E_V8HFmode)")
684 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_ratio(E_V16HFmode)")
685 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_ratio(E_V32HFmode)")
686 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_ratio(E_V64HFmode)")
687 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_ratio(E_V128HFmode)")
688 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_ratio(E_V256HFmode)")
689 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_ratio(E_V512HFmode)")
690 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_ratio(E_V1024HFmode)")
691 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_ratio(E_V2048HFmode)")
692 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_ratio(E_V1SFmode)")
693 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_ratio(E_V2SFmode)")
694 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_ratio(E_V4SFmode)")
695 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_ratio(E_V8SFmode)")
696 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_ratio(E_V16SFmode)")
697 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_ratio(E_V32SFmode)")
698 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_ratio(E_V64SFmode)")
699 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_ratio(E_V128SFmode)")
700 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_ratio(E_V256SFmode)")
701 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_ratio(E_V512SFmode)")
702 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_ratio(E_V1024SFmode)")
703 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_ratio(E_V1DFmode)")
704 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_ratio(E_V2DFmode)")
705 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_ratio(E_V4DFmode)")
706 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_ratio(E_V8DFmode)")
707 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_ratio(E_V16DFmode)")
708 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_ratio(E_V32DFmode)")
709 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_ratio(E_V64DFmode)")
710 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_ratio(E_V128DFmode)")
711 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_ratio(E_V256DFmode)")
712 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_ratio(E_V512DFmode)")]
713 (const_int INVALID_ATTRIBUTE)))
715 ;; The index of operand[] to get the merge op.
716 (define_attr "merge_op_idx" ""
717 (cond [(eq_attr "type" "vlde,vimov,vfmov,vldm,vlds,vmalu,vldux,vldox,vicmp,\
718 vialu,vshift,viminmax,vimul,vidiv,vsalu,vext,viwalu,\
719 viwmul,vnshift,vaalu,vsmul,vsshift,vnclip,vmsfs,\
720 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
721 vfsqrt,vfrecp,vfsgnj,vfcmp,vfcvtitof,vfcvtftoi,vfwcvtitof,\
722 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,\
723 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\
724 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
725 vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
726 vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh")
727 (const_int 2)
729 (eq_attr "type" "vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
730 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
731 (const_int 1)
733 (eq_attr "type" "vimuladd,vfmuladd")
734 (const_int 2)]
735 (const_int INVALID_ATTRIBUTE)))
737 ;; The index of operand[] represents the machine mode of the instruction.
738 (define_attr "mode_idx" ""
739 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vldff,vldr,vstr,\
740 vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vialu,vext,vicalu,\
741 vshift,vicmp,viminmax,vimul,vidiv,vimuladd,vimerge,vimov,\
742 vsalu,vaalu,vsmul,vsshift,vfalu,vfmul,vfdiv,vfmuladd,vfsqrt,vfrecp,\
743 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
744 vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\
745 vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
746 vgather,vcompress,vmov,vnclip,vnshift")
747 (const_int 0)
749 (eq_attr "type" "vimovvx,vfmovvf")
750 (const_int 1)
752 (eq_attr "type" "vssegte,vmpop,vmffs")
753 (const_int 2)
755 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi,
756 vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo")
757 (const_int 3)
759 (eq_attr "type" "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd")
760 (const_int 4)]
761 (const_int INVALID_ATTRIBUTE)))
763 ;; The index of operand[] to get the avl op.
764 (define_attr "vl_op_idx" ""
765 (cond [(eq_attr "type" "vlde,vste,vimov,vfmov,vldm,vstm,vmalu,vsts,vstux,\
766 vstox,vext,vmsfs,vmiota,vfsqrt,vfrecp,vfcvtitof,vldff,\
767 vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
768 vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\
769 vlsegde,vssegts,vssegtux,vssegtox,vlsegdff,vbrev,vbrev8,vrev8,\
770 vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c")
771 (const_int 4)
773 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
774 ;; wheras it is pred_strided_load if operands[3] is vector mode.
775 (eq_attr "type" "vlds")
776 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
777 (const_int 5)
778 (const_int 4))
780 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
781 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
782 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
783 vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
784 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
785 vgather,viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
786 vror,vwsll,vclmul,vclmulh")
787 (const_int 5)
789 (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd")
790 (const_int 6)
792 (eq_attr "type" "vmpop,vmffs,vmidx,vssegte,vclz,vctz,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
793 vaesz,vsm4r")
794 (const_int 3)]
795 (const_int INVALID_ATTRIBUTE)))
797 ;; The tail policy op value.
798 (define_attr "ta" ""
799 (cond [(eq_attr "type" "vlde,vimov,vfmov,vext,vmiota,vfsqrt,vfrecp,\
800 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\
801 vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\
802 vcompress,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,vghsh,\
803 vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c")
804 (symbol_ref "riscv_vector::get_ta(operands[5])")
806 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
807 ;; wheras it is pred_strided_load if operands[3] is vector mode.
808 (eq_attr "type" "vlds")
809 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
810 (symbol_ref "riscv_vector::get_ta(operands[6])")
811 (symbol_ref "riscv_vector::get_ta(operands[5])"))
813 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
814 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
815 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,\
816 vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\
817 vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
818 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
819 vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh")
820 (symbol_ref "riscv_vector::get_ta(operands[6])")
822 (eq_attr "type" "vimuladd,vfmuladd")
823 (symbol_ref "riscv_vector::get_ta(operands[7])")
825 (eq_attr "type" "vmidx,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,vsm4r")
826 (symbol_ref "riscv_vector::get_ta(operands[4])")]
827 (const_int INVALID_ATTRIBUTE)))
829 ;; The mask policy op value.
830 (define_attr "ma" ""
831 (cond [(eq_attr "type" "vlde,vext,vmiota,vfsqrt,vfrecp,vfcvtitof,vfcvtftoi,\
832 vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
833 vfncvtftof,vfclass,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8")
834 (symbol_ref "riscv_vector::get_ma(operands[6])")
836 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
837 ;; wheras it is pred_strided_load if operands[3] is vector mode.
838 (eq_attr "type" "vlds")
839 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
840 (symbol_ref "riscv_vector::get_ma(operands[7])")
841 (symbol_ref "riscv_vector::get_ma(operands[6])"))
843 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
844 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
845 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,\
846 vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
847 vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\
848 viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
849 vror,vwsll,vclmul,vclmulh")
850 (symbol_ref "riscv_vector::get_ma(operands[7])")
852 (eq_attr "type" "vimuladd,vfmuladd")
853 (symbol_ref "riscv_vector::get_ma(operands[8])")
855 (eq_attr "type" "vmsfs,vmidx")
856 (symbol_ref "riscv_vector::get_ma(operands[5])")]
857 (const_int INVALID_ATTRIBUTE)))
859 ;; The avl type value.
860 (define_attr "avl_type_idx" ""
861 (cond [(eq_attr "type" "vlde,vldff,vste,vimov,vfmov,vext,vimerge,\
862 vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
863 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
864 vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
865 vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota,vbrev,vbrev8,vrev8")
866 (const_int 7)
867 (eq_attr "type" "vldm,vstm,vmalu,vmalu,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,\
868 vsm4r")
869 (const_int 5)
871 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
872 ;; wheras it is pred_strided_load if operands[3] is vector mode.
873 (eq_attr "type" "vlds")
874 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
875 (const_int 8)
876 (const_int 7))
878 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
879 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
880 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
881 vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\
882 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
883 vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll")
884 (const_int 8)
885 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox")
886 (const_int 5)
888 (eq_attr "type" "vimuladd,vfmuladd")
889 (const_int 9)
891 (eq_attr "type" "vmsfs,vmidx,vcompress,vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,\
892 vsm4k,vsm3me,vsm3c")
893 (const_int 6)
895 (eq_attr "type" "vmpop,vmffs,vssegte,vclz,vctz")
896 (const_int 4)]
897 (const_int INVALID_ATTRIBUTE)))
899 ;; Defines rounding mode of an fixed-point operation.
901 (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
902 (cond [(eq_attr "type" "vaalu,vsmul,vsshift,vnclip")
903 (cond
904 [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
905 (const_string "rnu")
907 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
908 (const_string "rne")
910 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
911 (const_string "rdn")
913 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
914 (const_string "rod")]
915 (const_string "none"))]
916 (const_string "none")))
918 ;; Defines rounding mode of an floating-point operation.
919 (define_attr "frm_mode" ""
920 (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
921 (symbol_ref "riscv_vector::FRM_DYN")]
922 (symbol_ref "riscv_vector::FRM_NONE")))
924 (include "thead-vector.md")
926 ;; -----------------------------------------------------------------
927 ;; ---- Miscellaneous Operations
928 ;; -----------------------------------------------------------------
930 (define_insn "@vundefined<mode>"
931 [(set (match_operand:V 0 "register_operand" "=vr")
932 (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
933 "TARGET_VECTOR"
934 ""
935 [(set_attr "type" "vector")])
937 (define_insn "@vundefined<mode>"
938 [(set (match_operand:VB 0 "register_operand" "=vr")
939 (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
940 "TARGET_VECTOR"
941 ""
942 [(set_attr "type" "vector")])
944 (define_insn "@vundefined<mode>"
945 [(set (match_operand:VT 0 "register_operand" "=vr")
946 (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
947 "TARGET_VECTOR"
948 ""
949 [(set_attr "type" "vector")])
951 (define_expand "@vreinterpret<mode>"
952 [(set (match_operand:V 0 "register_operand")
953 (match_operand 1 "vector_any_register_operand"))]
954 "TARGET_VECTOR"
955 {
956 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
957 DONE;
958 }
959 )
961 (define_expand "@vreinterpret<mode>"
962 [(set (match_operand:VB 0 "register_operand")
963 (match_operand 1 "vector_any_register_operand"))]
964 "TARGET_VECTOR"
965 {
966 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
967 DONE;
968 }
969 )
971 ;; This pattern is used to hold the AVL operand for
972 ;; RVV instructions that implicity use VLMAX AVL.
973 ;; RVV instruction implicitly use GPR that is ultimately
974 ;; defined by this pattern is safe for VSETVL pass emit
975 ;; a vsetvl instruction modify this register after RA.
976 ;; Case 1:
977 ;; vlmax_avl a5
978 ;; ... (across many blocks)
979 ;; vadd (implicit use a5) ====> emit: vsetvl a5,zero
980 ;; Case 2:
981 ;; vlmax_avl a5
982 ;; ... (across many blocks)
983 ;; mv a6,a5
984 ;; ... (across many blocks)
985 ;; vadd (implicit use a6) ====> emit: vsetvl a6,zero
986 ;; Case 3:
987 ;; vlmax_avl a5
988 ;; ... (across many blocks)
989 ;; store mem,a5 (spill)
990 ;; ... (across many blocks)
991 ;; load a7,mem (spill)
992 ;; ... (across many blocks)
993 ;; vadd (implicit use a7) ====> emit: vsetvl a7,zero
994 ;; Such cases are all safe for VSETVL PASS to emit a vsetvl
995 ;; instruction that modifies the AVL operand.
996 (define_insn "@vlmax_avl<mode>"
997 [(set (match_operand:P 0 "register_operand" "=r")
998 (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
999 "TARGET_VECTOR"
1000 ""
1001 [(set_attr "type" "vsetvl_pre")]
1002 )
1004 ;; Set VXRM
1005 (define_insn "vxrmsi"
1006 [(set (reg:SI VXRM_REGNUM)
1007 (match_operand:SI 0 "const_int_operand" "i"))]
1008 "TARGET_VECTOR"
1009 "csrwi\tvxrm,%0"
1010 [(set_attr "type" "wrvxrm")
1011 (set_attr "mode" "SI")])
1013 ;; Set FRM
1014 (define_insn "fsrmsi_backup"
1015 [(set (match_operand:SI 0 "register_operand" "=r,r")
1016 (reg:SI FRM_REGNUM))
1017 (set (reg:SI FRM_REGNUM)
1018 (match_operand:SI 1 "reg_or_int_operand" "r,i"))]
1019 "TARGET_VECTOR"
1020 "@
1021 fsrm\t%0,%1
1022 fsrmi\t%0,%1"
1023 [(set_attr "type" "wrfrm,wrfrm")
1024 (set_attr "mode" "SI")]
1025 )
1027 (define_insn "fsrmsi_restore"
1028 [(set (reg:SI FRM_REGNUM)
1029 (match_operand:SI 0 "reg_or_int_operand" "r,i"))]
1030 "TARGET_VECTOR"
1031 "@
1032 fsrm\t%0
1033 fsrmi\t%0"
1034 [(set_attr "type" "wrfrm,wrfrm")
1035 (set_attr "mode" "SI")]
1036 )
1038 ;; The volatile fsrmsi restore is used for the exit point for the
1039 ;; dynamic mode switching. It will generate one volatile fsrm a5
1040 ;; which won't be eliminated.
1041 (define_insn "fsrmsi_restore_volatile"
1042 [(set (reg:SI FRM_REGNUM)
1043 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1044 UNSPECV_FRM_RESTORE_EXIT))]
1045 "TARGET_VECTOR"
1046 "fsrm\t%0"
1047 [(set_attr "type" "wrfrm")
1048 (set_attr "mode" "SI")]
1049 )
1051 ;; Read FRM
1052 (define_insn "frrmsi"
1053 [(set (match_operand:SI 0 "register_operand" "=r")
1054 (reg:SI FRM_REGNUM))]
1055 "TARGET_VECTOR"
1056 "frrm\t%0"
1057 [(set_attr "type" "fmove")
1058 (set_attr "mode" "SI")]
1059 )
1061 ;; -----------------------------------------------------------------
1062 ;; ---- Moves Operations
1063 ;; -----------------------------------------------------------------
1065 (define_expand "mov<mode>"
1066 [(set (match_operand:V 0 "reg_or_mem_operand")
1067 (match_operand:V 1 "general_operand"))]
1068 "TARGET_VECTOR"
1069 {
1070 /* For whole register move, we transform the pattern into the format
1071 that excludes the clobber of scratch register.
1073 We include clobber of a scalar scratch register which is going to be
1074 used for emit of vsetvl instruction after reload_completed since we
1075 need vsetvl instruction to set VL/VTYPE global status for fractional
1076 vector load/store.
1078 For example:
1079 [(set (match_operand:RVVMF8QI v24)
1080 (match_operand:RVVMF8QI (mem: a4)))
1081 (clobber (scratch:SI a5))]
1082 ====>> vsetvl a5,zero,e8,mf8
1083 ====>> vle8.v v24,(a4)
1085 Philosophy:
1087 - Clobber a scalar scratch register for each mov<mode>.
1089 - Classify the machine_mode mode = <MODE>mode into 2 class:
1090 Whole register move and fractional register move.
1092 - Transform and remove scratch clobber register for whole
1093 register move so that we can avoid occupying the scalar
1094 registers.
1096 - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
1097 before spilling. The clobber scratch is used by spilling fractional
1098 registers in IRA/LRA so it's too early. */
1099 if (TARGET_XTHEADVECTOR)
1100 {
1101 emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
1102 RVV_VLMAX, GEN_INT(riscv_vector::VLMAX)));
1103 DONE;
1104 }
1106 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1107 DONE;
1108 })
1110 ;; This pattern is used for code-gen for whole register load/stores.
1111 ;; Also applicable for all register moves.
1112 ;; Fractional vector modes load/store are not allowed to match this pattern.
1113 ;; Mask modes load/store are not allowed to match this pattern.
1114 ;; We seperate "*mov<mode>" into "*mov<mode>_whole" and "*mov<mode>_fract" because
1115 ;; we don't want to include fractional load/store in "*mov<mode>" which will
1116 ;; create unexpected patterns in LRA.
1117 ;; For example:
1118 ;; ira rtl:
1119 ;; (insn 20 19 9 2 (set (reg/v:RVVMF4QI 97 v1 [ v1 ])
1120 ;; (reg:RVVMF4QI 134 [ _1 ])) "rvv.c":9:22 571 {*movvnx2qi_fract}
1121 ;; (nil))
1122 ;; When the value of pseudo register 134 of the insn above is discovered already
1123 ;; spilled in the memory during LRA.
1124 ;; LRA will reload this pattern into a memory load instruction pattern.
1125 ;; Because RVVMF4QI is a fractional vector, we want LRA reload this pattern into
1126 ;; (insn 20 19 9 2 (parallel [
1127 ;; (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1128 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8]))
1129 ;; (clobber (reg:SI 14 a4 [149]))])
1130 ;; So that we could be able to emit vsetvl instruction using clobber sratch a4.
1131 ;; To let LRA generate the expected pattern, we should exclude fractional vector
1132 ;; load/store in "*mov<mode>_whole". Otherwise, it will reload this pattern into:
1133 ;; (insn 20 19 9 2 (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1134 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8])))
1135 ;; which is not the pattern we want.
1136 ;; According the facts above, we make "*mov<mode>_whole" includes load/store/move for whole
1137 ;; vector modes according to '-march' and "*mov<mode>_fract" only include fractional vector modes.
1138 (define_insn "*mov<mode>_whole"
1139 [(set (match_operand:V_WHOLE 0 "reg_or_mem_operand" "=vr, m,vr")
1140 (match_operand:V_WHOLE 1 "reg_or_mem_operand" " m,vr,vr"))]
1141 "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
1142 "@
1143 vl%m1re<sew>.v\t%0,%1
1144 vs%m1r.v\t%1,%0
1145 vmv%m1r.v\t%0,%1"
1146 [(set_attr "type" "vldr,vstr,vmov")
1147 (set_attr "mode" "<MODE>")])
1149 (define_insn "*mov<mode>_fract"
1150 [(set (match_operand:V_FRACT 0 "register_operand" "=vr")
1151 (match_operand:V_FRACT 1 "register_operand" " vr"))]
1152 "TARGET_VECTOR"
1153 "vmv1r.v\t%0,%1"
1154 [(set_attr "type" "vmov")
1155 (set_attr "mode" "<MODE>")])
1157 (define_expand "mov<mode>"
1158 [(set (match_operand:VB 0 "reg_or_mem_operand")
1159 (match_operand:VB 1 "general_operand"))]
1160 "TARGET_VECTOR"
1161 {
1162 if (TARGET_XTHEADVECTOR)
1163 {
1164 emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
1165 RVV_VLMAX, GEN_INT(riscv_vector::VLMAX)));
1166 DONE;
1167 }
1169 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1170 DONE;
1171 })
1173 (define_insn "*mov<mode>"
1174 [(set (match_operand:VB 0 "register_operand" "=vr")
1175 (match_operand:VB 1 "register_operand" " vr"))]
1176 "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
1177 "vmv1r.v\t%0,%1"
1178 [(set_attr "type" "vmov")
1179 (set_attr "mode" "<MODE>")])
1181 (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
1182 [(parallel
1183 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
1184 (match_operand:V_FRACT 1 "reg_or_mem_operand"))
1185 (clobber (match_scratch:P 2))])]
1186 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1187 {})
1189 (define_expand "@mov<VB:mode><P:mode>_lra"
1190 [(parallel
1191 [(set (match_operand:VB 0 "reg_or_mem_operand")
1192 (match_operand:VB 1 "reg_or_mem_operand"))
1193 (clobber (match_scratch:P 2))])]
1194 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1195 {})
1197 (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
1198 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
1199 (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
1200 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1201 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1202 "#"
1203 "&& reload_completed"
1204 [(const_int 0)]
1205 {
1206 if (REG_P (operands[0]) && REG_P (operands[1]))
1207 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1208 else
1209 {
1210 riscv_vector::emit_vlmax_vsetvl (<V_FRACT:MODE>mode, operands[2]);
1211 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<V_FRACT:MODE>mode),
1212 riscv_vector::UNARY_OP, operands, operands[2]);
1213 }
1214 DONE;
1215 }
1216 [(set_attr "type" "vector")]
1217 )
1219 (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
1220 [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
1221 (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
1222 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1223 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1224 "#"
1225 "&& reload_completed"
1226 [(const_int 0)]
1227 {
1228 if (REG_P (operands[0]) && REG_P (operands[1]))
1229 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1230 else
1231 {
1232 riscv_vector::emit_vlmax_vsetvl (<VB:MODE>mode, operands[2]);
1233 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<VB:MODE>mode),
1234 riscv_vector::UNARY_MASK_OP, operands, operands[2]);
1235 }
1236 DONE;
1237 }
1238 [(set_attr "type" "vector")]
1239 )
1241 ;; Define tuple modes data movement.
1242 ;; operands[2] is used to save the offset of each subpart.
1243 ;; operands[3] is used to calculate the address for each subpart.
1244 ;; operands[4] is VL of vsevli instruction.
1245 (define_expand "mov<mode>"
1246 [(parallel [(set (match_operand:VT 0 "reg_or_mem_operand")
1247 (match_operand:VT 1 "general_operand"))
1248 (clobber (match_dup 2))
1249 (clobber (match_dup 3))
1250 (clobber (match_dup 4))])]
1251 "TARGET_VECTOR"
1252 {
1253 /* Need to force register if mem <- !reg. */
1254 if (MEM_P (operands[0]) && !REG_P (operands[1]))
1255 operands[1] = force_reg (<MODE>mode, operands[1]);
1257 if (GET_CODE (operands[1]) == CONST_VECTOR)
1258 {
1259 riscv_vector::expand_tuple_move (operands);
1260 DONE;
1261 }
1263 operands[2] = gen_rtx_SCRATCH (Pmode);
1264 operands[3] = gen_rtx_SCRATCH (Pmode);
1265 operands[4] = gen_rtx_SCRATCH (Pmode);
1266 })
1268 (define_insn_and_split "*mov<VT:mode>_<P:mode>"
1269 [(set (match_operand:VT 0 "reg_or_mem_operand" "=vr,vr, m")
1270 (match_operand:VT 1 "reg_or_mem_operand" " vr, m,vr"))
1271 (clobber (match_scratch:P 2 "=X,&r,&r"))
1272 (clobber (match_scratch:P 3 "=X,&r,&r"))
1273 (clobber (match_scratch:P 4 "=X,&r,&r"))]
1274 "TARGET_VECTOR"
1275 "#"
1276 "&& reload_completed"
1277 [(const_int 0)]
1278 {
1279 riscv_vector::expand_tuple_move (operands);
1280 DONE;
1281 }
1282 [(set_attr "type" "vmov,vlde,vste")
1283 (set_attr "mode" "<VT:MODE>")
1284 (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
1285 (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))])
1287 ;; -----------------------------------------------------------------
1288 ;; ---- VLS Moves Operations
1289 ;; -----------------------------------------------------------------
1291 (define_expand "mov<mode>"
1292 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
1293 (match_operand:VLS_AVL_IMM 1 "general_operand"))]
1294 "TARGET_VECTOR"
1295 {
1296 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1297 DONE;
1298 })
1300 (define_insn_and_split "*mov<mode>"
1301 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
1302 (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
1303 "TARGET_VECTOR
1304 && (register_operand (operands[0], <MODE>mode)
1305 || register_operand (operands[1], <MODE>mode))"
1306 "@
1307 #
1308 #
1309 vmv%m1r.v\t%0,%1"
1310 "&& reload_completed
1311 && (!register_operand (operands[0], <MODE>mode)
1312 || !register_operand (operands[1], <MODE>mode))"
1313 [(const_int 0)]
1314 {
1315 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1316 gcc_assert (ok_p);
1317 DONE;
1318 }
1319 [(set_attr "type" "vmov")]
1320 )
1322 (define_expand "mov<mode>"
1323 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1324 (match_operand:VLS_AVL_REG 1 "general_operand"))]
1325 "TARGET_VECTOR"
1326 {
1327 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1328 gcc_assert (ok_p);
1329 DONE;
1330 })
1332 (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
1333 [(parallel
1334 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1335 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
1336 (clobber (match_scratch:P 2))])]
1337 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1338 {})
1340 (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
1341 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
1342 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
1343 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1344 "TARGET_VECTOR && (lra_in_progress || reload_completed)
1345 && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
1346 || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
1347 "#"
1348 "&& reload_completed"
1349 [(const_int 0)]
1350 {
1351 if (REG_P (operands[0]) && REG_P (operands[1]))
1352 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1353 else
1354 {
1355 emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
1356 Pmode));
1357 unsigned insn_flags
1358 = GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
1359 ? riscv_vector::UNARY_MASK_OP
1360 : riscv_vector::UNARY_OP;
1361 riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
1362 insn_flags, operands, operands[2]);
1363 }
1364 DONE;
1365 }
1366 [(set_attr "type" "vmov")]
1367 )
1369 (define_insn "*mov<mode>_vls"
1370 [(set (match_operand:VLS 0 "register_operand" "=vr")
1371 (match_operand:VLS 1 "register_operand" " vr"))]
1372 "TARGET_VECTOR"
1373 "vmv%m1r.v\t%0,%1"
1374 [(set_attr "type" "vmov")
1375 (set_attr "mode" "<MODE>")])
1377 (define_insn "*mov<mode>_vls"
1378 [(set (match_operand:VLSB 0 "register_operand" "=vr")
1379 (match_operand:VLSB 1 "register_operand" " vr"))]
1380 "TARGET_VECTOR"
1381 "vmv1r.v\t%0,%1"
1382 [(set_attr "type" "vmov")
1383 (set_attr "mode" "<MODE>")])
1385 ;; According to RVV ISA:
1386 ;; If an element accessed by a vector memory instruction is not naturally aligned to the size of the element,
1387 ;; either the element is transferred successfully or an address misaligned exception is raised on that element.
1388 (define_expand "movmisalign<mode>"
1389 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1390 (match_operand:V_VLS 1 "general_operand"))]
1391 "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
1392 {
1393 emit_move_insn (operands[0], operands[1]);
1394 DONE;
1395 }
1396 )
1398 ;; -----------------------------------------------------------------
1399 ;; ---- Duplicate Operations
1400 ;; -----------------------------------------------------------------
1402 (define_expand "vec_duplicate<mode>"
1403 [(set (match_operand:V_VLS 0 "register_operand")
1404 (vec_duplicate:V_VLS
1405 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1406 "TARGET_VECTOR"
1407 {
1408 /* Early expand DImode broadcast in RV32 system to avoid RA reload
1409 generate (set (reg) (vec_duplicate:DI)). */
1410 if (maybe_gt (GET_MODE_SIZE (<VEL>mode), GET_MODE_SIZE (Pmode)))
1411 {
1412 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1413 riscv_vector::UNARY_OP, operands);
1414 DONE;
1415 }
1416 /* Otherwise, allow it fall into general vec_duplicate pattern
1417 which allow us to have vv->vx combine optimization in later pass. */
1418 })
1420 ;; According to GCC internal:
1421 ;; This pattern only handles duplicates of non-constant inputs.
1422 ;; Constant vectors go through the movm pattern instead.
1423 ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT.
1424 (define_insn_and_split "*vec_duplicate<mode>"
1425 [(set (match_operand:V_VLS 0 "register_operand")
1426 (vec_duplicate:V_VLS
1427 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1428 "TARGET_VECTOR && can_create_pseudo_p ()"
1429 "#"
1430 "&& 1"
1431 [(const_int 0)]
1432 {
1433 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1434 riscv_vector::UNARY_OP, operands);
1435 DONE;
1436 }
1437 [(set_attr "type" "vector")]
1438 )
1440 ;; -----------------------------------------------------------------
1441 ;; ---- 6. Configuration-Setting Instructions
1442 ;; -----------------------------------------------------------------
1443 ;; Includes:
1444 ;; - 6.1 vsetvli/vsetivl/vsetvl instructions
1445 ;; -----------------------------------------------------------------
1447 ;; we dont't define vsetvli as unspec_volatile which has side effects.
1448 ;; This instruction can be scheduled by the instruction scheduler.
1449 ;; This means these instructions will be deleted when
1450 ;; there is no instructions using vl or vtype in the following.
1451 ;; rd | rs1 | AVL value | Effect on vl
1452 ;; - | !x0 | x[rs1] | Normal stripmining
1453 ;; !x0 | x0 | ~0 | Set vl to VLMAX
1454 ;; operands[0]: VL.
1455 ;; operands[1]: AVL.
1456 ;; operands[2]: SEW
1457 ;; operands[3]: LMUL
1458 ;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)
1459 ;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)
1461 ;; We define 2 types of "vsetvl*" instruction patterns:
1463 ;; - "@vsetvl<mode>" is a parallel format which has side effects.
1465 ;; - "@vsetvl<mode>_no_side_effects" has no side effects.
1467 ;; - "@vsetvl<mode>" is used by "vsetvl" intrinsics and "insert-vsetvl" PASS.
1469 ;; - "@vsetvl<mode>_no_side_effects" is used by GCC standard patterns.
1471 ;; - "@vsetvl<mode>" includes VL/VTYPE global registers status (define set)
1472 ;; and each RVV instruction includes VL/VTYPE global registers status (use)
1473 ;; so that we can guarantee each RVV instruction can execute with correct
1474 ;; VL/VTYPE global registers status after "insert-vsetvl" PASS.
1476 ;; - "@vsetvl<mode>_no_side_effects" has no side effects and excludes VL/VTYPE
1477 ;; global registers status (define set). It's only used by GCC standard pattern
1478 ;; expansion. For example: "mov<mode>" pattern for fractional vector modes which
1479 ;; need to set VL/VTYPE. Then we could manually call this pattern to gain benefits
1480 ;; from the optimization of each GCC internal PASS.
1482 ;; 1. void foo (float *in, float *out)
1483 ;; {
1484 ;; vfloat32mf2_t v = *(vfloat32mf2_t*)in;
1485 ;; *(vfloat32mf2_t*)out = v;
1486 ;; }
1487 ;; We could eliminate the second "vsetvl" by calling "@vsetvl<mode>_no_side_effects".
1488 ;;
1489 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1490 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; vsetvli a4,zero,e32,mf2,ta,ma
1491 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1492 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; --
1493 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1494 ;; ret ;; ret
1496 ;; 2. void foo (int8_t *in, int8_t *out, int M)
1497 ;; {
1498 ;; for (int i = 0; i < M; i++){
1499 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1500 ;; *(vint8mf2_t*)(out + i) = v;
1501 ;; }
1502 ;; }
1503 ;;
1504 ;; Hoist "vsetvl" instruction in LICM:
1505 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1506 ;; - ;; vsetvli a4,zero,e32,mf2,ta,ma
1507 ;; LOOP: ;; LOOP:
1508 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1509 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1510 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1511 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1513 ;; However, it may produce wrong codegen if we exclude VL/VTYPE in "vsevl<mode>".
1514 ;; 3. void foo (int8_t *in, int8_t *out, int32_t *in2, int32_t *out2, int M)
1515 ;; {
1516 ;; for (int i = 0; i < M; i++){
1517 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1518 ;; vint32mf2_t v2 = *(vint32mf2_t*)(in + i + i);
1519 ;; *(vint8mf2_t*)(out + i) = v;
1520 ;; *(vint32mf2_t*)(out + i + i) = v2;
1521 ;; }
1522 ;; }
1523 ;;
1524 ;; vsetvli a6,zero,e8,mf2,ta,ma
1525 ;; vsetvli a2,zero,e32,mf2,ta,ma
1526 ;; LOOP:
1527 ;; vle8.v v25,(a0)
1528 ;; vle32.v v24,(a5)
1529 ;; addi a0,a0,1
1530 ;; vse8.v v25,(a1)
1531 ;; vse32.v v24,(a3)
1532 ;;
1533 ;; Both vle8.v and vle32.v are using the wrong VL/VTYPE status.
1534 ;; We leave it to "insert-vsetvl" PASS to correct this situation.
1536 ;; The "insert-vsetvl" PASS mechanism:
1537 ;; 1. Before "insert-vsetvl" PASS, only RVV instructions are generated
1538 ;; by GCC standard pattern expansion has the corresponding "vsetvl".
1539 ;; We exploit each GCC internal optimization pass to optimize the "vsetvl".
1540 ;; 2. Correct the VL/VTYPE status for each GCC standard pattern RVV instructions.
1541 ;; Insert vsetvl for each RVV instructions that has no VL/VTYPE status if necessary.
1542 ;; For example: RVV intrinsics.
1543 ;; 3. Optimize "vsetvl" instructions.
1545 (define_insn "@vsetvl<mode>"
1546 [(set (match_operand:P 0 "register_operand" "=r")
1547 (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
1548 (match_operand 2 "const_int_operand" "i")
1549 (match_operand 3 "const_int_operand" "i")
1550 (match_operand 4 "const_int_operand" "i")
1551 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
1552 (set (reg:SI VL_REGNUM)
1553 (unspec:SI [(match_dup 1)
1554 (match_dup 2)
1555 (match_dup 3)] UNSPEC_VSETVL))
1556 (set (reg:SI VTYPE_REGNUM)
1557 (unspec:SI [(match_dup 2)
1558 (match_dup 3)
1559 (match_dup 4)
1560 (match_dup 5)] UNSPEC_VSETVL))]
1561 "TARGET_VECTOR"
1562 "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
1563 [(set_attr "type" "vsetvl")
1564 (set_attr "mode" "<MODE>")
1565 (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
1566 (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
1567 (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
1568 (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
1570 ;; vsetvl zero,zero,vtype instruction.
1571 ;; This pattern has no side effects and does not set X0 register.
1572 (define_insn "vsetvl_vtype_change_only"
1573 [(set (reg:SI VTYPE_REGNUM)
1574 (unspec:SI
1575 [(match_operand 0 "const_int_operand" "i")
1576 (match_operand 1 "const_int_operand" "i")
1577 (match_operand 2 "const_int_operand" "i")
1578 (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
1579 "TARGET_VECTOR"
1580 "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
1581 [(set_attr "type" "vsetvl")
1582 (set_attr "mode" "SI")
1583 (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
1584 (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
1585 (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
1586 (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
1588 ;; vsetvl zero,rs1,vtype instruction.
1589 ;; The reason we need this pattern since we should avoid setting X0 register
1590 ;; in vsetvl instruction pattern.
1591 (define_insn "@vsetvl_discard_result<mode>"
1592 [(set (reg:SI VL_REGNUM)
1593 (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK")
1594 (match_operand 1 "const_int_operand" "i")
1595 (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
1596 (set (reg:SI VTYPE_REGNUM)
1597 (unspec:SI [(match_dup 1)
1598 (match_dup 2)
1599 (match_operand 3 "const_int_operand" "i")
1600 (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
1601 "TARGET_VECTOR"
1602 "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
1603 [(set_attr "type" "vsetvl")
1604 (set_attr "mode" "<MODE>")
1605 (set (attr "sew") (symbol_ref "INTVAL (operands[1])"))
1606 (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])"))
1607 (set (attr "ta") (symbol_ref "INTVAL (operands[3])"))
1608 (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))])
1610 ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.
1611 ;; Since we have many optmization passes from "expand" to "reload_completed",
1612 ;; such pattern can allow us gain benefits of these optimizations.
1613 (define_insn_and_split "@vsetvl<mode>_no_side_effects"
1614 [(set (match_operand:P 0 "register_operand" "=r")
1615 (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
1616 (match_operand 2 "const_int_operand" "i")
1617 (match_operand 3 "const_int_operand" "i")
1618 (match_operand 4 "const_int_operand" "i")
1619 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
1620 "TARGET_VECTOR"
1621 "#"
1622 "&& epilogue_completed"
1623 [(parallel
1624 [(set (match_dup 0)
1625 (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
1626 (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
1627 (set (reg:SI VL_REGNUM)
1628 (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
1629 (set (reg:SI VTYPE_REGNUM)
1630 (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
1631 (match_dup 5)] UNSPEC_VSETVL))])]
1632 ""
1633 [(set_attr "type" "vsetvl")
1634 (set_attr "mode" "SI")])
1636 ;; This pattern use to combine bellow two insns and then further remove
1637 ;; unnecessary sign_extend operations:
1638 ;; (set (reg:DI 134 [ _1 ])
1639 ;; (unspec:DI [
1640 ;; (const_int 19 [0x13])
1641 ;; (const_int 8 [0x8])
1642 ;; (const_int 5 [0x5])
1643 ;; (const_int 2 [0x2]) repeated x2
1644 ;; ] UNSPEC_VSETVL))
1645 ;; (set (reg/v:DI 135 [ <retval> ])
1646 ;; (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0)))
1647 ;;
1648 ;; The reason we can remove signe_extend is because currently the vl value
1649 ;; returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and
1650 ;; bits 17 to 63 (including 31) are always 0, so there is no change after
1651 ;; sign_extend. Note that for HI and QI modes we cannot do this.
1652 ;; Of course, if the range of instructions returned by vsetvl later expands
1653 ;; to 32bits, then this combine pattern needs to be removed. But that could be
1654 ;; a long time from now.
1655 (define_insn_and_split "*vsetvldi_no_side_effects_si_extend"
1656 [(set (match_operand:DI 0 "register_operand")
1657 (sign_extend:DI
1658 (subreg:SI
1659 (unspec:DI [(match_operand:P 1 "vector_length_operand")
1660 (match_operand 2 "const_int_operand")
1661 (match_operand 3 "const_int_operand")
1662 (match_operand 4 "const_int_operand")
1663 (match_operand 5 "const_int_operand")] UNSPEC_VSETVL) 0)))]
1664 "TARGET_VECTOR && TARGET_64BIT"
1665 "#"
1666 "&& 1"
1667 [(set (match_dup 0)
1668 (unspec:DI [(match_dup 1)
1669 (match_dup 2)
1670 (match_dup 3)
1671 (match_dup 4)
1672 (match_dup 5)] UNSPEC_VSETVL))]
1673 ""
1674 [(set_attr "type" "vsetvl")
1675 (set_attr "mode" "SI")])
1677 ;; RVV machine description matching format
1678 ;; (define_insn ""
1679 ;; [(set (match_operand:MODE 0)
1680 ;; (if_then_else:MODE
1681 ;; (unspec:<MODE:VM>
1682 ;; [(match_operand:<VM> 1 "vector_mask_operand")
1683 ;; (match_operand N + 4 "vector_length_operand")
1684 ;; (match_operand N + 5 "const_int_operand")
1685 ;; (match_operand N + 6 "const_int_operand")
1686 ;; (reg:SI VL_REGNUM)
1687 ;; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1688 ;; (instruction operation:MODE
1689 ;; (match_operand 3
1690 ;; (match_operand 4
1691 ;; (match_operand 5
1692 ;; ................
1693 ;; (match_operand N + 3)
1694 ;; (match_operand:MODE 2 "vector_reg_or_const0_operand")))]
1695 ;;
1696 ;; (unspec:[........] UNSPEC_VPREDICATE) is a predicate wrapper.
1697 ;; Include mask predicate && length predicate && vector policy.
1699 ;; -------------------------------------------------------------------------------
1700 ;; ---- Predicated Mov
1701 ;; -------------------------------------------------------------------------------
1702 ;; Includes:
1703 ;; - 7.4. Vector Unit-Stride Instructions
1704 ;; - 11.15 Vector Integer Merge Instructions
1705 ;; - 11.16 Vector Integer Move Instructions
1706 ;; - 13.16 Vector Floating-Point Move Instruction
1707 ;; - 15.1 Vector Mask-Register Logical Instructions
1708 ;; -------------------------------------------------------------------------------
1710 ;; vle.v/vse.v/vmv.v.v.
1711 ;; For vle.v/vmv.v.v, we may need merge and mask operand.
1712 ;; For vse.v, we don't need merge operand, so it should always match "vu".
1713 ;; constraint alternative 0 ~ 1 match vle.v.
1714 ;; constraint alternative 2 match vse.v.
1715 ;; constraint alternative 3 match vmv.v.v.
1717 ;; If operand 3 is a const_vector, then it is left to pred_braordcast patterns.
1718 (define_expand "@pred_mov<mode>"
1719 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1720 (if_then_else:V_VLS
1721 (unspec:<VM>
1722 [(match_operand:<VM> 1 "vector_mask_operand")
1723 (match_operand 4 "vector_length_operand")
1724 (match_operand 5 "const_int_operand")
1725 (match_operand 6 "const_int_operand")
1726 (match_operand 7 "const_int_operand")
1727 (reg:SI VL_REGNUM)
1728 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1729 (match_operand:V_VLS 3 "vector_move_operand")
1730 (match_operand:V_VLS 2 "vector_merge_operand")))]
1731 "TARGET_VECTOR"
1732 {})
1734 ;; vle.v/vse.v,vmv.v.v
1735 (define_insn_and_split "*pred_mov<mode>"
1736 [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=vr, vr, vd, m, vr, vr")
1737 (if_then_else:V_VLS
1738 (unspec:<VM>
1739 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, Wc1")
1740 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
1741 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
1742 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
1743 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
1744 (reg:SI VL_REGNUM)
1745 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1746 (match_operand:V_VLS 3 "reg_or_mem_operand" " m, m, m, vr, vr, vr")
1747 (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, vu, vu, 0")))]
1748 "(TARGET_VECTOR
1749 && (register_operand (operands[0], <MODE>mode)
1750 || register_operand (operands[3], <MODE>mode)))"
1751 "@
1752 vle<sew>.v\t%0,%3%p1
1753 vle<sew>.v\t%0,%3
1754 vle<sew>.v\t%0,%3,%1.t
1755 vse<sew>.v\t%3,%0%p1
1756 vmv.v.v\t%0,%3
1757 vmv.v.v\t%0,%3"
1758 "&& riscv_vector::whole_reg_to_reg_move_p (operands, <MODE>mode, 7)"
1759 [(set (match_dup 0) (match_dup 3))]
1760 ""
1761 [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
1762 (set_attr "mode" "<MODE>")])
1764 ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include
1765 ;; memory operand as input which will produce inferior codegen.
1766 (define_insn "@pred_store<mode>"
1767 [(set (match_operand:V 0 "memory_operand" "+m")
1768 (if_then_else:V
1769 (unspec:<VM>
1770 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
1771 (match_operand 3 "vector_length_operand" " rK")
1772 (match_operand 4 "const_int_operand" " i")
1773 (reg:SI VL_REGNUM)
1774 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1775 (match_operand:V 2 "register_operand" " vr")
1776 (match_dup 0)))]
1777 "TARGET_VECTOR"
1778 "vse<sew>.v\t%2,%0%p1"
1779 [(set_attr "type" "vste")
1780 (set_attr "mode" "<MODE>")
1781 (set (attr "avl_type_idx") (const_int 4))
1782 (set_attr "vl_op_idx" "3")])
1784 ;; vlm.v/vsm.v/vmclr.m/vmset.m.
1785 ;; constraint alternative 0 match vlm.v.
1786 ;; constraint alternative 1 match vsm.v.
1787 ;; constraint alternative 3 match vmclr.m.
1788 ;; constraint alternative 4 match vmset.m.
1789 (define_insn_and_split "@pred_mov<mode>"
1790 [(set (match_operand:VB_VLS 0 "nonimmediate_operand" "=vr, m, vr, vr, vr")
1791 (if_then_else:VB_VLS
1792 (unspec:VB_VLS
1793 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
1794 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
1795 (match_operand 5 "const_int_operand" " i, i, i, i, i")
1796 (reg:SI VL_REGNUM)
1797 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1798 (match_operand:VB_VLS 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
1799 (match_operand:VB_VLS 2 "vector_undef_operand" " vu, vu, vu, vu, vu")))]
1800 "TARGET_VECTOR"
1801 "@
1802 vlm.v\t%0,%3
1803 vsm.v\t%3,%0
1804 vmmv.m\t%0,%3
1805 vmclr.m\t%0
1806 vmset.m\t%0"
1807 "&& riscv_vector::whole_reg_to_reg_move_p (operands, <MODE>mode, 5)"
1808 [(set (match_dup 0) (match_dup 3))]
1809 ""
1810 [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu")
1811 (set_attr "mode" "<MODE>")])
1813 ;; Dedicated pattern for vsm.v instruction since we can't reuse pred_mov pattern to include
1814 ;; memory operand as input which will produce inferior codegen.
1815 (define_insn "@pred_store<mode>"
1816 [(set (match_operand:VB 0 "memory_operand" "+m")
1817 (if_then_else:VB
1818 (unspec:VB
1819 [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
1820 (match_operand 3 "vector_length_operand" " rK")
1821 (match_operand 4 "const_int_operand" " i")
1822 (reg:SI VL_REGNUM)
1823 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1824 (match_operand:VB 2 "register_operand" " vr")
1825 (match_dup 0)))]
1826 "TARGET_VECTOR"
1827 "vsm.v\t%2,%0"
1828 [(set_attr "type" "vstm")
1829 (set_attr "mode" "<MODE>")
1830 (set (attr "avl_type_idx") (const_int 4))
1831 (set_attr "vl_op_idx" "3")])
1833 (define_insn "@pred_merge<mode>"
1834 [(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd")
1835 (if_then_else:V_VLS
1836 (unspec:<VM>
1837 [(match_operand 5 "vector_length_operand" " rK,rK,rK,rK")
1838 (match_operand 6 "const_int_operand" " i, i, i, i")
1839 (match_operand 7 "const_int_operand" " i, i, i, i")
1840 (reg:SI VL_REGNUM)
1841 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1842 (vec_merge:V_VLS
1843 (match_operand:V_VLS 3 "vector_arith_operand" " vr,vr,vi,vi")
1844 (match_operand:V_VLS 2 "register_operand" " vr,vr,vr,vr")
1845 (match_operand:<VM> 4 "register_operand" " vm,vm,vm,vm"))
1846 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0,vu, 0")))]
1847 "TARGET_VECTOR"
1848 "vmerge.v%o3m\t%0,%2,%v3,%4"
1849 [(set_attr "type" "vimerge")
1850 (set_attr "mode" "<MODE>")])
1852 (define_insn "@pred_merge<mode>_scalar"
1853 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd")
1854 (if_then_else:V_VLSI_QHS
1855 (unspec:<VM>
1856 [(match_operand 5 "vector_length_operand" " rK,rK")
1857 (match_operand 6 "const_int_operand" " i, i")
1858 (match_operand 7 "const_int_operand" " i, i")
1859 (reg:SI VL_REGNUM)
1860 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1861 (vec_merge:V_VLSI_QHS
1862 (vec_duplicate:V_VLSI_QHS
1863 (match_operand:<VEL> 3 "register_operand" " r, r"))
1864 (match_operand:V_VLSI_QHS 2 "register_operand" " vr,vr")
1865 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1866 (match_operand:V_VLSI_QHS 1 "vector_merge_operand" " vu, 0")))]
1867 "TARGET_VECTOR"
1868 "vmerge.vxm\t%0,%2,%3,%4"
1869 [(set_attr "type" "vimerge")
1870 (set_attr "mode" "<MODE>")])
1872 (define_expand "@pred_merge<mode>_scalar"
1873 [(set (match_operand:V_VLSI_D 0 "register_operand")
1874 (if_then_else:V_VLSI_D
1875 (unspec:<VM>
1876 [(match_operand 5 "vector_length_operand")
1877 (match_operand 6 "const_int_operand")
1878 (match_operand 7 "const_int_operand")
1879 (reg:SI VL_REGNUM)
1880 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1881 (vec_merge:V_VLSI_D
1882 (vec_duplicate:V_VLSI_D
1883 (match_operand:<VEL> 3 "reg_or_int_operand"))
1884 (match_operand:V_VLSI_D 2 "register_operand")
1885 (match_operand:<VM> 4 "register_operand"))
1886 (match_operand:V_VLSI_D 1 "vector_merge_operand")))]
1887 "TARGET_VECTOR"
1888 {
1889 if (riscv_vector::sew64_scalar_helper (
1890 operands,
1891 /* scalar op */&operands[3],
1892 /* vl */operands[5],
1893 <MODE>mode,
1894 riscv_vector::simm5_p (operands[3]),
1895 [] (rtx *operands, rtx boardcast_scalar) {
1896 emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
1897 operands[2], boardcast_scalar, operands[4], operands[5],
1898 operands[6], operands[7]));
1899 },
1900 (riscv_vector::avl_type) INTVAL (operands[7])))
1901 DONE;
1902 })
1904 (define_insn "*pred_merge<mode>_scalar"
1905 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1906 (if_then_else:V_VLSI_D
1907 (unspec:<VM>
1908 [(match_operand 5 "vector_length_operand" " rK,rK")
1909 (match_operand 6 "const_int_operand" " i, i")
1910 (match_operand 7 "const_int_operand" " i, i")
1911 (reg:SI VL_REGNUM)
1912 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1913 (vec_merge:V_VLSI_D
1914 (vec_duplicate:V_VLSI_D
1915 (match_operand:<VEL> 3 "register_operand" " r, r"))
1916 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1917 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1918 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1919 "TARGET_VECTOR"
1920 "vmerge.vxm\t%0,%2,%3,%4"
1921 [(set_attr "type" "vimerge")
1922 (set_attr "mode" "<MODE>")])
1924 (define_insn "*pred_merge<mode>_extended_scalar"
1925 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1926 (if_then_else:V_VLSI_D
1927 (unspec:<VM>
1928 [(match_operand 5 "vector_length_operand" " rK,rK")
1929 (match_operand 6 "const_int_operand" " i, i")
1930 (match_operand 7 "const_int_operand" " i, i")
1931 (reg:SI VL_REGNUM)
1932 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1933 (vec_merge:V_VLSI_D
1934 (vec_duplicate:V_VLSI_D
1935 (sign_extend:<VEL>
1936 (match_operand:<VSUBEL> 3 "register_operand" " r, r")))
1937 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1938 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1939 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1940 "TARGET_VECTOR && !TARGET_64BIT"
1941 "vmerge.vxm\t%0,%2,%3,%4"
1942 [(set_attr "type" "vimerge")
1943 (set_attr "mode" "<MODE>")])
1945 ;; -------------------------------------------------------------------------------
1946 ;; ---- Predicated Broadcast
1947 ;; -------------------------------------------------------------------------------
1948 ;; Includes:
1949 ;; - 7.5. Vector Strided Instructions (zero stride)
1950 ;; - 11.16 Vector Integer Move Instructions (vmv.v.x)
1951 ;; - 13.16 Vector Floating-Point Move Instruction (vfmv.v.f)
1952 ;; - 16.1 Integer Scalar Move Instructions (vmv.s.x)
1953 ;; - 16.2 Floating-Point Scalar Move Instructions (vfmv.s.f)
1954 ;; -------------------------------------------------------------------------------
1956 ;; According to RVV ISA, vector-scalar instruction doesn't support
1957 ;; operand fetched from 2 consecutive registers, so we should use
1958 ;; vlse.v which is a memory access to broadcast a DImode scalar into a vector.
1959 ;;
1960 ;; Since the optimization flow in GCC is as follows:
1961 ;; expand --> LICM (Loop invariant) --> split.
1962 ;; To use LICM optimization, we postpone generation of vlse.v to split stage since
1963 ;; a memory access instruction can not be optimized by LICM (Loop invariant).
1964 (define_expand "@pred_broadcast<mode>"
1965 [(set (match_operand:V_VLS 0 "register_operand")
1966 (if_then_else:V_VLS
1967 (unspec:<VM>
1968 [(match_operand:<VM> 1 "vector_broadcast_mask_operand")
1969 (match_operand 4 "vector_length_operand")
1970 (match_operand 5 "const_int_operand")
1971 (match_operand 6 "const_int_operand")
1972 (match_operand 7 "const_int_operand")
1973 (reg:SI VL_REGNUM)
1974 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1975 (vec_duplicate:V_VLS
1976 (match_operand:<VEL> 3 "direct_broadcast_operand"))
1977 (match_operand:V_VLS 2 "vector_merge_operand")))]
1978 "TARGET_VECTOR"
1979 {
1980 /* Transform vmv.v.x/vfmv.v.f (avl = 1) into vmv.s.x since vmv.s.x/vfmv.s.f
1981 has better chances to do vsetvl fusion in vsetvl pass. */
1982 if (riscv_vector::splat_to_scalar_move_p (operands))
1983 {
1984 operands[1] = riscv_vector::gen_scalar_move_mask (<VM>mode);
1985 operands[3] = force_reg (<VEL>mode, operands[3]);
1986 }
1987 /* Handle vmv.s.x instruction (Wb1 mask) which has memory scalar. */
1988 else if (satisfies_constraint_Wdm (operands[3]))
1989 {
1990 if (satisfies_constraint_Wb1 (operands[1]))
1991 {
1992 /* Case 1: vmv.s.x (TA, x == memory) ==> vlse.v (TA) */
1993 if (satisfies_constraint_vu (operands[2]))
1994 operands[1] = CONSTM1_RTX (<VM>mode);
1995 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
1996 {
1997 /* Case 2: vmv.s.x (TU, x == memory) ==>
1998 vl = 0 or 1; + vlse.v (TU) in RV32 system */
1999 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2000 operands[1] = CONSTM1_RTX (<VM>mode);
2001 }
2002 else
2003 /* Case 3: load x (memory) to register. */
2004 operands[3] = force_reg (<VEL>mode, operands[3]);
2005 }
2006 }
2007 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)
2008 && (immediate_operand (operands[3], Pmode)
2009 || (CONST_POLY_INT_P (operands[3])
2010 && known_ge (rtx_to_poly_int64 (operands[3]), 0U)
2011 && known_le (rtx_to_poly_int64 (operands[3]), GET_MODE_SIZE (<MODE>mode)))))
2012 {
2013 rtx tmp = gen_reg_rtx (Pmode);
2014 poly_int64 value = rtx_to_poly_int64 (operands[3]);
2015 emit_move_insn (tmp, gen_int_mode (value, Pmode));
2016 operands[3] = gen_rtx_SIGN_EXTEND (<VEL>mode, tmp);
2017 }
2018 else
2019 operands[3] = force_reg (<VEL>mode, operands[3]);
2020 })
2022 (define_insn_and_split "*pred_broadcast<mode>"
2023 [(set (match_operand:V_VLSI 0 "register_operand" "=vr, vr, vd, vd, vr, vr, vr, vr")
2024 (if_then_else:V_VLSI
2025 (unspec:<VM>
2026 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
2027 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
2028 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
2029 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2030 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2031 (reg:SI VL_REGNUM)
2032 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2033 (vec_duplicate:V_VLSI
2034 (match_operand:<VEL> 3 "direct_broadcast_operand" " r, r,Wdm,Wdm,Wdm,Wdm, r, r"))
2035 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2036 "TARGET_VECTOR"
2037 "@
2038 vmv.v.x\t%0,%3
2039 vmv.v.x\t%0,%3
2040 vlse<sew>.v\t%0,%3,zero,%1.t
2041 vlse<sew>.v\t%0,%3,zero,%1.t
2042 vlse<sew>.v\t%0,%3,zero
2043 vlse<sew>.v\t%0,%3,zero
2044 vmv.s.x\t%0,%3
2045 vmv.s.x\t%0,%3"
2046 "(register_operand (operands[3], <VEL>mode)
2047 || CONST_POLY_INT_P (operands[3]))
2048 && GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)"
2049 [(set (match_dup 0)
2050 (if_then_else:V_VLSI (unspec:<VM> [(match_dup 1) (match_dup 4)
2051 (match_dup 5) (match_dup 6) (match_dup 7)
2052 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2053 (vec_duplicate:V_VLSI (match_dup 3))
2054 (match_dup 2)))]
2055 {
2056 gcc_assert (can_create_pseudo_p ());
2057 if (CONST_POLY_INT_P (operands[3]))
2058 {
2059 rtx tmp = gen_reg_rtx (<VEL>mode);
2060 emit_move_insn (tmp, operands[3]);
2061 operands[3] = tmp;
2062 }
2063 rtx m = assign_stack_local (<VEL>mode, GET_MODE_SIZE (<VEL>mode),
2064 GET_MODE_ALIGNMENT (<VEL>mode));
2065 m = validize_mem (m);
2066 emit_move_insn (m, operands[3]);
2067 m = gen_rtx_MEM (<VEL>mode, force_reg (Pmode, XEXP (m, 0)));
2068 operands[3] = m;
2070 /* For SEW = 64 in RV32 system, we expand vmv.s.x:
2071 andi a2,a2,1
2072 vsetvl zero,a2,e64
2073 vlse64.v */
2074 if (satisfies_constraint_Wb1 (operands[1]))
2075 {
2076 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2077 operands[1] = CONSTM1_RTX (<VM>mode);
2078 }
2079 }
2080 [(set_attr "type" "vimov,vimov,vlds,vlds,vlds,vlds,vimovxv,vimovxv")
2081 (set_attr "mode" "<MODE>")])
2083 (define_insn "*pred_broadcast<mode>"
2084 [(set (match_operand:V_VLSF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, vr, vr")
2085 (if_then_else:V_VLSF_ZVFHMIN
2086 (unspec:<VM>
2087 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
2088 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
2089 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
2090 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2091 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2092 (reg:SI VL_REGNUM)
2093 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2094 (vec_duplicate:V_VLSF_ZVFHMIN
2095 (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
2096 (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2097 "TARGET_VECTOR"
2098 "@
2099 vfmv.v.f\t%0,%3
2100 vfmv.v.f\t%0,%3
2101 vlse<sew>.v\t%0,%3,zero,%1.t
2102 vlse<sew>.v\t%0,%3,zero,%1.t
2103 vlse<sew>.v\t%0,%3,zero
2104 vlse<sew>.v\t%0,%3,zero
2105 vfmv.s.f\t%0,%3
2106 vfmv.s.f\t%0,%3"
2107 [(set_attr "type" "vfmov,vfmov,vlds,vlds,vlds,vlds,vfmovfv,vfmovfv")
2108 (set_attr "mode" "<MODE>")])
2110 (define_insn "*pred_broadcast<mode>_extended_scalar"
2111 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vr, vr, vr, vr")
2112 (if_then_else:V_VLSI_D
2113 (unspec:<VM>
2114 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,Wb1,Wb1")
2115 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
2116 (match_operand 5 "const_int_operand" " i, i, i, i")
2117 (match_operand 6 "const_int_operand" " i, i, i, i")
2118 (match_operand 7 "const_int_operand" " i, i, i, i")
2119 (reg:SI VL_REGNUM)
2120 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2121 (vec_duplicate:V_VLSI_D
2122 (sign_extend:<VEL>
2123 (match_operand:<VSUBEL> 3 "register_operand" " r, r, r, r")))
2124 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2125 "TARGET_VECTOR && !TARGET_64BIT"
2126 "@
2127 vmv.v.x\t%0,%3
2128 vmv.v.x\t%0,%3
2129 vmv.s.x\t%0,%3
2130 vmv.s.x\t%0,%3"
2131 [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
2132 (set_attr "mode" "<MODE>")])
2134 (define_insn "*pred_broadcast<mode>_zero"
2135 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2136 (if_then_else:V_VLS
2137 (unspec:<VM>
2138 [(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1, Wb1")
2139 (match_operand 4 "vector_length_operand" " rK, rK")
2140 (match_operand 5 "const_int_operand" " i, i")
2141 (match_operand 6 "const_int_operand" " i, i")
2142 (match_operand 7 "const_int_operand" " i, i")
2143 (reg:SI VL_REGNUM)
2144 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2145 (match_operand:V_VLS 3 "vector_const_0_operand" "Wc0, Wc0")
2146 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2147 "TARGET_VECTOR"
2148 "vmv.s.x\t%0,zero"
2149 [(set_attr "type" "vimovxv,vimovxv")
2150 (set_attr "mode" "<MODE>")])
2152 ;; Because (vec_duplicate imm) will be converted to (const_vector imm),
2153 ;; This pattern is used to handle this case.
2154 (define_insn "*pred_broadcast<mode>_imm"
2155 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2156 (if_then_else:V_VLS
2157 (unspec:<VM>
2158 [(match_operand:<VM> 1 "vector_all_trues_mask_operand" " Wc1, Wc1")
2159 (match_operand 4 "vector_length_operand" " rK, rK")
2160 (match_operand 5 "const_int_operand" " i, i")
2161 (match_operand 6 "const_int_operand" " i, i")
2162 (match_operand 7 "const_int_operand" " i, i")
2163 (reg:SI VL_REGNUM)
2164 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2165 (match_operand:V_VLS 3 "vector_const_int_or_double_0_operand" "viWc0, viWc0")
2166 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2167 "TARGET_VECTOR"
2168 "vmv.v.i\t%0,%v3"
2169 [(set_attr "type" "vimov,vimov")
2170 (set_attr "mode" "<MODE>")])
2172 ;; -------------------------------------------------------------------------------
2173 ;; ---- Predicated Strided loads/stores
2174 ;; -------------------------------------------------------------------------------
2175 ;; Includes:
2176 ;; - 7.5. Vector Strided Instructions
2177 ;; -------------------------------------------------------------------------------
2179 (define_insn "@pred_strided_load<mode>"
2180 [(set (match_operand:V 0 "register_operand" "=vr, vr, vd, vr, vr, vd")
2181 (if_then_else:V
2182 (unspec:<VM>
2183 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, vm")
2184 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2185 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2186 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2187 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2188 (reg:SI VL_REGNUM)
2189 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2190 (unspec:V
2191 [(match_operand:V 3 "memory_operand" " m, m, m, m, m, m")
2192 (match_operand 4 "<V:stride_predicate>" "<V:stride_load_constraint>")] UNSPEC_STRIDED)
2193 (match_operand:V 2 "vector_merge_operand" " 0, vu, vu, 0, vu, vu")))]
2194 "TARGET_VECTOR"
2195 "@
2196 vlse<sew>.v\t%0,%3,%z4%p1
2197 vlse<sew>.v\t%0,%3,%z4
2198 vlse<sew>.v\t%0,%3,%z4,%1.t
2199 vle<sew>.v\t%0,%3%p1
2200 vle<sew>.v\t%0,%3
2201 vle<sew>.v\t%0,%3,%1.t"
2202 [(set_attr "type" "vlds")
2203 (set_attr "mode" "<MODE>")])
2205 (define_insn "@pred_strided_store<mode>"
2206 [(set (match_operand:V 0 "memory_operand" "+m, m")
2207 (if_then_else:V
2208 (unspec:<VM>
2209 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
2210 (match_operand 4 "vector_length_operand" " rK, rK")
2211 (match_operand 5 "const_int_operand" " i, i")
2212 (reg:SI VL_REGNUM)
2213 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2214 (unspec:V
2215 [(match_operand 2 "<V:stride_predicate>" "<V:stride_store_constraint>")
2216 (match_operand:V 3 "register_operand" " vr, vr")] UNSPEC_STRIDED)
2217 (match_dup 0)))]
2218 "TARGET_VECTOR"
2219 "@
2220 vsse<sew>.v\t%3,%0,%z2%p1
2221 vse<sew>.v\t%3,%0%p1"
2222 [(set_attr "type" "vsts")
2223 (set_attr "mode" "<MODE>")
2224 (set (attr "avl_type_idx") (const_int 5))])
2226 ;; -------------------------------------------------------------------------------
2227 ;; ---- Predicated indexed loads/stores
2228 ;; -------------------------------------------------------------------------------
2229 ;; Includes:
2230 ;; - 7.6. Vector Indexed Instructions
2231 ;; -------------------------------------------------------------------------------
2233 ;; DEST eew is same as SOURCE eew, DEST register can overlap SOURCE.
2234 (define_insn "@pred_indexed_<order>load<mode>_same_eew"
2235 [(set (match_operand:VINDEXED 0 "register_operand" "=vd, vr,vd, vr")
2236 (if_then_else:VINDEXED
2237 (unspec:<VM>
2238 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
2239 (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
2240 (match_operand 6 "const_int_operand" " i, i, i, i")
2241 (match_operand 7 "const_int_operand" " i, i, i, i")
2242 (match_operand 8 "const_int_operand" " i, i, i, i")
2243 (reg:SI VL_REGNUM)
2244 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2245 (unspec:VINDEXED
2246 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ")
2247 (mem:BLK (scratch))
2248 (match_operand:<VINDEX> 4 "register_operand" " vr, vr,vr, vr")] ORDER)
2249 (match_operand:VINDEXED 2 "vector_merge_operand" " vu, vu, 0, 0")))]
2250 "TARGET_VECTOR"
2251 "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"
2252 [(set_attr "type" "vld<order>x")
2253 (set_attr "mode" "<MODE>")])
2255 ;; DEST eew is greater than SOURCE eew.
2256 (define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew"
2257 [(set (match_operand:VEEWEXT2 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
2258 (if_then_else:VEEWEXT2
2259 (unspec:<VM>
2260 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
2261 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2262 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
2263 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
2264 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
2265 (reg:SI VL_REGNUM)
2266 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2267 (unspec:VEEWEXT2
2268 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")
2269 (mem:BLK (scratch))
2270 (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")] ORDER)
2271 (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
2272 "TARGET_VECTOR"
2273 "vl<order>xei<double_trunc_sew>.v\t%0,(%z3),%4%p1"
2274 [(set_attr "type" "vld<order>x")
2275 (set_attr "mode" "<MODE>")
2276 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
2278 (define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew"
2279 [(set (match_operand:VEEWEXT4 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
2280 (if_then_else:VEEWEXT4
2281 (unspec:<VM>
2282 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
2283 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2284 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
2285 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
2286 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
2287 (reg:SI VL_REGNUM)
2288 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2289 (unspec:VEEWEXT4
2290 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")
2291 (mem:BLK (scratch))
2292 (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr")] ORDER)
2293 (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
2294 "TARGET_VECTOR"
2295 "vl<order>xei<quad_trunc_sew>.v\t%0,(%z3),%4%p1"
2296 [(set_attr "type" "vld<order>x")
2297 (set_attr "mode" "<MODE>")
2298 (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")])
2300 (define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew"
2301 [(set (match_operand:VEEWEXT8 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr")
2302 (if_then_else:VEEWEXT8
2303 (unspec:<VM>
2304 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1")
2305 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2306 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2307 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2308 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2309 (reg:SI VL_REGNUM)
2310 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2311 (unspec:VEEWEXT8
2312 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2313 (mem:BLK (scratch))
2314 (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" "W87,W87,W87,W87, vr, vr")] ORDER)
2315 (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))]
2316 "TARGET_VECTOR"
2317 "vl<order>xei<oct_trunc_sew>.v\t%0,(%z3),%4%p1"
2318 [(set_attr "type" "vld<order>x")
2319 (set_attr "mode" "<MODE>")
2320 (set_attr "group_overlap" "W87,W87,W87,W87,none,none")])
2322 ;; DEST eew is smaller than SOURCE eew.
2323 (define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew"
2324 [(set (match_operand:VEEWTRUNC2 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2325 (if_then_else:VEEWTRUNC2
2326 (unspec:<VM>
2327 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2328 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2329 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2330 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2331 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2332 (reg:SI VL_REGNUM)
2333 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2334 (unspec:VEEWTRUNC2
2335 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2336 (mem:BLK (scratch))
2337 (match_operand:<VINDEX_DOUBLE_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2338 (match_operand:VEEWTRUNC2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2339 "TARGET_VECTOR"
2340 "vl<order>xei<double_ext_sew>.v\t%0,(%z3),%4%p1"
2341 [(set_attr "type" "vld<order>x")
2342 (set_attr "mode" "<MODE>")])
2344 (define_insn "@pred_indexed_<order>load<mode>_x4_smaller_eew"
2345 [(set (match_operand:VEEWTRUNC4 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2346 (if_then_else:VEEWTRUNC4
2347 (unspec:<VM>
2348 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2349 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2350 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2351 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2352 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2353 (reg:SI VL_REGNUM)
2354 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2355 (unspec:VEEWTRUNC4
2356 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2357 (mem:BLK (scratch))
2358 (match_operand:<VINDEX_QUAD_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2359 (match_operand:VEEWTRUNC4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2360 "TARGET_VECTOR"
2361 "vl<order>xei<quad_ext_sew>.v\t%0,(%z3),%4%p1"
2362 [(set_attr "type" "vld<order>x")
2363 (set_attr "mode" "<MODE>")])
2365 (define_insn "@pred_indexed_<order>load<mode>_x8_smaller_eew"
2366 [(set (match_operand:VEEWTRUNC8 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2367 (if_then_else:VEEWTRUNC8
2368 (unspec:<VM>
2369 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2370 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2371 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2372 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2373 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2374 (reg:SI VL_REGNUM)
2375 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2376 (unspec:VEEWTRUNC8
2377 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2378 (mem:BLK (scratch))
2379 (match_operand:<VINDEX_OCT_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2380 (match_operand:VEEWTRUNC8 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2381 "TARGET_VECTOR"
2382 "vl<order>xei<oct_ext_sew>.v\t%0,(%z3),%4%p1"
2383 [(set_attr "type" "vld<order>x")
2384 (set_attr "mode" "<MODE>")])
2386 (define_insn "@pred_indexed_<order>store<RATIO64:mode><RATIO64I:mode>"
2387 [(set (mem:BLK (scratch))
2388 (unspec:BLK
2389 [(unspec:<VM>
2390 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2391 (match_operand 4 "vector_length_operand" " rK")
2392 (match_operand 5 "const_int_operand" " i")
2393 (reg:SI VL_REGNUM)
2394 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2395 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2396 (match_operand:RATIO64I 2 "register_operand" " vr")
2397 (match_operand:RATIO64 3 "register_operand" " vr")] ORDER))]
2398 "TARGET_VECTOR"
2399 "vs<order>xei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
2400 [(set_attr "type" "vst<order>x")
2401 (set_attr "mode" "<RATIO64:MODE>")])
2403 (define_insn "@pred_indexed_<order>store<RATIO32:mode><RATIO32I:mode>"
2404 [(set (mem:BLK (scratch))
2405 (unspec:BLK
2406 [(unspec:<VM>
2407 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2408 (match_operand 4 "vector_length_operand" " rK")
2409 (match_operand 5 "const_int_operand" " i")
2410 (reg:SI VL_REGNUM)
2411 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2412 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2413 (match_operand:RATIO32I 2 "register_operand" " vr")
2414 (match_operand:RATIO32 3 "register_operand" " vr")] ORDER))]
2415 "TARGET_VECTOR"
2416 "vs<order>xei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
2417 [(set_attr "type" "vst<order>x")
2418 (set_attr "mode" "<RATIO32:MODE>")])
2420 (define_insn "@pred_indexed_<order>store<RATIO16:mode><RATIO16I:mode>"
2421 [(set (mem:BLK (scratch))
2422 (unspec:BLK
2423 [(unspec:<VM>
2424 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2425 (match_operand 4 "vector_length_operand" " rK")
2426 (match_operand 5 "const_int_operand" " i")
2427 (reg:SI VL_REGNUM)
2428 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2429 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2430 (match_operand:RATIO16I 2 "register_operand" " vr")
2431 (match_operand:RATIO16 3 "register_operand" " vr")] ORDER))]
2432 "TARGET_VECTOR"
2433 "vs<order>xei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
2434 [(set_attr "type" "vst<order>x")
2435 (set_attr "mode" "<RATIO16:MODE>")])
2437 (define_insn "@pred_indexed_<order>store<RATIO8:mode><RATIO8I:mode>"
2438 [(set (mem:BLK (scratch))
2439 (unspec:BLK
2440 [(unspec:<VM>
2441 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2442 (match_operand 4 "vector_length_operand" " rK")
2443 (match_operand 5 "const_int_operand" " i")
2444 (reg:SI VL_REGNUM)
2445 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2446 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2447 (match_operand:RATIO8I 2 "register_operand" " vr")
2448 (match_operand:RATIO8 3 "register_operand" " vr")] ORDER))]
2449 "TARGET_VECTOR"
2450 "vs<order>xei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
2451 [(set_attr "type" "vst<order>x")
2452 (set_attr "mode" "<RATIO8:MODE>")])
2454 (define_insn "@pred_indexed_<order>store<RATIO4:mode><RATIO4I:mode>"
2455 [(set (mem:BLK (scratch))
2456 (unspec:BLK
2457 [(unspec:<VM>
2458 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2459 (match_operand 4 "vector_length_operand" " rK")
2460 (match_operand 5 "const_int_operand" " i")
2461 (reg:SI VL_REGNUM)
2462 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2463 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2464 (match_operand:RATIO4I 2 "register_operand" " vr")
2465 (match_operand:RATIO4 3 "register_operand" " vr")] ORDER))]
2466 "TARGET_VECTOR"
2467 "vs<order>xei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
2468 [(set_attr "type" "vst<order>x")
2469 (set_attr "mode" "<RATIO4:MODE>")])
2471 (define_insn "@pred_indexed_<order>store<RATIO2:mode><RATIO2I:mode>"
2472 [(set (mem:BLK (scratch))
2473 (unspec:BLK
2474 [(unspec:<VM>
2475 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2476 (match_operand 4 "vector_length_operand" " rK")
2477 (match_operand 5 "const_int_operand" " i")
2478 (reg:SI VL_REGNUM)
2479 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2480 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2481 (match_operand:RATIO2I 2 "register_operand" " vr")
2482 (match_operand:RATIO2 3 "register_operand" " vr")] ORDER))]
2483 "TARGET_VECTOR"
2484 "vs<order>xei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
2485 [(set_attr "type" "vst<order>x")
2486 (set_attr "mode" "<RATIO2:MODE>")])
2488 (define_insn "@pred_indexed_<order>store<RATIO1:mode><RATIO1:mode>"
2489 [(set (mem:BLK (scratch))
2490 (unspec:BLK
2491 [(unspec:<VM>
2492 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2493 (match_operand 4 "vector_length_operand" " rK")
2494 (match_operand 5 "const_int_operand" " i")
2495 (reg:SI VL_REGNUM)
2496 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2497 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2498 (match_operand:RATIO1 2 "register_operand" " vr")
2499 (match_operand:RATIO1 3 "register_operand" " vr")] ORDER))]
2500 "TARGET_VECTOR"
2501 "vs<order>xei<RATIO1:sew>.v\t%3,(%z1),%2%p0"
2502 [(set_attr "type" "vst<order>x")
2503 (set_attr "mode" "<RATIO1:MODE>")])
2505 ;; -------------------------------------------------------------------------------
2506 ;; ---- Predicated integer binary operations
2507 ;; -------------------------------------------------------------------------------
2508 ;; Includes:
2509 ;; - 11.1 Vector Single-Width Integer Add and Subtract
2510 ;; - 11.4 Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions
2511 ;; - 11.5 Vector Bitwise Logical Instructions
2512 ;; - 11.6 Vector Single-Width Bit Shift Instructions
2513 ;; - 11.9 Vector Integer Min/Max Instructions
2514 ;; - 11.10 Vector Single-Width Integer Multiply Instructions
2515 ;; - 11.11 Vector Integer Divide Instructions
2516 ;; -------------------------------------------------------------------------------
2518 (define_insn "@pred_<optab><mode>"
2519 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
2520 (if_then_else:V_VLSI
2521 (unspec:<VM>
2522 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
2523 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2524 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2525 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2526 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2527 (reg:SI VL_REGNUM)
2528 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2529 (any_int_binop:V_VLSI
2530 (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
2531 (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
2532 (match_operand:V_VLSI 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
2533 "TARGET_VECTOR"
2534 "@
2535 v<insn>.vv\t%0,%3,%4%p1
2536 v<insn>.vv\t%0,%3,%4%p1
2537 v<insn>.vv\t%0,%3,%4%p1
2538 v<insn>.vv\t%0,%3,%4%p1
2539 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2540 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2541 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2542 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2543 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2544 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2545 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2546 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
2547 [(set_attr "type" "<int_binop_insn_type>")
2548 (set_attr "mode" "<MODE>")])
2550 ;; vx instructions patterns.
2551 ;; Note: Unlike vv patterns, we should split them since they are variant.
2552 ;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the
2553 ;; scalar mode is inner mode of the RVV mode for other vx patterns.
2554 (define_insn "@pred_<optab><mode>_scalar"
2555 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr,vd,vd, vr, vr")
2556 (if_then_else:V_VLSI
2557 (unspec:<VM>
2558 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
2559 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK,rK,rK, rK, rK")
2560 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2561 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2562 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
2563 (reg:SI VL_REGNUM)
2564 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2565 (any_shift:V_VLSI
2566 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr,vr,vr, vr, vr")
2567 (match_operand 4 "pmode_reg_or_uimm5_operand" " r, r, r, r, K, K, K, K"))
2568 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0,vu, 0, vu, 0")))]
2569 "TARGET_VECTOR"
2570 "v<insn>.v%o4\t%0,%3,%4%p1"
2571 [(set_attr "type" "vshift")
2572 (set_attr "mode" "<MODE>")])
2574 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
2575 (define_insn "@pred_<optab><mode>_scalar"
2576 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2577 (if_then_else:V_VLSI_QHS
2578 (unspec:<VM>
2579 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2580 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2581 (match_operand 6 "const_int_operand" " i, i, i, i")
2582 (match_operand 7 "const_int_operand" " i, i, i, i")
2583 (match_operand 8 "const_int_operand" " i, i, i, i")
2584 (reg:SI VL_REGNUM)
2585 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2586 (any_commutative_binop:V_VLSI_QHS
2587 (vec_duplicate:V_VLSI_QHS
2588 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2589 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2590 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2591 "TARGET_VECTOR"
2592 "v<insn>.vx\t%0,%3,%z4%p1"
2593 [(set_attr "type" "<int_binop_insn_type>")
2594 (set_attr "mode" "<MODE>")])
2596 (define_insn "@pred_<optab><mode>_scalar"
2597 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2598 (if_then_else:V_VLSI_QHS
2599 (unspec:<VM>
2600 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2601 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2602 (match_operand 6 "const_int_operand" " i, i, i, i")
2603 (match_operand 7 "const_int_operand" " i, i, i, i")
2604 (match_operand 8 "const_int_operand" " i, i, i, i")
2605 (reg:SI VL_REGNUM)
2606 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2607 (any_non_commutative_binop:V_VLSI_QHS
2608 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr")
2609 (vec_duplicate:V_VLSI_QHS
2610 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2611 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2612 "TARGET_VECTOR"
2613 "v<insn>.vx\t%0,%3,%z4%p1"
2614 [(set_attr "type" "<int_binop_insn_type>")
2615 (set_attr "mode" "<MODE>")])
2617 (define_insn "@pred_sub<mode>_reverse_scalar"
2618 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2619 (if_then_else:V_VLSI_QHS
2620 (unspec:<VM>
2621 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2622 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2623 (match_operand 6 "const_int_operand" " i, i, i, i")
2624 (match_operand 7 "const_int_operand" " i, i, i, i")
2625 (match_operand 8 "const_int_operand" " i, i, i, i")
2626 (reg:SI VL_REGNUM)
2627 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2628 (minus:V_VLSI_QHS
2629 (vec_duplicate:V_VLSI_QHS
2630 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2631 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2632 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2633 "TARGET_VECTOR"
2634 "vrsub.vx\t%0,%3,%z4%p1"
2635 [(set_attr "type" "vialu")
2636 (set_attr "mode" "<MODE>")])
2638 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
2639 ;; we need to deal with SEW = 64 in RV32 system.
2640 (define_expand "@pred_<optab><mode>_scalar"
2641 [(set (match_operand:V_VLSI_D 0 "register_operand")
2642 (if_then_else:V_VLSI_D
2643 (unspec:<VM>
2644 [(match_operand:<VM> 1 "vector_mask_operand")
2645 (match_operand 5 "vector_length_operand")
2646 (match_operand 6 "const_int_operand")
2647 (match_operand 7 "const_int_operand")
2648 (match_operand 8 "const_int_operand")
2649 (reg:SI VL_REGNUM)
2650 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2651 (any_commutative_binop:V_VLSI_D
2652 (vec_duplicate:V_VLSI_D
2653 (match_operand:<VEL> 4 "reg_or_int_operand"))
2654 (match_operand:V_VLSI_D 3 "register_operand"))
2655 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2656 "TARGET_VECTOR"
2657 {
2658 if (riscv_vector::sew64_scalar_helper (
2659 operands,
2660 /* scalar op */&operands[4],
2661 /* vl */operands[5],
2662 <MODE>mode,
2663 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2664 [] (rtx *operands, rtx boardcast_scalar) {
2665 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2666 operands[2], operands[3], boardcast_scalar, operands[5],
2667 operands[6], operands[7], operands[8]));
2668 },
2669 (riscv_vector::avl_type) INTVAL (operands[8])))
2670 DONE;
2671 })
2673 (define_insn "*pred_<optab><mode>_scalar"
2674 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2675 (if_then_else:V_VLSI_D
2676 (unspec:<VM>
2677 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2678 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2679 (match_operand 6 "const_int_operand" " i, i, i, i")
2680 (match_operand 7 "const_int_operand" " i, i, i, i")
2681 (match_operand 8 "const_int_operand" " i, i, i, i")
2682 (reg:SI VL_REGNUM)
2683 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2684 (any_commutative_binop:V_VLSI_D
2685 (vec_duplicate:V_VLSI_D
2686 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2687 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2688 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2689 "TARGET_VECTOR"
2690 "v<insn>.vx\t%0,%3,%z4%p1"
2691 [(set_attr "type" "<int_binop_insn_type>")
2692 (set_attr "mode" "<MODE>")])
2694 (define_insn "*pred_<optab><mode>_extended_scalar"
2695 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2696 (if_then_else:V_VLSI_D
2697 (unspec:<VM>
2698 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2699 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2700 (match_operand 6 "const_int_operand" " i, i, i, i")
2701 (match_operand 7 "const_int_operand" " i, i, i, i")
2702 (match_operand 8 "const_int_operand" " i, i, i, i")
2703 (reg:SI VL_REGNUM)
2704 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2705 (any_commutative_binop:V_VLSI_D
2706 (vec_duplicate:V_VLSI_D
2707 (sign_extend:<VEL>
2708 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2709 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2710 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2711 "TARGET_VECTOR && !TARGET_64BIT"
2712 "v<insn>.vx\t%0,%3,%z4%p1"
2713 [(set_attr "type" "<int_binop_insn_type>")
2714 (set_attr "mode" "<MODE>")])
2716 (define_expand "@pred_<optab><mode>_scalar"
2717 [(set (match_operand:V_VLSI_D 0 "register_operand")
2718 (if_then_else:V_VLSI_D
2719 (unspec:<VM>
2720 [(match_operand:<VM> 1 "vector_mask_operand")
2721 (match_operand 5 "vector_length_operand")
2722 (match_operand 6 "const_int_operand")
2723 (match_operand 7 "const_int_operand")
2724 (match_operand 8 "const_int_operand")
2725 (reg:SI VL_REGNUM)
2726 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2727 (any_non_commutative_binop:V_VLSI_D
2728 (match_operand:V_VLSI_D 3 "register_operand")
2729 (vec_duplicate:V_VLSI_D
2730 (match_operand:<VEL> 4 "reg_or_int_operand")))
2731 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2732 "TARGET_VECTOR"
2733 {
2734 if (riscv_vector::sew64_scalar_helper (
2735 operands,
2736 /* scalar op */&operands[4],
2737 /* vl */operands[5],
2738 <MODE>mode,
2739 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2740 [] (rtx *operands, rtx boardcast_scalar) {
2741 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2742 operands[2], operands[3], boardcast_scalar, operands[5],
2743 operands[6], operands[7], operands[8]));
2744 },
2745 (riscv_vector::avl_type) INTVAL (operands[8])))
2746 DONE;
2747 })
2749 (define_insn "*pred_<optab><mode>_scalar"
2750 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2751 (if_then_else:V_VLSI_D
2752 (unspec:<VM>
2753 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2754 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2755 (match_operand 6 "const_int_operand" " i, i, i, i")
2756 (match_operand 7 "const_int_operand" " i, i, i, i")
2757 (match_operand 8 "const_int_operand" " i, i, i, i")
2758 (reg:SI VL_REGNUM)
2759 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2760 (any_non_commutative_binop:V_VLSI_D
2761 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2762 (vec_duplicate:V_VLSI_D
2763 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2764 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2765 "TARGET_VECTOR"
2766 "v<insn>.vx\t%0,%3,%z4%p1"
2767 [(set_attr "type" "<int_binop_insn_type>")
2768 (set_attr "mode" "<MODE>")])
2770 (define_insn "*pred_<optab><mode>_extended_scalar"
2771 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2772 (if_then_else:V_VLSI_D
2773 (unspec:<VM>
2774 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2775 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2776 (match_operand 6 "const_int_operand" " i, i, i, i")
2777 (match_operand 7 "const_int_operand" " i, i, i, i")
2778 (match_operand 8 "const_int_operand" " i, i, i, i")
2779 (reg:SI VL_REGNUM)
2780 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2781 (any_non_commutative_binop:V_VLSI_D
2782 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2783 (vec_duplicate:V_VLSI_D
2784 (sign_extend:<VEL>
2785 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
2786 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2787 "TARGET_VECTOR && !TARGET_64BIT"
2788 "v<insn>.vx\t%0,%3,%z4%p1"
2789 [(set_attr "type" "<int_binop_insn_type>")
2790 (set_attr "mode" "<MODE>")])
2792 (define_expand "@pred_sub<mode>_reverse_scalar"
2793 [(set (match_operand:V_VLSI_D 0 "register_operand")
2794 (if_then_else:V_VLSI_D
2795 (unspec:<VM>
2796 [(match_operand:<VM> 1 "vector_mask_operand")
2797 (match_operand 5 "vector_length_operand")
2798 (match_operand 6 "const_int_operand")
2799 (match_operand 7 "const_int_operand")
2800 (match_operand 8 "const_int_operand")
2801 (reg:SI VL_REGNUM)
2802 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2803 (minus:V_VLSI_D
2804 (vec_duplicate:V_VLSI_D
2805 (match_operand:<VEL> 4 "reg_or_int_operand"))
2806 (match_operand:V_VLSI_D 3 "register_operand"))
2807 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2808 "TARGET_VECTOR"
2809 {
2810 if (riscv_vector::sew64_scalar_helper (
2811 operands,
2812 /* scalar op */&operands[4],
2813 /* vl */operands[5],
2814 <MODE>mode,
2815 riscv_vector::neg_simm5_p (operands[4]),
2816 [] (rtx *operands, rtx boardcast_scalar) {
2817 emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
2818 operands[2], boardcast_scalar, operands[3], operands[5],
2819 operands[6], operands[7], operands[8]));
2820 },
2821 (riscv_vector::avl_type) INTVAL (operands[8])))
2822 DONE;
2823 })
2825 (define_insn "*pred_sub<mode>_reverse_scalar"
2826 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2827 (if_then_else:V_VLSI_D
2828 (unspec:<VM>
2829 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2830 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2831 (match_operand 6 "const_int_operand" " i, i, i, i")
2832 (match_operand 7 "const_int_operand" " i, i, i, i")
2833 (match_operand 8 "const_int_operand" " i, i, i, i")
2834 (reg:SI VL_REGNUM)
2835 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2836 (minus:V_VLSI_D
2837 (vec_duplicate:V_VLSI_D
2838 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2839 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2840 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2841 "TARGET_VECTOR"
2842 "vrsub.vx\t%0,%3,%z4%p1"
2843 [(set_attr "type" "vialu")
2844 (set_attr "mode" "<MODE>")])
2846 (define_insn "*pred_sub<mode>_extended_reverse_scalar"
2847 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2848 (if_then_else:V_VLSI_D
2849 (unspec:<VM>
2850 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2851 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2852 (match_operand 6 "const_int_operand" " i, i, i, i")
2853 (match_operand 7 "const_int_operand" " i, i, i, i")
2854 (match_operand 8 "const_int_operand" " i, i, i, i")
2855 (reg:SI VL_REGNUM)
2856 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2857 (minus:V_VLSI_D
2858 (vec_duplicate:V_VLSI_D
2859 (sign_extend:<VEL>
2860 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2861 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2862 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2863 "TARGET_VECTOR && !TARGET_64BIT"
2864 "vrsub.vx\t%0,%3,%z4%p1"
2865 [(set_attr "type" "vialu")
2866 (set_attr "mode" "<MODE>")])
2868 ;; Multiply High instructions.
2869 (define_insn "@pred_mulh<v_su><mode>"
2870 [(set (match_operand:VFULLI 0 "register_operand" "=vd,vd, vr, vr")
2871 (if_then_else:VFULLI
2872 (unspec:<VM>
2873 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2874 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2875 (match_operand 6 "const_int_operand" " i, i, i, i")
2876 (match_operand 7 "const_int_operand" " i, i, i, i")
2877 (match_operand 8 "const_int_operand" " i, i, i, i")
2878 (reg:SI VL_REGNUM)
2879 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2880 (unspec:VFULLI
2881 [(match_operand:VFULLI 3 "register_operand" "vr,vr, vr, vr")
2882 (match_operand:VFULLI 4 "register_operand" "vr,vr, vr, vr")] VMULH)
2883 (match_operand:VFULLI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2884 "TARGET_VECTOR"
2885 "vmulh<v_su>.vv\t%0,%3,%4%p1"
2886 [(set_attr "type" "vimul")
2887 (set_attr "mode" "<MODE>")])
2889 (define_insn "@pred_mulh<v_su><mode>_scalar"
2890 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2891 (if_then_else:VI_QHS
2892 (unspec:<VM>
2893 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2894 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2895 (match_operand 6 "const_int_operand" " i, i, i, i")
2896 (match_operand 7 "const_int_operand" " i, i, i, i")
2897 (match_operand 8 "const_int_operand" " i, i, i, i")
2898 (reg:SI VL_REGNUM)
2899 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2900 (unspec:VI_QHS
2901 [(vec_duplicate:VI_QHS
2902 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2903 (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2904 (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2905 "TARGET_VECTOR"
2906 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2907 [(set_attr "type" "vimul")
2908 (set_attr "mode" "<MODE>")])
2910 (define_expand "@pred_mulh<v_su><mode>_scalar"
2911 [(set (match_operand:VFULLI_D 0 "register_operand")
2912 (if_then_else:VFULLI_D
2913 (unspec:<VM>
2914 [(match_operand:<VM> 1 "vector_mask_operand")
2915 (match_operand 5 "vector_length_operand")
2916 (match_operand 6 "const_int_operand")
2917 (match_operand 7 "const_int_operand")
2918 (match_operand 8 "const_int_operand")
2919 (reg:SI VL_REGNUM)
2920 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2921 (unspec:VFULLI_D
2922 [(vec_duplicate:VFULLI_D
2923 (match_operand:<VEL> 4 "reg_or_int_operand"))
2924 (match_operand:VFULLI_D 3 "register_operand")] VMULH)
2925 (match_operand:VFULLI_D 2 "vector_merge_operand")))]
2926 "TARGET_VECTOR"
2927 {
2928 if (riscv_vector::sew64_scalar_helper (
2929 operands,
2930 /* scalar op */&operands[4],
2931 /* vl */operands[5],
2932 <MODE>mode,
2933 false,
2934 [] (rtx *operands, rtx boardcast_scalar) {
2935 emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
2936 operands[2], operands[3], boardcast_scalar, operands[5],
2937 operands[6], operands[7], operands[8]));
2938 },
2939 (riscv_vector::avl_type) INTVAL (operands[8])))
2940 DONE;
2941 })
2943 (define_insn "*pred_mulh<v_su><mode>_scalar"
2944 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
2945 (if_then_else:VFULLI_D
2946 (unspec:<VM>
2947 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2948 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2949 (match_operand 6 "const_int_operand" " i, i, i, i")
2950 (match_operand 7 "const_int_operand" " i, i, i, i")
2951 (match_operand 8 "const_int_operand" " i, i, i, i")
2952 (reg:SI VL_REGNUM)
2953 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2954 (unspec:VFULLI_D
2955 [(vec_duplicate:VFULLI_D
2956 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2957 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2958 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2959 "TARGET_VECTOR"
2960 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2961 [(set_attr "type" "vimul")
2962 (set_attr "mode" "<MODE>")])
2964 (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
2965 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
2966 (if_then_else:VFULLI_D
2967 (unspec:<VM>
2968 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2969 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2970 (match_operand 6 "const_int_operand" " i, i, i, i")
2971 (match_operand 7 "const_int_operand" " i, i, i, i")
2972 (match_operand 8 "const_int_operand" " i, i, i, i")
2973 (reg:SI VL_REGNUM)
2974 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2975 (unspec:VFULLI_D
2976 [(vec_duplicate:VFULLI_D
2977 (sign_extend:<VEL>
2978 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2979 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2980 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2981 "TARGET_VECTOR && !TARGET_64BIT"
2982 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2983 [(set_attr "type" "vimul")
2984 (set_attr "mode" "<MODE>")])
2986 ;; Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
2987 (define_insn "@pred_adc<mode>"
2988 [(set (match_operand:VI 0 "register_operand" "=vd,vd,vd,vd")
2989 (if_then_else:VI
2990 (unspec:<VM>
2991 [(match_operand 5 "vector_length_operand" "rK,rK,rK,rK")
2992 (match_operand 6 "const_int_operand" " i, i, i, i")
2993 (match_operand 7 "const_int_operand" " i, i, i, i")
2994 (reg:SI VL_REGNUM)
2995 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2996 (unspec:VI
2997 [(plus:VI
2998 (match_operand:VI 2 "register_operand" "vr,vr,vr,vr")
2999 (match_operand:VI 3 "vector_arith_operand" "vr,vr,vi,vi"))
3000 (match_operand:<VM> 4 "register_operand" "vm,vm,vm,vm")] UNSPEC_VADC)
3001 (match_operand:VI 1 "vector_merge_operand" "vu, 0,vu, 0")))]
3002 "TARGET_VECTOR"
3003 "vadc.v%o3m\t%0,%2,%v3,%4"
3004 [(set_attr "type" "vicalu")
3005 (set_attr "mode" "<MODE>")
3006 (set_attr "merge_op_idx" "1")
3007 (set_attr "vl_op_idx" "5")
3008 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3009 (set (attr "avl_type_idx") (const_int 7))])
3011 (define_insn "@pred_sbc<mode>"
3012 [(set (match_operand:VI 0 "register_operand" "=vd,vd")
3013 (if_then_else:VI
3014 (unspec:<VM>
3015 [(match_operand 5 "vector_length_operand" "rK,rK")
3016 (match_operand 6 "const_int_operand" " i, i")
3017 (match_operand 7 "const_int_operand" " i, i")
3018 (reg:SI VL_REGNUM)
3019 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3020 (unspec:VI
3021 [(minus:VI
3022 (match_operand:VI 2 "register_operand" "vr,vr")
3023 (match_operand:VI 3 "register_operand" "vr,vr"))
3024 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3025 (match_operand:VI 1 "vector_merge_operand" "vu, 0")))]
3026 "TARGET_VECTOR"
3027 "vsbc.vvm\t%0,%2,%3,%4"
3028 [(set_attr "type" "vicalu")
3029 (set_attr "mode" "<MODE>")
3030 (set_attr "merge_op_idx" "1")
3031 (set_attr "vl_op_idx" "5")
3032 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3033 (set (attr "avl_type_idx") (const_int 7))])
3035 (define_insn "@pred_adc<mode>_scalar"
3036 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3037 (if_then_else:VI_QHS
3038 (unspec:<VM>
3039 [(match_operand 5 "vector_length_operand" "rK,rK")
3040 (match_operand 6 "const_int_operand" " i, i")
3041 (match_operand 7 "const_int_operand" " i, i")
3042 (reg:SI VL_REGNUM)
3043 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3044 (unspec:VI_QHS
3045 [(plus:VI_QHS
3046 (vec_duplicate:VI_QHS
3047 (match_operand:<VEL> 3 "register_operand" " r, r"))
3048 (match_operand:VI_QHS 2 "register_operand" "vr,vr"))
3049 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3050 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3051 "TARGET_VECTOR"
3052 "vadc.vxm\t%0,%2,%3,%4"
3053 [(set_attr "type" "vicalu")
3054 (set_attr "mode" "<MODE>")
3055 (set_attr "merge_op_idx" "1")
3056 (set_attr "vl_op_idx" "5")
3057 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3058 (set (attr "avl_type_idx") (const_int 7))])
3060 (define_insn "@pred_sbc<mode>_scalar"
3061 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3062 (if_then_else:VI_QHS
3063 (unspec:<VM>
3064 [(match_operand 5 "vector_length_operand" "rK,rK")
3065 (match_operand 6 "const_int_operand" " i, i")
3066 (match_operand 7 "const_int_operand" " i, i")
3067 (reg:SI VL_REGNUM)
3068 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3069 (unspec:VI_QHS
3070 [(minus:VI_QHS
3071 (match_operand:VI_QHS 2 "register_operand" "vr,vr")
3072 (vec_duplicate:VI_QHS
3073 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3074 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3075 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3076 "TARGET_VECTOR"
3077 "vsbc.vxm\t%0,%2,%z3,%4"
3078 [(set_attr "type" "vicalu")
3079 (set_attr "mode" "<MODE>")
3080 (set_attr "merge_op_idx" "1")
3081 (set_attr "vl_op_idx" "5")
3082 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3083 (set (attr "avl_type_idx") (const_int 7))])
3085 (define_expand "@pred_adc<mode>_scalar"
3086 [(set (match_operand:VI_D 0 "register_operand")
3087 (if_then_else:VI_D
3088 (unspec:<VM>
3089 [(match_operand 5 "vector_length_operand")
3090 (match_operand 6 "const_int_operand")
3091 (match_operand 7 "const_int_operand")
3092 (reg:SI VL_REGNUM)
3093 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3094 (unspec:VI_D
3095 [(plus:VI_D
3096 (vec_duplicate:VI_D
3097 (match_operand:<VEL> 3 "reg_or_int_operand"))
3098 (match_operand:VI_D 2 "register_operand"))
3099 (match_operand:<VM> 4 "register_operand")] UNSPEC_VADC)
3100 (match_operand:VI_D 1 "vector_merge_operand")))]
3101 "TARGET_VECTOR"
3102 {
3103 if (riscv_vector::sew64_scalar_helper (
3104 operands,
3105 /* scalar op */&operands[3],
3106 /* vl */operands[5],
3107 <MODE>mode,
3108 riscv_vector::simm5_p (operands[3]),
3109 [] (rtx *operands, rtx boardcast_scalar) {
3110 emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
3111 operands[2], boardcast_scalar, operands[4], operands[5],
3112 operands[6], operands[7]));
3113 },
3114 (riscv_vector::avl_type) INTVAL (operands[7])))
3115 DONE;
3116 })
3118 (define_insn "*pred_adc<mode>_scalar"
3119 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3120 (if_then_else:VI_D
3121 (unspec:<VM>
3122 [(match_operand 5 "vector_length_operand" "rK,rK")
3123 (match_operand 6 "const_int_operand" " i, i")
3124 (match_operand 7 "const_int_operand" " i, i")
3125 (reg:SI VL_REGNUM)
3126 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3127 (unspec:VI_D
3128 [(plus:VI_D
3129 (vec_duplicate:VI_D
3130 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ"))
3131 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3132 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3133 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3134 "TARGET_VECTOR"
3135 "vadc.vxm\t%0,%2,%z3,%4"
3136 [(set_attr "type" "vicalu")
3137 (set_attr "mode" "<MODE>")
3138 (set_attr "merge_op_idx" "1")
3139 (set_attr "vl_op_idx" "5")
3140 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3141 (set (attr "avl_type_idx") (const_int 7))])
3143 (define_insn "*pred_adc<mode>_extended_scalar"
3144 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3145 (if_then_else:VI_D
3146 (unspec:<VM>
3147 [(match_operand 5 "vector_length_operand" "rK,rK")
3148 (match_operand 6 "const_int_operand" " i, i")
3149 (match_operand 7 "const_int_operand" " i, i")
3150 (reg:SI VL_REGNUM)
3151 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3152 (unspec:VI_D
3153 [(plus:VI_D
3154 (vec_duplicate:VI_D
3155 (sign_extend:<VEL>
3156 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ")))
3157 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3158 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3159 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3160 "TARGET_VECTOR && !TARGET_64BIT"
3161 "vadc.vxm\t%0,%2,%z3,%4"
3162 [(set_attr "type" "vicalu")
3163 (set_attr "mode" "<MODE>")
3164 (set_attr "merge_op_idx" "1")
3165 (set_attr "vl_op_idx" "5")
3166 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3167 (set (attr "avl_type_idx") (const_int 7))])
3169 (define_expand "@pred_sbc<mode>_scalar"
3170 [(set (match_operand:VI_D 0 "register_operand")
3171 (if_then_else:VI_D
3172 (unspec:<VM>
3173 [(match_operand 5 "vector_length_operand")
3174 (match_operand 6 "const_int_operand")
3175 (match_operand 7 "const_int_operand")
3176 (reg:SI VL_REGNUM)
3177 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3178 (unspec:VI_D
3179 [(minus:VI_D
3180 (match_operand:VI_D 2 "register_operand")
3181 (vec_duplicate:VI_D
3182 (match_operand:<VEL> 3 "reg_or_int_operand")))
3183 (match_operand:<VM> 4 "register_operand")] UNSPEC_VSBC)
3184 (match_operand:VI_D 1 "vector_merge_operand")))]
3185 "TARGET_VECTOR"
3186 {
3187 if (riscv_vector::sew64_scalar_helper (
3188 operands,
3189 /* scalar op */&operands[3],
3190 /* vl */operands[5],
3191 <MODE>mode,
3192 false,
3193 [] (rtx *operands, rtx boardcast_scalar) {
3194 emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
3195 operands[2], boardcast_scalar, operands[4], operands[5],
3196 operands[6], operands[7]));
3197 },
3198 (riscv_vector::avl_type) INTVAL (operands[7])))
3199 DONE;
3200 })
3202 (define_insn "*pred_sbc<mode>_scalar"
3203 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3204 (if_then_else:VI_D
3205 (unspec:<VM>
3206 [(match_operand 5 "vector_length_operand" "rK,rK")
3207 (match_operand 6 "const_int_operand" " i, i")
3208 (match_operand 7 "const_int_operand" " i, i")
3209 (reg:SI VL_REGNUM)
3210 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3211 (unspec:VI_D
3212 [(minus:VI_D
3213 (match_operand:VI_D 2 "register_operand" "vr,vr")
3214 (vec_duplicate:VI_D
3215 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3216 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3217 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3218 "TARGET_VECTOR"
3219 "vsbc.vxm\t%0,%2,%z3,%4"
3220 [(set_attr "type" "vicalu")
3221 (set_attr "mode" "<MODE>")
3222 (set_attr "merge_op_idx" "1")
3223 (set_attr "vl_op_idx" "5")
3224 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3225 (set (attr "avl_type_idx") (const_int 7))])
3227 (define_insn "*pred_sbc<mode>_extended_scalar"
3228 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3229 (if_then_else:VI_D
3230 (unspec:<VM>
3231 [(match_operand 5 "vector_length_operand" "rK,rK")
3232 (match_operand 6 "const_int_operand" " i, i")
3233 (match_operand 7 "const_int_operand" " i, i")
3234 (reg:SI VL_REGNUM)
3235 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3236 (unspec:VI_D
3237 [(minus:VI_D
3238 (match_operand:VI_D 2 "register_operand" "vr,vr")
3239 (vec_duplicate:VI_D
3240 (sign_extend:<VEL>
3241 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ"))))
3242 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3243 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3244 "TARGET_VECTOR && !TARGET_64BIT"
3245 "vsbc.vxm\t%0,%2,%z3,%4"
3246 [(set_attr "type" "vicalu")
3247 (set_attr "mode" "<MODE>")
3248 (set_attr "merge_op_idx" "1")
3249 (set_attr "vl_op_idx" "5")
3250 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3251 (set (attr "avl_type_idx") (const_int 7))])
3253 (define_insn "@pred_madc<mode>"
3254 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3255 (unspec:<VM>
3256 [(plus:VI
3257 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3258 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3259 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3260 (unspec:<VM>
3261 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3262 (match_operand 5 "const_int_operand" " i, i, i")
3263 (reg:SI VL_REGNUM)
3264 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3265 "TARGET_VECTOR"
3266 "vmadc.v%o2m\t%0,%1,%v2,%3"
3267 [(set_attr "type" "vicalu")
3268 (set_attr "mode" "<MODE>")
3269 (set_attr "vl_op_idx" "4")
3270 (set (attr "avl_type_idx") (const_int 5))
3271 (set_attr "spec_restriction" "thv,none,none")])
3273 (define_insn "@pred_msbc<mode>"
3274 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
3275 (unspec:<VM>
3276 [(minus:VI
3277 (match_operand:VI 1 "register_operand" " 0, vr, vr")
3278 (match_operand:VI 2 "register_operand" " vr, 0, vr"))
3279 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3280 (unspec:<VM>
3281 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3282 (match_operand 5 "const_int_operand" " i, i, i")
3283 (reg:SI VL_REGNUM)
3284 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3285 "TARGET_VECTOR"
3286 "vmsbc.vvm\t%0,%1,%2,%3"
3287 [(set_attr "type" "vicalu")
3288 (set_attr "mode" "<MODE>")
3289 (set_attr "vl_op_idx" "4")
3290 (set (attr "avl_type_idx") (const_int 5))
3291 (set_attr "spec_restriction" "thv,thv,none")])
3293 (define_insn "@pred_madc<mode>_scalar"
3294 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3295 (unspec:<VM>
3296 [(plus:VI_QHS
3297 (vec_duplicate:VI_QHS
3298 (match_operand:<VEL> 2 "register_operand" " r, r"))
3299 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3300 (match_operand:<VM> 3 "register_operand" " vm, vm")
3301 (unspec:<VM>
3302 [(match_operand 4 "vector_length_operand" " rK, rK")
3303 (match_operand 5 "const_int_operand" " i, i")
3304 (reg:SI VL_REGNUM)
3305 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3306 "TARGET_VECTOR"
3307 "vmadc.vxm\t%0,%1,%2,%3"
3308 [(set_attr "type" "vicalu")
3309 (set_attr "mode" "<MODE>")
3310 (set_attr "vl_op_idx" "4")
3311 (set (attr "avl_type_idx") (const_int 5))
3312 (set_attr "spec_restriction" "thv,none")])
3314 (define_insn "@pred_msbc<mode>_scalar"
3315 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3316 (unspec:<VM>
3317 [(minus:VI_QHS
3318 (vec_duplicate:VI_QHS
3319 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3320 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3321 (match_operand:<VM> 3 "register_operand" " vm, vm")
3322 (unspec:<VM>
3323 [(match_operand 4 "vector_length_operand" " rK, rK")
3324 (match_operand 5 "const_int_operand" " i, i")
3325 (reg:SI VL_REGNUM)
3326 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3327 "TARGET_VECTOR"
3328 "vmsbc.vxm\t%0,%1,%z2,%3"
3329 [(set_attr "type" "vicalu")
3330 (set_attr "mode" "<MODE>")
3331 (set_attr "vl_op_idx" "4")
3332 (set (attr "avl_type_idx") (const_int 5))
3333 (set_attr "spec_restriction" "thv,none")])
3335 (define_expand "@pred_madc<mode>_scalar"
3336 [(set (match_operand:<VM> 0 "register_operand")
3337 (unspec:<VM>
3338 [(plus:VI_D
3339 (vec_duplicate:VI_D
3340 (match_operand:<VEL> 2 "reg_or_int_operand"))
3341 (match_operand:VI_D 1 "register_operand"))
3342 (match_operand:<VM> 3 "register_operand")
3343 (unspec:<VM>
3344 [(match_operand 4 "vector_length_operand")
3345 (match_operand 5 "const_int_operand")
3346 (reg:SI VL_REGNUM)
3347 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3348 "TARGET_VECTOR"
3349 {
3350 if (riscv_vector::sew64_scalar_helper (
3351 operands,
3352 /* scalar op */&operands[2],
3353 /* vl */operands[4],
3354 <MODE>mode,
3355 riscv_vector::simm5_p (operands[2]),
3356 [] (rtx *operands, rtx boardcast_scalar) {
3357 emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
3358 boardcast_scalar, operands[3], operands[4], operands[5]));
3359 },
3360 (riscv_vector::avl_type) INTVAL (operands[5])))
3361 DONE;
3362 })
3364 (define_insn "*pred_madc<mode>_scalar"
3365 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3366 (unspec:<VM>
3367 [(plus:VI_D
3368 (vec_duplicate:VI_D
3369 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3370 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3371 (match_operand:<VM> 3 "register_operand" " vm, vm")
3372 (unspec:<VM>
3373 [(match_operand 4 "vector_length_operand" " rK, rK")
3374 (match_operand 5 "const_int_operand" " i, i")
3375 (reg:SI VL_REGNUM)
3376 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3377 "TARGET_VECTOR"
3378 "vmadc.vxm\t%0,%1,%z2,%3"
3379 [(set_attr "type" "vicalu")
3380 (set_attr "mode" "<MODE>")
3381 (set_attr "vl_op_idx" "4")
3382 (set (attr "avl_type_idx") (const_int 5))
3383 (set_attr "spec_restriction" "thv,none")])
3385 (define_insn "*pred_madc<mode>_extended_scalar"
3386 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3387 (unspec:<VM>
3388 [(plus:VI_D
3389 (vec_duplicate:VI_D
3390 (sign_extend:<VEL>
3391 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3392 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3393 (match_operand:<VM> 3 "register_operand" " vm, vm")
3394 (unspec:<VM>
3395 [(match_operand 4 "vector_length_operand" " rK, rK")
3396 (match_operand 5 "const_int_operand" " i, i")
3397 (reg:SI VL_REGNUM)
3398 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3399 "TARGET_VECTOR && !TARGET_64BIT"
3400 "vmadc.vxm\t%0,%1,%z2,%3"
3401 [(set_attr "type" "vicalu")
3402 (set_attr "mode" "<MODE>")
3403 (set_attr "vl_op_idx" "4")
3404 (set (attr "avl_type_idx") (const_int 5))
3405 (set_attr "spec_restriction" "thv,none")])
3407 (define_expand "@pred_msbc<mode>_scalar"
3408 [(set (match_operand:<VM> 0 "register_operand")
3409 (unspec:<VM>
3410 [(minus:VI_D
3411 (vec_duplicate:VI_D
3412 (match_operand:<VEL> 2 "reg_or_int_operand"))
3413 (match_operand:VI_D 1 "register_operand"))
3414 (match_operand:<VM> 3 "register_operand")
3415 (unspec:<VM>
3416 [(match_operand 4 "vector_length_operand")
3417 (match_operand 5 "const_int_operand")
3418 (reg:SI VL_REGNUM)
3419 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3420 "TARGET_VECTOR"
3421 {
3422 if (riscv_vector::sew64_scalar_helper (
3423 operands,
3424 /* scalar op */&operands[2],
3425 /* vl */operands[4],
3426 <MODE>mode,
3427 false,
3428 [] (rtx *operands, rtx boardcast_scalar) {
3429 emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
3430 boardcast_scalar, operands[3], operands[4], operands[5]));
3431 },
3432 (riscv_vector::avl_type) INTVAL (operands[5])))
3433 DONE;
3434 })
3436 (define_insn "*pred_msbc<mode>_scalar"
3437 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3438 (unspec:<VM>
3439 [(minus:VI_D
3440 (vec_duplicate:VI_D
3441 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3442 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3443 (match_operand:<VM> 3 "register_operand" " vm, vm")
3444 (unspec:<VM>
3445 [(match_operand 4 "vector_length_operand" " rK, rK")
3446 (match_operand 5 "const_int_operand" " i, i")
3447 (reg:SI VL_REGNUM)
3448 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3449 "TARGET_VECTOR"
3450 "vmsbc.vxm\t%0,%1,%z2,%3"
3451 [(set_attr "type" "vicalu")
3452 (set_attr "mode" "<MODE>")
3453 (set_attr "vl_op_idx" "4")
3454 (set (attr "avl_type_idx") (const_int 5))
3455 (set_attr "spec_restriction" "thv,none")])
3457 (define_insn "*pred_msbc<mode>_extended_scalar"
3458 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3459 (unspec:<VM>
3460 [(minus:VI_D
3461 (vec_duplicate:VI_D
3462 (sign_extend:<VEL>
3463 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3464 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3465 (match_operand:<VM> 3 "register_operand" " vm, vm")
3466 (unspec:<VM>
3467 [(match_operand 4 "vector_length_operand" " rK, rK")
3468 (match_operand 5 "const_int_operand" " i, i")
3469 (reg:SI VL_REGNUM)
3470 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3471 "TARGET_VECTOR && !TARGET_64BIT"
3472 "vmsbc.vxm\t%0,%1,%z2,%3"
3473 [(set_attr "type" "vicalu")
3474 (set_attr "mode" "<MODE>")
3475 (set_attr "vl_op_idx" "4")
3476 (set (attr "avl_type_idx") (const_int 5))
3477 (set_attr "spec_restriction" "thv,none")])
3479 (define_insn "@pred_madc<mode>_overflow"
3480 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3481 (unspec:<VM>
3482 [(plus:VI
3483 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3484 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3485 (unspec:<VM>
3486 [(match_operand 3 "vector_length_operand" " rK, rK, rK")
3487 (match_operand 4 "const_int_operand" " i, i, i")
3488 (reg:SI VL_REGNUM)
3489 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3490 "TARGET_VECTOR"
3491 "vmadc.v%o2\t%0,%1,%v2"
3492 [(set_attr "type" "vicalu")
3493 (set_attr "mode" "<MODE>")
3494 (set_attr "vl_op_idx" "3")
3495 (set (attr "avl_type_idx") (const_int 4))
3496 (set_attr "spec_restriction" "thv,none,none")])
3498 (define_insn "@pred_msbc<mode>_overflow"
3499 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
3500 (unspec:<VM>
3501 [(minus:VI
3502 (match_operand:VI 1 "register_operand" " 0, vr, vr, vr")
3503 (match_operand:VI 2 "register_operand" " vr, 0, vr, vi"))
3504 (unspec:<VM>
3505 [(match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
3506 (match_operand 4 "const_int_operand" " i, i, i, i")
3507 (reg:SI VL_REGNUM)
3508 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3509 "TARGET_VECTOR"
3510 "vmsbc.vv\t%0,%1,%2"
3511 [(set_attr "type" "vicalu")
3512 (set_attr "mode" "<MODE>")
3513 (set_attr "vl_op_idx" "3")
3514 (set (attr "avl_type_idx") (const_int 4))
3515 (set_attr "spec_restriction" "thv,thv,none,none")])
3517 (define_insn "@pred_madc<mode>_overflow_scalar"
3518 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3519 (unspec:<VM>
3520 [(plus:VI_QHS
3521 (vec_duplicate:VI_QHS
3522 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3523 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3524 (unspec:<VM>
3525 [(match_operand 3 "vector_length_operand" " rK, rK")
3526 (match_operand 4 "const_int_operand" " i, i")
3527 (reg:SI VL_REGNUM)
3528 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3529 "TARGET_VECTOR"
3530 "vmadc.vx\t%0,%1,%z2"
3531 [(set_attr "type" "vicalu")
3532 (set_attr "mode" "<MODE>")
3533 (set_attr "vl_op_idx" "3")
3534 (set (attr "avl_type_idx") (const_int 4))
3535 (set_attr "spec_restriction" "thv,none")])
3537 (define_insn "@pred_msbc<mode>_overflow_scalar"
3538 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3539 (unspec:<VM>
3540 [(minus:VI_QHS
3541 (vec_duplicate:VI_QHS
3542 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3543 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3544 (unspec:<VM>
3545 [(match_operand 3 "vector_length_operand" " rK, rK")
3546 (match_operand 4 "const_int_operand" " i, i")
3547 (reg:SI VL_REGNUM)
3548 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3549 "TARGET_VECTOR"
3550 "vmsbc.vx\t%0,%1,%z2"
3551 [(set_attr "type" "vicalu")
3552 (set_attr "mode" "<MODE>")
3553 (set_attr "vl_op_idx" "3")
3554 (set (attr "avl_type_idx") (const_int 4))
3555 (set_attr "spec_restriction" "thv,none")])
3557 (define_expand "@pred_madc<mode>_overflow_scalar"
3558 [(set (match_operand:<VM> 0 "register_operand")
3559 (unspec:<VM>
3560 [(plus:VI_D
3561 (vec_duplicate:VI_D
3562 (match_operand:<VEL> 2 "reg_or_int_operand"))
3563 (match_operand:VI_D 1 "register_operand"))
3564 (unspec:<VM>
3565 [(match_operand 3 "vector_length_operand")
3566 (match_operand 4 "const_int_operand")
3567 (reg:SI VL_REGNUM)
3568 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3569 "TARGET_VECTOR"
3570 {
3571 if (riscv_vector::sew64_scalar_helper (
3572 operands,
3573 /* scalar op */&operands[2],
3574 /* vl */operands[3],
3575 <MODE>mode,
3576 riscv_vector::simm5_p (operands[2]),
3577 [] (rtx *operands, rtx boardcast_scalar) {
3578 emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
3579 boardcast_scalar, operands[3], operands[4]));
3580 },
3581 (riscv_vector::avl_type) INTVAL (operands[4])))
3582 DONE;
3583 })
3585 (define_insn "*pred_madc<mode>_overflow_scalar"
3586 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3587 (unspec:<VM>
3588 [(plus:VI_D
3589 (vec_duplicate:VI_D
3590 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3591 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3592 (unspec:<VM>
3593 [(match_operand 3 "vector_length_operand" " rK, rK")
3594 (match_operand 4 "const_int_operand" " i, i")
3595 (reg:SI VL_REGNUM)
3596 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3597 "TARGET_VECTOR"
3598 "vmadc.vx\t%0,%1,%z2"
3599 [(set_attr "type" "vicalu")
3600 (set_attr "mode" "<MODE>")
3601 (set_attr "vl_op_idx" "3")
3602 (set (attr "avl_type_idx") (const_int 4))
3603 (set_attr "spec_restriction" "thv,none")])
3605 (define_insn "*pred_madc<mode>_overflow_extended_scalar"
3606 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3607 (unspec:<VM>
3608 [(plus:VI_D
3609 (vec_duplicate:VI_D
3610 (sign_extend:<VEL>
3611 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3612 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3613 (unspec:<VM>
3614 [(match_operand 3 "vector_length_operand" " rK, rK")
3615 (match_operand 4 "const_int_operand" " i, i")
3616 (reg:SI VL_REGNUM)
3617 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3618 "TARGET_VECTOR && !TARGET_64BIT"
3619 "vmadc.vx\t%0,%1,%z2"
3620 [(set_attr "type" "vicalu")
3621 (set_attr "mode" "<MODE>")
3622 (set_attr "vl_op_idx" "3")
3623 (set (attr "avl_type_idx") (const_int 4))
3624 (set_attr "spec_restriction" "thv,none")])
3626 (define_expand "@pred_msbc<mode>_overflow_scalar"
3627 [(set (match_operand:<VM> 0 "register_operand")
3628 (unspec:<VM>
3629 [(minus:VI_D
3630 (vec_duplicate:VI_D
3631 (match_operand:<VEL> 2 "reg_or_int_operand"))
3632 (match_operand:VI_D 1 "register_operand"))
3633 (unspec:<VM>
3634 [(match_operand 3 "vector_length_operand")
3635 (match_operand 4 "const_int_operand")
3636 (reg:SI VL_REGNUM)
3637 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3638 "TARGET_VECTOR"
3639 {
3640 if (riscv_vector::sew64_scalar_helper (
3641 operands,
3642 /* scalar op */&operands[2],
3643 /* vl */operands[3],
3644 <MODE>mode,
3645 false,
3646 [] (rtx *operands, rtx boardcast_scalar) {
3647 emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
3648 boardcast_scalar, operands[3], operands[4]));
3649 },
3650 (riscv_vector::avl_type) INTVAL (operands[4])))
3651 DONE;
3652 })
3654 (define_insn "*pred_msbc<mode>_overflow_scalar"
3655 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3656 (unspec:<VM>
3657 [(minus:VI_D
3658 (vec_duplicate:VI_D
3659 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3660 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3661 (unspec:<VM>
3662 [(match_operand 3 "vector_length_operand" " rK, rK")
3663 (match_operand 4 "const_int_operand" " i, i")
3664 (reg:SI VL_REGNUM)
3665 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3666 "TARGET_VECTOR"
3667 "vmsbc.vx\t%0,%1,%z2"
3668 [(set_attr "type" "vicalu")
3669 (set_attr "mode" "<MODE>")
3670 (set_attr "vl_op_idx" "3")
3671 (set (attr "avl_type_idx") (const_int 4))
3672 (set_attr "spec_restriction" "thv,none")])
3674 (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
3675 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3676 (unspec:<VM>
3677 [(minus:VI_D
3678 (vec_duplicate:VI_D
3679 (sign_extend:<VEL>
3680 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3681 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3682 (unspec:<VM>
3683 [(match_operand 3 "vector_length_operand" " rK, rK")
3684 (match_operand 4 "const_int_operand" " i, i")
3685 (reg:SI VL_REGNUM)
3686 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3687 "TARGET_VECTOR && !TARGET_64BIT"
3688 "vmsbc.vx\t%0,%1,%z2"
3689 [(set_attr "type" "vicalu")
3690 (set_attr "mode" "<MODE>")
3691 (set_attr "vl_op_idx" "3")
3692 (set (attr "avl_type_idx") (const_int 4))
3693 (set_attr "spec_restriction" "thv,none")])
3695 ;; -------------------------------------------------------------------------------
3696 ;; ---- Predicated integer unary operations
3697 ;; -------------------------------------------------------------------------------
3698 ;; Includes:
3699 ;; - vneg.v/vnot.v
3700 ;; -------------------------------------------------------------------------------
3702 (define_insn "@pred_<optab><mode>"
3703 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
3704 (if_then_else:V_VLSI
3705 (unspec:<VM>
3706 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3707 (match_operand 4 "vector_length_operand" "rK,rK, rK, rK")
3708 (match_operand 5 "const_int_operand" " i, i, i, i")
3709 (match_operand 6 "const_int_operand" " i, i, i, i")
3710 (match_operand 7 "const_int_operand" " i, i, i, i")
3711 (reg:SI VL_REGNUM)
3712 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3713 (any_int_unop:V_VLSI
3714 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr"))
3715 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3716 "TARGET_VECTOR"
3717 "v<insn>.v\t%0,%3%p1"
3718 [(set_attr "type" "vialu")
3719 (set_attr "mode" "<MODE>")
3720 (set_attr "vl_op_idx" "4")
3721 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3722 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3723 (set (attr "avl_type_idx") (const_int 7))])
3725 ;; -------------------------------------------------------------------------------
3726 ;; ---- Predicated integer widening binary operations
3727 ;; -------------------------------------------------------------------------------
3728 ;; Includes:
3729 ;; - 11.2 Vector Widening Integer Add/Subtract
3730 ;; - 11.3 Vector Integer Extension
3731 ;; - 11.12 Vector Widening Integer Multiply Instructions
3732 ;; -------------------------------------------------------------------------------
3734 ;; Vector Double-Widening Sign-extend and Zero-extend.
3735 (define_insn "@pred_<optab><mode>_vf2"
3736 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3737 (if_then_else:VWEXTI
3738 (unspec:<VM>
3739 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3740 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3741 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3742 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3743 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3744 (reg:SI VL_REGNUM)
3745 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3746 (any_extend:VWEXTI
3747 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
3748 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3749 "TARGET_VECTOR"
3750 "v<sz>ext.vf2\t%0,%3%p1"
3751 [(set_attr "type" "vext")
3752 (set_attr "mode" "<MODE>")
3753 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
3755 ;; Vector Quad-Widening Sign-extend and Zero-extend.
3756 (define_insn "@pred_<optab><mode>_vf4"
3757 [(set (match_operand:VQEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3758 (if_then_else:VQEXTI
3759 (unspec:<VM>
3760 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3761 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3762 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
3763 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
3764 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i")
3765 (reg:SI VL_REGNUM)
3766 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3767 (any_extend:VQEXTI
3768 (match_operand:<V_QUAD_TRUNC> 3 "register_operand" "W43,W43,W43,W43,W86,W86,W86,W86, vr, vr"))
3769 (match_operand:VQEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3770 "TARGET_VECTOR"
3771 "v<sz>ext.vf4\t%0,%3%p1"
3772 [(set_attr "type" "vext")
3773 (set_attr "mode" "<MODE>")
3774 (set_attr "group_overlap" "W43,W43,W43,W43,W86,W86,W86,W86,none,none")])
3776 ;; Vector Oct-Widening Sign-extend and Zero-extend.
3777 (define_insn "@pred_<optab><mode>_vf8"
3778 [(set (match_operand:VOEXTI 0 "register_operand" "=vd, vr, vd, vr, ?&vr, ?&vr")
3779 (if_then_else:VOEXTI
3780 (unspec:<VM>
3781 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3782 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3783 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
3784 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3785 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3786 (reg:SI VL_REGNUM)
3787 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3788 (any_extend:VOEXTI
3789 (match_operand:<V_OCT_TRUNC> 3 "register_operand" "W87,W87,W87,W87, vr, vr"))
3790 (match_operand:VOEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, 0")))]
3791 "TARGET_VECTOR"
3792 "v<sz>ext.vf8\t%0,%3%p1"
3793 [(set_attr "type" "vext")
3794 (set_attr "mode" "<MODE>")
3795 (set_attr "group_overlap" "W87,W87,W87,W87,none,none")])
3797 ;; Vector Widening Add/Subtract/Multiply.
3798 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
3799 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3800 (if_then_else:VWEXTI
3801 (unspec:<VM>
3802 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3803 (match_operand 5 "vector_length_operand" " rK, rK")
3804 (match_operand 6 "const_int_operand" " i, i")
3805 (match_operand 7 "const_int_operand" " i, i")
3806 (match_operand 8 "const_int_operand" " i, i")
3807 (reg:SI VL_REGNUM)
3808 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3809 (any_widen_binop:VWEXTI
3810 (any_extend:VWEXTI
3811 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3812 (any_extend:VWEXTI
3813 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3814 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3815 "TARGET_VECTOR"
3816 "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
3817 [(set_attr "type" "vi<widen_binop_insn_type>")
3818 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3820 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
3821 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3822 (if_then_else:VWEXTI
3823 (unspec:<VM>
3824 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3825 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3826 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3827 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3828 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3829 (reg:SI VL_REGNUM)
3830 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3831 (any_widen_binop:VWEXTI
3832 (any_extend:VWEXTI
3833 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
3834 (any_extend:VWEXTI
3835 (vec_duplicate:<V_DOUBLE_TRUNC>
3836 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ"))))
3837 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3838 "TARGET_VECTOR"
3839 "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
3840 [(set_attr "type" "vi<widen_binop_insn_type>")
3841 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3842 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
3844 (define_insn "@pred_single_widen_sub<any_extend:su><mode>"
3845 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
3846 (if_then_else:VWEXTI
3847 (unspec:<VM>
3848 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
3849 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3850 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3851 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3852 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3853 (reg:SI VL_REGNUM)
3854 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3855 (minus:VWEXTI
3856 (match_operand:VWEXTI 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr")
3857 (any_extend:VWEXTI
3858 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr")))
3859 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
3860 "TARGET_VECTOR"
3861 "vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
3862 [(set_attr "type" "viwalu")
3863 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3864 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
3866 (define_insn "@pred_single_widen_add<any_extend:su><mode>"
3867 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
3868 (if_then_else:VWEXTI
3869 (unspec:<VM>
3870 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
3871 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3872 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3873 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3874 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3875 (reg:SI VL_REGNUM)
3876 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3877 (plus:VWEXTI
3878 (any_extend:VWEXTI
3879 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr"))
3880 (match_operand:VWEXTI 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr"))
3881 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
3882 "TARGET_VECTOR"
3883 "vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
3884 [(set_attr "type" "viwalu")
3885 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3886 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
3888 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
3889 [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
3890 (if_then_else:VWEXTI
3891 (unspec:<VM>
3892 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3893 (match_operand 5 "vector_length_operand" " rK, rK")
3894 (match_operand 6 "const_int_operand" " i, i")
3895 (match_operand 7 "const_int_operand" " i, i")
3896 (match_operand 8 "const_int_operand" " i, i")
3897 (reg:SI VL_REGNUM)
3898 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3899 (plus_minus:VWEXTI
3900 (match_operand:VWEXTI 3 "register_operand" " vr, vr")
3901 (any_extend:VWEXTI
3902 (vec_duplicate:<V_DOUBLE_TRUNC>
3903 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3904 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3905 "TARGET_VECTOR"
3906 "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
3907 [(set_attr "type" "vi<widen_binop_insn_type>")
3908 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3910 (define_insn "@pred_widen_mulsu<mode>"
3911 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3912 (if_then_else:VWEXTI
3913 (unspec:<VM>
3914 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3915 (match_operand 5 "vector_length_operand" " rK, rK")
3916 (match_operand 6 "const_int_operand" " i, i")
3917 (match_operand 7 "const_int_operand" " i, i")
3918 (match_operand 8 "const_int_operand" " i, i")
3919 (reg:SI VL_REGNUM)
3920 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3921 (mult:VWEXTI
3922 (sign_extend:VWEXTI
3923 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3924 (zero_extend:VWEXTI
3925 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3926 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3927 "TARGET_VECTOR"
3928 "vwmulsu.vv\t%0,%3,%4%p1"
3929 [(set_attr "type" "viwmul")
3930 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3932 (define_insn "@pred_widen_mulsu<mode>_scalar"
3933 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3934 (if_then_else:VWEXTI
3935 (unspec:<VM>
3936 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3937 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3938 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3939 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3940 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3941 (reg:SI VL_REGNUM)
3942 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3943 (mult:VWEXTI
3944 (sign_extend:VWEXTI
3945 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
3946 (zero_extend:VWEXTI
3947 (vec_duplicate:<V_DOUBLE_TRUNC>
3948 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ"))))
3949 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3950 "TARGET_VECTOR"
3951 "vwmulsu.vx\t%0,%3,%z4%p1"
3952 [(set_attr "type" "viwmul")
3953 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3954 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
3956 ;; vwcvt<u>.x.x.v
3957 (define_insn "@pred_<optab><mode>"
3958 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
3959 (if_then_else:VWEXTI
3960 (unspec:<VM>
3961 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
3962 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
3963 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3964 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3965 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
3966 (reg:SI VL_REGNUM)
3967 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3968 (plus:VWEXTI
3969 (any_extend:VWEXTI
3970 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
3971 (vec_duplicate:VWEXTI
3972 (reg:<VEL> X0_REGNUM)))
3973 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
3974 "TARGET_VECTOR"
3975 "vwcvt<u>.x.x.v\t%0,%3%p1"
3976 [(set_attr "type" "viwalu")
3977 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3978 (set_attr "vl_op_idx" "4")
3979 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3980 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3981 (set (attr "avl_type_idx") (const_int 7))
3982 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
3984 ;; -------------------------------------------------------------------------------
3985 ;; ---- Predicated integer Narrowing operations
3986 ;; -------------------------------------------------------------------------------
3987 ;; Includes:
3988 ;; - 11.7 Vector Narrowing Integer Right Shift Instructions
3989 ;; -------------------------------------------------------------------------------
3991 ;; The destination EEW is smaller than the source EEW and the overlap is in the
3992 ;; lowest-numbered part of the source register group
3993 ;; e.g, when LMUL = 1, vnsrl.wi v0,v0,3 is legal but a destination of v1 is not.
3994 (define_insn "@pred_narrow_<optab><mode>"
3995 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
3996 (if_then_else:<V_DOUBLE_TRUNC>
3997 (unspec:<VM>
3998 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
3999 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
4000 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4001 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4002 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4003 (reg:SI VL_REGNUM)
4004 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4005 (truncate:<V_DOUBLE_TRUNC>
4006 (any_shiftrt:VWEXTI
4007 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4008 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")))
4009 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4010 "TARGET_VECTOR"
4011 "vn<insn>.w%o4\t%0,%3,%v4%p1"
4012 [(set_attr "type" "vnshift")
4013 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4014 (set_attr "spec_restriction" "none,none,thv,thv,none,thv,none,none,none,thv,none,none")])
4016 (define_insn "@pred_narrow_<optab><mode>_scalar"
4017 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4018 (if_then_else:<V_DOUBLE_TRUNC>
4019 (unspec:<VM>
4020 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4021 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4022 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4023 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4024 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4025 (reg:SI VL_REGNUM)
4026 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4027 (truncate:<V_DOUBLE_TRUNC>
4028 (any_shiftrt:VWEXTI
4029 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4030 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")))
4031 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4032 "TARGET_VECTOR"
4033 "vn<insn>.w%o4\t%0,%3,%4%p1"
4034 [(set_attr "type" "vnshift")
4035 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4036 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
4038 ;; vncvt.x.x.w
4039 (define_insn "@pred_trunc<mode>"
4040 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4041 (if_then_else:<V_DOUBLE_TRUNC>
4042 (unspec:<VM>
4043 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4044 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4045 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
4046 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4047 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4048 (reg:SI VL_REGNUM)
4049 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4050 (truncate:<V_DOUBLE_TRUNC>
4051 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
4052 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4053 "TARGET_VECTOR"
4054 "vncvt.x.x.w\t%0,%3%p1"
4055 [(set_attr "type" "vnshift")
4056 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4057 (set_attr "vl_op_idx" "4")
4058 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
4059 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4060 (set (attr "avl_type_idx") (const_int 7))
4061 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
4063 ;; -------------------------------------------------------------------------------
4064 ;; ---- Predicated fixed-point operations
4065 ;; -------------------------------------------------------------------------------
4066 ;; Includes:
4067 ;; - 12.1 Vector Single-Width Saturating Add and Subtract
4068 ;; - 12.2 Vector Single-Width Aaveraging Add and Subtract
4069 ;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation
4070 ;; - 12.4 Vector Single-Width Scaling Shift Instructions
4071 ;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions
4072 ;; -------------------------------------------------------------------------------
4074 ;; Saturating Add and Subtract
4075 (define_insn "@pred_<optab><mode>"
4076 [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr")
4077 (if_then_else:VI
4078 (unspec:<VM>
4079 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
4080 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4081 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
4082 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4083 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4084 (reg:SI VL_REGNUM)
4085 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4086 (any_sat_int_binop:VI
4087 (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
4088 (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
4089 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4090 "TARGET_VECTOR"
4091 "@
4092 v<insn>.vv\t%0,%3,%4%p1
4093 v<insn>.vv\t%0,%3,%4%p1
4094 v<insn>.vv\t%0,%3,%4%p1
4095 v<insn>.vv\t%0,%3,%4%p1
4096 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4097 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4098 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4099 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
4100 [(set_attr "type" "<int_binop_insn_type>")
4101 (set_attr "mode" "<MODE>")])
4103 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4104 (define_insn "@pred_<optab><mode>_scalar"
4105 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4106 (if_then_else:VI_QHS
4107 (unspec:<VM>
4108 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4109 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4110 (match_operand 6 "const_int_operand" " i, i, i, i")
4111 (match_operand 7 "const_int_operand" " i, i, i, i")
4112 (match_operand 8 "const_int_operand" " i, i, i, i")
4113 (reg:SI VL_REGNUM)
4114 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4115 (sat_int_plus_binop:VI_QHS
4116 (vec_duplicate:VI_QHS
4117 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4118 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr"))
4119 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4120 "TARGET_VECTOR"
4121 "v<insn>.vx\t%0,%3,%4%p1"
4122 [(set_attr "type" "<int_binop_insn_type>")
4123 (set_attr "mode" "<MODE>")])
4125 (define_insn "@pred_<optab><mode>_scalar"
4126 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4127 (if_then_else:VI_QHS
4128 (unspec:<VM>
4129 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4130 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4131 (match_operand 6 "const_int_operand" " i, i, i, i")
4132 (match_operand 7 "const_int_operand" " i, i, i, i")
4133 (match_operand 8 "const_int_operand" " i, i, i, i")
4134 (reg:SI VL_REGNUM)
4135 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4136 (sat_int_minus_binop:VI_QHS
4137 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4138 (vec_duplicate:VI_QHS
4139 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4140 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4141 "TARGET_VECTOR"
4142 "v<insn>.vx\t%0,%3,%4%p1"
4143 [(set_attr "type" "<int_binop_insn_type>")
4144 (set_attr "mode" "<MODE>")])
4146 (define_expand "@pred_<optab><mode>_scalar"
4147 [(set (match_operand:VI_D 0 "register_operand")
4148 (if_then_else:VI_D
4149 (unspec:<VM>
4150 [(match_operand:<VM> 1 "vector_mask_operand")
4151 (match_operand 5 "vector_length_operand")
4152 (match_operand 6 "const_int_operand")
4153 (match_operand 7 "const_int_operand")
4154 (match_operand 8 "const_int_operand")
4155 (reg:SI VL_REGNUM)
4156 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4157 (sat_int_plus_binop:VI_D
4158 (vec_duplicate:VI_D
4159 (match_operand:<VEL> 4 "reg_or_int_operand"))
4160 (match_operand:VI_D 3 "register_operand"))
4161 (match_operand:VI_D 2 "vector_merge_operand")))]
4162 "TARGET_VECTOR"
4163 {
4164 if (riscv_vector::sew64_scalar_helper (
4165 operands,
4166 /* scalar op */&operands[4],
4167 /* vl */operands[5],
4168 <MODE>mode,
4169 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4170 [] (rtx *operands, rtx boardcast_scalar) {
4171 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4172 operands[2], operands[3], boardcast_scalar, operands[5],
4173 operands[6], operands[7], operands[8]));
4174 },
4175 (riscv_vector::avl_type) INTVAL (operands[8])))
4176 DONE;
4177 })
4179 (define_insn "*pred_<optab><mode>_scalar"
4180 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4181 (if_then_else:VI_D
4182 (unspec:<VM>
4183 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4184 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4185 (match_operand 6 "const_int_operand" " i, i, i, i")
4186 (match_operand 7 "const_int_operand" " i, i, i, i")
4187 (match_operand 8 "const_int_operand" " i, i, i, i")
4188 (reg:SI VL_REGNUM)
4189 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4190 (sat_int_plus_binop:VI_D
4191 (vec_duplicate:VI_D
4192 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4193 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4194 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4195 "TARGET_VECTOR"
4196 "v<insn>.vx\t%0,%3,%4%p1"
4197 [(set_attr "type" "<int_binop_insn_type>")
4198 (set_attr "mode" "<MODE>")])
4200 (define_insn "*pred_<optab><mode>_extended_scalar"
4201 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4202 (if_then_else:VI_D
4203 (unspec:<VM>
4204 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4205 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4206 (match_operand 6 "const_int_operand" " i, i, i, i")
4207 (match_operand 7 "const_int_operand" " i, i, i, i")
4208 (match_operand 8 "const_int_operand" " i, i, i, i")
4209 (reg:SI VL_REGNUM)
4210 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4211 (sat_int_plus_binop:VI_D
4212 (vec_duplicate:VI_D
4213 (sign_extend:<VEL>
4214 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r")))
4215 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4216 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4217 "TARGET_VECTOR && !TARGET_64BIT"
4218 "v<insn>.vx\t%0,%3,%4%p1"
4219 [(set_attr "type" "<int_binop_insn_type>")
4220 (set_attr "mode" "<MODE>")])
4222 (define_expand "@pred_<optab><mode>_scalar"
4223 [(set (match_operand:VI_D 0 "register_operand")
4224 (if_then_else:VI_D
4225 (unspec:<VM>
4226 [(match_operand:<VM> 1 "vector_mask_operand")
4227 (match_operand 5 "vector_length_operand")
4228 (match_operand 6 "const_int_operand")
4229 (match_operand 7 "const_int_operand")
4230 (match_operand 8 "const_int_operand")
4231 (reg:SI VL_REGNUM)
4232 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4233 (sat_int_minus_binop:VI_D
4234 (match_operand:VI_D 3 "register_operand")
4235 (vec_duplicate:VI_D
4236 (match_operand:<VEL> 4 "reg_or_int_operand")))
4237 (match_operand:VI_D 2 "vector_merge_operand")))]
4238 "TARGET_VECTOR"
4239 {
4240 if (riscv_vector::sew64_scalar_helper (
4241 operands,
4242 /* scalar op */&operands[4],
4243 /* vl */operands[5],
4244 <MODE>mode,
4245 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4246 [] (rtx *operands, rtx boardcast_scalar) {
4247 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4248 operands[2], operands[3], boardcast_scalar, operands[5],
4249 operands[6], operands[7], operands[8]));
4250 },
4251 (riscv_vector::avl_type) INTVAL (operands[8])))
4252 DONE;
4253 })
4255 (define_insn "*pred_<optab><mode>_scalar"
4256 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4257 (if_then_else:VI_D
4258 (unspec:<VM>
4259 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4260 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4261 (match_operand 6 "const_int_operand" " i, i, i, i")
4262 (match_operand 7 "const_int_operand" " i, i, i, i")
4263 (match_operand 8 "const_int_operand" " i, i, i, i")
4264 (reg:SI VL_REGNUM)
4265 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4266 (sat_int_minus_binop:VI_D
4267 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4268 (vec_duplicate:VI_D
4269 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4270 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4271 "TARGET_VECTOR"
4272 "v<insn>.vx\t%0,%3,%4%p1"
4273 [(set_attr "type" "<int_binop_insn_type>")
4274 (set_attr "mode" "<MODE>")])
4276 (define_insn "*pred_<optab><mode>_extended_scalar"
4277 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4278 (if_then_else:VI_D
4279 (unspec:<VM>
4280 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4281 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4282 (match_operand 6 "const_int_operand" " i, i, i, i")
4283 (match_operand 7 "const_int_operand" " i, i, i, i")
4284 (match_operand 8 "const_int_operand" " i, i, i, i")
4285 (reg:SI VL_REGNUM)
4286 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4287 (sat_int_minus_binop:VI_D
4288 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4289 (vec_duplicate:VI_D
4290 (sign_extend:<VEL>
4291 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r"))))
4292 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4293 "TARGET_VECTOR && !TARGET_64BIT"
4294 "v<insn>.vx\t%0,%3,%4%p1"
4295 [(set_attr "type" "<int_binop_insn_type>")
4296 (set_attr "mode" "<MODE>")])
4298 (define_insn "@pred_<sat_op><mode>"
4299 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
4300 (if_then_else:V_VLSI
4301 (unspec:<VM>
4302 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4303 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4304 (match_operand 6 "const_int_operand" " i, i, i, i")
4305 (match_operand 7 "const_int_operand" " i, i, i, i")
4306 (match_operand 8 "const_int_operand" " i, i, i, i")
4307 (match_operand 9 "const_int_operand" " i, i, i, i")
4308 (reg:SI VL_REGNUM)
4309 (reg:SI VTYPE_REGNUM)
4310 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4311 (unspec:V_VLSI
4312 [(match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")
4313 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")] VSAT_OP)
4314 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4315 "TARGET_VECTOR"
4316 "v<sat_op>.vv\t%0,%3,%4%p1"
4317 [(set_attr "type" "<sat_insn_type>")
4318 (set_attr "mode" "<MODE>")])
4320 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4321 (define_insn "@pred_<sat_op><mode>_scalar"
4322 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr, vd, vr")
4323 (if_then_else:VI_QHS
4324 (unspec:<VM>
4325 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4326 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4327 (match_operand 6 "const_int_operand" " i, i, i, i")
4328 (match_operand 7 "const_int_operand" " i, i, i, i")
4329 (match_operand 8 "const_int_operand" " i, i, i, i")
4330 (match_operand 9 "const_int_operand" " i, i, i, i")
4331 (reg:SI VL_REGNUM)
4332 (reg:SI VTYPE_REGNUM)
4333 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4334 (unspec:VI_QHS
4335 [(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4336 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4337 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4338 "TARGET_VECTOR"
4339 "v<sat_op>.vx\t%0,%3,%z4%p1"
4340 [(set_attr "type" "<sat_insn_type>")
4341 (set_attr "mode" "<MODE>")])
4343 (define_insn "@pred_<sat_op><mode>_scalar"
4344 [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
4345 (if_then_else:VI
4346 (unspec:<VM>
4347 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4348 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4349 (match_operand 6 "const_int_operand" " i, i, i, i")
4350 (match_operand 7 "const_int_operand" " i, i, i, i")
4351 (match_operand 8 "const_int_operand" " i, i, i, i")
4352 (match_operand 9 "const_int_operand" " i, i, i, i")
4353 (reg:SI VL_REGNUM)
4354 (reg:SI VTYPE_REGNUM)
4355 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4356 (unspec:VI
4357 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4358 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
4359 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4360 "TARGET_VECTOR"
4361 "v<sat_op>.v%o4\t%0,%3,%4%p1"
4362 [(set_attr "type" "<sat_insn_type>")
4363 (set_attr "mode" "<MODE>")])
4365 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4366 ;; we need to deal with SEW = 64 in RV32 system.
4367 (define_expand "@pred_<sat_op><mode>_scalar"
4368 [(set (match_operand:VI_D 0 "register_operand")
4369 (if_then_else:VI_D
4370 (unspec:<VM>
4371 [(match_operand:<VM> 1 "vector_mask_operand")
4372 (match_operand 5 "vector_length_operand")
4373 (match_operand 6 "const_int_operand")
4374 (match_operand 7 "const_int_operand")
4375 (match_operand 8 "const_int_operand")
4376 (match_operand 9 "const_int_operand")
4377 (reg:SI VL_REGNUM)
4378 (reg:SI VTYPE_REGNUM)
4379 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4380 (unspec:VI_D
4381 [(match_operand:VI_D 3 "register_operand")
4382 (match_operand:<VEL> 4 "reg_or_int_operand")] VSAT_ARITH_OP)
4383 (match_operand:VI_D 2 "vector_merge_operand")))]
4384 "TARGET_VECTOR"
4385 {
4386 if (riscv_vector::sew64_scalar_helper (
4387 operands,
4388 /* scalar op */&operands[4],
4389 /* vl */operands[5],
4390 <MODE>mode,
4391 false,
4392 [] (rtx *operands, rtx boardcast_scalar) {
4393 emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
4394 operands[2], operands[3], boardcast_scalar, operands[5],
4395 operands[6], operands[7], operands[8], operands[9]));
4396 },
4397 (riscv_vector::avl_type) INTVAL (operands[8])))
4398 DONE;
4399 })
4401 (define_insn "*pred_<sat_op><mode>_scalar"
4402 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4403 (if_then_else:VI_D
4404 (unspec:<VM>
4405 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4406 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4407 (match_operand 6 "const_int_operand" " i, i, i, i")
4408 (match_operand 7 "const_int_operand" " i, i, i, i")
4409 (match_operand 8 "const_int_operand" " i, i, i, i")
4410 (match_operand 9 "const_int_operand" " i, i, i, i")
4411 (reg:SI VL_REGNUM)
4412 (reg:SI VTYPE_REGNUM)
4413 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4414 (unspec:VI_D
4415 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4416 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4417 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4418 "TARGET_VECTOR"
4419 "v<sat_op>.vx\t%0,%3,%z4%p1"
4420 [(set_attr "type" "<sat_insn_type>")
4421 (set_attr "mode" "<MODE>")])
4423 (define_insn "*pred_<sat_op><mode>_extended_scalar"
4424 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4425 (if_then_else:VI_D
4426 (unspec:<VM>
4427 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4428 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4429 (match_operand 6 "const_int_operand" " i, i, i, i")
4430 (match_operand 7 "const_int_operand" " i, i, i, i")
4431 (match_operand 8 "const_int_operand" " i, i, i, i")
4432 (match_operand 9 "const_int_operand" " i, i, i, i")
4433 (reg:SI VL_REGNUM)
4434 (reg:SI VTYPE_REGNUM)
4435 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4436 (unspec:VI_D
4437 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4438 (sign_extend:<VEL>
4439 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP)
4440 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4441 "TARGET_VECTOR && !TARGET_64BIT"
4442 "v<sat_op>.vx\t%0,%3,%z4%p1"
4443 [(set_attr "type" "<sat_insn_type>")
4444 (set_attr "mode" "<MODE>")])
4446 ;; CLIP
4447 (define_insn "@pred_narrow_clip<v_su><mode>"
4448 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
4449 (if_then_else:<V_DOUBLE_TRUNC>
4450 (unspec:<VM>
4451 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
4452 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
4453 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4454 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4455 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4456 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4457 (reg:SI VL_REGNUM)
4458 (reg:SI VTYPE_REGNUM)
4459 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4460 (unspec:<V_DOUBLE_TRUNC>
4461 [(match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4462 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")] VNCLIP)
4463 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4464 "TARGET_VECTOR"
4465 "vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
4466 [(set_attr "type" "vnclip")
4467 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4468 (set_attr "spec_restriction" "thv,thv,thv,thv,thv,thv,none,none,thv,thv,none,none")])
4470 (define_insn "@pred_narrow_clip<v_su><mode>_scalar"
4471 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4472 (if_then_else:<V_DOUBLE_TRUNC>
4473 (unspec:<VM>
4474 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4475 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4476 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4477 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4478 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4479 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
4480 (reg:SI VL_REGNUM)
4481 (reg:SI VTYPE_REGNUM)
4482 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4483 (unspec:<V_DOUBLE_TRUNC>
4484 [(match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4485 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")] VNCLIP)
4486 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4487 "TARGET_VECTOR"
4488 "vnclip<v_su>.w%o4\t%0,%3,%4%p1"
4489 [(set_attr "type" "vnclip")
4490 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4491 (set_attr "spec_restriction" "thv,thv,thv,thv,none,none")])
4493 ;; -------------------------------------------------------------------------------
4494 ;; ---- Predicated integer comparison operations
4495 ;; -------------------------------------------------------------------------------
4496 ;; Includes:
4497 ;; - 11.8 Vector Integer Comparision Instructions
4498 ;; -------------------------------------------------------------------------------
4500 (define_expand "@pred_cmp<mode>"
4501 [(set (match_operand:<VM> 0 "register_operand")
4502 (if_then_else:<VM>
4503 (unspec:<VM>
4504 [(match_operand:<VM> 1 "vector_mask_operand")
4505 (match_operand 6 "vector_length_operand")
4506 (match_operand 7 "const_int_operand")
4507 (match_operand 8 "const_int_operand")
4508 (reg:SI VL_REGNUM)
4509 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4510 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4511 [(match_operand:V_VLSI 4 "register_operand")
4512 (match_operand:V_VLSI 5 "vector_arith_operand")])
4513 (match_operand:<VM> 2 "vector_merge_operand")))]
4514 "TARGET_VECTOR"
4515 {})
4517 (define_insn "*pred_cmp<mode>_merge_tie_mask"
4518 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4519 (if_then_else:<VM>
4520 (unspec:<VM>
4521 [(match_operand:<VM> 1 "register_operand" " 0")
4522 (match_operand 5 "vector_length_operand" " rK")
4523 (match_operand 6 "const_int_operand" " i")
4524 (match_operand 7 "const_int_operand" " i")
4525 (reg:SI VL_REGNUM)
4526 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4527 (match_operator:<VM> 2 "comparison_except_ltge_operator"
4528 [(match_operand:V_VLSI 3 "register_operand" " vr")
4529 (match_operand:V_VLSI 4 "vector_arith_operand" "vrvi")])
4530 (match_dup 1)))]
4531 "TARGET_VECTOR"
4532 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4533 [(set_attr "type" "vicmp")
4534 (set_attr "mode" "<MODE>")
4535 (set_attr "merge_op_idx" "1")
4536 (set_attr "vl_op_idx" "5")
4537 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4538 (set (attr "avl_type_idx") (const_int 7))])
4540 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4541 (define_insn "*pred_cmp<mode>"
4542 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr")
4543 (if_then_else:<VM>
4544 (unspec:<VM>
4545 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4546 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4547 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4548 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4549 (reg:SI VL_REGNUM)
4550 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4551 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4552 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr")
4553 (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi, vr, vr, vi, vi")])
4554 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4555 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4556 "vms%B3.v%o5\t%0,%4,%v5%p1"
4557 [(set_attr "type" "vicmp")
4558 (set_attr "mode" "<MODE>")
4559 (set_attr "spec_restriction" "thv,thv,thv,thv,rvv,rvv,rvv,rvv")])
4561 ;; We use early-clobber for source LMUL > dest LMUL.
4562 (define_insn "*pred_cmp<mode>_narrow"
4563 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4564 (if_then_else:<VM>
4565 (unspec:<VM>
4566 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4567 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4568 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4569 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4570 (reg:SI VL_REGNUM)
4571 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4572 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4573 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4574 (match_operand:V_VLSI 5 "vector_arith_operand" " vrvi, vrvi, 0, 0, vrvi, 0, 0, vrvi, vrvi")])
4575 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4576 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4577 "vms%B3.v%o5\t%0,%4,%v5%p1"
4578 [(set_attr "type" "vicmp")
4579 (set_attr "mode" "<MODE>")
4580 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
4582 (define_expand "@pred_ltge<mode>"
4583 [(set (match_operand:<VM> 0 "register_operand")
4584 (if_then_else:<VM>
4585 (unspec:<VM>
4586 [(match_operand:<VM> 1 "vector_mask_operand")
4587 (match_operand 6 "vector_length_operand")
4588 (match_operand 7 "const_int_operand")
4589 (match_operand 8 "const_int_operand")
4590 (reg:SI VL_REGNUM)
4591 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4592 (match_operator:<VM> 3 "ltge_operator"
4593 [(match_operand:V_VLSI 4 "register_operand")
4594 (match_operand:V_VLSI 5 "vector_neg_arith_operand")])
4595 (match_operand:<VM> 2 "vector_merge_operand")))]
4596 "TARGET_VECTOR"
4597 {})
4599 (define_insn "*pred_ltge<mode>_merge_tie_mask"
4600 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4601 (if_then_else:<VM>
4602 (unspec:<VM>
4603 [(match_operand:<VM> 1 "register_operand" " 0")
4604 (match_operand 5 "vector_length_operand" " rK")
4605 (match_operand 6 "const_int_operand" " i")
4606 (match_operand 7 "const_int_operand" " i")
4607 (reg:SI VL_REGNUM)
4608 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4609 (match_operator:<VM> 2 "ltge_operator"
4610 [(match_operand:V_VLSI 3 "register_operand" " vr")
4611 (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")])
4612 (match_dup 1)))]
4613 "TARGET_VECTOR"
4614 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4615 [(set_attr "type" "vicmp")
4616 (set_attr "mode" "<MODE>")
4617 (set_attr "merge_op_idx" "1")
4618 (set_attr "vl_op_idx" "5")
4619 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4620 (set (attr "avl_type_idx") (const_int 7))])
4622 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4623 (define_insn "*pred_ltge<mode>"
4624 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr")
4625 (if_then_else:<VM>
4626 (unspec:<VM>
4627 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4628 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4629 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4630 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4631 (reg:SI VL_REGNUM)
4632 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4633 (match_operator:<VM> 3 "ltge_operator"
4634 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr")
4635 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj, vr, vr, vj, vj")])
4636 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4637 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4638 "vms%B3.v%o5\t%0,%4,%v5%p1"
4639 [(set_attr "type" "vicmp")
4640 (set_attr "mode" "<MODE>")
4641 (set_attr "spec_restriction" "thv,thv,thv,thv,rvv,rvv,rvv,rvv")])
4643 ;; We use early-clobber for source LMUL > dest LMUL.
4644 (define_insn "*pred_ltge<mode>_narrow"
4645 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4646 (if_then_else:<VM>
4647 (unspec:<VM>
4648 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4649 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4650 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4651 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4652 (reg:SI VL_REGNUM)
4653 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4654 (match_operator:<VM> 3 "ltge_operator"
4655 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4656 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vrvj, vrvj, 0, 0, vrvj, 0, 0, vrvj, vrvj")])
4657 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4658 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4659 "vms%B3.v%o5\t%0,%4,%v5%p1"
4660 [(set_attr "type" "vicmp")
4661 (set_attr "mode" "<MODE>")
4662 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
4664 (define_expand "@pred_cmp<mode>_scalar"
4665 [(set (match_operand:<VM> 0 "register_operand")
4666 (if_then_else:<VM>
4667 (unspec:<VM>
4668 [(match_operand:<VM> 1 "vector_mask_operand")
4669 (match_operand 6 "vector_length_operand")
4670 (match_operand 7 "const_int_operand")
4671 (match_operand 8 "const_int_operand")
4672 (reg:SI VL_REGNUM)
4673 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4674 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4675 [(match_operand:V_VLSI_QHS 4 "register_operand")
4676 (vec_duplicate:V_VLSI_QHS
4677 (match_operand:<VEL> 5 "register_operand"))])
4678 (match_operand:<VM> 2 "vector_merge_operand")))]
4679 "TARGET_VECTOR"
4680 {})
4682 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4683 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4684 (if_then_else:<VM>
4685 (unspec:<VM>
4686 [(match_operand:<VM> 1 "register_operand" " 0")
4687 (match_operand 5 "vector_length_operand" " rK")
4688 (match_operand 6 "const_int_operand" " i")
4689 (match_operand 7 "const_int_operand" " i")
4690 (reg:SI VL_REGNUM)
4691 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4692 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4693 [(match_operand:V_VLSI_QHS 3 "register_operand" " vr")
4694 (vec_duplicate:V_VLSI_QHS
4695 (match_operand:<VEL> 4 "register_operand" " r"))])
4696 (match_dup 1)))]
4697 "TARGET_VECTOR"
4698 "vms%B2.vx\t%0,%3,%4,v0.t"
4699 [(set_attr "type" "vicmp")
4700 (set_attr "mode" "<MODE>")
4701 (set_attr "merge_op_idx" "1")
4702 (set_attr "vl_op_idx" "5")
4703 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4704 (set (attr "avl_type_idx") (const_int 7))])
4706 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4707 (define_insn "*pred_cmp<mode>_scalar"
4708 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
4709 (if_then_else:<VM>
4710 (unspec:<VM>
4711 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4712 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4713 (match_operand 7 "const_int_operand" " i, i, i, i")
4714 (match_operand 8 "const_int_operand" " i, i, i, i")
4715 (reg:SI VL_REGNUM)
4716 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4717 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4718 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")
4719 (vec_duplicate:V_VLSI_QHS
4720 (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
4721 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4722 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4723 "vms%B3.vx\t%0,%4,%5%p1"
4724 [(set_attr "type" "vicmp")
4725 (set_attr "mode" "<MODE>")
4726 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
4728 ;; We use early-clobber for source LMUL > dest LMUL.
4729 (define_insn "*pred_cmp<mode>_scalar_narrow"
4730 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4731 (if_then_else:<VM>
4732 (unspec:<VM>
4733 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4734 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4735 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4736 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4737 (reg:SI VL_REGNUM)
4738 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4739 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4740 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")
4741 (vec_duplicate:V_VLSI_QHS
4742 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4743 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4744 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4745 "vms%B3.vx\t%0,%4,%5%p1"
4746 [(set_attr "type" "vicmp")
4747 (set_attr "mode" "<MODE>")
4748 (set_attr "spec_restriction" "none,thv,thv,none,none")])
4750 (define_expand "@pred_eqne<mode>_scalar"
4751 [(set (match_operand:<VM> 0 "register_operand")
4752 (if_then_else:<VM>
4753 (unspec:<VM>
4754 [(match_operand:<VM> 1 "vector_mask_operand")
4755 (match_operand 6 "vector_length_operand")
4756 (match_operand 7 "const_int_operand")
4757 (match_operand 8 "const_int_operand")
4758 (reg:SI VL_REGNUM)
4759 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4760 (match_operator:<VM> 3 "equality_operator"
4761 [(vec_duplicate:V_VLSI_QHS
4762 (match_operand:<VEL> 5 "register_operand"))
4763 (match_operand:V_VLSI_QHS 4 "register_operand")])
4764 (match_operand:<VM> 2 "vector_merge_operand")))]
4765 "TARGET_VECTOR"
4766 {})
4768 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
4769 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4770 (if_then_else:<VM>
4771 (unspec:<VM>
4772 [(match_operand:<VM> 1 "register_operand" " 0")
4773 (match_operand 5 "vector_length_operand" " rK")
4774 (match_operand 6 "const_int_operand" " i")
4775 (match_operand 7 "const_int_operand" " i")
4776 (reg:SI VL_REGNUM)
4777 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4778 (match_operator:<VM> 2 "equality_operator"
4779 [(vec_duplicate:V_VLSI_QHS
4780 (match_operand:<VEL> 4 "register_operand" " r"))
4781 (match_operand:V_VLSI_QHS 3 "register_operand" " vr")])
4782 (match_dup 1)))]
4783 "TARGET_VECTOR"
4784 "vms%B2.vx\t%0,%3,%4,v0.t"
4785 [(set_attr "type" "vicmp")
4786 (set_attr "mode" "<MODE>")
4787 (set_attr "merge_op_idx" "1")
4788 (set_attr "vl_op_idx" "5")
4789 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4790 (set (attr "avl_type_idx") (const_int 7))])
4792 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4793 (define_insn "*pred_eqne<mode>_scalar"
4794 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
4795 (if_then_else:<VM>
4796 (unspec:<VM>
4797 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4798 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4799 (match_operand 7 "const_int_operand" " i, i, i, i")
4800 (match_operand 8 "const_int_operand" " i, i, i, i")
4801 (reg:SI VL_REGNUM)
4802 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4803 (match_operator:<VM> 3 "equality_operator"
4804 [(vec_duplicate:V_VLSI_QHS
4805 (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))
4806 (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")])
4807 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4808 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4809 "vms%B3.vx\t%0,%4,%5%p1"
4810 [(set_attr "type" "vicmp")
4811 (set_attr "mode" "<MODE>")
4812 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
4814 ;; We use early-clobber for source LMUL > dest LMUL.
4815 (define_insn "*pred_eqne<mode>_scalar_narrow"
4816 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4817 (if_then_else:<VM>
4818 (unspec:<VM>
4819 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4820 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4821 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4822 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4823 (reg:SI VL_REGNUM)
4824 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4825 (match_operator:<VM> 3 "equality_operator"
4826 [(vec_duplicate:V_VLSI_QHS
4827 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
4828 (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")])
4829 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4830 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4831 "vms%B3.vx\t%0,%4,%5%p1"
4832 [(set_attr "type" "vicmp")
4833 (set_attr "mode" "<MODE>")
4834 (set_attr "spec_restriction" "none,thv,thv,none,none")])
4836 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4837 ;; we need to deal with SEW = 64 in RV32 system.
4838 (define_expand "@pred_cmp<mode>_scalar"
4839 [(set (match_operand:<VM> 0 "register_operand")
4840 (if_then_else:<VM>
4841 (unspec:<VM>
4842 [(match_operand:<VM> 1 "vector_mask_operand")
4843 (match_operand 6 "vector_length_operand")
4844 (match_operand 7 "const_int_operand")
4845 (match_operand 8 "const_int_operand")
4846 (reg:SI VL_REGNUM)
4847 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4848 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4849 [(match_operand:V_VLSI_D 4 "register_operand")
4850 (vec_duplicate:V_VLSI_D
4851 (match_operand:<VEL> 5 "reg_or_int_operand"))])
4852 (match_operand:<VM> 2 "vector_merge_operand")))]
4853 "TARGET_VECTOR"
4854 {
4855 enum rtx_code code = GET_CODE (operands[3]);
4856 if (riscv_vector::sew64_scalar_helper (
4857 operands,
4858 /* scalar op */&operands[5],
4859 /* vl */operands[6],
4860 <MODE>mode,
4861 riscv_vector::has_vi_variant_p (code, operands[5]),
4862 code == LT || code == LTU ?
4863 [] (rtx *operands, rtx boardcast_scalar) {
4864 emit_insn (gen_pred_ltge<mode> (operands[0], operands[1],
4865 operands[2], operands[3], operands[4], boardcast_scalar,
4866 operands[6], operands[7], operands[8]));
4867 }
4868 :
4869 [] (rtx *operands, rtx boardcast_scalar) {
4870 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4871 operands[2], operands[3], operands[4], boardcast_scalar,
4872 operands[6], operands[7], operands[8]));
4873 },
4874 (riscv_vector::avl_type) INTVAL (operands[8])))
4875 DONE;
4876 })
4878 (define_expand "@pred_eqne<mode>_scalar"
4879 [(set (match_operand:<VM> 0 "register_operand")
4880 (if_then_else:<VM>
4881 (unspec:<VM>
4882 [(match_operand:<VM> 1 "vector_mask_operand")
4883 (match_operand 6 "vector_length_operand")
4884 (match_operand 7 "const_int_operand")
4885 (match_operand 8 "const_int_operand")
4886 (reg:SI VL_REGNUM)
4887 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4888 (match_operator:<VM> 3 "equality_operator"
4889 [(vec_duplicate:V_VLSI_D
4890 (match_operand:<VEL> 5 "reg_or_int_operand"))
4891 (match_operand:V_VLSI_D 4 "register_operand")])
4892 (match_operand:<VM> 2 "vector_merge_operand")))]
4893 "TARGET_VECTOR"
4894 {
4895 enum rtx_code code = GET_CODE (operands[3]);
4896 if (riscv_vector::sew64_scalar_helper (
4897 operands,
4898 /* scalar op */&operands[5],
4899 /* vl */operands[6],
4900 <MODE>mode,
4901 riscv_vector::has_vi_variant_p (code, operands[5]),
4902 [] (rtx *operands, rtx boardcast_scalar) {
4903 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4904 operands[2], operands[3], operands[4], boardcast_scalar,
4905 operands[6], operands[7], operands[8]));
4906 },
4907 (riscv_vector::avl_type) INTVAL (operands[8])))
4908 DONE;
4909 })
4911 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4912 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4913 (if_then_else:<VM>
4914 (unspec:<VM>
4915 [(match_operand:<VM> 1 "register_operand" " 0")
4916 (match_operand 5 "vector_length_operand" " rK")
4917 (match_operand 6 "const_int_operand" " i")
4918 (match_operand 7 "const_int_operand" " i")
4919 (reg:SI VL_REGNUM)
4920 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4921 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4922 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
4923 (vec_duplicate:V_VLSI_D
4924 (match_operand:<VEL> 4 "register_operand" " r"))])
4925 (match_dup 1)))]
4926 "TARGET_VECTOR"
4927 "vms%B2.vx\t%0,%3,%4,v0.t"
4928 [(set_attr "type" "vicmp")
4929 (set_attr "mode" "<MODE>")
4930 (set_attr "merge_op_idx" "1")
4931 (set_attr "vl_op_idx" "5")
4932 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4933 (set (attr "avl_type_idx") (const_int 7))])
4935 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
4936 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4937 (if_then_else:<VM>
4938 (unspec:<VM>
4939 [(match_operand:<VM> 1 "register_operand" " 0")
4940 (match_operand 5 "vector_length_operand" " rK")
4941 (match_operand 6 "const_int_operand" " i")
4942 (match_operand 7 "const_int_operand" " i")
4943 (reg:SI VL_REGNUM)
4944 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4945 (match_operator:<VM> 2 "equality_operator"
4946 [(vec_duplicate:V_VLSI_D
4947 (match_operand:<VEL> 4 "register_operand" " r"))
4948 (match_operand:V_VLSI_D 3 "register_operand" " vr")])
4949 (match_dup 1)))]
4950 "TARGET_VECTOR"
4951 "vms%B2.vx\t%0,%3,%4,v0.t"
4952 [(set_attr "type" "vicmp")
4953 (set_attr "mode" "<MODE>")
4954 (set_attr "merge_op_idx" "1")
4955 (set_attr "vl_op_idx" "5")
4956 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4957 (set (attr "avl_type_idx") (const_int 7))])
4959 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4960 (define_insn "*pred_cmp<mode>_scalar"
4961 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
4962 (if_then_else:<VM>
4963 (unspec:<VM>
4964 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4965 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4966 (match_operand 7 "const_int_operand" " i, i, i, i")
4967 (match_operand 8 "const_int_operand" " i, i, i, i")
4968 (reg:SI VL_REGNUM)
4969 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4970 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4971 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
4972 (vec_duplicate:V_VLSI_D
4973 (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
4974 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4975 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4976 "vms%B3.vx\t%0,%4,%5%p1"
4977 [(set_attr "type" "vicmp")
4978 (set_attr "mode" "<MODE>")
4979 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
4981 ;; We use early-clobber for source LMUL > dest LMUL.
4982 (define_insn "*pred_cmp<mode>_scalar_narrow"
4983 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4984 (if_then_else:<VM>
4985 (unspec:<VM>
4986 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4987 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4988 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4989 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4990 (reg:SI VL_REGNUM)
4991 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4992 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4993 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
4994 (vec_duplicate:V_VLSI_D
4995 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4996 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4997 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4998 "vms%B3.vx\t%0,%4,%5%p1"
4999 [(set_attr "type" "vicmp")
5000 (set_attr "mode" "<MODE>")
5001 (set_attr "spec_restriction" "none,thv,thv,none,none")])
5003 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5004 (define_insn "*pred_eqne<mode>_scalar"
5005 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
5006 (if_then_else:<VM>
5007 (unspec:<VM>
5008 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
5009 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
5010 (match_operand 7 "const_int_operand" " i, i, i, i")
5011 (match_operand 8 "const_int_operand" " i, i, i, i")
5012 (reg:SI VL_REGNUM)
5013 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5014 (match_operator:<VM> 3 "equality_operator"
5015 [(vec_duplicate:V_VLSI_D
5016 (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))
5017 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")])
5018 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
5019 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
5020 "vms%B3.vx\t%0,%4,%5%p1"
5021 [(set_attr "type" "vicmp")
5022 (set_attr "mode" "<MODE>")
5023 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
5025 ;; We use early-clobber for source LMUL > dest LMUL.
5026 (define_insn "*pred_eqne<mode>_scalar_narrow"
5027 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5028 (if_then_else:<VM>
5029 (unspec:<VM>
5030 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5031 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5032 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5033 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5034 (reg:SI VL_REGNUM)
5035 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5036 (match_operator:<VM> 3 "equality_operator"
5037 [(vec_duplicate:V_VLSI_D
5038 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
5039 (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
5040 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5041 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
5042 "vms%B3.vx\t%0,%4,%5%p1"
5043 [(set_attr "type" "vicmp")
5044 (set_attr "mode" "<MODE>")
5045 (set_attr "spec_restriction" "none,thv,thv,none,none")])
5047 (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
5048 [(set (match_operand:<VM> 0 "register_operand" "=vm")
5049 (if_then_else:<VM>
5050 (unspec:<VM>
5051 [(match_operand:<VM> 1 "register_operand" " 0")
5052 (match_operand 5 "vector_length_operand" " rK")
5053 (match_operand 6 "const_int_operand" " i")
5054 (match_operand 7 "const_int_operand" " i")
5055 (reg:SI VL_REGNUM)
5056 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5057 (match_operator:<VM> 2 "comparison_except_eqge_operator"
5058 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
5059 (vec_duplicate:V_VLSI_D
5060 (sign_extend:<VEL>
5061 (match_operand:<VSUBEL> 4 "register_operand" " r")))])
5062 (match_dup 1)))]
5063 "TARGET_VECTOR && !TARGET_64BIT"
5064 "vms%B2.vx\t%0,%3,%4,v0.t"
5065 [(set_attr "type" "vicmp")
5066 (set_attr "mode" "<MODE>")
5067 (set_attr "merge_op_idx" "1")
5068 (set_attr "vl_op_idx" "5")
5069 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5070 (set (attr "avl_type_idx") (const_int 7))])
5072 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5073 (define_insn "*pred_cmp<mode>_extended_scalar"
5074 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
5075 (if_then_else:<VM>
5076 (unspec:<VM>
5077 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
5078 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
5079 (match_operand 7 "const_int_operand" " i, i, i, i")
5080 (match_operand 8 "const_int_operand" " i, i, i, i")
5081 (reg:SI VL_REGNUM)
5082 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5083 (match_operator:<VM> 3 "comparison_except_eqge_operator"
5084 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5085 (vec_duplicate:V_VLSI_D
5086 (sign_extend:<VEL>
5087 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r")))])
5088 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
5089 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
5090 "vms%B3.vx\t%0,%4,%5%p1"
5091 [(set_attr "type" "vicmp")
5092 (set_attr "mode" "<MODE>")
5093 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
5095 (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
5096 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5097 (if_then_else:<VM>
5098 (unspec:<VM>
5099 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5100 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5101 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5102 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5103 (reg:SI VL_REGNUM)
5104 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5105 (match_operator:<VM> 3 "comparison_except_eqge_operator"
5106 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
5107 (vec_duplicate:V_VLSI_D
5108 (sign_extend:<VEL>
5109 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))])
5110 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5111 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
5112 "vms%B3.vx\t%0,%4,%5%p1"
5113 [(set_attr "type" "vicmp")
5114 (set_attr "mode" "<MODE>")
5115 (set_attr "spec_restriction" "none,thv,thv,none,none")])
5117 (define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
5118 [(set (match_operand:<VM> 0 "register_operand" "=vm")
5119 (if_then_else:<VM>
5120 (unspec:<VM>
5121 [(match_operand:<VM> 1 "register_operand" " 0")
5122 (match_operand 5 "vector_length_operand" " rK")
5123 (match_operand 6 "const_int_operand" " i")
5124 (match_operand 7 "const_int_operand" " i")
5125 (reg:SI VL_REGNUM)
5126 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5127 (match_operator:<VM> 2 "equality_operator"
5128 [(vec_duplicate:V_VLSI_D
5129 (sign_extend:<VEL>
5130 (match_operand:<VSUBEL> 4 "register_operand" " r")))
5131 (match_operand:V_VLSI_D 3 "register_operand" " vr")])
5132 (match_dup 1)))]
5133 "TARGET_VECTOR && !TARGET_64BIT"
5134 "vms%B2.vx\t%0,%3,%4,v0.t"
5135 [(set_attr "type" "vicmp")
5136 (set_attr "mode" "<MODE>")
5137 (set_attr "merge_op_idx" "1")
5138 (set_attr "vl_op_idx" "5")
5139 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5140 (set (attr "avl_type_idx") (const_int 7))])
5142 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5143 (define_insn "*pred_eqne<mode>_extended_scalar"
5144 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
5145 (if_then_else:<VM>
5146 (unspec:<VM>
5147 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
5148 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
5149 (match_operand 7 "const_int_operand" " i, i, i, i")
5150 (match_operand 8 "const_int_operand" " i, i, i, i")
5151 (reg:SI VL_REGNUM)
5152 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5153 (match_operator:<VM> 3 "equality_operator"
5154 [(vec_duplicate:V_VLSI_D
5155 (sign_extend:<VEL>
5156 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r")))
5157 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")])
5158 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
5159 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
5160 "vms%B3.vx\t%0,%4,%5%p1"
5161 [(set_attr "type" "vicmp")
5162 (set_attr "mode" "<MODE>")
5163 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
5165 (define_insn "*pred_eqne<mode>_extended_scalar_narrow"
5166 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5167 (if_then_else:<VM>
5168 (unspec:<VM>
5169 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5170 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5171 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5172 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5173 (reg:SI VL_REGNUM)
5174 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5175 (match_operator:<VM> 3 "equality_operator"
5176 [(vec_duplicate:V_VLSI_D
5177 (sign_extend:<VEL>
5178 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))
5179 (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
5180 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5181 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
5182 "vms%B3.vx\t%0,%4,%5%p1"
5183 [(set_attr "type" "vicmp")
5184 (set_attr "mode" "<MODE>")
5185 (set_attr "spec_restriction" "none,thv,thv,none,none")])
5187 ;; GE, vmsge.vx/vmsgeu.vx
5188 ;;
5189 ;; unmasked va >= x
5190 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x
5191 ;; - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
5192 ;;
5193 ;; masked va >= x, vd != v0
5194 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5195 ;; - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
5196 ;;
5197 ;; masked va >= x, vd == v0
5198 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5199 ;; - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
5200 (define_expand "@pred_ge<mode>_scalar"
5201 [(set (match_operand:<VM> 0 "register_operand")
5202 (if_then_else:<VM>
5203 (unspec:<VM>
5204 [(match_operand:<VM> 1 "vector_mask_operand")
5205 (match_operand 6 "vector_length_operand")
5206 (match_operand 7 "const_int_operand")
5207 (match_operand 8 "const_int_operand")
5208 (reg:SI VL_REGNUM)
5209 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5210 (match_operator:<VM> 3 "ge_operator"
5211 [(match_operand:V_VLSI 4 "register_operand")
5212 (vec_duplicate:V_VLSI
5213 (match_operand:<VEL> 5 "reg_or_int_operand"))])
5214 (match_operand:<VM> 2 "vector_merge_operand")))]
5215 "TARGET_VECTOR"
5216 {
5217 enum rtx_code code = GET_CODE (operands[3]);
5218 rtx undef = RVV_VUNDEF (<VM>mode);
5219 rtx tmp = gen_reg_rtx (<VM>mode);
5220 if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
5221 {
5222 /* If vmsgeu with 0 immediate, expand it to vmset. */
5223 if (satisfies_constraint_Wc1 (operands[1]))
5224 emit_insn (
5225 gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
5226 CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
5227 else
5228 {
5229 /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
5230 */
5231 if (rtx_equal_p (operands[1], operands[2]))
5232 emit_move_insn (operands[0], operands[1]);
5233 else if (register_operand (operands[2], <VM>mode))
5234 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5235 CONSTM1_RTX (<VM>mode), undef, operands[1],
5236 operands[2], operands[6], operands[8]));
5237 else
5238 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5239 CONSTM1_RTX (<VM>mode), undef, operands[1],
5240 operands[1], operands[6], operands[8]));
5241 }
5242 }
5243 else if (riscv_vector::neg_simm5_p (operands[5]))
5244 emit_insn (
5245 gen_pred_ltge<mode> (operands[0], operands[1], operands[2], operands[3],
5246 operands[4],
5247 gen_const_vec_duplicate (<MODE>mode, operands[5]),
5248 operands[6], operands[7], operands[8]));
5249 else
5250 {
5251 if (code == GE)
5252 operands[3] = gen_rtx_fmt_ee (LT, <VM>mode, XEXP (operands[3], 0),
5253 XEXP (operands[3], 1));
5254 else
5255 operands[3] = gen_rtx_fmt_ee (LTU, <VM>mode, XEXP (operands[3], 0),
5256 XEXP (operands[3], 1));
5257 if (GET_MODE_BITSIZE (<VEL>mode) <= GET_MODE_BITSIZE (Pmode))
5258 operands[5] = force_reg (<VEL>mode, operands[5]);
5260 if (satisfies_constraint_Wc1 (operands[1]))
5261 {
5262 /* unmasked va >= x
5263 - pseudoinstruction: vmsge{u}.vx vd, va, x
5264 - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */
5265 emit_insn (
5266 gen_pred_cmp<mode>_scalar (tmp, operands[1], operands[2],
5267 operands[3], operands[4], operands[5],
5268 operands[6], operands[7], operands[8]));
5269 emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
5270 undef, tmp, tmp, operands[6], operands[8]));
5271 }
5272 else
5273 {
5274 if (rtx_equal_p (operands[1], operands[2]))
5275 {
5276 /* masked va >= x, vd == v0
5277 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5278 - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt. */
5279 emit_insn (gen_pred_cmp<mode>_scalar (
5280 tmp, CONSTM1_RTX (<VM>mode), undef, operands[3], operands[4],
5281 operands[5], operands[6], operands[7], operands[8]));
5282 emit_insn (
5283 gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
5284 operands[1], tmp, operands[6], operands[8]));
5285 }
5286 else
5287 {
5288 /* masked va >= x, vd != v0
5289 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5290 - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
5291 */
5292 emit_insn (gen_pred_cmp<mode>_scalar (
5293 tmp, operands[1], operands[2], operands[3], operands[4],
5294 operands[5], operands[6], operands[7], operands[8]));
5295 emit_insn (gen_pred (XOR, <VM>mode, operands[0],
5296 CONSTM1_RTX (<VM>mode), undef, tmp,
5297 operands[1], operands[6], operands[8]));
5298 }
5299 }
5300 }
5301 DONE;
5302 })
5304 ;; -------------------------------------------------------------------------------
5305 ;; ---- Predicated integer ternary operations
5306 ;; -------------------------------------------------------------------------------
5307 ;; Includes:
5308 ;; - 11.13 Vector Single-Width Integer Multiply-Add Instructions
5309 ;; -------------------------------------------------------------------------------
5311 (define_expand "@pred_mul_plus<mode>"
5312 [(set (match_operand:V_VLSI 0 "register_operand")
5313 (if_then_else:V_VLSI
5314 (unspec:<VM>
5315 [(match_operand:<VM> 1 "vector_mask_operand")
5316 (match_operand 6 "vector_length_operand")
5317 (match_operand 7 "const_int_operand")
5318 (match_operand 8 "const_int_operand")
5319 (match_operand 9 "const_int_operand")
5320 (reg:SI VL_REGNUM)
5321 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5322 (plus:V_VLSI
5323 (mult:V_VLSI
5324 (match_operand:V_VLSI 2 "register_operand")
5325 (match_operand:V_VLSI 3 "register_operand"))
5326 (match_operand:V_VLSI 4 "register_operand"))
5327 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5328 "TARGET_VECTOR"
5329 {
5330 riscv_vector::prepare_ternary_operands (operands);
5331 })
5333 (define_insn "*pred_mul_plus<mode>_undef"
5334 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5335 (if_then_else:V_VLSI
5336 (unspec:<VM>
5337 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5338 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5339 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5340 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5341 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5342 (reg:SI VL_REGNUM)
5343 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5344 (plus:V_VLSI
5345 (mult:V_VLSI
5346 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5347 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))
5348 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
5349 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5350 "TARGET_VECTOR"
5351 "@
5352 vmadd.vv\t%0,%4,%5%p1
5353 vmacc.vv\t%0,%3,%4%p1
5354 vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1
5355 vmadd.vv\t%0,%4,%5%p1
5356 vmacc.vv\t%0,%3,%4%p1
5357 vmv%m5r.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1"
5358 [(set_attr "type" "vimuladd")
5359 (set_attr "mode" "<MODE>")])
5361 (define_insn "*pred_madd<mode>"
5362 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5363 (if_then_else:V_VLSI
5364 (unspec:<VM>
5365 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5366 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5367 (match_operand 6 "const_int_operand" " i, i, i, i")
5368 (match_operand 7 "const_int_operand" " i, i, i, i")
5369 (match_operand 8 "const_int_operand" " i, i, i, i")
5370 (reg:SI VL_REGNUM)
5371 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5372 (plus:V_VLSI
5373 (mult:V_VLSI
5374 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5375 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5376 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5377 (match_dup 2)))]
5378 "TARGET_VECTOR"
5379 "@
5380 vmadd.vv\t%0,%3,%4%p1
5381 vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1
5382 vmadd.vv\t%0,%3,%4%p1
5383 vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1"
5384 [(set_attr "type" "vimuladd")
5385 (set_attr "mode" "<MODE>")
5386 (set_attr "merge_op_idx" "2")
5387 (set_attr "vl_op_idx" "5")
5388 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5389 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5390 (set (attr "avl_type_idx") (const_int 8))])
5392 (define_insn "*pred_macc<mode>"
5393 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5394 (if_then_else:V_VLSI
5395 (unspec:<VM>
5396 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5397 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5398 (match_operand 6 "const_int_operand" " i, i, i, i")
5399 (match_operand 7 "const_int_operand" " i, i, i, i")
5400 (match_operand 8 "const_int_operand" " i, i, i, i")
5401 (reg:SI VL_REGNUM)
5402 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5403 (plus:V_VLSI
5404 (mult:V_VLSI
5405 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5406 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5407 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5408 (match_dup 4)))]
5409 "TARGET_VECTOR"
5410 "@
5411 vmacc.vv\t%0,%2,%3%p1
5412 vmv%m4r.v\t%0,%4;vmacc.vv\t%0,%2,%3%p1
5413 vmacc.vv\t%0,%2,%3%p1
5414 vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1"
5415 [(set_attr "type" "vimuladd")
5416 (set_attr "mode" "<MODE>")
5417 (set_attr "merge_op_idx" "4")
5418 (set_attr "vl_op_idx" "5")
5419 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5420 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5421 (set (attr "avl_type_idx") (const_int 8))])
5423 (define_expand "@pred_mul_plus<mode>_scalar"
5424 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5425 (if_then_else:V_VLSI_QHS
5426 (unspec:<VM>
5427 [(match_operand:<VM> 1 "vector_mask_operand")
5428 (match_operand 6 "vector_length_operand")
5429 (match_operand 7 "const_int_operand")
5430 (match_operand 8 "const_int_operand")
5431 (match_operand 9 "const_int_operand")
5432 (reg:SI VL_REGNUM)
5433 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5434 (plus:V_VLSI_QHS
5435 (mult:V_VLSI_QHS
5436 (vec_duplicate:V_VLSI_QHS
5437 (match_operand:<VEL> 2 "register_operand"))
5438 (match_operand:V_VLSI_QHS 3 "register_operand"))
5439 (match_operand:V_VLSI_QHS 4 "register_operand"))
5440 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5441 "TARGET_VECTOR"
5442 {})
5444 (define_insn "*pred_madd<mode>_scalar"
5445 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5446 (if_then_else:V_VLSI
5447 (unspec:<VM>
5448 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5449 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5450 (match_operand 6 "const_int_operand" " i, i, i, i")
5451 (match_operand 7 "const_int_operand" " i, i, i, i")
5452 (match_operand 8 "const_int_operand" " i, i, i, i")
5453 (reg:SI VL_REGNUM)
5454 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5455 (plus:V_VLSI
5456 (mult:V_VLSI
5457 (vec_duplicate:V_VLSI
5458 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5459 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))
5460 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5461 (match_dup 3)))]
5462 "TARGET_VECTOR"
5463 "@
5464 vmadd.vx\t%0,%2,%4%p1
5465 vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1
5466 vmadd.vx\t%0,%2,%4%p1
5467 vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1"
5468 [(set_attr "type" "vimuladd")
5469 (set_attr "mode" "<MODE>")
5470 (set_attr "merge_op_idx" "3")
5471 (set_attr "vl_op_idx" "5")
5472 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5473 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5474 (set (attr "avl_type_idx") (const_int 8))])
5476 (define_insn "*pred_macc<mode>_scalar"
5477 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5478 (if_then_else:V_VLSI
5479 (unspec:<VM>
5480 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5481 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5482 (match_operand 6 "const_int_operand" " i, i, i, i")
5483 (match_operand 7 "const_int_operand" " i, i, i, i")
5484 (match_operand 8 "const_int_operand" " i, i, i, i")
5485 (reg:SI VL_REGNUM)
5486 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5487 (plus:V_VLSI
5488 (mult:V_VLSI
5489 (vec_duplicate:V_VLSI
5490 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5491 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5492 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5493 (match_dup 4)))]
5494 "TARGET_VECTOR"
5495 "@
5496 vmacc.vx\t%0,%2,%3%p1
5497 vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5498 vmacc.vx\t%0,%2,%3%p1
5499 vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5500 [(set_attr "type" "vimuladd")
5501 (set_attr "mode" "<MODE>")
5502 (set_attr "merge_op_idx" "4")
5503 (set_attr "vl_op_idx" "5")
5504 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5505 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5506 (set (attr "avl_type_idx") (const_int 8))])
5508 (define_expand "@pred_mul_plus<mode>_scalar"
5509 [(set (match_operand:V_VLSI_D 0 "register_operand")
5510 (if_then_else:V_VLSI_D
5511 (unspec:<VM>
5512 [(match_operand:<VM> 1 "vector_mask_operand")
5513 (match_operand 6 "vector_length_operand")
5514 (match_operand 7 "const_int_operand")
5515 (match_operand 8 "const_int_operand")
5516 (match_operand 9 "const_int_operand")
5517 (reg:SI VL_REGNUM)
5518 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5519 (plus:V_VLSI_D
5520 (mult:V_VLSI_D
5521 (vec_duplicate:V_VLSI_D
5522 (match_operand:<VEL> 2 "reg_or_int_operand"))
5523 (match_operand:V_VLSI_D 3 "register_operand"))
5524 (match_operand:V_VLSI_D 4 "register_operand"))
5525 (match_operand:V_VLSI_D 5 "register_operand")))]
5526 "TARGET_VECTOR"
5527 {
5528 if (riscv_vector::sew64_scalar_helper (
5529 operands,
5530 /* scalar op */&operands[2],
5531 /* vl */operands[6],
5532 <MODE>mode,
5533 false,
5534 [] (rtx *operands, rtx boardcast_scalar) {
5535 emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
5536 boardcast_scalar, operands[3], operands[4], operands[5],
5537 operands[6], operands[7], operands[8], operands[9]));
5538 },
5539 (riscv_vector::avl_type) INTVAL (operands[9])))
5540 DONE;
5541 })
5543 (define_insn "*pred_madd<mode>_extended_scalar"
5544 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5545 (if_then_else:V_VLSI_D
5546 (unspec:<VM>
5547 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5548 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5549 (match_operand 6 "const_int_operand" " i, i, i, i")
5550 (match_operand 7 "const_int_operand" " i, i, i, i")
5551 (match_operand 8 "const_int_operand" " i, i, i, i")
5552 (reg:SI VL_REGNUM)
5553 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5554 (plus:V_VLSI_D
5555 (mult:V_VLSI_D
5556 (vec_duplicate:V_VLSI_D
5557 (sign_extend:<VEL>
5558 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5559 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))
5560 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr"))
5561 (match_dup 3)))]
5562 "TARGET_VECTOR && !TARGET_64BIT"
5563 "@
5564 vmadd.vx\t%0,%2,%4%p1
5565 vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1
5566 vmadd.vx\t%0,%2,%4%p1
5567 vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1"
5568 [(set_attr "type" "vimuladd")
5569 (set_attr "mode" "<MODE>")
5570 (set_attr "merge_op_idx" "3")
5571 (set_attr "vl_op_idx" "5")
5572 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5573 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5574 (set (attr "avl_type_idx") (const_int 8))])
5576 (define_insn "*pred_macc<mode>_extended_scalar"
5577 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5578 (if_then_else:V_VLSI_D
5579 (unspec:<VM>
5580 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5581 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5582 (match_operand 6 "const_int_operand" " i, i, i, i")
5583 (match_operand 7 "const_int_operand" " i, i, i, i")
5584 (match_operand 8 "const_int_operand" " i, i, i, i")
5585 (reg:SI VL_REGNUM)
5586 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5587 (plus:V_VLSI_D
5588 (mult:V_VLSI_D
5589 (vec_duplicate:V_VLSI_D
5590 (sign_extend:<VEL>
5591 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5592 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))
5593 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr"))
5594 (match_dup 4)))]
5595 "TARGET_VECTOR && !TARGET_64BIT"
5596 "@
5597 vmacc.vx\t%0,%2,%3%p1
5598 vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5599 vmacc.vx\t%0,%2,%3%p1
5600 vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5601 [(set_attr "type" "vimuladd")
5602 (set_attr "mode" "<MODE>")
5603 (set_attr "merge_op_idx" "4")
5604 (set_attr "vl_op_idx" "5")
5605 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5606 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5607 (set (attr "avl_type_idx") (const_int 8))])
5609 (define_expand "@pred_minus_mul<mode>"
5610 [(set (match_operand:V_VLSI 0 "register_operand")
5611 (if_then_else:V_VLSI
5612 (unspec:<VM>
5613 [(match_operand:<VM> 1 "vector_mask_operand")
5614 (match_operand 6 "vector_length_operand")
5615 (match_operand 7 "const_int_operand")
5616 (match_operand 8 "const_int_operand")
5617 (match_operand 9 "const_int_operand")
5618 (reg:SI VL_REGNUM)
5619 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5620 (minus:V_VLSI
5621 (match_operand:V_VLSI 4 "register_operand")
5622 (mult:V_VLSI
5623 (match_operand:V_VLSI 2 "register_operand")
5624 (match_operand:V_VLSI 3 "register_operand")))
5625 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5626 "TARGET_VECTOR"
5627 {
5628 riscv_vector::prepare_ternary_operands (operands);
5629 })
5631 (define_insn "*pred_minus_mul<mode>_undef"
5632 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5633 (if_then_else:V_VLSI
5634 (unspec:<VM>
5635 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5636 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5637 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5638 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5639 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5640 (reg:SI VL_REGNUM)
5641 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5642 (minus:V_VLSI
5643 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr")
5644 (mult:V_VLSI
5645 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5646 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr")))
5647 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5648 "TARGET_VECTOR"
5649 "@
5650 vnmsub.vv\t%0,%4,%5%p1
5651 vnmsac.vv\t%0,%3,%4%p1
5652 vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1
5653 vnmsub.vv\t%0,%4,%5%p1
5654 vnmsac.vv\t%0,%3,%4%p1
5655 vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1"
5656 [(set_attr "type" "vimuladd")
5657 (set_attr "mode" "<MODE>")])
5659 (define_insn "*pred_nmsub<mode>"
5660 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5661 (if_then_else:V_VLSI
5662 (unspec:<VM>
5663 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5664 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5665 (match_operand 6 "const_int_operand" " i, i, i, i")
5666 (match_operand 7 "const_int_operand" " i, i, i, i")
5667 (match_operand 8 "const_int_operand" " i, i, i, i")
5668 (reg:SI VL_REGNUM)
5669 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5670 (minus:V_VLSI
5671 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5672 (mult:V_VLSI
5673 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5674 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5675 (match_dup 2)))]
5676 "TARGET_VECTOR"
5677 "@
5678 vnmsub.vv\t%0,%3,%4%p1
5679 vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1
5680 vnmsub.vv\t%0,%3,%4%p1
5681 vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1"
5682 [(set_attr "type" "vimuladd")
5683 (set_attr "mode" "<MODE>")
5684 (set_attr "merge_op_idx" "2")
5685 (set_attr "vl_op_idx" "5")
5686 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5687 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5688 (set (attr "avl_type_idx") (const_int 8))])
5690 (define_insn "*pred_nmsac<mode>"
5691 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5692 (if_then_else:V_VLSI
5693 (unspec:<VM>
5694 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5695 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5696 (match_operand 6 "const_int_operand" " i, i, i, i")
5697 (match_operand 7 "const_int_operand" " i, i, i, i")
5698 (match_operand 8 "const_int_operand" " i, i, i, i")
5699 (reg:SI VL_REGNUM)
5700 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5701 (minus:V_VLSI
5702 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5703 (mult:V_VLSI
5704 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5705 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5706 (match_dup 4)))]
5707 "TARGET_VECTOR"
5708 "@
5709 vnmsac.vv\t%0,%2,%3%p1
5710 vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1
5711 vnmsac.vv\t%0,%2,%3%p1
5712 vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1"
5713 [(set_attr "type" "vimuladd")
5714 (set_attr "mode" "<MODE>")
5715 (set_attr "merge_op_idx" "4")
5716 (set_attr "vl_op_idx" "5")
5717 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5718 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5719 (set (attr "avl_type_idx") (const_int 8))])
5721 (define_expand "@pred_minus_mul<mode>_scalar"
5722 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5723 (if_then_else:V_VLSI_QHS
5724 (unspec:<VM>
5725 [(match_operand:<VM> 1 "vector_mask_operand")
5726 (match_operand 6 "vector_length_operand")
5727 (match_operand 7 "const_int_operand")
5728 (match_operand 8 "const_int_operand")
5729 (match_operand 9 "const_int_operand")
5730 (reg:SI VL_REGNUM)
5731 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5732 (minus:V_VLSI_QHS
5733 (match_operand:V_VLSI_QHS 4 "register_operand")
5734 (mult:V_VLSI_QHS
5735 (vec_duplicate:V_VLSI_QHS
5736 (match_operand:<VEL> 2 "register_operand"))
5737 (match_operand:V_VLSI_QHS 3 "register_operand")))
5738 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5739 "TARGET_VECTOR"
5740 {})
5742 (define_insn "*pred_nmsub<mode>_scalar"
5743 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5744 (if_then_else:V_VLSI
5745 (unspec:<VM>
5746 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5747 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5748 (match_operand 6 "const_int_operand" " i, i, i, i")
5749 (match_operand 7 "const_int_operand" " i, i, i, i")
5750 (match_operand 8 "const_int_operand" " i, i, i, i")
5751 (reg:SI VL_REGNUM)
5752 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5753 (minus:V_VLSI
5754 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5755 (mult:V_VLSI
5756 (vec_duplicate:V_VLSI
5757 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5758 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")))
5759 (match_dup 3)))]
5760 "TARGET_VECTOR"
5761 "@
5762 vnmsub.vx\t%0,%2,%4%p1
5763 vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5764 vnmsub.vx\t%0,%2,%4%p1
5765 vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5766 [(set_attr "type" "vimuladd")
5767 (set_attr "mode" "<MODE>")
5768 (set_attr "merge_op_idx" "3")
5769 (set_attr "vl_op_idx" "5")
5770 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5771 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5772 (set (attr "avl_type_idx") (const_int 8))])
5774 (define_insn "*pred_nmsac<mode>_scalar"
5775 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5776 (if_then_else:V_VLSI
5777 (unspec:<VM>
5778 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5779 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5780 (match_operand 6 "const_int_operand" " i, i, i, i")
5781 (match_operand 7 "const_int_operand" " i, i, i, i")
5782 (match_operand 8 "const_int_operand" " i, i, i, i")
5783 (reg:SI VL_REGNUM)
5784 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5785 (minus:V_VLSI
5786 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5787 (mult:V_VLSI
5788 (vec_duplicate:V_VLSI
5789 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5790 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5791 (match_dup 4)))]
5792 "TARGET_VECTOR"
5793 "@
5794 vnmsac.vx\t%0,%2,%3%p1
5795 vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5796 vnmsac.vx\t%0,%2,%3%p1
5797 vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5798 [(set_attr "type" "vimuladd")
5799 (set_attr "mode" "<MODE>")
5800 (set_attr "merge_op_idx" "4")
5801 (set_attr "vl_op_idx" "5")
5802 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5803 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5804 (set (attr "avl_type_idx") (const_int 8))])
5806 (define_expand "@pred_minus_mul<mode>_scalar"
5807 [(set (match_operand:V_VLSI_D 0 "register_operand")
5808 (if_then_else:V_VLSI_D
5809 (unspec:<VM>
5810 [(match_operand:<VM> 1 "vector_mask_operand")
5811 (match_operand 6 "vector_length_operand")
5812 (match_operand 7 "const_int_operand")
5813 (match_operand 8 "const_int_operand")
5814 (match_operand 9 "const_int_operand")
5815 (reg:SI VL_REGNUM)
5816 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5817 (minus:V_VLSI_D
5818 (match_operand:V_VLSI_D 4 "register_operand")
5819 (mult:V_VLSI_D
5820 (vec_duplicate:V_VLSI_D
5821 (match_operand:<VEL> 2 "reg_or_int_operand"))
5822 (match_operand:V_VLSI_D 3 "register_operand")))
5823 (match_operand:V_VLSI_D 5 "register_operand")))]
5824 "TARGET_VECTOR"
5825 {
5826 if (riscv_vector::sew64_scalar_helper (
5827 operands,
5828 /* scalar op */&operands[2],
5829 /* vl */operands[6],
5830 <MODE>mode,
5831 false,
5832 [] (rtx *operands, rtx boardcast_scalar) {
5833 emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
5834 boardcast_scalar, operands[3], operands[4], operands[5],
5835 operands[6], operands[7], operands[8], operands[9]));
5836 },
5837 (riscv_vector::avl_type) INTVAL (operands[9])))
5838 DONE;
5839 })
5841 (define_insn "*pred_nmsub<mode>_extended_scalar"
5842 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5843 (if_then_else:V_VLSI_D
5844 (unspec:<VM>
5845 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5846 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5847 (match_operand 6 "const_int_operand" " i, i, i, i")
5848 (match_operand 7 "const_int_operand" " i, i, i, i")
5849 (match_operand 8 "const_int_operand" " i, i, i, i")
5850 (reg:SI VL_REGNUM)
5851 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5852 (minus:V_VLSI_D
5853 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5854 (mult:V_VLSI_D
5855 (vec_duplicate:V_VLSI_D
5856 (sign_extend:<VEL>
5857 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5858 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")))
5859 (match_dup 3)))]
5860 "TARGET_VECTOR && !TARGET_64BIT"
5861 "@
5862 vnmsub.vx\t%0,%2,%4%p1
5863 vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5864 vnmsub.vx\t%0,%2,%4%p1
5865 vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5866 [(set_attr "type" "vimuladd")
5867 (set_attr "mode" "<MODE>")
5868 (set_attr "merge_op_idx" "3")
5869 (set_attr "vl_op_idx" "5")
5870 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5871 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5872 (set (attr "avl_type_idx") (const_int 8))])
5874 (define_insn "*pred_nmsac<mode>_extended_scalar"
5875 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5876 (if_then_else:V_VLSI_D
5877 (unspec:<VM>
5878 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5879 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5880 (match_operand 6 "const_int_operand" " i, i, i, i")
5881 (match_operand 7 "const_int_operand" " i, i, i, i")
5882 (match_operand 8 "const_int_operand" " i, i, i, i")
5883 (reg:SI VL_REGNUM)
5884 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5885 (minus:V_VLSI_D
5886 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")
5887 (mult:V_VLSI_D
5888 (vec_duplicate:V_VLSI_D
5889 (sign_extend:<VEL>
5890 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5891 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")))
5892 (match_dup 4)))]
5893 "TARGET_VECTOR && !TARGET_64BIT"
5894 "@
5895 vnmsac.vx\t%0,%2,%3%p1
5896 vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5897 vnmsac.vx\t%0,%2,%3%p1
5898 vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5899 [(set_attr "type" "vimuladd")
5900 (set_attr "mode" "<MODE>")
5901 (set_attr "merge_op_idx" "4")
5902 (set_attr "vl_op_idx" "5")
5903 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5904 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5905 (set (attr "avl_type_idx") (const_int 8))])
5907 ;; -------------------------------------------------------------------------------
5908 ;; ---- Predicated widen integer ternary operations
5909 ;; -------------------------------------------------------------------------------
5910 ;; Includes:
5911 ;; - 11.14 Vector Widening Integer Multiply-Add Instructions
5912 ;; -------------------------------------------------------------------------------
5914 (define_insn "@pred_widen_mul_plus<su><mode>"
5915 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5916 (if_then_else:VWEXTI
5917 (unspec:<VM>
5918 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5919 (match_operand 5 "vector_length_operand" " rK")
5920 (match_operand 6 "const_int_operand" " i")
5921 (match_operand 7 "const_int_operand" " i")
5922 (match_operand 8 "const_int_operand" " i")
5923 (reg:SI VL_REGNUM)
5924 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5925 (plus:VWEXTI
5926 (mult:VWEXTI
5927 (any_extend:VWEXTI
5928 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5929 (any_extend:VWEXTI
5930 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5931 (match_operand:VWEXTI 2 "register_operand" " 0"))
5932 (match_dup 2)))]
5933 "TARGET_VECTOR"
5934 "vwmacc<u>.vv\t%0,%3,%4%p1"
5935 [(set_attr "type" "viwmuladd")
5936 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5938 (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
5939 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
5940 (if_then_else:VWEXTI
5941 (unspec:<VM>
5942 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
5943 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
5944 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
5945 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
5946 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
5947 (reg:SI VL_REGNUM)
5948 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5949 (plus:VWEXTI
5950 (mult:VWEXTI
5951 (any_extend:VWEXTI
5952 (vec_duplicate:<V_DOUBLE_TRUNC>
5953 (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
5954 (any_extend:VWEXTI
5955 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
5956 (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
5957 (match_dup 2)))]
5958 "TARGET_VECTOR"
5959 "vwmacc<u>.vx\t%0,%z3,%4%p1"
5960 [(set_attr "type" "viwmuladd")
5961 (set_attr "mode" "<V_DOUBLE_TRUNC>")
5962 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
5964 (define_insn "@pred_widen_mul_plussu<mode>"
5965 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5966 (if_then_else:VWEXTI
5967 (unspec:<VM>
5968 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5969 (match_operand 5 "vector_length_operand" " rK")
5970 (match_operand 6 "const_int_operand" " i")
5971 (match_operand 7 "const_int_operand" " i")
5972 (match_operand 8 "const_int_operand" " i")
5973 (reg:SI VL_REGNUM)
5974 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5975 (plus:VWEXTI
5976 (mult:VWEXTI
5977 (sign_extend:VWEXTI
5978 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5979 (zero_extend:VWEXTI
5980 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5981 (match_operand:VWEXTI 2 "register_operand" " 0"))
5982 (match_dup 2)))]
5983 "TARGET_VECTOR"
5984 "vwmaccsu.vv\t%0,%3,%4%p1"
5985 [(set_attr "type" "viwmuladd")
5986 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5988 (define_insn "@pred_widen_mul_plussu<mode>_scalar"
5989 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
5990 (if_then_else:VWEXTI
5991 (unspec:<VM>
5992 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
5993 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
5994 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
5995 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
5996 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
5997 (reg:SI VL_REGNUM)
5998 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5999 (plus:VWEXTI
6000 (mult:VWEXTI
6001 (sign_extend:VWEXTI
6002 (vec_duplicate:<V_DOUBLE_TRUNC>
6003 (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
6004 (zero_extend:VWEXTI
6005 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
6006 (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
6007 (match_dup 2)))]
6008 "TARGET_VECTOR"
6009 "vwmaccsu.vx\t%0,%z3,%4%p1"
6010 [(set_attr "type" "viwmuladd")
6011 (set_attr "mode" "<V_DOUBLE_TRUNC>")
6012 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
6014 (define_insn "@pred_widen_mul_plusus<mode>_scalar"
6015 [(set (match_operand:VWEXTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
6016 (if_then_else:VWEXTI
6017 (unspec:<VM>
6018 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
6019 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
6020 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
6021 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
6022 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
6023 (reg:SI VL_REGNUM)
6024 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6025 (plus:VWEXTI
6026 (mult:VWEXTI
6027 (zero_extend:VWEXTI
6028 (vec_duplicate:<V_DOUBLE_TRUNC>
6029 (match_operand:<VSUBEL> 3 "reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ")))
6030 (sign_extend:VWEXTI
6031 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
6032 (match_operand:VWEXTI 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
6033 (match_dup 2)))]
6034 "TARGET_VECTOR"
6035 "vwmaccus.vx\t%0,%z3,%4%p1"
6036 [(set_attr "type" "viwmuladd")
6037 (set_attr "mode" "<V_DOUBLE_TRUNC>")
6038 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
6040 ;; -------------------------------------------------------------------------------
6041 ;; ---- Predicated BOOL mask operations
6042 ;; -------------------------------------------------------------------------------
6043 ;; Includes:
6044 ;; - 15.1 Vector Mask-Register Logical Instructions
6045 ;; - 15.2 Vector count population in mask vcpop.m
6046 ;; - 15.3 vfirst find-first-set mask bit
6047 ;; - 15.4 vmsbf.m set-before-first mask bit
6048 ;; - 15.5 vmsif.m set-including-first mask bit
6049 ;; - 15.6 vmsof.m set-only-first mask bit
6050 ;; - 15.8 Vector Iota Instruction
6051 ;; - 15.9 Vector Element Index Instruction
6052 ;; -------------------------------------------------------------------------------
6054 ;; We keep this pattern same as pred_mov so that we can gain more optimizations.
6055 ;; For example, if we have vmxor.mm v1,v1,v1. It will be optmized as vmclr.m which
6056 ;; is generated by pred_mov.
6057 (define_insn "@pred_<optab><mode>"
6058 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6059 (if_then_else:VB_VLS
6060 (unspec:VB_VLS
6061 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6062 (match_operand 5 "vector_length_operand" " rK")
6063 (match_operand 6 "const_int_operand" " i")
6064 (reg:SI VL_REGNUM)
6065 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6066 (any_bitwise:VB_VLS
6067 (match_operand:VB_VLS 3 "register_operand" " vr")
6068 (match_operand:VB_VLS 4 "register_operand" " vr"))
6069 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6070 "TARGET_VECTOR"
6071 "vm<insn>.mm\t%0,%3,%4"
6072 [(set_attr "type" "vmalu")
6073 (set_attr "mode" "<MODE>")
6074 (set_attr "vl_op_idx" "5")
6075 (set (attr "avl_type_idx") (const_int 6))])
6077 (define_insn "@pred_n<optab><mode>"
6078 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6079 (if_then_else:VB_VLS
6080 (unspec:VB_VLS
6081 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6082 (match_operand 5 "vector_length_operand" " rK")
6083 (match_operand 6 "const_int_operand" " i")
6084 (reg:SI VL_REGNUM)
6085 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6086 (not:VB_VLS
6087 (any_bitwise:VB_VLS
6088 (match_operand:VB_VLS 3 "register_operand" " vr")
6089 (match_operand:VB_VLS 4 "register_operand" " vr")))
6090 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6091 "TARGET_VECTOR"
6092 "vm<ninsn>.mm\t%0,%3,%4"
6093 [(set_attr "type" "vmalu")
6094 (set_attr "mode" "<MODE>")
6095 (set_attr "vl_op_idx" "5")
6096 (set (attr "avl_type_idx") (const_int 6))])
6098 (define_insn "@pred_<optab>not<mode>"
6099 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6100 (if_then_else:VB_VLS
6101 (unspec:VB_VLS
6102 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6103 (match_operand 5 "vector_length_operand" " rK")
6104 (match_operand 6 "const_int_operand" " i")
6105 (reg:SI VL_REGNUM)
6106 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6107 (and_ior:VB_VLS
6108 (match_operand:VB_VLS 3 "register_operand" " vr")
6109 (not:VB_VLS
6110 (match_operand:VB_VLS 4 "register_operand" " vr")))
6111 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6112 "TARGET_VECTOR"
6113 "vm<insn>n.mm\t%0,%3,%4"
6114 [(set_attr "type" "vmalu")
6115 (set_attr "mode" "<MODE>")
6116 (set_attr "vl_op_idx" "5")
6117 (set (attr "avl_type_idx") (const_int 6))])
6119 (define_insn "@pred_not<mode>"
6120 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6121 (if_then_else:VB_VLS
6122 (unspec:VB_VLS
6123 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6124 (match_operand 4 "vector_length_operand" " rK")
6125 (match_operand 5 "const_int_operand" " i")
6126 (reg:SI VL_REGNUM)
6127 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6128 (not:VB_VLS
6129 (match_operand:VB_VLS 3 "register_operand" " vr"))
6130 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6131 "TARGET_VECTOR"
6132 "vmnot.m\t%0,%3"
6133 [(set_attr "type" "vmalu")
6134 (set_attr "mode" "<MODE>")
6135 (set_attr "vl_op_idx" "4")
6136 (set (attr "avl_type_idx") (const_int 5))])
6138 (define_insn "@pred_popcount<VB:mode><P:mode>"
6139 [(set (match_operand:P 0 "register_operand" "=r")
6140 (popcount:P
6141 (unspec:VB
6142 [(and:VB
6143 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6144 (match_operand:VB 2 "register_operand" " vr"))
6145 (match_operand 3 "vector_length_operand" " rK")
6146 (match_operand 4 "const_int_operand" " i")
6147 (reg:SI VL_REGNUM)
6148 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
6149 "TARGET_VECTOR"
6150 "vcpop.m\t%0,%2%p1"
6151 [(set_attr "type" "vmpop")
6152 (set_attr "mode" "<VB:MODE>")])
6154 (define_insn "@pred_ffs<VB:mode><P:mode>"
6155 [(set (match_operand:P 0 "register_operand" "=r")
6156 (plus:P
6157 (ffs:P
6158 (unspec:VB
6159 [(and:VB
6160 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6161 (match_operand:VB 2 "register_operand" " vr"))
6162 (match_operand 3 "vector_length_operand" " rK")
6163 (match_operand 4 "const_int_operand" " i")
6164 (reg:SI VL_REGNUM)
6165 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))
6166 (const_int -1)))]
6167 "TARGET_VECTOR"
6168 "vfirst.m\t%0,%2%p1"
6169 [(set_attr "type" "vmffs")
6170 (set_attr "mode" "<VB:MODE>")])
6172 (define_insn "@pred_<misc_op><mode>"
6173 [(set (match_operand:VB 0 "register_operand" "=&vr, &vr")
6174 (if_then_else:VB
6175 (unspec:VB
6176 [(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
6177 (match_operand 4 "vector_length_operand" " rK, rK")
6178 (match_operand 5 "const_int_operand" " i, i")
6179 (match_operand 6 "const_int_operand" " i, i")
6180 (reg:SI VL_REGNUM)
6181 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6182 (unspec:VB
6183 [(match_operand:VB 3 "register_operand" " vr, vr")] VMISC)
6184 (match_operand:VB 2 "vector_merge_operand" " vu, 0")))]
6185 "TARGET_VECTOR"
6186 "vm<misc_op>.m\t%0,%3%p1"
6187 [(set_attr "type" "vmsfs")
6188 (set_attr "mode" "<MODE>")])
6190 (define_insn "@pred_iota<mode>"
6191 [(set (match_operand:VI 0 "register_operand" "=&vr, &vr")
6192 (if_then_else:VI
6193 (unspec:<VM>
6194 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
6195 (match_operand 4 "vector_length_operand" " rK, rK")
6196 (match_operand 5 "const_int_operand" " i, i")
6197 (match_operand 6 "const_int_operand" " i, i")
6198 (match_operand 7 "const_int_operand" " i, i")
6199 (reg:SI VL_REGNUM)
6200 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6201 (unspec:VI
6202 [(match_operand:<VM> 3 "register_operand" " vr, vr")] UNSPEC_VIOTA)
6203 (match_operand:VI 2 "vector_merge_operand" " vu, 0")))]
6204 "TARGET_VECTOR"
6205 "viota.m\t%0,%3%p1"
6206 [(set_attr "type" "vmiota")
6207 (set_attr "mode" "<MODE>")])
6209 (define_insn "@pred_series<mode>"
6210 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
6211 (if_then_else:V_VLSI
6212 (unspec:<VM>
6213 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6214 (match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
6215 (match_operand 4 "const_int_operand" " i, i, i, i")
6216 (match_operand 5 "const_int_operand" " i, i, i, i")
6217 (match_operand 6 "const_int_operand" " i, i, i, i")
6218 (reg:SI VL_REGNUM)
6219 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6220 (vec_series:V_VLSI (const_int 0) (const_int 1))
6221 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6222 "TARGET_VECTOR"
6223 "vid.v\t%0%p1"
6224 [(set_attr "type" "vmidx")
6225 (set_attr "mode" "<MODE>")])
6227 ;; -------------------------------------------------------------------------------
6228 ;; ---- Predicated floating-point binary operations
6229 ;; -------------------------------------------------------------------------------
6230 ;; Includes:
6231 ;; - 13.2 Vector Single-Width Floating-Point Add/Subtract Instructions
6232 ;; - 13.4 Vector Single-Width Floating-Point Multiply/Divide Instructions
6233 ;; - 13.11 Vector Floating-Point MIN/MAX Instructions
6234 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions
6235 ;; -------------------------------------------------------------------------------
6237 (define_insn "@pred_<optab><mode>"
6238 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6239 (if_then_else:V_VLSF
6240 (unspec:<VM>
6241 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6242 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6243 (match_operand 6 "const_int_operand" " i, i, i, i")
6244 (match_operand 7 "const_int_operand" " i, i, i, i")
6245 (match_operand 8 "const_int_operand" " i, i, i, i")
6246 (match_operand 9 "const_int_operand" " i, i, i, i")
6247 (reg:SI VL_REGNUM)
6248 (reg:SI VTYPE_REGNUM)
6249 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6250 (any_float_binop:V_VLSF
6251 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6252 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6253 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6254 "TARGET_VECTOR"
6255 "vf<insn>.vv\t%0,%3,%4%p1"
6256 [(set_attr "type" "<float_insn_type>")
6257 (set_attr "mode" "<MODE>")
6258 (set (attr "frm_mode")
6259 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6261 (define_insn "@pred_<optab><mode>"
6262 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6263 (if_then_else:V_VLSF
6264 (unspec:<VM>
6265 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6266 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6267 (match_operand 6 "const_int_operand" " i, i, i, i")
6268 (match_operand 7 "const_int_operand" " i, i, i, i")
6269 (match_operand 8 "const_int_operand" " i, i, i, i")
6270 (reg:SI VL_REGNUM)
6271 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6272 (any_float_binop_nofrm:V_VLSF
6273 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6274 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6275 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6276 "TARGET_VECTOR"
6277 "vf<insn>.vv\t%0,%3,%4%p1"
6278 [(set_attr "type" "<float_insn_type>")
6279 (set_attr "mode" "<MODE>")])
6281 (define_insn "@pred_<ieee_fmaxmin_op><mode>"
6282 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6283 (if_then_else:V_VLSF
6284 (unspec:<VM>
6285 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6286 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6287 (match_operand 6 "const_int_operand" " i, i, i, i")
6288 (match_operand 7 "const_int_operand" " i, i, i, i")
6289 (match_operand 8 "const_int_operand" " i, i, i, i")
6290 (reg:SI VL_REGNUM)
6291 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6292 (unspec:V_VLSF
6293 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6294 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]
6295 UNSPEC_VFMAXMIN)
6296 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6297 "TARGET_VECTOR"
6298 "v<ieee_fmaxmin_op>.vv\t%0,%3,%4%p1"
6299 [(set_attr "type" "vfminmax")
6300 (set_attr "mode" "<MODE>")])
6302 (define_insn "@pred_<optab><mode>_scalar"
6303 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6304 (if_then_else:VF
6305 (unspec:<VM>
6306 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6307 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6308 (match_operand 6 "const_int_operand" " i, i, i, i")
6309 (match_operand 7 "const_int_operand" " i, i, i, i")
6310 (match_operand 8 "const_int_operand" " i, i, i, i")
6311 (match_operand 9 "const_int_operand" " i, i, i, i")
6312 (reg:SI VL_REGNUM)
6313 (reg:SI VTYPE_REGNUM)
6314 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6315 (commutative_float_binop:VF
6316 (vec_duplicate:VF
6317 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6318 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6319 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6320 "TARGET_VECTOR"
6321 "vf<insn>.vf\t%0,%3,%4%p1"
6322 [(set_attr "type" "<float_insn_type>")
6323 (set_attr "mode" "<MODE>")
6324 (set (attr "frm_mode")
6325 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6327 (define_insn "@pred_<optab><mode>_scalar"
6328 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6329 (if_then_else:VF
6330 (unspec:<VM>
6331 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6332 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6333 (match_operand 6 "const_int_operand" " i, i, i, i")
6334 (match_operand 7 "const_int_operand" " i, i, i, i")
6335 (match_operand 8 "const_int_operand" " i, i, i, i")
6336 (reg:SI VL_REGNUM)
6337 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6338 (commutative_float_binop_nofrm:VF
6339 (vec_duplicate:VF
6340 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6341 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6342 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6343 "TARGET_VECTOR"
6344 "vf<insn>.vf\t%0,%3,%4%p1"
6345 [(set_attr "type" "<float_insn_type>")
6346 (set_attr "mode" "<MODE>")])
6348 (define_insn "@pred_<ieee_fmaxmin_op><mode>_scalar"
6349 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6350 (if_then_else:VF
6351 (unspec:<VM>
6352 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6353 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6354 (match_operand 6 "const_int_operand" " i, i, i, i")
6355 (match_operand 7 "const_int_operand" " i, i, i, i")
6356 (match_operand 8 "const_int_operand" " i, i, i, i")
6357 (reg:SI VL_REGNUM)
6358 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6359 (unspec:VF
6360 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6361 (vec_duplicate:VF
6362 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))]
6363 UNSPEC_VFMAXMIN)
6364 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6365 "TARGET_VECTOR"
6366 "v<ieee_fmaxmin_op>.vf\t%0,%3,%4%p1"
6367 [(set_attr "type" "vfminmax")
6368 (set_attr "mode" "<MODE>")])
6370 (define_insn "@pred_<optab><mode>_scalar"
6371 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6372 (if_then_else:VF
6373 (unspec:<VM>
6374 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6375 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6376 (match_operand 6 "const_int_operand" " i, i, i, i")
6377 (match_operand 7 "const_int_operand" " i, i, i, i")
6378 (match_operand 8 "const_int_operand" " i, i, i, i")
6379 (match_operand 9 "const_int_operand" " i, i, i, i")
6380 (reg:SI VL_REGNUM)
6381 (reg:SI VTYPE_REGNUM)
6382 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6383 (non_commutative_float_binop:VF
6384 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6385 (vec_duplicate:VF
6386 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
6387 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6388 "TARGET_VECTOR"
6389 "vf<insn>.vf\t%0,%3,%4%p1"
6390 [(set_attr "type" "<float_insn_type>")
6391 (set_attr "mode" "<MODE>")
6392 (set (attr "frm_mode")
6393 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6395 (define_insn "@pred_<optab><mode>_reverse_scalar"
6396 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6397 (if_then_else:VF
6398 (unspec:<VM>
6399 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6400 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6401 (match_operand 6 "const_int_operand" " i, i, i, i")
6402 (match_operand 7 "const_int_operand" " i, i, i, i")
6403 (match_operand 8 "const_int_operand" " i, i, i, i")
6404 (match_operand 9 "const_int_operand" " i, i, i, i")
6405 (reg:SI VL_REGNUM)
6406 (reg:SI VTYPE_REGNUM)
6407 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6408 (non_commutative_float_binop:VF
6409 (vec_duplicate:VF
6410 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6411 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6412 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6413 "TARGET_VECTOR"
6414 "vfr<insn>.vf\t%0,%3,%4%p1"
6415 [(set_attr "type" "<float_insn_type>")
6416 (set_attr "mode" "<MODE>")
6417 (set (attr "frm_mode")
6418 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6420 (define_insn "@pred_<copysign><mode>"
6421 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6422 (if_then_else:V_VLSF
6423 (unspec:<VM>
6424 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6425 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6426 (match_operand 6 "const_int_operand" " i, i, i, i")
6427 (match_operand 7 "const_int_operand" " i, i, i, i")
6428 (match_operand 8 "const_int_operand" " i, i, i, i")
6429 (reg:SI VL_REGNUM)
6430 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6431 (unspec:V_VLSF
6432 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6433 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
6434 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6435 "TARGET_VECTOR"
6436 "vfsgnj<nx>.vv\t%0,%3,%4%p1"
6437 [(set_attr "type" "vfsgnj")
6438 (set_attr "mode" "<MODE>")])
6440 (define_insn "@pred_ncopysign<mode>"
6441 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6442 (if_then_else:VF
6443 (unspec:<VM>
6444 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6445 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6446 (match_operand 6 "const_int_operand" " i, i, i, i")
6447 (match_operand 7 "const_int_operand" " i, i, i, i")
6448 (match_operand 8 "const_int_operand" " i, i, i, i")
6449 (reg:SI VL_REGNUM)
6450 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6451 (neg:VF
6452 (unspec:VF
6453 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6454 (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))
6455 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6456 "TARGET_VECTOR"
6457 "vfsgnjn.vv\t%0,%3,%4%p1"
6458 [(set_attr "type" "vfsgnj")
6459 (set_attr "mode" "<MODE>")])
6461 (define_insn "@pred_<copysign><mode>_scalar"
6462 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6463 (if_then_else:V_VLSF
6464 (unspec:<VM>
6465 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6466 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6467 (match_operand 6 "const_int_operand" " i, i, i, i")
6468 (match_operand 7 "const_int_operand" " i, i, i, i")
6469 (match_operand 8 "const_int_operand" " i, i, i, i")
6470 (reg:SI VL_REGNUM)
6471 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6472 (unspec:V_VLSF
6473 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6474 (vec_duplicate:V_VLSF
6475 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
6476 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6477 "TARGET_VECTOR"
6478 "vfsgnj<nx>.vf\t%0,%3,%4%p1"
6479 [(set_attr "type" "vfsgnj")
6480 (set_attr "mode" "<MODE>")])
6482 (define_insn "@pred_ncopysign<mode>_scalar"
6483 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6484 (if_then_else:VF
6485 (unspec:<VM>
6486 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6487 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6488 (match_operand 6 "const_int_operand" " i, i, i, i")
6489 (match_operand 7 "const_int_operand" " i, i, i, i")
6490 (match_operand 8 "const_int_operand" " i, i, i, i")
6491 (reg:SI VL_REGNUM)
6492 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6493 (neg:VF
6494 (unspec:VF
6495 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6496 (vec_duplicate:VF
6497 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] UNSPEC_VCOPYSIGN))
6498 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6499 "TARGET_VECTOR"
6500 "vfsgnjn.vf\t%0,%3,%4%p1"
6501 [(set_attr "type" "vfsgnj")
6502 (set_attr "mode" "<MODE>")])
6504 ;; -------------------------------------------------------------------------------
6505 ;; ---- Predicated floating-point ternary operations
6506 ;; -------------------------------------------------------------------------------
6507 ;; Includes:
6508 ;; - 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions
6509 ;; -------------------------------------------------------------------------------
6511 (define_expand "@pred_mul_<optab><mode>"
6512 [(set (match_operand:V_VLSF 0 "register_operand")
6513 (if_then_else:V_VLSF
6514 (unspec:<VM>
6515 [(match_operand:<VM> 1 "vector_mask_operand")
6516 (match_operand 6 "vector_length_operand")
6517 (match_operand 7 "const_int_operand")
6518 (match_operand 8 "const_int_operand")
6519 (match_operand 9 "const_int_operand")
6520 (match_operand 10 "const_int_operand")
6521 (reg:SI VL_REGNUM)
6522 (reg:SI VTYPE_REGNUM)
6523 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6524 (plus_minus:V_VLSF
6525 (mult:V_VLSF
6526 (match_operand:V_VLSF 2 "register_operand")
6527 (match_operand:V_VLSF 3 "register_operand"))
6528 (match_operand:V_VLSF 4 "register_operand"))
6529 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6530 "TARGET_VECTOR"
6531 {
6532 riscv_vector::prepare_ternary_operands (operands);
6533 })
6535 (define_insn "*pred_mul_<optab><mode>_undef"
6536 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6537 (if_then_else:V_VLSF
6538 (unspec:<VM>
6539 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6540 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6541 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6542 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6543 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6544 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6545 (reg:SI VL_REGNUM)
6546 (reg:SI VTYPE_REGNUM)
6547 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6548 (plus_minus:V_VLSF
6549 (mult:V_VLSF
6550 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6551 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr"))
6552 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6553 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6554 "TARGET_VECTOR"
6555 "@
6556 vf<madd_msub>.vv\t%0,%4,%5%p1
6557 vf<macc_msac>.vv\t%0,%3,%4%p1
6558 vmv%m3r.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1
6559 vf<madd_msub>.vv\t%0,%4,%5%p1
6560 vf<macc_msac>.vv\t%0,%3,%4%p1
6561 vmv%m3r.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1"
6562 [(set_attr "type" "vfmuladd")
6563 (set_attr "mode" "<MODE>")
6564 (set (attr "frm_mode")
6565 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6567 (define_insn "*pred_<madd_msub><mode>"
6568 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6569 (if_then_else:V_VLSF
6570 (unspec:<VM>
6571 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6572 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6573 (match_operand 6 "const_int_operand" " i, i, i, i")
6574 (match_operand 7 "const_int_operand" " i, i, i, i")
6575 (match_operand 8 "const_int_operand" " i, i, i, i")
6576 (match_operand 9 "const_int_operand" " i, i, i, i")
6577 (reg:SI VL_REGNUM)
6578 (reg:SI VTYPE_REGNUM)
6579 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6580 (plus_minus:V_VLSF
6581 (mult:V_VLSF
6582 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6583 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6584 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6585 (match_dup 2)))]
6586 "TARGET_VECTOR"
6587 "@
6588 vf<madd_msub>.vv\t%0,%3,%4%p1
6589 vmv%m2r.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
6590 vf<madd_msub>.vv\t%0,%3,%4%p1
6591 vmv%m2r.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1"
6592 [(set_attr "type" "vfmuladd")
6593 (set_attr "mode" "<MODE>")
6594 (set_attr "merge_op_idx" "2")
6595 (set_attr "vl_op_idx" "5")
6596 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6597 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6598 (set (attr "avl_type_idx") (const_int 8))
6599 (set (attr "frm_mode")
6600 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6602 (define_insn "*pred_<macc_msac><mode>"
6603 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6604 (if_then_else:V_VLSF
6605 (unspec:<VM>
6606 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6607 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6608 (match_operand 6 "const_int_operand" " i, i, i, i")
6609 (match_operand 7 "const_int_operand" " i, i, i, i")
6610 (match_operand 8 "const_int_operand" " i, i, i, i")
6611 (match_operand 9 "const_int_operand" " i, i, i, i")
6612 (reg:SI VL_REGNUM)
6613 (reg:SI VTYPE_REGNUM)
6614 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6615 (plus_minus:V_VLSF
6616 (mult:V_VLSF
6617 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6618 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6619 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6620 (match_dup 4)))]
6621 "TARGET_VECTOR"
6622 "@
6623 vf<macc_msac>.vv\t%0,%2,%3%p1
6624 vmv%m4r.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
6625 vf<macc_msac>.vv\t%0,%2,%3%p1
6626 vmv%m4r.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1"
6627 [(set_attr "type" "vfmuladd")
6628 (set_attr "mode" "<MODE>")
6629 (set_attr "merge_op_idx" "4")
6630 (set_attr "vl_op_idx" "5")
6631 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6632 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6633 (set (attr "avl_type_idx") (const_int 8))
6634 (set (attr "frm_mode")
6635 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6637 (define_expand "@pred_mul_<optab><mode>_scalar"
6638 [(set (match_operand:V_VLSF 0 "register_operand")
6639 (if_then_else:V_VLSF
6640 (unspec:<VM>
6641 [(match_operand:<VM> 1 "vector_mask_operand")
6642 (match_operand 6 "vector_length_operand")
6643 (match_operand 7 "const_int_operand")
6644 (match_operand 8 "const_int_operand")
6645 (match_operand 9 "const_int_operand")
6646 (match_operand 10 "const_int_operand")
6647 (reg:SI VL_REGNUM)
6648 (reg:SI VTYPE_REGNUM)
6649 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6650 (plus_minus:V_VLSF
6651 (mult:V_VLSF
6652 (vec_duplicate:V_VLSF
6653 (match_operand:<VEL> 2 "register_operand"))
6654 (match_operand:V_VLSF 3 "register_operand"))
6655 (match_operand:V_VLSF 4 "register_operand"))
6656 (match_operand:V_VLSF 5 "register_operand")))]
6657 "TARGET_VECTOR"
6658 {})
6660 (define_insn "*pred_<madd_msub><mode>_scalar"
6661 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6662 (if_then_else:V_VLSF
6663 (unspec:<VM>
6664 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6665 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6666 (match_operand 6 "const_int_operand" " i, i, i, i")
6667 (match_operand 7 "const_int_operand" " i, i, i, i")
6668 (match_operand 8 "const_int_operand" " i, i, i, i")
6669 (match_operand 9 "const_int_operand" " i, i, i, i")
6670 (reg:SI VL_REGNUM)
6671 (reg:SI VTYPE_REGNUM)
6672 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6673 (plus_minus:V_VLSF
6674 (mult:V_VLSF
6675 (vec_duplicate:V_VLSF
6676 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6677 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr"))
6678 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6679 (match_dup 3)))]
6680 "TARGET_VECTOR"
6681 "@
6682 vf<madd_msub>.vf\t%0,%2,%4%p1
6683 vmv%m3r.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
6684 vf<madd_msub>.vf\t%0,%2,%4%p1
6685 vmv%m3r.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1"
6686 [(set_attr "type" "vfmuladd")
6687 (set_attr "mode" "<MODE>")
6688 (set_attr "merge_op_idx" "3")
6689 (set_attr "vl_op_idx" "5")
6690 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6691 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6692 (set (attr "avl_type_idx") (const_int 8))
6693 (set (attr "frm_mode")
6694 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6696 (define_insn "*pred_<macc_msac><mode>_scalar"
6697 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6698 (if_then_else:V_VLSF
6699 (unspec:<VM>
6700 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6701 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6702 (match_operand 6 "const_int_operand" " i, i, i, i")
6703 (match_operand 7 "const_int_operand" " i, i, i, i")
6704 (match_operand 8 "const_int_operand" " i, i, i, i")
6705 (match_operand 9 "const_int_operand" " i, i, i, i")
6706 (reg:SI VL_REGNUM)
6707 (reg:SI VTYPE_REGNUM)
6708 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6709 (plus_minus:V_VLSF
6710 (mult:V_VLSF
6711 (vec_duplicate:V_VLSF
6712 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6713 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6714 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6715 (match_dup 4)))]
6716 "TARGET_VECTOR"
6717 "@
6718 vf<macc_msac>.vf\t%0,%2,%3%p1
6719 vmv%m4r.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
6720 vf<macc_msac>.vf\t%0,%2,%3%p1
6721 vmv%m4r.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1"
6722 [(set_attr "type" "vfmuladd")
6723 (set_attr "mode" "<MODE>")
6724 (set_attr "merge_op_idx" "4")
6725 (set_attr "vl_op_idx" "5")
6726 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6727 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6728 (set (attr "avl_type_idx") (const_int 8))
6729 (set (attr "frm_mode")
6730 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6732 (define_expand "@pred_mul_neg_<optab><mode>"
6733 [(set (match_operand:V_VLSF 0 "register_operand")
6734 (if_then_else:V_VLSF
6735 (unspec:<VM>
6736 [(match_operand:<VM> 1 "vector_mask_operand")
6737 (match_operand 6 "vector_length_operand")
6738 (match_operand 7 "const_int_operand")
6739 (match_operand 8 "const_int_operand")
6740 (match_operand 9 "const_int_operand")
6741 (match_operand 10 "const_int_operand")
6742 (reg:SI VL_REGNUM)
6743 (reg:SI VTYPE_REGNUM)
6744 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6745 (plus_minus:V_VLSF
6746 (neg:V_VLSF
6747 (mult:V_VLSF
6748 (match_operand:V_VLSF 2 "register_operand")
6749 (match_operand:V_VLSF 3 "register_operand")))
6750 (match_operand:V_VLSF 4 "register_operand"))
6751 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6752 "TARGET_VECTOR"
6753 {
6754 riscv_vector::prepare_ternary_operands (operands);
6755 })
6757 (define_insn "*pred_mul_neg_<optab><mode>_undef"
6758 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6759 (if_then_else:V_VLSF
6760 (unspec:<VM>
6761 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6762 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6763 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6764 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6765 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6766 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6767 (reg:SI VL_REGNUM)
6768 (reg:SI VTYPE_REGNUM)
6769 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6770 (plus_minus:V_VLSF
6771 (neg:V_VLSF
6772 (mult:V_VLSF
6773 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6774 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr")))
6775 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6776 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6777 "TARGET_VECTOR"
6778 "@
6779 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6780 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6781 vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6782 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6783 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6784 vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1"
6785 [(set_attr "type" "vfmuladd")
6786 (set_attr "mode" "<MODE>")
6787 (set (attr "frm_mode")
6788 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6790 (define_insn "*pred_<nmsub_nmadd><mode>"
6791 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6792 (if_then_else:V_VLSF
6793 (unspec:<VM>
6794 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6795 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6796 (match_operand 6 "const_int_operand" " i, i, i, i")
6797 (match_operand 7 "const_int_operand" " i, i, i, i")
6798 (match_operand 8 "const_int_operand" " i, i, i, i")
6799 (match_operand 9 "const_int_operand" " i, i, i, i")
6800 (reg:SI VL_REGNUM)
6801 (reg:SI VTYPE_REGNUM)
6802 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6803 (plus_minus:V_VLSF
6804 (neg:V_VLSF
6805 (mult:V_VLSF
6806 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6807 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6808 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6809 (match_dup 2)))]
6810 "TARGET_VECTOR"
6811 "@
6812 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6813 vmv%m2r.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6814 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6815 vmv%m2r.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
6816 [(set_attr "type" "vfmuladd")
6817 (set_attr "mode" "<MODE>")
6818 (set_attr "merge_op_idx" "2")
6819 (set_attr "vl_op_idx" "5")
6820 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6821 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6822 (set (attr "avl_type_idx") (const_int 8))
6823 (set (attr "frm_mode")
6824 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6826 (define_insn "*pred_<nmsac_nmacc><mode>"
6827 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6828 (if_then_else:V_VLSF
6829 (unspec:<VM>
6830 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6831 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6832 (match_operand 6 "const_int_operand" " i, i, i, i")
6833 (match_operand 7 "const_int_operand" " i, i, i, i")
6834 (match_operand 8 "const_int_operand" " i, i, i, i")
6835 (match_operand 9 "const_int_operand" " i, i, i, i")
6836 (reg:SI VL_REGNUM)
6837 (reg:SI VTYPE_REGNUM)
6838 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6839 (plus_minus:V_VLSF
6840 (neg:V_VLSF
6841 (mult:V_VLSF
6842 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6843 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6844 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6845 (match_dup 4)))]
6846 "TARGET_VECTOR"
6847 "@
6848 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6849 vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6850 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6851 vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
6852 [(set_attr "type" "vfmuladd")
6853 (set_attr "mode" "<MODE>")
6854 (set_attr "merge_op_idx" "4")
6855 (set_attr "vl_op_idx" "5")
6856 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6857 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6858 (set (attr "avl_type_idx") (const_int 8))
6859 (set (attr "frm_mode")
6860 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6862 (define_expand "@pred_mul_neg_<optab><mode>_scalar"
6863 [(set (match_operand:V_VLSF 0 "register_operand")
6864 (if_then_else:V_VLSF
6865 (unspec:<VM>
6866 [(match_operand:<VM> 1 "vector_mask_operand")
6867 (match_operand 6 "vector_length_operand")
6868 (match_operand 7 "const_int_operand")
6869 (match_operand 8 "const_int_operand")
6870 (match_operand 9 "const_int_operand")
6871 (match_operand 10 "const_int_operand")
6872 (reg:SI VL_REGNUM)
6873 (reg:SI VTYPE_REGNUM)
6874 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6875 (plus_minus:V_VLSF
6876 (neg:V_VLSF
6877 (mult:V_VLSF
6878 (vec_duplicate:V_VLSF
6879 (match_operand:<VEL> 2 "register_operand"))
6880 (match_operand:V_VLSF 3 "register_operand")))
6881 (match_operand:V_VLSF 4 "register_operand"))
6882 (match_operand:V_VLSF 5 "register_operand")))]
6883 "TARGET_VECTOR"
6884 {})
6886 (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
6887 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6888 (if_then_else:V_VLSF
6889 (unspec:<VM>
6890 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6891 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6892 (match_operand 6 "const_int_operand" " i, i, i, i")
6893 (match_operand 7 "const_int_operand" " i, i, i, i")
6894 (match_operand 8 "const_int_operand" " i, i, i, i")
6895 (match_operand 9 "const_int_operand" " i, i, i, i")
6896 (reg:SI VL_REGNUM)
6897 (reg:SI VTYPE_REGNUM)
6898 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6899 (plus_minus:V_VLSF
6900 (neg:V_VLSF
6901 (mult:V_VLSF
6902 (vec_duplicate:V_VLSF
6903 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6904 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr")))
6905 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6906 (match_dup 3)))]
6907 "TARGET_VECTOR"
6908 "@
6909 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6910 vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6911 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6912 vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
6913 [(set_attr "type" "vfmuladd")
6914 (set_attr "mode" "<MODE>")
6915 (set_attr "merge_op_idx" "3")
6916 (set_attr "vl_op_idx" "5")
6917 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6918 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6919 (set (attr "avl_type_idx") (const_int 8))
6920 (set (attr "frm_mode")
6921 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6923 (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
6924 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6925 (if_then_else:V_VLSF
6926 (unspec:<VM>
6927 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6928 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6929 (match_operand 6 "const_int_operand" " i, i, i, i")
6930 (match_operand 7 "const_int_operand" " i, i, i, i")
6931 (match_operand 8 "const_int_operand" " i, i, i, i")
6932 (match_operand 9 "const_int_operand" " i, i, i, i")
6933 (reg:SI VL_REGNUM)
6934 (reg:SI VTYPE_REGNUM)
6935 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6936 (plus_minus:V_VLSF
6937 (neg:V_VLSF
6938 (mult:V_VLSF
6939 (vec_duplicate:V_VLSF
6940 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6941 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6942 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6943 (match_dup 4)))]
6944 "TARGET_VECTOR"
6945 "@
6946 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6947 vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6948 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6949 vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
6950 [(set_attr "type" "vfmuladd")
6951 (set_attr "mode" "<MODE>")
6952 (set_attr "merge_op_idx" "4")
6953 (set_attr "vl_op_idx" "5")
6954 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6955 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6956 (set (attr "avl_type_idx") (const_int 8))
6957 (set (attr "frm_mode")
6958 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6960 ;; -------------------------------------------------------------------------------
6961 ;; ---- Predicated floating-point unary operations
6962 ;; -------------------------------------------------------------------------------
6963 ;; Includes:
6964 ;; - 13.8 Vector Floating-Point Square-Root Instruction
6965 ;; - 13.9 Vector Floating-Point Reciprocal Square-Root Estimate Instruction
6966 ;; - 13.10 Vector Floating-Point Reciprocal Estimate Instruction
6967 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions (vfneg.v/vfabs.v)
6968 ;; - 13.14 Vector Floating-Point Classify Instruction
6969 ;; -------------------------------------------------------------------------------
6971 (define_insn "@pred_<optab><mode>"
6972 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6973 (if_then_else:V_VLSF
6974 (unspec:<VM>
6975 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6976 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6977 (match_operand 5 "const_int_operand" " i, i, i, i")
6978 (match_operand 6 "const_int_operand" " i, i, i, i")
6979 (match_operand 7 "const_int_operand" " i, i, i, i")
6980 (match_operand 8 "const_int_operand" " i, i, i, i")
6981 (reg:SI VL_REGNUM)
6982 (reg:SI VTYPE_REGNUM)
6983 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6984 (any_float_unop:V_VLSF
6985 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6986 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6987 "TARGET_VECTOR"
6988 "vf<insn>.v\t%0,%3%p1"
6989 [(set_attr "type" "<float_insn_type>")
6990 (set_attr "mode" "<MODE>")
6991 (set_attr "vl_op_idx" "4")
6992 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6993 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6994 (set (attr "avl_type_idx") (const_int 7))
6995 (set (attr "frm_mode")
6996 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6998 (define_insn "@pred_<optab><mode>"
6999 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
7000 (if_then_else:V_VLSF
7001 (unspec:<VM>
7002 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7003 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7004 (match_operand 5 "const_int_operand" " i, i, i, i")
7005 (match_operand 6 "const_int_operand" " i, i, i, i")
7006 (match_operand 7 "const_int_operand" " i, i, i, i")
7007 (reg:SI VL_REGNUM)
7008 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7009 (any_float_unop_nofrm:V_VLSF
7010 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
7011 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7012 "TARGET_VECTOR"
7013 "vf<insn>.v\t%0,%3%p1"
7014 [(set_attr "type" "<float_insn_type>")
7015 (set_attr "mode" "<MODE>")
7016 (set_attr "vl_op_idx" "4")
7017 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
7018 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7019 (set (attr "avl_type_idx") (const_int 7))])
7021 (define_insn "@pred_<misc_op><mode>"
7022 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
7023 (if_then_else:VF
7024 (unspec:<VM>
7025 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7026 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7027 (match_operand 5 "const_int_operand" " i, i, i, i")
7028 (match_operand 6 "const_int_operand" " i, i, i, i")
7029 (match_operand 7 "const_int_operand" " i, i, i, i")
7030 (reg:SI VL_REGNUM)
7031 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7032 (unspec:VF
7033 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
7034 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7035 "TARGET_VECTOR"
7036 "vf<misc_op>.v\t%0,%3%p1"
7037 [(set_attr "type" "<float_insn_type>")
7038 (set_attr "mode" "<MODE>")])
7040 (define_insn "@pred_<misc_frm_op><mode>"
7041 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
7042 (if_then_else:VF
7043 (unspec:<VM>
7044 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7045 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7046 (match_operand 5 "const_int_operand" " i, i, i, i")
7047 (match_operand 6 "const_int_operand" " i, i, i, i")
7048 (match_operand 7 "const_int_operand" " i, i, i, i")
7049 (match_operand 8 "const_int_operand" " i, i, i, i")
7050 (reg:SI VL_REGNUM)
7051 (reg:SI VTYPE_REGNUM)
7052 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7053 (unspec:VF
7054 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM)
7055 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7056 "TARGET_VECTOR"
7057 "vf<misc_frm_op>.v\t%0,%3%p1"
7058 [(set_attr "type" "<float_frm_insn_type>")
7059 (set_attr "mode" "<MODE>")
7060 (set (attr "frm_mode")
7061 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7063 (define_insn "@pred_class<mode>"
7064 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7065 (if_then_else:<VCONVERT>
7066 (unspec:<VM>
7067 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7068 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7069 (match_operand 5 "const_int_operand" " i, i, i, i")
7070 (match_operand 6 "const_int_operand" " i, i, i, i")
7071 (match_operand 7 "const_int_operand" " i, i, i, i")
7072 (reg:SI VL_REGNUM)
7073 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7074 (unspec:<VCONVERT>
7075 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
7076 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7077 "TARGET_VECTOR"
7078 "vfclass.v\t%0,%3%p1"
7079 [(set_attr "type" "vfclass")
7080 (set_attr "mode" "<MODE>")])
7082 ;; -------------------------------------------------------------------------------
7083 ;; ---- Predicated floating-point widen binary operations
7084 ;; -------------------------------------------------------------------------------
7085 ;; Includes:
7086 ;; - 13.3 Vector Widening Floating-Point Add/Subtract Instructions
7087 ;; - 13.5 Vector Widening Floating-Point Multiply
7088 ;; -------------------------------------------------------------------------------
7090 ;; Vector Widening Add/Subtract/Multiply.
7091 (define_insn "@pred_dual_widen_<optab><mode>"
7092 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7093 (if_then_else:VWEXTF
7094 (unspec:<VM>
7095 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7096 (match_operand 5 "vector_length_operand" " rK, rK")
7097 (match_operand 6 "const_int_operand" " i, i")
7098 (match_operand 7 "const_int_operand" " i, i")
7099 (match_operand 8 "const_int_operand" " i, i")
7100 (match_operand 9 "const_int_operand" " i, i")
7101 (reg:SI VL_REGNUM)
7102 (reg:SI VTYPE_REGNUM)
7103 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7104 (any_widen_binop:VWEXTF
7105 (float_extend:VWEXTF
7106 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7107 (float_extend:VWEXTF
7108 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7109 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7110 "TARGET_VECTOR"
7111 "vfw<insn>.vv\t%0,%3,%4%p1"
7112 [(set_attr "type" "vf<widen_binop_insn_type>")
7113 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7114 (set (attr "frm_mode")
7115 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7117 (define_insn "@pred_dual_widen_<optab><mode>_scalar"
7118 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7119 (if_then_else:VWEXTF
7120 (unspec:<VM>
7121 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7122 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7123 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7124 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7125 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7126 (match_operand 9 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7127 (reg:SI VL_REGNUM)
7128 (reg:SI VTYPE_REGNUM)
7129 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7130 (any_widen_binop:VWEXTF
7131 (float_extend:VWEXTF
7132 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
7133 (float_extend:VWEXTF
7134 (vec_duplicate:<V_DOUBLE_TRUNC>
7135 (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f, f, f, f, f, f, f, f, f, f, f"))))
7136 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7137 "TARGET_VECTOR"
7138 "vfw<insn>.vf\t%0,%3,%4%p1"
7139 [(set_attr "type" "vf<widen_binop_insn_type>")
7140 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7141 (set (attr "frm_mode")
7142 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7143 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7145 (define_insn "@pred_single_widen_add<mode>"
7146 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
7147 (if_then_else:VWEXTF
7148 (unspec:<VM>
7149 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
7150 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7151 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7152 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7153 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7154 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7155 (reg:SI VL_REGNUM)
7156 (reg:SI VTYPE_REGNUM)
7157 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7158 (plus:VWEXTF
7159 (float_extend:VWEXTF
7160 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr"))
7161 (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr"))
7162 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
7163 "TARGET_VECTOR"
7164 "vfwadd.wv\t%0,%3,%4%p1"
7165 [(set_attr "type" "vfwalu")
7166 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7167 (set (attr "frm_mode")
7168 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7169 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
7171 (define_insn "@pred_single_widen_sub<mode>"
7172 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, &vr, &vr, ?&vr, ?&vr")
7173 (if_then_else:VWEXTF
7174 (unspec:<VM>
7175 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1,vmWc1,vmWc1")
7176 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7177 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7178 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7179 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7180 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7181 (reg:SI VL_REGNUM)
7182 (reg:SI VTYPE_REGNUM)
7183 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7184 (minus:VWEXTF
7185 (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, vr, 0, 0, vr, vr")
7186 (float_extend:VWEXTF
7187 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr, vr, vr")))
7188 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0, vu, 0")))]
7189 "TARGET_VECTOR"
7190 "vfwsub.wv\t%0,%3,%4%p1"
7191 [(set_attr "type" "vfwalu")
7192 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7193 (set (attr "frm_mode")
7194 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7195 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,W0,W0,none,none")])
7197 (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
7198 [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr")
7199 (if_then_else:VWEXTF
7200 (unspec:<VM>
7201 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7202 (match_operand 5 "vector_length_operand" " rK, rK")
7203 (match_operand 6 "const_int_operand" " i, i")
7204 (match_operand 7 "const_int_operand" " i, i")
7205 (match_operand 8 "const_int_operand" " i, i")
7206 (match_operand 9 "const_int_operand" " i, i")
7207 (reg:SI VL_REGNUM)
7208 (reg:SI VTYPE_REGNUM)
7209 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7210 (plus_minus:VWEXTF
7211 (match_operand:VWEXTF 3 "register_operand" " vr, vr")
7212 (float_extend:VWEXTF
7213 (vec_duplicate:<V_DOUBLE_TRUNC>
7214 (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
7215 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7216 "TARGET_VECTOR"
7217 "vfw<insn>.wf\t%0,%3,%4%p1"
7218 [(set_attr "type" "vf<widen_binop_insn_type>")
7219 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7220 (set (attr "frm_mode")
7221 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7223 ;; -------------------------------------------------------------------------------
7224 ;; ---- Predicated widen floating-point ternary operations
7225 ;; -------------------------------------------------------------------------------
7226 ;; Includes:
7227 ;; - 13.7 Vector Widening Floating-Point Fused Multiply-Add Instructions
7228 ;; -------------------------------------------------------------------------------
7230 (define_insn "@pred_widen_mul_<optab><mode>"
7231 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7232 (if_then_else:VWEXTF
7233 (unspec:<VM>
7234 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7235 (match_operand 5 "vector_length_operand" " rK")
7236 (match_operand 6 "const_int_operand" " i")
7237 (match_operand 7 "const_int_operand" " i")
7238 (match_operand 8 "const_int_operand" " i")
7239 (match_operand 9 "const_int_operand" " i")
7240 (reg:SI VL_REGNUM)
7241 (reg:SI VTYPE_REGNUM)
7242 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7243 (plus_minus:VWEXTF
7244 (mult:VWEXTF
7245 (float_extend:VWEXTF
7246 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7247 (float_extend:VWEXTF
7248 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7249 (match_operand:VWEXTF 2 "register_operand" " 0"))
7250 (match_dup 2)))]
7251 "TARGET_VECTOR"
7252 "vfw<macc_msac>.vv\t%0,%3,%4%p1"
7253 [(set_attr "type" "vfwmuladd")
7254 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7255 (set (attr "frm_mode")
7256 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7258 (define_insn "@pred_widen_mul_<optab><mode>_scalar"
7259 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
7260 (if_then_else:VWEXTF
7261 (unspec:<VM>
7262 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
7263 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
7264 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
7265 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
7266 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
7267 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i")
7268 (reg:SI VL_REGNUM)
7269 (reg:SI VTYPE_REGNUM)
7270 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7271 (plus_minus:VWEXTF
7272 (mult:VWEXTF
7273 (float_extend:VWEXTF
7274 (vec_duplicate:<V_DOUBLE_TRUNC>
7275 (match_operand:<VSUBEL> 3 "register_operand" " f, f, f, f, f, f, f")))
7276 (float_extend:VWEXTF
7277 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr")))
7278 (match_operand:VWEXTF 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
7279 (match_dup 2)))]
7280 "TARGET_VECTOR"
7281 "vfw<macc_msac>.vf\t%0,%3,%4%p1"
7282 [(set_attr "type" "vfwmuladd")
7283 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7284 (set (attr "frm_mode")
7285 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7286 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
7288 (define_insn "@pred_widen_mul_neg_<optab><mode>"
7289 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7290 (if_then_else:VWEXTF
7291 (unspec:<VM>
7292 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7293 (match_operand 5 "vector_length_operand" " rK")
7294 (match_operand 6 "const_int_operand" " i")
7295 (match_operand 7 "const_int_operand" " i")
7296 (match_operand 8 "const_int_operand" " i")
7297 (match_operand 9 "const_int_operand" " i")
7298 (reg:SI VL_REGNUM)
7299 (reg:SI VTYPE_REGNUM)
7300 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7301 (plus_minus:VWEXTF
7302 (neg:VWEXTF
7303 (mult:VWEXTF
7304 (float_extend:VWEXTF
7305 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7306 (float_extend:VWEXTF
7307 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7308 (match_operand:VWEXTF 2 "register_operand" " 0"))
7309 (match_dup 2)))]
7310 "TARGET_VECTOR"
7311 "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
7312 [(set_attr "type" "vfwmuladd")
7313 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7314 (set (attr "frm_mode")
7315 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7317 (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
7318 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, ?&vr")
7319 (if_then_else:VWEXTF
7320 (unspec:<VM>
7321 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1,vmWc1")
7322 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK")
7323 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i")
7324 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i")
7325 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i")
7326 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i")
7327 (reg:SI VL_REGNUM)
7328 (reg:SI VTYPE_REGNUM)
7329 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7330 (plus_minus:VWEXTF
7331 (neg:VWEXTF
7332 (mult:VWEXTF
7333 (float_extend:VWEXTF
7334 (vec_duplicate:<V_DOUBLE_TRUNC>
7335 (match_operand:<VSUBEL> 3 "register_operand" " f, f, f, f, f, f, f")))
7336 (float_extend:VWEXTF
7337 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" "W21,W21,W42,W42,W84,W84, vr"))))
7338 (match_operand:VWEXTF 2 "register_operand" " 0, 0, 0, 0, 0, 0, 0"))
7339 (match_dup 2)))]
7340 "TARGET_VECTOR"
7341 "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
7342 [(set_attr "type" "vfwmuladd")
7343 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7344 (set (attr "frm_mode")
7345 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))
7346 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none")])
7348 ;; -------------------------------------------------------------------------------
7349 ;; ---- Predicated floating-point comparison operations
7350 ;; -------------------------------------------------------------------------------
7351 ;; Includes:
7352 ;; - 13.13 Vector Floating-Point Compare Instructions
7353 ;; -------------------------------------------------------------------------------
7355 (define_expand "@pred_cmp<mode>"
7356 [(set (match_operand:<VM> 0 "register_operand")
7357 (if_then_else:<VM>
7358 (unspec:<VM>
7359 [(match_operand:<VM> 1 "vector_mask_operand")
7360 (match_operand 6 "vector_length_operand")
7361 (match_operand 7 "const_int_operand")
7362 (match_operand 8 "const_int_operand")
7363 (reg:SI VL_REGNUM)
7364 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7365 (match_operator:<VM> 3 "signed_order_operator"
7366 [(match_operand:V_VLSF 4 "register_operand")
7367 (match_operand:V_VLSF 5 "register_operand")])
7368 (match_operand:<VM> 2 "vector_merge_operand")))]
7369 "TARGET_VECTOR"
7370 {})
7372 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7373 (define_insn "*pred_cmp<mode>"
7374 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
7375 (if_then_else:<VM>
7376 (unspec:<VM>
7377 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
7378 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
7379 (match_operand 7 "const_int_operand" " i, i, i, i")
7380 (match_operand 8 "const_int_operand" " i, i, i, i")
7381 (reg:SI VL_REGNUM)
7382 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7383 (match_operator:<VM> 3 "signed_order_operator"
7384 [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")
7385 (match_operand:V_VLSF 5 "register_operand" " vr, vr, vr, vr")])
7386 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7387 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7388 "vmf%B3.vv\t%0,%4,%5%p1"
7389 [(set_attr "type" "vfcmp")
7390 (set_attr "mode" "<MODE>")
7391 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
7393 (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
7394 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7395 (if_then_else:<VM>
7396 (unspec:<VM>
7397 [(match_operand:<VM> 1 "register_operand" " 0")
7398 (match_operand 5 "vector_length_operand" " rK")
7399 (match_operand 6 "const_int_operand" " i")
7400 (match_operand 7 "const_int_operand" " i")
7401 (reg:SI VL_REGNUM)
7402 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7403 (match_operator:<VM> 2 "signed_order_operator"
7404 [(match_operand:V_VLSF 3 "register_operand" " vr")
7405 (match_operand:V_VLSF 4 "register_operand" " vr")])
7406 (match_dup 1)))]
7407 "TARGET_VECTOR"
7408 "vmf%B2.vv\t%0,%3,%4,v0.t"
7409 [(set_attr "type" "vfcmp")
7410 (set_attr "mode" "<MODE>")
7411 (set_attr "merge_op_idx" "1")
7412 (set_attr "vl_op_idx" "5")
7413 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7414 (set (attr "avl_type_idx") (const_int 7))])
7416 ;; We use early-clobber for source LMUL > dest LMUL.
7417 (define_insn "*pred_cmp<mode>_narrow"
7418 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
7419 (if_then_else:<VM>
7420 (unspec:<VM>
7421 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7422 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
7423 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7424 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7425 (reg:SI VL_REGNUM)
7426 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7427 (match_operator:<VM> 3 "signed_order_operator"
7428 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
7429 (match_operand:V_VLSF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
7430 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
7431 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7432 "vmf%B3.vv\t%0,%4,%5%p1"
7433 [(set_attr "type" "vfcmp")
7434 (set_attr "mode" "<MODE>")
7435 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
7437 (define_expand "@pred_cmp<mode>_scalar"
7438 [(set (match_operand:<VM> 0 "register_operand")
7439 (if_then_else:<VM>
7440 (unspec:<VM>
7441 [(match_operand:<VM> 1 "vector_mask_operand")
7442 (match_operand 6 "vector_length_operand")
7443 (match_operand 7 "const_int_operand")
7444 (match_operand 8 "const_int_operand")
7445 (reg:SI VL_REGNUM)
7446 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7447 (match_operator:<VM> 3 "signed_order_operator"
7448 [(match_operand:V_VLSF 4 "register_operand")
7449 (vec_duplicate:V_VLSF
7450 (match_operand:<VEL> 5 "register_operand"))])
7451 (match_operand:<VM> 2 "vector_merge_operand")))]
7452 "TARGET_VECTOR"
7453 {})
7455 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
7456 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7457 (if_then_else:<VM>
7458 (unspec:<VM>
7459 [(match_operand:<VM> 1 "register_operand" " 0")
7460 (match_operand 5 "vector_length_operand" " rK")
7461 (match_operand 6 "const_int_operand" " i")
7462 (match_operand 7 "const_int_operand" " i")
7463 (reg:SI VL_REGNUM)
7464 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7465 (match_operator:<VM> 2 "signed_order_operator"
7466 [(match_operand:V_VLSF 3 "register_operand" " vr")
7467 (vec_duplicate:V_VLSF
7468 (match_operand:<VEL> 4 "register_operand" " f"))])
7469 (match_dup 1)))]
7470 "TARGET_VECTOR"
7471 "vmf%B2.vf\t%0,%3,%4,v0.t"
7472 [(set_attr "type" "vfcmp")
7473 (set_attr "mode" "<MODE>")
7474 (set_attr "merge_op_idx" "1")
7475 (set_attr "vl_op_idx" "5")
7476 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7477 (set (attr "avl_type_idx") (const_int 7))])
7479 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7480 (define_insn "*pred_cmp<mode>_scalar"
7481 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
7482 (if_then_else:<VM>
7483 (unspec:<VM>
7484 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
7485 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
7486 (match_operand 7 "const_int_operand" " i, i, i, i")
7487 (match_operand 8 "const_int_operand" " i, i, i, i")
7488 (reg:SI VL_REGNUM)
7489 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7490 (match_operator:<VM> 3 "signed_order_operator"
7491 [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")
7492 (vec_duplicate:V_VLSF
7493 (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))])
7494 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7495 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7496 "vmf%B3.vf\t%0,%4,%5%p1"
7497 [(set_attr "type" "vfcmp")
7498 (set_attr "mode" "<MODE>")
7499 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
7501 ;; We use early-clobber for source LMUL > dest LMUL.
7502 (define_insn "*pred_cmp<mode>_scalar_narrow"
7503 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7504 (if_then_else:<VM>
7505 (unspec:<VM>
7506 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7507 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7508 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7509 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7510 (reg:SI VL_REGNUM)
7511 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7512 (match_operator:<VM> 3 "signed_order_operator"
7513 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")
7514 (vec_duplicate:V_VLSF
7515 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
7516 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7517 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7518 "vmf%B3.vf\t%0,%4,%5%p1"
7519 [(set_attr "type" "vfcmp")
7520 (set_attr "mode" "<MODE>")
7521 (set_attr "spec_restriction" "none,thv,thv,none,none")])
7523 (define_expand "@pred_eqne<mode>_scalar"
7524 [(set (match_operand:<VM> 0 "register_operand")
7525 (if_then_else:<VM>
7526 (unspec:<VM>
7527 [(match_operand:<VM> 1 "vector_mask_operand")
7528 (match_operand 6 "vector_length_operand")
7529 (match_operand 7 "const_int_operand")
7530 (match_operand 8 "const_int_operand")
7531 (reg:SI VL_REGNUM)
7532 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7533 (match_operator:<VM> 3 "equality_operator"
7534 [(vec_duplicate:V_VLSF
7535 (match_operand:<VEL> 5 "register_operand"))
7536 (match_operand:V_VLSF 4 "register_operand")])
7537 (match_operand:<VM> 2 "vector_merge_operand")))]
7538 "TARGET_VECTOR"
7539 {})
7541 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
7542 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7543 (if_then_else:<VM>
7544 (unspec:<VM>
7545 [(match_operand:<VM> 1 "register_operand" " 0")
7546 (match_operand 5 "vector_length_operand" " rK")
7547 (match_operand 6 "const_int_operand" " i")
7548 (match_operand 7 "const_int_operand" " i")
7549 (reg:SI VL_REGNUM)
7550 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7551 (match_operator:<VM> 2 "equality_operator"
7552 [(vec_duplicate:V_VLSF
7553 (match_operand:<VEL> 4 "register_operand" " f"))
7554 (match_operand:V_VLSF 3 "register_operand" " vr")])
7555 (match_dup 1)))]
7556 "TARGET_VECTOR"
7557 "vmf%B2.vf\t%0,%3,%4,v0.t"
7558 [(set_attr "type" "vfcmp")
7559 (set_attr "mode" "<MODE>")
7560 (set_attr "merge_op_idx" "1")
7561 (set_attr "vl_op_idx" "5")
7562 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7563 (set (attr "avl_type_idx") (const_int 7))])
7565 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7566 (define_insn "*pred_eqne<mode>_scalar"
7567 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
7568 (if_then_else:<VM>
7569 (unspec:<VM>
7570 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
7571 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
7572 (match_operand 7 "const_int_operand" " i, i, i, i")
7573 (match_operand 8 "const_int_operand" " i, i, i, i")
7574 (reg:SI VL_REGNUM)
7575 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7576 (match_operator:<VM> 3 "equality_operator"
7577 [(vec_duplicate:V_VLSF
7578 (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))
7579 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")])
7580 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7581 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7582 "vmf%B3.vf\t%0,%4,%5%p1"
7583 [(set_attr "type" "vfcmp")
7584 (set_attr "mode" "<MODE>")
7585 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
7587 ;; We use early-clobber for source LMUL > dest LMUL.
7588 (define_insn "*pred_eqne<mode>_scalar_narrow"
7589 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7590 (if_then_else:<VM>
7591 (unspec:<VM>
7592 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7593 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7594 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7595 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7596 (reg:SI VL_REGNUM)
7597 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7598 (match_operator:<VM> 3 "equality_operator"
7599 [(vec_duplicate:V_VLSF
7600 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
7601 (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")])
7602 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7603 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7604 "vmf%B3.vf\t%0,%4,%5%p1"
7605 [(set_attr "type" "vfcmp")
7606 (set_attr "mode" "<MODE>")
7607 (set_attr "spec_restriction" "none,thv,thv,none,none")])
7609 ;; -------------------------------------------------------------------------------
7610 ;; ---- Predicated floating-point merge
7611 ;; -------------------------------------------------------------------------------
7612 ;; Includes:
7613 ;; - 13.15 Vector Floating-Point Merge Instruction
7614 ;; -------------------------------------------------------------------------------
7616 (define_insn "@pred_merge<mode>_scalar"
7617 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd")
7618 (if_then_else:V_VLSF
7619 (unspec:<VM>
7620 [(match_operand 5 "vector_length_operand" " rK,rK")
7621 (match_operand 6 "const_int_operand" " i, i")
7622 (match_operand 7 "const_int_operand" " i, i")
7623 (reg:SI VL_REGNUM)
7624 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7625 (vec_merge:V_VLSF
7626 (vec_duplicate:V_VLSF
7627 (match_operand:<VEL> 3 "register_operand" " f, f"))
7628 (match_operand:V_VLSF 2 "register_operand" " vr,vr")
7629 (match_operand:<VM> 4 "register_operand" " vm,vm"))
7630 (match_operand:V_VLSF 1 "vector_merge_operand" " vu, 0")))]
7631 "TARGET_VECTOR"
7632 "vfmerge.vfm\t%0,%2,%3,%4"
7633 [(set_attr "type" "vfmerge")
7634 (set_attr "mode" "<MODE>")])
7636 ;; -------------------------------------------------------------------------------
7637 ;; ---- Predicated floating-point conversions
7638 ;; -------------------------------------------------------------------------------
7639 ;; Includes:
7640 ;; - 13.17 Single-Width Floating-Point/Integer Type-Convert Instructions
7641 ;; -------------------------------------------------------------------------------
7643 (define_insn "@pred_fcvt_x<v_su>_f<mode>"
7644 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7645 (if_then_else:<VCONVERT>
7646 (unspec:<VM>
7647 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7648 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7649 (match_operand 5 "const_int_operand" " i, i, i, i")
7650 (match_operand 6 "const_int_operand" " i, i, i, i")
7651 (match_operand 7 "const_int_operand" " i, i, i, i")
7652 (match_operand 8 "const_int_operand" " i, i, i, i")
7653 (reg:SI VL_REGNUM)
7654 (reg:SI VTYPE_REGNUM)
7655 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7656 (unspec:<VCONVERT>
7657 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
7658 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7659 "TARGET_VECTOR"
7660 "vfcvt.x<v_su>.f.v\t%0,%3%p1"
7661 [(set_attr "type" "vfcvtftoi")
7662 (set_attr "mode" "<MODE>")
7663 (set (attr "frm_mode")
7664 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7666 (define_insn "@pred_<fix_cvt><mode>"
7667 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7668 (if_then_else:<VCONVERT>
7669 (unspec:<VM>
7670 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7671 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7672 (match_operand 5 "const_int_operand" " i, i, i, i")
7673 (match_operand 6 "const_int_operand" " i, i, i, i")
7674 (match_operand 7 "const_int_operand" " i, i, i, i")
7675 (reg:SI VL_REGNUM)
7676 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7677 (any_fix:<VCONVERT>
7678 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
7679 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7680 "TARGET_VECTOR"
7681 "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
7682 [(set_attr "type" "vfcvtftoi")
7683 (set_attr "mode" "<MODE>")])
7685 (define_insn "@pred_<float_cvt><mode>"
7686 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
7687 (if_then_else:V_VLSF
7688 (unspec:<VM>
7689 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7690 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7691 (match_operand 5 "const_int_operand" " i, i, i, i")
7692 (match_operand 6 "const_int_operand" " i, i, i, i")
7693 (match_operand 7 "const_int_operand" " i, i, i, i")
7694 (match_operand 8 "const_int_operand" " i, i, i, i")
7695 (reg:SI VL_REGNUM)
7696 (reg:SI VTYPE_REGNUM)
7697 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7698 (any_float:V_VLSF
7699 (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
7700 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7701 "TARGET_VECTOR"
7702 "vfcvt.f.x<u>.v\t%0,%3%p1"
7703 [(set_attr "type" "vfcvtitof")
7704 (set_attr "mode" "<MODE>")
7705 (set (attr "frm_mode")
7706 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7708 ;; -------------------------------------------------------------------------------
7709 ;; ---- Predicated floating-point widen conversions
7710 ;; -------------------------------------------------------------------------------
7711 ;; Includes:
7712 ;; - 13.18 Widening Floating-Point/Integer Type-Convert Instructions
7713 ;; -------------------------------------------------------------------------------
7715 (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
7716 [(set (match_operand:VWCONVERTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7717 (if_then_else:VWCONVERTI
7718 (unspec:<VM>
7719 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7720 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7721 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7722 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7723 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7724 (match_operand 8 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7725 (reg:SI VL_REGNUM)
7726 (reg:SI VTYPE_REGNUM)
7727 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7728 (unspec:VWCONVERTI
7729 [(match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr")] VFCVTS)
7730 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7731 "TARGET_VECTOR"
7732 "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
7733 [(set_attr "type" "vfwcvtftoi")
7734 (set_attr "mode" "<VNCONVERT>")
7735 (set (attr "frm_mode")
7736 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7737 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7739 (define_insn "@pred_widen_<fix_cvt><mode>"
7740 [(set (match_operand:VWCONVERTI 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7741 (if_then_else:VWCONVERTI
7742 (unspec:<VM>
7743 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7744 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7745 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7746 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7747 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7748 (reg:SI VL_REGNUM)
7749 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7750 (any_fix:VWCONVERTI
7751 (match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
7752 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7753 "TARGET_VECTOR"
7754 "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
7755 [(set_attr "type" "vfwcvtftoi")
7756 (set_attr "mode" "<VNCONVERT>")
7757 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7759 (define_insn "@pred_widen_<float_cvt><mode>"
7760 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7761 (if_then_else:V_VLSF
7762 (unspec:<VM>
7763 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7764 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7765 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7766 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7767 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7768 (reg:SI VL_REGNUM)
7769 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7770 (any_float:V_VLSF
7771 (match_operand:<VNCONVERT> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
7772 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7773 "TARGET_VECTOR"
7774 "vfwcvt.f.x<u>.v\t%0,%3%p1"
7775 [(set_attr "type" "vfwcvtitof")
7776 (set_attr "mode" "<VNCONVERT>")
7777 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7779 (define_insn "@pred_extend<mode>"
7780 [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, vd, vr, ?&vr, ?&vr")
7781 (if_then_else:VWEXTF_ZVFHMIN
7782 (unspec:<VM>
7783 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1, vm,Wc1,vmWc1,vmWc1")
7784 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
7785 (match_operand 5 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7786 (match_operand 6 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7787 (match_operand 7 "const_int_operand" "i, i, i, i, i, i, i, i, i, i, i, i, i, i")
7788 (reg:SI VL_REGNUM)
7789 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7790 (float_extend:VWEXTF_ZVFHMIN
7791 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84, vr, vr"))
7792 (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, vu, 0, 0, vu, vu, 0, 0, vu, vu, 0, 0, vu, 0")))]
7793 "TARGET_VECTOR"
7794 "vfwcvt.f.f.v\t%0,%3%p1"
7795 [(set_attr "type" "vfwcvtftof")
7796 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7797 (set_attr "group_overlap" "W21,W21,W21,W21,W42,W42,W42,W42,W84,W84,W84,W84,none,none")])
7799 ;; -------------------------------------------------------------------------------
7800 ;; ---- Predicated floating-point narrow conversions
7801 ;; -------------------------------------------------------------------------------
7802 ;; Includes:
7803 ;; - 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
7804 ;; -------------------------------------------------------------------------------
7806 (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
7807 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7808 (if_then_else:<VNCONVERT>
7809 (unspec:<VM>
7810 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7811 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7812 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7813 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7814 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7815 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7816 (reg:SI VL_REGNUM)
7817 (reg:SI VTYPE_REGNUM)
7818 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7819 (unspec:<VNCONVERT>
7820 [(match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
7821 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7822 "TARGET_VECTOR"
7823 "vfncvt.x<v_su>.f.w\t%0,%3%p1"
7824 [(set_attr "type" "vfncvtftoi")
7825 (set_attr "mode" "<VNCONVERT>")
7826 (set (attr "frm_mode")
7827 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7828 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7830 (define_insn "@pred_narrow_<fix_cvt><mode>"
7831 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7832 (if_then_else:<VNCONVERT>
7833 (unspec:<VM>
7834 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7835 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7836 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7837 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7838 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7839 (reg:SI VL_REGNUM)
7840 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7841 (any_fix:<VNCONVERT>
7842 (match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7843 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7844 "TARGET_VECTOR"
7845 "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
7846 [(set_attr "type" "vfncvtftoi")
7847 (set_attr "mode" "<VNCONVERT>")])
7849 (define_insn "@pred_narrow_<float_cvt><mode>"
7850 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7851 (if_then_else:<VNCONVERT>
7852 (unspec:<VM>
7853 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7854 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7855 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7856 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7857 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7858 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7859 (reg:SI VL_REGNUM)
7860 (reg:SI VTYPE_REGNUM)
7861 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7862 (any_float:<VNCONVERT>
7863 (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7864 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7865 "TARGET_VECTOR"
7866 "vfncvt.f.x<u>.w\t%0,%3%p1"
7867 [(set_attr "type" "vfncvtitof")
7868 (set_attr "mode" "<VNCONVERT>")
7869 (set (attr "frm_mode")
7870 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7871 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7873 (define_insn "@pred_trunc<mode>"
7874 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7875 (if_then_else:<V_DOUBLE_TRUNC>
7876 (unspec:<VM>
7877 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7878 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7879 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7880 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7881 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7882 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7883 (reg:SI VL_REGNUM)
7884 (reg:SI VTYPE_REGNUM)
7885 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7886 (float_truncate:<V_DOUBLE_TRUNC>
7887 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7888 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7889 "TARGET_VECTOR"
7890 "vfncvt.f.f.w\t%0,%3%p1"
7891 [(set_attr "type" "vfncvtftof")
7892 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7893 (set (attr "frm_mode")
7894 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7895 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7897 (define_insn "@pred_rod_trunc<mode>"
7898 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7899 (if_then_else:<V_DOUBLE_TRUNC>
7900 (unspec:<VM>
7901 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7902 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7903 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7904 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7905 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7906 (reg:SI VL_REGNUM)
7907 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7908 (unspec:<V_DOUBLE_TRUNC>
7909 [(float_truncate:<V_DOUBLE_TRUNC>
7910 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
7911 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7912 "TARGET_VECTOR"
7913 "vfncvt.rod.f.f.w\t%0,%3%p1"
7914 [(set_attr "type" "vfncvtftof")
7915 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
7917 ;; -------------------------------------------------------------------------------
7918 ;; ---- Predicated reduction operations
7919 ;; -------------------------------------------------------------------------------
7920 ;; Includes:
7921 ;; - 14.1 Vector Single-Width Integer Reduction Instructions
7922 ;; - 14.2 Vector Widening Integer Reduction Instructions
7923 ;; - 14.3 Vector Single-Width Floating-Point Reduction Instructions
7924 ;; - 14.4 Vector Widening Floating-Point Reduction Instructions
7925 ;; -------------------------------------------------------------------------------
7927 ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
7928 (define_insn "@pred_<reduc_op><mode>"
7929 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7930 (unspec:<V_LMUL1>
7931 [(unspec:<VM>
7932 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7933 (match_operand 5 "vector_length_operand" " rK, rK")
7934 (match_operand 6 "const_int_operand" " i, i")
7935 (match_operand 7 "const_int_operand" " i, i")
7936 (reg:SI VL_REGNUM)
7937 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7938 (unspec:<V_LMUL1> [
7939 (match_operand:V_VLSI 3 "register_operand" " vr, vr")
7940 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7941 ] ANY_REDUC)
7942 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7943 "TARGET_VECTOR"
7944 "v<reduc_op>.vs\t%0,%3,%4%p1"
7945 [(set_attr "type" "vired")
7946 (set_attr "mode" "<MODE>")])
7948 ;; Integer Widen Reduction Sum (vwredsum[u].vs)
7949 (define_insn "@pred_<reduc_op><mode>"
7950 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr, vr")
7951 (unspec:<V_EXT_LMUL1>
7952 [(unspec:<VM>
7953 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7954 (match_operand 5 "vector_length_operand" " rK, rK")
7955 (match_operand 6 "const_int_operand" " i, i")
7956 (match_operand 7 "const_int_operand" " i, i")
7957 (reg:SI VL_REGNUM)
7958 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7959 (unspec:<V_EXT_LMUL1> [
7960 (match_operand:VI_QHS 3 "register_operand" " vr, vr")
7961 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
7962 ] ANY_WREDUC)
7963 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7964 "TARGET_VECTOR"
7965 "v<reduc_op>.vs\t%0,%3,%4%p1"
7966 [(set_attr "type" "viwred")
7967 (set_attr "mode" "<MODE>")])
7969 ;; Float Reduction (vfred(max|min).vs)
7970 (define_insn "@pred_<reduc_op><mode>"
7971 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7972 (unspec:<V_LMUL1>
7973 [(unspec:<VM>
7974 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7975 (match_operand 5 "vector_length_operand" " rK, rK")
7976 (match_operand 6 "const_int_operand" " i, i")
7977 (match_operand 7 "const_int_operand" " i, i")
7978 (reg:SI VL_REGNUM)
7979 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7980 (unspec:<V_LMUL1> [
7981 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7982 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7983 ] ANY_FREDUC)
7984 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7985 "TARGET_VECTOR"
7986 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7987 [(set_attr "type" "vfredu")
7988 (set_attr "mode" "<MODE>")])
7990 ;; Float Reduction Sum (vfred[ou]sum.vs)
7991 (define_insn "@pred_<reduc_op><mode>"
7992 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
7993 (unspec:<V_LMUL1>
7994 [(unspec:<VM>
7995 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7996 (match_operand 5 "vector_length_operand" " rK, rK")
7997 (match_operand 6 "const_int_operand" " i, i")
7998 (match_operand 7 "const_int_operand" " i, i")
7999 (match_operand 8 "const_int_operand" " i, i")
8000 (reg:SI VL_REGNUM)
8001 (reg:SI VTYPE_REGNUM)
8002 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
8003 (unspec:<V_LMUL1> [
8004 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
8005 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
8006 ] ANY_FREDUC_SUM)
8007 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
8008 "TARGET_VECTOR"
8009 "vf<reduc_op>.vs\t%0,%3,%4%p1"
8010 [(set_attr "type" "vfred<order>")
8011 (set_attr "mode" "<MODE>")
8012 (set (attr "frm_mode")
8013 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
8015 ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
8016 (define_insn "@pred_<reduc_op><mode>"
8017 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr, vr")
8018 (unspec:<V_EXT_LMUL1>
8019 [(unspec:<VM>
8020 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8021 (match_operand 5 "vector_length_operand" " rK, rK")
8022 (match_operand 6 "const_int_operand" " i, i")
8023 (match_operand 7 "const_int_operand" " i, i")
8024 (match_operand 8 "const_int_operand" " i, i")
8025 (reg:SI VL_REGNUM)
8026 (reg:SI VTYPE_REGNUM)
8027 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
8028 (unspec:<V_EXT_LMUL1> [
8029 (match_operand:VF_HS 3 "register_operand" " vr, vr")
8030 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
8031 ] ANY_FWREDUC_SUM)
8032 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
8033 "TARGET_VECTOR"
8034 "vf<reduc_op>.vs\t%0,%3,%4%p1"
8035 [(set_attr "type" "vfwred<order>")
8036 (set_attr "mode" "<MODE>")
8037 (set (attr "frm_mode")
8038 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
8040 ;; -------------------------------------------------------------------------------
8041 ;; ---- Predicated permutation operations
8042 ;; -------------------------------------------------------------------------------
8043 ;; Includes:
8044 ;; - 16.1 Integer Scalar Move Instructions
8045 ;; - 16.2 Floating-Point Scalar Move Instructions
8046 ;; - 16.3 Vector Slide Instructions
8047 ;; - 16.4 Vector Register Gather Instructions
8048 ;; - 16.5 Vector Compress Instruction
8049 ;; -------------------------------------------------------------------------------
8051 (define_expand "@pred_extract_first<mode>"
8052 [(set (match_operand:<VEL> 0 "register_operand")
8053 (unspec:<VEL>
8054 [(vec_select:<VEL>
8055 (match_operand:V_VLSI 1 "reg_or_mem_operand")
8056 (parallel [(const_int 0)]))
8057 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8058 "TARGET_VECTOR"
8059 {
8060 if (MEM_P (operands[1]))
8061 {
8062 /* Combine vle.v + vmv.x.s ==> lw. */
8063 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
8064 DONE;
8065 }
8066 })
8068 (define_insn_and_split "*pred_extract_first<mode>"
8069 [(set (match_operand:<VEL> 0 "register_operand" "=r")
8070 (unspec:<VEL>
8071 [(vec_select:<VEL>
8072 (match_operand:V_VLSI 1 "register_operand" "vr")
8073 (parallel [(const_int 0)]))
8074 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8075 "TARGET_VECTOR"
8076 "vmv.x.s\t%0,%1"
8077 "known_gt (GET_MODE_BITSIZE (<VEL>mode), GET_MODE_BITSIZE (Pmode))"
8078 [(const_int 0)]
8079 {
8080 /* In rv32 system, we can't use vmv.x.s directly.
8081 Instead, we should generate this following code sequence:
8082 vsrl.vx v16,v8,a0
8083 vmv.x.s a1,v16
8084 vmv.x.s a0,v8 */
8085 rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
8086 rtx high_bits = gen_reg_rtx (<MODE>mode);
8087 emit_insn (gen_pred_scalar (LSHIFTRT, <MODE>mode, high_bits, CONSTM1_RTX (<VM>mode),
8088 RVV_VUNDEF (<MODE>mode), operands[1], nbits, /* vl */ const1_rtx,
8089 gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
8090 gen_int_mode (riscv_vector::MASK_ANY, Pmode),
8091 gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
8092 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8093 gen_highpart (SImode, operands[0]), high_bits));
8094 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8095 gen_lowpart (SImode, operands[0]), operands[1]));
8096 DONE;
8097 }
8098 [(set_attr "type" "vimovvx")
8099 (set_attr "mode" "<MODE>")])
8101 (define_insn "@pred_extract_first_trunc<mode>"
8102 [(set (match_operand:SI 0 "register_operand" "=r")
8103 (truncate:SI
8104 (unspec:<VEL>
8105 [(vec_select:<VEL>
8106 (match_operand:V_VLSI_D 1 "register_operand" "vr")
8107 (parallel [(const_int 0)]))
8108 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
8109 "TARGET_VECTOR"
8110 "vmv.x.s\t%0,%1"
8111 [(set_attr "type" "vimovvx")
8112 (set_attr "mode" "<MODE>")])
8114 (define_expand "@pred_extract_first<mode>"
8115 [(set (match_operand:<VEL> 0 "register_operand")
8116 (unspec:<VEL>
8117 [(vec_select:<VEL>
8118 (match_operand:V_VLSF 1 "reg_or_mem_operand")
8119 (parallel [(const_int 0)]))
8120 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8121 "TARGET_VECTOR"
8122 {
8123 if (MEM_P (operands[1]))
8124 {
8125 /* Combine vle.v + vmv.f.s ==> flw. */
8126 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
8127 DONE;
8128 }
8129 })
8131 (define_insn "*pred_extract_first<mode>"
8132 [(set (match_operand:<VEL> 0 "register_operand" "=f")
8133 (unspec:<VEL>
8134 [(vec_select:<VEL>
8135 (match_operand:V_VLSF 1 "register_operand" "vr")
8136 (parallel [(const_int 0)]))
8137 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8138 "TARGET_VECTOR"
8139 "vfmv.f.s\t%0,%1"
8140 [(set_attr "type" "vfmovvf")
8141 (set_attr "mode" "<MODE>")])
8143 ;; vslide instructions
8144 (define_insn "@pred_slide<ud><mode>"
8145 [(set (match_operand:V_VLS 0 "register_operand" "<ud_constraint>")
8146 (unspec:V_VLS
8147 [(unspec:<VM>
8148 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8149 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8150 (match_operand 6 "const_int_operand" " i, i, i, i")
8151 (match_operand 7 "const_int_operand" " i, i, i, i")
8152 (match_operand 8 "const_int_operand" " i, i, i, i")
8153 (reg:SI VL_REGNUM)
8154 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8155 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0, vu, 0")
8156 (match_operand:V_VLS 3 "register_operand" " vr, vr, vr, vr")
8157 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSLIDES))]
8158 "TARGET_VECTOR"
8159 "vslide<ud>.v%o4\t%0,%3,%4%p1"
8160 [(set_attr "type" "vslide<ud>")
8161 (set_attr "mode" "<MODE>")])
8163 ;; vslide1 instructions
8164 (define_insn "@pred_slide<ud><mode>"
8165 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "<ud_constraint>")
8166 (unspec:V_VLSI_QHS
8167 [(unspec:<VM>
8168 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8169 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8170 (match_operand 6 "const_int_operand" " i, i, i, i")
8171 (match_operand 7 "const_int_operand" " i, i, i, i")
8172 (match_operand 8 "const_int_operand" " i, i, i, i")
8173 (reg:SI VL_REGNUM)
8174 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8175 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")
8176 (match_operand:V_VLSI_QHS 3 "register_operand" " vr, vr, vr, vr")
8177 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8178 "TARGET_VECTOR"
8179 "vslide<ud>.vx\t%0,%3,%z4%p1"
8180 [(set_attr "type" "vislide<ud>")
8181 (set_attr "mode" "<MODE>")])
8183 (define_expand "@pred_slide<ud><mode>"
8184 [(set (match_operand:V_VLSI_D 0 "register_operand")
8185 (unspec:V_VLSI_D
8186 [(unspec:<VM>
8187 [(match_operand:<VM> 1 "vector_mask_operand")
8188 (match_operand 5 "reg_or_int_operand")
8189 (match_operand 6 "const_int_operand")
8190 (match_operand 7 "const_int_operand")
8191 (match_operand 8 "const_int_operand")
8192 (reg:SI VL_REGNUM)
8193 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8194 (match_operand:V_VLSI_D 2 "vector_merge_operand")
8195 (match_operand:V_VLSI_D 3 "register_operand")
8196 (match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
8197 "TARGET_VECTOR"
8198 {
8199 poly_uint64 nunits = GET_MODE_NUNITS (<MODE>mode) * 2;
8200 machine_mode vsimode = riscv_vector::get_vector_mode (SImode, nunits).require ();
8201 machine_mode vbimode = riscv_vector::get_vector_mode (BImode, nunits).require ();
8202 if (riscv_vector::slide1_sew64_helper (<UNSPEC>, <MODE>mode,
8203 vsimode, vbimode,
8204 operands))
8205 DONE;
8206 })
8208 (define_insn "*pred_slide<ud><mode>"
8209 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8210 (unspec:V_VLSI_D
8211 [(unspec:<VM>
8212 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8213 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8214 (match_operand 6 "const_int_operand" " i, i, i, i")
8215 (match_operand 7 "const_int_operand" " i, i, i, i")
8216 (match_operand 8 "const_int_operand" " i, i, i, i")
8217 (reg:SI VL_REGNUM)
8218 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8219 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8220 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8221 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8222 "TARGET_VECTOR"
8223 "vslide<ud>.vx\t%0,%3,%z4%p1"
8224 [(set_attr "type" "vislide<ud>")
8225 (set_attr "mode" "<MODE>")])
8227 (define_insn "*pred_slide<ud><mode>_extended"
8228 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8229 (unspec:V_VLSI_D
8230 [(unspec:<VM>
8231 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8232 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8233 (match_operand 6 "const_int_operand" " i, i, i, i")
8234 (match_operand 7 "const_int_operand" " i, i, i, i")
8235 (match_operand 8 "const_int_operand" " i, i, i, i")
8236 (reg:SI VL_REGNUM)
8237 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8238 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8239 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8240 (sign_extend:<VEL>
8241 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))]
8242 "TARGET_VECTOR && !TARGET_64BIT"
8243 "vslide<ud>.vx\t%0,%3,%z4%p1"
8244 [(set_attr "type" "vislide<ud>")
8245 (set_attr "mode" "<MODE>")])
8247 ;; vfslide1 instructions
8248 (define_insn "@pred_slide<ud><mode>"
8249 [(set (match_operand:V_VLSF 0 "register_operand" "<ud_constraint>")
8250 (unspec:V_VLSF
8251 [(unspec:<VM>
8252 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8253 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8254 (match_operand 6 "const_int_operand" " i, i, i, i")
8255 (match_operand 7 "const_int_operand" " i, i, i, i")
8256 (match_operand 8 "const_int_operand" " i, i, i, i")
8257 (reg:SI VL_REGNUM)
8258 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8259 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")
8260 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
8261 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
8262 "TARGET_VECTOR"
8263 "vfslide<ud>.vf\t%0,%3,%4%p1"
8264 [(set_attr "type" "vfslide<ud>")
8265 (set_attr "mode" "<MODE>")])
8267 ;; vrgather
8268 (define_insn "@pred_gather<mode>"
8269 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8270 (if_then_else:V_VLS
8271 (unspec:<VM>
8272 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8273 (match_operand 5 "vector_length_operand" " rK, rK")
8274 (match_operand 6 "const_int_operand" " i, i")
8275 (match_operand 7 "const_int_operand" " i, i")
8276 (match_operand 8 "const_int_operand" " i, i")
8277 (reg:SI VL_REGNUM)
8278 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8279 (unspec:V_VLS
8280 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8281 (match_operand:<VINDEX> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHER)
8282 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8283 "TARGET_VECTOR"
8284 "vrgather.vv\t%0,%3,%4%p1"
8285 [(set_attr "type" "vgather")
8286 (set_attr "mode" "<MODE>")])
8288 (define_insn "@pred_gather<mode>_scalar"
8289 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8290 (if_then_else:V_VLS
8291 (unspec:<VM>
8292 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8293 (match_operand 5 "vector_length_operand" " rK, rK")
8294 (match_operand 6 "const_int_operand" " i, i")
8295 (match_operand 7 "const_int_operand" " i, i")
8296 (match_operand 8 "const_int_operand" " i, i")
8297 (reg:SI VL_REGNUM)
8298 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8299 (unspec:V_VLS
8300 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8301 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] UNSPEC_VRGATHER)
8302 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8303 "TARGET_VECTOR"
8304 "vrgather.v%o4\t%0,%3,%4%p1"
8305 [(set_attr "type" "vgather")
8306 (set_attr "mode" "<MODE>")])
8308 ;; vrgatherei16
8309 (define_insn "@pred_gatherei16<mode>"
8310 [(set (match_operand:VEI16 0 "register_operand" "=&vr, &vr")
8311 (if_then_else:VEI16
8312 (unspec:<VM>
8313 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8314 (match_operand 5 "vector_length_operand" " rK, rK")
8315 (match_operand 6 "const_int_operand" " i, i")
8316 (match_operand 7 "const_int_operand" " i, i")
8317 (match_operand 8 "const_int_operand" " i, i")
8318 (reg:SI VL_REGNUM)
8319 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8320 (unspec:VEI16
8321 [(match_operand:VEI16 3 "register_operand" " vr, vr")
8322 (match_operand:<VINDEXEI16> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHEREI16)
8323 (match_operand:VEI16 2 "vector_merge_operand" " vu, 0")))]
8324 "TARGET_VECTOR"
8325 "vrgatherei16.vv\t%0,%3,%4%p1"
8326 [(set_attr "type" "vgather")
8327 (set_attr "mode" "<MODE>")])
8329 ;; vcompress
8330 (define_insn "@pred_compress<mode>"
8331 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8332 (unspec:V_VLS
8333 [(unspec:<VM>
8334 [(match_operand:<VM> 3 "register_operand" " vm, vm")
8335 (match_operand 4 "vector_length_operand" " rK, rK")
8336 (match_operand 5 "const_int_operand" " i, i")
8337 (match_operand 6 "const_int_operand" " i, i")
8338 (reg:SI VL_REGNUM)
8339 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8340 (match_operand:V_VLS 2 "register_operand" " vr, vr")
8341 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))]
8342 "TARGET_VECTOR"
8343 "vcompress.vm\t%0,%2,%3"
8344 [(set_attr "type" "vcompress")
8345 (set_attr "mode" "<MODE>")])
8347 ;; -------------------------------------------------------------------------------
8348 ;; ---- Predicated Fault-Only-First loads
8349 ;; -------------------------------------------------------------------------------
8350 ;; Includes:
8351 ;; - 7.7. Unit-stride Fault-Only-First Loads
8352 ;; -------------------------------------------------------------------------------
8354 (define_insn "read_vlsi"
8355 [(set (match_operand:SI 0 "register_operand" "=r")
8356 (reg:SI VL_REGNUM))]
8357 "TARGET_VECTOR"
8358 "csrr\t%0,vl"
8359 [(set_attr "type" "rdvl")
8360 (set_attr "mode" "SI")])
8362 (define_insn "read_vldi_zero_extend"
8363 [(set (match_operand:DI 0 "register_operand" "=r")
8364 (zero_extend:DI (reg:SI VL_REGNUM)))]
8365 "TARGET_VECTOR && TARGET_64BIT"
8366 "csrr\t%0,vl"
8367 [(set_attr "type" "rdvl")
8368 (set_attr "mode" "DI")])
8370 (define_insn "@pred_fault_load<mode>"
8371 [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr")
8372 (if_then_else:V
8373 (unspec:<VM>
8374 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1, Wc1")
8375 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
8376 (match_operand 5 "const_int_operand" " i, i, i, i")
8377 (match_operand 6 "const_int_operand" " i, i, i, i")
8378 (match_operand 7 "const_int_operand" " i, i, i, i")
8379 (reg:SI VL_REGNUM)
8380 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8381 (unspec:V
8382 [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF)
8383 (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0")))
8384 (set (reg:SI VL_REGNUM)
8385 (unspec:SI
8386 [(if_then_else:V
8387 (unspec:<VM>
8388 [(match_dup 1) (match_dup 4) (match_dup 5)
8389 (match_dup 6) (match_dup 7)
8390 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8391 (unspec:V [(match_dup 3)] UNSPEC_VLEFF)
8392 (match_dup 2))] UNSPEC_MODIFY_VL))]
8393 "TARGET_VECTOR"
8394 "vle<sew>ff.v\t%0,%3%p1"
8395 [(set_attr "type" "vldff")
8396 (set_attr "mode" "<MODE>")])
8399 ;; -------------------------------------------------------------------------------
8400 ;; ---- Predicated Segment loads/stores
8401 ;; -------------------------------------------------------------------------------
8402 ;; Includes:
8403 ;; - 7.8.1. Vector Unit-Stride Segment Loads and Stores
8404 ;; - 7.8.2. Vector Strided Segment Loads and Stores
8405 ;; - 7.8.3. Vector Indexed Segment Loads and Stores
8406 ;; -------------------------------------------------------------------------------
8408 (define_insn "@pred_unit_strided_load<mode>"
8409 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8410 (if_then_else:VT
8411 (unspec:<VM>
8412 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8413 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8414 (match_operand 5 "const_int_operand" " i, i, i")
8415 (match_operand 6 "const_int_operand" " i, i, i")
8416 (match_operand 7 "const_int_operand" " i, i, i")
8417 (reg:SI VL_REGNUM)
8418 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8419 (unspec:VT
8420 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8421 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED)
8422 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8423 "TARGET_VECTOR"
8424 "vlseg<nf>e<sew>.v\t%0,(%z3)%p1"
8425 [(set_attr "type" "vlsegde")
8426 (set_attr "mode" "<MODE>")])
8428 (define_insn "@pred_unit_strided_store<mode>"
8429 [(set (mem:BLK (scratch))
8430 (unspec:BLK
8431 [(unspec:<VM>
8432 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8433 (match_operand 3 "vector_length_operand" " rK")
8434 (match_operand 4 "const_int_operand" " i")
8435 (reg:SI VL_REGNUM)
8436 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8437 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8438 (match_operand:VT 2 "register_operand" " vr")
8439 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED))]
8440 "TARGET_VECTOR"
8441 "vsseg<nf>e<sew>.v\t%2,(%z1)%p0"
8442 [(set_attr "type" "vssegte")
8443 (set_attr "mode" "<MODE>")])
8445 (define_insn "@pred_strided_load<mode>"
8446 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8447 (if_then_else:VT
8448 (unspec:<VM>
8449 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8450 (match_operand 5 "vector_length_operand" " rK, rK, rK")
8451 (match_operand 6 "const_int_operand" " i, i, i")
8452 (match_operand 7 "const_int_operand" " i, i, i")
8453 (match_operand 8 "const_int_operand" " i, i, i")
8454 (reg:SI VL_REGNUM)
8455 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8456 (unspec:VT
8457 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8458 (match_operand 4 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8459 (mem:BLK (scratch))] UNSPEC_STRIDED)
8460 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8461 "TARGET_VECTOR"
8462 "vlsseg<nf>e<sew>.v\t%0,(%z3),%z4%p1"
8463 [(set_attr "type" "vlsegds")
8464 (set_attr "mode" "<MODE>")])
8466 (define_insn "@pred_strided_store<mode>"
8467 [(set (mem:BLK (scratch))
8468 (unspec:BLK
8469 [(unspec:<VM>
8470 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8471 (match_operand 4 "vector_length_operand" " rK")
8472 (match_operand 5 "const_int_operand" " i")
8473 (reg:SI VL_REGNUM)
8474 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8475 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8476 (match_operand 2 "pmode_reg_or_0_operand" " rJ")
8477 (match_operand:VT 3 "register_operand" " vr")
8478 (mem:BLK (scratch))] UNSPEC_STRIDED))]
8479 "TARGET_VECTOR"
8480 "vssseg<nf>e<sew>.v\t%3,(%z1),%z2%p0"
8481 [(set_attr "type" "vssegts")
8482 (set_attr "mode" "<MODE>")])
8484 (define_insn "@pred_fault_load<mode>"
8485 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8486 (if_then_else:VT
8487 (unspec:<VM>
8488 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8489 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8490 (match_operand 5 "const_int_operand" " i, i, i")
8491 (match_operand 6 "const_int_operand" " i, i, i")
8492 (match_operand 7 "const_int_operand" " i, i, i")
8493 (reg:SI VL_REGNUM)
8494 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8495 (unspec:VT
8496 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8497 (mem:BLK (scratch))] UNSPEC_VLEFF)
8498 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))
8499 (set (reg:SI VL_REGNUM)
8500 (unspec:SI
8501 [(if_then_else:VT
8502 (unspec:<VM>
8503 [(match_dup 1) (match_dup 4) (match_dup 5)
8504 (match_dup 6) (match_dup 7)
8505 (reg:SI VL_REGNUM)
8506 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8507 (unspec:VT
8508 [(match_dup 3) (mem:BLK (scratch))] UNSPEC_VLEFF)
8509 (match_dup 2))] UNSPEC_MODIFY_VL))]
8510 "TARGET_VECTOR"
8511 "vlseg<nf>e<sew>ff.v\t%0,(%z3)%p1"
8512 [(set_attr "type" "vlsegdff")
8513 (set_attr "mode" "<MODE>")])
8515 (define_insn "@pred_indexed_<order>load<V1T:mode><RATIO64I:mode>"
8516 [(set (match_operand:V1T 0 "register_operand" "=&vr, &vr")
8517 (if_then_else:V1T
8518 (unspec:<VM>
8519 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8520 (match_operand 5 "vector_length_operand" " rK, rK")
8521 (match_operand 6 "const_int_operand" " i, i")
8522 (match_operand 7 "const_int_operand" " i, i")
8523 (match_operand 8 "const_int_operand" " i, i")
8524 (reg:SI VL_REGNUM)
8525 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8526 (unspec:V1T
8527 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8528 (mem:BLK (scratch))
8529 (match_operand:RATIO64I 4 "register_operand" " vr, vr")] ORDER)
8530 (match_operand:V1T 2 "vector_merge_operand" " vu, 0")))]
8531 "TARGET_VECTOR"
8532 "vl<order>xseg<nf>ei<RATIO64I:sew>.v\t%0,(%z3),%4%p1"
8533 [(set_attr "type" "vlsegd<order>x")
8534 (set_attr "mode" "<V1T:MODE>")])
8536 (define_insn "@pred_indexed_<order>load<V2T:mode><RATIO32I:mode>"
8537 [(set (match_operand:V2T 0 "register_operand" "=&vr, &vr")
8538 (if_then_else:V2T
8539 (unspec:<VM>
8540 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8541 (match_operand 5 "vector_length_operand" " rK, rK")
8542 (match_operand 6 "const_int_operand" " i, i")
8543 (match_operand 7 "const_int_operand" " i, i")
8544 (match_operand 8 "const_int_operand" " i, i")
8545 (reg:SI VL_REGNUM)
8546 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8547 (unspec:V2T
8548 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8549 (mem:BLK (scratch))
8550 (match_operand:RATIO32I 4 "register_operand" " vr, vr")] ORDER)
8551 (match_operand:V2T 2 "vector_merge_operand" " vu, 0")))]
8552 "TARGET_VECTOR"
8553 "vl<order>xseg<nf>ei<RATIO32I:sew>.v\t%0,(%z3),%4%p1"
8554 [(set_attr "type" "vlsegd<order>x")
8555 (set_attr "mode" "<V2T:MODE>")])
8557 (define_insn "@pred_indexed_<order>load<V4T:mode><RATIO16I:mode>"
8558 [(set (match_operand:V4T 0 "register_operand" "=&vr, &vr")
8559 (if_then_else:V4T
8560 (unspec:<VM>
8561 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8562 (match_operand 5 "vector_length_operand" " rK, rK")
8563 (match_operand 6 "const_int_operand" " i, i")
8564 (match_operand 7 "const_int_operand" " i, i")
8565 (match_operand 8 "const_int_operand" " i, i")
8566 (reg:SI VL_REGNUM)
8567 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8568 (unspec:V4T
8569 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8570 (mem:BLK (scratch))
8571 (match_operand:RATIO16I 4 "register_operand" " vr, vr")] ORDER)
8572 (match_operand:V4T 2 "vector_merge_operand" " vu, 0")))]
8573 "TARGET_VECTOR"
8574 "vl<order>xseg<nf>ei<RATIO16I:sew>.v\t%0,(%z3),%4%p1"
8575 [(set_attr "type" "vlsegd<order>x")
8576 (set_attr "mode" "<V4T:MODE>")])
8578 (define_insn "@pred_indexed_<order>load<V8T:mode><RATIO8I:mode>"
8579 [(set (match_operand:V8T 0 "register_operand" "=&vr, &vr")
8580 (if_then_else:V8T
8581 (unspec:<VM>
8582 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8583 (match_operand 5 "vector_length_operand" " rK, rK")
8584 (match_operand 6 "const_int_operand" " i, i")
8585 (match_operand 7 "const_int_operand" " i, i")
8586 (match_operand 8 "const_int_operand" " i, i")
8587 (reg:SI VL_REGNUM)
8588 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8589 (unspec:V8T
8590 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8591 (mem:BLK (scratch))
8592 (match_operand:RATIO8I 4 "register_operand" " vr, vr")] ORDER)
8593 (match_operand:V8T 2 "vector_merge_operand" " vu, 0")))]
8594 "TARGET_VECTOR"
8595 "vl<order>xseg<nf>ei<RATIO8I:sew>.v\t%0,(%z3),%4%p1"
8596 [(set_attr "type" "vlsegd<order>x")
8597 (set_attr "mode" "<V8T:MODE>")])
8599 (define_insn "@pred_indexed_<order>load<V16T:mode><RATIO4I:mode>"
8600 [(set (match_operand:V16T 0 "register_operand" "=&vr, &vr")
8601 (if_then_else:V16T
8602 (unspec:<VM>
8603 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8604 (match_operand 5 "vector_length_operand" " rK, rK")
8605 (match_operand 6 "const_int_operand" " i, i")
8606 (match_operand 7 "const_int_operand" " i, i")
8607 (match_operand 8 "const_int_operand" " i, i")
8608 (reg:SI VL_REGNUM)
8609 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8610 (unspec:V16T
8611 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8612 (mem:BLK (scratch))
8613 (match_operand:RATIO4I 4 "register_operand" " vr, vr")] ORDER)
8614 (match_operand:V16T 2 "vector_merge_operand" " vu, 0")))]
8615 "TARGET_VECTOR"
8616 "vl<order>xseg<nf>ei<RATIO4I:sew>.v\t%0,(%z3),%4%p1"
8617 [(set_attr "type" "vlsegd<order>x")
8618 (set_attr "mode" "<V16T:MODE>")])
8620 (define_insn "@pred_indexed_<order>load<V32T:mode><RATIO2I:mode>"
8621 [(set (match_operand:V32T 0 "register_operand" "=&vr, &vr")
8622 (if_then_else:V32T
8623 (unspec:<VM>
8624 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8625 (match_operand 5 "vector_length_operand" " rK, rK")
8626 (match_operand 6 "const_int_operand" " i, i")
8627 (match_operand 7 "const_int_operand" " i, i")
8628 (match_operand 8 "const_int_operand" " i, i")
8629 (reg:SI VL_REGNUM)
8630 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8631 (unspec:V32T
8632 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8633 (mem:BLK (scratch))
8634 (match_operand:RATIO2I 4 "register_operand" " vr, vr")] ORDER)
8635 (match_operand:V32T 2 "vector_merge_operand" " vu, 0")))]
8636 "TARGET_VECTOR"
8637 "vl<order>xseg<nf>ei<RATIO2I:sew>.v\t%0,(%z3),%4%p1"
8638 [(set_attr "type" "vlsegd<order>x")
8639 (set_attr "mode" "<V32T:MODE>")])
8641 (define_insn "@pred_indexed_<order>store<V1T:mode><RATIO64I:mode>"
8642 [(set (mem:BLK (scratch))
8643 (unspec:BLK
8644 [(unspec:<VM>
8645 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8646 (match_operand 4 "vector_length_operand" " rK")
8647 (match_operand 5 "const_int_operand" " i")
8648 (reg:SI VL_REGNUM)
8649 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8650 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8651 (match_operand:RATIO64I 2 "register_operand" " vr")
8652 (match_operand:V1T 3 "register_operand" " vr")] ORDER))]
8653 "TARGET_VECTOR"
8654 "vs<order>xseg<nf>ei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
8655 [(set_attr "type" "vssegt<order>x")
8656 (set_attr "mode" "<V1T:MODE>")])
8658 (define_insn "@pred_indexed_<order>store<V2T:mode><RATIO32I:mode>"
8659 [(set (mem:BLK (scratch))
8660 (unspec:BLK
8661 [(unspec:<VM>
8662 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8663 (match_operand 4 "vector_length_operand" " rK")
8664 (match_operand 5 "const_int_operand" " i")
8665 (reg:SI VL_REGNUM)
8666 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8667 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8668 (match_operand:RATIO32I 2 "register_operand" " vr")
8669 (match_operand:V2T 3 "register_operand" " vr")] ORDER))]
8670 "TARGET_VECTOR"
8671 "vs<order>xseg<nf>ei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
8672 [(set_attr "type" "vssegt<order>x")
8673 (set_attr "mode" "<V2T:MODE>")])
8675 (define_insn "@pred_indexed_<order>store<V4T:mode><RATIO16I:mode>"
8676 [(set (mem:BLK (scratch))
8677 (unspec:BLK
8678 [(unspec:<VM>
8679 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8680 (match_operand 4 "vector_length_operand" " rK")
8681 (match_operand 5 "const_int_operand" " i")
8682 (reg:SI VL_REGNUM)
8683 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8684 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8685 (match_operand:RATIO16I 2 "register_operand" " vr")
8686 (match_operand:V4T 3 "register_operand" " vr")] ORDER))]
8687 "TARGET_VECTOR"
8688 "vs<order>xseg<nf>ei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
8689 [(set_attr "type" "vssegt<order>x")
8690 (set_attr "mode" "<V4T:MODE>")])
8692 (define_insn "@pred_indexed_<order>store<V8T:mode><RATIO8I:mode>"
8693 [(set (mem:BLK (scratch))
8694 (unspec:BLK
8695 [(unspec:<VM>
8696 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8697 (match_operand 4 "vector_length_operand" " rK")
8698 (match_operand 5 "const_int_operand" " i")
8699 (reg:SI VL_REGNUM)
8700 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8701 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8702 (match_operand:RATIO8I 2 "register_operand" " vr")
8703 (match_operand:V8T 3 "register_operand" " vr")] ORDER))]
8704 "TARGET_VECTOR"
8705 "vs<order>xseg<nf>ei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
8706 [(set_attr "type" "vssegt<order>x")
8707 (set_attr "mode" "<V8T:MODE>")])
8709 (define_insn "@pred_indexed_<order>store<V16T:mode><RATIO4I:mode>"
8710 [(set (mem:BLK (scratch))
8711 (unspec:BLK
8712 [(unspec:<VM>
8713 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8714 (match_operand 4 "vector_length_operand" " rK")
8715 (match_operand 5 "const_int_operand" " i")
8716 (reg:SI VL_REGNUM)
8717 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8718 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8719 (match_operand:RATIO4I 2 "register_operand" " vr")
8720 (match_operand:V16T 3 "register_operand" " vr")] ORDER))]
8721 "TARGET_VECTOR"
8722 "vs<order>xseg<nf>ei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
8723 [(set_attr "type" "vssegt<order>x")
8724 (set_attr "mode" "<V16T:MODE>")])
8726 (define_insn "@pred_indexed_<order>store<V32T:mode><RATIO2I:mode>"
8727 [(set (mem:BLK (scratch))
8728 (unspec:BLK
8729 [(unspec:<VM>
8730 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8731 (match_operand 4 "vector_length_operand" " rK")
8732 (match_operand 5 "const_int_operand" " i")
8733 (reg:SI VL_REGNUM)
8734 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8735 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8736 (match_operand:RATIO2I 2 "register_operand" " vr")
8737 (match_operand:V32T 3 "register_operand" " vr")] ORDER))]
8738 "TARGET_VECTOR"
8739 "vs<order>xseg<nf>ei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
8740 [(set_attr "type" "vssegt<order>x")
8741 (set_attr "mode" "<V32T:MODE>")])
8743 (include "autovec.md")
8744 (include "autovec-opt.md")