| blob | bcedf3d79e2610ec5e51268e2f5404c1ddafd562 |
1 ;; Machine description for RISC-V 'V' Extension for GNU compiler.
2 ;; Copyright (C) 2022-2024 Free Software Foundation, Inc.
3 ;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; This file describes the RISC-V 'V' Extension, Version 1.0.
22 ;;
23 ;; This file include :
24 ;;
25 ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
26 ;; - Auto-vectorization (autovec.md)
27 ;; - Optimization (autovec-opt.md)
29 (include "vector-iterators.md")
31 (define_constants [
32 (INVALID_ATTRIBUTE 255)
33 (X0_REGNUM 0)
34 ])
36 ;; True if the type is RVV instructions that include VTYPE
37 ;; global status register in the use op list.
38 ;; We known VTYPE has 4 fields: SEW, LMUL, TA, MA.
39 ;; The instruction need any of VTYPE field is set as true
40 ;; in this attribute.
41 (define_attr "has_vtype_op" "false,true"
42 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
43 vldux,vldox,vstux,vstox,vldff,\
44 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
45 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
46 vsalu,vaalu,vsmul,vsshift,vnclip,\
47 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
48 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
49 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
50 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
51 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
52 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,\
53 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
54 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
55 vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
56 vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
57 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
58 vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
59 (const_string "true")]
60 (const_string "false")))
62 ;; True if the type is RVV instructions that include VL
63 ;; global status register in the use op list.
64 ;; The instruction need vector length to be specified is set
65 ;; in this attribute.
66 (define_attr "has_vl_op" "false,true"
67 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
68 vldux,vldox,vstux,vstox,vldff,\
69 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
70 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
71 vsalu,vaalu,vsmul,vsshift,vnclip,\
72 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
73 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
74 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
75 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
76 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
77 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovxv,vfmovfv,\
78 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
79 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
80 vssegtux,vssegtox,vlsegdff,vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,\
81 vror,vwsll,vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
82 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,\
83 vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
84 (const_string "true")]
85 (const_string "false")))
87 ;; The default SEW of RVV instruction. This attribute doesn't mean the instruction
88 ;; is necessary to require SEW check for example vlm.v which require ratio to
89 ;; check. However, we need default value of SEW for vsetvl instruction since there
90 ;; is no field for ratio in the vsetvl instruction encoding.
91 (define_attr "sew" ""
92 (cond [(eq_attr "mode" "RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\
93 RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,\
94 RVVM1x8QI,RVVMF2x8QI,RVVMF4x8QI,RVVMF8x8QI,\
95 RVVM1x7QI,RVVMF2x7QI,RVVMF4x7QI,RVVMF8x7QI,\
96 RVVM1x6QI,RVVMF2x6QI,RVVMF4x6QI,RVVMF8x6QI,\
97 RVVM1x5QI,RVVMF2x5QI,RVVMF4x5QI,RVVMF8x5QI,\
98 RVVM2x4QI,RVVM1x4QI,RVVMF2x4QI,RVVMF4x4QI,RVVMF8x4QI,\
99 RVVM2x3QI,RVVM1x3QI,RVVMF2x3QI,RVVMF4x3QI,RVVMF8x3QI,\
100 RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4x2QI,RVVMF8x2QI,\
101 V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,\
102 V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI")
103 (const_int 8)
104 (eq_attr "mode" "RVVMF16BI")
105 (if_then_else (match_test "TARGET_XTHEADVECTOR")
106 (const_int 16)
107 (const_int 8))
108 (eq_attr "mode" "RVVMF32BI")
109 (if_then_else (match_test "TARGET_XTHEADVECTOR")
110 (const_int 32)
111 (const_int 8))
112 (eq_attr "mode" "RVVMF64BI")
113 (if_then_else (match_test "TARGET_XTHEADVECTOR")
114 (const_int 64)
115 (const_int 8))
116 (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,\
117 RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\
118 RVVM1x7HI,RVVMF2x7HI,RVVMF4x7HI,\
119 RVVM1x6HI,RVVMF2x6HI,RVVMF4x6HI,\
120 RVVM1x5HI,RVVMF2x5HI,RVVMF4x5HI,\
121 RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,\
122 RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,\
123 RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,\
124 RVVM8BF,RVVM4BF,RVVM2BF,RVVM1BF,RVVMF2BF,RVVMF4BF,\
125 RVVM1x8BF,RVVMF2x8BF,RVVMF4x8BF,\
126 RVVM1x7BF,RVVMF2x7BF,RVVMF4x7BF,\
127 RVVM1x6BF,RVVMF2x6BF,RVVMF4x6BF,\
128 RVVM1x5BF,RVVMF2x5BF,RVVMF4x5BF,\
129 RVVM2x4BF,RVVM1x4BF,RVVMF2x4BF,RVVMF4x4BF,\
130 RVVM2x3BF,RVVM1x3BF,RVVMF2x3BF,RVVMF4x3BF,\
131 RVVM4x2BF,RVVM2x2BF,RVVM1x2BF,RVVMF2x2BF,RVVMF4x2BF,\
132 RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,\
133 RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,\
134 RVVM1x7HF,RVVMF2x7HF,RVVMF4x7HF,\
135 RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,\
136 RVVM1x5HF,RVVMF2x5HF,RVVMF4x5HF,\
137 RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF,RVVMF4x4HF,\
138 RVVM2x3HF,RVVM1x3HF,RVVMF2x3HF,RVVMF4x3HF,\
139 RVVM4x2HF,RVVM2x2HF,RVVM1x2HF,RVVMF2x2HF,RVVMF4x2HF,\
140 V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI,\
141 V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V2048HF")
142 (const_int 16)
143 (eq_attr "mode" "RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI,\
144 RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF,\
145 RVVM1x8SI,RVVMF2x8SI,\
146 RVVM1x7SI,RVVMF2x7SI,\
147 RVVM1x6SI,RVVMF2x6SI,\
148 RVVM1x5SI,RVVMF2x5SI,\
149 RVVMF2x4SI,RVVMF2x3SI,\
150 RVVM2x4SI,RVVM1x4SI,\
151 RVVM2x3SI,RVVM1x3SI,\
152 RVVM4x2SI,RVVM2x2SI,RVVM1x2SI,RVVMF2x2SI,\
153 RVVM1x8SF,RVVMF2x8SF,\
154 RVVM1x7SF,RVVMF2x7SF,\
155 RVVM1x6SF,RVVMF2x6SF,\
156 RVVM1x5SF,RVVMF2x5SF,\
157 RVVM2x4SF,RVVM1x4SF,RVVMF2x4SF,\
158 RVVM2x3SF,RVVM1x3SF,RVVMF2x3SF,\
159 RVVM4x2SF,RVVM2x2SF,RVVM1x2SF,RVVMF2x2SF,\
160 V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI,\
161 V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF")
162 (const_int 32)
163 (eq_attr "mode" "RVVM8DI,RVVM4DI,RVVM2DI,RVVM1DI,\
164 RVVM8DF,RVVM4DF,RVVM2DF,RVVM1DF,\
165 RVVM1x8DI,RVVM1x7DI,RVVM1x6DI,RVVM1x5DI,\
166 RVVM2x4DI,RVVM1x4DI,\
167 RVVM2x3DI,RVVM1x3DI,\
168 RVVM4x2DI,RVVM2x2DI,RVVM1x2DI,\
169 RVVM1x8DF,RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,\
170 RVVM2x4DF,RVVM1x4DF,\
171 RVVM2x3DF,RVVM1x3DF,\
172 RVVM4x2DF,RVVM2x2DF,RVVM1x2DF,\
173 V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,\
174 V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF")
175 (const_int 64)]
176 (const_int INVALID_ATTRIBUTE)))
178 ;; Ditto to LMUL.
179 (define_attr "vlmul" ""
180 (cond [(eq_attr "mode" "RVVM8QI,RVVM1BI") (symbol_ref "riscv_vector::LMUL_8")
181 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (symbol_ref "riscv_vector::LMUL_4")
182 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (symbol_ref "riscv_vector::LMUL_2")
183 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (symbol_ref "riscv_vector::LMUL_1")
184 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F2")
185 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F4")
186 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (symbol_ref "TARGET_XTHEADVECTOR ? riscv_vector::LMUL_1 : riscv_vector::LMUL_F8")
187 (eq_attr "mode" "RVVM8HI") (symbol_ref "riscv_vector::LMUL_8")
188 (eq_attr "mode" "RVVM4HI") (symbol_ref "riscv_vector::LMUL_4")
189 (eq_attr "mode" "RVVM2HI") (symbol_ref "riscv_vector::LMUL_2")
190 (eq_attr "mode" "RVVM1HI") (symbol_ref "riscv_vector::LMUL_1")
191 (eq_attr "mode" "RVVMF2HI") (symbol_ref "riscv_vector::LMUL_F2")
192 (eq_attr "mode" "RVVMF4HI") (symbol_ref "riscv_vector::LMUL_F4")
193 (eq_attr "mode" "RVVM8BF") (symbol_ref "riscv_vector::LMUL_8")
194 (eq_attr "mode" "RVVM4BF") (symbol_ref "riscv_vector::LMUL_4")
195 (eq_attr "mode" "RVVM2BF") (symbol_ref "riscv_vector::LMUL_2")
196 (eq_attr "mode" "RVVM1BF") (symbol_ref "riscv_vector::LMUL_1")
197 (eq_attr "mode" "RVVMF2BF") (symbol_ref "riscv_vector::LMUL_F2")
198 (eq_attr "mode" "RVVMF4BF") (symbol_ref "riscv_vector::LMUL_F4")
199 (eq_attr "mode" "RVVM8HF") (symbol_ref "riscv_vector::LMUL_8")
200 (eq_attr "mode" "RVVM4HF") (symbol_ref "riscv_vector::LMUL_4")
201 (eq_attr "mode" "RVVM2HF") (symbol_ref "riscv_vector::LMUL_2")
202 (eq_attr "mode" "RVVM1HF") (symbol_ref "riscv_vector::LMUL_1")
203 (eq_attr "mode" "RVVMF2HF") (symbol_ref "riscv_vector::LMUL_F2")
204 (eq_attr "mode" "RVVMF4HF") (symbol_ref "riscv_vector::LMUL_F4")
205 (eq_attr "mode" "RVVM8SI") (symbol_ref "riscv_vector::LMUL_8")
206 (eq_attr "mode" "RVVM4SI") (symbol_ref "riscv_vector::LMUL_4")
207 (eq_attr "mode" "RVVM2SI") (symbol_ref "riscv_vector::LMUL_2")
208 (eq_attr "mode" "RVVM1SI") (symbol_ref "riscv_vector::LMUL_1")
209 (eq_attr "mode" "RVVMF2SI") (symbol_ref "riscv_vector::LMUL_F2")
210 (eq_attr "mode" "RVVM8SF") (symbol_ref "riscv_vector::LMUL_8")
211 (eq_attr "mode" "RVVM4SF") (symbol_ref "riscv_vector::LMUL_4")
212 (eq_attr "mode" "RVVM2SF") (symbol_ref "riscv_vector::LMUL_2")
213 (eq_attr "mode" "RVVM1SF") (symbol_ref "riscv_vector::LMUL_1")
214 (eq_attr "mode" "RVVMF2SF") (symbol_ref "riscv_vector::LMUL_F2")
215 (eq_attr "mode" "RVVM8DI") (symbol_ref "riscv_vector::LMUL_8")
216 (eq_attr "mode" "RVVM4DI") (symbol_ref "riscv_vector::LMUL_4")
217 (eq_attr "mode" "RVVM2DI") (symbol_ref "riscv_vector::LMUL_2")
218 (eq_attr "mode" "RVVM1DI") (symbol_ref "riscv_vector::LMUL_1")
219 (eq_attr "mode" "RVVM8DF") (symbol_ref "riscv_vector::LMUL_8")
220 (eq_attr "mode" "RVVM4DF") (symbol_ref "riscv_vector::LMUL_4")
221 (eq_attr "mode" "RVVM2DF") (symbol_ref "riscv_vector::LMUL_2")
222 (eq_attr "mode" "RVVM1DF") (symbol_ref "riscv_vector::LMUL_1")
223 (eq_attr "mode" "RVVM1x8QI") (symbol_ref "riscv_vector::LMUL_1")
224 (eq_attr "mode" "RVVMF2x8QI") (symbol_ref "riscv_vector::LMUL_F2")
225 (eq_attr "mode" "RVVMF4x8QI") (symbol_ref "riscv_vector::LMUL_F4")
226 (eq_attr "mode" "RVVMF8x8QI") (symbol_ref "riscv_vector::LMUL_F8")
227 (eq_attr "mode" "RVVM1x7QI") (symbol_ref "riscv_vector::LMUL_1")
228 (eq_attr "mode" "RVVMF2x7QI") (symbol_ref "riscv_vector::LMUL_F2")
229 (eq_attr "mode" "RVVMF4x7QI") (symbol_ref "riscv_vector::LMUL_F4")
230 (eq_attr "mode" "RVVMF8x7QI") (symbol_ref "riscv_vector::LMUL_F8")
231 (eq_attr "mode" "RVVM1x6QI") (symbol_ref "riscv_vector::LMUL_1")
232 (eq_attr "mode" "RVVMF2x6QI") (symbol_ref "riscv_vector::LMUL_F2")
233 (eq_attr "mode" "RVVMF4x6QI") (symbol_ref "riscv_vector::LMUL_F4")
234 (eq_attr "mode" "RVVMF8x6QI") (symbol_ref "riscv_vector::LMUL_F8")
235 (eq_attr "mode" "RVVM1x5QI") (symbol_ref "riscv_vector::LMUL_1")
236 (eq_attr "mode" "RVVMF2x5QI") (symbol_ref "riscv_vector::LMUL_F2")
237 (eq_attr "mode" "RVVMF4x5QI") (symbol_ref "riscv_vector::LMUL_F4")
238 (eq_attr "mode" "RVVMF8x5QI") (symbol_ref "riscv_vector::LMUL_F8")
239 (eq_attr "mode" "RVVM2x4QI") (symbol_ref "riscv_vector::LMUL_2")
240 (eq_attr "mode" "RVVM1x4QI") (symbol_ref "riscv_vector::LMUL_1")
241 (eq_attr "mode" "RVVMF2x4QI") (symbol_ref "riscv_vector::LMUL_F2")
242 (eq_attr "mode" "RVVMF4x4QI") (symbol_ref "riscv_vector::LMUL_F4")
243 (eq_attr "mode" "RVVMF8x4QI") (symbol_ref "riscv_vector::LMUL_F8")
244 (eq_attr "mode" "RVVM2x3QI") (symbol_ref "riscv_vector::LMUL_2")
245 (eq_attr "mode" "RVVM1x3QI") (symbol_ref "riscv_vector::LMUL_1")
246 (eq_attr "mode" "RVVMF2x3QI") (symbol_ref "riscv_vector::LMUL_F2")
247 (eq_attr "mode" "RVVMF4x3QI") (symbol_ref "riscv_vector::LMUL_F4")
248 (eq_attr "mode" "RVVMF8x3QI") (symbol_ref "riscv_vector::LMUL_F8")
249 (eq_attr "mode" "RVVM4x2QI") (symbol_ref "riscv_vector::LMUL_4")
250 (eq_attr "mode" "RVVM2x2QI") (symbol_ref "riscv_vector::LMUL_2")
251 (eq_attr "mode" "RVVM1x2QI") (symbol_ref "riscv_vector::LMUL_1")
252 (eq_attr "mode" "RVVMF2x2QI") (symbol_ref "riscv_vector::LMUL_F2")
253 (eq_attr "mode" "RVVMF4x2QI") (symbol_ref "riscv_vector::LMUL_F4")
254 (eq_attr "mode" "RVVMF8x2QI") (symbol_ref "riscv_vector::LMUL_F8")
255 (eq_attr "mode" "RVVM1x8HI") (symbol_ref "riscv_vector::LMUL_1")
256 (eq_attr "mode" "RVVMF2x8HI") (symbol_ref "riscv_vector::LMUL_F2")
257 (eq_attr "mode" "RVVMF4x8HI") (symbol_ref "riscv_vector::LMUL_F4")
258 (eq_attr "mode" "RVVM1x7HI") (symbol_ref "riscv_vector::LMUL_1")
259 (eq_attr "mode" "RVVMF2x7HI") (symbol_ref "riscv_vector::LMUL_F2")
260 (eq_attr "mode" "RVVMF4x7HI") (symbol_ref "riscv_vector::LMUL_F4")
261 (eq_attr "mode" "RVVM1x6HI") (symbol_ref "riscv_vector::LMUL_1")
262 (eq_attr "mode" "RVVMF2x6HI") (symbol_ref "riscv_vector::LMUL_F2")
263 (eq_attr "mode" "RVVMF4x6HI") (symbol_ref "riscv_vector::LMUL_F4")
264 (eq_attr "mode" "RVVM1x5HI") (symbol_ref "riscv_vector::LMUL_1")
265 (eq_attr "mode" "RVVMF2x5HI") (symbol_ref "riscv_vector::LMUL_F2")
266 (eq_attr "mode" "RVVMF4x5HI") (symbol_ref "riscv_vector::LMUL_F4")
267 (eq_attr "mode" "RVVM2x4HI") (symbol_ref "riscv_vector::LMUL_2")
268 (eq_attr "mode" "RVVM1x4HI") (symbol_ref "riscv_vector::LMUL_1")
269 (eq_attr "mode" "RVVMF2x4HI") (symbol_ref "riscv_vector::LMUL_F2")
270 (eq_attr "mode" "RVVMF4x4HI") (symbol_ref "riscv_vector::LMUL_F4")
271 (eq_attr "mode" "RVVM2x3HI") (symbol_ref "riscv_vector::LMUL_2")
272 (eq_attr "mode" "RVVM1x3HI") (symbol_ref "riscv_vector::LMUL_1")
273 (eq_attr "mode" "RVVMF2x3HI") (symbol_ref "riscv_vector::LMUL_F2")
274 (eq_attr "mode" "RVVMF4x3HI") (symbol_ref "riscv_vector::LMUL_F4")
275 (eq_attr "mode" "RVVM4x2HI") (symbol_ref "riscv_vector::LMUL_4")
276 (eq_attr "mode" "RVVM2x2HI") (symbol_ref "riscv_vector::LMUL_2")
277 (eq_attr "mode" "RVVM1x2HI") (symbol_ref "riscv_vector::LMUL_1")
278 (eq_attr "mode" "RVVMF2x2HI") (symbol_ref "riscv_vector::LMUL_F2")
279 (eq_attr "mode" "RVVMF4x2HI") (symbol_ref "riscv_vector::LMUL_F4")
280 (eq_attr "mode" "RVVM1x8BF") (symbol_ref "riscv_vector::LMUL_1")
281 (eq_attr "mode" "RVVMF2x8BF") (symbol_ref "riscv_vector::LMUL_F2")
282 (eq_attr "mode" "RVVMF4x8BF") (symbol_ref "riscv_vector::LMUL_F4")
283 (eq_attr "mode" "RVVM1x7BF") (symbol_ref "riscv_vector::LMUL_1")
284 (eq_attr "mode" "RVVMF2x7BF") (symbol_ref "riscv_vector::LMUL_F2")
285 (eq_attr "mode" "RVVMF4x7BF") (symbol_ref "riscv_vector::LMUL_F4")
286 (eq_attr "mode" "RVVM1x6BF") (symbol_ref "riscv_vector::LMUL_1")
287 (eq_attr "mode" "RVVMF2x6BF") (symbol_ref "riscv_vector::LMUL_F2")
288 (eq_attr "mode" "RVVMF4x6BF") (symbol_ref "riscv_vector::LMUL_F4")
289 (eq_attr "mode" "RVVM1x5BF") (symbol_ref "riscv_vector::LMUL_1")
290 (eq_attr "mode" "RVVMF2x5BF") (symbol_ref "riscv_vector::LMUL_F2")
291 (eq_attr "mode" "RVVMF4x5BF") (symbol_ref "riscv_vector::LMUL_F4")
292 (eq_attr "mode" "RVVM2x4BF") (symbol_ref "riscv_vector::LMUL_2")
293 (eq_attr "mode" "RVVM1x4BF") (symbol_ref "riscv_vector::LMUL_1")
294 (eq_attr "mode" "RVVMF2x4BF") (symbol_ref "riscv_vector::LMUL_F2")
295 (eq_attr "mode" "RVVMF4x4BF") (symbol_ref "riscv_vector::LMUL_F4")
296 (eq_attr "mode" "RVVM2x3BF") (symbol_ref "riscv_vector::LMUL_2")
297 (eq_attr "mode" "RVVM1x3BF") (symbol_ref "riscv_vector::LMUL_1")
298 (eq_attr "mode" "RVVMF2x3BF") (symbol_ref "riscv_vector::LMUL_F2")
299 (eq_attr "mode" "RVVMF4x3BF") (symbol_ref "riscv_vector::LMUL_F4")
300 (eq_attr "mode" "RVVM4x2BF") (symbol_ref "riscv_vector::LMUL_4")
301 (eq_attr "mode" "RVVM2x2BF") (symbol_ref "riscv_vector::LMUL_2")
302 (eq_attr "mode" "RVVM1x2BF") (symbol_ref "riscv_vector::LMUL_1")
303 (eq_attr "mode" "RVVMF2x2BF") (symbol_ref "riscv_vector::LMUL_F2")
304 (eq_attr "mode" "RVVMF4x2BF") (symbol_ref "riscv_vector::LMUL_F4")
305 (eq_attr "mode" "RVVM1x8HF") (symbol_ref "riscv_vector::LMUL_1")
306 (eq_attr "mode" "RVVMF2x8HF") (symbol_ref "riscv_vector::LMUL_F2")
307 (eq_attr "mode" "RVVMF4x8HF") (symbol_ref "riscv_vector::LMUL_F4")
308 (eq_attr "mode" "RVVM1x7HF") (symbol_ref "riscv_vector::LMUL_1")
309 (eq_attr "mode" "RVVMF2x7HF") (symbol_ref "riscv_vector::LMUL_F2")
310 (eq_attr "mode" "RVVMF4x7HF") (symbol_ref "riscv_vector::LMUL_F4")
311 (eq_attr "mode" "RVVM1x6HF") (symbol_ref "riscv_vector::LMUL_1")
312 (eq_attr "mode" "RVVMF2x6HF") (symbol_ref "riscv_vector::LMUL_F2")
313 (eq_attr "mode" "RVVMF4x6HF") (symbol_ref "riscv_vector::LMUL_F4")
314 (eq_attr "mode" "RVVM1x5HF") (symbol_ref "riscv_vector::LMUL_1")
315 (eq_attr "mode" "RVVMF2x5HF") (symbol_ref "riscv_vector::LMUL_F2")
316 (eq_attr "mode" "RVVMF4x5HF") (symbol_ref "riscv_vector::LMUL_F4")
317 (eq_attr "mode" "RVVM2x4HF") (symbol_ref "riscv_vector::LMUL_2")
318 (eq_attr "mode" "RVVM1x4HF") (symbol_ref "riscv_vector::LMUL_1")
319 (eq_attr "mode" "RVVMF2x4HF") (symbol_ref "riscv_vector::LMUL_F2")
320 (eq_attr "mode" "RVVMF4x4HF") (symbol_ref "riscv_vector::LMUL_F4")
321 (eq_attr "mode" "RVVM2x3HF") (symbol_ref "riscv_vector::LMUL_2")
322 (eq_attr "mode" "RVVM1x3HF") (symbol_ref "riscv_vector::LMUL_1")
323 (eq_attr "mode" "RVVMF2x3HF") (symbol_ref "riscv_vector::LMUL_F2")
324 (eq_attr "mode" "RVVMF4x3HF") (symbol_ref "riscv_vector::LMUL_F4")
325 (eq_attr "mode" "RVVM4x2HF") (symbol_ref "riscv_vector::LMUL_4")
326 (eq_attr "mode" "RVVM2x2HF") (symbol_ref "riscv_vector::LMUL_2")
327 (eq_attr "mode" "RVVM1x2HF") (symbol_ref "riscv_vector::LMUL_1")
328 (eq_attr "mode" "RVVMF2x2HF") (symbol_ref "riscv_vector::LMUL_F2")
329 (eq_attr "mode" "RVVMF4x2HF") (symbol_ref "riscv_vector::LMUL_F4")
330 (eq_attr "mode" "RVVM1x8SI") (symbol_ref "riscv_vector::LMUL_1")
331 (eq_attr "mode" "RVVMF2x8SI") (symbol_ref "riscv_vector::LMUL_F2")
332 (eq_attr "mode" "RVVM1x7SI") (symbol_ref "riscv_vector::LMUL_1")
333 (eq_attr "mode" "RVVMF2x7SI") (symbol_ref "riscv_vector::LMUL_F2")
334 (eq_attr "mode" "RVVM1x6SI") (symbol_ref "riscv_vector::LMUL_1")
335 (eq_attr "mode" "RVVMF2x6SI") (symbol_ref "riscv_vector::LMUL_F2")
336 (eq_attr "mode" "RVVM1x5SI") (symbol_ref "riscv_vector::LMUL_1")
337 (eq_attr "mode" "RVVMF2x5SI") (symbol_ref "riscv_vector::LMUL_F2")
338 (eq_attr "mode" "RVVM2x4SI") (symbol_ref "riscv_vector::LMUL_2")
339 (eq_attr "mode" "RVVM1x4SI") (symbol_ref "riscv_vector::LMUL_1")
340 (eq_attr "mode" "RVVMF2x4SI") (symbol_ref "riscv_vector::LMUL_F2")
341 (eq_attr "mode" "RVVM2x3SI") (symbol_ref "riscv_vector::LMUL_2")
342 (eq_attr "mode" "RVVM1x3SI") (symbol_ref "riscv_vector::LMUL_1")
343 (eq_attr "mode" "RVVMF2x3SI") (symbol_ref "riscv_vector::LMUL_F2")
344 (eq_attr "mode" "RVVM4x2SI") (symbol_ref "riscv_vector::LMUL_4")
345 (eq_attr "mode" "RVVM2x2SI") (symbol_ref "riscv_vector::LMUL_2")
346 (eq_attr "mode" "RVVM1x2SI") (symbol_ref "riscv_vector::LMUL_1")
347 (eq_attr "mode" "RVVMF2x2SI") (symbol_ref "riscv_vector::LMUL_F2")
348 (eq_attr "mode" "RVVM1x8SF") (symbol_ref "riscv_vector::LMUL_1")
349 (eq_attr "mode" "RVVMF2x8SF") (symbol_ref "riscv_vector::LMUL_F2")
350 (eq_attr "mode" "RVVM1x7SF") (symbol_ref "riscv_vector::LMUL_1")
351 (eq_attr "mode" "RVVMF2x7SF") (symbol_ref "riscv_vector::LMUL_F2")
352 (eq_attr "mode" "RVVM1x6SF") (symbol_ref "riscv_vector::LMUL_1")
353 (eq_attr "mode" "RVVMF2x6SF") (symbol_ref "riscv_vector::LMUL_F2")
354 (eq_attr "mode" "RVVM1x5SF") (symbol_ref "riscv_vector::LMUL_1")
355 (eq_attr "mode" "RVVMF2x5SF") (symbol_ref "riscv_vector::LMUL_F2")
356 (eq_attr "mode" "RVVM2x4SF") (symbol_ref "riscv_vector::LMUL_2")
357 (eq_attr "mode" "RVVM1x4SF") (symbol_ref "riscv_vector::LMUL_1")
358 (eq_attr "mode" "RVVMF2x4SF") (symbol_ref "riscv_vector::LMUL_F2")
359 (eq_attr "mode" "RVVM2x3SF") (symbol_ref "riscv_vector::LMUL_2")
360 (eq_attr "mode" "RVVM1x3SF") (symbol_ref "riscv_vector::LMUL_1")
361 (eq_attr "mode" "RVVMF2x3SF") (symbol_ref "riscv_vector::LMUL_F2")
362 (eq_attr "mode" "RVVM4x2SF") (symbol_ref "riscv_vector::LMUL_4")
363 (eq_attr "mode" "RVVM2x2SF") (symbol_ref "riscv_vector::LMUL_2")
364 (eq_attr "mode" "RVVM1x2SF") (symbol_ref "riscv_vector::LMUL_1")
365 (eq_attr "mode" "RVVMF2x2SF") (symbol_ref "riscv_vector::LMUL_F2")
366 (eq_attr "mode" "RVVM1x8DI") (symbol_ref "riscv_vector::LMUL_1")
367 (eq_attr "mode" "RVVM1x7DI") (symbol_ref "riscv_vector::LMUL_1")
368 (eq_attr "mode" "RVVM1x6DI") (symbol_ref "riscv_vector::LMUL_1")
369 (eq_attr "mode" "RVVM1x5DI") (symbol_ref "riscv_vector::LMUL_1")
370 (eq_attr "mode" "RVVM2x4DI") (symbol_ref "riscv_vector::LMUL_2")
371 (eq_attr "mode" "RVVM1x4DI") (symbol_ref "riscv_vector::LMUL_1")
372 (eq_attr "mode" "RVVM2x3DI") (symbol_ref "riscv_vector::LMUL_2")
373 (eq_attr "mode" "RVVM1x3DI") (symbol_ref "riscv_vector::LMUL_1")
374 (eq_attr "mode" "RVVM4x2DI") (symbol_ref "riscv_vector::LMUL_4")
375 (eq_attr "mode" "RVVM2x2DI") (symbol_ref "riscv_vector::LMUL_2")
376 (eq_attr "mode" "RVVM1x2DI") (symbol_ref "riscv_vector::LMUL_1")
377 (eq_attr "mode" "RVVM1x8DF") (symbol_ref "riscv_vector::LMUL_1")
378 (eq_attr "mode" "RVVM1x7DF") (symbol_ref "riscv_vector::LMUL_1")
379 (eq_attr "mode" "RVVM1x6DF") (symbol_ref "riscv_vector::LMUL_1")
380 (eq_attr "mode" "RVVM1x5DF") (symbol_ref "riscv_vector::LMUL_1")
381 (eq_attr "mode" "RVVM2x4DF") (symbol_ref "riscv_vector::LMUL_2")
382 (eq_attr "mode" "RVVM1x4DF") (symbol_ref "riscv_vector::LMUL_1")
383 (eq_attr "mode" "RVVM2x3DF") (symbol_ref "riscv_vector::LMUL_2")
384 (eq_attr "mode" "RVVM1x3DF") (symbol_ref "riscv_vector::LMUL_1")
385 (eq_attr "mode" "RVVM4x2DF") (symbol_ref "riscv_vector::LMUL_4")
386 (eq_attr "mode" "RVVM2x2DF") (symbol_ref "riscv_vector::LMUL_2")
387 (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1")
389 ;; VLS modes.
390 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_vlmul(E_V1QImode)")
391 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_vlmul(E_V2QImode)")
392 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_vlmul(E_V4QImode)")
393 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_vlmul(E_V8QImode)")
394 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
395 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_vlmul(E_V32QImode)")
396 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_vlmul(E_V64QImode)")
397 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_vlmul(E_V128QImode)")
398 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_vlmul(E_V256QImode)")
399 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_vlmul(E_V512QImode)")
400 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_vlmul(E_V1024QImode)")
401 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_vlmul(E_V2048QImode)")
402 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_vlmul(E_V4096QImode)")
403 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_vlmul(E_V1HImode)")
404 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_vlmul(E_V2HImode)")
405 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_vlmul(E_V4HImode)")
406 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_vlmul(E_V8HImode)")
407 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_vlmul(E_V16HImode)")
408 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_vlmul(E_V32HImode)")
409 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_vlmul(E_V64HImode)")
410 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_vlmul(E_V128HImode)")
411 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_vlmul(E_V256HImode)")
412 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_vlmul(E_V512HImode)")
413 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_vlmul(E_V1024HImode)")
414 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_vlmul(E_V2048HImode)")
415 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_vlmul(E_V1SImode)")
416 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_vlmul(E_V2SImode)")
417 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_vlmul(E_V4SImode)")
418 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_vlmul(E_V8SImode)")
419 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_vlmul(E_V16SImode)")
420 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_vlmul(E_V32SImode)")
421 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_vlmul(E_V64SImode)")
422 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_vlmul(E_V128SImode)")
423 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_vlmul(E_V256SImode)")
424 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_vlmul(E_V512SImode)")
425 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_vlmul(E_V1024SImode)")
426 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_vlmul(E_V1DImode)")
427 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_vlmul(E_V2DImode)")
428 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_vlmul(E_V4DImode)")
429 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_vlmul(E_V8DImode)")
430 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_vlmul(E_V16DImode)")
431 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_vlmul(E_V32DImode)")
432 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_vlmul(E_V64DImode)")
433 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_vlmul(E_V128DImode)")
434 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_vlmul(E_V256DImode)")
435 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_vlmul(E_V512DImode)")
436 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_vlmul(E_V1HFmode)")
437 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_vlmul(E_V2HFmode)")
438 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_vlmul(E_V4HFmode)")
439 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_vlmul(E_V8HFmode)")
440 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_vlmul(E_V16HFmode)")
441 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_vlmul(E_V32HFmode)")
442 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_vlmul(E_V64HFmode)")
443 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_vlmul(E_V128HFmode)")
444 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_vlmul(E_V256HFmode)")
445 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_vlmul(E_V512HFmode)")
446 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_vlmul(E_V1024HFmode)")
447 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_vlmul(E_V2048HFmode)")
448 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_vlmul(E_V1SFmode)")
449 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_vlmul(E_V2SFmode)")
450 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_vlmul(E_V4SFmode)")
451 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_vlmul(E_V8SFmode)")
452 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_vlmul(E_V16SFmode)")
453 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_vlmul(E_V32SFmode)")
454 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_vlmul(E_V64SFmode)")
455 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_vlmul(E_V128SFmode)")
456 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_vlmul(E_V256SFmode)")
457 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_vlmul(E_V512SFmode)")
458 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_vlmul(E_V1024SFmode)")
459 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_vlmul(E_V1DFmode)")
460 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_vlmul(E_V2DFmode)")
461 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_vlmul(E_V4DFmode)")
462 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_vlmul(E_V8DFmode)")
463 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_vlmul(E_V16DFmode)")
464 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_vlmul(E_V32DFmode)")
465 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_vlmul(E_V64DFmode)")
466 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_vlmul(E_V128DFmode)")
467 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_vlmul(E_V256DFmode)")
468 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_vlmul(E_V512DFmode)")]
469 (const_int INVALID_ATTRIBUTE)))
471 ;; It is valid for instruction that require sew/lmul ratio.
472 (define_attr "ratio" ""
473 (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\
474 vialu,vshift,vicmp,vimul,vidiv,vsalu,\
475 vext,viwalu,viwmul,vicalu,vnshift,\
476 vimuladd,vimerge,vaalu,vsmul,vsshift,\
477 vnclip,viminmax,viwmuladd,\
478 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\
479 vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\
480 vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
481 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
482 vfncvtftof,vfmuladd,vfwmuladd,vfclass,vired,\
483 viwred,vfredu,vfredo,vfwredu,vfwredo,vimovvx,\
484 vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\
485 vislide1up,vislide1down,vfslide1up,vfslide1down,\
486 vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox,\
487 vandn,vbrev,vbrev8,vrev8,vcpop,vclz,vctz,vrol,vror,vwsll,\
488 vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
489 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\
490 vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
491 (const_int INVALID_ATTRIBUTE)
492 (and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\
493 vlsegdff,vssegtux,vlsegdox,vlsegdux")
494 (match_test "TARGET_XTHEADVECTOR"))
495 (const_int INVALID_ATTRIBUTE)
496 (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
497 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (const_int 2)
498 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (const_int 4)
499 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (const_int 8)
500 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (const_int 16)
501 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (const_int 32)
502 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (const_int 64)
503 (eq_attr "mode" "RVVM8HI") (const_int 2)
504 (eq_attr "mode" "RVVM4HI") (const_int 4)
505 (eq_attr "mode" "RVVM2HI") (const_int 8)
506 (eq_attr "mode" "RVVM1HI") (const_int 16)
507 (eq_attr "mode" "RVVMF2HI") (const_int 32)
508 (eq_attr "mode" "RVVMF4HI") (const_int 64)
509 (eq_attr "mode" "RVVM8BF") (const_int 2)
510 (eq_attr "mode" "RVVM4BF") (const_int 4)
511 (eq_attr "mode" "RVVM2BF") (const_int 8)
512 (eq_attr "mode" "RVVM1BF") (const_int 16)
513 (eq_attr "mode" "RVVMF2BF") (const_int 32)
514 (eq_attr "mode" "RVVMF4BF") (const_int 64)
515 (eq_attr "mode" "RVVM8HF") (const_int 2)
516 (eq_attr "mode" "RVVM4HF") (const_int 4)
517 (eq_attr "mode" "RVVM2HF") (const_int 8)
518 (eq_attr "mode" "RVVM1HF") (const_int 16)
519 (eq_attr "mode" "RVVMF2HF") (const_int 32)
520 (eq_attr "mode" "RVVMF4HF") (const_int 64)
521 (eq_attr "mode" "RVVM8SI") (const_int 4)
522 (eq_attr "mode" "RVVM4SI") (const_int 8)
523 (eq_attr "mode" "RVVM2SI") (const_int 16)
524 (eq_attr "mode" "RVVM1SI") (const_int 32)
525 (eq_attr "mode" "RVVMF2SI") (const_int 64)
526 (eq_attr "mode" "RVVM8SF") (const_int 4)
527 (eq_attr "mode" "RVVM4SF") (const_int 8)
528 (eq_attr "mode" "RVVM2SF") (const_int 16)
529 (eq_attr "mode" "RVVM1SF") (const_int 32)
530 (eq_attr "mode" "RVVMF2SF") (const_int 64)
531 (eq_attr "mode" "RVVM8DI") (const_int 8)
532 (eq_attr "mode" "RVVM4DI") (const_int 16)
533 (eq_attr "mode" "RVVM2DI") (const_int 32)
534 (eq_attr "mode" "RVVM1DI") (const_int 64)
535 (eq_attr "mode" "RVVM8DF") (const_int 8)
536 (eq_attr "mode" "RVVM4DF") (const_int 16)
537 (eq_attr "mode" "RVVM2DF") (const_int 32)
538 (eq_attr "mode" "RVVM1DF") (const_int 64)
539 (eq_attr "mode" "RVVM1x8QI") (const_int 8)
540 (eq_attr "mode" "RVVMF2x8QI") (const_int 16)
541 (eq_attr "mode" "RVVMF4x8QI") (const_int 32)
542 (eq_attr "mode" "RVVMF8x8QI") (const_int 64)
543 (eq_attr "mode" "RVVM1x7QI") (const_int 8)
544 (eq_attr "mode" "RVVMF2x7QI") (const_int 16)
545 (eq_attr "mode" "RVVMF4x7QI") (const_int 32)
546 (eq_attr "mode" "RVVMF8x7QI") (const_int 64)
547 (eq_attr "mode" "RVVM1x6QI") (const_int 8)
548 (eq_attr "mode" "RVVMF2x6QI") (const_int 16)
549 (eq_attr "mode" "RVVMF4x6QI") (const_int 32)
550 (eq_attr "mode" "RVVMF8x6QI") (const_int 64)
551 (eq_attr "mode" "RVVM1x5QI") (const_int 8)
552 (eq_attr "mode" "RVVMF2x5QI") (const_int 16)
553 (eq_attr "mode" "RVVMF4x5QI") (const_int 32)
554 (eq_attr "mode" "RVVMF8x5QI") (const_int 64)
555 (eq_attr "mode" "RVVM2x4QI") (const_int 4)
556 (eq_attr "mode" "RVVM1x4QI") (const_int 8)
557 (eq_attr "mode" "RVVMF2x4QI") (const_int 16)
558 (eq_attr "mode" "RVVMF4x4QI") (const_int 32)
559 (eq_attr "mode" "RVVMF8x4QI") (const_int 64)
560 (eq_attr "mode" "RVVM2x3QI") (const_int 4)
561 (eq_attr "mode" "RVVM1x3QI") (const_int 8)
562 (eq_attr "mode" "RVVMF2x3QI") (const_int 16)
563 (eq_attr "mode" "RVVMF4x3QI") (const_int 32)
564 (eq_attr "mode" "RVVMF8x3QI") (const_int 64)
565 (eq_attr "mode" "RVVM4x2QI") (const_int 2)
566 (eq_attr "mode" "RVVM2x2QI") (const_int 4)
567 (eq_attr "mode" "RVVM1x2QI") (const_int 8)
568 (eq_attr "mode" "RVVMF2x2QI") (const_int 16)
569 (eq_attr "mode" "RVVMF4x2QI") (const_int 32)
570 (eq_attr "mode" "RVVMF8x2QI") (const_int 64)
571 (eq_attr "mode" "RVVM1x8HI") (const_int 16)
572 (eq_attr "mode" "RVVMF2x8HI") (const_int 32)
573 (eq_attr "mode" "RVVMF4x8HI") (const_int 64)
574 (eq_attr "mode" "RVVM1x7HI") (const_int 16)
575 (eq_attr "mode" "RVVMF2x7HI") (const_int 32)
576 (eq_attr "mode" "RVVMF4x7HI") (const_int 64)
577 (eq_attr "mode" "RVVM1x6HI") (const_int 16)
578 (eq_attr "mode" "RVVMF2x6HI") (const_int 32)
579 (eq_attr "mode" "RVVMF4x6HI") (const_int 64)
580 (eq_attr "mode" "RVVM1x5HI") (const_int 16)
581 (eq_attr "mode" "RVVMF2x5HI") (const_int 32)
582 (eq_attr "mode" "RVVMF4x5HI") (const_int 64)
583 (eq_attr "mode" "RVVM2x4HI") (const_int 8)
584 (eq_attr "mode" "RVVM1x4HI") (const_int 16)
585 (eq_attr "mode" "RVVMF2x4HI") (const_int 32)
586 (eq_attr "mode" "RVVMF4x4HI") (const_int 64)
587 (eq_attr "mode" "RVVM2x3HI") (const_int 8)
588 (eq_attr "mode" "RVVM1x3HI") (const_int 16)
589 (eq_attr "mode" "RVVMF2x3HI") (const_int 32)
590 (eq_attr "mode" "RVVMF4x3HI") (const_int 64)
591 (eq_attr "mode" "RVVM4x2HI") (const_int 4)
592 (eq_attr "mode" "RVVM2x2HI") (const_int 8)
593 (eq_attr "mode" "RVVM1x2HI") (const_int 16)
594 (eq_attr "mode" "RVVMF2x2HI") (const_int 32)
595 (eq_attr "mode" "RVVMF4x2HI") (const_int 64)
596 (eq_attr "mode" "RVVM1x8BF") (const_int 16)
597 (eq_attr "mode" "RVVMF2x8BF") (const_int 32)
598 (eq_attr "mode" "RVVMF4x8BF") (const_int 64)
599 (eq_attr "mode" "RVVM1x7BF") (const_int 16)
600 (eq_attr "mode" "RVVMF2x7BF") (const_int 32)
601 (eq_attr "mode" "RVVMF4x7BF") (const_int 64)
602 (eq_attr "mode" "RVVM1x6BF") (const_int 16)
603 (eq_attr "mode" "RVVMF2x6BF") (const_int 32)
604 (eq_attr "mode" "RVVMF4x6BF") (const_int 64)
605 (eq_attr "mode" "RVVM1x5BF") (const_int 16)
606 (eq_attr "mode" "RVVMF2x5BF") (const_int 32)
607 (eq_attr "mode" "RVVMF4x5BF") (const_int 64)
608 (eq_attr "mode" "RVVM2x4BF") (const_int 8)
609 (eq_attr "mode" "RVVM1x4BF") (const_int 16)
610 (eq_attr "mode" "RVVMF2x4BF") (const_int 32)
611 (eq_attr "mode" "RVVMF4x4BF") (const_int 64)
612 (eq_attr "mode" "RVVM2x3BF") (const_int 8)
613 (eq_attr "mode" "RVVM1x3BF") (const_int 16)
614 (eq_attr "mode" "RVVMF2x3BF") (const_int 32)
615 (eq_attr "mode" "RVVMF4x3BF") (const_int 64)
616 (eq_attr "mode" "RVVM4x2BF") (const_int 4)
617 (eq_attr "mode" "RVVM2x2BF") (const_int 8)
618 (eq_attr "mode" "RVVM1x2BF") (const_int 16)
619 (eq_attr "mode" "RVVMF2x2BF") (const_int 32)
620 (eq_attr "mode" "RVVMF4x2BF") (const_int 64)
621 (eq_attr "mode" "RVVM1x8HF") (const_int 16)
622 (eq_attr "mode" "RVVMF2x8HF") (const_int 32)
623 (eq_attr "mode" "RVVMF4x8HF") (const_int 64)
624 (eq_attr "mode" "RVVM1x7HF") (const_int 16)
625 (eq_attr "mode" "RVVMF2x7HF") (const_int 32)
626 (eq_attr "mode" "RVVMF4x7HF") (const_int 64)
627 (eq_attr "mode" "RVVM1x6HF") (const_int 16)
628 (eq_attr "mode" "RVVMF2x6HF") (const_int 32)
629 (eq_attr "mode" "RVVMF4x6HF") (const_int 64)
630 (eq_attr "mode" "RVVM1x5HF") (const_int 16)
631 (eq_attr "mode" "RVVMF2x5HF") (const_int 32)
632 (eq_attr "mode" "RVVMF4x5HF") (const_int 64)
633 (eq_attr "mode" "RVVM2x4HF") (const_int 8)
634 (eq_attr "mode" "RVVM1x4HF") (const_int 16)
635 (eq_attr "mode" "RVVMF2x4HF") (const_int 32)
636 (eq_attr "mode" "RVVMF4x4HF") (const_int 64)
637 (eq_attr "mode" "RVVM2x3HF") (const_int 8)
638 (eq_attr "mode" "RVVM1x3HF") (const_int 16)
639 (eq_attr "mode" "RVVMF2x3HF") (const_int 32)
640 (eq_attr "mode" "RVVMF4x3HF") (const_int 64)
641 (eq_attr "mode" "RVVM4x2HF") (const_int 4)
642 (eq_attr "mode" "RVVM2x2HF") (const_int 8)
643 (eq_attr "mode" "RVVM1x2HF") (const_int 16)
644 (eq_attr "mode" "RVVMF2x2HF") (const_int 32)
645 (eq_attr "mode" "RVVMF4x2HF") (const_int 64)
646 (eq_attr "mode" "RVVM1x8SI") (const_int 32)
647 (eq_attr "mode" "RVVMF2x8SI") (const_int 64)
648 (eq_attr "mode" "RVVM1x7SI") (const_int 32)
649 (eq_attr "mode" "RVVMF2x7SI") (const_int 64)
650 (eq_attr "mode" "RVVM1x6SI") (const_int 32)
651 (eq_attr "mode" "RVVMF2x6SI") (const_int 64)
652 (eq_attr "mode" "RVVM1x5SI") (const_int 32)
653 (eq_attr "mode" "RVVMF2x5SI") (const_int 64)
654 (eq_attr "mode" "RVVM2x4SI") (const_int 16)
655 (eq_attr "mode" "RVVM1x4SI") (const_int 32)
656 (eq_attr "mode" "RVVMF2x4SI") (const_int 64)
657 (eq_attr "mode" "RVVM2x3SI") (const_int 16)
658 (eq_attr "mode" "RVVM1x3SI") (const_int 32)
659 (eq_attr "mode" "RVVMF2x3SI") (const_int 64)
660 (eq_attr "mode" "RVVM4x2SI") (const_int 8)
661 (eq_attr "mode" "RVVM2x2SI") (const_int 16)
662 (eq_attr "mode" "RVVM1x2SI") (const_int 32)
663 (eq_attr "mode" "RVVMF2x2SI") (const_int 64)
664 (eq_attr "mode" "RVVM1x8SF") (const_int 32)
665 (eq_attr "mode" "RVVMF2x8SF") (const_int 64)
666 (eq_attr "mode" "RVVM1x7SF") (const_int 32)
667 (eq_attr "mode" "RVVMF2x7SF") (const_int 64)
668 (eq_attr "mode" "RVVM1x6SF") (const_int 32)
669 (eq_attr "mode" "RVVMF2x6SF") (const_int 64)
670 (eq_attr "mode" "RVVM1x5SF") (const_int 32)
671 (eq_attr "mode" "RVVMF2x5SF") (const_int 64)
672 (eq_attr "mode" "RVVM2x4SF") (const_int 16)
673 (eq_attr "mode" "RVVM1x4SF") (const_int 32)
674 (eq_attr "mode" "RVVMF2x4SF") (const_int 64)
675 (eq_attr "mode" "RVVM2x3SF") (const_int 16)
676 (eq_attr "mode" "RVVM1x3SF") (const_int 32)
677 (eq_attr "mode" "RVVMF2x3SF") (const_int 64)
678 (eq_attr "mode" "RVVM4x2SF") (const_int 8)
679 (eq_attr "mode" "RVVM2x2SF") (const_int 16)
680 (eq_attr "mode" "RVVM1x2SF") (const_int 32)
681 (eq_attr "mode" "RVVMF2x2SF") (const_int 64)
682 (eq_attr "mode" "RVVM1x8DI") (const_int 64)
683 (eq_attr "mode" "RVVM1x7DI") (const_int 64)
684 (eq_attr "mode" "RVVM1x6DI") (const_int 64)
685 (eq_attr "mode" "RVVM1x5DI") (const_int 64)
686 (eq_attr "mode" "RVVM2x4DI") (const_int 32)
687 (eq_attr "mode" "RVVM1x4DI") (const_int 64)
688 (eq_attr "mode" "RVVM2x3DI") (const_int 32)
689 (eq_attr "mode" "RVVM1x3DI") (const_int 64)
690 (eq_attr "mode" "RVVM4x2DI") (const_int 16)
691 (eq_attr "mode" "RVVM2x2DI") (const_int 32)
692 (eq_attr "mode" "RVVM1x2DI") (const_int 64)
693 (eq_attr "mode" "RVVM1x8DF") (const_int 64)
694 (eq_attr "mode" "RVVM1x7DF") (const_int 64)
695 (eq_attr "mode" "RVVM1x6DF") (const_int 64)
696 (eq_attr "mode" "RVVM1x5DF") (const_int 64)
697 (eq_attr "mode" "RVVM2x4DF") (const_int 32)
698 (eq_attr "mode" "RVVM1x4DF") (const_int 64)
699 (eq_attr "mode" "RVVM2x3DF") (const_int 32)
700 (eq_attr "mode" "RVVM1x3DF") (const_int 64)
701 (eq_attr "mode" "RVVM4x2DF") (const_int 16)
702 (eq_attr "mode" "RVVM2x2DF") (const_int 32)
703 (eq_attr "mode" "RVVM1x2DF") (const_int 64)
705 ;; VLS modes.
706 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_ratio(E_V1QImode)")
707 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_ratio(E_V2QImode)")
708 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_ratio(E_V4QImode)")
709 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_ratio(E_V8QImode)")
710 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_ratio(E_V16QImode)")
711 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_ratio(E_V32QImode)")
712 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_ratio(E_V64QImode)")
713 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_ratio(E_V128QImode)")
714 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_ratio(E_V256QImode)")
715 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_ratio(E_V512QImode)")
716 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_ratio(E_V1024QImode)")
717 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_ratio(E_V2048QImode)")
718 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_ratio(E_V4096QImode)")
719 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_ratio(E_V1HImode)")
720 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_ratio(E_V2HImode)")
721 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_ratio(E_V4HImode)")
722 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_ratio(E_V8HImode)")
723 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_ratio(E_V16HImode)")
724 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_ratio(E_V32HImode)")
725 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_ratio(E_V64HImode)")
726 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_ratio(E_V128HImode)")
727 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_ratio(E_V256HImode)")
728 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_ratio(E_V512HImode)")
729 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_ratio(E_V1024HImode)")
730 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_ratio(E_V2048HImode)")
731 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_ratio(E_V1SImode)")
732 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_ratio(E_V2SImode)")
733 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_ratio(E_V4SImode)")
734 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_ratio(E_V8SImode)")
735 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_ratio(E_V16SImode)")
736 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_ratio(E_V32SImode)")
737 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_ratio(E_V64SImode)")
738 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_ratio(E_V128SImode)")
739 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_ratio(E_V256SImode)")
740 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_ratio(E_V512SImode)")
741 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_ratio(E_V1024SImode)")
742 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_ratio(E_V1DImode)")
743 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_ratio(E_V2DImode)")
744 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_ratio(E_V4DImode)")
745 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_ratio(E_V8DImode)")
746 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_ratio(E_V16DImode)")
747 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_ratio(E_V32DImode)")
748 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_ratio(E_V64DImode)")
749 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_ratio(E_V128DImode)")
750 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_ratio(E_V256DImode)")
751 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_ratio(E_V512DImode)")
752 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_ratio(E_V1HFmode)")
753 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_ratio(E_V2HFmode)")
754 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_ratio(E_V4HFmode)")
755 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_ratio(E_V8HFmode)")
756 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_ratio(E_V16HFmode)")
757 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_ratio(E_V32HFmode)")
758 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_ratio(E_V64HFmode)")
759 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_ratio(E_V128HFmode)")
760 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_ratio(E_V256HFmode)")
761 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_ratio(E_V512HFmode)")
762 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_ratio(E_V1024HFmode)")
763 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_ratio(E_V2048HFmode)")
764 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_ratio(E_V1SFmode)")
765 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_ratio(E_V2SFmode)")
766 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_ratio(E_V4SFmode)")
767 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_ratio(E_V8SFmode)")
768 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_ratio(E_V16SFmode)")
769 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_ratio(E_V32SFmode)")
770 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_ratio(E_V64SFmode)")
771 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_ratio(E_V128SFmode)")
772 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_ratio(E_V256SFmode)")
773 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_ratio(E_V512SFmode)")
774 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_ratio(E_V1024SFmode)")
775 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_ratio(E_V1DFmode)")
776 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_ratio(E_V2DFmode)")
777 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_ratio(E_V4DFmode)")
778 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_ratio(E_V8DFmode)")
779 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_ratio(E_V16DFmode)")
780 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_ratio(E_V32DFmode)")
781 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_ratio(E_V64DFmode)")
782 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_ratio(E_V128DFmode)")
783 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_ratio(E_V256DFmode)")
784 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_ratio(E_V512DFmode)")]
785 (const_int INVALID_ATTRIBUTE)))
787 ;; The index of operand[] to get the merge op.
788 (define_attr "merge_op_idx" ""
789 (cond [(eq_attr "type" "vlde,vimov,vfmov,vldm,vlds,vmalu,vldux,vldox,vicmp,\
790 vialu,vshift,viminmax,vimul,vidiv,vsalu,vext,viwalu,\
791 viwmul,vnshift,vaalu,vsmul,vsshift,vnclip,vmsfs,\
792 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
793 vfsqrt,vfrecp,vfsgnj,vfcmp,vfcvtitof,vfcvtftoi,vfwcvtitof,\
794 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,\
795 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\
796 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
797 vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,\
798 vandn,vbrev,vbrev8,vrev8,vrol,vror,vwsll,vclmul,vclmulh,\
799 vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
800 (const_int 2)
802 (eq_attr "type" "vimerge,vfmerge,vcompress,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,\
803 vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c")
804 (const_int 1)
806 (eq_attr "type" "vimuladd,vfmuladd")
807 (const_int 2)]
808 (const_int INVALID_ATTRIBUTE)))
810 ;; The index of operand[] represents the machine mode of the instruction.
811 (define_attr "mode_idx" ""
812 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vldff,vldr,vstr,\
813 vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vialu,vext,vicalu,\
814 vshift,vicmp,viminmax,vimul,vidiv,vimuladd,vimerge,vimov,\
815 vsalu,vaalu,vsmul,vsshift,vfalu,vfmul,vfdiv,vfmuladd,vfsqrt,vfrecp,\
816 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
817 vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\
818 vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
819 vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz")
820 (const_int 0)
822 (eq_attr "type" "vimovvx,vfmovvf")
823 (const_int 1)
825 (eq_attr "type" "vssegte,vmpop,vmffs")
826 (const_int 2)
828 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi,
829 vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vwsll")
830 (const_int 3)
832 (eq_attr "type" "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd")
833 (const_int 4)]
834 (const_int INVALID_ATTRIBUTE)))
836 ;; The index of operand[] to get the avl op.
837 (define_attr "vl_op_idx" ""
838 (cond [(eq_attr "type" "vlde,vste,vimov,vfmov,vldm,vstm,vmalu,vsts,vstux,\
839 vstox,vext,vmsfs,vmiota,vfsqrt,vfrecp,vfcvtitof,vldff,\
840 vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
841 vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\
842 vlsegde,vssegts,vssegtux,vssegtox,vlsegdff,vbrev,vbrev8,vrev8,\
843 vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c,\
844 vfncvtbf16,vfwcvtbf16")
845 (const_int 4)
847 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
848 ;; wheras it is pred_strided_load if operands[3] is vector mode.
849 (eq_attr "type" "vlds")
850 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
851 (const_int 5)
852 (const_int 4))
854 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
855 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
856 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
857 vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
858 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
859 vgather,viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
860 vror,vwsll,vclmul,vclmulh,vfwmaccbf16")
861 (const_int 5)
863 (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd")
864 (const_int 6)
866 (eq_attr "type" "vmpop,vmffs,vmidx,vssegte,vcpop,vclz,vctz,vgmul,vaesef,vaesem,vaesdf,\
867 vaesdm,vaesz,vsm4r")
868 (const_int 3)]
869 (const_int INVALID_ATTRIBUTE)))
871 ;; The tail policy op value.
872 (define_attr "ta" ""
873 (cond [(eq_attr "type" "vlde,vimov,vfmov,vext,vmiota,vfsqrt,vfrecp,\
874 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\
875 vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\
876 vcompress,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,vghsh,\
877 vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm3me,vsm3c,\
878 vfncvtbf16,vfwcvtbf16")
879 (symbol_ref "riscv_vector::get_ta(operands[5])")
881 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
882 ;; wheras it is pred_strided_load if operands[3] is vector mode.
883 (eq_attr "type" "vlds")
884 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
885 (symbol_ref "riscv_vector::get_ta(operands[6])")
886 (symbol_ref "riscv_vector::get_ta(operands[5])"))
888 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
889 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
890 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,\
891 vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\
892 vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
893 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
894 vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vwsll,vclmul,vclmulh,\
895 vfwmaccbf16")
896 (symbol_ref "riscv_vector::get_ta(operands[6])")
898 (eq_attr "type" "vimuladd,vfmuladd")
899 (symbol_ref "riscv_vector::get_ta(operands[7])")
901 (eq_attr "type" "vmidx,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,vsm4r")
902 (symbol_ref "riscv_vector::get_ta(operands[4])")]
903 (const_int INVALID_ATTRIBUTE)))
905 ;; The mask policy op value.
906 (define_attr "ma" ""
907 (cond [(eq_attr "type" "vlde,vext,vmiota,vfsqrt,vfrecp,vfcvtitof,vfcvtftoi,\
908 vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
909 vfncvtftof,vfclass,vldff,vlsegde,vlsegdff,vbrev,vbrev8,vrev8,\
910 vfncvtbf16,vfwcvtbf16")
911 (symbol_ref "riscv_vector::get_ma(operands[6])")
913 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
914 ;; wheras it is pred_strided_load if operands[3] is vector mode.
915 (eq_attr "type" "vlds")
916 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
917 (symbol_ref "riscv_vector::get_ma(operands[7])")
918 (symbol_ref "riscv_vector::get_ma(operands[6])"))
920 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
921 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
922 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,\
923 vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
924 vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\
925 viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox,vandn,vrol,\
926 vror,vwsll,vclmul,vclmulh,vfwmaccbf16")
927 (symbol_ref "riscv_vector::get_ma(operands[7])")
929 (eq_attr "type" "vimuladd,vfmuladd")
930 (symbol_ref "riscv_vector::get_ma(operands[8])")
932 (eq_attr "type" "vmsfs,vmidx")
933 (symbol_ref "riscv_vector::get_ma(operands[5])")]
934 (const_int INVALID_ATTRIBUTE)))
936 ;; The avl type value.
937 (define_attr "avl_type_idx" ""
938 (cond [(eq_attr "type" "vlde,vldff,vste,vimov,vfmov,vext,vimerge,\
939 vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
940 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
941 vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
942 vimovxv,vfmovfv,vlsegde,vlsegdff,vmiota,vbrev,vbrev8,vrev8,\
943 vfncvtbf16,vfwcvtbf16")
944 (const_int 7)
945 (eq_attr "type" "vldm,vstm,vmalu,vmalu,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaesz,\
946 vsm4r")
947 (const_int 5)
949 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
950 ;; wheras it is pred_strided_load if operands[3] is vector mode.
951 (eq_attr "type" "vlds")
952 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
953 (const_int 8)
954 (const_int 7))
956 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
957 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
958 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
959 vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\
960 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
961 vlsegds,vlsegdux,vlsegdox,vandn,vrol,vror,vclmul,vclmulh,vwsll,\
962 vfwmaccbf16")
963 (const_int 8)
964 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox")
965 (const_int 5)
967 (eq_attr "type" "vimuladd,vfmuladd")
968 (const_int 9)
970 (eq_attr "type" "vmsfs,vmidx,vcompress,vghsh,vaeskf1,vaeskf2,vsha2ms,vsha2ch,vsha2cl,\
971 vsm4k,vsm3me,vsm3c")
972 (const_int 6)
974 (eq_attr "type" "vmpop,vmffs,vssegte,vcpop,vclz,vctz")
975 (const_int 4)]
976 (const_int INVALID_ATTRIBUTE)))
978 ;; Defines rounding mode of an fixed-point operation.
980 (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
981 (cond [(eq_attr "type" "vaalu,vsmul,vsshift,vnclip")
982 (cond
983 [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
984 (const_string "rnu")
986 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
987 (const_string "rne")
989 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
990 (const_string "rdn")
992 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
993 (const_string "rod")]
994 (const_string "none"))]
995 (const_string "none")))
997 ;; Defines rounding mode of an floating-point operation.
998 (define_attr "frm_mode" ""
999 (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
1000 (symbol_ref "riscv_vector::FRM_DYN")]
1001 (symbol_ref "riscv_vector::FRM_NONE")))
1003 (include "thead-vector.md")
1005 ;; -----------------------------------------------------------------
1006 ;; ---- Miscellaneous Operations
1007 ;; -----------------------------------------------------------------
1009 (define_insn "@vundefined<mode>"
1010 [(set (match_operand:V 0 "register_operand" "=vr")
1011 (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
1012 "TARGET_VECTOR"
1013 ""
1014 [(set_attr "type" "vector")])
1016 (define_insn "@vundefined<mode>"
1017 [(set (match_operand:VB 0 "register_operand" "=vr")
1018 (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
1019 "TARGET_VECTOR"
1020 ""
1021 [(set_attr "type" "vector")])
1023 (define_insn "@vundefined<mode>"
1024 [(set (match_operand:VT 0 "register_operand" "=vr")
1025 (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
1026 "TARGET_VECTOR"
1027 ""
1028 [(set_attr "type" "vector")])
1030 (define_expand "@vreinterpret<mode>"
1031 [(set (match_operand:V 0 "register_operand")
1032 (match_operand 1 "vector_any_register_operand"))]
1033 "TARGET_VECTOR"
1034 {
1035 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
1036 DONE;
1037 }
1038 )
1040 (define_expand "@vreinterpret<mode>"
1041 [(set (match_operand:VB 0 "register_operand")
1042 (match_operand 1 "vector_any_register_operand"))]
1043 "TARGET_VECTOR"
1044 {
1045 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
1046 DONE;
1047 }
1048 )
1050 ;; This pattern is used to hold the AVL operand for
1051 ;; RVV instructions that implicity use VLMAX AVL.
1052 ;; RVV instruction implicitly use GPR that is ultimately
1053 ;; defined by this pattern is safe for VSETVL pass emit
1054 ;; a vsetvl instruction modify this register after RA.
1055 ;; Case 1:
1056 ;; vlmax_avl a5
1057 ;; ... (across many blocks)
1058 ;; vadd (implicit use a5) ====> emit: vsetvl a5,zero
1059 ;; Case 2:
1060 ;; vlmax_avl a5
1061 ;; ... (across many blocks)
1062 ;; mv a6,a5
1063 ;; ... (across many blocks)
1064 ;; vadd (implicit use a6) ====> emit: vsetvl a6,zero
1065 ;; Case 3:
1066 ;; vlmax_avl a5
1067 ;; ... (across many blocks)
1068 ;; store mem,a5 (spill)
1069 ;; ... (across many blocks)
1070 ;; load a7,mem (spill)
1071 ;; ... (across many blocks)
1072 ;; vadd (implicit use a7) ====> emit: vsetvl a7,zero
1073 ;; Such cases are all safe for VSETVL PASS to emit a vsetvl
1074 ;; instruction that modifies the AVL operand.
1075 (define_insn "@vlmax_avl<mode>"
1076 [(set (match_operand:P 0 "register_operand" "=r")
1077 (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
1078 "TARGET_VECTOR"
1079 ""
1080 [(set_attr "type" "vsetvl_pre")]
1081 )
1083 ;; Set VXRM
1084 (define_insn "vxrmsi"
1085 [(set (reg:SI VXRM_REGNUM)
1086 (match_operand:SI 0 "const_int_operand" "i"))]
1087 "TARGET_VECTOR"
1088 "csrwi\tvxrm,%0"
1089 [(set_attr "type" "wrvxrm")
1090 (set_attr "mode" "SI")])
1092 ;; Set FRM
1093 (define_insn "fsrmsi_backup"
1094 [(set (match_operand:SI 0 "register_operand" "=r,r")
1095 (reg:SI FRM_REGNUM))
1096 (set (reg:SI FRM_REGNUM)
1097 (match_operand:SI 1 "reg_or_int_operand" "r,i"))]
1098 "TARGET_VECTOR"
1099 "@
1100 fsrm\t%0,%1
1101 fsrmi\t%0,%1"
1102 [(set_attr "type" "wrfrm,wrfrm")
1103 (set_attr "mode" "SI")]
1104 )
1106 (define_insn "fsrmsi_restore"
1107 [(set (reg:SI FRM_REGNUM)
1108 (match_operand:SI 0 "reg_or_int_operand" "r,i"))]
1109 "TARGET_VECTOR"
1110 "@
1111 fsrm\t%0
1112 fsrmi\t%0"
1113 [(set_attr "type" "wrfrm,wrfrm")
1114 (set_attr "mode" "SI")]
1115 )
1117 ;; The volatile fsrmsi restore is used for the exit point for the
1118 ;; dynamic mode switching. It will generate one volatile fsrm a5
1119 ;; which won't be eliminated.
1120 (define_insn "fsrmsi_restore_volatile"
1121 [(set (reg:SI FRM_REGNUM)
1122 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1123 UNSPECV_FRM_RESTORE_EXIT))]
1124 "TARGET_VECTOR"
1125 "fsrm\t%0"
1126 [(set_attr "type" "wrfrm")
1127 (set_attr "mode" "SI")]
1128 )
1130 ;; Read FRM
1131 (define_insn "frrmsi"
1132 [(set (match_operand:SI 0 "register_operand" "=r")
1133 (reg:SI FRM_REGNUM))]
1134 "TARGET_VECTOR"
1135 "frrm\t%0"
1136 [(set_attr "type" "fmove")
1137 (set_attr "mode" "SI")]
1138 )
1140 ;; -----------------------------------------------------------------
1141 ;; ---- Moves Operations
1142 ;; -----------------------------------------------------------------
1144 (define_expand "mov<mode>"
1145 [(set (match_operand:V 0 "reg_or_mem_operand")
1146 (match_operand:V 1 "general_operand"))]
1147 "TARGET_VECTOR"
1148 {
1149 /* For whole register move, we transform the pattern into the format
1150 that excludes the clobber of scratch register.
1152 We include clobber of a scalar scratch register which is going to be
1153 used for emit of vsetvl instruction after reload_completed since we
1154 need vsetvl instruction to set VL/VTYPE global status for fractional
1155 vector load/store.
1157 For example:
1158 [(set (match_operand:RVVMF8QI v24)
1159 (match_operand:RVVMF8QI (mem: a4)))
1160 (clobber (scratch:SI a5))]
1161 ====>> vsetvl a5,zero,e8,mf8
1162 ====>> vle8.v v24,(a4)
1164 Philosophy:
1166 - Clobber a scalar scratch register for each mov<mode>.
1168 - Classify the machine_mode mode = <MODE>mode into 2 class:
1169 Whole register move and fractional register move.
1171 - Transform and remove scratch clobber register for whole
1172 register move so that we can avoid occupying the scalar
1173 registers.
1175 - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
1176 before spilling. The clobber scratch is used by spilling fractional
1177 registers in IRA/LRA so it's too early. */
1178 if (TARGET_XTHEADVECTOR)
1179 {
1180 emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
1181 RVV_VLMAX, GEN_INT(riscv_vector::VLMAX)));
1182 DONE;
1183 }
1185 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1186 DONE;
1187 })
1189 ;; This pattern is used for code-gen for whole register load/stores.
1190 ;; Also applicable for all register moves.
1191 ;; Fractional vector modes load/store are not allowed to match this pattern.
1192 ;; Mask modes load/store are not allowed to match this pattern.
1193 ;; We seperate "*mov<mode>" into "*mov<mode>_whole" and "*mov<mode>_fract" because
1194 ;; we don't want to include fractional load/store in "*mov<mode>" which will
1195 ;; create unexpected patterns in LRA.
1196 ;; For example:
1197 ;; ira rtl:
1198 ;; (insn 20 19 9 2 (set (reg/v:RVVMF4QI 97 v1 [ v1 ])
1199 ;; (reg:RVVMF4QI 134 [ _1 ])) "rvv.c":9:22 571 {*movvnx2qi_fract}
1200 ;; (nil))
1201 ;; When the value of pseudo register 134 of the insn above is discovered already
1202 ;; spilled in the memory during LRA.
1203 ;; LRA will reload this pattern into a memory load instruction pattern.
1204 ;; Because RVVMF4QI is a fractional vector, we want LRA reload this pattern into
1205 ;; (insn 20 19 9 2 (parallel [
1206 ;; (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1207 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8]))
1208 ;; (clobber (reg:SI 14 a4 [149]))])
1209 ;; So that we could be able to emit vsetvl instruction using clobber sratch a4.
1210 ;; To let LRA generate the expected pattern, we should exclude fractional vector
1211 ;; load/store in "*mov<mode>_whole". Otherwise, it will reload this pattern into:
1212 ;; (insn 20 19 9 2 (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1213 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8])))
1214 ;; which is not the pattern we want.
1215 ;; According the facts above, we make "*mov<mode>_whole" includes load/store/move for whole
1216 ;; vector modes according to '-march' and "*mov<mode>_fract" only include fractional vector modes.
1217 (define_insn "*mov<mode>_whole"
1218 [(set (match_operand:V_WHOLE 0 "reg_or_mem_operand" "=vr, m,vr")
1219 (match_operand:V_WHOLE 1 "reg_or_mem_operand" " m,vr,vr"))]
1220 "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
1221 "@
1222 vl%m1re<sew>.v\t%0,%1
1223 vs%m1r.v\t%1,%0
1224 vmv%m1r.v\t%0,%1"
1225 [(set_attr "type" "vldr,vstr,vmov")
1226 (set_attr "mode" "<MODE>")])
1228 (define_insn "*mov<mode>_fract"
1229 [(set (match_operand:V_FRACT 0 "register_operand" "=vr")
1230 (match_operand:V_FRACT 1 "register_operand" " vr"))]
1231 "TARGET_VECTOR"
1232 "vmv1r.v\t%0,%1"
1233 [(set_attr "type" "vmov")
1234 (set_attr "mode" "<MODE>")])
1236 (define_expand "mov<mode>"
1237 [(set (match_operand:VB 0 "reg_or_mem_operand")
1238 (match_operand:VB 1 "general_operand"))]
1239 "TARGET_VECTOR"
1240 {
1241 if (TARGET_XTHEADVECTOR)
1242 {
1243 emit_insn (gen_pred_th_whole_mov (<MODE>mode, operands[0], operands[1],
1244 RVV_VLMAX, GEN_INT(riscv_vector::VLMAX)));
1245 DONE;
1246 }
1248 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1249 DONE;
1250 })
1252 (define_insn "*mov<mode>"
1253 [(set (match_operand:VB 0 "register_operand" "=vr")
1254 (match_operand:VB 1 "register_operand" " vr"))]
1255 "TARGET_VECTOR && !TARGET_XTHEADVECTOR"
1256 "vmv1r.v\t%0,%1"
1257 [(set_attr "type" "vmov")
1258 (set_attr "mode" "<MODE>")])
1260 (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
1261 [(parallel
1262 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
1263 (match_operand:V_FRACT 1 "reg_or_mem_operand"))
1264 (clobber (match_scratch:P 2))])]
1265 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1266 {})
1268 (define_expand "@mov<VB:mode><P:mode>_lra"
1269 [(parallel
1270 [(set (match_operand:VB 0 "reg_or_mem_operand")
1271 (match_operand:VB 1 "reg_or_mem_operand"))
1272 (clobber (match_scratch:P 2))])]
1273 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1274 {})
1276 (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
1277 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
1278 (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
1279 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1280 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1281 "#"
1282 "&& reload_completed"
1283 [(const_int 0)]
1284 {
1285 if (REG_P (operands[0]) && REG_P (operands[1]))
1286 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1287 else
1288 {
1289 riscv_vector::emit_vlmax_vsetvl (<V_FRACT:MODE>mode, operands[2]);
1290 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<V_FRACT:MODE>mode),
1291 riscv_vector::UNARY_OP, operands, operands[2]);
1292 }
1293 DONE;
1294 }
1295 [(set_attr "type" "vector")]
1296 )
1298 (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
1299 [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
1300 (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
1301 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1302 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1303 "#"
1304 "&& reload_completed"
1305 [(const_int 0)]
1306 {
1307 if (REG_P (operands[0]) && REG_P (operands[1]))
1308 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1309 else
1310 {
1311 riscv_vector::emit_vlmax_vsetvl (<VB:MODE>mode, operands[2]);
1312 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<VB:MODE>mode),
1313 riscv_vector::UNARY_MASK_OP, operands, operands[2]);
1314 }
1315 DONE;
1316 }
1317 [(set_attr "type" "vector")]
1318 )
1320 ;; Define tuple modes data movement.
1321 ;; operands[2] is used to save the offset of each subpart.
1322 ;; operands[3] is used to calculate the address for each subpart.
1323 ;; operands[4] is VL of vsevli instruction.
1324 (define_expand "mov<mode>"
1325 [(parallel [(set (match_operand:VT 0 "reg_or_mem_operand")
1326 (match_operand:VT 1 "general_operand"))
1327 (clobber (match_dup 2))
1328 (clobber (match_dup 3))
1329 (clobber (match_dup 4))])]
1330 "TARGET_VECTOR"
1331 {
1332 /* Need to force register if mem <- !reg. */
1333 if (MEM_P (operands[0]) && !REG_P (operands[1]))
1334 operands[1] = force_reg (<MODE>mode, operands[1]);
1336 if (GET_CODE (operands[1]) == CONST_VECTOR)
1337 {
1338 riscv_vector::expand_tuple_move (operands);
1339 DONE;
1340 }
1342 operands[2] = gen_rtx_SCRATCH (Pmode);
1343 operands[3] = gen_rtx_SCRATCH (Pmode);
1344 operands[4] = gen_rtx_SCRATCH (Pmode);
1345 })
1347 (define_insn_and_split "*mov<VT:mode>_<P:mode>"
1348 [(set (match_operand:VT 0 "reg_or_mem_operand" "=vr,vr, m")
1349 (match_operand:VT 1 "reg_or_mem_operand" " vr, m,vr"))
1350 (clobber (match_scratch:P 2 "=X,&r,&r"))
1351 (clobber (match_scratch:P 3 "=X,&r,&r"))
1352 (clobber (match_scratch:P 4 "=X,&r,&r"))]
1353 "TARGET_VECTOR"
1354 "#"
1355 "&& reload_completed"
1356 [(const_int 0)]
1357 {
1358 riscv_vector::expand_tuple_move (operands);
1359 DONE;
1360 }
1361 [(set_attr "type" "vmov,vlde,vste")
1362 (set_attr "mode" "<VT:MODE>")
1363 (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
1364 (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))])
1366 ;; -----------------------------------------------------------------
1367 ;; ---- VLS Moves Operations
1368 ;; -----------------------------------------------------------------
1370 (define_expand "mov<mode>"
1371 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
1372 (match_operand:VLS_AVL_IMM 1 "general_operand"))]
1373 "TARGET_VECTOR"
1374 {
1375 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1376 DONE;
1377 })
1379 (define_insn_and_split "*mov<mode>"
1380 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
1381 (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
1382 "TARGET_VECTOR
1383 && (register_operand (operands[0], <MODE>mode)
1384 || register_operand (operands[1], <MODE>mode))"
1385 "@
1386 #
1387 #
1388 vmv%m1r.v\t%0,%1"
1389 "&& reload_completed
1390 && (!register_operand (operands[0], <MODE>mode)
1391 || !register_operand (operands[1], <MODE>mode))"
1392 [(const_int 0)]
1393 {
1394 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1395 gcc_assert (ok_p);
1396 DONE;
1397 }
1398 [(set_attr "type" "vmov")]
1399 )
1401 (define_expand "mov<mode>"
1402 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1403 (match_operand:VLS_AVL_REG 1 "general_operand"))]
1404 "TARGET_VECTOR"
1405 {
1406 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1407 gcc_assert (ok_p);
1408 DONE;
1409 })
1411 (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
1412 [(parallel
1413 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1414 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
1415 (clobber (match_scratch:P 2))])]
1416 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1417 {})
1419 (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
1420 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
1421 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
1422 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1423 "TARGET_VECTOR && (lra_in_progress || reload_completed)
1424 && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
1425 || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
1426 "#"
1427 "&& reload_completed"
1428 [(const_int 0)]
1429 {
1430 if (REG_P (operands[0]) && REG_P (operands[1]))
1431 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1432 else
1433 {
1434 emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
1435 Pmode));
1436 unsigned insn_flags
1437 = GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
1438 ? riscv_vector::UNARY_MASK_OP
1439 : riscv_vector::UNARY_OP;
1440 riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
1441 insn_flags, operands, operands[2]);
1442 }
1443 DONE;
1444 }
1445 [(set_attr "type" "vmov")]
1446 )
1448 (define_insn "*mov<mode>_vls"
1449 [(set (match_operand:VLS 0 "register_operand" "=vr")
1450 (match_operand:VLS 1 "register_operand" " vr"))]
1451 "TARGET_VECTOR"
1452 "vmv%m1r.v\t%0,%1"
1453 [(set_attr "type" "vmov")
1454 (set_attr "mode" "<MODE>")])
1456 (define_insn "*mov<mode>_vls"
1457 [(set (match_operand:VLSB 0 "register_operand" "=vr")
1458 (match_operand:VLSB 1 "register_operand" " vr"))]
1459 "TARGET_VECTOR"
1460 "vmv1r.v\t%0,%1"
1461 [(set_attr "type" "vmov")
1462 (set_attr "mode" "<MODE>")])
1464 ;; According to RVV ISA:
1465 ;; If an element accessed by a vector memory instruction is not naturally aligned to the size of the element,
1466 ;; either the element is transferred successfully or an address misaligned exception is raised on that element.
1467 (define_expand "movmisalign<mode>"
1468 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1469 (match_operand:V_VLS 1 "general_operand"))]
1470 "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
1471 {
1472 emit_move_insn (operands[0], operands[1]);
1473 DONE;
1474 }
1475 )
1477 ;; -----------------------------------------------------------------
1478 ;; ---- Duplicate Operations
1479 ;; -----------------------------------------------------------------
1481 (define_expand "vec_duplicate<mode>"
1482 [(set (match_operand:V_VLS 0 "register_operand")
1483 (vec_duplicate:V_VLS
1484 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1485 "TARGET_VECTOR"
1486 {
1487 /* Early expand DImode broadcast in RV32 system to avoid RA reload
1488 generate (set (reg) (vec_duplicate:DI)). */
1489 if (maybe_gt (GET_MODE_SIZE (<VEL>mode), GET_MODE_SIZE (Pmode)))
1490 {
1491 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1492 riscv_vector::UNARY_OP, operands);
1493 DONE;
1494 }
1495 /* Otherwise, allow it fall into general vec_duplicate pattern
1496 which allow us to have vv->vx combine optimization in later pass. */
1497 })
1499 ;; According to GCC internal:
1500 ;; This pattern only handles duplicates of non-constant inputs.
1501 ;; Constant vectors go through the movm pattern instead.
1502 ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT.
1503 (define_insn_and_split "*vec_duplicate<mode>"
1504 [(set (match_operand:V_VLS 0 "register_operand")
1505 (vec_duplicate:V_VLS
1506 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1507 "TARGET_VECTOR && can_create_pseudo_p ()"
1508 "#"
1509 "&& 1"
1510 [(const_int 0)]
1511 {
1512 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1513 riscv_vector::UNARY_OP, operands);
1514 DONE;
1515 }
1516 [(set_attr "type" "vector")]
1517 )
1519 ;; -----------------------------------------------------------------
1520 ;; ---- 6. Configuration-Setting Instructions
1521 ;; -----------------------------------------------------------------
1522 ;; Includes:
1523 ;; - 6.1 vsetvli/vsetivl/vsetvl instructions
1524 ;; -----------------------------------------------------------------
1526 ;; we dont't define vsetvli as unspec_volatile which has side effects.
1527 ;; This instruction can be scheduled by the instruction scheduler.
1528 ;; This means these instructions will be deleted when
1529 ;; there is no instructions using vl or vtype in the following.
1530 ;; rd | rs1 | AVL value | Effect on vl
1531 ;; - | !x0 | x[rs1] | Normal stripmining
1532 ;; !x0 | x0 | ~0 | Set vl to VLMAX
1533 ;; operands[0]: VL.
1534 ;; operands[1]: AVL.
1535 ;; operands[2]: SEW
1536 ;; operands[3]: LMUL
1537 ;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)
1538 ;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)
1540 ;; We define 2 types of "vsetvl*" instruction patterns:
1542 ;; - "@vsetvl<mode>" is a parallel format which has side effects.
1544 ;; - "@vsetvl<mode>_no_side_effects" has no side effects.
1546 ;; - "@vsetvl<mode>" is used by "vsetvl" intrinsics and "insert-vsetvl" PASS.
1548 ;; - "@vsetvl<mode>_no_side_effects" is used by GCC standard patterns.
1550 ;; - "@vsetvl<mode>" includes VL/VTYPE global registers status (define set)
1551 ;; and each RVV instruction includes VL/VTYPE global registers status (use)
1552 ;; so that we can guarantee each RVV instruction can execute with correct
1553 ;; VL/VTYPE global registers status after "insert-vsetvl" PASS.
1555 ;; - "@vsetvl<mode>_no_side_effects" has no side effects and excludes VL/VTYPE
1556 ;; global registers status (define set). It's only used by GCC standard pattern
1557 ;; expansion. For example: "mov<mode>" pattern for fractional vector modes which
1558 ;; need to set VL/VTYPE. Then we could manually call this pattern to gain benefits
1559 ;; from the optimization of each GCC internal PASS.
1561 ;; 1. void foo (float *in, float *out)
1562 ;; {
1563 ;; vfloat32mf2_t v = *(vfloat32mf2_t*)in;
1564 ;; *(vfloat32mf2_t*)out = v;
1565 ;; }
1566 ;; We could eliminate the second "vsetvl" by calling "@vsetvl<mode>_no_side_effects".
1567 ;;
1568 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1569 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; vsetvli a4,zero,e32,mf2,ta,ma
1570 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1571 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; --
1572 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1573 ;; ret ;; ret
1575 ;; 2. void foo (int8_t *in, int8_t *out, int M)
1576 ;; {
1577 ;; for (int i = 0; i < M; i++){
1578 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1579 ;; *(vint8mf2_t*)(out + i) = v;
1580 ;; }
1581 ;; }
1582 ;;
1583 ;; Hoist "vsetvl" instruction in LICM:
1584 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1585 ;; - ;; vsetvli a4,zero,e32,mf2,ta,ma
1586 ;; LOOP: ;; LOOP:
1587 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1588 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1589 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1590 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1592 ;; However, it may produce wrong codegen if we exclude VL/VTYPE in "vsevl<mode>".
1593 ;; 3. void foo (int8_t *in, int8_t *out, int32_t *in2, int32_t *out2, int M)
1594 ;; {
1595 ;; for (int i = 0; i < M; i++){
1596 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1597 ;; vint32mf2_t v2 = *(vint32mf2_t*)(in + i + i);
1598 ;; *(vint8mf2_t*)(out + i) = v;
1599 ;; *(vint32mf2_t*)(out + i + i) = v2;
1600 ;; }
1601 ;; }
1602 ;;
1603 ;; vsetvli a6,zero,e8,mf2,ta,ma
1604 ;; vsetvli a2,zero,e32,mf2,ta,ma
1605 ;; LOOP:
1606 ;; vle8.v v25,(a0)
1607 ;; vle32.v v24,(a5)
1608 ;; addi a0,a0,1
1609 ;; vse8.v v25,(a1)
1610 ;; vse32.v v24,(a3)
1611 ;;
1612 ;; Both vle8.v and vle32.v are using the wrong VL/VTYPE status.
1613 ;; We leave it to "insert-vsetvl" PASS to correct this situation.
1615 ;; The "insert-vsetvl" PASS mechanism:
1616 ;; 1. Before "insert-vsetvl" PASS, only RVV instructions are generated
1617 ;; by GCC standard pattern expansion has the corresponding "vsetvl".
1618 ;; We exploit each GCC internal optimization pass to optimize the "vsetvl".
1619 ;; 2. Correct the VL/VTYPE status for each GCC standard pattern RVV instructions.
1620 ;; Insert vsetvl for each RVV instructions that has no VL/VTYPE status if necessary.
1621 ;; For example: RVV intrinsics.
1622 ;; 3. Optimize "vsetvl" instructions.
1624 (define_insn "@vsetvl<mode>"
1625 [(set (match_operand:P 0 "register_operand" "=r")
1626 (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
1627 (match_operand 2 "const_int_operand" "i")
1628 (match_operand 3 "const_int_operand" "i")
1629 (match_operand 4 "const_int_operand" "i")
1630 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
1631 (set (reg:SI VL_REGNUM)
1632 (unspec:SI [(match_dup 1)
1633 (match_dup 2)
1634 (match_dup 3)] UNSPEC_VSETVL))
1635 (set (reg:SI VTYPE_REGNUM)
1636 (unspec:SI [(match_dup 2)
1637 (match_dup 3)
1638 (match_dup 4)
1639 (match_dup 5)] UNSPEC_VSETVL))]
1640 "TARGET_VECTOR"
1641 "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
1642 [(set_attr "type" "vsetvl")
1643 (set_attr "mode" "<MODE>")
1644 (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
1645 (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
1646 (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
1647 (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
1649 ;; vsetvl zero,zero,vtype instruction.
1650 ;; This pattern has no side effects and does not set X0 register.
1651 (define_insn "vsetvl_vtype_change_only"
1652 [(set (reg:SI VTYPE_REGNUM)
1653 (unspec:SI
1654 [(match_operand 0 "const_int_operand" "i")
1655 (match_operand 1 "const_int_operand" "i")
1656 (match_operand 2 "const_int_operand" "i")
1657 (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
1658 "TARGET_VECTOR"
1659 "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
1660 [(set_attr "type" "vsetvl")
1661 (set_attr "mode" "SI")
1662 (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
1663 (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
1664 (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
1665 (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
1667 ;; vsetvl zero,rs1,vtype instruction.
1668 ;; The reason we need this pattern since we should avoid setting X0 register
1669 ;; in vsetvl instruction pattern.
1670 (define_insn "@vsetvl_discard_result<mode>"
1671 [(set (reg:SI VL_REGNUM)
1672 (unspec:SI [(match_operand:P 0 "vector_length_operand" "rK")
1673 (match_operand 1 "const_int_operand" "i")
1674 (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
1675 (set (reg:SI VTYPE_REGNUM)
1676 (unspec:SI [(match_dup 1)
1677 (match_dup 2)
1678 (match_operand 3 "const_int_operand" "i")
1679 (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
1680 "TARGET_VECTOR"
1681 "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
1682 [(set_attr "type" "vsetvl")
1683 (set_attr "mode" "<MODE>")
1684 (set (attr "sew") (symbol_ref "INTVAL (operands[1])"))
1685 (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])"))
1686 (set (attr "ta") (symbol_ref "INTVAL (operands[3])"))
1687 (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))])
1689 ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.
1690 ;; Since we have many optmization passes from "expand" to "reload_completed",
1691 ;; such pattern can allow us gain benefits of these optimizations.
1692 (define_insn_and_split "@vsetvl<mode>_no_side_effects"
1693 [(set (match_operand:P 0 "register_operand" "=r")
1694 (unspec:P [(match_operand:P 1 "vector_length_operand" "rK")
1695 (match_operand 2 "const_int_operand" "i")
1696 (match_operand 3 "const_int_operand" "i")
1697 (match_operand 4 "const_int_operand" "i")
1698 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
1699 "TARGET_VECTOR"
1700 "#"
1701 "&& epilogue_completed"
1702 [(parallel
1703 [(set (match_dup 0)
1704 (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
1705 (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
1706 (set (reg:SI VL_REGNUM)
1707 (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
1708 (set (reg:SI VTYPE_REGNUM)
1709 (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
1710 (match_dup 5)] UNSPEC_VSETVL))])]
1711 ""
1712 [(set_attr "type" "vsetvl")
1713 (set_attr "mode" "SI")])
1715 ;; This pattern use to combine bellow two insns and then further remove
1716 ;; unnecessary sign_extend operations:
1717 ;; (set (reg:DI 134 [ _1 ])
1718 ;; (unspec:DI [
1719 ;; (const_int 19 [0x13])
1720 ;; (const_int 8 [0x8])
1721 ;; (const_int 5 [0x5])
1722 ;; (const_int 2 [0x2]) repeated x2
1723 ;; ] UNSPEC_VSETVL))
1724 ;; (set (reg/v:DI 135 [ <retval> ])
1725 ;; (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0)))
1726 ;;
1727 ;; The reason we can remove signe_extend is because currently the vl value
1728 ;; returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and
1729 ;; bits 17 to 63 (including 31) are always 0, so there is no change after
1730 ;; sign_extend. Note that for HI and QI modes we cannot do this.
1731 ;; Of course, if the range of instructions returned by vsetvl later expands
1732 ;; to 32bits, then this combine pattern needs to be removed. But that could be
1733 ;; a long time from now.
1734 (define_insn_and_split "*vsetvldi_no_side_effects_si_extend"
1735 [(set (match_operand:DI 0 "register_operand")
1736 (sign_extend:DI
1737 (subreg:SI
1738 (unspec:DI [(match_operand:P 1 "vector_length_operand")
1739 (match_operand 2 "const_int_operand")
1740 (match_operand 3 "const_int_operand")
1741 (match_operand 4 "const_int_operand")
1742 (match_operand 5 "const_int_operand")] UNSPEC_VSETVL) 0)))]
1743 "TARGET_VECTOR && TARGET_64BIT"
1744 "#"
1745 "&& 1"
1746 [(set (match_dup 0)
1747 (unspec:DI [(match_dup 1)
1748 (match_dup 2)
1749 (match_dup 3)
1750 (match_dup 4)
1751 (match_dup 5)] UNSPEC_VSETVL))]
1752 ""
1753 [(set_attr "type" "vsetvl")
1754 (set_attr "mode" "SI")])
1756 ;; RVV machine description matching format
1757 ;; (define_insn ""
1758 ;; [(set (match_operand:MODE 0)
1759 ;; (if_then_else:MODE
1760 ;; (unspec:<MODE:VM>
1761 ;; [(match_operand:<VM> 1 "vector_mask_operand")
1762 ;; (match_operand N + 4 "vector_length_operand")
1763 ;; (match_operand N + 5 "const_int_operand")
1764 ;; (match_operand N + 6 "const_int_operand")
1765 ;; (reg:SI VL_REGNUM)
1766 ;; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1767 ;; (instruction operation:MODE
1768 ;; (match_operand 3
1769 ;; (match_operand 4
1770 ;; (match_operand 5
1771 ;; ................
1772 ;; (match_operand N + 3)
1773 ;; (match_operand:MODE 2 "vector_reg_or_const0_operand")))]
1774 ;;
1775 ;; (unspec:[........] UNSPEC_VPREDICATE) is a predicate wrapper.
1776 ;; Include mask predicate && length predicate && vector policy.
1778 ;; -------------------------------------------------------------------------------
1779 ;; ---- Predicated Mov
1780 ;; -------------------------------------------------------------------------------
1781 ;; Includes:
1782 ;; - 7.4. Vector Unit-Stride Instructions
1783 ;; - 11.15 Vector Integer Merge Instructions
1784 ;; - 11.16 Vector Integer Move Instructions
1785 ;; - 13.16 Vector Floating-Point Move Instruction
1786 ;; - 15.1 Vector Mask-Register Logical Instructions
1787 ;; -------------------------------------------------------------------------------
1789 ;; vle.v/vse.v/vmv.v.v.
1790 ;; For vle.v/vmv.v.v, we may need merge and mask operand.
1791 ;; For vse.v, we don't need merge operand, so it should always match "vu".
1792 ;; constraint alternative 0 ~ 1 match vle.v.
1793 ;; constraint alternative 2 match vse.v.
1794 ;; constraint alternative 3 match vmv.v.v.
1796 ;; If operand 3 is a const_vector, then it is left to pred_braordcast patterns.
1797 (define_expand "@pred_mov<mode>"
1798 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1799 (if_then_else:V_VLS
1800 (unspec:<VM>
1801 [(match_operand:<VM> 1 "vector_mask_operand")
1802 (match_operand 4 "vector_length_operand")
1803 (match_operand 5 "const_int_operand")
1804 (match_operand 6 "const_int_operand")
1805 (match_operand 7 "const_int_operand")
1806 (reg:SI VL_REGNUM)
1807 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1808 (match_operand:V_VLS 3 "vector_move_operand")
1809 (match_operand:V_VLS 2 "vector_merge_operand")))]
1810 "TARGET_VECTOR"
1811 {})
1813 ;; vle.v/vse.v,vmv.v.v
1814 (define_insn_and_split "*pred_mov<mode>"
1815 [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=vr, vr, vd, m, vr, vr")
1816 (if_then_else:V_VLS
1817 (unspec:<VM>
1818 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, Wc1")
1819 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
1820 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
1821 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
1822 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
1823 (reg:SI VL_REGNUM)
1824 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1825 (match_operand:V_VLS 3 "reg_or_mem_operand" " m, m, m, vr, vr, vr")
1826 (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, vu, vu, 0")))]
1827 "(TARGET_VECTOR
1828 && (register_operand (operands[0], <MODE>mode)
1829 || register_operand (operands[3], <MODE>mode)))"
1830 "@
1831 vle<sew>.v\t%0,%3%p1
1832 vle<sew>.v\t%0,%3
1833 vle<sew>.v\t%0,%3,%1.t
1834 vse<sew>.v\t%3,%0%p1
1835 vmv.v.v\t%0,%3
1836 vmv.v.v\t%0,%3"
1837 "&& riscv_vector::whole_reg_to_reg_move_p (operands, <MODE>mode, 7)"
1838 [(set (match_dup 0) (match_dup 3))]
1839 ""
1840 [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
1841 (set_attr "mode" "<MODE>")])
1843 ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include
1844 ;; memory operand as input which will produce inferior codegen.
1845 (define_insn "@pred_store<mode>"
1846 [(set (match_operand:V 0 "memory_operand" "+m")
1847 (if_then_else:V
1848 (unspec:<VM>
1849 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
1850 (match_operand 3 "vector_length_operand" " rK")
1851 (match_operand 4 "const_int_operand" " i")
1852 (reg:SI VL_REGNUM)
1853 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1854 (match_operand:V 2 "register_operand" " vr")
1855 (match_dup 0)))]
1856 "TARGET_VECTOR"
1857 "vse<sew>.v\t%2,%0%p1"
1858 [(set_attr "type" "vste")
1859 (set_attr "mode" "<MODE>")
1860 (set (attr "avl_type_idx") (const_int 4))
1861 (set_attr "vl_op_idx" "3")])
1863 ;; vlm.v/vsm.v/vmclr.m/vmset.m.
1864 ;; constraint alternative 0 match vlm.v.
1865 ;; constraint alternative 1 match vsm.v.
1866 ;; constraint alternative 3 match vmclr.m.
1867 ;; constraint alternative 4 match vmset.m.
1868 (define_insn_and_split "@pred_mov<mode>"
1869 [(set (match_operand:VB_VLS 0 "nonimmediate_operand" "=vr, m, vr, vr, vr")
1870 (if_then_else:VB_VLS
1871 (unspec:VB_VLS
1872 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
1873 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
1874 (match_operand 5 "const_int_operand" " i, i, i, i, i")
1875 (reg:SI VL_REGNUM)
1876 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1877 (match_operand:VB_VLS 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
1878 (match_operand:VB_VLS 2 "vector_undef_operand" " vu, vu, vu, vu, vu")))]
1879 "TARGET_VECTOR"
1880 "@
1881 vlm.v\t%0,%3
1882 vsm.v\t%3,%0
1883 vmmv.m\t%0,%3
1884 vmclr.m\t%0
1885 vmset.m\t%0"
1886 "&& riscv_vector::whole_reg_to_reg_move_p (operands, <MODE>mode, 5)"
1887 [(set (match_dup 0) (match_dup 3))]
1888 ""
1889 [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu")
1890 (set_attr "mode" "<MODE>")])
1892 ;; Dedicated pattern for vsm.v instruction since we can't reuse pred_mov pattern to include
1893 ;; memory operand as input which will produce inferior codegen.
1894 (define_insn "@pred_store<mode>"
1895 [(set (match_operand:VB 0 "memory_operand" "+m")
1896 (if_then_else:VB
1897 (unspec:VB
1898 [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
1899 (match_operand 3 "vector_length_operand" " rK")
1900 (match_operand 4 "const_int_operand" " i")
1901 (reg:SI VL_REGNUM)
1902 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1903 (match_operand:VB 2 "register_operand" " vr")
1904 (match_dup 0)))]
1905 "TARGET_VECTOR"
1906 "vsm.v\t%2,%0"
1907 [(set_attr "type" "vstm")
1908 (set_attr "mode" "<MODE>")
1909 (set (attr "avl_type_idx") (const_int 4))
1910 (set_attr "vl_op_idx" "3")])
1912 (define_insn "@pred_merge<mode>"
1913 [(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd")
1914 (if_then_else:V_VLS
1915 (unspec:<VM>
1916 [(match_operand 5 "vector_length_operand" " rK,rK,rK,rK")
1917 (match_operand 6 "const_int_operand" " i, i, i, i")
1918 (match_operand 7 "const_int_operand" " i, i, i, i")
1919 (reg:SI VL_REGNUM)
1920 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1921 (vec_merge:V_VLS
1922 (match_operand:V_VLS 3 "vector_arith_operand" " vr,vr,vi,vi")
1923 (match_operand:V_VLS 2 "register_operand" " vr,vr,vr,vr")
1924 (match_operand:<VM> 4 "register_operand" " vm,vm,vm,vm"))
1925 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0,vu, 0")))]
1926 "TARGET_VECTOR"
1927 "vmerge.v%o3m\t%0,%2,%v3,%4"
1928 [(set_attr "type" "vimerge")
1929 (set_attr "mode" "<MODE>")])
1931 (define_insn "@pred_merge<mode>_scalar"
1932 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd")
1933 (if_then_else:V_VLSI_QHS
1934 (unspec:<VM>
1935 [(match_operand 5 "vector_length_operand" " rK,rK")
1936 (match_operand 6 "const_int_operand" " i, i")
1937 (match_operand 7 "const_int_operand" " i, i")
1938 (reg:SI VL_REGNUM)
1939 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1940 (vec_merge:V_VLSI_QHS
1941 (vec_duplicate:V_VLSI_QHS
1942 (match_operand:<VEL> 3 "register_operand" " r, r"))
1943 (match_operand:V_VLSI_QHS 2 "register_operand" " vr,vr")
1944 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1945 (match_operand:V_VLSI_QHS 1 "vector_merge_operand" " vu, 0")))]
1946 "TARGET_VECTOR"
1947 "vmerge.vxm\t%0,%2,%3,%4"
1948 [(set_attr "type" "vimerge")
1949 (set_attr "mode" "<MODE>")])
1951 (define_expand "@pred_merge<mode>_scalar"
1952 [(set (match_operand:V_VLSI_D 0 "register_operand")
1953 (if_then_else:V_VLSI_D
1954 (unspec:<VM>
1955 [(match_operand 5 "vector_length_operand")
1956 (match_operand 6 "const_int_operand")
1957 (match_operand 7 "const_int_operand")
1958 (reg:SI VL_REGNUM)
1959 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1960 (vec_merge:V_VLSI_D
1961 (vec_duplicate:V_VLSI_D
1962 (match_operand:<VEL> 3 "reg_or_int_operand"))
1963 (match_operand:V_VLSI_D 2 "register_operand")
1964 (match_operand:<VM> 4 "register_operand"))
1965 (match_operand:V_VLSI_D 1 "vector_merge_operand")))]
1966 "TARGET_VECTOR"
1967 {
1968 if (riscv_vector::sew64_scalar_helper (
1969 operands,
1970 /* scalar op */&operands[3],
1971 /* vl */operands[5],
1972 <MODE>mode,
1973 riscv_vector::simm5_p (operands[3]),
1974 [] (rtx *operands, rtx boardcast_scalar) {
1975 emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
1976 operands[2], boardcast_scalar, operands[4], operands[5],
1977 operands[6], operands[7]));
1978 },
1979 (riscv_vector::avl_type) INTVAL (operands[7])))
1980 DONE;
1981 })
1983 (define_insn "*pred_merge<mode>_scalar"
1984 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1985 (if_then_else:V_VLSI_D
1986 (unspec:<VM>
1987 [(match_operand 5 "vector_length_operand" " rK,rK")
1988 (match_operand 6 "const_int_operand" " i, i")
1989 (match_operand 7 "const_int_operand" " i, i")
1990 (reg:SI VL_REGNUM)
1991 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1992 (vec_merge:V_VLSI_D
1993 (vec_duplicate:V_VLSI_D
1994 (match_operand:<VEL> 3 "register_operand" " r, r"))
1995 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1996 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1997 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1998 "TARGET_VECTOR"
1999 "vmerge.vxm\t%0,%2,%3,%4"
2000 [(set_attr "type" "vimerge")
2001 (set_attr "mode" "<MODE>")])
2003 (define_insn "*pred_merge<mode>_extended_scalar"
2004 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
2005 (if_then_else:V_VLSI_D
2006 (unspec:<VM>
2007 [(match_operand 5 "vector_length_operand" " rK,rK")
2008 (match_operand 6 "const_int_operand" " i, i")
2009 (match_operand 7 "const_int_operand" " i, i")
2010 (reg:SI VL_REGNUM)
2011 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2012 (vec_merge:V_VLSI_D
2013 (vec_duplicate:V_VLSI_D
2014 (sign_extend:<VEL>
2015 (match_operand:<VSUBEL> 3 "register_operand" " r, r")))
2016 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
2017 (match_operand:<VM> 4 "register_operand" " vm,vm"))
2018 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
2019 "TARGET_VECTOR && !TARGET_64BIT"
2020 "vmerge.vxm\t%0,%2,%3,%4"
2021 [(set_attr "type" "vimerge")
2022 (set_attr "mode" "<MODE>")])
2024 ;; -------------------------------------------------------------------------------
2025 ;; ---- Predicated Broadcast
2026 ;; -------------------------------------------------------------------------------
2027 ;; Includes:
2028 ;; - 7.5. Vector Strided Instructions (zero stride)
2029 ;; - 11.16 Vector Integer Move Instructions (vmv.v.x)
2030 ;; - 13.16 Vector Floating-Point Move Instruction (vfmv.v.f)
2031 ;; - 16.1 Integer Scalar Move Instructions (vmv.s.x)
2032 ;; - 16.2 Floating-Point Scalar Move Instructions (vfmv.s.f)
2033 ;; -------------------------------------------------------------------------------
2035 ;; According to RVV ISA, vector-scalar instruction doesn't support
2036 ;; operand fetched from 2 consecutive registers, so we should use
2037 ;; vlse.v which is a memory access to broadcast a DImode scalar into a vector.
2038 ;;
2039 ;; Since the optimization flow in GCC is as follows:
2040 ;; expand --> LICM (Loop invariant) --> split.
2041 ;; To use LICM optimization, we postpone generation of vlse.v to split stage since
2042 ;; a memory access instruction can not be optimized by LICM (Loop invariant).
2043 (define_expand "@pred_broadcast<mode>"
2044 [(set (match_operand:V_VLS 0 "register_operand")
2045 (if_then_else:V_VLS
2046 (unspec:<VM>
2047 [(match_operand:<VM> 1 "vector_broadcast_mask_operand")
2048 (match_operand 4 "vector_length_operand")
2049 (match_operand 5 "const_int_operand")
2050 (match_operand 6 "const_int_operand")
2051 (match_operand 7 "const_int_operand")
2052 (reg:SI VL_REGNUM)
2053 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2054 (vec_duplicate:V_VLS
2055 (match_operand:<VEL> 3 "direct_broadcast_operand"))
2056 (match_operand:V_VLS 2 "vector_merge_operand")))]
2057 "TARGET_VECTOR"
2058 {
2059 /* Transform vmv.v.x/vfmv.v.f (avl = 1) into vmv.s.x since vmv.s.x/vfmv.s.f
2060 has better chances to do vsetvl fusion in vsetvl pass. */
2061 if (riscv_vector::splat_to_scalar_move_p (operands))
2062 {
2063 operands[1] = riscv_vector::gen_scalar_move_mask (<VM>mode);
2064 operands[3] = force_reg (<VEL>mode, operands[3]);
2065 }
2066 /* Handle vmv.s.x instruction (Wb1 mask) which has memory scalar. */
2067 else if (satisfies_constraint_Wdm (operands[3]))
2068 {
2069 if (satisfies_constraint_Wb1 (operands[1]))
2070 {
2071 /* Case 1: vmv.s.x (TA, x == memory) ==> vlse.v (TA) */
2072 if (satisfies_constraint_vu (operands[2]))
2073 operands[1] = CONSTM1_RTX (<VM>mode);
2074 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
2075 {
2076 /* Case 2: vmv.s.x (TU, x == memory) ==>
2077 vl = 0 or 1; + vlse.v (TU) in RV32 system */
2078 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2079 operands[1] = CONSTM1_RTX (<VM>mode);
2080 }
2081 else
2082 /* Case 3: load x (memory) to register. */
2083 operands[3] = force_reg (<VEL>mode, operands[3]);
2084 }
2085 }
2086 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)
2087 && (immediate_operand (operands[3], Pmode)
2088 || (CONST_POLY_INT_P (operands[3])
2089 && known_ge (rtx_to_poly_int64 (operands[3]), 0U)
2090 && known_le (rtx_to_poly_int64 (operands[3]), GET_MODE_SIZE (<MODE>mode)))))
2091 {
2092 rtx tmp = gen_reg_rtx (Pmode);
2093 poly_int64 value = rtx_to_poly_int64 (operands[3]);
2094 emit_move_insn (tmp, gen_int_mode (value, Pmode));
2095 operands[3] = gen_rtx_SIGN_EXTEND (<VEL>mode, tmp);
2096 }
2097 else
2098 operands[3] = force_reg (<VEL>mode, operands[3]);
2099 })
2101 (define_insn_and_split "*pred_broadcast<mode>"
2102 [(set (match_operand:V_VLSI 0 "register_operand" "=vr, vr, vd, vd, vr, vr, vr, vr")
2103 (if_then_else:V_VLSI
2104 (unspec:<VM>
2105 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
2106 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
2107 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
2108 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2109 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2110 (reg:SI VL_REGNUM)
2111 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2112 (vec_duplicate:V_VLSI
2113 (match_operand:<VEL> 3 "direct_broadcast_operand" " r, r,Wdm,Wdm,Wdm,Wdm, r, r"))
2114 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2115 "TARGET_VECTOR"
2116 "@
2117 vmv.v.x\t%0,%3
2118 vmv.v.x\t%0,%3
2119 vlse<sew>.v\t%0,%3,zero,%1.t
2120 vlse<sew>.v\t%0,%3,zero,%1.t
2121 vlse<sew>.v\t%0,%3,zero
2122 vlse<sew>.v\t%0,%3,zero
2123 vmv.s.x\t%0,%3
2124 vmv.s.x\t%0,%3"
2125 "(register_operand (operands[3], <VEL>mode)
2126 || CONST_POLY_INT_P (operands[3]))
2127 && GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)"
2128 [(set (match_dup 0)
2129 (if_then_else:V_VLSI (unspec:<VM> [(match_dup 1) (match_dup 4)
2130 (match_dup 5) (match_dup 6) (match_dup 7)
2131 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2132 (vec_duplicate:V_VLSI (match_dup 3))
2133 (match_dup 2)))]
2134 {
2135 gcc_assert (can_create_pseudo_p ());
2136 if (CONST_POLY_INT_P (operands[3]))
2137 {
2138 rtx tmp = gen_reg_rtx (<VEL>mode);
2139 emit_move_insn (tmp, operands[3]);
2140 operands[3] = tmp;
2141 }
2142 rtx m = assign_stack_local (<VEL>mode, GET_MODE_SIZE (<VEL>mode),
2143 GET_MODE_ALIGNMENT (<VEL>mode));
2144 m = validize_mem (m);
2145 emit_move_insn (m, operands[3]);
2146 m = gen_rtx_MEM (<VEL>mode, force_reg (Pmode, XEXP (m, 0)));
2147 operands[3] = m;
2149 /* For SEW = 64 in RV32 system, we expand vmv.s.x:
2150 andi a2,a2,1
2151 vsetvl zero,a2,e64
2152 vlse64.v */
2153 if (satisfies_constraint_Wb1 (operands[1]))
2154 {
2155 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2156 operands[1] = CONSTM1_RTX (<VM>mode);
2157 }
2158 }
2159 [(set_attr "type" "vimov,vimov,vlds,vlds,vlds,vlds,vimovxv,vimovxv")
2160 (set_attr "mode" "<MODE>")])
2162 (define_insn "*pred_broadcast<mode>_zvfh"
2163 [(set (match_operand:V_VLSF 0 "register_operand" "=vr, vr, vr, vr")
2164 (if_then_else:V_VLSF
2165 (unspec:<VM>
2166 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1, Wc1, Wb1, Wb1")
2167 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
2168 (match_operand 5 "const_int_operand" " i, i, i, i")
2169 (match_operand 6 "const_int_operand" " i, i, i, i")
2170 (match_operand 7 "const_int_operand" " i, i, i, i")
2171 (reg:SI VL_REGNUM)
2172 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2173 (vec_duplicate:V_VLSF
2174 (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f, f, f"))
2175 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
2176 "TARGET_VECTOR"
2177 "@
2178 vfmv.v.f\t%0,%3
2179 vfmv.v.f\t%0,%3
2180 vfmv.s.f\t%0,%3
2181 vfmv.s.f\t%0,%3"
2182 [(set_attr "type" "vfmov,vfmov,vfmovfv,vfmovfv")
2183 (set_attr "mode" "<MODE>")])
2185 (define_insn "*pred_broadcast<mode>_zvfhmin"
2186 [(set (match_operand:V_VLSF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr")
2187 (if_then_else:V_VLSF_ZVFHMIN
2188 (unspec:<VM>
2189 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" " vm, vm, Wc1, Wc1")
2190 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
2191 (match_operand 5 "const_int_operand" " i, i, i, i")
2192 (match_operand 6 "const_int_operand" " i, i, i, i")
2193 (match_operand 7 "const_int_operand" " i, i, i, i")
2194 (reg:SI VL_REGNUM)
2195 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2196 (vec_duplicate:V_VLSF_ZVFHMIN
2197 (match_operand:<VEL> 3 "direct_broadcast_operand" "Wdm, Wdm, Wdm, Wdm"))
2198 (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand" " vu, 0, vu, 0")))]
2199 "TARGET_VECTOR"
2200 "@
2201 vlse<sew>.v\t%0,%3,zero,%1.t
2202 vlse<sew>.v\t%0,%3,zero,%1.t
2203 vlse<sew>.v\t%0,%3,zero
2204 vlse<sew>.v\t%0,%3,zero"
2205 [(set_attr "type" "vlds,vlds,vlds,vlds")
2206 (set_attr "mode" "<MODE>")])
2208 (define_insn "*pred_broadcast<mode>_extended_scalar"
2209 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vr, vr, vr, vr")
2210 (if_then_else:V_VLSI_D
2211 (unspec:<VM>
2212 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,Wb1,Wb1")
2213 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
2214 (match_operand 5 "const_int_operand" " i, i, i, i")
2215 (match_operand 6 "const_int_operand" " i, i, i, i")
2216 (match_operand 7 "const_int_operand" " i, i, i, i")
2217 (reg:SI VL_REGNUM)
2218 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2219 (vec_duplicate:V_VLSI_D
2220 (sign_extend:<VEL>
2221 (match_operand:<VSUBEL> 3 "register_operand" " r, r, r, r")))
2222 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2223 "TARGET_VECTOR && !TARGET_64BIT"
2224 "@
2225 vmv.v.x\t%0,%3
2226 vmv.v.x\t%0,%3
2227 vmv.s.x\t%0,%3
2228 vmv.s.x\t%0,%3"
2229 [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
2230 (set_attr "mode" "<MODE>")])
2232 (define_insn "*pred_broadcast<mode>_zero"
2233 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2234 (if_then_else:V_VLS
2235 (unspec:<VM>
2236 [(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1, Wb1")
2237 (match_operand 4 "vector_length_operand" " rK, rK")
2238 (match_operand 5 "const_int_operand" " i, i")
2239 (match_operand 6 "const_int_operand" " i, i")
2240 (match_operand 7 "const_int_operand" " i, i")
2241 (reg:SI VL_REGNUM)
2242 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2243 (match_operand:V_VLS 3 "vector_const_0_operand" "Wc0, Wc0")
2244 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2245 "TARGET_VECTOR"
2246 "vmv.s.x\t%0,zero"
2247 [(set_attr "type" "vimovxv,vimovxv")
2248 (set_attr "mode" "<MODE>")])
2250 ;; Because (vec_duplicate imm) will be converted to (const_vector imm),
2251 ;; This pattern is used to handle this case.
2252 (define_insn "*pred_broadcast<mode>_imm"
2253 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2254 (if_then_else:V_VLS
2255 (unspec:<VM>
2256 [(match_operand:<VM> 1 "vector_all_trues_mask_operand" " Wc1, Wc1")
2257 (match_operand 4 "vector_length_operand" " rK, rK")
2258 (match_operand 5 "const_int_operand" " i, i")
2259 (match_operand 6 "const_int_operand" " i, i")
2260 (match_operand 7 "const_int_operand" " i, i")
2261 (reg:SI VL_REGNUM)
2262 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2263 (match_operand:V_VLS 3 "vector_const_int_or_double_0_operand" "viWc0, viWc0")
2264 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2265 "TARGET_VECTOR"
2266 "vmv.v.i\t%0,%v3"
2267 [(set_attr "type" "vimov,vimov")
2268 (set_attr "mode" "<MODE>")])
2270 ;; -------------------------------------------------------------------------------
2271 ;; ---- Predicated Strided loads/stores
2272 ;; -------------------------------------------------------------------------------
2273 ;; Includes:
2274 ;; - 7.5. Vector Strided Instructions
2275 ;; -------------------------------------------------------------------------------
2277 (define_insn "@pred_strided_load<mode>"
2278 [(set (match_operand:V 0 "register_operand" "=vr, vr, vd, vr, vr, vd")
2279 (if_then_else:V
2280 (unspec:<VM>
2281 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, vm")
2282 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2283 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2284 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2285 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2286 (reg:SI VL_REGNUM)
2287 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2288 (unspec:V
2289 [(match_operand:V 3 "memory_operand" " m, m, m, m, m, m")
2290 (match_operand 4 "<V:stride_predicate>" "<V:stride_load_constraint>")] UNSPEC_STRIDED)
2291 (match_operand:V 2 "vector_merge_operand" " 0, vu, vu, 0, vu, vu")))]
2292 "TARGET_VECTOR"
2293 "@
2294 vlse<sew>.v\t%0,%3,%z4%p1
2295 vlse<sew>.v\t%0,%3,%z4
2296 vlse<sew>.v\t%0,%3,%z4,%1.t
2297 vle<sew>.v\t%0,%3%p1
2298 vle<sew>.v\t%0,%3
2299 vle<sew>.v\t%0,%3,%1.t"
2300 [(set_attr "type" "vlds")
2301 (set_attr "mode" "<MODE>")])
2303 (define_insn "@pred_strided_store<mode>"
2304 [(set (match_operand:V 0 "memory_operand" "+m, m")
2305 (if_then_else:V
2306 (unspec:<VM>
2307 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
2308 (match_operand 4 "vector_length_operand" " rK, rK")
2309 (match_operand 5 "const_int_operand" " i, i")
2310 (reg:SI VL_REGNUM)
2311 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2312 (unspec:V
2313 [(match_operand 2 "<V:stride_predicate>" "<V:stride_store_constraint>")
2314 (match_operand:V 3 "register_operand" " vr, vr")] UNSPEC_STRIDED)
2315 (match_dup 0)))]
2316 "TARGET_VECTOR"
2317 "@
2318 vsse<sew>.v\t%3,%0,%z2%p1
2319 vse<sew>.v\t%3,%0%p1"
2320 [(set_attr "type" "vsts")
2321 (set_attr "mode" "<MODE>")
2322 (set (attr "avl_type_idx") (const_int 5))])
2324 ;; -------------------------------------------------------------------------------
2325 ;; ---- Predicated indexed loads/stores
2326 ;; -------------------------------------------------------------------------------
2327 ;; Includes:
2328 ;; - 7.6. Vector Indexed Instructions
2329 ;; -------------------------------------------------------------------------------
2331 ;; DEST eew is same as SOURCE eew, DEST register can overlap SOURCE.
2332 (define_insn "@pred_indexed_<order>load<mode>_same_eew"
2333 [(set (match_operand:VINDEXED 0 "register_operand" "=vd, vr,vd, vr")
2334 (if_then_else:VINDEXED
2335 (unspec:<VM>
2336 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
2337 (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
2338 (match_operand 6 "const_int_operand" " i, i, i, i")
2339 (match_operand 7 "const_int_operand" " i, i, i, i")
2340 (match_operand 8 "const_int_operand" " i, i, i, i")
2341 (reg:SI VL_REGNUM)
2342 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2343 (unspec:VINDEXED
2344 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ")
2345 (mem:BLK (scratch))
2346 (match_operand:<VINDEX> 4 "register_operand" " vr, vr,vr, vr")] ORDER)
2347 (match_operand:VINDEXED 2 "vector_merge_operand" " vu, vu, 0, 0")))]
2348 "TARGET_VECTOR"
2349 "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"
2350 [(set_attr "type" "vld<order>x")
2351 (set_attr "mode" "<MODE>")])
2353 ;; DEST eew is greater than SOURCE eew.
2354 (define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew"
2355 [(set (match_operand:VEEWEXT2 0 "register_operand" "=&vr, &vr")
2356 (if_then_else:VEEWEXT2
2357 (unspec:<VM>
2358 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2359 (match_operand 5 "vector_length_operand" " rK, rK")
2360 (match_operand 6 "const_int_operand" " i, i")
2361 (match_operand 7 "const_int_operand" " i, i")
2362 (match_operand 8 "const_int_operand" " i, i")
2363 (reg:SI VL_REGNUM)
2364 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2365 (unspec:VEEWEXT2
2366 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2367 (mem:BLK (scratch))
2368 (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2369 (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, 0")))]
2370 "TARGET_VECTOR"
2371 "vl<order>xei<double_trunc_sew>.v\t%0,(%z3),%4%p1"
2372 [(set_attr "type" "vld<order>x")
2373 (set_attr "mode" "<MODE>")])
2375 (define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew"
2376 [(set (match_operand:VEEWEXT4 0 "register_operand" "=&vr, &vr")
2377 (if_then_else:VEEWEXT4
2378 (unspec:<VM>
2379 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2380 (match_operand 5 "vector_length_operand" " rK, rK")
2381 (match_operand 6 "const_int_operand" " i, i")
2382 (match_operand 7 "const_int_operand" " i, i")
2383 (match_operand 8 "const_int_operand" " i, i")
2384 (reg:SI VL_REGNUM)
2385 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2386 (unspec:VEEWEXT4
2387 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2388 (mem:BLK (scratch))
2389 (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2390 (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, 0")))]
2391 "TARGET_VECTOR"
2392 "vl<order>xei<quad_trunc_sew>.v\t%0,(%z3),%4%p1"
2393 [(set_attr "type" "vld<order>x")
2394 (set_attr "mode" "<MODE>")])
2396 (define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew"
2397 [(set (match_operand:VEEWEXT8 0 "register_operand" "=&vr, &vr")
2398 (if_then_else:VEEWEXT8
2399 (unspec:<VM>
2400 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2401 (match_operand 5 "vector_length_operand" " rK, rK")
2402 (match_operand 6 "const_int_operand" " i, i")
2403 (match_operand 7 "const_int_operand" " i, i")
2404 (match_operand 8 "const_int_operand" " i, i")
2405 (reg:SI VL_REGNUM)
2406 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2407 (unspec:VEEWEXT8
2408 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2409 (mem:BLK (scratch))
2410 (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2411 (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, 0")))]
2412 "TARGET_VECTOR"
2413 "vl<order>xei<oct_trunc_sew>.v\t%0,(%z3),%4%p1"
2414 [(set_attr "type" "vld<order>x")
2415 (set_attr "mode" "<MODE>")])
2417 ;; DEST eew is smaller than SOURCE eew.
2418 (define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew"
2419 [(set (match_operand:VEEWTRUNC2 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2420 (if_then_else:VEEWTRUNC2
2421 (unspec:<VM>
2422 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2423 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2424 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2425 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2426 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2427 (reg:SI VL_REGNUM)
2428 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2429 (unspec:VEEWTRUNC2
2430 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2431 (mem:BLK (scratch))
2432 (match_operand:<VINDEX_DOUBLE_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2433 (match_operand:VEEWTRUNC2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2434 "TARGET_VECTOR"
2435 "vl<order>xei<double_ext_sew>.v\t%0,(%z3),%4%p1"
2436 [(set_attr "type" "vld<order>x")
2437 (set_attr "mode" "<MODE>")])
2439 (define_insn "@pred_indexed_<order>load<mode>_x4_smaller_eew"
2440 [(set (match_operand:VEEWTRUNC4 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2441 (if_then_else:VEEWTRUNC4
2442 (unspec:<VM>
2443 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2444 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2445 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2446 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2447 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2448 (reg:SI VL_REGNUM)
2449 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2450 (unspec:VEEWTRUNC4
2451 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2452 (mem:BLK (scratch))
2453 (match_operand:<VINDEX_QUAD_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2454 (match_operand:VEEWTRUNC4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2455 "TARGET_VECTOR"
2456 "vl<order>xei<quad_ext_sew>.v\t%0,(%z3),%4%p1"
2457 [(set_attr "type" "vld<order>x")
2458 (set_attr "mode" "<MODE>")])
2460 (define_insn "@pred_indexed_<order>load<mode>_x8_smaller_eew"
2461 [(set (match_operand:VEEWTRUNC8 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2462 (if_then_else:VEEWTRUNC8
2463 (unspec:<VM>
2464 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2465 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2466 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2467 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2468 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2469 (reg:SI VL_REGNUM)
2470 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2471 (unspec:VEEWTRUNC8
2472 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2473 (mem:BLK (scratch))
2474 (match_operand:<VINDEX_OCT_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2475 (match_operand:VEEWTRUNC8 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2476 "TARGET_VECTOR"
2477 "vl<order>xei<oct_ext_sew>.v\t%0,(%z3),%4%p1"
2478 [(set_attr "type" "vld<order>x")
2479 (set_attr "mode" "<MODE>")])
2481 (define_insn "@pred_indexed_<order>store<RATIO64:mode><RATIO64I:mode>"
2482 [(set (mem:BLK (scratch))
2483 (unspec:BLK
2484 [(unspec:<VM>
2485 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2486 (match_operand 4 "vector_length_operand" " rK")
2487 (match_operand 5 "const_int_operand" " i")
2488 (reg:SI VL_REGNUM)
2489 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2490 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2491 (match_operand:RATIO64I 2 "register_operand" " vr")
2492 (match_operand:RATIO64 3 "register_operand" " vr")] ORDER))]
2493 "TARGET_VECTOR"
2494 "vs<order>xei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
2495 [(set_attr "type" "vst<order>x")
2496 (set_attr "mode" "<RATIO64:MODE>")])
2498 (define_insn "@pred_indexed_<order>store<RATIO32:mode><RATIO32I:mode>"
2499 [(set (mem:BLK (scratch))
2500 (unspec:BLK
2501 [(unspec:<VM>
2502 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2503 (match_operand 4 "vector_length_operand" " rK")
2504 (match_operand 5 "const_int_operand" " i")
2505 (reg:SI VL_REGNUM)
2506 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2507 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2508 (match_operand:RATIO32I 2 "register_operand" " vr")
2509 (match_operand:RATIO32 3 "register_operand" " vr")] ORDER))]
2510 "TARGET_VECTOR"
2511 "vs<order>xei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
2512 [(set_attr "type" "vst<order>x")
2513 (set_attr "mode" "<RATIO32:MODE>")])
2515 (define_insn "@pred_indexed_<order>store<RATIO16:mode><RATIO16I:mode>"
2516 [(set (mem:BLK (scratch))
2517 (unspec:BLK
2518 [(unspec:<VM>
2519 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2520 (match_operand 4 "vector_length_operand" " rK")
2521 (match_operand 5 "const_int_operand" " i")
2522 (reg:SI VL_REGNUM)
2523 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2524 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2525 (match_operand:RATIO16I 2 "register_operand" " vr")
2526 (match_operand:RATIO16 3 "register_operand" " vr")] ORDER))]
2527 "TARGET_VECTOR"
2528 "vs<order>xei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
2529 [(set_attr "type" "vst<order>x")
2530 (set_attr "mode" "<RATIO16:MODE>")])
2532 (define_insn "@pred_indexed_<order>store<RATIO8:mode><RATIO8I:mode>"
2533 [(set (mem:BLK (scratch))
2534 (unspec:BLK
2535 [(unspec:<VM>
2536 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2537 (match_operand 4 "vector_length_operand" " rK")
2538 (match_operand 5 "const_int_operand" " i")
2539 (reg:SI VL_REGNUM)
2540 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2541 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2542 (match_operand:RATIO8I 2 "register_operand" " vr")
2543 (match_operand:RATIO8 3 "register_operand" " vr")] ORDER))]
2544 "TARGET_VECTOR"
2545 "vs<order>xei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
2546 [(set_attr "type" "vst<order>x")
2547 (set_attr "mode" "<RATIO8:MODE>")])
2549 (define_insn "@pred_indexed_<order>store<RATIO4:mode><RATIO4I:mode>"
2550 [(set (mem:BLK (scratch))
2551 (unspec:BLK
2552 [(unspec:<VM>
2553 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2554 (match_operand 4 "vector_length_operand" " rK")
2555 (match_operand 5 "const_int_operand" " i")
2556 (reg:SI VL_REGNUM)
2557 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2558 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2559 (match_operand:RATIO4I 2 "register_operand" " vr")
2560 (match_operand:RATIO4 3 "register_operand" " vr")] ORDER))]
2561 "TARGET_VECTOR"
2562 "vs<order>xei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
2563 [(set_attr "type" "vst<order>x")
2564 (set_attr "mode" "<RATIO4:MODE>")])
2566 (define_insn "@pred_indexed_<order>store<RATIO2:mode><RATIO2I:mode>"
2567 [(set (mem:BLK (scratch))
2568 (unspec:BLK
2569 [(unspec:<VM>
2570 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2571 (match_operand 4 "vector_length_operand" " rK")
2572 (match_operand 5 "const_int_operand" " i")
2573 (reg:SI VL_REGNUM)
2574 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2575 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2576 (match_operand:RATIO2I 2 "register_operand" " vr")
2577 (match_operand:RATIO2 3 "register_operand" " vr")] ORDER))]
2578 "TARGET_VECTOR"
2579 "vs<order>xei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
2580 [(set_attr "type" "vst<order>x")
2581 (set_attr "mode" "<RATIO2:MODE>")])
2583 (define_insn "@pred_indexed_<order>store<RATIO1:mode><RATIO1:mode>"
2584 [(set (mem:BLK (scratch))
2585 (unspec:BLK
2586 [(unspec:<VM>
2587 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2588 (match_operand 4 "vector_length_operand" " rK")
2589 (match_operand 5 "const_int_operand" " i")
2590 (reg:SI VL_REGNUM)
2591 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2592 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2593 (match_operand:RATIO1 2 "register_operand" " vr")
2594 (match_operand:RATIO1 3 "register_operand" " vr")] ORDER))]
2595 "TARGET_VECTOR"
2596 "vs<order>xei<RATIO1:sew>.v\t%3,(%z1),%2%p0"
2597 [(set_attr "type" "vst<order>x")
2598 (set_attr "mode" "<RATIO1:MODE>")])
2600 ;; -------------------------------------------------------------------------------
2601 ;; ---- Predicated integer binary operations
2602 ;; -------------------------------------------------------------------------------
2603 ;; Includes:
2604 ;; - 11.1 Vector Single-Width Integer Add and Subtract
2605 ;; - 11.4 Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions
2606 ;; - 11.5 Vector Bitwise Logical Instructions
2607 ;; - 11.6 Vector Single-Width Bit Shift Instructions
2608 ;; - 11.9 Vector Integer Min/Max Instructions
2609 ;; - 11.10 Vector Single-Width Integer Multiply Instructions
2610 ;; - 11.11 Vector Integer Divide Instructions
2611 ;; -------------------------------------------------------------------------------
2613 (define_insn "@pred_<optab><mode>"
2614 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
2615 (if_then_else:V_VLSI
2616 (unspec:<VM>
2617 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
2618 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2619 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2620 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2621 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2622 (reg:SI VL_REGNUM)
2623 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2624 (any_int_binop:V_VLSI
2625 (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
2626 (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
2627 (match_operand:V_VLSI 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
2628 "TARGET_VECTOR"
2629 "@
2630 v<insn>.vv\t%0,%3,%4%p1
2631 v<insn>.vv\t%0,%3,%4%p1
2632 v<insn>.vv\t%0,%3,%4%p1
2633 v<insn>.vv\t%0,%3,%4%p1
2634 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2635 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2636 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2637 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2638 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2639 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2640 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2641 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
2642 [(set_attr "type" "<int_binop_insn_type>")
2643 (set_attr "mode" "<MODE>")])
2645 ;; vx instructions patterns.
2646 ;; Note: Unlike vv patterns, we should split them since they are variant.
2647 ;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the
2648 ;; scalar mode is inner mode of the RVV mode for other vx patterns.
2649 (define_insn "@pred_<optab><mode>_scalar"
2650 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr,vd,vd, vr, vr")
2651 (if_then_else:V_VLSI
2652 (unspec:<VM>
2653 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
2654 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK,rK,rK, rK, rK")
2655 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2656 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2657 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
2658 (reg:SI VL_REGNUM)
2659 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2660 (any_shift:V_VLSI
2661 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr,vr,vr, vr, vr")
2662 (match_operand 4 "pmode_reg_or_uimm5_operand" " r, r, r, r, K, K, K, K"))
2663 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0,vu, 0, vu, 0")))]
2664 "TARGET_VECTOR"
2665 "v<insn>.v%o4\t%0,%3,%4%p1"
2666 [(set_attr "type" "vshift")
2667 (set_attr "mode" "<MODE>")])
2669 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
2670 (define_insn "@pred_<optab><mode>_scalar"
2671 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2672 (if_then_else:V_VLSI_QHS
2673 (unspec:<VM>
2674 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2675 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2676 (match_operand 6 "const_int_operand" " i, i, i, i")
2677 (match_operand 7 "const_int_operand" " i, i, i, i")
2678 (match_operand 8 "const_int_operand" " i, i, i, i")
2679 (reg:SI VL_REGNUM)
2680 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2681 (any_commutative_binop:V_VLSI_QHS
2682 (vec_duplicate:V_VLSI_QHS
2683 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2684 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2685 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2686 "TARGET_VECTOR"
2687 "v<insn>.vx\t%0,%3,%z4%p1"
2688 [(set_attr "type" "<int_binop_insn_type>")
2689 (set_attr "mode" "<MODE>")])
2691 (define_insn "@pred_<optab><mode>_scalar"
2692 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2693 (if_then_else:V_VLSI_QHS
2694 (unspec:<VM>
2695 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2696 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2697 (match_operand 6 "const_int_operand" " i, i, i, i")
2698 (match_operand 7 "const_int_operand" " i, i, i, i")
2699 (match_operand 8 "const_int_operand" " i, i, i, i")
2700 (reg:SI VL_REGNUM)
2701 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2702 (any_non_commutative_binop:V_VLSI_QHS
2703 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr")
2704 (vec_duplicate:V_VLSI_QHS
2705 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2706 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2707 "TARGET_VECTOR"
2708 "v<insn>.vx\t%0,%3,%z4%p1"
2709 [(set_attr "type" "<int_binop_insn_type>")
2710 (set_attr "mode" "<MODE>")])
2712 (define_insn "@pred_sub<mode>_reverse_scalar"
2713 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2714 (if_then_else:V_VLSI_QHS
2715 (unspec:<VM>
2716 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2717 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2718 (match_operand 6 "const_int_operand" " i, i, i, i")
2719 (match_operand 7 "const_int_operand" " i, i, i, i")
2720 (match_operand 8 "const_int_operand" " i, i, i, i")
2721 (reg:SI VL_REGNUM)
2722 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2723 (minus:V_VLSI_QHS
2724 (vec_duplicate:V_VLSI_QHS
2725 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2726 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2727 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2728 "TARGET_VECTOR"
2729 "vrsub.vx\t%0,%3,%z4%p1"
2730 [(set_attr "type" "vialu")
2731 (set_attr "mode" "<MODE>")])
2733 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
2734 ;; we need to deal with SEW = 64 in RV32 system.
2735 (define_expand "@pred_<optab><mode>_scalar"
2736 [(set (match_operand:V_VLSI_D 0 "register_operand")
2737 (if_then_else:V_VLSI_D
2738 (unspec:<VM>
2739 [(match_operand:<VM> 1 "vector_mask_operand")
2740 (match_operand 5 "vector_length_operand")
2741 (match_operand 6 "const_int_operand")
2742 (match_operand 7 "const_int_operand")
2743 (match_operand 8 "const_int_operand")
2744 (reg:SI VL_REGNUM)
2745 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2746 (any_commutative_binop:V_VLSI_D
2747 (vec_duplicate:V_VLSI_D
2748 (match_operand:<VEL> 4 "reg_or_int_operand"))
2749 (match_operand:V_VLSI_D 3 "register_operand"))
2750 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2751 "TARGET_VECTOR"
2752 {
2753 if (riscv_vector::sew64_scalar_helper (
2754 operands,
2755 /* scalar op */&operands[4],
2756 /* vl */operands[5],
2757 <MODE>mode,
2758 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2759 [] (rtx *operands, rtx boardcast_scalar) {
2760 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2761 operands[2], operands[3], boardcast_scalar, operands[5],
2762 operands[6], operands[7], operands[8]));
2763 },
2764 (riscv_vector::avl_type) INTVAL (operands[8])))
2765 DONE;
2766 })
2768 (define_insn "*pred_<optab><mode>_scalar"
2769 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2770 (if_then_else:V_VLSI_D
2771 (unspec:<VM>
2772 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2773 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2774 (match_operand 6 "const_int_operand" " i, i, i, i")
2775 (match_operand 7 "const_int_operand" " i, i, i, i")
2776 (match_operand 8 "const_int_operand" " i, i, i, i")
2777 (reg:SI VL_REGNUM)
2778 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2779 (any_commutative_binop:V_VLSI_D
2780 (vec_duplicate:V_VLSI_D
2781 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2782 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2783 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2784 "TARGET_VECTOR"
2785 "v<insn>.vx\t%0,%3,%z4%p1"
2786 [(set_attr "type" "<int_binop_insn_type>")
2787 (set_attr "mode" "<MODE>")])
2789 (define_insn "*pred_<optab><mode>_extended_scalar"
2790 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2791 (if_then_else:V_VLSI_D
2792 (unspec:<VM>
2793 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2794 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2795 (match_operand 6 "const_int_operand" " i, i, i, i")
2796 (match_operand 7 "const_int_operand" " i, i, i, i")
2797 (match_operand 8 "const_int_operand" " i, i, i, i")
2798 (reg:SI VL_REGNUM)
2799 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2800 (any_commutative_binop:V_VLSI_D
2801 (vec_duplicate:V_VLSI_D
2802 (sign_extend:<VEL>
2803 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2804 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2805 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2806 "TARGET_VECTOR && !TARGET_64BIT"
2807 "v<insn>.vx\t%0,%3,%z4%p1"
2808 [(set_attr "type" "<int_binop_insn_type>")
2809 (set_attr "mode" "<MODE>")])
2811 (define_expand "@pred_<optab><mode>_scalar"
2812 [(set (match_operand:V_VLSI_D 0 "register_operand")
2813 (if_then_else:V_VLSI_D
2814 (unspec:<VM>
2815 [(match_operand:<VM> 1 "vector_mask_operand")
2816 (match_operand 5 "vector_length_operand")
2817 (match_operand 6 "const_int_operand")
2818 (match_operand 7 "const_int_operand")
2819 (match_operand 8 "const_int_operand")
2820 (reg:SI VL_REGNUM)
2821 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2822 (any_non_commutative_binop:V_VLSI_D
2823 (match_operand:V_VLSI_D 3 "register_operand")
2824 (vec_duplicate:V_VLSI_D
2825 (match_operand:<VEL> 4 "reg_or_int_operand")))
2826 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2827 "TARGET_VECTOR"
2828 {
2829 if (riscv_vector::sew64_scalar_helper (
2830 operands,
2831 /* scalar op */&operands[4],
2832 /* vl */operands[5],
2833 <MODE>mode,
2834 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2835 [] (rtx *operands, rtx boardcast_scalar) {
2836 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2837 operands[2], operands[3], boardcast_scalar, operands[5],
2838 operands[6], operands[7], operands[8]));
2839 },
2840 (riscv_vector::avl_type) INTVAL (operands[8])))
2841 DONE;
2842 })
2844 (define_insn "*pred_<optab><mode>_scalar"
2845 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2846 (if_then_else:V_VLSI_D
2847 (unspec:<VM>
2848 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2849 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2850 (match_operand 6 "const_int_operand" " i, i, i, i")
2851 (match_operand 7 "const_int_operand" " i, i, i, i")
2852 (match_operand 8 "const_int_operand" " i, i, i, i")
2853 (reg:SI VL_REGNUM)
2854 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2855 (any_non_commutative_binop:V_VLSI_D
2856 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2857 (vec_duplicate:V_VLSI_D
2858 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2859 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2860 "TARGET_VECTOR"
2861 "v<insn>.vx\t%0,%3,%z4%p1"
2862 [(set_attr "type" "<int_binop_insn_type>")
2863 (set_attr "mode" "<MODE>")])
2865 (define_insn "*pred_<optab><mode>_extended_scalar"
2866 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2867 (if_then_else:V_VLSI_D
2868 (unspec:<VM>
2869 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2870 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2871 (match_operand 6 "const_int_operand" " i, i, i, i")
2872 (match_operand 7 "const_int_operand" " i, i, i, i")
2873 (match_operand 8 "const_int_operand" " i, i, i, i")
2874 (reg:SI VL_REGNUM)
2875 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2876 (any_non_commutative_binop:V_VLSI_D
2877 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2878 (vec_duplicate:V_VLSI_D
2879 (sign_extend:<VEL>
2880 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
2881 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2882 "TARGET_VECTOR && !TARGET_64BIT"
2883 "v<insn>.vx\t%0,%3,%z4%p1"
2884 [(set_attr "type" "<int_binop_insn_type>")
2885 (set_attr "mode" "<MODE>")])
2887 (define_expand "@pred_sub<mode>_reverse_scalar"
2888 [(set (match_operand:V_VLSI_D 0 "register_operand")
2889 (if_then_else:V_VLSI_D
2890 (unspec:<VM>
2891 [(match_operand:<VM> 1 "vector_mask_operand")
2892 (match_operand 5 "vector_length_operand")
2893 (match_operand 6 "const_int_operand")
2894 (match_operand 7 "const_int_operand")
2895 (match_operand 8 "const_int_operand")
2896 (reg:SI VL_REGNUM)
2897 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2898 (minus:V_VLSI_D
2899 (vec_duplicate:V_VLSI_D
2900 (match_operand:<VEL> 4 "reg_or_int_operand"))
2901 (match_operand:V_VLSI_D 3 "register_operand"))
2902 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2903 "TARGET_VECTOR"
2904 {
2905 if (riscv_vector::sew64_scalar_helper (
2906 operands,
2907 /* scalar op */&operands[4],
2908 /* vl */operands[5],
2909 <MODE>mode,
2910 riscv_vector::neg_simm5_p (operands[4]),
2911 [] (rtx *operands, rtx boardcast_scalar) {
2912 emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
2913 operands[2], boardcast_scalar, operands[3], operands[5],
2914 operands[6], operands[7], operands[8]));
2915 },
2916 (riscv_vector::avl_type) INTVAL (operands[8])))
2917 DONE;
2918 })
2920 (define_insn "*pred_sub<mode>_reverse_scalar"
2921 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2922 (if_then_else:V_VLSI_D
2923 (unspec:<VM>
2924 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2925 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2926 (match_operand 6 "const_int_operand" " i, i, i, i")
2927 (match_operand 7 "const_int_operand" " i, i, i, i")
2928 (match_operand 8 "const_int_operand" " i, i, i, i")
2929 (reg:SI VL_REGNUM)
2930 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2931 (minus:V_VLSI_D
2932 (vec_duplicate:V_VLSI_D
2933 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2934 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2935 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2936 "TARGET_VECTOR"
2937 "vrsub.vx\t%0,%3,%z4%p1"
2938 [(set_attr "type" "vialu")
2939 (set_attr "mode" "<MODE>")])
2941 (define_insn "*pred_sub<mode>_extended_reverse_scalar"
2942 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2943 (if_then_else:V_VLSI_D
2944 (unspec:<VM>
2945 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2946 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2947 (match_operand 6 "const_int_operand" " i, i, i, i")
2948 (match_operand 7 "const_int_operand" " i, i, i, i")
2949 (match_operand 8 "const_int_operand" " i, i, i, i")
2950 (reg:SI VL_REGNUM)
2951 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2952 (minus:V_VLSI_D
2953 (vec_duplicate:V_VLSI_D
2954 (sign_extend:<VEL>
2955 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2956 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2957 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2958 "TARGET_VECTOR && !TARGET_64BIT"
2959 "vrsub.vx\t%0,%3,%z4%p1"
2960 [(set_attr "type" "vialu")
2961 (set_attr "mode" "<MODE>")])
2963 ;; Multiply High instructions.
2964 (define_insn "@pred_mulh<v_su><mode>"
2965 [(set (match_operand:VFULLI 0 "register_operand" "=vd,vd, vr, vr")
2966 (if_then_else:VFULLI
2967 (unspec:<VM>
2968 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2969 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2970 (match_operand 6 "const_int_operand" " i, i, i, i")
2971 (match_operand 7 "const_int_operand" " i, i, i, i")
2972 (match_operand 8 "const_int_operand" " i, i, i, i")
2973 (reg:SI VL_REGNUM)
2974 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2975 (unspec:VFULLI
2976 [(match_operand:VFULLI 3 "register_operand" "vr,vr, vr, vr")
2977 (match_operand:VFULLI 4 "register_operand" "vr,vr, vr, vr")] VMULH)
2978 (match_operand:VFULLI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2979 "TARGET_VECTOR"
2980 "vmulh<v_su>.vv\t%0,%3,%4%p1"
2981 [(set_attr "type" "vimul")
2982 (set_attr "mode" "<MODE>")])
2984 (define_insn "@pred_mulh<v_su><mode>_scalar"
2985 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2986 (if_then_else:VI_QHS
2987 (unspec:<VM>
2988 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2989 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2990 (match_operand 6 "const_int_operand" " i, i, i, i")
2991 (match_operand 7 "const_int_operand" " i, i, i, i")
2992 (match_operand 8 "const_int_operand" " i, i, i, i")
2993 (reg:SI VL_REGNUM)
2994 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2995 (unspec:VI_QHS
2996 [(vec_duplicate:VI_QHS
2997 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2998 (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2999 (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3000 "TARGET_VECTOR"
3001 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
3002 [(set_attr "type" "vimul")
3003 (set_attr "mode" "<MODE>")])
3005 (define_expand "@pred_mulh<v_su><mode>_scalar"
3006 [(set (match_operand:VFULLI_D 0 "register_operand")
3007 (if_then_else:VFULLI_D
3008 (unspec:<VM>
3009 [(match_operand:<VM> 1 "vector_mask_operand")
3010 (match_operand 5 "vector_length_operand")
3011 (match_operand 6 "const_int_operand")
3012 (match_operand 7 "const_int_operand")
3013 (match_operand 8 "const_int_operand")
3014 (reg:SI VL_REGNUM)
3015 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3016 (unspec:VFULLI_D
3017 [(vec_duplicate:VFULLI_D
3018 (match_operand:<VEL> 4 "reg_or_int_operand"))
3019 (match_operand:VFULLI_D 3 "register_operand")] VMULH)
3020 (match_operand:VFULLI_D 2 "vector_merge_operand")))]
3021 "TARGET_VECTOR"
3022 {
3023 if (riscv_vector::sew64_scalar_helper (
3024 operands,
3025 /* scalar op */&operands[4],
3026 /* vl */operands[5],
3027 <MODE>mode,
3028 false,
3029 [] (rtx *operands, rtx boardcast_scalar) {
3030 emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
3031 operands[2], operands[3], boardcast_scalar, operands[5],
3032 operands[6], operands[7], operands[8]));
3033 },
3034 (riscv_vector::avl_type) INTVAL (operands[8])))
3035 DONE;
3036 })
3038 (define_insn "*pred_mulh<v_su><mode>_scalar"
3039 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
3040 (if_then_else:VFULLI_D
3041 (unspec:<VM>
3042 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3043 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
3044 (match_operand 6 "const_int_operand" " i, i, i, i")
3045 (match_operand 7 "const_int_operand" " i, i, i, i")
3046 (match_operand 8 "const_int_operand" " i, i, i, i")
3047 (reg:SI VL_REGNUM)
3048 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3049 (unspec:VFULLI_D
3050 [(vec_duplicate:VFULLI_D
3051 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
3052 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
3053 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3054 "TARGET_VECTOR"
3055 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
3056 [(set_attr "type" "vimul")
3057 (set_attr "mode" "<MODE>")])
3059 (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
3060 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
3061 (if_then_else:VFULLI_D
3062 (unspec:<VM>
3063 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3064 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
3065 (match_operand 6 "const_int_operand" " i, i, i, i")
3066 (match_operand 7 "const_int_operand" " i, i, i, i")
3067 (match_operand 8 "const_int_operand" " i, i, i, i")
3068 (reg:SI VL_REGNUM)
3069 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3070 (unspec:VFULLI_D
3071 [(vec_duplicate:VFULLI_D
3072 (sign_extend:<VEL>
3073 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
3074 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
3075 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3076 "TARGET_VECTOR && !TARGET_64BIT"
3077 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
3078 [(set_attr "type" "vimul")
3079 (set_attr "mode" "<MODE>")])
3081 ;; Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
3082 (define_insn "@pred_adc<mode>"
3083 [(set (match_operand:VI 0 "register_operand" "=vd,vd,vd,vd")
3084 (if_then_else:VI
3085 (unspec:<VM>
3086 [(match_operand 5 "vector_length_operand" "rK,rK,rK,rK")
3087 (match_operand 6 "const_int_operand" " i, i, i, i")
3088 (match_operand 7 "const_int_operand" " i, i, i, i")
3089 (reg:SI VL_REGNUM)
3090 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3091 (unspec:VI
3092 [(plus:VI
3093 (match_operand:VI 2 "register_operand" "vr,vr,vr,vr")
3094 (match_operand:VI 3 "vector_arith_operand" "vr,vr,vi,vi"))
3095 (match_operand:<VM> 4 "register_operand" "vm,vm,vm,vm")] UNSPEC_VADC)
3096 (match_operand:VI 1 "vector_merge_operand" "vu, 0,vu, 0")))]
3097 "TARGET_VECTOR"
3098 "vadc.v%o3m\t%0,%2,%v3,%4"
3099 [(set_attr "type" "vicalu")
3100 (set_attr "mode" "<MODE>")
3101 (set_attr "merge_op_idx" "1")
3102 (set_attr "vl_op_idx" "5")
3103 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3104 (set (attr "avl_type_idx") (const_int 7))])
3106 (define_insn "@pred_sbc<mode>"
3107 [(set (match_operand:VI 0 "register_operand" "=vd,vd")
3108 (if_then_else:VI
3109 (unspec:<VM>
3110 [(match_operand 5 "vector_length_operand" "rK,rK")
3111 (match_operand 6 "const_int_operand" " i, i")
3112 (match_operand 7 "const_int_operand" " i, i")
3113 (reg:SI VL_REGNUM)
3114 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3115 (unspec:VI
3116 [(minus:VI
3117 (match_operand:VI 2 "register_operand" "vr,vr")
3118 (match_operand:VI 3 "register_operand" "vr,vr"))
3119 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3120 (match_operand:VI 1 "vector_merge_operand" "vu, 0")))]
3121 "TARGET_VECTOR"
3122 "vsbc.vvm\t%0,%2,%3,%4"
3123 [(set_attr "type" "vicalu")
3124 (set_attr "mode" "<MODE>")
3125 (set_attr "merge_op_idx" "1")
3126 (set_attr "vl_op_idx" "5")
3127 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3128 (set (attr "avl_type_idx") (const_int 7))])
3130 (define_insn "@pred_adc<mode>_scalar"
3131 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3132 (if_then_else:VI_QHS
3133 (unspec:<VM>
3134 [(match_operand 5 "vector_length_operand" "rK,rK")
3135 (match_operand 6 "const_int_operand" " i, i")
3136 (match_operand 7 "const_int_operand" " i, i")
3137 (reg:SI VL_REGNUM)
3138 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3139 (unspec:VI_QHS
3140 [(plus:VI_QHS
3141 (vec_duplicate:VI_QHS
3142 (match_operand:<VEL> 3 "register_operand" " r, r"))
3143 (match_operand:VI_QHS 2 "register_operand" "vr,vr"))
3144 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3145 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3146 "TARGET_VECTOR"
3147 "vadc.vxm\t%0,%2,%3,%4"
3148 [(set_attr "type" "vicalu")
3149 (set_attr "mode" "<MODE>")
3150 (set_attr "merge_op_idx" "1")
3151 (set_attr "vl_op_idx" "5")
3152 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3153 (set (attr "avl_type_idx") (const_int 7))])
3155 (define_insn "@pred_sbc<mode>_scalar"
3156 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3157 (if_then_else:VI_QHS
3158 (unspec:<VM>
3159 [(match_operand 5 "vector_length_operand" "rK,rK")
3160 (match_operand 6 "const_int_operand" " i, i")
3161 (match_operand 7 "const_int_operand" " i, i")
3162 (reg:SI VL_REGNUM)
3163 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3164 (unspec:VI_QHS
3165 [(minus:VI_QHS
3166 (match_operand:VI_QHS 2 "register_operand" "vr,vr")
3167 (vec_duplicate:VI_QHS
3168 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3169 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3170 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3171 "TARGET_VECTOR"
3172 "vsbc.vxm\t%0,%2,%z3,%4"
3173 [(set_attr "type" "vicalu")
3174 (set_attr "mode" "<MODE>")
3175 (set_attr "merge_op_idx" "1")
3176 (set_attr "vl_op_idx" "5")
3177 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3178 (set (attr "avl_type_idx") (const_int 7))])
3180 (define_expand "@pred_adc<mode>_scalar"
3181 [(set (match_operand:VI_D 0 "register_operand")
3182 (if_then_else:VI_D
3183 (unspec:<VM>
3184 [(match_operand 5 "vector_length_operand")
3185 (match_operand 6 "const_int_operand")
3186 (match_operand 7 "const_int_operand")
3187 (reg:SI VL_REGNUM)
3188 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3189 (unspec:VI_D
3190 [(plus:VI_D
3191 (vec_duplicate:VI_D
3192 (match_operand:<VEL> 3 "reg_or_int_operand"))
3193 (match_operand:VI_D 2 "register_operand"))
3194 (match_operand:<VM> 4 "register_operand")] UNSPEC_VADC)
3195 (match_operand:VI_D 1 "vector_merge_operand")))]
3196 "TARGET_VECTOR"
3197 {
3198 if (riscv_vector::sew64_scalar_helper (
3199 operands,
3200 /* scalar op */&operands[3],
3201 /* vl */operands[5],
3202 <MODE>mode,
3203 riscv_vector::simm5_p (operands[3]),
3204 [] (rtx *operands, rtx boardcast_scalar) {
3205 emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
3206 operands[2], boardcast_scalar, operands[4], operands[5],
3207 operands[6], operands[7]));
3208 },
3209 (riscv_vector::avl_type) INTVAL (operands[7])))
3210 DONE;
3211 })
3213 (define_insn "*pred_adc<mode>_scalar"
3214 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3215 (if_then_else:VI_D
3216 (unspec:<VM>
3217 [(match_operand 5 "vector_length_operand" "rK,rK")
3218 (match_operand 6 "const_int_operand" " i, i")
3219 (match_operand 7 "const_int_operand" " i, i")
3220 (reg:SI VL_REGNUM)
3221 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3222 (unspec:VI_D
3223 [(plus:VI_D
3224 (vec_duplicate:VI_D
3225 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ"))
3226 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3227 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3228 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3229 "TARGET_VECTOR"
3230 "vadc.vxm\t%0,%2,%z3,%4"
3231 [(set_attr "type" "vicalu")
3232 (set_attr "mode" "<MODE>")
3233 (set_attr "merge_op_idx" "1")
3234 (set_attr "vl_op_idx" "5")
3235 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3236 (set (attr "avl_type_idx") (const_int 7))])
3238 (define_insn "*pred_adc<mode>_extended_scalar"
3239 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3240 (if_then_else:VI_D
3241 (unspec:<VM>
3242 [(match_operand 5 "vector_length_operand" "rK,rK")
3243 (match_operand 6 "const_int_operand" " i, i")
3244 (match_operand 7 "const_int_operand" " i, i")
3245 (reg:SI VL_REGNUM)
3246 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3247 (unspec:VI_D
3248 [(plus:VI_D
3249 (vec_duplicate:VI_D
3250 (sign_extend:<VEL>
3251 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ")))
3252 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3253 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3254 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3255 "TARGET_VECTOR && !TARGET_64BIT"
3256 "vadc.vxm\t%0,%2,%z3,%4"
3257 [(set_attr "type" "vicalu")
3258 (set_attr "mode" "<MODE>")
3259 (set_attr "merge_op_idx" "1")
3260 (set_attr "vl_op_idx" "5")
3261 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3262 (set (attr "avl_type_idx") (const_int 7))])
3264 (define_expand "@pred_sbc<mode>_scalar"
3265 [(set (match_operand:VI_D 0 "register_operand")
3266 (if_then_else:VI_D
3267 (unspec:<VM>
3268 [(match_operand 5 "vector_length_operand")
3269 (match_operand 6 "const_int_operand")
3270 (match_operand 7 "const_int_operand")
3271 (reg:SI VL_REGNUM)
3272 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3273 (unspec:VI_D
3274 [(minus:VI_D
3275 (match_operand:VI_D 2 "register_operand")
3276 (vec_duplicate:VI_D
3277 (match_operand:<VEL> 3 "reg_or_int_operand")))
3278 (match_operand:<VM> 4 "register_operand")] UNSPEC_VSBC)
3279 (match_operand:VI_D 1 "vector_merge_operand")))]
3280 "TARGET_VECTOR"
3281 {
3282 if (riscv_vector::sew64_scalar_helper (
3283 operands,
3284 /* scalar op */&operands[3],
3285 /* vl */operands[5],
3286 <MODE>mode,
3287 false,
3288 [] (rtx *operands, rtx boardcast_scalar) {
3289 emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
3290 operands[2], boardcast_scalar, operands[4], operands[5],
3291 operands[6], operands[7]));
3292 },
3293 (riscv_vector::avl_type) INTVAL (operands[7])))
3294 DONE;
3295 })
3297 (define_insn "*pred_sbc<mode>_scalar"
3298 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3299 (if_then_else:VI_D
3300 (unspec:<VM>
3301 [(match_operand 5 "vector_length_operand" "rK,rK")
3302 (match_operand 6 "const_int_operand" " i, i")
3303 (match_operand 7 "const_int_operand" " i, i")
3304 (reg:SI VL_REGNUM)
3305 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3306 (unspec:VI_D
3307 [(minus:VI_D
3308 (match_operand:VI_D 2 "register_operand" "vr,vr")
3309 (vec_duplicate:VI_D
3310 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3311 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3312 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3313 "TARGET_VECTOR"
3314 "vsbc.vxm\t%0,%2,%z3,%4"
3315 [(set_attr "type" "vicalu")
3316 (set_attr "mode" "<MODE>")
3317 (set_attr "merge_op_idx" "1")
3318 (set_attr "vl_op_idx" "5")
3319 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3320 (set (attr "avl_type_idx") (const_int 7))])
3322 (define_insn "*pred_sbc<mode>_extended_scalar"
3323 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3324 (if_then_else:VI_D
3325 (unspec:<VM>
3326 [(match_operand 5 "vector_length_operand" "rK,rK")
3327 (match_operand 6 "const_int_operand" " i, i")
3328 (match_operand 7 "const_int_operand" " i, i")
3329 (reg:SI VL_REGNUM)
3330 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3331 (unspec:VI_D
3332 [(minus:VI_D
3333 (match_operand:VI_D 2 "register_operand" "vr,vr")
3334 (vec_duplicate:VI_D
3335 (sign_extend:<VEL>
3336 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ"))))
3337 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3338 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3339 "TARGET_VECTOR && !TARGET_64BIT"
3340 "vsbc.vxm\t%0,%2,%z3,%4"
3341 [(set_attr "type" "vicalu")
3342 (set_attr "mode" "<MODE>")
3343 (set_attr "merge_op_idx" "1")
3344 (set_attr "vl_op_idx" "5")
3345 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3346 (set (attr "avl_type_idx") (const_int 7))])
3348 (define_insn "@pred_madc<mode>"
3349 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3350 (unspec:<VM>
3351 [(plus:VI
3352 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3353 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3354 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3355 (unspec:<VM>
3356 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3357 (match_operand 5 "const_int_operand" " i, i, i")
3358 (reg:SI VL_REGNUM)
3359 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3360 "TARGET_VECTOR"
3361 "vmadc.v%o2m\t%0,%1,%v2,%3"
3362 [(set_attr "type" "vicalu")
3363 (set_attr "mode" "<MODE>")
3364 (set_attr "vl_op_idx" "4")
3365 (set (attr "avl_type_idx") (const_int 5))
3366 (set_attr "spec_restriction" "thv,none,none")])
3368 (define_insn "@pred_msbc<mode>"
3369 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
3370 (unspec:<VM>
3371 [(minus:VI
3372 (match_operand:VI 1 "register_operand" " 0, vr, vr")
3373 (match_operand:VI 2 "register_operand" " vr, 0, vr"))
3374 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3375 (unspec:<VM>
3376 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3377 (match_operand 5 "const_int_operand" " i, i, i")
3378 (reg:SI VL_REGNUM)
3379 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3380 "TARGET_VECTOR"
3381 "vmsbc.vvm\t%0,%1,%2,%3"
3382 [(set_attr "type" "vicalu")
3383 (set_attr "mode" "<MODE>")
3384 (set_attr "vl_op_idx" "4")
3385 (set (attr "avl_type_idx") (const_int 5))
3386 (set_attr "spec_restriction" "thv,thv,none")])
3388 (define_insn "@pred_madc<mode>_scalar"
3389 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3390 (unspec:<VM>
3391 [(plus:VI_QHS
3392 (vec_duplicate:VI_QHS
3393 (match_operand:<VEL> 2 "register_operand" " r, r"))
3394 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3395 (match_operand:<VM> 3 "register_operand" " vm, vm")
3396 (unspec:<VM>
3397 [(match_operand 4 "vector_length_operand" " rK, rK")
3398 (match_operand 5 "const_int_operand" " i, i")
3399 (reg:SI VL_REGNUM)
3400 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3401 "TARGET_VECTOR"
3402 "vmadc.vxm\t%0,%1,%2,%3"
3403 [(set_attr "type" "vicalu")
3404 (set_attr "mode" "<MODE>")
3405 (set_attr "vl_op_idx" "4")
3406 (set (attr "avl_type_idx") (const_int 5))
3407 (set_attr "spec_restriction" "thv,none")])
3409 (define_insn "@pred_msbc<mode>_scalar"
3410 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3411 (unspec:<VM>
3412 [(minus:VI_QHS
3413 (vec_duplicate:VI_QHS
3414 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3415 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3416 (match_operand:<VM> 3 "register_operand" " vm, vm")
3417 (unspec:<VM>
3418 [(match_operand 4 "vector_length_operand" " rK, rK")
3419 (match_operand 5 "const_int_operand" " i, i")
3420 (reg:SI VL_REGNUM)
3421 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3422 "TARGET_VECTOR"
3423 "vmsbc.vxm\t%0,%1,%z2,%3"
3424 [(set_attr "type" "vicalu")
3425 (set_attr "mode" "<MODE>")
3426 (set_attr "vl_op_idx" "4")
3427 (set (attr "avl_type_idx") (const_int 5))
3428 (set_attr "spec_restriction" "thv,none")])
3430 (define_expand "@pred_madc<mode>_scalar"
3431 [(set (match_operand:<VM> 0 "register_operand")
3432 (unspec:<VM>
3433 [(plus:VI_D
3434 (vec_duplicate:VI_D
3435 (match_operand:<VEL> 2 "reg_or_int_operand"))
3436 (match_operand:VI_D 1 "register_operand"))
3437 (match_operand:<VM> 3 "register_operand")
3438 (unspec:<VM>
3439 [(match_operand 4 "vector_length_operand")
3440 (match_operand 5 "const_int_operand")
3441 (reg:SI VL_REGNUM)
3442 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3443 "TARGET_VECTOR"
3444 {
3445 if (riscv_vector::sew64_scalar_helper (
3446 operands,
3447 /* scalar op */&operands[2],
3448 /* vl */operands[4],
3449 <MODE>mode,
3450 riscv_vector::simm5_p (operands[2]),
3451 [] (rtx *operands, rtx boardcast_scalar) {
3452 emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
3453 boardcast_scalar, operands[3], operands[4], operands[5]));
3454 },
3455 (riscv_vector::avl_type) INTVAL (operands[5])))
3456 DONE;
3457 })
3459 (define_insn "*pred_madc<mode>_scalar"
3460 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3461 (unspec:<VM>
3462 [(plus:VI_D
3463 (vec_duplicate:VI_D
3464 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3465 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3466 (match_operand:<VM> 3 "register_operand" " vm, vm")
3467 (unspec:<VM>
3468 [(match_operand 4 "vector_length_operand" " rK, rK")
3469 (match_operand 5 "const_int_operand" " i, i")
3470 (reg:SI VL_REGNUM)
3471 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3472 "TARGET_VECTOR"
3473 "vmadc.vxm\t%0,%1,%z2,%3"
3474 [(set_attr "type" "vicalu")
3475 (set_attr "mode" "<MODE>")
3476 (set_attr "vl_op_idx" "4")
3477 (set (attr "avl_type_idx") (const_int 5))
3478 (set_attr "spec_restriction" "thv,none")])
3480 (define_insn "*pred_madc<mode>_extended_scalar"
3481 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3482 (unspec:<VM>
3483 [(plus:VI_D
3484 (vec_duplicate:VI_D
3485 (sign_extend:<VEL>
3486 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3487 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3488 (match_operand:<VM> 3 "register_operand" " vm, vm")
3489 (unspec:<VM>
3490 [(match_operand 4 "vector_length_operand" " rK, rK")
3491 (match_operand 5 "const_int_operand" " i, i")
3492 (reg:SI VL_REGNUM)
3493 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3494 "TARGET_VECTOR && !TARGET_64BIT"
3495 "vmadc.vxm\t%0,%1,%z2,%3"
3496 [(set_attr "type" "vicalu")
3497 (set_attr "mode" "<MODE>")
3498 (set_attr "vl_op_idx" "4")
3499 (set (attr "avl_type_idx") (const_int 5))
3500 (set_attr "spec_restriction" "thv,none")])
3502 (define_expand "@pred_msbc<mode>_scalar"
3503 [(set (match_operand:<VM> 0 "register_operand")
3504 (unspec:<VM>
3505 [(minus:VI_D
3506 (vec_duplicate:VI_D
3507 (match_operand:<VEL> 2 "reg_or_int_operand"))
3508 (match_operand:VI_D 1 "register_operand"))
3509 (match_operand:<VM> 3 "register_operand")
3510 (unspec:<VM>
3511 [(match_operand 4 "vector_length_operand")
3512 (match_operand 5 "const_int_operand")
3513 (reg:SI VL_REGNUM)
3514 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3515 "TARGET_VECTOR"
3516 {
3517 if (riscv_vector::sew64_scalar_helper (
3518 operands,
3519 /* scalar op */&operands[2],
3520 /* vl */operands[4],
3521 <MODE>mode,
3522 false,
3523 [] (rtx *operands, rtx boardcast_scalar) {
3524 emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
3525 boardcast_scalar, operands[3], operands[4], operands[5]));
3526 },
3527 (riscv_vector::avl_type) INTVAL (operands[5])))
3528 DONE;
3529 })
3531 (define_insn "*pred_msbc<mode>_scalar"
3532 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3533 (unspec:<VM>
3534 [(minus:VI_D
3535 (vec_duplicate:VI_D
3536 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3537 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3538 (match_operand:<VM> 3 "register_operand" " vm, vm")
3539 (unspec:<VM>
3540 [(match_operand 4 "vector_length_operand" " rK, rK")
3541 (match_operand 5 "const_int_operand" " i, i")
3542 (reg:SI VL_REGNUM)
3543 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3544 "TARGET_VECTOR"
3545 "vmsbc.vxm\t%0,%1,%z2,%3"
3546 [(set_attr "type" "vicalu")
3547 (set_attr "mode" "<MODE>")
3548 (set_attr "vl_op_idx" "4")
3549 (set (attr "avl_type_idx") (const_int 5))
3550 (set_attr "spec_restriction" "thv,none")])
3552 (define_insn "*pred_msbc<mode>_extended_scalar"
3553 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3554 (unspec:<VM>
3555 [(minus:VI_D
3556 (vec_duplicate:VI_D
3557 (sign_extend:<VEL>
3558 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3559 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3560 (match_operand:<VM> 3 "register_operand" " vm, vm")
3561 (unspec:<VM>
3562 [(match_operand 4 "vector_length_operand" " rK, rK")
3563 (match_operand 5 "const_int_operand" " i, i")
3564 (reg:SI VL_REGNUM)
3565 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3566 "TARGET_VECTOR && !TARGET_64BIT"
3567 "vmsbc.vxm\t%0,%1,%z2,%3"
3568 [(set_attr "type" "vicalu")
3569 (set_attr "mode" "<MODE>")
3570 (set_attr "vl_op_idx" "4")
3571 (set (attr "avl_type_idx") (const_int 5))
3572 (set_attr "spec_restriction" "thv,none")])
3574 (define_insn "@pred_madc<mode>_overflow"
3575 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3576 (unspec:<VM>
3577 [(plus:VI
3578 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3579 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3580 (unspec:<VM>
3581 [(match_operand 3 "vector_length_operand" " rK, rK, rK")
3582 (match_operand 4 "const_int_operand" " i, i, i")
3583 (reg:SI VL_REGNUM)
3584 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3585 "TARGET_VECTOR"
3586 "vmadc.v%o2\t%0,%1,%v2"
3587 [(set_attr "type" "vicalu")
3588 (set_attr "mode" "<MODE>")
3589 (set_attr "vl_op_idx" "3")
3590 (set (attr "avl_type_idx") (const_int 4))
3591 (set_attr "spec_restriction" "thv,none,none")])
3593 (define_insn "@pred_msbc<mode>_overflow"
3594 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
3595 (unspec:<VM>
3596 [(minus:VI
3597 (match_operand:VI 1 "register_operand" " 0, vr, vr, vr")
3598 (match_operand:VI 2 "register_operand" " vr, 0, vr, vi"))
3599 (unspec:<VM>
3600 [(match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
3601 (match_operand 4 "const_int_operand" " i, i, i, i")
3602 (reg:SI VL_REGNUM)
3603 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3604 "TARGET_VECTOR"
3605 "vmsbc.vv\t%0,%1,%2"
3606 [(set_attr "type" "vicalu")
3607 (set_attr "mode" "<MODE>")
3608 (set_attr "vl_op_idx" "3")
3609 (set (attr "avl_type_idx") (const_int 4))
3610 (set_attr "spec_restriction" "thv,thv,none,none")])
3612 (define_insn "@pred_madc<mode>_overflow_scalar"
3613 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3614 (unspec:<VM>
3615 [(plus:VI_QHS
3616 (vec_duplicate:VI_QHS
3617 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3618 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3619 (unspec:<VM>
3620 [(match_operand 3 "vector_length_operand" " rK, rK")
3621 (match_operand 4 "const_int_operand" " i, i")
3622 (reg:SI VL_REGNUM)
3623 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3624 "TARGET_VECTOR"
3625 "vmadc.vx\t%0,%1,%z2"
3626 [(set_attr "type" "vicalu")
3627 (set_attr "mode" "<MODE>")
3628 (set_attr "vl_op_idx" "3")
3629 (set (attr "avl_type_idx") (const_int 4))
3630 (set_attr "spec_restriction" "thv,none")])
3632 (define_insn "@pred_msbc<mode>_overflow_scalar"
3633 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3634 (unspec:<VM>
3635 [(minus:VI_QHS
3636 (vec_duplicate:VI_QHS
3637 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3638 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3639 (unspec:<VM>
3640 [(match_operand 3 "vector_length_operand" " rK, rK")
3641 (match_operand 4 "const_int_operand" " i, i")
3642 (reg:SI VL_REGNUM)
3643 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3644 "TARGET_VECTOR"
3645 "vmsbc.vx\t%0,%1,%z2"
3646 [(set_attr "type" "vicalu")
3647 (set_attr "mode" "<MODE>")
3648 (set_attr "vl_op_idx" "3")
3649 (set (attr "avl_type_idx") (const_int 4))
3650 (set_attr "spec_restriction" "thv,none")])
3652 (define_expand "@pred_madc<mode>_overflow_scalar"
3653 [(set (match_operand:<VM> 0 "register_operand")
3654 (unspec:<VM>
3655 [(plus:VI_D
3656 (vec_duplicate:VI_D
3657 (match_operand:<VEL> 2 "reg_or_int_operand"))
3658 (match_operand:VI_D 1 "register_operand"))
3659 (unspec:<VM>
3660 [(match_operand 3 "vector_length_operand")
3661 (match_operand 4 "const_int_operand")
3662 (reg:SI VL_REGNUM)
3663 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3664 "TARGET_VECTOR"
3665 {
3666 if (riscv_vector::sew64_scalar_helper (
3667 operands,
3668 /* scalar op */&operands[2],
3669 /* vl */operands[3],
3670 <MODE>mode,
3671 riscv_vector::simm5_p (operands[2]),
3672 [] (rtx *operands, rtx boardcast_scalar) {
3673 emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
3674 boardcast_scalar, operands[3], operands[4]));
3675 },
3676 (riscv_vector::avl_type) INTVAL (operands[4])))
3677 DONE;
3678 })
3680 (define_insn "*pred_madc<mode>_overflow_scalar"
3681 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3682 (unspec:<VM>
3683 [(plus:VI_D
3684 (vec_duplicate:VI_D
3685 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3686 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3687 (unspec:<VM>
3688 [(match_operand 3 "vector_length_operand" " rK, rK")
3689 (match_operand 4 "const_int_operand" " i, i")
3690 (reg:SI VL_REGNUM)
3691 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3692 "TARGET_VECTOR"
3693 "vmadc.vx\t%0,%1,%z2"
3694 [(set_attr "type" "vicalu")
3695 (set_attr "mode" "<MODE>")
3696 (set_attr "vl_op_idx" "3")
3697 (set (attr "avl_type_idx") (const_int 4))
3698 (set_attr "spec_restriction" "thv,none")])
3700 (define_insn "*pred_madc<mode>_overflow_extended_scalar"
3701 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3702 (unspec:<VM>
3703 [(plus:VI_D
3704 (vec_duplicate:VI_D
3705 (sign_extend:<VEL>
3706 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3707 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3708 (unspec:<VM>
3709 [(match_operand 3 "vector_length_operand" " rK, rK")
3710 (match_operand 4 "const_int_operand" " i, i")
3711 (reg:SI VL_REGNUM)
3712 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3713 "TARGET_VECTOR && !TARGET_64BIT"
3714 "vmadc.vx\t%0,%1,%z2"
3715 [(set_attr "type" "vicalu")
3716 (set_attr "mode" "<MODE>")
3717 (set_attr "vl_op_idx" "3")
3718 (set (attr "avl_type_idx") (const_int 4))
3719 (set_attr "spec_restriction" "thv,none")])
3721 (define_expand "@pred_msbc<mode>_overflow_scalar"
3722 [(set (match_operand:<VM> 0 "register_operand")
3723 (unspec:<VM>
3724 [(minus:VI_D
3725 (vec_duplicate:VI_D
3726 (match_operand:<VEL> 2 "reg_or_int_operand"))
3727 (match_operand:VI_D 1 "register_operand"))
3728 (unspec:<VM>
3729 [(match_operand 3 "vector_length_operand")
3730 (match_operand 4 "const_int_operand")
3731 (reg:SI VL_REGNUM)
3732 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3733 "TARGET_VECTOR"
3734 {
3735 if (riscv_vector::sew64_scalar_helper (
3736 operands,
3737 /* scalar op */&operands[2],
3738 /* vl */operands[3],
3739 <MODE>mode,
3740 false,
3741 [] (rtx *operands, rtx boardcast_scalar) {
3742 emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
3743 boardcast_scalar, operands[3], operands[4]));
3744 },
3745 (riscv_vector::avl_type) INTVAL (operands[4])))
3746 DONE;
3747 })
3749 (define_insn "*pred_msbc<mode>_overflow_scalar"
3750 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3751 (unspec:<VM>
3752 [(minus:VI_D
3753 (vec_duplicate:VI_D
3754 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3755 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3756 (unspec:<VM>
3757 [(match_operand 3 "vector_length_operand" " rK, rK")
3758 (match_operand 4 "const_int_operand" " i, i")
3759 (reg:SI VL_REGNUM)
3760 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3761 "TARGET_VECTOR"
3762 "vmsbc.vx\t%0,%1,%z2"
3763 [(set_attr "type" "vicalu")
3764 (set_attr "mode" "<MODE>")
3765 (set_attr "vl_op_idx" "3")
3766 (set (attr "avl_type_idx") (const_int 4))
3767 (set_attr "spec_restriction" "thv,none")])
3769 (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
3770 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3771 (unspec:<VM>
3772 [(minus:VI_D
3773 (vec_duplicate:VI_D
3774 (sign_extend:<VEL>
3775 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3776 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3777 (unspec:<VM>
3778 [(match_operand 3 "vector_length_operand" " rK, rK")
3779 (match_operand 4 "const_int_operand" " i, i")
3780 (reg:SI VL_REGNUM)
3781 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3782 "TARGET_VECTOR && !TARGET_64BIT"
3783 "vmsbc.vx\t%0,%1,%z2"
3784 [(set_attr "type" "vicalu")
3785 (set_attr "mode" "<MODE>")
3786 (set_attr "vl_op_idx" "3")
3787 (set (attr "avl_type_idx") (const_int 4))
3788 (set_attr "spec_restriction" "thv,none")])
3790 ;; -------------------------------------------------------------------------------
3791 ;; ---- Predicated integer unary operations
3792 ;; -------------------------------------------------------------------------------
3793 ;; Includes:
3794 ;; - vneg.v/vnot.v
3795 ;; -------------------------------------------------------------------------------
3797 (define_insn "@pred_<optab><mode>"
3798 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
3799 (if_then_else:V_VLSI
3800 (unspec:<VM>
3801 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3802 (match_operand 4 "vector_length_operand" "rK,rK, rK, rK")
3803 (match_operand 5 "const_int_operand" " i, i, i, i")
3804 (match_operand 6 "const_int_operand" " i, i, i, i")
3805 (match_operand 7 "const_int_operand" " i, i, i, i")
3806 (reg:SI VL_REGNUM)
3807 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3808 (any_int_unop:V_VLSI
3809 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr"))
3810 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3811 "TARGET_VECTOR"
3812 "v<insn>.v\t%0,%3%p1"
3813 [(set_attr "type" "vialu")
3814 (set_attr "mode" "<MODE>")
3815 (set_attr "vl_op_idx" "4")
3816 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3817 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3818 (set (attr "avl_type_idx") (const_int 7))])
3820 ;; -------------------------------------------------------------------------------
3821 ;; ---- Predicated integer widening binary operations
3822 ;; -------------------------------------------------------------------------------
3823 ;; Includes:
3824 ;; - 11.2 Vector Widening Integer Add/Subtract
3825 ;; - 11.3 Vector Integer Extension
3826 ;; - 11.12 Vector Widening Integer Multiply Instructions
3827 ;; -------------------------------------------------------------------------------
3829 ;; Vector Double-Widening Sign-extend and Zero-extend.
3830 (define_insn "@pred_<optab><mode>_vf2"
3831 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3832 (if_then_else:VWEXTI
3833 (unspec:<VM>
3834 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3835 (match_operand 4 "vector_length_operand" " rK, rK")
3836 (match_operand 5 "const_int_operand" " i, i")
3837 (match_operand 6 "const_int_operand" " i, i")
3838 (match_operand 7 "const_int_operand" " i, i")
3839 (reg:SI VL_REGNUM)
3840 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3841 (any_extend:VWEXTI
3842 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3843 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3844 "TARGET_VECTOR"
3845 "v<sz>ext.vf2\t%0,%3%p1"
3846 [(set_attr "type" "vext")
3847 (set_attr "mode" "<MODE>")])
3849 ;; Vector Quad-Widening Sign-extend and Zero-extend.
3850 (define_insn "@pred_<optab><mode>_vf4"
3851 [(set (match_operand:VQEXTI 0 "register_operand" "=&vr,&vr")
3852 (if_then_else:VQEXTI
3853 (unspec:<VM>
3854 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3855 (match_operand 4 "vector_length_operand" " rK, rK")
3856 (match_operand 5 "const_int_operand" " i, i")
3857 (match_operand 6 "const_int_operand" " i, i")
3858 (match_operand 7 "const_int_operand" " i, i")
3859 (reg:SI VL_REGNUM)
3860 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3861 (any_extend:VQEXTI
3862 (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " vr, vr"))
3863 (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0")))]
3864 "TARGET_VECTOR"
3865 "v<sz>ext.vf4\t%0,%3%p1"
3866 [(set_attr "type" "vext")
3867 (set_attr "mode" "<MODE>")])
3869 ;; Vector Oct-Widening Sign-extend and Zero-extend.
3870 (define_insn "@pred_<optab><mode>_vf8"
3871 [(set (match_operand:VOEXTI 0 "register_operand" "=&vr,&vr")
3872 (if_then_else:VOEXTI
3873 (unspec:<VM>
3874 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3875 (match_operand 4 "vector_length_operand" " rK, rK")
3876 (match_operand 5 "const_int_operand" " i, i")
3877 (match_operand 6 "const_int_operand" " i, i")
3878 (match_operand 7 "const_int_operand" " i, i")
3879 (reg:SI VL_REGNUM)
3880 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3881 (any_extend:VOEXTI
3882 (match_operand:<V_OCT_TRUNC> 3 "register_operand" " vr, vr"))
3883 (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0")))]
3884 "TARGET_VECTOR"
3885 "v<sz>ext.vf8\t%0,%3%p1"
3886 [(set_attr "type" "vext")
3887 (set_attr "mode" "<MODE>")])
3889 ;; Vector Widening Add/Subtract/Multiply.
3890 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
3891 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3892 (if_then_else:VWEXTI
3893 (unspec:<VM>
3894 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3895 (match_operand 5 "vector_length_operand" " rK, rK")
3896 (match_operand 6 "const_int_operand" " i, i")
3897 (match_operand 7 "const_int_operand" " i, i")
3898 (match_operand 8 "const_int_operand" " i, i")
3899 (reg:SI VL_REGNUM)
3900 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3901 (any_widen_binop:VWEXTI
3902 (any_extend:VWEXTI
3903 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3904 (any_extend:VWEXTI
3905 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3906 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3907 "TARGET_VECTOR"
3908 "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
3909 [(set_attr "type" "vi<widen_binop_insn_type>")
3910 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3912 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
3913 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3914 (if_then_else:VWEXTI
3915 (unspec:<VM>
3916 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3917 (match_operand 5 "vector_length_operand" " rK, rK")
3918 (match_operand 6 "const_int_operand" " i, i")
3919 (match_operand 7 "const_int_operand" " i, i")
3920 (match_operand 8 "const_int_operand" " i, i")
3921 (reg:SI VL_REGNUM)
3922 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3923 (any_widen_binop:VWEXTI
3924 (any_extend:VWEXTI
3925 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3926 (any_extend:VWEXTI
3927 (vec_duplicate:<V_DOUBLE_TRUNC>
3928 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3929 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3930 "TARGET_VECTOR"
3931 "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
3932 [(set_attr "type" "vi<widen_binop_insn_type>")
3933 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3935 (define_insn "@pred_single_widen_sub<any_extend:su><mode>"
3936 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3937 (if_then_else:VWEXTI
3938 (unspec:<VM>
3939 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3940 (match_operand 5 "vector_length_operand" " rK, rK")
3941 (match_operand 6 "const_int_operand" " i, i")
3942 (match_operand 7 "const_int_operand" " i, i")
3943 (match_operand 8 "const_int_operand" " i, i")
3944 (reg:SI VL_REGNUM)
3945 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3946 (minus:VWEXTI
3947 (match_operand:VWEXTI 3 "register_operand" " vr, vr")
3948 (any_extend:VWEXTI
3949 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3950 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3951 "TARGET_VECTOR"
3952 "vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
3953 [(set_attr "type" "viwalu")
3954 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3956 (define_insn "@pred_single_widen_add<any_extend:su><mode>"
3957 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3958 (if_then_else:VWEXTI
3959 (unspec:<VM>
3960 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3961 (match_operand 5 "vector_length_operand" " rK, rK")
3962 (match_operand 6 "const_int_operand" " i, i")
3963 (match_operand 7 "const_int_operand" " i, i")
3964 (match_operand 8 "const_int_operand" " i, i")
3965 (reg:SI VL_REGNUM)
3966 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3967 (plus:VWEXTI
3968 (any_extend:VWEXTI
3969 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
3970 (match_operand:VWEXTI 3 "register_operand" " vr, vr"))
3971 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3972 "TARGET_VECTOR"
3973 "vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
3974 [(set_attr "type" "viwalu")
3975 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3977 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
3978 [(set (match_operand:VWEXTI 0 "register_operand" "=vd,vd, vr, vr")
3979 (if_then_else:VWEXTI
3980 (unspec:<VM>
3981 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
3982 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK")
3983 (match_operand 6 "const_int_operand" " i, i, i, i")
3984 (match_operand 7 "const_int_operand" " i, i, i, i")
3985 (match_operand 8 "const_int_operand" " i, i, i, i")
3986 (reg:SI VL_REGNUM)
3987 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3988 (plus_minus:VWEXTI
3989 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr")
3990 (any_extend:VWEXTI
3991 (vec_duplicate:<V_DOUBLE_TRUNC>
3992 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ,rJ, rJ, rJ"))))
3993 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
3994 "TARGET_VECTOR"
3995 "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
3996 [(set_attr "type" "vi<widen_binop_insn_type>")
3997 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3999 (define_insn "@pred_single_widen_add<any_extend:su><mode>_extended_scalar"
4000 [(set (match_operand:VWEXTI 0 "register_operand" "=vd,vd, vr, vr")
4001 (if_then_else:VWEXTI
4002 (unspec:<VM>
4003 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
4004 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK")
4005 (match_operand 6 "const_int_operand" " i, i, i, i")
4006 (match_operand 7 "const_int_operand" " i, i, i, i")
4007 (match_operand 8 "const_int_operand" " i, i, i, i")
4008 (reg:SI VL_REGNUM)
4009 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4010 (plus:VWEXTI
4011 (vec_duplicate:VWEXTI
4012 (any_extend:<VEL>
4013 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ,rJ, rJ, rJ")))
4014 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr"))
4015 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4016 "TARGET_VECTOR"
4017 "vwadd<any_extend:u>.wx\t%0,%3,%z4%p1"
4018 [(set_attr "type" "viwalu")
4019 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4021 (define_insn "@pred_single_widen_sub<any_extend:su><mode>_extended_scalar"
4022 [(set (match_operand:VWEXTI 0 "register_operand" "=vd,vd, vr, vr")
4023 (if_then_else:VWEXTI
4024 (unspec:<VM>
4025 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1")
4026 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK")
4027 (match_operand 6 "const_int_operand" " i, i, i, i")
4028 (match_operand 7 "const_int_operand" " i, i, i, i")
4029 (match_operand 8 "const_int_operand" " i, i, i, i")
4030 (reg:SI VL_REGNUM)
4031 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4032 (minus:VWEXTI
4033 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr")
4034 (vec_duplicate:VWEXTI
4035 (any_extend:<VEL>
4036 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ,rJ, rJ, rJ"))))
4037 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4038 "TARGET_VECTOR"
4039 "vwsub<any_extend:u>.wx\t%0,%3,%z4%p1"
4040 [(set_attr "type" "viwalu")
4041 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4043 (define_insn "@pred_widen_mulsu<mode>"
4044 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4045 (if_then_else:VWEXTI
4046 (unspec:<VM>
4047 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4048 (match_operand 5 "vector_length_operand" " rK, rK")
4049 (match_operand 6 "const_int_operand" " i, i")
4050 (match_operand 7 "const_int_operand" " i, i")
4051 (match_operand 8 "const_int_operand" " i, i")
4052 (reg:SI VL_REGNUM)
4053 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4054 (mult:VWEXTI
4055 (sign_extend:VWEXTI
4056 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
4057 (zero_extend:VWEXTI
4058 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
4059 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4060 "TARGET_VECTOR"
4061 "vwmulsu.vv\t%0,%3,%4%p1"
4062 [(set_attr "type" "viwmul")
4063 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4065 (define_insn "@pred_widen_mulsu<mode>_scalar"
4066 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4067 (if_then_else:VWEXTI
4068 (unspec:<VM>
4069 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4070 (match_operand 5 "vector_length_operand" " rK, rK")
4071 (match_operand 6 "const_int_operand" " i, i")
4072 (match_operand 7 "const_int_operand" " i, i")
4073 (match_operand 8 "const_int_operand" " i, i")
4074 (reg:SI VL_REGNUM)
4075 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4076 (mult:VWEXTI
4077 (sign_extend:VWEXTI
4078 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
4079 (zero_extend:VWEXTI
4080 (vec_duplicate:<V_DOUBLE_TRUNC>
4081 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
4082 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4083 "TARGET_VECTOR"
4084 "vwmulsu.vx\t%0,%3,%z4%p1"
4085 [(set_attr "type" "viwmul")
4086 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4088 ;; vwcvt<u>.x.x.v
4089 (define_insn "@pred_<optab><mode>"
4090 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
4091 (if_then_else:VWEXTI
4092 (unspec:<VM>
4093 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4094 (match_operand 4 "vector_length_operand" " rK, rK")
4095 (match_operand 5 "const_int_operand" " i, i")
4096 (match_operand 6 "const_int_operand" " i, i")
4097 (match_operand 7 "const_int_operand" " i, i")
4098 (reg:SI VL_REGNUM)
4099 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4100 (plus:VWEXTI
4101 (any_extend:VWEXTI
4102 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
4103 (vec_duplicate:VWEXTI
4104 (reg:<VEL> X0_REGNUM)))
4105 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
4106 "TARGET_VECTOR"
4107 "vwcvt<u>.x.x.v\t%0,%3%p1"
4108 [(set_attr "type" "viwalu")
4109 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4110 (set_attr "vl_op_idx" "4")
4111 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
4112 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4113 (set (attr "avl_type_idx") (const_int 7))])
4115 ;; -------------------------------------------------------------------------------
4116 ;; ---- Predicated integer Narrowing operations
4117 ;; -------------------------------------------------------------------------------
4118 ;; Includes:
4119 ;; - 11.7 Vector Narrowing Integer Right Shift Instructions
4120 ;; -------------------------------------------------------------------------------
4122 ;; The destination EEW is smaller than the source EEW and the overlap is in the
4123 ;; lowest-numbered part of the source register group
4124 ;; e.g, when LMUL = 1, vnsrl.wi v0,v0,3 is legal but a destination of v1 is not.
4125 (define_insn "@pred_narrow_<optab><mode>"
4126 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
4127 (if_then_else:<V_DOUBLE_TRUNC>
4128 (unspec:<VM>
4129 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
4130 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
4131 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4132 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4133 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4134 (reg:SI VL_REGNUM)
4135 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4136 (truncate:<V_DOUBLE_TRUNC>
4137 (any_shiftrt:VWEXTI
4138 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4139 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")))
4140 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4141 "TARGET_VECTOR"
4142 "vn<insn>.w%o4\t%0,%3,%v4%p1"
4143 [(set_attr "type" "vnshift")
4144 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4145 (set_attr "spec_restriction" "none,none,thv,thv,none,thv,none,none,none,thv,none,none")])
4147 (define_insn "@pred_narrow_<optab><mode>_scalar"
4148 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4149 (if_then_else:<V_DOUBLE_TRUNC>
4150 (unspec:<VM>
4151 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4152 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4153 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4154 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4155 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4156 (reg:SI VL_REGNUM)
4157 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4158 (truncate:<V_DOUBLE_TRUNC>
4159 (any_shiftrt:VWEXTI
4160 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4161 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")))
4162 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4163 "TARGET_VECTOR"
4164 "vn<insn>.w%o4\t%0,%3,%4%p1"
4165 [(set_attr "type" "vnshift")
4166 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4167 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
4169 ;; vncvt.x.x.w
4170 (define_insn "@pred_trunc<mode>"
4171 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4172 (if_then_else:<V_DOUBLE_TRUNC>
4173 (unspec:<VM>
4174 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4175 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4176 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
4177 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4178 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4179 (reg:SI VL_REGNUM)
4180 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4181 (truncate:<V_DOUBLE_TRUNC>
4182 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
4183 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4184 "TARGET_VECTOR"
4185 "vncvt.x.x.w\t%0,%3%p1"
4186 [(set_attr "type" "vnshift")
4187 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4188 (set_attr "vl_op_idx" "4")
4189 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
4190 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4191 (set (attr "avl_type_idx") (const_int 7))
4192 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
4194 ;; -------------------------------------------------------------------------------
4195 ;; ---- Predicated fixed-point operations
4196 ;; -------------------------------------------------------------------------------
4197 ;; Includes:
4198 ;; - 12.1 Vector Single-Width Saturating Add and Subtract
4199 ;; - 12.2 Vector Single-Width Aaveraging Add and Subtract
4200 ;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation
4201 ;; - 12.4 Vector Single-Width Scaling Shift Instructions
4202 ;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions
4203 ;; -------------------------------------------------------------------------------
4205 ;; Saturating Add and Subtract
4206 (define_insn "@pred_<optab><mode>"
4207 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr")
4208 (if_then_else:V_VLSI
4209 (unspec:<VM>
4210 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
4211 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4212 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
4213 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4214 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4215 (reg:SI VL_REGNUM)
4216 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4217 (any_sat_int_binop:V_VLSI
4218 (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
4219 (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
4220 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4221 "TARGET_VECTOR"
4222 "@
4223 v<insn>.vv\t%0,%3,%4%p1
4224 v<insn>.vv\t%0,%3,%4%p1
4225 v<insn>.vv\t%0,%3,%4%p1
4226 v<insn>.vv\t%0,%3,%4%p1
4227 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4228 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4229 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4230 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
4231 [(set_attr "type" "<int_binop_insn_type>")
4232 (set_attr "mode" "<MODE>")])
4234 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4235 (define_insn "@pred_<optab><mode>_scalar"
4236 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4237 (if_then_else:VI_QHS
4238 (unspec:<VM>
4239 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4240 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4241 (match_operand 6 "const_int_operand" " i, i, i, i")
4242 (match_operand 7 "const_int_operand" " i, i, i, i")
4243 (match_operand 8 "const_int_operand" " i, i, i, i")
4244 (reg:SI VL_REGNUM)
4245 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4246 (sat_int_plus_binop:VI_QHS
4247 (vec_duplicate:VI_QHS
4248 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4249 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr"))
4250 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4251 "TARGET_VECTOR"
4252 "v<insn>.vx\t%0,%3,%4%p1"
4253 [(set_attr "type" "<int_binop_insn_type>")
4254 (set_attr "mode" "<MODE>")])
4256 (define_insn "@pred_<optab><mode>_scalar"
4257 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4258 (if_then_else:VI_QHS
4259 (unspec:<VM>
4260 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4261 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4262 (match_operand 6 "const_int_operand" " i, i, i, i")
4263 (match_operand 7 "const_int_operand" " i, i, i, i")
4264 (match_operand 8 "const_int_operand" " i, i, i, i")
4265 (reg:SI VL_REGNUM)
4266 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4267 (sat_int_minus_binop:VI_QHS
4268 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4269 (vec_duplicate:VI_QHS
4270 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4271 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4272 "TARGET_VECTOR"
4273 "v<insn>.vx\t%0,%3,%4%p1"
4274 [(set_attr "type" "<int_binop_insn_type>")
4275 (set_attr "mode" "<MODE>")])
4277 (define_expand "@pred_<optab><mode>_scalar"
4278 [(set (match_operand:VI_D 0 "register_operand")
4279 (if_then_else:VI_D
4280 (unspec:<VM>
4281 [(match_operand:<VM> 1 "vector_mask_operand")
4282 (match_operand 5 "vector_length_operand")
4283 (match_operand 6 "const_int_operand")
4284 (match_operand 7 "const_int_operand")
4285 (match_operand 8 "const_int_operand")
4286 (reg:SI VL_REGNUM)
4287 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4288 (sat_int_plus_binop:VI_D
4289 (vec_duplicate:VI_D
4290 (match_operand:<VEL> 4 "reg_or_int_operand"))
4291 (match_operand:VI_D 3 "register_operand"))
4292 (match_operand:VI_D 2 "vector_merge_operand")))]
4293 "TARGET_VECTOR"
4294 {
4295 if (riscv_vector::sew64_scalar_helper (
4296 operands,
4297 /* scalar op */&operands[4],
4298 /* vl */operands[5],
4299 <MODE>mode,
4300 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4301 [] (rtx *operands, rtx boardcast_scalar) {
4302 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4303 operands[2], operands[3], boardcast_scalar, operands[5],
4304 operands[6], operands[7], operands[8]));
4305 },
4306 (riscv_vector::avl_type) INTVAL (operands[8])))
4307 DONE;
4308 })
4310 (define_insn "*pred_<optab><mode>_scalar"
4311 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4312 (if_then_else:VI_D
4313 (unspec:<VM>
4314 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4315 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4316 (match_operand 6 "const_int_operand" " i, i, i, i")
4317 (match_operand 7 "const_int_operand" " i, i, i, i")
4318 (match_operand 8 "const_int_operand" " i, i, i, i")
4319 (reg:SI VL_REGNUM)
4320 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4321 (sat_int_plus_binop:VI_D
4322 (vec_duplicate:VI_D
4323 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4324 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4325 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4326 "TARGET_VECTOR"
4327 "v<insn>.vx\t%0,%3,%4%p1"
4328 [(set_attr "type" "<int_binop_insn_type>")
4329 (set_attr "mode" "<MODE>")])
4331 (define_insn "*pred_<optab><mode>_extended_scalar"
4332 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4333 (if_then_else:VI_D
4334 (unspec:<VM>
4335 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4336 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4337 (match_operand 6 "const_int_operand" " i, i, i, i")
4338 (match_operand 7 "const_int_operand" " i, i, i, i")
4339 (match_operand 8 "const_int_operand" " i, i, i, i")
4340 (reg:SI VL_REGNUM)
4341 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4342 (sat_int_plus_binop:VI_D
4343 (vec_duplicate:VI_D
4344 (sign_extend:<VEL>
4345 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r")))
4346 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4347 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4348 "TARGET_VECTOR && !TARGET_64BIT"
4349 "v<insn>.vx\t%0,%3,%4%p1"
4350 [(set_attr "type" "<int_binop_insn_type>")
4351 (set_attr "mode" "<MODE>")])
4353 (define_expand "@pred_<optab><mode>_scalar"
4354 [(set (match_operand:VI_D 0 "register_operand")
4355 (if_then_else:VI_D
4356 (unspec:<VM>
4357 [(match_operand:<VM> 1 "vector_mask_operand")
4358 (match_operand 5 "vector_length_operand")
4359 (match_operand 6 "const_int_operand")
4360 (match_operand 7 "const_int_operand")
4361 (match_operand 8 "const_int_operand")
4362 (reg:SI VL_REGNUM)
4363 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4364 (sat_int_minus_binop:VI_D
4365 (match_operand:VI_D 3 "register_operand")
4366 (vec_duplicate:VI_D
4367 (match_operand:<VEL> 4 "reg_or_int_operand")))
4368 (match_operand:VI_D 2 "vector_merge_operand")))]
4369 "TARGET_VECTOR"
4370 {
4371 if (riscv_vector::sew64_scalar_helper (
4372 operands,
4373 /* scalar op */&operands[4],
4374 /* vl */operands[5],
4375 <MODE>mode,
4376 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4377 [] (rtx *operands, rtx boardcast_scalar) {
4378 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4379 operands[2], operands[3], boardcast_scalar, operands[5],
4380 operands[6], operands[7], operands[8]));
4381 },
4382 (riscv_vector::avl_type) INTVAL (operands[8])))
4383 DONE;
4384 })
4386 (define_insn "*pred_<optab><mode>_scalar"
4387 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4388 (if_then_else:VI_D
4389 (unspec:<VM>
4390 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4391 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4392 (match_operand 6 "const_int_operand" " i, i, i, i")
4393 (match_operand 7 "const_int_operand" " i, i, i, i")
4394 (match_operand 8 "const_int_operand" " i, i, i, i")
4395 (reg:SI VL_REGNUM)
4396 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4397 (sat_int_minus_binop:VI_D
4398 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4399 (vec_duplicate:VI_D
4400 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4401 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4402 "TARGET_VECTOR"
4403 "v<insn>.vx\t%0,%3,%4%p1"
4404 [(set_attr "type" "<int_binop_insn_type>")
4405 (set_attr "mode" "<MODE>")])
4407 (define_insn "*pred_<optab><mode>_extended_scalar"
4408 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4409 (if_then_else:VI_D
4410 (unspec:<VM>
4411 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4412 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4413 (match_operand 6 "const_int_operand" " i, i, i, i")
4414 (match_operand 7 "const_int_operand" " i, i, i, i")
4415 (match_operand 8 "const_int_operand" " i, i, i, i")
4416 (reg:SI VL_REGNUM)
4417 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4418 (sat_int_minus_binop:VI_D
4419 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4420 (vec_duplicate:VI_D
4421 (sign_extend:<VEL>
4422 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r"))))
4423 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4424 "TARGET_VECTOR && !TARGET_64BIT"
4425 "v<insn>.vx\t%0,%3,%4%p1"
4426 [(set_attr "type" "<int_binop_insn_type>")
4427 (set_attr "mode" "<MODE>")])
4429 (define_insn "@pred_<sat_op><mode>"
4430 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
4431 (if_then_else:V_VLSI
4432 (unspec:<VM>
4433 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4434 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4435 (match_operand 6 "const_int_operand" " i, i, i, i")
4436 (match_operand 7 "const_int_operand" " i, i, i, i")
4437 (match_operand 8 "const_int_operand" " i, i, i, i")
4438 (match_operand 9 "const_int_operand" " i, i, i, i")
4439 (reg:SI VL_REGNUM)
4440 (reg:SI VTYPE_REGNUM)
4441 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4442 (unspec:V_VLSI
4443 [(match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")
4444 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")] VSAT_OP)
4445 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4446 "TARGET_VECTOR"
4447 "v<sat_op>.vv\t%0,%3,%4%p1"
4448 [(set_attr "type" "<sat_insn_type>")
4449 (set_attr "mode" "<MODE>")])
4451 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4452 (define_insn "@pred_<sat_op><mode>_scalar"
4453 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr, vd, vr")
4454 (if_then_else:VI_QHS
4455 (unspec:<VM>
4456 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4457 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4458 (match_operand 6 "const_int_operand" " i, i, i, i")
4459 (match_operand 7 "const_int_operand" " i, i, i, i")
4460 (match_operand 8 "const_int_operand" " i, i, i, i")
4461 (match_operand 9 "const_int_operand" " i, i, i, i")
4462 (reg:SI VL_REGNUM)
4463 (reg:SI VTYPE_REGNUM)
4464 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4465 (unspec:VI_QHS
4466 [(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4467 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4468 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4469 "TARGET_VECTOR"
4470 "v<sat_op>.vx\t%0,%3,%z4%p1"
4471 [(set_attr "type" "<sat_insn_type>")
4472 (set_attr "mode" "<MODE>")])
4474 (define_insn "@pred_<sat_op><mode>_scalar"
4475 [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
4476 (if_then_else:VI
4477 (unspec:<VM>
4478 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4479 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4480 (match_operand 6 "const_int_operand" " i, i, i, i")
4481 (match_operand 7 "const_int_operand" " i, i, i, i")
4482 (match_operand 8 "const_int_operand" " i, i, i, i")
4483 (match_operand 9 "const_int_operand" " i, i, i, i")
4484 (reg:SI VL_REGNUM)
4485 (reg:SI VTYPE_REGNUM)
4486 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4487 (unspec:VI
4488 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4489 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
4490 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4491 "TARGET_VECTOR"
4492 "v<sat_op>.v%o4\t%0,%3,%4%p1"
4493 [(set_attr "type" "<sat_insn_type>")
4494 (set_attr "mode" "<MODE>")])
4496 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4497 ;; we need to deal with SEW = 64 in RV32 system.
4498 (define_expand "@pred_<sat_op><mode>_scalar"
4499 [(set (match_operand:VI_D 0 "register_operand")
4500 (if_then_else:VI_D
4501 (unspec:<VM>
4502 [(match_operand:<VM> 1 "vector_mask_operand")
4503 (match_operand 5 "vector_length_operand")
4504 (match_operand 6 "const_int_operand")
4505 (match_operand 7 "const_int_operand")
4506 (match_operand 8 "const_int_operand")
4507 (match_operand 9 "const_int_operand")
4508 (reg:SI VL_REGNUM)
4509 (reg:SI VTYPE_REGNUM)
4510 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4511 (unspec:VI_D
4512 [(match_operand:VI_D 3 "register_operand")
4513 (match_operand:<VEL> 4 "reg_or_int_operand")] VSAT_ARITH_OP)
4514 (match_operand:VI_D 2 "vector_merge_operand")))]
4515 "TARGET_VECTOR"
4516 {
4517 if (riscv_vector::sew64_scalar_helper (
4518 operands,
4519 /* scalar op */&operands[4],
4520 /* vl */operands[5],
4521 <MODE>mode,
4522 false,
4523 [] (rtx *operands, rtx boardcast_scalar) {
4524 emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
4525 operands[2], operands[3], boardcast_scalar, operands[5],
4526 operands[6], operands[7], operands[8], operands[9]));
4527 },
4528 (riscv_vector::avl_type) INTVAL (operands[8])))
4529 DONE;
4530 })
4532 (define_insn "*pred_<sat_op><mode>_scalar"
4533 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4534 (if_then_else:VI_D
4535 (unspec:<VM>
4536 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4537 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4538 (match_operand 6 "const_int_operand" " i, i, i, i")
4539 (match_operand 7 "const_int_operand" " i, i, i, i")
4540 (match_operand 8 "const_int_operand" " i, i, i, i")
4541 (match_operand 9 "const_int_operand" " i, i, i, i")
4542 (reg:SI VL_REGNUM)
4543 (reg:SI VTYPE_REGNUM)
4544 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4545 (unspec:VI_D
4546 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4547 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4548 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4549 "TARGET_VECTOR"
4550 "v<sat_op>.vx\t%0,%3,%z4%p1"
4551 [(set_attr "type" "<sat_insn_type>")
4552 (set_attr "mode" "<MODE>")])
4554 (define_insn "*pred_<sat_op><mode>_extended_scalar"
4555 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4556 (if_then_else:VI_D
4557 (unspec:<VM>
4558 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4559 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4560 (match_operand 6 "const_int_operand" " i, i, i, i")
4561 (match_operand 7 "const_int_operand" " i, i, i, i")
4562 (match_operand 8 "const_int_operand" " i, i, i, i")
4563 (match_operand 9 "const_int_operand" " i, i, i, i")
4564 (reg:SI VL_REGNUM)
4565 (reg:SI VTYPE_REGNUM)
4566 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4567 (unspec:VI_D
4568 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4569 (sign_extend:<VEL>
4570 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP)
4571 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4572 "TARGET_VECTOR && !TARGET_64BIT"
4573 "v<sat_op>.vx\t%0,%3,%z4%p1"
4574 [(set_attr "type" "<sat_insn_type>")
4575 (set_attr "mode" "<MODE>")])
4577 ;; CLIP
4578 (define_insn "@pred_narrow_clip<v_su><mode>"
4579 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
4580 (if_then_else:<V_DOUBLE_TRUNC>
4581 (unspec:<VM>
4582 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
4583 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
4584 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4585 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4586 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4587 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4588 (reg:SI VL_REGNUM)
4589 (reg:SI VTYPE_REGNUM)
4590 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4591 (unspec:<V_DOUBLE_TRUNC>
4592 [(match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4593 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")] VNCLIP)
4594 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4595 "TARGET_VECTOR"
4596 "vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
4597 [(set_attr "type" "vnclip")
4598 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4599 (set_attr "spec_restriction" "thv,thv,thv,thv,thv,thv,none,none,thv,thv,none,none")])
4601 (define_insn "@pred_narrow_clip<v_su><mode>_scalar"
4602 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4603 (if_then_else:<V_DOUBLE_TRUNC>
4604 (unspec:<VM>
4605 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4606 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4607 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4608 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4609 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4610 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
4611 (reg:SI VL_REGNUM)
4612 (reg:SI VTYPE_REGNUM)
4613 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4614 (unspec:<V_DOUBLE_TRUNC>
4615 [(match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4616 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")] VNCLIP)
4617 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4618 "TARGET_VECTOR"
4619 "vnclip<v_su>.w%o4\t%0,%3,%4%p1"
4620 [(set_attr "type" "vnclip")
4621 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4622 (set_attr "spec_restriction" "thv,thv,thv,thv,none,none")])
4624 ;; -------------------------------------------------------------------------------
4625 ;; ---- Predicated integer comparison operations
4626 ;; -------------------------------------------------------------------------------
4627 ;; Includes:
4628 ;; - 11.8 Vector Integer Comparision Instructions
4629 ;; -------------------------------------------------------------------------------
4631 (define_expand "@pred_cmp<mode>"
4632 [(set (match_operand:<VM> 0 "register_operand")
4633 (if_then_else:<VM>
4634 (unspec:<VM>
4635 [(match_operand:<VM> 1 "vector_mask_operand")
4636 (match_operand 6 "vector_length_operand")
4637 (match_operand 7 "const_int_operand")
4638 (match_operand 8 "const_int_operand")
4639 (reg:SI VL_REGNUM)
4640 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4641 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4642 [(match_operand:V_VLSI 4 "register_operand")
4643 (match_operand:V_VLSI 5 "vector_arith_operand")])
4644 (match_operand:<VM> 2 "vector_merge_operand")))]
4645 "TARGET_VECTOR"
4646 {})
4648 (define_insn "*pred_cmp<mode>_merge_tie_mask"
4649 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4650 (if_then_else:<VM>
4651 (unspec:<VM>
4652 [(match_operand:<VM> 1 "register_operand" " 0")
4653 (match_operand 5 "vector_length_operand" " rK")
4654 (match_operand 6 "const_int_operand" " i")
4655 (match_operand 7 "const_int_operand" " i")
4656 (reg:SI VL_REGNUM)
4657 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4658 (match_operator:<VM> 2 "comparison_except_ltge_operator"
4659 [(match_operand:V_VLSI 3 "register_operand" " vr")
4660 (match_operand:V_VLSI 4 "vector_arith_operand" "vrvi")])
4661 (match_dup 1)))]
4662 "TARGET_VECTOR"
4663 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4664 [(set_attr "type" "vicmp")
4665 (set_attr "mode" "<MODE>")
4666 (set_attr "merge_op_idx" "1")
4667 (set_attr "vl_op_idx" "5")
4668 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4669 (set (attr "avl_type_idx") (const_int 7))])
4671 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4672 (define_insn "*pred_cmp<mode>"
4673 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr")
4674 (if_then_else:<VM>
4675 (unspec:<VM>
4676 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4677 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4678 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4679 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4680 (reg:SI VL_REGNUM)
4681 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4682 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4683 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr")
4684 (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi, vr, vr, vi, vi")])
4685 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4686 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4687 "vms%B3.v%o5\t%0,%4,%v5%p1"
4688 [(set_attr "type" "vicmp")
4689 (set_attr "mode" "<MODE>")
4690 (set_attr "spec_restriction" "thv,thv,thv,thv,rvv,rvv,rvv,rvv")])
4692 ;; We use early-clobber for source LMUL > dest LMUL.
4693 (define_insn "*pred_cmp<mode>_narrow"
4694 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4695 (if_then_else:<VM>
4696 (unspec:<VM>
4697 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4698 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4699 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4700 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4701 (reg:SI VL_REGNUM)
4702 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4703 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4704 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4705 (match_operand:V_VLSI 5 "vector_arith_operand" " vrvi, vrvi, 0, 0, vrvi, 0, 0, vrvi, vrvi")])
4706 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4707 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4708 "vms%B3.v%o5\t%0,%4,%v5%p1"
4709 [(set_attr "type" "vicmp")
4710 (set_attr "mode" "<MODE>")
4711 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
4713 (define_expand "@pred_ltge<mode>"
4714 [(set (match_operand:<VM> 0 "register_operand")
4715 (if_then_else:<VM>
4716 (unspec:<VM>
4717 [(match_operand:<VM> 1 "vector_mask_operand")
4718 (match_operand 6 "vector_length_operand")
4719 (match_operand 7 "const_int_operand")
4720 (match_operand 8 "const_int_operand")
4721 (reg:SI VL_REGNUM)
4722 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4723 (match_operator:<VM> 3 "ltge_operator"
4724 [(match_operand:V_VLSI 4 "register_operand")
4725 (match_operand:V_VLSI 5 "vector_neg_arith_operand")])
4726 (match_operand:<VM> 2 "vector_merge_operand")))]
4727 "TARGET_VECTOR"
4728 {})
4730 (define_insn "*pred_ltge<mode>_merge_tie_mask"
4731 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4732 (if_then_else:<VM>
4733 (unspec:<VM>
4734 [(match_operand:<VM> 1 "register_operand" " 0")
4735 (match_operand 5 "vector_length_operand" " rK")
4736 (match_operand 6 "const_int_operand" " i")
4737 (match_operand 7 "const_int_operand" " i")
4738 (reg:SI VL_REGNUM)
4739 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4740 (match_operator:<VM> 2 "ltge_operator"
4741 [(match_operand:V_VLSI 3 "register_operand" " vr")
4742 (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")])
4743 (match_dup 1)))]
4744 "TARGET_VECTOR"
4745 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4746 [(set_attr "type" "vicmp")
4747 (set_attr "mode" "<MODE>")
4748 (set_attr "merge_op_idx" "1")
4749 (set_attr "vl_op_idx" "5")
4750 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4751 (set (attr "avl_type_idx") (const_int 7))])
4753 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4754 (define_insn "*pred_ltge<mode>"
4755 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr, &vr, &vr, &vr, &vr")
4756 (if_then_else:<VM>
4757 (unspec:<VM>
4758 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4759 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4760 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4761 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4762 (reg:SI VL_REGNUM)
4763 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4764 (match_operator:<VM> 3 "ltge_operator"
4765 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr, vr, vr")
4766 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj, vr, vr, vj, vj")])
4767 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4768 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4769 "vms%B3.v%o5\t%0,%4,%v5%p1"
4770 [(set_attr "type" "vicmp")
4771 (set_attr "mode" "<MODE>")
4772 (set_attr "spec_restriction" "thv,thv,thv,thv,rvv,rvv,rvv,rvv")])
4774 ;; We use early-clobber for source LMUL > dest LMUL.
4775 (define_insn "*pred_ltge<mode>_narrow"
4776 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4777 (if_then_else:<VM>
4778 (unspec:<VM>
4779 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4780 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4781 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4782 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4783 (reg:SI VL_REGNUM)
4784 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4785 (match_operator:<VM> 3 "ltge_operator"
4786 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4787 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vrvj, vrvj, 0, 0, vrvj, 0, 0, vrvj, vrvj")])
4788 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4789 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4790 "vms%B3.v%o5\t%0,%4,%v5%p1"
4791 [(set_attr "type" "vicmp")
4792 (set_attr "mode" "<MODE>")
4793 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
4795 (define_expand "@pred_cmp<mode>_scalar"
4796 [(set (match_operand:<VM> 0 "register_operand")
4797 (if_then_else:<VM>
4798 (unspec:<VM>
4799 [(match_operand:<VM> 1 "vector_mask_operand")
4800 (match_operand 6 "vector_length_operand")
4801 (match_operand 7 "const_int_operand")
4802 (match_operand 8 "const_int_operand")
4803 (reg:SI VL_REGNUM)
4804 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4805 (match_operator:<VM> 3 "comparison_except_ge_operator"
4806 [(match_operand:V_VLSI_QHS 4 "register_operand")
4807 (vec_duplicate:V_VLSI_QHS
4808 (match_operand:<VEL> 5 "register_operand"))])
4809 (match_operand:<VM> 2 "vector_merge_operand")))]
4810 "TARGET_VECTOR"
4811 {})
4813 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4814 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4815 (if_then_else:<VM>
4816 (unspec:<VM>
4817 [(match_operand:<VM> 1 "register_operand" " 0")
4818 (match_operand 5 "vector_length_operand" " rK")
4819 (match_operand 6 "const_int_operand" " i")
4820 (match_operand 7 "const_int_operand" " i")
4821 (reg:SI VL_REGNUM)
4822 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4823 (match_operator:<VM> 2 "comparison_except_ge_operator"
4824 [(match_operand:V_VLSI_QHS 3 "register_operand" " vr")
4825 (vec_duplicate:V_VLSI_QHS
4826 (match_operand:<VEL> 4 "register_operand" " r"))])
4827 (match_dup 1)))]
4828 "TARGET_VECTOR"
4829 "vms%B2.vx\t%0,%3,%4,v0.t"
4830 [(set_attr "type" "vicmp")
4831 (set_attr "mode" "<MODE>")
4832 (set_attr "merge_op_idx" "1")
4833 (set_attr "vl_op_idx" "5")
4834 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4835 (set (attr "avl_type_idx") (const_int 7))])
4837 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4838 (define_insn "*pred_cmp<mode>_scalar"
4839 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
4840 (if_then_else:<VM>
4841 (unspec:<VM>
4842 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4843 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4844 (match_operand 7 "const_int_operand" " i, i, i, i")
4845 (match_operand 8 "const_int_operand" " i, i, i, i")
4846 (reg:SI VL_REGNUM)
4847 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4848 (match_operator:<VM> 3 "comparison_except_ge_operator"
4849 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr, vr, vr")
4850 (vec_duplicate:V_VLSI_QHS
4851 (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
4852 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4853 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4854 "vms%B3.vx\t%0,%4,%5%p1"
4855 [(set_attr "type" "vicmp")
4856 (set_attr "mode" "<MODE>")
4857 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
4859 ;; We use early-clobber for source LMUL > dest LMUL.
4860 (define_insn "*pred_cmp<mode>_scalar_narrow"
4861 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4862 (if_then_else:<VM>
4863 (unspec:<VM>
4864 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4865 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4866 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4867 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4868 (reg:SI VL_REGNUM)
4869 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4870 (match_operator:<VM> 3 "comparison_except_ge_operator"
4871 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")
4872 (vec_duplicate:V_VLSI_QHS
4873 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4874 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4875 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4876 "vms%B3.vx\t%0,%4,%5%p1"
4877 [(set_attr "type" "vicmp")
4878 (set_attr "mode" "<MODE>")
4879 (set_attr "spec_restriction" "none,thv,thv,none,none")])
4881 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4882 ;; we need to deal with SEW = 64 in RV32 system.
4883 (define_expand "@pred_cmp<mode>_scalar"
4884 [(set (match_operand:<VM> 0 "register_operand")
4885 (if_then_else:<VM>
4886 (unspec:<VM>
4887 [(match_operand:<VM> 1 "vector_mask_operand")
4888 (match_operand 6 "vector_length_operand")
4889 (match_operand 7 "const_int_operand")
4890 (match_operand 8 "const_int_operand")
4891 (reg:SI VL_REGNUM)
4892 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4893 (match_operator:<VM> 3 "comparison_except_ge_operator"
4894 [(match_operand:V_VLSI_D 4 "register_operand")
4895 (vec_duplicate:V_VLSI_D
4896 (match_operand:<VEL> 5 "reg_or_int_operand"))])
4897 (match_operand:<VM> 2 "vector_merge_operand")))]
4898 "TARGET_VECTOR"
4899 {
4900 enum rtx_code code = GET_CODE (operands[3]);
4901 if (riscv_vector::sew64_scalar_helper (
4902 operands,
4903 /* scalar op */&operands[5],
4904 /* vl */operands[6],
4905 <MODE>mode,
4906 riscv_vector::has_vi_variant_p (code, operands[5]),
4907 code == LT || code == LTU ?
4908 [] (rtx *operands, rtx boardcast_scalar) {
4909 emit_insn (gen_pred_ltge<mode> (operands[0], operands[1],
4910 operands[2], operands[3], operands[4], boardcast_scalar,
4911 operands[6], operands[7], operands[8]));
4912 }
4913 :
4914 [] (rtx *operands, rtx boardcast_scalar) {
4915 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4916 operands[2], operands[3], operands[4], boardcast_scalar,
4917 operands[6], operands[7], operands[8]));
4918 },
4919 (riscv_vector::avl_type) INTVAL (operands[8])))
4920 DONE;
4921 })
4923 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4924 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4925 (if_then_else:<VM>
4926 (unspec:<VM>
4927 [(match_operand:<VM> 1 "register_operand" " 0")
4928 (match_operand 5 "vector_length_operand" " rK")
4929 (match_operand 6 "const_int_operand" " i")
4930 (match_operand 7 "const_int_operand" " i")
4931 (reg:SI VL_REGNUM)
4932 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4933 (match_operator:<VM> 2 "comparison_except_ge_operator"
4934 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
4935 (vec_duplicate:V_VLSI_D
4936 (match_operand:<VEL> 4 "register_operand" " r"))])
4937 (match_dup 1)))]
4938 "TARGET_VECTOR"
4939 "vms%B2.vx\t%0,%3,%4,v0.t"
4940 [(set_attr "type" "vicmp")
4941 (set_attr "mode" "<MODE>")
4942 (set_attr "merge_op_idx" "1")
4943 (set_attr "vl_op_idx" "5")
4944 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4945 (set (attr "avl_type_idx") (const_int 7))])
4947 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4948 (define_insn "*pred_cmp<mode>_scalar"
4949 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
4950 (if_then_else:<VM>
4951 (unspec:<VM>
4952 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4953 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4954 (match_operand 7 "const_int_operand" " i, i, i, i")
4955 (match_operand 8 "const_int_operand" " i, i, i, i")
4956 (reg:SI VL_REGNUM)
4957 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4958 (match_operator:<VM> 3 "comparison_except_ge_operator"
4959 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
4960 (vec_duplicate:V_VLSI_D
4961 (match_operand:<VEL> 5 "register_operand" " r, r, r, r"))])
4962 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4963 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4964 "vms%B3.vx\t%0,%4,%5%p1"
4965 [(set_attr "type" "vicmp")
4966 (set_attr "mode" "<MODE>")
4967 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
4969 ;; We use early-clobber for source LMUL > dest LMUL.
4970 (define_insn "*pred_cmp<mode>_scalar_narrow"
4971 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4972 (if_then_else:<VM>
4973 (unspec:<VM>
4974 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4975 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4976 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4977 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4978 (reg:SI VL_REGNUM)
4979 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4980 (match_operator:<VM> 3 "comparison_except_ge_operator"
4981 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
4982 (vec_duplicate:V_VLSI_D
4983 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4984 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4985 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4986 "vms%B3.vx\t%0,%4,%5%p1"
4987 [(set_attr "type" "vicmp")
4988 (set_attr "mode" "<MODE>")
4989 (set_attr "spec_restriction" "none,thv,thv,none,none")])
4991 (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
4992 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4993 (if_then_else:<VM>
4994 (unspec:<VM>
4995 [(match_operand:<VM> 1 "register_operand" " 0")
4996 (match_operand 5 "vector_length_operand" " rK")
4997 (match_operand 6 "const_int_operand" " i")
4998 (match_operand 7 "const_int_operand" " i")
4999 (reg:SI VL_REGNUM)
5000 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5001 (match_operator:<VM> 2 "comparison_except_ge_operator"
5002 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
5003 (vec_duplicate:V_VLSI_D
5004 (sign_extend:<VEL>
5005 (match_operand:<VSUBEL> 4 "register_operand" " r")))])
5006 (match_dup 1)))]
5007 "TARGET_VECTOR && !TARGET_64BIT"
5008 "vms%B2.vx\t%0,%3,%4,v0.t"
5009 [(set_attr "type" "vicmp")
5010 (set_attr "mode" "<MODE>")
5011 (set_attr "merge_op_idx" "1")
5012 (set_attr "vl_op_idx" "5")
5013 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5014 (set (attr "avl_type_idx") (const_int 7))])
5016 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5017 (define_insn "*pred_cmp<mode>_extended_scalar"
5018 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
5019 (if_then_else:<VM>
5020 (unspec:<VM>
5021 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
5022 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
5023 (match_operand 7 "const_int_operand" " i, i, i, i")
5024 (match_operand 8 "const_int_operand" " i, i, i, i")
5025 (reg:SI VL_REGNUM)
5026 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5027 (match_operator:<VM> 3 "comparison_except_ge_operator"
5028 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5029 (vec_duplicate:V_VLSI_D
5030 (sign_extend:<VEL>
5031 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r")))])
5032 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
5033 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode) && !TARGET_64BIT"
5034 "vms%B3.vx\t%0,%4,%5%p1"
5035 [(set_attr "type" "vicmp")
5036 (set_attr "mode" "<MODE>")
5037 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
5039 (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
5040 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5041 (if_then_else:<VM>
5042 (unspec:<VM>
5043 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5044 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5045 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5046 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5047 (reg:SI VL_REGNUM)
5048 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5049 (match_operator:<VM> 3 "comparison_except_ge_operator"
5050 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
5051 (vec_duplicate:V_VLSI_D
5052 (sign_extend:<VEL>
5053 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))])
5054 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5055 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode) && !TARGET_64BIT"
5056 "vms%B3.vx\t%0,%4,%5%p1"
5057 [(set_attr "type" "vicmp")
5058 (set_attr "mode" "<MODE>")
5059 (set_attr "spec_restriction" "none,thv,thv,none,none")])
5061 ;; GE, vmsge.vx/vmsgeu.vx
5062 ;;
5063 ;; unmasked va >= x
5064 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x
5065 ;; - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
5066 ;;
5067 ;; masked va >= x, vd != v0
5068 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5069 ;; - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
5070 ;;
5071 ;; masked va >= x, vd == v0
5072 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5073 ;; - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
5074 (define_expand "@pred_ge<mode>_scalar"
5075 [(set (match_operand:<VM> 0 "register_operand")
5076 (if_then_else:<VM>
5077 (unspec:<VM>
5078 [(match_operand:<VM> 1 "vector_mask_operand")
5079 (match_operand 6 "vector_length_operand")
5080 (match_operand 7 "const_int_operand")
5081 (match_operand 8 "const_int_operand")
5082 (reg:SI VL_REGNUM)
5083 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5084 (match_operator:<VM> 3 "ge_operator"
5085 [(match_operand:V_VLSI 4 "register_operand")
5086 (vec_duplicate:V_VLSI
5087 (match_operand:<VEL> 5 "reg_or_int_operand"))])
5088 (match_operand:<VM> 2 "vector_merge_operand")))]
5089 "TARGET_VECTOR"
5090 {
5091 enum rtx_code code = GET_CODE (operands[3]);
5092 rtx undef = RVV_VUNDEF (<VM>mode);
5093 rtx tmp = gen_reg_rtx (<VM>mode);
5094 if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
5095 {
5096 /* If vmsgeu with 0 immediate, expand it to vmset. */
5097 if (satisfies_constraint_Wc1 (operands[1]))
5098 emit_insn (
5099 gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
5100 CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
5101 else
5102 {
5103 /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
5104 */
5105 if (rtx_equal_p (operands[1], operands[2]))
5106 emit_move_insn (operands[0], operands[1]);
5107 else if (register_operand (operands[2], <VM>mode))
5108 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5109 CONSTM1_RTX (<VM>mode), undef, operands[1],
5110 operands[2], operands[6], operands[8]));
5111 else
5112 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5113 CONSTM1_RTX (<VM>mode), undef, operands[1],
5114 operands[1], operands[6], operands[8]));
5115 }
5116 }
5117 else if (riscv_vector::neg_simm5_p (operands[5]))
5118 emit_insn (
5119 gen_pred_ltge<mode> (operands[0], operands[1], operands[2], operands[3],
5120 operands[4],
5121 gen_const_vec_duplicate (<MODE>mode, operands[5]),
5122 operands[6], operands[7], operands[8]));
5123 else
5124 {
5125 if (code == GE)
5126 operands[3] = gen_rtx_fmt_ee (LT, <VM>mode, XEXP (operands[3], 0),
5127 XEXP (operands[3], 1));
5128 else
5129 operands[3] = gen_rtx_fmt_ee (LTU, <VM>mode, XEXP (operands[3], 0),
5130 XEXP (operands[3], 1));
5131 if (GET_MODE_BITSIZE (<VEL>mode) <= GET_MODE_BITSIZE (Pmode))
5132 operands[5] = force_reg (<VEL>mode, operands[5]);
5134 if (satisfies_constraint_Wc1 (operands[1]))
5135 {
5136 /* unmasked va >= x
5137 - pseudoinstruction: vmsge{u}.vx vd, va, x
5138 - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */
5139 emit_insn (
5140 gen_pred_cmp<mode>_scalar (tmp, operands[1], operands[2],
5141 operands[3], operands[4], operands[5],
5142 operands[6], operands[7], operands[8]));
5143 emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
5144 undef, tmp, tmp, operands[6], operands[8]));
5145 }
5146 else
5147 {
5148 if (rtx_equal_p (operands[1], operands[2]))
5149 {
5150 /* masked va >= x, vd == v0
5151 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5152 - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt. */
5153 emit_insn (gen_pred_cmp<mode>_scalar (
5154 tmp, CONSTM1_RTX (<VM>mode), undef, operands[3], operands[4],
5155 operands[5], operands[6], operands[7], operands[8]));
5156 emit_insn (
5157 gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
5158 operands[1], tmp, operands[6], operands[8]));
5159 }
5160 else
5161 {
5162 /* masked va >= x, vd != v0
5163 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5164 - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
5165 */
5166 emit_insn (gen_pred_cmp<mode>_scalar (
5167 tmp, operands[1], operands[2], operands[3], operands[4],
5168 operands[5], operands[6], operands[7], operands[8]));
5169 emit_insn (gen_pred (XOR, <VM>mode, operands[0],
5170 CONSTM1_RTX (<VM>mode), undef, tmp,
5171 operands[1], operands[6], operands[8]));
5172 }
5173 }
5174 }
5175 DONE;
5176 })
5178 ;; -------------------------------------------------------------------------------
5179 ;; ---- Predicated integer ternary operations
5180 ;; -------------------------------------------------------------------------------
5181 ;; Includes:
5182 ;; - 11.13 Vector Single-Width Integer Multiply-Add Instructions
5183 ;; -------------------------------------------------------------------------------
5185 (define_expand "@pred_mul_plus<mode>"
5186 [(set (match_operand:V_VLSI 0 "register_operand")
5187 (if_then_else:V_VLSI
5188 (unspec:<VM>
5189 [(match_operand:<VM> 1 "vector_mask_operand")
5190 (match_operand 6 "vector_length_operand")
5191 (match_operand 7 "const_int_operand")
5192 (match_operand 8 "const_int_operand")
5193 (match_operand 9 "const_int_operand")
5194 (reg:SI VL_REGNUM)
5195 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5196 (plus:V_VLSI
5197 (mult:V_VLSI
5198 (match_operand:V_VLSI 2 "register_operand")
5199 (match_operand:V_VLSI 3 "register_operand"))
5200 (match_operand:V_VLSI 4 "register_operand"))
5201 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5202 "TARGET_VECTOR"
5203 {
5204 riscv_vector::prepare_ternary_operands (operands);
5205 })
5207 (define_insn "*pred_mul_plus<mode>_undef"
5208 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5209 (if_then_else:V_VLSI
5210 (unspec:<VM>
5211 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5212 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5213 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5214 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5215 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5216 (reg:SI VL_REGNUM)
5217 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5218 (plus:V_VLSI
5219 (mult:V_VLSI
5220 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5221 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))
5222 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
5223 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5224 "TARGET_VECTOR"
5225 "@
5226 vmadd.vv\t%0,%4,%5%p1
5227 vmacc.vv\t%0,%3,%4%p1
5228 vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1
5229 vmadd.vv\t%0,%4,%5%p1
5230 vmacc.vv\t%0,%3,%4%p1
5231 vmv%m5r.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1"
5232 [(set_attr "type" "vimuladd")
5233 (set_attr "mode" "<MODE>")])
5235 (define_insn "*pred_madd<mode>"
5236 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5237 (if_then_else:V_VLSI
5238 (unspec:<VM>
5239 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5240 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5241 (match_operand 6 "const_int_operand" " i, i, i, i")
5242 (match_operand 7 "const_int_operand" " i, i, i, i")
5243 (match_operand 8 "const_int_operand" " i, i, i, i")
5244 (reg:SI VL_REGNUM)
5245 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5246 (plus:V_VLSI
5247 (mult:V_VLSI
5248 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5249 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5250 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5251 (match_dup 2)))]
5252 "TARGET_VECTOR"
5253 "@
5254 vmadd.vv\t%0,%3,%4%p1
5255 vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1
5256 vmadd.vv\t%0,%3,%4%p1
5257 vmv%m2r.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1"
5258 [(set_attr "type" "vimuladd")
5259 (set_attr "mode" "<MODE>")
5260 (set_attr "merge_op_idx" "2")
5261 (set_attr "vl_op_idx" "5")
5262 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5263 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5264 (set (attr "avl_type_idx") (const_int 8))])
5266 (define_insn "*pred_macc<mode>"
5267 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5268 (if_then_else:V_VLSI
5269 (unspec:<VM>
5270 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5271 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5272 (match_operand 6 "const_int_operand" " i, i, i, i")
5273 (match_operand 7 "const_int_operand" " i, i, i, i")
5274 (match_operand 8 "const_int_operand" " i, i, i, i")
5275 (reg:SI VL_REGNUM)
5276 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5277 (plus:V_VLSI
5278 (mult:V_VLSI
5279 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5280 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5281 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5282 (match_dup 4)))]
5283 "TARGET_VECTOR"
5284 "@
5285 vmacc.vv\t%0,%2,%3%p1
5286 vmv%m4r.v\t%0,%4;vmacc.vv\t%0,%2,%3%p1
5287 vmacc.vv\t%0,%2,%3%p1
5288 vmv%m4r.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1"
5289 [(set_attr "type" "vimuladd")
5290 (set_attr "mode" "<MODE>")
5291 (set_attr "merge_op_idx" "4")
5292 (set_attr "vl_op_idx" "5")
5293 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5294 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5295 (set (attr "avl_type_idx") (const_int 8))])
5297 (define_expand "@pred_mul_plus<mode>_scalar"
5298 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5299 (if_then_else:V_VLSI_QHS
5300 (unspec:<VM>
5301 [(match_operand:<VM> 1 "vector_mask_operand")
5302 (match_operand 6 "vector_length_operand")
5303 (match_operand 7 "const_int_operand")
5304 (match_operand 8 "const_int_operand")
5305 (match_operand 9 "const_int_operand")
5306 (reg:SI VL_REGNUM)
5307 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5308 (plus:V_VLSI_QHS
5309 (mult:V_VLSI_QHS
5310 (vec_duplicate:V_VLSI_QHS
5311 (match_operand:<VEL> 2 "register_operand"))
5312 (match_operand:V_VLSI_QHS 3 "register_operand"))
5313 (match_operand:V_VLSI_QHS 4 "register_operand"))
5314 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5315 "TARGET_VECTOR"
5316 {})
5318 (define_insn "*pred_madd<mode>_scalar"
5319 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5320 (if_then_else:V_VLSI
5321 (unspec:<VM>
5322 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5323 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5324 (match_operand 6 "const_int_operand" " i, i, i, i")
5325 (match_operand 7 "const_int_operand" " i, i, i, i")
5326 (match_operand 8 "const_int_operand" " i, i, i, i")
5327 (reg:SI VL_REGNUM)
5328 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5329 (plus:V_VLSI
5330 (mult:V_VLSI
5331 (vec_duplicate:V_VLSI
5332 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5333 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))
5334 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5335 (match_dup 3)))]
5336 "TARGET_VECTOR"
5337 "@
5338 vmadd.vx\t%0,%2,%4%p1
5339 vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1
5340 vmadd.vx\t%0,%2,%4%p1
5341 vmv%m3r.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1"
5342 [(set_attr "type" "vimuladd")
5343 (set_attr "mode" "<MODE>")
5344 (set_attr "merge_op_idx" "3")
5345 (set_attr "vl_op_idx" "5")
5346 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5347 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5348 (set (attr "avl_type_idx") (const_int 8))])
5350 (define_insn "*pred_macc<mode>_scalar"
5351 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5352 (if_then_else:V_VLSI
5353 (unspec:<VM>
5354 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5355 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5356 (match_operand 6 "const_int_operand" " i, i, i, i")
5357 (match_operand 7 "const_int_operand" " i, i, i, i")
5358 (match_operand 8 "const_int_operand" " i, i, i, i")
5359 (reg:SI VL_REGNUM)
5360 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5361 (plus:V_VLSI
5362 (mult:V_VLSI
5363 (vec_duplicate:V_VLSI
5364 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5365 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5366 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5367 (match_dup 4)))]
5368 "TARGET_VECTOR"
5369 "@
5370 vmacc.vx\t%0,%2,%3%p1
5371 vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5372 vmacc.vx\t%0,%2,%3%p1
5373 vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5374 [(set_attr "type" "vimuladd")
5375 (set_attr "mode" "<MODE>")
5376 (set_attr "merge_op_idx" "4")
5377 (set_attr "vl_op_idx" "5")
5378 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5379 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5380 (set (attr "avl_type_idx") (const_int 8))])
5382 (define_expand "@pred_mul_plus<mode>_scalar"
5383 [(set (match_operand:V_VLSI_D 0 "register_operand")
5384 (if_then_else:V_VLSI_D
5385 (unspec:<VM>
5386 [(match_operand:<VM> 1 "vector_mask_operand")
5387 (match_operand 6 "vector_length_operand")
5388 (match_operand 7 "const_int_operand")
5389 (match_operand 8 "const_int_operand")
5390 (match_operand 9 "const_int_operand")
5391 (reg:SI VL_REGNUM)
5392 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5393 (plus:V_VLSI_D
5394 (mult:V_VLSI_D
5395 (vec_duplicate:V_VLSI_D
5396 (match_operand:<VEL> 2 "reg_or_int_operand"))
5397 (match_operand:V_VLSI_D 3 "register_operand"))
5398 (match_operand:V_VLSI_D 4 "register_operand"))
5399 (match_operand:V_VLSI_D 5 "register_operand")))]
5400 "TARGET_VECTOR"
5401 {
5402 if (riscv_vector::sew64_scalar_helper (
5403 operands,
5404 /* scalar op */&operands[2],
5405 /* vl */operands[6],
5406 <MODE>mode,
5407 false,
5408 [] (rtx *operands, rtx boardcast_scalar) {
5409 emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
5410 boardcast_scalar, operands[3], operands[4], operands[5],
5411 operands[6], operands[7], operands[8], operands[9]));
5412 },
5413 (riscv_vector::avl_type) INTVAL (operands[9])))
5414 DONE;
5415 })
5417 (define_insn "*pred_madd<mode>_extended_scalar"
5418 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5419 (if_then_else:V_VLSI_D
5420 (unspec:<VM>
5421 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5422 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5423 (match_operand 6 "const_int_operand" " i, i, i, i")
5424 (match_operand 7 "const_int_operand" " i, i, i, i")
5425 (match_operand 8 "const_int_operand" " i, i, i, i")
5426 (reg:SI VL_REGNUM)
5427 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5428 (plus:V_VLSI_D
5429 (mult:V_VLSI_D
5430 (vec_duplicate:V_VLSI_D
5431 (sign_extend:<VEL>
5432 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5433 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))
5434 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr"))
5435 (match_dup 3)))]
5436 "TARGET_VECTOR && !TARGET_64BIT"
5437 "@
5438 vmadd.vx\t%0,%2,%4%p1
5439 vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1
5440 vmadd.vx\t%0,%2,%4%p1
5441 vmv%m2r.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1"
5442 [(set_attr "type" "vimuladd")
5443 (set_attr "mode" "<MODE>")
5444 (set_attr "merge_op_idx" "3")
5445 (set_attr "vl_op_idx" "5")
5446 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5447 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5448 (set (attr "avl_type_idx") (const_int 8))])
5450 (define_insn "*pred_macc<mode>_extended_scalar"
5451 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5452 (if_then_else:V_VLSI_D
5453 (unspec:<VM>
5454 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5455 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5456 (match_operand 6 "const_int_operand" " i, i, i, i")
5457 (match_operand 7 "const_int_operand" " i, i, i, i")
5458 (match_operand 8 "const_int_operand" " i, i, i, i")
5459 (reg:SI VL_REGNUM)
5460 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5461 (plus:V_VLSI_D
5462 (mult:V_VLSI_D
5463 (vec_duplicate:V_VLSI_D
5464 (sign_extend:<VEL>
5465 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5466 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))
5467 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr"))
5468 (match_dup 4)))]
5469 "TARGET_VECTOR && !TARGET_64BIT"
5470 "@
5471 vmacc.vx\t%0,%2,%3%p1
5472 vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5473 vmacc.vx\t%0,%2,%3%p1
5474 vmv%m4r.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5475 [(set_attr "type" "vimuladd")
5476 (set_attr "mode" "<MODE>")
5477 (set_attr "merge_op_idx" "4")
5478 (set_attr "vl_op_idx" "5")
5479 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5480 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5481 (set (attr "avl_type_idx") (const_int 8))])
5483 (define_expand "@pred_minus_mul<mode>"
5484 [(set (match_operand:V_VLSI 0 "register_operand")
5485 (if_then_else:V_VLSI
5486 (unspec:<VM>
5487 [(match_operand:<VM> 1 "vector_mask_operand")
5488 (match_operand 6 "vector_length_operand")
5489 (match_operand 7 "const_int_operand")
5490 (match_operand 8 "const_int_operand")
5491 (match_operand 9 "const_int_operand")
5492 (reg:SI VL_REGNUM)
5493 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5494 (minus:V_VLSI
5495 (match_operand:V_VLSI 4 "register_operand")
5496 (mult:V_VLSI
5497 (match_operand:V_VLSI 2 "register_operand")
5498 (match_operand:V_VLSI 3 "register_operand")))
5499 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5500 "TARGET_VECTOR"
5501 {
5502 riscv_vector::prepare_ternary_operands (operands);
5503 })
5505 (define_insn "*pred_minus_mul<mode>_undef"
5506 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5507 (if_then_else:V_VLSI
5508 (unspec:<VM>
5509 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5510 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5511 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5512 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5513 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5514 (reg:SI VL_REGNUM)
5515 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5516 (minus:V_VLSI
5517 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr")
5518 (mult:V_VLSI
5519 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5520 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr")))
5521 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5522 "TARGET_VECTOR"
5523 "@
5524 vnmsub.vv\t%0,%4,%5%p1
5525 vnmsac.vv\t%0,%3,%4%p1
5526 vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1
5527 vnmsub.vv\t%0,%4,%5%p1
5528 vnmsac.vv\t%0,%3,%4%p1
5529 vmv%m3r.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1"
5530 [(set_attr "type" "vimuladd")
5531 (set_attr "mode" "<MODE>")])
5533 (define_insn "*pred_nmsub<mode>"
5534 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5535 (if_then_else:V_VLSI
5536 (unspec:<VM>
5537 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5538 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5539 (match_operand 6 "const_int_operand" " i, i, i, i")
5540 (match_operand 7 "const_int_operand" " i, i, i, i")
5541 (match_operand 8 "const_int_operand" " i, i, i, i")
5542 (reg:SI VL_REGNUM)
5543 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5544 (minus:V_VLSI
5545 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5546 (mult:V_VLSI
5547 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5548 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5549 (match_dup 2)))]
5550 "TARGET_VECTOR"
5551 "@
5552 vnmsub.vv\t%0,%3,%4%p1
5553 vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1
5554 vnmsub.vv\t%0,%3,%4%p1
5555 vmv%m2r.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1"
5556 [(set_attr "type" "vimuladd")
5557 (set_attr "mode" "<MODE>")
5558 (set_attr "merge_op_idx" "2")
5559 (set_attr "vl_op_idx" "5")
5560 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5561 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5562 (set (attr "avl_type_idx") (const_int 8))])
5564 (define_insn "*pred_nmsac<mode>"
5565 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5566 (if_then_else:V_VLSI
5567 (unspec:<VM>
5568 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5569 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5570 (match_operand 6 "const_int_operand" " i, i, i, i")
5571 (match_operand 7 "const_int_operand" " i, i, i, i")
5572 (match_operand 8 "const_int_operand" " i, i, i, i")
5573 (reg:SI VL_REGNUM)
5574 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5575 (minus:V_VLSI
5576 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5577 (mult:V_VLSI
5578 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5579 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5580 (match_dup 4)))]
5581 "TARGET_VECTOR"
5582 "@
5583 vnmsac.vv\t%0,%2,%3%p1
5584 vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1
5585 vnmsac.vv\t%0,%2,%3%p1
5586 vmv%m4r.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1"
5587 [(set_attr "type" "vimuladd")
5588 (set_attr "mode" "<MODE>")
5589 (set_attr "merge_op_idx" "4")
5590 (set_attr "vl_op_idx" "5")
5591 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5592 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5593 (set (attr "avl_type_idx") (const_int 8))])
5595 (define_expand "@pred_minus_mul<mode>_scalar"
5596 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5597 (if_then_else:V_VLSI_QHS
5598 (unspec:<VM>
5599 [(match_operand:<VM> 1 "vector_mask_operand")
5600 (match_operand 6 "vector_length_operand")
5601 (match_operand 7 "const_int_operand")
5602 (match_operand 8 "const_int_operand")
5603 (match_operand 9 "const_int_operand")
5604 (reg:SI VL_REGNUM)
5605 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5606 (minus:V_VLSI_QHS
5607 (match_operand:V_VLSI_QHS 4 "register_operand")
5608 (mult:V_VLSI_QHS
5609 (vec_duplicate:V_VLSI_QHS
5610 (match_operand:<VEL> 2 "register_operand"))
5611 (match_operand:V_VLSI_QHS 3 "register_operand")))
5612 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5613 "TARGET_VECTOR"
5614 {})
5616 (define_insn "*pred_nmsub<mode>_scalar"
5617 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5618 (if_then_else:V_VLSI
5619 (unspec:<VM>
5620 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5621 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5622 (match_operand 6 "const_int_operand" " i, i, i, i")
5623 (match_operand 7 "const_int_operand" " i, i, i, i")
5624 (match_operand 8 "const_int_operand" " i, i, i, i")
5625 (reg:SI VL_REGNUM)
5626 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5627 (minus:V_VLSI
5628 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5629 (mult:V_VLSI
5630 (vec_duplicate:V_VLSI
5631 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5632 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")))
5633 (match_dup 3)))]
5634 "TARGET_VECTOR"
5635 "@
5636 vnmsub.vx\t%0,%2,%4%p1
5637 vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5638 vnmsub.vx\t%0,%2,%4%p1
5639 vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5640 [(set_attr "type" "vimuladd")
5641 (set_attr "mode" "<MODE>")
5642 (set_attr "merge_op_idx" "3")
5643 (set_attr "vl_op_idx" "5")
5644 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5645 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5646 (set (attr "avl_type_idx") (const_int 8))])
5648 (define_insn "*pred_nmsac<mode>_scalar"
5649 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5650 (if_then_else:V_VLSI
5651 (unspec:<VM>
5652 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5653 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5654 (match_operand 6 "const_int_operand" " i, i, i, i")
5655 (match_operand 7 "const_int_operand" " i, i, i, i")
5656 (match_operand 8 "const_int_operand" " i, i, i, i")
5657 (reg:SI VL_REGNUM)
5658 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5659 (minus:V_VLSI
5660 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5661 (mult:V_VLSI
5662 (vec_duplicate:V_VLSI
5663 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5664 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5665 (match_dup 4)))]
5666 "TARGET_VECTOR"
5667 "@
5668 vnmsac.vx\t%0,%2,%3%p1
5669 vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5670 vnmsac.vx\t%0,%2,%3%p1
5671 vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5672 [(set_attr "type" "vimuladd")
5673 (set_attr "mode" "<MODE>")
5674 (set_attr "merge_op_idx" "4")
5675 (set_attr "vl_op_idx" "5")
5676 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5677 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5678 (set (attr "avl_type_idx") (const_int 8))])
5680 (define_expand "@pred_minus_mul<mode>_scalar"
5681 [(set (match_operand:V_VLSI_D 0 "register_operand")
5682 (if_then_else:V_VLSI_D
5683 (unspec:<VM>
5684 [(match_operand:<VM> 1 "vector_mask_operand")
5685 (match_operand 6 "vector_length_operand")
5686 (match_operand 7 "const_int_operand")
5687 (match_operand 8 "const_int_operand")
5688 (match_operand 9 "const_int_operand")
5689 (reg:SI VL_REGNUM)
5690 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5691 (minus:V_VLSI_D
5692 (match_operand:V_VLSI_D 4 "register_operand")
5693 (mult:V_VLSI_D
5694 (vec_duplicate:V_VLSI_D
5695 (match_operand:<VEL> 2 "reg_or_int_operand"))
5696 (match_operand:V_VLSI_D 3 "register_operand")))
5697 (match_operand:V_VLSI_D 5 "register_operand")))]
5698 "TARGET_VECTOR"
5699 {
5700 if (riscv_vector::sew64_scalar_helper (
5701 operands,
5702 /* scalar op */&operands[2],
5703 /* vl */operands[6],
5704 <MODE>mode,
5705 false,
5706 [] (rtx *operands, rtx boardcast_scalar) {
5707 emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
5708 boardcast_scalar, operands[3], operands[4], operands[5],
5709 operands[6], operands[7], operands[8], operands[9]));
5710 },
5711 (riscv_vector::avl_type) INTVAL (operands[9])))
5712 DONE;
5713 })
5715 (define_insn "*pred_nmsub<mode>_extended_scalar"
5716 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5717 (if_then_else:V_VLSI_D
5718 (unspec:<VM>
5719 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5720 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5721 (match_operand 6 "const_int_operand" " i, i, i, i")
5722 (match_operand 7 "const_int_operand" " i, i, i, i")
5723 (match_operand 8 "const_int_operand" " i, i, i, i")
5724 (reg:SI VL_REGNUM)
5725 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5726 (minus:V_VLSI_D
5727 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5728 (mult:V_VLSI_D
5729 (vec_duplicate:V_VLSI_D
5730 (sign_extend:<VEL>
5731 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5732 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")))
5733 (match_dup 3)))]
5734 "TARGET_VECTOR && !TARGET_64BIT"
5735 "@
5736 vnmsub.vx\t%0,%2,%4%p1
5737 vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5738 vnmsub.vx\t%0,%2,%4%p1
5739 vmv%m3r.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5740 [(set_attr "type" "vimuladd")
5741 (set_attr "mode" "<MODE>")
5742 (set_attr "merge_op_idx" "3")
5743 (set_attr "vl_op_idx" "5")
5744 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5745 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5746 (set (attr "avl_type_idx") (const_int 8))])
5748 (define_insn "*pred_nmsac<mode>_extended_scalar"
5749 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5750 (if_then_else:V_VLSI_D
5751 (unspec:<VM>
5752 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5753 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5754 (match_operand 6 "const_int_operand" " i, i, i, i")
5755 (match_operand 7 "const_int_operand" " i, i, i, i")
5756 (match_operand 8 "const_int_operand" " i, i, i, i")
5757 (reg:SI VL_REGNUM)
5758 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5759 (minus:V_VLSI_D
5760 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")
5761 (mult:V_VLSI_D
5762 (vec_duplicate:V_VLSI_D
5763 (sign_extend:<VEL>
5764 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5765 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")))
5766 (match_dup 4)))]
5767 "TARGET_VECTOR && !TARGET_64BIT"
5768 "@
5769 vnmsac.vx\t%0,%2,%3%p1
5770 vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5771 vnmsac.vx\t%0,%2,%3%p1
5772 vmv%m4r.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5773 [(set_attr "type" "vimuladd")
5774 (set_attr "mode" "<MODE>")
5775 (set_attr "merge_op_idx" "4")
5776 (set_attr "vl_op_idx" "5")
5777 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5778 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5779 (set (attr "avl_type_idx") (const_int 8))])
5781 ;; -------------------------------------------------------------------------------
5782 ;; ---- Predicated widen integer ternary operations
5783 ;; -------------------------------------------------------------------------------
5784 ;; Includes:
5785 ;; - 11.14 Vector Widening Integer Multiply-Add Instructions
5786 ;; -------------------------------------------------------------------------------
5788 (define_insn "@pred_widen_mul_plus<su><mode>"
5789 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5790 (if_then_else:VWEXTI
5791 (unspec:<VM>
5792 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5793 (match_operand 5 "vector_length_operand" " rK")
5794 (match_operand 6 "const_int_operand" " i")
5795 (match_operand 7 "const_int_operand" " i")
5796 (match_operand 8 "const_int_operand" " i")
5797 (reg:SI VL_REGNUM)
5798 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5799 (plus:VWEXTI
5800 (mult:VWEXTI
5801 (any_extend:VWEXTI
5802 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5803 (any_extend:VWEXTI
5804 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5805 (match_operand:VWEXTI 2 "register_operand" " 0"))
5806 (match_dup 2)))]
5807 "TARGET_VECTOR"
5808 "vwmacc<u>.vv\t%0,%3,%4%p1"
5809 [(set_attr "type" "viwmuladd")
5810 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5812 (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
5813 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5814 (if_then_else:VWEXTI
5815 (unspec:<VM>
5816 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5817 (match_operand 5 "vector_length_operand" " rK")
5818 (match_operand 6 "const_int_operand" " i")
5819 (match_operand 7 "const_int_operand" " i")
5820 (match_operand 8 "const_int_operand" " i")
5821 (reg:SI VL_REGNUM)
5822 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5823 (plus:VWEXTI
5824 (mult:VWEXTI
5825 (any_extend:VWEXTI
5826 (vec_duplicate:<V_DOUBLE_TRUNC>
5827 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5828 (any_extend:VWEXTI
5829 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5830 (match_operand:VWEXTI 2 "register_operand" " 0"))
5831 (match_dup 2)))]
5832 "TARGET_VECTOR"
5833 "vwmacc<u>.vx\t%0,%3,%4%p1"
5834 [(set_attr "type" "viwmuladd")
5835 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5837 (define_insn "@pred_widen_mul_plussu<mode>"
5838 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5839 (if_then_else:VWEXTI
5840 (unspec:<VM>
5841 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5842 (match_operand 5 "vector_length_operand" " rK")
5843 (match_operand 6 "const_int_operand" " i")
5844 (match_operand 7 "const_int_operand" " i")
5845 (match_operand 8 "const_int_operand" " i")
5846 (reg:SI VL_REGNUM)
5847 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5848 (plus:VWEXTI
5849 (mult:VWEXTI
5850 (sign_extend:VWEXTI
5851 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5852 (zero_extend:VWEXTI
5853 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5854 (match_operand:VWEXTI 2 "register_operand" " 0"))
5855 (match_dup 2)))]
5856 "TARGET_VECTOR"
5857 "vwmaccsu.vv\t%0,%3,%4%p1"
5858 [(set_attr "type" "viwmuladd")
5859 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5861 (define_insn "@pred_widen_mul_plussu<mode>_scalar"
5862 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5863 (if_then_else:VWEXTI
5864 (unspec:<VM>
5865 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5866 (match_operand 5 "vector_length_operand" " rK")
5867 (match_operand 6 "const_int_operand" " i")
5868 (match_operand 7 "const_int_operand" " i")
5869 (match_operand 8 "const_int_operand" " i")
5870 (reg:SI VL_REGNUM)
5871 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5872 (plus:VWEXTI
5873 (mult:VWEXTI
5874 (sign_extend:VWEXTI
5875 (vec_duplicate:<V_DOUBLE_TRUNC>
5876 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5877 (zero_extend:VWEXTI
5878 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5879 (match_operand:VWEXTI 2 "register_operand" " 0"))
5880 (match_dup 2)))]
5881 "TARGET_VECTOR"
5882 "vwmaccsu.vx\t%0,%3,%4%p1"
5883 [(set_attr "type" "viwmuladd")
5884 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5886 (define_insn "@pred_widen_mul_plusus<mode>_scalar"
5887 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5888 (if_then_else:VWEXTI
5889 (unspec:<VM>
5890 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5891 (match_operand 5 "vector_length_operand" " rK")
5892 (match_operand 6 "const_int_operand" " i")
5893 (match_operand 7 "const_int_operand" " i")
5894 (match_operand 8 "const_int_operand" " i")
5895 (reg:SI VL_REGNUM)
5896 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5897 (plus:VWEXTI
5898 (mult:VWEXTI
5899 (zero_extend:VWEXTI
5900 (vec_duplicate:<V_DOUBLE_TRUNC>
5901 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5902 (sign_extend:VWEXTI
5903 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5904 (match_operand:VWEXTI 2 "register_operand" " 0"))
5905 (match_dup 2)))]
5906 "TARGET_VECTOR"
5907 "vwmaccus.vx\t%0,%3,%4%p1"
5908 [(set_attr "type" "viwmuladd")
5909 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5911 ;; -------------------------------------------------------------------------------
5912 ;; ---- Predicated BOOL mask operations
5913 ;; -------------------------------------------------------------------------------
5914 ;; Includes:
5915 ;; - 15.1 Vector Mask-Register Logical Instructions
5916 ;; - 15.2 Vector count population in mask vcpop.m
5917 ;; - 15.3 vfirst find-first-set mask bit
5918 ;; - 15.4 vmsbf.m set-before-first mask bit
5919 ;; - 15.5 vmsif.m set-including-first mask bit
5920 ;; - 15.6 vmsof.m set-only-first mask bit
5921 ;; - 15.8 Vector Iota Instruction
5922 ;; - 15.9 Vector Element Index Instruction
5923 ;; -------------------------------------------------------------------------------
5925 ;; We keep this pattern same as pred_mov so that we can gain more optimizations.
5926 ;; For example, if we have vmxor.mm v1,v1,v1. It will be optmized as vmclr.m which
5927 ;; is generated by pred_mov.
5928 (define_insn "@pred_<optab><mode>"
5929 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5930 (if_then_else:VB_VLS
5931 (unspec:VB_VLS
5932 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
5933 (match_operand 5 "vector_length_operand" " rK")
5934 (match_operand 6 "const_int_operand" " i")
5935 (reg:SI VL_REGNUM)
5936 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5937 (any_bitwise:VB_VLS
5938 (match_operand:VB_VLS 3 "register_operand" " vr")
5939 (match_operand:VB_VLS 4 "register_operand" " vr"))
5940 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
5941 "TARGET_VECTOR"
5942 "vm<insn>.mm\t%0,%3,%4"
5943 [(set_attr "type" "vmalu")
5944 (set_attr "mode" "<MODE>")
5945 (set_attr "vl_op_idx" "5")
5946 (set (attr "avl_type_idx") (const_int 6))])
5948 (define_insn "@pred_n<optab><mode>"
5949 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5950 (if_then_else:VB_VLS
5951 (unspec:VB_VLS
5952 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
5953 (match_operand 5 "vector_length_operand" " rK")
5954 (match_operand 6 "const_int_operand" " i")
5955 (reg:SI VL_REGNUM)
5956 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5957 (not:VB_VLS
5958 (any_bitwise:VB_VLS
5959 (match_operand:VB_VLS 3 "register_operand" " vr")
5960 (match_operand:VB_VLS 4 "register_operand" " vr")))
5961 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
5962 "TARGET_VECTOR"
5963 "vm<ninsn>.mm\t%0,%3,%4"
5964 [(set_attr "type" "vmalu")
5965 (set_attr "mode" "<MODE>")
5966 (set_attr "vl_op_idx" "5")
5967 (set (attr "avl_type_idx") (const_int 6))])
5969 (define_insn "@pred_<optab>not<mode>"
5970 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5971 (if_then_else:VB_VLS
5972 (unspec:VB_VLS
5973 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
5974 (match_operand 5 "vector_length_operand" " rK")
5975 (match_operand 6 "const_int_operand" " i")
5976 (reg:SI VL_REGNUM)
5977 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5978 (and_ior:VB_VLS
5979 (match_operand:VB_VLS 3 "register_operand" " vr")
5980 (not:VB_VLS
5981 (match_operand:VB_VLS 4 "register_operand" " vr")))
5982 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
5983 "TARGET_VECTOR"
5984 "vm<insn>n.mm\t%0,%3,%4"
5985 [(set_attr "type" "vmalu")
5986 (set_attr "mode" "<MODE>")
5987 (set_attr "vl_op_idx" "5")
5988 (set (attr "avl_type_idx") (const_int 6))])
5990 (define_insn "@pred_not<mode>"
5991 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5992 (if_then_else:VB_VLS
5993 (unspec:VB_VLS
5994 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
5995 (match_operand 4 "vector_length_operand" " rK")
5996 (match_operand 5 "const_int_operand" " i")
5997 (reg:SI VL_REGNUM)
5998 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5999 (not:VB_VLS
6000 (match_operand:VB_VLS 3 "register_operand" " vr"))
6001 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6002 "TARGET_VECTOR"
6003 "vmnot.m\t%0,%3"
6004 [(set_attr "type" "vmalu")
6005 (set_attr "mode" "<MODE>")
6006 (set_attr "vl_op_idx" "4")
6007 (set (attr "avl_type_idx") (const_int 5))])
6009 (define_insn "@pred_popcount<VB_VLS:mode><P:mode>"
6010 [(set (match_operand:P 0 "register_operand" "=r")
6011 (popcount:P
6012 (unspec:VB_VLS
6013 [(and:VB_VLS
6014 (match_operand:VB_VLS 1 "vector_mask_operand" "vmWc1")
6015 (match_operand:VB_VLS 2 "register_operand" " vr"))
6016 (match_operand 3 "vector_length_operand" " rK")
6017 (match_operand 4 "const_int_operand" " i")
6018 (reg:SI VL_REGNUM)
6019 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
6020 "TARGET_VECTOR"
6021 "vcpop.m\t%0,%2%p1"
6022 [(set_attr "type" "vmpop")
6023 (set_attr "mode" "<VB_VLS:MODE>")])
6025 (define_insn "@pred_ffs<VB:mode><P:mode>"
6026 [(set (match_operand:P 0 "register_operand" "=r")
6027 (plus:P
6028 (ffs:P
6029 (unspec:VB
6030 [(and:VB
6031 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6032 (match_operand:VB 2 "register_operand" " vr"))
6033 (match_operand 3 "vector_length_operand" " rK")
6034 (match_operand 4 "const_int_operand" " i")
6035 (reg:SI VL_REGNUM)
6036 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))
6037 (const_int -1)))]
6038 "TARGET_VECTOR"
6039 "vfirst.m\t%0,%2%p1"
6040 [(set_attr "type" "vmffs")
6041 (set_attr "mode" "<VB:MODE>")])
6043 (define_insn "@pred_<misc_op><mode>"
6044 [(set (match_operand:VB 0 "register_operand" "=&vr, &vr")
6045 (if_then_else:VB
6046 (unspec:VB
6047 [(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
6048 (match_operand 4 "vector_length_operand" " rK, rK")
6049 (match_operand 5 "const_int_operand" " i, i")
6050 (match_operand 6 "const_int_operand" " i, i")
6051 (reg:SI VL_REGNUM)
6052 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6053 (unspec:VB
6054 [(match_operand:VB 3 "register_operand" " vr, vr")] VMISC)
6055 (match_operand:VB 2 "vector_merge_operand" " vu, 0")))]
6056 "TARGET_VECTOR"
6057 "vm<misc_op>.m\t%0,%3%p1"
6058 [(set_attr "type" "vmsfs")
6059 (set_attr "mode" "<MODE>")])
6061 (define_insn "@pred_iota<mode>"
6062 [(set (match_operand:VI 0 "register_operand" "=&vr, &vr")
6063 (if_then_else:VI
6064 (unspec:<VM>
6065 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
6066 (match_operand 4 "vector_length_operand" " rK, rK")
6067 (match_operand 5 "const_int_operand" " i, i")
6068 (match_operand 6 "const_int_operand" " i, i")
6069 (match_operand 7 "const_int_operand" " i, i")
6070 (reg:SI VL_REGNUM)
6071 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6072 (unspec:VI
6073 [(match_operand:<VM> 3 "register_operand" " vr, vr")] UNSPEC_VIOTA)
6074 (match_operand:VI 2 "vector_merge_operand" " vu, 0")))]
6075 "TARGET_VECTOR"
6076 "viota.m\t%0,%3%p1"
6077 [(set_attr "type" "vmiota")
6078 (set_attr "mode" "<MODE>")])
6080 (define_insn "@pred_series<mode>"
6081 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
6082 (if_then_else:V_VLSI
6083 (unspec:<VM>
6084 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6085 (match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
6086 (match_operand 4 "const_int_operand" " i, i, i, i")
6087 (match_operand 5 "const_int_operand" " i, i, i, i")
6088 (match_operand 6 "const_int_operand" " i, i, i, i")
6089 (reg:SI VL_REGNUM)
6090 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6091 (vec_series:V_VLSI (const_int 0) (const_int 1))
6092 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6093 "TARGET_VECTOR"
6094 "vid.v\t%0%p1"
6095 [(set_attr "type" "vmidx")
6096 (set_attr "mode" "<MODE>")])
6098 ;; -------------------------------------------------------------------------------
6099 ;; ---- Predicated floating-point binary operations
6100 ;; -------------------------------------------------------------------------------
6101 ;; Includes:
6102 ;; - 13.2 Vector Single-Width Floating-Point Add/Subtract Instructions
6103 ;; - 13.4 Vector Single-Width Floating-Point Multiply/Divide Instructions
6104 ;; - 13.11 Vector Floating-Point MIN/MAX Instructions
6105 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions
6106 ;; -------------------------------------------------------------------------------
6108 (define_insn "@pred_<optab><mode>"
6109 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6110 (if_then_else:V_VLSF
6111 (unspec:<VM>
6112 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6113 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6114 (match_operand 6 "const_int_operand" " i, i, i, i")
6115 (match_operand 7 "const_int_operand" " i, i, i, i")
6116 (match_operand 8 "const_int_operand" " i, i, i, i")
6117 (match_operand 9 "const_int_operand" " i, i, i, i")
6118 (reg:SI VL_REGNUM)
6119 (reg:SI VTYPE_REGNUM)
6120 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6121 (any_float_binop:V_VLSF
6122 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6123 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6124 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6125 "TARGET_VECTOR"
6126 "vf<insn>.vv\t%0,%3,%4%p1"
6127 [(set_attr "type" "<float_insn_type>")
6128 (set_attr "mode" "<MODE>")
6129 (set (attr "frm_mode")
6130 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6132 (define_insn "@pred_<optab><mode>"
6133 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6134 (if_then_else:V_VLSF
6135 (unspec:<VM>
6136 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6137 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6138 (match_operand 6 "const_int_operand" " i, i, i, i")
6139 (match_operand 7 "const_int_operand" " i, i, i, i")
6140 (match_operand 8 "const_int_operand" " i, i, i, i")
6141 (reg:SI VL_REGNUM)
6142 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6143 (any_float_binop_nofrm:V_VLSF
6144 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6145 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6146 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6147 "TARGET_VECTOR"
6148 "vf<insn>.vv\t%0,%3,%4%p1"
6149 [(set_attr "type" "<float_insn_type>")
6150 (set_attr "mode" "<MODE>")])
6152 (define_insn "@pred_<ieee_fmaxmin_op><mode>"
6153 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6154 (if_then_else:V_VLSF
6155 (unspec:<VM>
6156 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6157 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6158 (match_operand 6 "const_int_operand" " i, i, i, i")
6159 (match_operand 7 "const_int_operand" " i, i, i, i")
6160 (match_operand 8 "const_int_operand" " i, i, i, i")
6161 (reg:SI VL_REGNUM)
6162 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6163 (unspec:V_VLSF
6164 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6165 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]
6166 UNSPEC_VFMAXMIN)
6167 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6168 "TARGET_VECTOR"
6169 "v<ieee_fmaxmin_op>.vv\t%0,%3,%4%p1"
6170 [(set_attr "type" "vfminmax")
6171 (set_attr "mode" "<MODE>")])
6173 (define_insn "@pred_<optab><mode>_scalar"
6174 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6175 (if_then_else:VF
6176 (unspec:<VM>
6177 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6178 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6179 (match_operand 6 "const_int_operand" " i, i, i, i")
6180 (match_operand 7 "const_int_operand" " i, i, i, i")
6181 (match_operand 8 "const_int_operand" " i, i, i, i")
6182 (match_operand 9 "const_int_operand" " i, i, i, i")
6183 (reg:SI VL_REGNUM)
6184 (reg:SI VTYPE_REGNUM)
6185 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6186 (commutative_float_binop:VF
6187 (vec_duplicate:VF
6188 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6189 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6190 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6191 "TARGET_VECTOR"
6192 "vf<insn>.vf\t%0,%3,%4%p1"
6193 [(set_attr "type" "<float_insn_type>")
6194 (set_attr "mode" "<MODE>")
6195 (set (attr "frm_mode")
6196 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6198 (define_insn "@pred_<optab><mode>_scalar"
6199 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6200 (if_then_else:VF
6201 (unspec:<VM>
6202 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6203 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6204 (match_operand 6 "const_int_operand" " i, i, i, i")
6205 (match_operand 7 "const_int_operand" " i, i, i, i")
6206 (match_operand 8 "const_int_operand" " i, i, i, i")
6207 (reg:SI VL_REGNUM)
6208 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6209 (commutative_float_binop_nofrm:VF
6210 (vec_duplicate:VF
6211 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6212 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6213 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6214 "TARGET_VECTOR"
6215 "vf<insn>.vf\t%0,%3,%4%p1"
6216 [(set_attr "type" "<float_insn_type>")
6217 (set_attr "mode" "<MODE>")])
6219 (define_insn "@pred_<ieee_fmaxmin_op><mode>_scalar"
6220 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6221 (if_then_else:VF
6222 (unspec:<VM>
6223 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6224 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6225 (match_operand 6 "const_int_operand" " i, i, i, i")
6226 (match_operand 7 "const_int_operand" " i, i, i, i")
6227 (match_operand 8 "const_int_operand" " i, i, i, i")
6228 (reg:SI VL_REGNUM)
6229 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6230 (unspec:VF
6231 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6232 (vec_duplicate:VF
6233 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))]
6234 UNSPEC_VFMAXMIN)
6235 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6236 "TARGET_VECTOR"
6237 "v<ieee_fmaxmin_op>.vf\t%0,%3,%4%p1"
6238 [(set_attr "type" "vfminmax")
6239 (set_attr "mode" "<MODE>")])
6241 (define_insn "@pred_<optab><mode>_scalar"
6242 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6243 (if_then_else:VF
6244 (unspec:<VM>
6245 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6246 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6247 (match_operand 6 "const_int_operand" " i, i, i, i")
6248 (match_operand 7 "const_int_operand" " i, i, i, i")
6249 (match_operand 8 "const_int_operand" " i, i, i, i")
6250 (match_operand 9 "const_int_operand" " i, i, i, i")
6251 (reg:SI VL_REGNUM)
6252 (reg:SI VTYPE_REGNUM)
6253 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6254 (non_commutative_float_binop:VF
6255 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6256 (vec_duplicate:VF
6257 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
6258 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6259 "TARGET_VECTOR"
6260 "vf<insn>.vf\t%0,%3,%4%p1"
6261 [(set_attr "type" "<float_insn_type>")
6262 (set_attr "mode" "<MODE>")
6263 (set (attr "frm_mode")
6264 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6266 (define_insn "@pred_<optab><mode>_reverse_scalar"
6267 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6268 (if_then_else:VF
6269 (unspec:<VM>
6270 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6271 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6272 (match_operand 6 "const_int_operand" " i, i, i, i")
6273 (match_operand 7 "const_int_operand" " i, i, i, i")
6274 (match_operand 8 "const_int_operand" " i, i, i, i")
6275 (match_operand 9 "const_int_operand" " i, i, i, i")
6276 (reg:SI VL_REGNUM)
6277 (reg:SI VTYPE_REGNUM)
6278 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6279 (non_commutative_float_binop:VF
6280 (vec_duplicate:VF
6281 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6282 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6283 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6284 "TARGET_VECTOR"
6285 "vfr<insn>.vf\t%0,%3,%4%p1"
6286 [(set_attr "type" "<float_insn_type>")
6287 (set_attr "mode" "<MODE>")
6288 (set (attr "frm_mode")
6289 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6291 (define_insn "@pred_<copysign><mode>"
6292 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6293 (if_then_else:V_VLSF
6294 (unspec:<VM>
6295 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6296 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6297 (match_operand 6 "const_int_operand" " i, i, i, i")
6298 (match_operand 7 "const_int_operand" " i, i, i, i")
6299 (match_operand 8 "const_int_operand" " i, i, i, i")
6300 (reg:SI VL_REGNUM)
6301 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6302 (unspec:V_VLSF
6303 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6304 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
6305 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6306 "TARGET_VECTOR"
6307 "vfsgnj<nx>.vv\t%0,%3,%4%p1"
6308 [(set_attr "type" "vfsgnj")
6309 (set_attr "mode" "<MODE>")])
6311 (define_insn "@pred_ncopysign<mode>"
6312 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6313 (if_then_else:VF
6314 (unspec:<VM>
6315 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6316 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6317 (match_operand 6 "const_int_operand" " i, i, i, i")
6318 (match_operand 7 "const_int_operand" " i, i, i, i")
6319 (match_operand 8 "const_int_operand" " i, i, i, i")
6320 (reg:SI VL_REGNUM)
6321 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6322 (neg:VF
6323 (unspec:VF
6324 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6325 (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))
6326 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6327 "TARGET_VECTOR"
6328 "vfsgnjn.vv\t%0,%3,%4%p1"
6329 [(set_attr "type" "vfsgnj")
6330 (set_attr "mode" "<MODE>")])
6332 (define_insn "@pred_<copysign><mode>_scalar"
6333 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6334 (if_then_else:V_VLSF
6335 (unspec:<VM>
6336 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6337 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6338 (match_operand 6 "const_int_operand" " i, i, i, i")
6339 (match_operand 7 "const_int_operand" " i, i, i, i")
6340 (match_operand 8 "const_int_operand" " i, i, i, i")
6341 (reg:SI VL_REGNUM)
6342 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6343 (unspec:V_VLSF
6344 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6345 (vec_duplicate:V_VLSF
6346 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
6347 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6348 "TARGET_VECTOR"
6349 "vfsgnj<nx>.vf\t%0,%3,%4%p1"
6350 [(set_attr "type" "vfsgnj")
6351 (set_attr "mode" "<MODE>")])
6353 (define_insn "@pred_ncopysign<mode>_scalar"
6354 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6355 (if_then_else:VF
6356 (unspec:<VM>
6357 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6358 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6359 (match_operand 6 "const_int_operand" " i, i, i, i")
6360 (match_operand 7 "const_int_operand" " i, i, i, i")
6361 (match_operand 8 "const_int_operand" " i, i, i, i")
6362 (reg:SI VL_REGNUM)
6363 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6364 (neg:VF
6365 (unspec:VF
6366 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6367 (vec_duplicate:VF
6368 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] UNSPEC_VCOPYSIGN))
6369 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6370 "TARGET_VECTOR"
6371 "vfsgnjn.vf\t%0,%3,%4%p1"
6372 [(set_attr "type" "vfsgnj")
6373 (set_attr "mode" "<MODE>")])
6375 ;; -------------------------------------------------------------------------------
6376 ;; ---- Predicated floating-point ternary operations
6377 ;; -------------------------------------------------------------------------------
6378 ;; Includes:
6379 ;; - 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions
6380 ;; -------------------------------------------------------------------------------
6382 (define_expand "@pred_mul_<optab><mode>"
6383 [(set (match_operand:V_VLSF 0 "register_operand")
6384 (if_then_else:V_VLSF
6385 (unspec:<VM>
6386 [(match_operand:<VM> 1 "vector_mask_operand")
6387 (match_operand 6 "vector_length_operand")
6388 (match_operand 7 "const_int_operand")
6389 (match_operand 8 "const_int_operand")
6390 (match_operand 9 "const_int_operand")
6391 (match_operand 10 "const_int_operand")
6392 (reg:SI VL_REGNUM)
6393 (reg:SI VTYPE_REGNUM)
6394 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6395 (plus_minus:V_VLSF
6396 (mult:V_VLSF
6397 (match_operand:V_VLSF 2 "register_operand")
6398 (match_operand:V_VLSF 3 "register_operand"))
6399 (match_operand:V_VLSF 4 "register_operand"))
6400 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6401 "TARGET_VECTOR"
6402 {
6403 riscv_vector::prepare_ternary_operands (operands);
6404 })
6406 (define_insn "*pred_mul_<optab><mode>_undef"
6407 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6408 (if_then_else:V_VLSF
6409 (unspec:<VM>
6410 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6411 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6412 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6413 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6414 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6415 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6416 (reg:SI VL_REGNUM)
6417 (reg:SI VTYPE_REGNUM)
6418 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6419 (plus_minus:V_VLSF
6420 (mult:V_VLSF
6421 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6422 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr"))
6423 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6424 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6425 "TARGET_VECTOR"
6426 "@
6427 vf<madd_msub>.vv\t%0,%4,%5%p1
6428 vf<macc_msac>.vv\t%0,%3,%4%p1
6429 vmv%m3r.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1
6430 vf<madd_msub>.vv\t%0,%4,%5%p1
6431 vf<macc_msac>.vv\t%0,%3,%4%p1
6432 vmv%m3r.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1"
6433 [(set_attr "type" "vfmuladd")
6434 (set_attr "mode" "<MODE>")
6435 (set (attr "frm_mode")
6436 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6438 (define_insn "*pred_<madd_msub><mode>"
6439 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6440 (if_then_else:V_VLSF
6441 (unspec:<VM>
6442 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6443 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6444 (match_operand 6 "const_int_operand" " i, i, i, i")
6445 (match_operand 7 "const_int_operand" " i, i, i, i")
6446 (match_operand 8 "const_int_operand" " i, i, i, i")
6447 (match_operand 9 "const_int_operand" " i, i, i, i")
6448 (reg:SI VL_REGNUM)
6449 (reg:SI VTYPE_REGNUM)
6450 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6451 (plus_minus:V_VLSF
6452 (mult:V_VLSF
6453 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6454 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6455 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6456 (match_dup 2)))]
6457 "TARGET_VECTOR"
6458 "@
6459 vf<madd_msub>.vv\t%0,%3,%4%p1
6460 vmv%m2r.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
6461 vf<madd_msub>.vv\t%0,%3,%4%p1
6462 vmv%m2r.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1"
6463 [(set_attr "type" "vfmuladd")
6464 (set_attr "mode" "<MODE>")
6465 (set_attr "merge_op_idx" "2")
6466 (set_attr "vl_op_idx" "5")
6467 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6468 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6469 (set (attr "avl_type_idx") (const_int 8))
6470 (set (attr "frm_mode")
6471 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6473 (define_insn "*pred_<macc_msac><mode>"
6474 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6475 (if_then_else:V_VLSF
6476 (unspec:<VM>
6477 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6478 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6479 (match_operand 6 "const_int_operand" " i, i, i, i")
6480 (match_operand 7 "const_int_operand" " i, i, i, i")
6481 (match_operand 8 "const_int_operand" " i, i, i, i")
6482 (match_operand 9 "const_int_operand" " i, i, i, i")
6483 (reg:SI VL_REGNUM)
6484 (reg:SI VTYPE_REGNUM)
6485 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6486 (plus_minus:V_VLSF
6487 (mult:V_VLSF
6488 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6489 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6490 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6491 (match_dup 4)))]
6492 "TARGET_VECTOR"
6493 "@
6494 vf<macc_msac>.vv\t%0,%2,%3%p1
6495 vmv%m4r.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
6496 vf<macc_msac>.vv\t%0,%2,%3%p1
6497 vmv%m4r.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1"
6498 [(set_attr "type" "vfmuladd")
6499 (set_attr "mode" "<MODE>")
6500 (set_attr "merge_op_idx" "4")
6501 (set_attr "vl_op_idx" "5")
6502 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6503 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6504 (set (attr "avl_type_idx") (const_int 8))
6505 (set (attr "frm_mode")
6506 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6508 (define_expand "@pred_mul_<optab><mode>_scalar"
6509 [(set (match_operand:V_VLSF 0 "register_operand")
6510 (if_then_else:V_VLSF
6511 (unspec:<VM>
6512 [(match_operand:<VM> 1 "vector_mask_operand")
6513 (match_operand 6 "vector_length_operand")
6514 (match_operand 7 "const_int_operand")
6515 (match_operand 8 "const_int_operand")
6516 (match_operand 9 "const_int_operand")
6517 (match_operand 10 "const_int_operand")
6518 (reg:SI VL_REGNUM)
6519 (reg:SI VTYPE_REGNUM)
6520 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6521 (plus_minus:V_VLSF
6522 (mult:V_VLSF
6523 (vec_duplicate:V_VLSF
6524 (match_operand:<VEL> 2 "register_operand"))
6525 (match_operand:V_VLSF 3 "register_operand"))
6526 (match_operand:V_VLSF 4 "register_operand"))
6527 (match_operand:V_VLSF 5 "register_operand")))]
6528 "TARGET_VECTOR"
6529 {})
6531 (define_insn "*pred_<madd_msub><mode>_scalar"
6532 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6533 (if_then_else:V_VLSF
6534 (unspec:<VM>
6535 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6536 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6537 (match_operand 6 "const_int_operand" " i, i, i, i")
6538 (match_operand 7 "const_int_operand" " i, i, i, i")
6539 (match_operand 8 "const_int_operand" " i, i, i, i")
6540 (match_operand 9 "const_int_operand" " i, i, i, i")
6541 (reg:SI VL_REGNUM)
6542 (reg:SI VTYPE_REGNUM)
6543 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6544 (plus_minus:V_VLSF
6545 (mult:V_VLSF
6546 (vec_duplicate:V_VLSF
6547 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6548 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr"))
6549 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6550 (match_dup 3)))]
6551 "TARGET_VECTOR"
6552 "@
6553 vf<madd_msub>.vf\t%0,%2,%4%p1
6554 vmv%m3r.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
6555 vf<madd_msub>.vf\t%0,%2,%4%p1
6556 vmv%m3r.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1"
6557 [(set_attr "type" "vfmuladd")
6558 (set_attr "mode" "<MODE>")
6559 (set_attr "merge_op_idx" "3")
6560 (set_attr "vl_op_idx" "5")
6561 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6562 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6563 (set (attr "avl_type_idx") (const_int 8))
6564 (set (attr "frm_mode")
6565 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6567 (define_insn "*pred_<macc_msac><mode>_scalar"
6568 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6569 (if_then_else:V_VLSF
6570 (unspec:<VM>
6571 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6572 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6573 (match_operand 6 "const_int_operand" " i, i, i, i")
6574 (match_operand 7 "const_int_operand" " i, i, i, i")
6575 (match_operand 8 "const_int_operand" " i, i, i, i")
6576 (match_operand 9 "const_int_operand" " i, i, i, i")
6577 (reg:SI VL_REGNUM)
6578 (reg:SI VTYPE_REGNUM)
6579 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6580 (plus_minus:V_VLSF
6581 (mult:V_VLSF
6582 (vec_duplicate:V_VLSF
6583 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6584 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6585 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6586 (match_dup 4)))]
6587 "TARGET_VECTOR"
6588 "@
6589 vf<macc_msac>.vf\t%0,%2,%3%p1
6590 vmv%m4r.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
6591 vf<macc_msac>.vf\t%0,%2,%3%p1
6592 vmv%m4r.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1"
6593 [(set_attr "type" "vfmuladd")
6594 (set_attr "mode" "<MODE>")
6595 (set_attr "merge_op_idx" "4")
6596 (set_attr "vl_op_idx" "5")
6597 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6598 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6599 (set (attr "avl_type_idx") (const_int 8))
6600 (set (attr "frm_mode")
6601 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6603 (define_expand "@pred_mul_neg_<optab><mode>"
6604 [(set (match_operand:V_VLSF 0 "register_operand")
6605 (if_then_else:V_VLSF
6606 (unspec:<VM>
6607 [(match_operand:<VM> 1 "vector_mask_operand")
6608 (match_operand 6 "vector_length_operand")
6609 (match_operand 7 "const_int_operand")
6610 (match_operand 8 "const_int_operand")
6611 (match_operand 9 "const_int_operand")
6612 (match_operand 10 "const_int_operand")
6613 (reg:SI VL_REGNUM)
6614 (reg:SI VTYPE_REGNUM)
6615 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6616 (plus_minus:V_VLSF
6617 (neg:V_VLSF
6618 (mult:V_VLSF
6619 (match_operand:V_VLSF 2 "register_operand")
6620 (match_operand:V_VLSF 3 "register_operand")))
6621 (match_operand:V_VLSF 4 "register_operand"))
6622 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6623 "TARGET_VECTOR"
6624 {
6625 riscv_vector::prepare_ternary_operands (operands);
6626 })
6628 (define_insn "*pred_mul_neg_<optab><mode>_undef"
6629 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6630 (if_then_else:V_VLSF
6631 (unspec:<VM>
6632 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6633 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6634 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6635 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6636 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6637 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6638 (reg:SI VL_REGNUM)
6639 (reg:SI VTYPE_REGNUM)
6640 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6641 (plus_minus:V_VLSF
6642 (neg:V_VLSF
6643 (mult:V_VLSF
6644 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6645 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr")))
6646 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6647 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6648 "TARGET_VECTOR"
6649 "@
6650 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6651 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6652 vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6653 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6654 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6655 vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1"
6656 [(set_attr "type" "vfmuladd")
6657 (set_attr "mode" "<MODE>")
6658 (set (attr "frm_mode")
6659 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6661 (define_insn "*pred_<nmsub_nmadd><mode>"
6662 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6663 (if_then_else:V_VLSF
6664 (unspec:<VM>
6665 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6666 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6667 (match_operand 6 "const_int_operand" " i, i, i, i")
6668 (match_operand 7 "const_int_operand" " i, i, i, i")
6669 (match_operand 8 "const_int_operand" " i, i, i, i")
6670 (match_operand 9 "const_int_operand" " i, i, i, i")
6671 (reg:SI VL_REGNUM)
6672 (reg:SI VTYPE_REGNUM)
6673 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6674 (plus_minus:V_VLSF
6675 (neg:V_VLSF
6676 (mult:V_VLSF
6677 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6678 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6679 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6680 (match_dup 2)))]
6681 "TARGET_VECTOR"
6682 "@
6683 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6684 vmv%m2r.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6685 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6686 vmv%m2r.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
6687 [(set_attr "type" "vfmuladd")
6688 (set_attr "mode" "<MODE>")
6689 (set_attr "merge_op_idx" "2")
6690 (set_attr "vl_op_idx" "5")
6691 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6692 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6693 (set (attr "avl_type_idx") (const_int 8))
6694 (set (attr "frm_mode")
6695 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6697 (define_insn "*pred_<nmsac_nmacc><mode>"
6698 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6699 (if_then_else:V_VLSF
6700 (unspec:<VM>
6701 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6702 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6703 (match_operand 6 "const_int_operand" " i, i, i, i")
6704 (match_operand 7 "const_int_operand" " i, i, i, i")
6705 (match_operand 8 "const_int_operand" " i, i, i, i")
6706 (match_operand 9 "const_int_operand" " i, i, i, i")
6707 (reg:SI VL_REGNUM)
6708 (reg:SI VTYPE_REGNUM)
6709 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6710 (plus_minus:V_VLSF
6711 (neg:V_VLSF
6712 (mult:V_VLSF
6713 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6714 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6715 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6716 (match_dup 4)))]
6717 "TARGET_VECTOR"
6718 "@
6719 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6720 vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6721 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6722 vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
6723 [(set_attr "type" "vfmuladd")
6724 (set_attr "mode" "<MODE>")
6725 (set_attr "merge_op_idx" "4")
6726 (set_attr "vl_op_idx" "5")
6727 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6728 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6729 (set (attr "avl_type_idx") (const_int 8))
6730 (set (attr "frm_mode")
6731 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6733 (define_expand "@pred_mul_neg_<optab><mode>_scalar"
6734 [(set (match_operand:V_VLSF 0 "register_operand")
6735 (if_then_else:V_VLSF
6736 (unspec:<VM>
6737 [(match_operand:<VM> 1 "vector_mask_operand")
6738 (match_operand 6 "vector_length_operand")
6739 (match_operand 7 "const_int_operand")
6740 (match_operand 8 "const_int_operand")
6741 (match_operand 9 "const_int_operand")
6742 (match_operand 10 "const_int_operand")
6743 (reg:SI VL_REGNUM)
6744 (reg:SI VTYPE_REGNUM)
6745 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6746 (plus_minus:V_VLSF
6747 (neg:V_VLSF
6748 (mult:V_VLSF
6749 (vec_duplicate:V_VLSF
6750 (match_operand:<VEL> 2 "register_operand"))
6751 (match_operand:V_VLSF 3 "register_operand")))
6752 (match_operand:V_VLSF 4 "register_operand"))
6753 (match_operand:V_VLSF 5 "register_operand")))]
6754 "TARGET_VECTOR"
6755 {})
6757 (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
6758 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6759 (if_then_else:V_VLSF
6760 (unspec:<VM>
6761 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6762 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6763 (match_operand 6 "const_int_operand" " i, i, i, i")
6764 (match_operand 7 "const_int_operand" " i, i, i, i")
6765 (match_operand 8 "const_int_operand" " i, i, i, i")
6766 (match_operand 9 "const_int_operand" " i, i, i, i")
6767 (reg:SI VL_REGNUM)
6768 (reg:SI VTYPE_REGNUM)
6769 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6770 (plus_minus:V_VLSF
6771 (neg:V_VLSF
6772 (mult:V_VLSF
6773 (vec_duplicate:V_VLSF
6774 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6775 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr")))
6776 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6777 (match_dup 3)))]
6778 "TARGET_VECTOR"
6779 "@
6780 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6781 vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6782 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6783 vmv%m3r.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
6784 [(set_attr "type" "vfmuladd")
6785 (set_attr "mode" "<MODE>")
6786 (set_attr "merge_op_idx" "3")
6787 (set_attr "vl_op_idx" "5")
6788 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6789 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6790 (set (attr "avl_type_idx") (const_int 8))
6791 (set (attr "frm_mode")
6792 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6794 (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
6795 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6796 (if_then_else:V_VLSF
6797 (unspec:<VM>
6798 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6799 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6800 (match_operand 6 "const_int_operand" " i, i, i, i")
6801 (match_operand 7 "const_int_operand" " i, i, i, i")
6802 (match_operand 8 "const_int_operand" " i, i, i, i")
6803 (match_operand 9 "const_int_operand" " i, i, i, i")
6804 (reg:SI VL_REGNUM)
6805 (reg:SI VTYPE_REGNUM)
6806 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6807 (plus_minus:V_VLSF
6808 (neg:V_VLSF
6809 (mult:V_VLSF
6810 (vec_duplicate:V_VLSF
6811 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6812 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6813 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6814 (match_dup 4)))]
6815 "TARGET_VECTOR"
6816 "@
6817 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6818 vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6819 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6820 vmv%m4r.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
6821 [(set_attr "type" "vfmuladd")
6822 (set_attr "mode" "<MODE>")
6823 (set_attr "merge_op_idx" "4")
6824 (set_attr "vl_op_idx" "5")
6825 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6826 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6827 (set (attr "avl_type_idx") (const_int 8))
6828 (set (attr "frm_mode")
6829 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6831 ;; -------------------------------------------------------------------------------
6832 ;; ---- Predicated floating-point unary operations
6833 ;; -------------------------------------------------------------------------------
6834 ;; Includes:
6835 ;; - 13.8 Vector Floating-Point Square-Root Instruction
6836 ;; - 13.9 Vector Floating-Point Reciprocal Square-Root Estimate Instruction
6837 ;; - 13.10 Vector Floating-Point Reciprocal Estimate Instruction
6838 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions (vfneg.v/vfabs.v)
6839 ;; - 13.14 Vector Floating-Point Classify Instruction
6840 ;; -------------------------------------------------------------------------------
6842 (define_insn "@pred_<optab><mode>"
6843 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6844 (if_then_else:V_VLSF
6845 (unspec:<VM>
6846 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6847 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6848 (match_operand 5 "const_int_operand" " i, i, i, i")
6849 (match_operand 6 "const_int_operand" " i, i, i, i")
6850 (match_operand 7 "const_int_operand" " i, i, i, i")
6851 (match_operand 8 "const_int_operand" " i, i, i, i")
6852 (reg:SI VL_REGNUM)
6853 (reg:SI VTYPE_REGNUM)
6854 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6855 (any_float_unop:V_VLSF
6856 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6857 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6858 "TARGET_VECTOR"
6859 "vf<insn>.v\t%0,%3%p1"
6860 [(set_attr "type" "<float_insn_type>")
6861 (set_attr "mode" "<MODE>")
6862 (set_attr "vl_op_idx" "4")
6863 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6864 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6865 (set (attr "avl_type_idx") (const_int 7))
6866 (set (attr "frm_mode")
6867 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6869 (define_insn "@pred_<optab><mode>"
6870 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6871 (if_then_else:V_VLSF
6872 (unspec:<VM>
6873 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6874 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6875 (match_operand 5 "const_int_operand" " i, i, i, i")
6876 (match_operand 6 "const_int_operand" " i, i, i, i")
6877 (match_operand 7 "const_int_operand" " i, i, i, i")
6878 (reg:SI VL_REGNUM)
6879 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6880 (any_float_unop_nofrm:V_VLSF
6881 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6882 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6883 "TARGET_VECTOR"
6884 "vf<insn>.v\t%0,%3%p1"
6885 [(set_attr "type" "<float_insn_type>")
6886 (set_attr "mode" "<MODE>")
6887 (set_attr "vl_op_idx" "4")
6888 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6889 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6890 (set (attr "avl_type_idx") (const_int 7))])
6892 (define_insn "@pred_<misc_op><mode>"
6893 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6894 (if_then_else:VF
6895 (unspec:<VM>
6896 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6897 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6898 (match_operand 5 "const_int_operand" " i, i, i, i")
6899 (match_operand 6 "const_int_operand" " i, i, i, i")
6900 (match_operand 7 "const_int_operand" " i, i, i, i")
6901 (reg:SI VL_REGNUM)
6902 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6903 (unspec:VF
6904 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
6905 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6906 "TARGET_VECTOR"
6907 "vf<misc_op>.v\t%0,%3%p1"
6908 [(set_attr "type" "<float_insn_type>")
6909 (set_attr "mode" "<MODE>")])
6911 (define_insn "@pred_<misc_frm_op><mode>"
6912 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6913 (if_then_else:VF
6914 (unspec:<VM>
6915 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6916 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6917 (match_operand 5 "const_int_operand" " i, i, i, i")
6918 (match_operand 6 "const_int_operand" " i, i, i, i")
6919 (match_operand 7 "const_int_operand" " i, i, i, i")
6920 (match_operand 8 "const_int_operand" " i, i, i, i")
6921 (reg:SI VL_REGNUM)
6922 (reg:SI VTYPE_REGNUM)
6923 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6924 (unspec:VF
6925 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM)
6926 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6927 "TARGET_VECTOR"
6928 "vf<misc_frm_op>.v\t%0,%3%p1"
6929 [(set_attr "type" "<float_frm_insn_type>")
6930 (set_attr "mode" "<MODE>")
6931 (set (attr "frm_mode")
6932 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6934 (define_insn "@pred_class<mode>"
6935 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
6936 (if_then_else:<VCONVERT>
6937 (unspec:<VM>
6938 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6939 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6940 (match_operand 5 "const_int_operand" " i, i, i, i")
6941 (match_operand 6 "const_int_operand" " i, i, i, i")
6942 (match_operand 7 "const_int_operand" " i, i, i, i")
6943 (reg:SI VL_REGNUM)
6944 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6945 (unspec:<VCONVERT>
6946 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
6947 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6948 "TARGET_VECTOR"
6949 "vfclass.v\t%0,%3%p1"
6950 [(set_attr "type" "vfclass")
6951 (set_attr "mode" "<MODE>")])
6953 ;; -------------------------------------------------------------------------------
6954 ;; ---- Predicated floating-point widen binary operations
6955 ;; -------------------------------------------------------------------------------
6956 ;; Includes:
6957 ;; - 13.3 Vector Widening Floating-Point Add/Subtract Instructions
6958 ;; - 13.5 Vector Widening Floating-Point Multiply
6959 ;; -------------------------------------------------------------------------------
6961 ;; Vector Widening Add/Subtract/Multiply.
6962 (define_insn "@pred_dual_widen_<optab><mode>"
6963 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
6964 (if_then_else:VWEXTF
6965 (unspec:<VM>
6966 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
6967 (match_operand 5 "vector_length_operand" " rK, rK")
6968 (match_operand 6 "const_int_operand" " i, i")
6969 (match_operand 7 "const_int_operand" " i, i")
6970 (match_operand 8 "const_int_operand" " i, i")
6971 (match_operand 9 "const_int_operand" " i, i")
6972 (reg:SI VL_REGNUM)
6973 (reg:SI VTYPE_REGNUM)
6974 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6975 (any_widen_binop:VWEXTF
6976 (float_extend:VWEXTF
6977 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
6978 (float_extend:VWEXTF
6979 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
6980 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
6981 "TARGET_VECTOR"
6982 "vfw<insn>.vv\t%0,%3,%4%p1"
6983 [(set_attr "type" "vf<widen_binop_insn_type>")
6984 (set_attr "mode" "<V_DOUBLE_TRUNC>")
6985 (set (attr "frm_mode")
6986 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6988 (define_insn "@pred_dual_widen_<optab><mode>_scalar"
6989 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
6990 (if_then_else:VWEXTF
6991 (unspec:<VM>
6992 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
6993 (match_operand 5 "vector_length_operand" " rK, rK")
6994 (match_operand 6 "const_int_operand" " i, i")
6995 (match_operand 7 "const_int_operand" " i, i")
6996 (match_operand 8 "const_int_operand" " i, i")
6997 (match_operand 9 "const_int_operand" " i, i")
6998 (reg:SI VL_REGNUM)
6999 (reg:SI VTYPE_REGNUM)
7000 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7001 (any_widen_binop:VWEXTF
7002 (float_extend:VWEXTF
7003 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7004 (float_extend:VWEXTF
7005 (vec_duplicate:<V_DOUBLE_TRUNC>
7006 (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
7007 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7008 "TARGET_VECTOR"
7009 "vfw<insn>.vf\t%0,%3,%4%p1"
7010 [(set_attr "type" "vf<widen_binop_insn_type>")
7011 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7012 (set (attr "frm_mode")
7013 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7015 (define_insn "@pred_single_widen_add<mode>"
7016 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7017 (if_then_else:VWEXTF
7018 (unspec:<VM>
7019 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7020 (match_operand 5 "vector_length_operand" " rK, rK")
7021 (match_operand 6 "const_int_operand" " i, i")
7022 (match_operand 7 "const_int_operand" " i, i")
7023 (match_operand 8 "const_int_operand" " i, i")
7024 (match_operand 9 "const_int_operand" " i, i")
7025 (reg:SI VL_REGNUM)
7026 (reg:SI VTYPE_REGNUM)
7027 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7028 (plus:VWEXTF
7029 (float_extend:VWEXTF
7030 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
7031 (match_operand:VWEXTF 3 "register_operand" " vr, vr"))
7032 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7033 "TARGET_VECTOR"
7034 "vfwadd.wv\t%0,%3,%4%p1"
7035 [(set_attr "type" "vfwalu")
7036 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7037 (set (attr "frm_mode")
7038 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7040 (define_insn "@pred_single_widen_sub<mode>"
7041 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7042 (if_then_else:VWEXTF
7043 (unspec:<VM>
7044 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7045 (match_operand 5 "vector_length_operand" " rK, rK")
7046 (match_operand 6 "const_int_operand" " i, i")
7047 (match_operand 7 "const_int_operand" " i, i")
7048 (match_operand 8 "const_int_operand" " i, i")
7049 (match_operand 9 "const_int_operand" " i, i")
7050 (reg:SI VL_REGNUM)
7051 (reg:SI VTYPE_REGNUM)
7052 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7053 (minus:VWEXTF
7054 (match_operand:VWEXTF 3 "register_operand" " vr, vr")
7055 (float_extend:VWEXTF
7056 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7057 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7058 "TARGET_VECTOR"
7059 "vfwsub.wv\t%0,%3,%4%p1"
7060 [(set_attr "type" "vfwalu")
7061 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7062 (set (attr "frm_mode")
7063 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7065 (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
7066 [(set (match_operand:VWEXTF 0 "register_operand" "=vd, vd, vr, vr")
7067 (if_then_else:VWEXTF
7068 (unspec:<VM>
7069 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7070 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
7071 (match_operand 6 "const_int_operand" " i, i, i, i")
7072 (match_operand 7 "const_int_operand" " i, i, i, i")
7073 (match_operand 8 "const_int_operand" " i, i, i, i")
7074 (match_operand 9 "const_int_operand" " i, i, i, i")
7075 (reg:SI VL_REGNUM)
7076 (reg:SI VTYPE_REGNUM)
7077 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7078 (plus_minus:VWEXTF
7079 (match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr")
7080 (float_extend:VWEXTF
7081 (vec_duplicate:<V_DOUBLE_TRUNC>
7082 (match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f"))))
7083 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7084 "TARGET_VECTOR"
7085 "vfw<insn>.wf\t%0,%3,%4%p1"
7086 [(set_attr "type" "vf<widen_binop_insn_type>")
7087 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7088 (set (attr "frm_mode")
7089 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7091 ;; -------------------------------------------------------------------------------
7092 ;; ---- Predicated widen floating-point ternary operations
7093 ;; -------------------------------------------------------------------------------
7094 ;; Includes:
7095 ;; - 13.7 Vector Widening Floating-Point Fused Multiply-Add Instructions
7096 ;; -------------------------------------------------------------------------------
7098 (define_insn "@pred_widen_mul_<optab><mode>"
7099 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7100 (if_then_else:VWEXTF
7101 (unspec:<VM>
7102 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7103 (match_operand 5 "vector_length_operand" " rK")
7104 (match_operand 6 "const_int_operand" " i")
7105 (match_operand 7 "const_int_operand" " i")
7106 (match_operand 8 "const_int_operand" " i")
7107 (match_operand 9 "const_int_operand" " i")
7108 (reg:SI VL_REGNUM)
7109 (reg:SI VTYPE_REGNUM)
7110 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7111 (plus_minus:VWEXTF
7112 (mult:VWEXTF
7113 (float_extend:VWEXTF
7114 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7115 (float_extend:VWEXTF
7116 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7117 (match_operand:VWEXTF 2 "register_operand" " 0"))
7118 (match_dup 2)))]
7119 "TARGET_VECTOR"
7120 "vfw<macc_msac>.vv\t%0,%3,%4%p1"
7121 [(set_attr "type" "vfwmuladd")
7122 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7123 (set (attr "frm_mode")
7124 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7126 (define_insn "@pred_widen_mul_<optab><mode>_scalar"
7127 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7128 (if_then_else:VWEXTF
7129 (unspec:<VM>
7130 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7131 (match_operand 5 "vector_length_operand" " rK")
7132 (match_operand 6 "const_int_operand" " i")
7133 (match_operand 7 "const_int_operand" " i")
7134 (match_operand 8 "const_int_operand" " i")
7135 (match_operand 9 "const_int_operand" " i")
7136 (reg:SI VL_REGNUM)
7137 (reg:SI VTYPE_REGNUM)
7138 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7139 (plus_minus:VWEXTF
7140 (mult:VWEXTF
7141 (float_extend:VWEXTF
7142 (vec_duplicate:<V_DOUBLE_TRUNC>
7143 (match_operand:<VSUBEL> 3 "register_operand" " f")))
7144 (float_extend:VWEXTF
7145 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7146 (match_operand:VWEXTF 2 "register_operand" " 0"))
7147 (match_dup 2)))]
7148 "TARGET_VECTOR"
7149 "vfw<macc_msac>.vf\t%0,%3,%4%p1"
7150 [(set_attr "type" "vfwmuladd")
7151 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7152 (set (attr "frm_mode")
7153 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7155 (define_insn "@pred_widen_mul_neg_<optab><mode>"
7156 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7157 (if_then_else:VWEXTF
7158 (unspec:<VM>
7159 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7160 (match_operand 5 "vector_length_operand" " rK")
7161 (match_operand 6 "const_int_operand" " i")
7162 (match_operand 7 "const_int_operand" " i")
7163 (match_operand 8 "const_int_operand" " i")
7164 (match_operand 9 "const_int_operand" " i")
7165 (reg:SI VL_REGNUM)
7166 (reg:SI VTYPE_REGNUM)
7167 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7168 (plus_minus:VWEXTF
7169 (neg:VWEXTF
7170 (mult:VWEXTF
7171 (float_extend:VWEXTF
7172 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7173 (float_extend:VWEXTF
7174 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7175 (match_operand:VWEXTF 2 "register_operand" " 0"))
7176 (match_dup 2)))]
7177 "TARGET_VECTOR"
7178 "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
7179 [(set_attr "type" "vfwmuladd")
7180 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7181 (set (attr "frm_mode")
7182 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7184 (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
7185 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7186 (if_then_else:VWEXTF
7187 (unspec:<VM>
7188 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7189 (match_operand 5 "vector_length_operand" " rK")
7190 (match_operand 6 "const_int_operand" " i")
7191 (match_operand 7 "const_int_operand" " i")
7192 (match_operand 8 "const_int_operand" " i")
7193 (match_operand 9 "const_int_operand" " i")
7194 (reg:SI VL_REGNUM)
7195 (reg:SI VTYPE_REGNUM)
7196 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7197 (plus_minus:VWEXTF
7198 (neg:VWEXTF
7199 (mult:VWEXTF
7200 (float_extend:VWEXTF
7201 (vec_duplicate:<V_DOUBLE_TRUNC>
7202 (match_operand:<VSUBEL> 3 "register_operand" " f")))
7203 (float_extend:VWEXTF
7204 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7205 (match_operand:VWEXTF 2 "register_operand" " 0"))
7206 (match_dup 2)))]
7207 "TARGET_VECTOR"
7208 "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
7209 [(set_attr "type" "vfwmuladd")
7210 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7211 (set (attr "frm_mode")
7212 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7214 ;; -------------------------------------------------------------------------------
7215 ;; ---- Predicated floating-point comparison operations
7216 ;; -------------------------------------------------------------------------------
7217 ;; Includes:
7218 ;; - 13.13 Vector Floating-Point Compare Instructions
7219 ;; -------------------------------------------------------------------------------
7221 (define_expand "@pred_cmp<mode>"
7222 [(set (match_operand:<VM> 0 "register_operand")
7223 (if_then_else:<VM>
7224 (unspec:<VM>
7225 [(match_operand:<VM> 1 "vector_mask_operand")
7226 (match_operand 6 "vector_length_operand")
7227 (match_operand 7 "const_int_operand")
7228 (match_operand 8 "const_int_operand")
7229 (reg:SI VL_REGNUM)
7230 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7231 (match_operator:<VM> 3 "signed_order_operator"
7232 [(match_operand:V_VLSF 4 "register_operand")
7233 (match_operand:V_VLSF 5 "register_operand")])
7234 (match_operand:<VM> 2 "vector_merge_operand")))]
7235 "TARGET_VECTOR"
7236 {})
7238 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7239 (define_insn "*pred_cmp<mode>"
7240 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
7241 (if_then_else:<VM>
7242 (unspec:<VM>
7243 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
7244 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
7245 (match_operand 7 "const_int_operand" " i, i, i, i")
7246 (match_operand 8 "const_int_operand" " i, i, i, i")
7247 (reg:SI VL_REGNUM)
7248 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7249 (match_operator:<VM> 3 "signed_order_operator"
7250 [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")
7251 (match_operand:V_VLSF 5 "register_operand" " vr, vr, vr, vr")])
7252 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7253 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7254 "vmf%B3.vv\t%0,%4,%5%p1"
7255 [(set_attr "type" "vfcmp")
7256 (set_attr "mode" "<MODE>")
7257 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
7259 (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
7260 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7261 (if_then_else:<VM>
7262 (unspec:<VM>
7263 [(match_operand:<VM> 1 "register_operand" " 0")
7264 (match_operand 5 "vector_length_operand" " rK")
7265 (match_operand 6 "const_int_operand" " i")
7266 (match_operand 7 "const_int_operand" " i")
7267 (reg:SI VL_REGNUM)
7268 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7269 (match_operator:<VM> 2 "signed_order_operator"
7270 [(match_operand:V_VLSF 3 "register_operand" " vr")
7271 (match_operand:V_VLSF 4 "register_operand" " vr")])
7272 (match_dup 1)))]
7273 "TARGET_VECTOR"
7274 "vmf%B2.vv\t%0,%3,%4,v0.t"
7275 [(set_attr "type" "vfcmp")
7276 (set_attr "mode" "<MODE>")
7277 (set_attr "merge_op_idx" "1")
7278 (set_attr "vl_op_idx" "5")
7279 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7280 (set (attr "avl_type_idx") (const_int 7))])
7282 ;; We use early-clobber for source LMUL > dest LMUL.
7283 (define_insn "*pred_cmp<mode>_narrow"
7284 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
7285 (if_then_else:<VM>
7286 (unspec:<VM>
7287 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7288 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
7289 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7290 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7291 (reg:SI VL_REGNUM)
7292 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7293 (match_operator:<VM> 3 "signed_order_operator"
7294 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
7295 (match_operand:V_VLSF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
7296 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
7297 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7298 "vmf%B3.vv\t%0,%4,%5%p1"
7299 [(set_attr "type" "vfcmp")
7300 (set_attr "mode" "<MODE>")
7301 (set_attr "spec_restriction" "none,thv,thv,thv,thv,thv,thv,none,none")])
7303 (define_expand "@pred_cmp<mode>_scalar"
7304 [(set (match_operand:<VM> 0 "register_operand")
7305 (if_then_else:<VM>
7306 (unspec:<VM>
7307 [(match_operand:<VM> 1 "vector_mask_operand")
7308 (match_operand 6 "vector_length_operand")
7309 (match_operand 7 "const_int_operand")
7310 (match_operand 8 "const_int_operand")
7311 (reg:SI VL_REGNUM)
7312 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7313 (match_operator:<VM> 3 "signed_order_operator"
7314 [(match_operand:V_VLSF 4 "register_operand")
7315 (vec_duplicate:V_VLSF
7316 (match_operand:<VEL> 5 "register_operand"))])
7317 (match_operand:<VM> 2 "vector_merge_operand")))]
7318 "TARGET_VECTOR"
7319 {})
7321 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
7322 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7323 (if_then_else:<VM>
7324 (unspec:<VM>
7325 [(match_operand:<VM> 1 "register_operand" " 0")
7326 (match_operand 5 "vector_length_operand" " rK")
7327 (match_operand 6 "const_int_operand" " i")
7328 (match_operand 7 "const_int_operand" " i")
7329 (reg:SI VL_REGNUM)
7330 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7331 (match_operator:<VM> 2 "signed_order_operator"
7332 [(match_operand:V_VLSF 3 "register_operand" " vr")
7333 (vec_duplicate:V_VLSF
7334 (match_operand:<VEL> 4 "register_operand" " f"))])
7335 (match_dup 1)))]
7336 "TARGET_VECTOR"
7337 "vmf%B2.vf\t%0,%3,%4,v0.t"
7338 [(set_attr "type" "vfcmp")
7339 (set_attr "mode" "<MODE>")
7340 (set_attr "merge_op_idx" "1")
7341 (set_attr "vl_op_idx" "5")
7342 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7343 (set (attr "avl_type_idx") (const_int 7))])
7345 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7346 (define_insn "*pred_cmp<mode>_scalar"
7347 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
7348 (if_then_else:<VM>
7349 (unspec:<VM>
7350 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
7351 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
7352 (match_operand 7 "const_int_operand" " i, i, i, i")
7353 (match_operand 8 "const_int_operand" " i, i, i, i")
7354 (reg:SI VL_REGNUM)
7355 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7356 (match_operator:<VM> 3 "signed_order_operator"
7357 [(match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")
7358 (vec_duplicate:V_VLSF
7359 (match_operand:<VEL> 5 "register_operand" " f, f, f, f"))])
7360 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7361 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7362 "vmf%B3.vf\t%0,%4,%5%p1"
7363 [(set_attr "type" "vfcmp")
7364 (set_attr "mode" "<MODE>")
7365 (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
7367 ;; We use early-clobber for source LMUL > dest LMUL.
7368 (define_insn "*pred_cmp<mode>_scalar_narrow"
7369 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7370 (if_then_else:<VM>
7371 (unspec:<VM>
7372 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7373 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7374 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7375 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7376 (reg:SI VL_REGNUM)
7377 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7378 (match_operator:<VM> 3 "signed_order_operator"
7379 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")
7380 (vec_duplicate:V_VLSF
7381 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
7382 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7383 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7384 "vmf%B3.vf\t%0,%4,%5%p1"
7385 [(set_attr "type" "vfcmp")
7386 (set_attr "mode" "<MODE>")
7387 (set_attr "spec_restriction" "none,thv,thv,none,none")])
7389 ;; -------------------------------------------------------------------------------
7390 ;; ---- Predicated floating-point merge
7391 ;; -------------------------------------------------------------------------------
7392 ;; Includes:
7393 ;; - 13.15 Vector Floating-Point Merge Instruction
7394 ;; -------------------------------------------------------------------------------
7396 (define_insn "@pred_merge<mode>_scalar"
7397 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd")
7398 (if_then_else:V_VLSF
7399 (unspec:<VM>
7400 [(match_operand 5 "vector_length_operand" " rK,rK")
7401 (match_operand 6 "const_int_operand" " i, i")
7402 (match_operand 7 "const_int_operand" " i, i")
7403 (reg:SI VL_REGNUM)
7404 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7405 (vec_merge:V_VLSF
7406 (vec_duplicate:V_VLSF
7407 (match_operand:<VEL> 3 "register_operand" " f, f"))
7408 (match_operand:V_VLSF 2 "register_operand" " vr,vr")
7409 (match_operand:<VM> 4 "register_operand" " vm,vm"))
7410 (match_operand:V_VLSF 1 "vector_merge_operand" " vu, 0")))]
7411 "TARGET_VECTOR"
7412 "vfmerge.vfm\t%0,%2,%3,%4"
7413 [(set_attr "type" "vfmerge")
7414 (set_attr "mode" "<MODE>")])
7416 ;; -------------------------------------------------------------------------------
7417 ;; ---- Predicated floating-point conversions
7418 ;; -------------------------------------------------------------------------------
7419 ;; Includes:
7420 ;; - 13.17 Single-Width Floating-Point/Integer Type-Convert Instructions
7421 ;; -------------------------------------------------------------------------------
7423 (define_insn "@pred_fcvt_x<v_su>_f<mode>"
7424 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7425 (if_then_else:<VCONVERT>
7426 (unspec:<VM>
7427 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7428 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7429 (match_operand 5 "const_int_operand" " i, i, i, i")
7430 (match_operand 6 "const_int_operand" " i, i, i, i")
7431 (match_operand 7 "const_int_operand" " i, i, i, i")
7432 (match_operand 8 "const_int_operand" " i, i, i, i")
7433 (reg:SI VL_REGNUM)
7434 (reg:SI VTYPE_REGNUM)
7435 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7436 (unspec:<VCONVERT>
7437 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
7438 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7439 "TARGET_VECTOR"
7440 "vfcvt.x<v_su>.f.v\t%0,%3%p1"
7441 [(set_attr "type" "vfcvtftoi")
7442 (set_attr "mode" "<MODE>")
7443 (set (attr "frm_mode")
7444 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7446 (define_insn "@pred_<fix_cvt><mode>"
7447 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7448 (if_then_else:<VCONVERT>
7449 (unspec:<VM>
7450 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7451 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7452 (match_operand 5 "const_int_operand" " i, i, i, i")
7453 (match_operand 6 "const_int_operand" " i, i, i, i")
7454 (match_operand 7 "const_int_operand" " i, i, i, i")
7455 (reg:SI VL_REGNUM)
7456 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7457 (any_fix:<VCONVERT>
7458 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
7459 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7460 "TARGET_VECTOR"
7461 "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
7462 [(set_attr "type" "vfcvtftoi")
7463 (set_attr "mode" "<MODE>")])
7465 (define_insn "@pred_<float_cvt><mode>"
7466 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
7467 (if_then_else:V_VLSF
7468 (unspec:<VM>
7469 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7470 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7471 (match_operand 5 "const_int_operand" " i, i, i, i")
7472 (match_operand 6 "const_int_operand" " i, i, i, i")
7473 (match_operand 7 "const_int_operand" " i, i, i, i")
7474 (match_operand 8 "const_int_operand" " i, i, i, i")
7475 (reg:SI VL_REGNUM)
7476 (reg:SI VTYPE_REGNUM)
7477 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7478 (any_float:V_VLSF
7479 (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
7480 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7481 "TARGET_VECTOR"
7482 "vfcvt.f.x<u>.v\t%0,%3%p1"
7483 [(set_attr "type" "vfcvtitof")
7484 (set_attr "mode" "<MODE>")
7485 (set (attr "frm_mode")
7486 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7488 ;; -------------------------------------------------------------------------------
7489 ;; ---- Predicated floating-point widen conversions
7490 ;; -------------------------------------------------------------------------------
7491 ;; Includes:
7492 ;; - 13.18 Widening Floating-Point/Integer Type-Convert Instructions
7493 ;; -------------------------------------------------------------------------------
7495 (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
7496 [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
7497 (if_then_else:VWCONVERTI
7498 (unspec:<VM>
7499 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7500 (match_operand 4 "vector_length_operand" " rK, rK")
7501 (match_operand 5 "const_int_operand" " i, i")
7502 (match_operand 6 "const_int_operand" " i, i")
7503 (match_operand 7 "const_int_operand" " i, i")
7504 (match_operand 8 "const_int_operand" " i, i")
7505 (reg:SI VL_REGNUM)
7506 (reg:SI VTYPE_REGNUM)
7507 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7508 (unspec:VWCONVERTI
7509 [(match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")] VFCVTS)
7510 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
7511 "TARGET_VECTOR"
7512 "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
7513 [(set_attr "type" "vfwcvtftoi")
7514 (set_attr "mode" "<VNCONVERT>")
7515 (set (attr "frm_mode")
7516 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7518 (define_insn "@pred_widen_<fix_cvt><mode>"
7519 [(set (match_operand:VWCONVERTI 0 "register_operand" "=&vr, &vr")
7520 (if_then_else:VWCONVERTI
7521 (unspec:<VM>
7522 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7523 (match_operand 4 "vector_length_operand" " rK, rK")
7524 (match_operand 5 "const_int_operand" " i, i")
7525 (match_operand 6 "const_int_operand" " i, i")
7526 (match_operand 7 "const_int_operand" " i, i")
7527 (reg:SI VL_REGNUM)
7528 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7529 (any_fix:VWCONVERTI
7530 (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
7531 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0")))]
7532 "TARGET_VECTOR"
7533 "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
7534 [(set_attr "type" "vfwcvtftoi")
7535 (set_attr "mode" "<VNCONVERT>")])
7537 (define_insn "@pred_widen_<float_cvt><mode>"
7538 [(set (match_operand:V_VLSF 0 "register_operand" "=&vr, &vr")
7539 (if_then_else:V_VLSF
7540 (unspec:<VM>
7541 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7542 (match_operand 4 "vector_length_operand" " rK, rK")
7543 (match_operand 5 "const_int_operand" " i, i")
7544 (match_operand 6 "const_int_operand" " i, i")
7545 (match_operand 7 "const_int_operand" " i, i")
7546 (reg:SI VL_REGNUM)
7547 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7548 (any_float:V_VLSF
7549 (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr"))
7550 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0")))]
7551 "TARGET_VECTOR"
7552 "vfwcvt.f.x<u>.v\t%0,%3%p1"
7553 [(set_attr "type" "vfwcvtitof")
7554 (set_attr "mode" "<VNCONVERT>")])
7556 (define_insn "@pred_extend<mode>"
7557 [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=&vr, &vr")
7558 (if_then_else:VWEXTF_ZVFHMIN
7559 (unspec:<VM>
7560 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7561 (match_operand 4 "vector_length_operand" " rK, rK")
7562 (match_operand 5 "const_int_operand" " i, i")
7563 (match_operand 6 "const_int_operand" " i, i")
7564 (match_operand 7 "const_int_operand" " i, i")
7565 (reg:SI VL_REGNUM)
7566 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7567 (float_extend:VWEXTF_ZVFHMIN
7568 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7569 (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0")))]
7570 "TARGET_VECTOR"
7571 "vfwcvt.f.f.v\t%0,%3%p1"
7572 [(set_attr "type" "vfwcvtftof")
7573 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
7575 ;; -------------------------------------------------------------------------------
7576 ;; ---- Predicated floating-point narrow conversions
7577 ;; -------------------------------------------------------------------------------
7578 ;; Includes:
7579 ;; - 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
7580 ;; -------------------------------------------------------------------------------
7582 (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
7583 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7584 (if_then_else:<VNCONVERT>
7585 (unspec:<VM>
7586 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7587 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7588 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7589 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7590 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7591 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7592 (reg:SI VL_REGNUM)
7593 (reg:SI VTYPE_REGNUM)
7594 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7595 (unspec:<VNCONVERT>
7596 [(match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
7597 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7598 "TARGET_VECTOR"
7599 "vfncvt.x<v_su>.f.w\t%0,%3%p1"
7600 [(set_attr "type" "vfncvtftoi")
7601 (set_attr "mode" "<VNCONVERT>")
7602 (set (attr "frm_mode")
7603 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7604 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7606 (define_insn "@pred_narrow_<fix_cvt><mode>"
7607 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7608 (if_then_else:<VNCONVERT>
7609 (unspec:<VM>
7610 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7611 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7612 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7613 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7614 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7615 (reg:SI VL_REGNUM)
7616 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7617 (any_fix:<VNCONVERT>
7618 (match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7619 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7620 "TARGET_VECTOR"
7621 "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
7622 [(set_attr "type" "vfncvtftoi")
7623 (set_attr "mode" "<VNCONVERT>")])
7625 (define_insn "@pred_narrow_<float_cvt><mode>"
7626 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7627 (if_then_else:<VNCONVERT>
7628 (unspec:<VM>
7629 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7630 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7631 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7632 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7633 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7634 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7635 (reg:SI VL_REGNUM)
7636 (reg:SI VTYPE_REGNUM)
7637 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7638 (any_float:<VNCONVERT>
7639 (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7640 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7641 "TARGET_VECTOR"
7642 "vfncvt.f.x<u>.w\t%0,%3%p1"
7643 [(set_attr "type" "vfncvtitof")
7644 (set_attr "mode" "<VNCONVERT>")
7645 (set (attr "frm_mode")
7646 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7647 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7649 (define_insn "@pred_trunc<mode>"
7650 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7651 (if_then_else:<V_DOUBLE_TRUNC>
7652 (unspec:<VM>
7653 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7654 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7655 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7656 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7657 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7658 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7659 (reg:SI VL_REGNUM)
7660 (reg:SI VTYPE_REGNUM)
7661 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7662 (float_truncate:<V_DOUBLE_TRUNC>
7663 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7664 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7665 "TARGET_VECTOR"
7666 "vfncvt.f.f.w\t%0,%3%p1"
7667 [(set_attr "type" "vfncvtftof")
7668 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7669 (set (attr "frm_mode")
7670 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7671 (set_attr "spec_restriction" "none,none,thv,thv,none,none")])
7673 (define_insn "@pred_rod_trunc<mode>"
7674 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7675 (if_then_else:<V_DOUBLE_TRUNC>
7676 (unspec:<VM>
7677 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7678 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7679 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7680 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7681 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7682 (reg:SI VL_REGNUM)
7683 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7684 (unspec:<V_DOUBLE_TRUNC>
7685 [(float_truncate:<V_DOUBLE_TRUNC>
7686 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
7687 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7688 "TARGET_VECTOR"
7689 "vfncvt.rod.f.f.w\t%0,%3%p1"
7690 [(set_attr "type" "vfncvtftof")
7691 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
7693 ;; -------------------------------------------------------------------------------
7694 ;; ---- Predicated reduction operations
7695 ;; -------------------------------------------------------------------------------
7696 ;; Includes:
7697 ;; - 14.1 Vector Single-Width Integer Reduction Instructions
7698 ;; - 14.2 Vector Widening Integer Reduction Instructions
7699 ;; - 14.3 Vector Single-Width Floating-Point Reduction Instructions
7700 ;; - 14.4 Vector Widening Floating-Point Reduction Instructions
7701 ;; -------------------------------------------------------------------------------
7703 ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
7704 (define_insn "@pred_<reduc_op><mode>"
7705 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7706 (unspec:<V_LMUL1>
7707 [(unspec:<VM>
7708 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7709 (match_operand 5 "vector_length_operand" " rK, rK")
7710 (match_operand 6 "const_int_operand" " i, i")
7711 (match_operand 7 "const_int_operand" " i, i")
7712 (reg:SI VL_REGNUM)
7713 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7714 (unspec:<V_LMUL1> [
7715 (match_operand:V_VLSI 3 "register_operand" " vr, vr")
7716 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7717 ] ANY_REDUC)
7718 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7719 "TARGET_VECTOR"
7720 "v<reduc_op>.vs\t%0,%3,%4%p1"
7721 [(set_attr "type" "vired")
7722 (set_attr "mode" "<MODE>")])
7724 ;; Integer Widen Reduction Sum (vwredsum[u].vs)
7725 (define_insn "@pred_<reduc_op><mode>"
7726 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr, vr")
7727 (unspec:<V_EXT_LMUL1>
7728 [(unspec:<VM>
7729 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7730 (match_operand 5 "vector_length_operand" " rK, rK")
7731 (match_operand 6 "const_int_operand" " i, i")
7732 (match_operand 7 "const_int_operand" " i, i")
7733 (reg:SI VL_REGNUM)
7734 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7735 (unspec:<V_EXT_LMUL1> [
7736 (match_operand:VI_QHS 3 "register_operand" " vr, vr")
7737 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
7738 ] ANY_WREDUC)
7739 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7740 "TARGET_VECTOR"
7741 "v<reduc_op>.vs\t%0,%3,%4%p1"
7742 [(set_attr "type" "viwred")
7743 (set_attr "mode" "<MODE>")])
7745 ;; Float Reduction (vfred(max|min).vs)
7746 (define_insn "@pred_<reduc_op><mode>"
7747 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7748 (unspec:<V_LMUL1>
7749 [(unspec:<VM>
7750 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7751 (match_operand 5 "vector_length_operand" " rK, rK")
7752 (match_operand 6 "const_int_operand" " i, i")
7753 (match_operand 7 "const_int_operand" " i, i")
7754 (reg:SI VL_REGNUM)
7755 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7756 (unspec:<V_LMUL1> [
7757 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7758 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7759 ] ANY_FREDUC)
7760 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7761 "TARGET_VECTOR"
7762 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7763 [(set_attr "type" "vfredu")
7764 (set_attr "mode" "<MODE>")])
7766 ;; Float Reduction Sum (vfred[ou]sum.vs)
7767 (define_insn "@pred_<reduc_op><mode>"
7768 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
7769 (unspec:<V_LMUL1>
7770 [(unspec:<VM>
7771 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7772 (match_operand 5 "vector_length_operand" " rK, rK")
7773 (match_operand 6 "const_int_operand" " i, i")
7774 (match_operand 7 "const_int_operand" " i, i")
7775 (match_operand 8 "const_int_operand" " i, i")
7776 (reg:SI VL_REGNUM)
7777 (reg:SI VTYPE_REGNUM)
7778 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7779 (unspec:<V_LMUL1> [
7780 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7781 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7782 ] ANY_FREDUC_SUM)
7783 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7784 "TARGET_VECTOR"
7785 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7786 [(set_attr "type" "vfred<order>")
7787 (set_attr "mode" "<MODE>")
7788 (set (attr "frm_mode")
7789 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7791 ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
7792 (define_insn "@pred_<reduc_op><mode>"
7793 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=vr, vr")
7794 (unspec:<V_EXT_LMUL1>
7795 [(unspec:<VM>
7796 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7797 (match_operand 5 "vector_length_operand" " rK, rK")
7798 (match_operand 6 "const_int_operand" " i, i")
7799 (match_operand 7 "const_int_operand" " i, i")
7800 (match_operand 8 "const_int_operand" " i, i")
7801 (reg:SI VL_REGNUM)
7802 (reg:SI VTYPE_REGNUM)
7803 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7804 (unspec:<V_EXT_LMUL1> [
7805 (match_operand:VF_HS 3 "register_operand" " vr, vr")
7806 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr, vr")
7807 ] ANY_FWREDUC_SUM)
7808 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7809 "TARGET_VECTOR"
7810 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7811 [(set_attr "type" "vfwred<order>")
7812 (set_attr "mode" "<MODE>")
7813 (set (attr "frm_mode")
7814 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7816 ;; -------------------------------------------------------------------------------
7817 ;; ---- Predicated permutation operations
7818 ;; -------------------------------------------------------------------------------
7819 ;; Includes:
7820 ;; - 16.1 Integer Scalar Move Instructions
7821 ;; - 16.2 Floating-Point Scalar Move Instructions
7822 ;; - 16.3 Vector Slide Instructions
7823 ;; - 16.4 Vector Register Gather Instructions
7824 ;; - 16.5 Vector Compress Instruction
7825 ;; -------------------------------------------------------------------------------
7827 (define_expand "@pred_extract_first<mode>"
7828 [(set (match_operand:<VEL> 0 "register_operand")
7829 (unspec:<VEL>
7830 [(vec_select:<VEL>
7831 (match_operand:V_VLSI 1 "reg_or_mem_operand")
7832 (parallel [(const_int 0)]))
7833 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7834 "TARGET_VECTOR"
7835 {
7836 if (MEM_P (operands[1]))
7837 {
7838 /* Combine vle.v + vmv.x.s ==> lw. */
7839 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
7840 DONE;
7841 }
7842 })
7844 (define_insn_and_split "*pred_extract_first<mode>"
7845 [(set (match_operand:<VEL> 0 "register_operand" "=r")
7846 (unspec:<VEL>
7847 [(vec_select:<VEL>
7848 (match_operand:V_VLSI 1 "register_operand" "vr")
7849 (parallel [(const_int 0)]))
7850 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7851 "TARGET_VECTOR"
7852 "vmv.x.s\t%0,%1"
7853 "known_gt (GET_MODE_BITSIZE (<VEL>mode), GET_MODE_BITSIZE (Pmode))"
7854 [(const_int 0)]
7855 {
7856 /* In rv32 system, we can't use vmv.x.s directly.
7857 Instead, we should generate this following code sequence:
7858 vsrl.vx v16,v8,a0
7859 vmv.x.s a1,v16
7860 vmv.x.s a0,v8 */
7861 rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
7862 rtx high_bits = gen_reg_rtx (<MODE>mode);
7863 emit_insn (gen_pred_scalar (LSHIFTRT, <MODE>mode, high_bits, CONSTM1_RTX (<VM>mode),
7864 RVV_VUNDEF (<MODE>mode), operands[1], nbits, /* vl */ const1_rtx,
7865 gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
7866 gen_int_mode (riscv_vector::MASK_ANY, Pmode),
7867 gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
7868 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
7869 gen_highpart (SImode, operands[0]), high_bits));
7870 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
7871 gen_lowpart (SImode, operands[0]), operands[1]));
7872 DONE;
7873 }
7874 [(set_attr "type" "vimovvx")
7875 (set_attr "mode" "<MODE>")])
7877 (define_insn "@pred_extract_first_trunc<mode>"
7878 [(set (match_operand:SI 0 "register_operand" "=r")
7879 (truncate:SI
7880 (unspec:<VEL>
7881 [(vec_select:<VEL>
7882 (match_operand:V_VLSI_D 1 "register_operand" "vr")
7883 (parallel [(const_int 0)]))
7884 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
7885 "TARGET_VECTOR"
7886 "vmv.x.s\t%0,%1"
7887 [(set_attr "type" "vimovvx")
7888 (set_attr "mode" "<MODE>")])
7890 (define_expand "@pred_extract_first<mode>"
7891 [(set (match_operand:<VEL> 0 "register_operand")
7892 (unspec:<VEL>
7893 [(vec_select:<VEL>
7894 (match_operand:V_VLSF 1 "reg_or_mem_operand")
7895 (parallel [(const_int 0)]))
7896 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7897 "TARGET_VECTOR"
7898 {
7899 if (MEM_P (operands[1]))
7900 {
7901 /* Combine vle.v + vmv.f.s ==> flw. */
7902 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
7903 DONE;
7904 }
7905 })
7907 (define_insn "*pred_extract_first<mode>"
7908 [(set (match_operand:<VEL> 0 "register_operand" "=f")
7909 (unspec:<VEL>
7910 [(vec_select:<VEL>
7911 (match_operand:V_VLSF 1 "register_operand" "vr")
7912 (parallel [(const_int 0)]))
7913 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7914 "TARGET_VECTOR"
7915 "vfmv.f.s\t%0,%1"
7916 [(set_attr "type" "vfmovvf")
7917 (set_attr "mode" "<MODE>")])
7919 ;; vslide instructions
7920 (define_insn "@pred_slide<ud><mode>"
7921 [(set (match_operand:V_VLS 0 "register_operand" "<ud_constraint>")
7922 (unspec:V_VLS
7923 [(unspec:<VM>
7924 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7925 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
7926 (match_operand 6 "const_int_operand" " i, i, i, i")
7927 (match_operand 7 "const_int_operand" " i, i, i, i")
7928 (match_operand 8 "const_int_operand" " i, i, i, i")
7929 (reg:SI VL_REGNUM)
7930 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7931 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0, vu, 0")
7932 (match_operand:V_VLS 3 "register_operand" " vr, vr, vr, vr")
7933 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSLIDES))]
7934 "TARGET_VECTOR"
7935 "vslide<ud>.v%o4\t%0,%3,%4%p1"
7936 [(set_attr "type" "vslide<ud>")
7937 (set_attr "mode" "<MODE>")])
7939 ;; vslide1 instructions
7940 (define_insn "@pred_slide<ud><mode>"
7941 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "<ud_constraint>")
7942 (unspec:V_VLSI_QHS
7943 [(unspec:<VM>
7944 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7945 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
7946 (match_operand 6 "const_int_operand" " i, i, i, i")
7947 (match_operand 7 "const_int_operand" " i, i, i, i")
7948 (match_operand 8 "const_int_operand" " i, i, i, i")
7949 (reg:SI VL_REGNUM)
7950 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7951 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")
7952 (match_operand:V_VLSI_QHS 3 "register_operand" " vr, vr, vr, vr")
7953 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
7954 "TARGET_VECTOR"
7955 "vslide<ud>.vx\t%0,%3,%z4%p1"
7956 [(set_attr "type" "vislide<ud>")
7957 (set_attr "mode" "<MODE>")])
7959 (define_expand "@pred_slide<ud><mode>"
7960 [(set (match_operand:V_VLSI_D 0 "register_operand")
7961 (unspec:V_VLSI_D
7962 [(unspec:<VM>
7963 [(match_operand:<VM> 1 "vector_mask_operand")
7964 (match_operand 5 "reg_or_int_operand")
7965 (match_operand 6 "const_int_operand")
7966 (match_operand 7 "const_int_operand")
7967 (match_operand 8 "const_int_operand")
7968 (reg:SI VL_REGNUM)
7969 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7970 (match_operand:V_VLSI_D 2 "vector_merge_operand")
7971 (match_operand:V_VLSI_D 3 "register_operand")
7972 (match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
7973 "TARGET_VECTOR"
7974 {
7975 poly_uint64 nunits = GET_MODE_NUNITS (<MODE>mode) * 2;
7976 machine_mode vsimode = riscv_vector::get_vector_mode (SImode, nunits).require ();
7977 machine_mode vbimode = riscv_vector::get_vector_mode (BImode, nunits).require ();
7978 if (riscv_vector::slide1_sew64_helper (<UNSPEC>, <MODE>mode,
7979 vsimode, vbimode,
7980 operands))
7981 DONE;
7982 })
7984 (define_insn "*pred_slide<ud><mode>"
7985 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
7986 (unspec:V_VLSI_D
7987 [(unspec:<VM>
7988 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7989 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
7990 (match_operand 6 "const_int_operand" " i, i, i, i")
7991 (match_operand 7 "const_int_operand" " i, i, i, i")
7992 (match_operand 8 "const_int_operand" " i, i, i, i")
7993 (reg:SI VL_REGNUM)
7994 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7995 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
7996 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
7997 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
7998 "TARGET_VECTOR"
7999 "vslide<ud>.vx\t%0,%3,%z4%p1"
8000 [(set_attr "type" "vislide<ud>")
8001 (set_attr "mode" "<MODE>")])
8003 (define_insn "*pred_slide<ud><mode>_extended"
8004 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8005 (unspec:V_VLSI_D
8006 [(unspec:<VM>
8007 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8008 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8009 (match_operand 6 "const_int_operand" " i, i, i, i")
8010 (match_operand 7 "const_int_operand" " i, i, i, i")
8011 (match_operand 8 "const_int_operand" " i, i, i, i")
8012 (reg:SI VL_REGNUM)
8013 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8014 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8015 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8016 (sign_extend:<VEL>
8017 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))]
8018 "TARGET_VECTOR && !TARGET_64BIT"
8019 "vslide<ud>.vx\t%0,%3,%z4%p1"
8020 [(set_attr "type" "vislide<ud>")
8021 (set_attr "mode" "<MODE>")])
8023 ;; vfslide1 instructions
8024 (define_insn "@pred_slide<ud><mode>"
8025 [(set (match_operand:V_VLSF 0 "register_operand" "<ud_constraint>")
8026 (unspec:V_VLSF
8027 [(unspec:<VM>
8028 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8029 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8030 (match_operand 6 "const_int_operand" " i, i, i, i")
8031 (match_operand 7 "const_int_operand" " i, i, i, i")
8032 (match_operand 8 "const_int_operand" " i, i, i, i")
8033 (reg:SI VL_REGNUM)
8034 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8035 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")
8036 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
8037 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
8038 "TARGET_VECTOR"
8039 "vfslide<ud>.vf\t%0,%3,%4%p1"
8040 [(set_attr "type" "vfslide<ud>")
8041 (set_attr "mode" "<MODE>")])
8043 ;; vrgather
8044 (define_insn "@pred_gather<mode>"
8045 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8046 (if_then_else:V_VLS
8047 (unspec:<VM>
8048 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8049 (match_operand 5 "vector_length_operand" " rK, rK")
8050 (match_operand 6 "const_int_operand" " i, i")
8051 (match_operand 7 "const_int_operand" " i, i")
8052 (match_operand 8 "const_int_operand" " i, i")
8053 (reg:SI VL_REGNUM)
8054 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8055 (unspec:V_VLS
8056 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8057 (match_operand:<VINDEX> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHER)
8058 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8059 "TARGET_VECTOR"
8060 "vrgather.vv\t%0,%3,%4%p1"
8061 [(set_attr "type" "vgather")
8062 (set_attr "mode" "<MODE>")])
8064 (define_insn "@pred_gather<mode>_scalar"
8065 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8066 (if_then_else:V_VLS
8067 (unspec:<VM>
8068 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8069 (match_operand 5 "vector_length_operand" " rK, rK")
8070 (match_operand 6 "const_int_operand" " i, i")
8071 (match_operand 7 "const_int_operand" " i, i")
8072 (match_operand 8 "const_int_operand" " i, i")
8073 (reg:SI VL_REGNUM)
8074 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8075 (unspec:V_VLS
8076 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8077 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] UNSPEC_VRGATHER)
8078 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8079 "TARGET_VECTOR"
8080 "vrgather.v%o4\t%0,%3,%4%p1"
8081 [(set_attr "type" "vgather")
8082 (set_attr "mode" "<MODE>")])
8084 ;; vrgatherei16
8085 (define_insn "@pred_gatherei16<mode>"
8086 [(set (match_operand:VEI16 0 "register_operand" "=&vr, &vr")
8087 (if_then_else:VEI16
8088 (unspec:<VM>
8089 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8090 (match_operand 5 "vector_length_operand" " rK, rK")
8091 (match_operand 6 "const_int_operand" " i, i")
8092 (match_operand 7 "const_int_operand" " i, i")
8093 (match_operand 8 "const_int_operand" " i, i")
8094 (reg:SI VL_REGNUM)
8095 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8096 (unspec:VEI16
8097 [(match_operand:VEI16 3 "register_operand" " vr, vr")
8098 (match_operand:<VINDEXEI16> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHEREI16)
8099 (match_operand:VEI16 2 "vector_merge_operand" " vu, 0")))]
8100 "TARGET_VECTOR"
8101 "vrgatherei16.vv\t%0,%3,%4%p1"
8102 [(set_attr "type" "vgather")
8103 (set_attr "mode" "<MODE>")])
8105 ;; vcompress
8106 (define_insn "@pred_compress<mode>"
8107 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8108 (unspec:V_VLS
8109 [(unspec:<VM>
8110 [(match_operand:<VM> 3 "register_operand" " vm, vm")
8111 (match_operand 4 "vector_length_operand" " rK, rK")
8112 (match_operand 5 "const_int_operand" " i, i")
8113 (match_operand 6 "const_int_operand" " i, i")
8114 (reg:SI VL_REGNUM)
8115 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8116 (match_operand:V_VLS 2 "register_operand" " vr, vr")
8117 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))]
8118 "TARGET_VECTOR"
8119 "vcompress.vm\t%0,%2,%3"
8120 [(set_attr "type" "vcompress")
8121 (set_attr "mode" "<MODE>")])
8123 ;; -------------------------------------------------------------------------------
8124 ;; ---- Predicated Fault-Only-First loads
8125 ;; -------------------------------------------------------------------------------
8126 ;; Includes:
8127 ;; - 7.7. Unit-stride Fault-Only-First Loads
8128 ;; -------------------------------------------------------------------------------
8130 (define_insn "read_vlsi"
8131 [(set (match_operand:SI 0 "register_operand" "=r")
8132 (reg:SI VL_REGNUM))]
8133 "TARGET_VECTOR"
8134 "csrr\t%0,vl"
8135 [(set_attr "type" "rdvl")
8136 (set_attr "mode" "SI")])
8138 (define_insn "read_vldi_zero_extend"
8139 [(set (match_operand:DI 0 "register_operand" "=r")
8140 (zero_extend:DI (reg:SI VL_REGNUM)))]
8141 "TARGET_VECTOR && TARGET_64BIT"
8142 "csrr\t%0,vl"
8143 [(set_attr "type" "rdvl")
8144 (set_attr "mode" "DI")])
8146 (define_insn "@pred_fault_load<mode>"
8147 [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr")
8148 (if_then_else:V
8149 (unspec:<VM>
8150 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1, Wc1")
8151 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
8152 (match_operand 5 "const_int_operand" " i, i, i, i")
8153 (match_operand 6 "const_int_operand" " i, i, i, i")
8154 (match_operand 7 "const_int_operand" " i, i, i, i")
8155 (reg:SI VL_REGNUM)
8156 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8157 (unspec:V
8158 [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF)
8159 (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0")))
8160 (set (reg:SI VL_REGNUM)
8161 (unspec:SI
8162 [(if_then_else:V
8163 (unspec:<VM>
8164 [(match_dup 1) (match_dup 4) (match_dup 5)
8165 (match_dup 6) (match_dup 7)
8166 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8167 (unspec:V [(match_dup 3)] UNSPEC_VLEFF)
8168 (match_dup 2))] UNSPEC_MODIFY_VL))]
8169 "TARGET_VECTOR"
8170 "vle<sew>ff.v\t%0,%3%p1"
8171 [(set_attr "type" "vldff")
8172 (set_attr "mode" "<MODE>")])
8175 ;; -------------------------------------------------------------------------------
8176 ;; ---- Predicated Segment loads/stores
8177 ;; -------------------------------------------------------------------------------
8178 ;; Includes:
8179 ;; - 7.8.1. Vector Unit-Stride Segment Loads and Stores
8180 ;; - 7.8.2. Vector Strided Segment Loads and Stores
8181 ;; - 7.8.3. Vector Indexed Segment Loads and Stores
8182 ;; -------------------------------------------------------------------------------
8184 (define_insn "@pred_unit_strided_load<mode>"
8185 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8186 (if_then_else:VT
8187 (unspec:<VM>
8188 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8189 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8190 (match_operand 5 "const_int_operand" " i, i, i")
8191 (match_operand 6 "const_int_operand" " i, i, i")
8192 (match_operand 7 "const_int_operand" " i, i, i")
8193 (reg:SI VL_REGNUM)
8194 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8195 (unspec:VT
8196 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8197 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED)
8198 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8199 "TARGET_VECTOR"
8200 "vlseg<nf>e<sew>.v\t%0,(%z3)%p1"
8201 [(set_attr "type" "vlsegde")
8202 (set_attr "mode" "<MODE>")])
8204 (define_insn "@pred_unit_strided_store<mode>"
8205 [(set (mem:BLK (scratch))
8206 (unspec:BLK
8207 [(unspec:<VM>
8208 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8209 (match_operand 3 "vector_length_operand" " rK")
8210 (match_operand 4 "const_int_operand" " i")
8211 (reg:SI VL_REGNUM)
8212 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8213 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8214 (match_operand:VT 2 "register_operand" " vr")
8215 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED))]
8216 "TARGET_VECTOR"
8217 "vsseg<nf>e<sew>.v\t%2,(%z1)%p0"
8218 [(set_attr "type" "vssegte")
8219 (set_attr "mode" "<MODE>")])
8221 (define_insn "@pred_strided_load<mode>"
8222 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8223 (if_then_else:VT
8224 (unspec:<VM>
8225 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8226 (match_operand 5 "vector_length_operand" " rK, rK, rK")
8227 (match_operand 6 "const_int_operand" " i, i, i")
8228 (match_operand 7 "const_int_operand" " i, i, i")
8229 (match_operand 8 "const_int_operand" " i, i, i")
8230 (reg:SI VL_REGNUM)
8231 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8232 (unspec:VT
8233 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8234 (match_operand 4 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8235 (mem:BLK (scratch))] UNSPEC_STRIDED)
8236 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8237 "TARGET_VECTOR"
8238 "vlsseg<nf>e<sew>.v\t%0,(%z3),%z4%p1"
8239 [(set_attr "type" "vlsegds")
8240 (set_attr "mode" "<MODE>")])
8242 (define_insn "@pred_strided_store<mode>"
8243 [(set (mem:BLK (scratch))
8244 (unspec:BLK
8245 [(unspec:<VM>
8246 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8247 (match_operand 4 "vector_length_operand" " rK")
8248 (match_operand 5 "const_int_operand" " i")
8249 (reg:SI VL_REGNUM)
8250 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8251 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8252 (match_operand 2 "pmode_reg_or_0_operand" " rJ")
8253 (match_operand:VT 3 "register_operand" " vr")
8254 (mem:BLK (scratch))] UNSPEC_STRIDED))]
8255 "TARGET_VECTOR"
8256 "vssseg<nf>e<sew>.v\t%3,(%z1),%z2%p0"
8257 [(set_attr "type" "vssegts")
8258 (set_attr "mode" "<MODE>")])
8260 (define_insn "@pred_fault_load<mode>"
8261 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8262 (if_then_else:VT
8263 (unspec:<VM>
8264 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8265 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8266 (match_operand 5 "const_int_operand" " i, i, i")
8267 (match_operand 6 "const_int_operand" " i, i, i")
8268 (match_operand 7 "const_int_operand" " i, i, i")
8269 (reg:SI VL_REGNUM)
8270 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8271 (unspec:VT
8272 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8273 (mem:BLK (scratch))] UNSPEC_VLEFF)
8274 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))
8275 (set (reg:SI VL_REGNUM)
8276 (unspec:SI
8277 [(if_then_else:VT
8278 (unspec:<VM>
8279 [(match_dup 1) (match_dup 4) (match_dup 5)
8280 (match_dup 6) (match_dup 7)
8281 (reg:SI VL_REGNUM)
8282 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8283 (unspec:VT
8284 [(match_dup 3) (mem:BLK (scratch))] UNSPEC_VLEFF)
8285 (match_dup 2))] UNSPEC_MODIFY_VL))]
8286 "TARGET_VECTOR"
8287 "vlseg<nf>e<sew>ff.v\t%0,(%z3)%p1"
8288 [(set_attr "type" "vlsegdff")
8289 (set_attr "mode" "<MODE>")])
8291 (define_insn "@pred_indexed_<order>load<V1T:mode><RATIO64I:mode>"
8292 [(set (match_operand:V1T 0 "register_operand" "=&vr, &vr")
8293 (if_then_else:V1T
8294 (unspec:<VM>
8295 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8296 (match_operand 5 "vector_length_operand" " rK, rK")
8297 (match_operand 6 "const_int_operand" " i, i")
8298 (match_operand 7 "const_int_operand" " i, i")
8299 (match_operand 8 "const_int_operand" " i, i")
8300 (reg:SI VL_REGNUM)
8301 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8302 (unspec:V1T
8303 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8304 (mem:BLK (scratch))
8305 (match_operand:RATIO64I 4 "register_operand" " vr, vr")] ORDER)
8306 (match_operand:V1T 2 "vector_merge_operand" " vu, 0")))]
8307 "TARGET_VECTOR"
8308 "vl<order>xseg<nf>ei<RATIO64I:sew>.v\t%0,(%z3),%4%p1"
8309 [(set_attr "type" "vlsegd<order>x")
8310 (set_attr "mode" "<V1T:MODE>")])
8312 (define_insn "@pred_indexed_<order>load<V2T:mode><RATIO32I:mode>"
8313 [(set (match_operand:V2T 0 "register_operand" "=&vr, &vr")
8314 (if_then_else:V2T
8315 (unspec:<VM>
8316 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8317 (match_operand 5 "vector_length_operand" " rK, rK")
8318 (match_operand 6 "const_int_operand" " i, i")
8319 (match_operand 7 "const_int_operand" " i, i")
8320 (match_operand 8 "const_int_operand" " i, i")
8321 (reg:SI VL_REGNUM)
8322 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8323 (unspec:V2T
8324 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8325 (mem:BLK (scratch))
8326 (match_operand:RATIO32I 4 "register_operand" " vr, vr")] ORDER)
8327 (match_operand:V2T 2 "vector_merge_operand" " vu, 0")))]
8328 "TARGET_VECTOR"
8329 "vl<order>xseg<nf>ei<RATIO32I:sew>.v\t%0,(%z3),%4%p1"
8330 [(set_attr "type" "vlsegd<order>x")
8331 (set_attr "mode" "<V2T:MODE>")])
8333 (define_insn "@pred_indexed_<order>load<V4T:mode><RATIO16I:mode>"
8334 [(set (match_operand:V4T 0 "register_operand" "=&vr, &vr")
8335 (if_then_else:V4T
8336 (unspec:<VM>
8337 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8338 (match_operand 5 "vector_length_operand" " rK, rK")
8339 (match_operand 6 "const_int_operand" " i, i")
8340 (match_operand 7 "const_int_operand" " i, i")
8341 (match_operand 8 "const_int_operand" " i, i")
8342 (reg:SI VL_REGNUM)
8343 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8344 (unspec:V4T
8345 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8346 (mem:BLK (scratch))
8347 (match_operand:RATIO16I 4 "register_operand" " vr, vr")] ORDER)
8348 (match_operand:V4T 2 "vector_merge_operand" " vu, 0")))]
8349 "TARGET_VECTOR"
8350 "vl<order>xseg<nf>ei<RATIO16I:sew>.v\t%0,(%z3),%4%p1"
8351 [(set_attr "type" "vlsegd<order>x")
8352 (set_attr "mode" "<V4T:MODE>")])
8354 (define_insn "@pred_indexed_<order>load<V8T:mode><RATIO8I:mode>"
8355 [(set (match_operand:V8T 0 "register_operand" "=&vr, &vr")
8356 (if_then_else:V8T
8357 (unspec:<VM>
8358 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8359 (match_operand 5 "vector_length_operand" " rK, rK")
8360 (match_operand 6 "const_int_operand" " i, i")
8361 (match_operand 7 "const_int_operand" " i, i")
8362 (match_operand 8 "const_int_operand" " i, i")
8363 (reg:SI VL_REGNUM)
8364 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8365 (unspec:V8T
8366 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8367 (mem:BLK (scratch))
8368 (match_operand:RATIO8I 4 "register_operand" " vr, vr")] ORDER)
8369 (match_operand:V8T 2 "vector_merge_operand" " vu, 0")))]
8370 "TARGET_VECTOR"
8371 "vl<order>xseg<nf>ei<RATIO8I:sew>.v\t%0,(%z3),%4%p1"
8372 [(set_attr "type" "vlsegd<order>x")
8373 (set_attr "mode" "<V8T:MODE>")])
8375 (define_insn "@pred_indexed_<order>load<V16T:mode><RATIO4I:mode>"
8376 [(set (match_operand:V16T 0 "register_operand" "=&vr, &vr")
8377 (if_then_else:V16T
8378 (unspec:<VM>
8379 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8380 (match_operand 5 "vector_length_operand" " rK, rK")
8381 (match_operand 6 "const_int_operand" " i, i")
8382 (match_operand 7 "const_int_operand" " i, i")
8383 (match_operand 8 "const_int_operand" " i, i")
8384 (reg:SI VL_REGNUM)
8385 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8386 (unspec:V16T
8387 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8388 (mem:BLK (scratch))
8389 (match_operand:RATIO4I 4 "register_operand" " vr, vr")] ORDER)
8390 (match_operand:V16T 2 "vector_merge_operand" " vu, 0")))]
8391 "TARGET_VECTOR"
8392 "vl<order>xseg<nf>ei<RATIO4I:sew>.v\t%0,(%z3),%4%p1"
8393 [(set_attr "type" "vlsegd<order>x")
8394 (set_attr "mode" "<V16T:MODE>")])
8396 (define_insn "@pred_indexed_<order>load<V32T:mode><RATIO2I:mode>"
8397 [(set (match_operand:V32T 0 "register_operand" "=&vr, &vr")
8398 (if_then_else:V32T
8399 (unspec:<VM>
8400 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8401 (match_operand 5 "vector_length_operand" " rK, rK")
8402 (match_operand 6 "const_int_operand" " i, i")
8403 (match_operand 7 "const_int_operand" " i, i")
8404 (match_operand 8 "const_int_operand" " i, i")
8405 (reg:SI VL_REGNUM)
8406 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8407 (unspec:V32T
8408 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8409 (mem:BLK (scratch))
8410 (match_operand:RATIO2I 4 "register_operand" " vr, vr")] ORDER)
8411 (match_operand:V32T 2 "vector_merge_operand" " vu, 0")))]
8412 "TARGET_VECTOR"
8413 "vl<order>xseg<nf>ei<RATIO2I:sew>.v\t%0,(%z3),%4%p1"
8414 [(set_attr "type" "vlsegd<order>x")
8415 (set_attr "mode" "<V32T:MODE>")])
8417 (define_insn "@pred_indexed_<order>store<V1T:mode><RATIO64I:mode>"
8418 [(set (mem:BLK (scratch))
8419 (unspec:BLK
8420 [(unspec:<VM>
8421 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8422 (match_operand 4 "vector_length_operand" " rK")
8423 (match_operand 5 "const_int_operand" " i")
8424 (reg:SI VL_REGNUM)
8425 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8426 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8427 (match_operand:RATIO64I 2 "register_operand" " vr")
8428 (match_operand:V1T 3 "register_operand" " vr")] ORDER))]
8429 "TARGET_VECTOR"
8430 "vs<order>xseg<nf>ei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
8431 [(set_attr "type" "vssegt<order>x")
8432 (set_attr "mode" "<V1T:MODE>")])
8434 (define_insn "@pred_indexed_<order>store<V2T:mode><RATIO32I:mode>"
8435 [(set (mem:BLK (scratch))
8436 (unspec:BLK
8437 [(unspec:<VM>
8438 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8439 (match_operand 4 "vector_length_operand" " rK")
8440 (match_operand 5 "const_int_operand" " i")
8441 (reg:SI VL_REGNUM)
8442 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8443 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8444 (match_operand:RATIO32I 2 "register_operand" " vr")
8445 (match_operand:V2T 3 "register_operand" " vr")] ORDER))]
8446 "TARGET_VECTOR"
8447 "vs<order>xseg<nf>ei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
8448 [(set_attr "type" "vssegt<order>x")
8449 (set_attr "mode" "<V2T:MODE>")])
8451 (define_insn "@pred_indexed_<order>store<V4T:mode><RATIO16I:mode>"
8452 [(set (mem:BLK (scratch))
8453 (unspec:BLK
8454 [(unspec:<VM>
8455 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8456 (match_operand 4 "vector_length_operand" " rK")
8457 (match_operand 5 "const_int_operand" " i")
8458 (reg:SI VL_REGNUM)
8459 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8460 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8461 (match_operand:RATIO16I 2 "register_operand" " vr")
8462 (match_operand:V4T 3 "register_operand" " vr")] ORDER))]
8463 "TARGET_VECTOR"
8464 "vs<order>xseg<nf>ei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
8465 [(set_attr "type" "vssegt<order>x")
8466 (set_attr "mode" "<V4T:MODE>")])
8468 (define_insn "@pred_indexed_<order>store<V8T:mode><RATIO8I:mode>"
8469 [(set (mem:BLK (scratch))
8470 (unspec:BLK
8471 [(unspec:<VM>
8472 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8473 (match_operand 4 "vector_length_operand" " rK")
8474 (match_operand 5 "const_int_operand" " i")
8475 (reg:SI VL_REGNUM)
8476 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8477 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8478 (match_operand:RATIO8I 2 "register_operand" " vr")
8479 (match_operand:V8T 3 "register_operand" " vr")] ORDER))]
8480 "TARGET_VECTOR"
8481 "vs<order>xseg<nf>ei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
8482 [(set_attr "type" "vssegt<order>x")
8483 (set_attr "mode" "<V8T:MODE>")])
8485 (define_insn "@pred_indexed_<order>store<V16T:mode><RATIO4I:mode>"
8486 [(set (mem:BLK (scratch))
8487 (unspec:BLK
8488 [(unspec:<VM>
8489 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8490 (match_operand 4 "vector_length_operand" " rK")
8491 (match_operand 5 "const_int_operand" " i")
8492 (reg:SI VL_REGNUM)
8493 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8494 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8495 (match_operand:RATIO4I 2 "register_operand" " vr")
8496 (match_operand:V16T 3 "register_operand" " vr")] ORDER))]
8497 "TARGET_VECTOR"
8498 "vs<order>xseg<nf>ei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
8499 [(set_attr "type" "vssegt<order>x")
8500 (set_attr "mode" "<V16T:MODE>")])
8502 (define_insn "@pred_indexed_<order>store<V32T:mode><RATIO2I:mode>"
8503 [(set (mem:BLK (scratch))
8504 (unspec:BLK
8505 [(unspec:<VM>
8506 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8507 (match_operand 4 "vector_length_operand" " rK")
8508 (match_operand 5 "const_int_operand" " i")
8509 (reg:SI VL_REGNUM)
8510 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8511 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8512 (match_operand:RATIO2I 2 "register_operand" " vr")
8513 (match_operand:V32T 3 "register_operand" " vr")] ORDER))]
8514 "TARGET_VECTOR"
8515 "vs<order>xseg<nf>ei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
8516 [(set_attr "type" "vssegt<order>x")
8517 (set_attr "mode" "<V32T:MODE>")])
8519 (include "autovec.md")
8520 (include "autovec-opt.md")