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2008-07-01 Jerry DeLisle <jvdelisle@gcc.gnu.org>
[official-gcc.git] / gcc / config / mips / mips.h
blob781528d01ba844019756cb30e6a46dc94d4f67cb
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
52 PROCESSOR_M4K,
53 PROCESSOR_R3900,
54 PROCESSOR_R6000,
55 PROCESSOR_R4000,
56 PROCESSOR_R4100,
57 PROCESSOR_R4111,
58 PROCESSOR_R4120,
59 PROCESSOR_R4130,
60 PROCESSOR_R4300,
61 PROCESSOR_R4600,
62 PROCESSOR_R4650,
63 PROCESSOR_R5000,
64 PROCESSOR_R5400,
65 PROCESSOR_R5500,
66 PROCESSOR_R7000,
67 PROCESSOR_R8000,
68 PROCESSOR_R9000,
69 PROCESSOR_SB1,
70 PROCESSOR_SB1A,
71 PROCESSOR_SR71000,
72 PROCESSOR_XLR,
73 PROCESSOR_MAX
74 };
75
76 /* Costs of various operations on the different architectures. */
77
78 struct mips_rtx_cost_data
79 {
80 unsigned short fp_add;
81 unsigned short fp_mult_sf;
82 unsigned short fp_mult_df;
83 unsigned short fp_div_sf;
84 unsigned short fp_div_df;
85 unsigned short int_mult_si;
86 unsigned short int_mult_di;
87 unsigned short int_div_si;
88 unsigned short int_div_di;
89 unsigned short branch_cost;
90 unsigned short memory_latency;
91 };
92
93 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
94 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
95 to work on a 64-bit machine. */
96
97 #define ABI_32 0
98 #define ABI_N32 1
99 #define ABI_64 2
100 #define ABI_EABI 3
101 #define ABI_O64 4
102
103 /* Masks that affect tuning.
104
105 PTF_AVOID_BRANCHLIKELY
106 Set if it is usually not profitable to use branch-likely instructions
107 for this target, typically because the branches are always predicted
108 taken and so incur a large overhead when not taken. */
109 #define PTF_AVOID_BRANCHLIKELY 0x1
110
111 /* Information about one recognized processor. Defined here for the
112 benefit of TARGET_CPU_CPP_BUILTINS. */
113 struct mips_cpu_info {
114 /* The 'canonical' name of the processor as far as GCC is concerned.
115 It's typically a manufacturer's prefix followed by a numerical
116 designation. It should be lowercase. */
117 const char *name;
118
119 /* The internal processor number that most closely matches this
120 entry. Several processors can have the same value, if there's no
121 difference between them from GCC's point of view. */
122 enum processor_type cpu;
123
124 /* The ISA level that the processor implements. */
125 int isa;
126
127 /* A mask of PTF_* values. */
128 unsigned int tune_flags;
129 };
130
131 /* Enumerates the setting of the -mcode-readable option. */
132 enum mips_code_readable_setting {
133 CODE_READABLE_NO,
134 CODE_READABLE_PCREL,
135 CODE_READABLE_YES
136 };
137
138 /* Macros to silence warnings about numbers being signed in traditional
139 C and unsigned in ISO C when compiled on 32-bit hosts. */
140
141 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
142 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
143 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
144
145 \f
146 /* Run-time compilation parameters selecting different hardware subsets. */
147
148 /* True if we are generating position-independent VxWorks RTP code. */
149 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
150
151 /* True if the call patterns should be split into a jalr followed by
152 an instruction to restore $gp. It is only safe to split the load
153 from the call when every use of $gp is explicit. */
154
155 #define TARGET_SPLIT_CALLS \
156 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
157
158 /* True if we're generating a form of -mabicalls in which we can use
159 operators like %hi and %lo to refer to locally-binding symbols.
160 We can only do this for -mno-shared, and only then if we can use
161 relocation operations instead of assembly macros. It isn't really
162 worth using absolute sequences for 64-bit symbols because GOT
163 accesses are so much shorter. */
164
165 #define TARGET_ABSOLUTE_ABICALLS \
166 (TARGET_ABICALLS \
167 && !TARGET_SHARED \
168 && TARGET_EXPLICIT_RELOCS \
169 && !ABI_HAS_64BIT_SYMBOLS)
170
171 /* True if we can optimize sibling calls. For simplicity, we only
172 handle cases in which call_insn_operand will reject invalid
173 sibcall addresses. There are two cases in which this isn't true:
174
175 - TARGET_MIPS16. call_insn_operand accepts constant addresses
176 but there is no direct jump instruction. It isn't worth
177 using sibling calls in this case anyway; they would usually
178 be longer than normal calls.
179
180 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
181 accepts global constants, but all sibcalls must be indirect. */
182 #define TARGET_SIBCALLS \
183 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
184
185 /* True if we need to use a global offset table to access some symbols. */
186 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
187
188 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
189 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
190
191 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
192 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
193
194 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
195 This is true for both the PIC and non-PIC VxWorks RTP modes. */
196 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
197
198 /* True if .gpword or .gpdword should be used for switch tables.
199
200 Although GAS does understand .gpdword, the SGI linker mishandles
201 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
202 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
203 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
204
205 /* Generate mips16 code */
206 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
207 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
208 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
209 /* Generate mips16e register save/restore sequences. */
210 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
211
212 /* True if we're generating a form of MIPS16 code in which general
213 text loads are allowed. */
214 #define TARGET_MIPS16_TEXT_LOADS \
215 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
216
217 /* True if we're generating a form of MIPS16 code in which PC-relative
218 loads are allowed. */
219 #define TARGET_MIPS16_PCREL_LOADS \
220 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
221
222 /* Generic ISA defines. */
223 #define ISA_MIPS1 (mips_isa == 1)
224 #define ISA_MIPS2 (mips_isa == 2)
225 #define ISA_MIPS3 (mips_isa == 3)
226 #define ISA_MIPS4 (mips_isa == 4)
227 #define ISA_MIPS32 (mips_isa == 32)
228 #define ISA_MIPS32R2 (mips_isa == 33)
229 #define ISA_MIPS64 (mips_isa == 64)
230
231 /* Architecture target defines. */
232 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
233 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
234 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
235 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
236 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
237 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
238 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
239 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
240 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
241 || mips_arch == PROCESSOR_SB1A)
242 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
243 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
244 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
245 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
246
247 /* Scheduling target defines. */
248 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
249 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
250 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
251 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
252 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
253 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
254 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
255 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
256 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
257 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
258 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
259 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
260 || mips_tune == PROCESSOR_SB1A)
261 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
262 || mips_tune == PROCESSOR_24KF2_1 \
263 || mips_tune == PROCESSOR_24KF1_1)
264 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
265 || mips_tune == PROCESSOR_74KF2_1 \
266 || mips_tune == PROCESSOR_74KF1_1 \
267 || mips_tune == PROCESSOR_74KF3_2)
268 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
269 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
270 || mips_tune == PROCESSOR_LOONGSON_2F)
271
272 /* Whether vector modes and intrinsics for ST Microelectronics
273 Loongson-2E/2F processors should be enabled. In o32 pairs of
274 floating-point registers provide 64-bit values. */
275 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
276 && TARGET_LOONGSON_2EF)
277
278 /* True if the pre-reload scheduler should try to create chains of
279 multiply-add or multiply-subtract instructions. For example,
280 suppose we have:
281
282 t1 = a * b
283 t2 = t1 + c * d
284 t3 = e * f
285 t4 = t3 - g * h
286
287 t1 will have a higher priority than t2 and t3 will have a higher
288 priority than t4. However, before reload, there is no dependence
289 between t1 and t3, and they can often have similar priorities.
290 The scheduler will then tend to prefer:
291
292 t1 = a * b
293 t3 = e * f
294 t2 = t1 + c * d
295 t4 = t3 - g * h
296
297 which stops us from making full use of macc/madd-style instructions.
298 This sort of situation occurs frequently in Fourier transforms and
299 in unrolled loops.
300
301 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
302 queue so that chained multiply-add and multiply-subtract instructions
303 appear ahead of any other instruction that is likely to clobber lo.
304 In the example above, if t2 and t3 become ready at the same time,
305 the code ensures that t2 is scheduled first.
306
307 Multiply-accumulate instructions are a bigger win for some targets
308 than others, so this macro is defined on an opt-in basis. */
309 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
310 || TUNE_MIPS4120 \
311 || TUNE_MIPS4130 \
312 || TUNE_24K)
313
314 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
315 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
316
317 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
318 directly accessible, while the command-line options select
319 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
320 in use. */
321 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
322 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
323
324 /* IRIX specific stuff. */
325 #define TARGET_IRIX 0
326 #define TARGET_IRIX6 0
327
328 /* Define preprocessor macros for the -march and -mtune options.
329 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
330 processor. If INFO's canonical name is "foo", define PREFIX to
331 be "foo", and define an additional macro PREFIX_FOO. */
332 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
333 do \
334 { \
335 char *macro, *p; \
336 \
337 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
338 for (p = macro; *p != 0; p++) \
339 *p = TOUPPER (*p); \
340 \
341 builtin_define (macro); \
342 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
343 free (macro); \
344 } \
345 while (0)
346
347 /* Target CPU builtins. */
348 #define TARGET_CPU_CPP_BUILTINS() \
349 do \
350 { \
351 /* Everyone but IRIX defines this to mips. */ \
352 if (!TARGET_IRIX) \
353 builtin_assert ("machine=mips"); \
354 \
355 builtin_assert ("cpu=mips"); \
356 builtin_define ("__mips__"); \
357 builtin_define ("_mips"); \
358 \
359 /* We do this here because __mips is defined below and so we \
360 can't use builtin_define_std. We don't ever want to define \
361 "mips" for VxWorks because some of the VxWorks headers \
362 construct include filenames from a root directory macro, \
363 an architecture macro and a filename, where the architecture \
364 macro expands to 'mips'. If we define 'mips' to 1, the \
365 architecture macro expands to 1 as well. */ \
366 if (!flag_iso && !TARGET_VXWORKS) \
367 builtin_define ("mips"); \
368 \
369 if (TARGET_64BIT) \
370 builtin_define ("__mips64"); \
371 \
372 if (!TARGET_IRIX) \
373 { \
374 /* Treat _R3000 and _R4000 like register-size \
375 defines, which is how they've historically \
376 been used. */ \
377 if (TARGET_64BIT) \
378 { \
379 builtin_define_std ("R4000"); \
380 builtin_define ("_R4000"); \
381 } \
382 else \
383 { \
384 builtin_define_std ("R3000"); \
385 builtin_define ("_R3000"); \
386 } \
387 } \
388 if (TARGET_FLOAT64) \
389 builtin_define ("__mips_fpr=64"); \
390 else \
391 builtin_define ("__mips_fpr=32"); \
392 \
393 if (TARGET_MIPS16) \
394 builtin_define ("__mips16"); \
395 \
396 if (TARGET_MIPS3D) \
397 builtin_define ("__mips3d"); \
398 \
399 if (TARGET_SMARTMIPS) \
400 builtin_define ("__mips_smartmips"); \
401 \
402 if (TARGET_DSP) \
403 { \
404 builtin_define ("__mips_dsp"); \
405 if (TARGET_DSPR2) \
406 { \
407 builtin_define ("__mips_dspr2"); \
408 builtin_define ("__mips_dsp_rev=2"); \
409 } \
410 else \
411 builtin_define ("__mips_dsp_rev=1"); \
412 } \
413 \
414 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
415 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
416 \
417 if (ISA_MIPS1) \
418 { \
419 builtin_define ("__mips=1"); \
420 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
421 } \
422 else if (ISA_MIPS2) \
423 { \
424 builtin_define ("__mips=2"); \
425 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
426 } \
427 else if (ISA_MIPS3) \
428 { \
429 builtin_define ("__mips=3"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
431 } \
432 else if (ISA_MIPS4) \
433 { \
434 builtin_define ("__mips=4"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
436 } \
437 else if (ISA_MIPS32) \
438 { \
439 builtin_define ("__mips=32"); \
440 builtin_define ("__mips_isa_rev=1"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
442 } \
443 else if (ISA_MIPS32R2) \
444 { \
445 builtin_define ("__mips=32"); \
446 builtin_define ("__mips_isa_rev=2"); \
447 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
448 } \
449 else if (ISA_MIPS64) \
450 { \
451 builtin_define ("__mips=64"); \
452 builtin_define ("__mips_isa_rev=1"); \
453 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
454 } \
455 \
456 switch (mips_abi) \
457 { \
458 case ABI_32: \
459 builtin_define ("_ABIO32=1"); \
460 builtin_define ("_MIPS_SIM=_ABIO32"); \
461 break; \
462 \
463 case ABI_N32: \
464 builtin_define ("_ABIN32=2"); \
465 builtin_define ("_MIPS_SIM=_ABIN32"); \
466 break; \
467 \
468 case ABI_64: \
469 builtin_define ("_ABI64=3"); \
470 builtin_define ("_MIPS_SIM=_ABI64"); \
471 break; \
472 \
473 case ABI_O64: \
474 builtin_define ("_ABIO64=4"); \
475 builtin_define ("_MIPS_SIM=_ABIO64"); \
476 break; \
477 } \
478 \
479 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
480 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
481 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
482 builtin_define_with_int_value ("_MIPS_FPSET", \
483 32 / MAX_FPRS_PER_FMT); \
484 \
485 /* These defines reflect the ABI in use, not whether the \
486 FPU is directly accessible. */ \
487 if (TARGET_HARD_FLOAT_ABI) \
488 builtin_define ("__mips_hard_float"); \
489 else \
490 builtin_define ("__mips_soft_float"); \
491 \
492 if (TARGET_SINGLE_FLOAT) \
493 builtin_define ("__mips_single_float"); \
494 \
495 if (TARGET_PAIRED_SINGLE_FLOAT) \
496 builtin_define ("__mips_paired_single_float"); \
497 \
498 if (TARGET_BIG_ENDIAN) \
499 { \
500 builtin_define_std ("MIPSEB"); \
501 builtin_define ("_MIPSEB"); \
502 } \
503 else \
504 { \
505 builtin_define_std ("MIPSEL"); \
506 builtin_define ("_MIPSEL"); \
507 } \
508 \
509 /* Whether Loongson vector modes are enabled. */ \
510 if (TARGET_LOONGSON_VECTORS) \
511 builtin_define ("__mips_loongson_vector_rev"); \
512 \
513 /* Macros dependent on the C dialect. */ \
514 if (preprocessing_asm_p ()) \
515 { \
516 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
517 builtin_define ("_LANGUAGE_ASSEMBLY"); \
518 } \
519 else if (c_dialect_cxx ()) \
520 { \
521 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
522 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
523 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
524 } \
525 else \
526 { \
527 builtin_define_std ("LANGUAGE_C"); \
528 builtin_define ("_LANGUAGE_C"); \
529 } \
530 if (c_dialect_objc ()) \
531 { \
532 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
533 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
534 /* Bizarre, but needed at least for Irix. */ \
535 builtin_define_std ("LANGUAGE_C"); \
536 builtin_define ("_LANGUAGE_C"); \
537 } \
538 \
539 if (mips_abi == ABI_EABI) \
540 builtin_define ("__mips_eabi"); \
541 } \
542 while (0)
543
544 /* Default target_flags if no switches are specified */
545
546 #ifndef TARGET_DEFAULT
547 #define TARGET_DEFAULT 0
548 #endif
549
550 #ifndef TARGET_CPU_DEFAULT
551 #define TARGET_CPU_DEFAULT 0
552 #endif
553
554 #ifndef TARGET_ENDIAN_DEFAULT
555 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
556 #endif
557
558 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
559 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
560 #endif
561
562 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
563 #ifndef MIPS_ISA_DEFAULT
564 #ifndef MIPS_CPU_STRING_DEFAULT
565 #define MIPS_CPU_STRING_DEFAULT "from-abi"
566 #endif
567 #endif
568
569 #ifdef IN_LIBGCC2
570 #undef TARGET_64BIT
571 /* Make this compile time constant for libgcc2 */
572 #ifdef __mips64
573 #define TARGET_64BIT 1
574 #else
575 #define TARGET_64BIT 0
576 #endif
577 #endif /* IN_LIBGCC2 */
578
579 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
580 when compiled with hardware floating point. This is because MIPS16
581 code cannot save and restore the floating-point registers, which is
582 important if in a mixed MIPS16/non-MIPS16 environment. */
583
584 #ifdef IN_LIBGCC2
585 #if __mips_hard_float
586 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
587 #endif
588 #endif /* IN_LIBGCC2 */
589
590 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
591
592 #ifndef MULTILIB_ENDIAN_DEFAULT
593 #if TARGET_ENDIAN_DEFAULT == 0
594 #define MULTILIB_ENDIAN_DEFAULT "EL"
595 #else
596 #define MULTILIB_ENDIAN_DEFAULT "EB"
597 #endif
598 #endif
599
600 #ifndef MULTILIB_ISA_DEFAULT
601 # if MIPS_ISA_DEFAULT == 1
602 # define MULTILIB_ISA_DEFAULT "mips1"
603 # else
604 # if MIPS_ISA_DEFAULT == 2
605 # define MULTILIB_ISA_DEFAULT "mips2"
606 # else
607 # if MIPS_ISA_DEFAULT == 3
608 # define MULTILIB_ISA_DEFAULT "mips3"
609 # else
610 # if MIPS_ISA_DEFAULT == 4
611 # define MULTILIB_ISA_DEFAULT "mips4"
612 # else
613 # if MIPS_ISA_DEFAULT == 32
614 # define MULTILIB_ISA_DEFAULT "mips32"
615 # else
616 # if MIPS_ISA_DEFAULT == 33
617 # define MULTILIB_ISA_DEFAULT "mips32r2"
618 # else
619 # if MIPS_ISA_DEFAULT == 64
620 # define MULTILIB_ISA_DEFAULT "mips64"
621 # else
622 # define MULTILIB_ISA_DEFAULT "mips1"
623 # endif
624 # endif
625 # endif
626 # endif
627 # endif
628 # endif
629 # endif
630 #endif
631
632 #ifndef MULTILIB_DEFAULTS
633 #define MULTILIB_DEFAULTS \
634 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
635 #endif
636
637 /* We must pass -EL to the linker by default for little endian embedded
638 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
639 linker will default to using big-endian output files. The OUTPUT_FORMAT
640 line must be in the linker script, otherwise -EB/-EL will not work. */
641
642 #ifndef ENDIAN_SPEC
643 #if TARGET_ENDIAN_DEFAULT == 0
644 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
645 #else
646 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
647 #endif
648 #endif
649
650 /* A spec condition that matches all non-mips16 -mips arguments. */
651
652 #define MIPS_ISA_LEVEL_OPTION_SPEC \
653 "mips1|mips2|mips3|mips4|mips32*|mips64*"
654
655 /* A spec condition that matches all non-mips16 architecture arguments. */
656
657 #define MIPS_ARCH_OPTION_SPEC \
658 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
659
660 /* A spec that infers a -mips argument from an -march argument,
661 or injects the default if no architecture is specified. */
662
663 #define MIPS_ISA_LEVEL_SPEC \
664 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
665 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
666 %{march=mips2|march=r6000:-mips2} \
667 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
668 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
669 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
670 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
671 |march=34k*|march=74k*: -mips32r2} \
672 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
673 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
674
675 /* A spec that infers a -mhard-float or -msoft-float setting from an
676 -march argument. Note that soft-float and hard-float code are not
677 link-compatible. */
678
679 #define MIPS_ARCH_FLOAT_SPEC \
680 "%{mhard-float|msoft-float|march=mips*:; \
681 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
682 |march=34kc|march=74kc|march=5kc: -msoft-float; \
683 march=*: -mhard-float}"
684
685 /* A spec condition that matches 32-bit options. It only works if
686 MIPS_ISA_LEVEL_SPEC has been applied. */
687
688 #define MIPS_32BIT_OPTION_SPEC \
689 "mips1|mips2|mips32*|mgp32"
690
691 /* Support for a compile-time default CPU, et cetera. The rules are:
692 --with-arch is ignored if -march is specified or a -mips is specified
693 (other than -mips16).
694 --with-tune is ignored if -mtune is specified.
695 --with-abi is ignored if -mabi is specified.
696 --with-float is ignored if -mhard-float or -msoft-float are
697 specified.
698 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
699 specified. */
700 #define OPTION_DEFAULT_SPECS \
701 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
702 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
703 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
704 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
705 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
706 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }
707
708
709 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
710 && ISA_HAS_COND_TRAP)
711
712 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
713
714 /* True if the ABI can only work with 64-bit integer registers. We
715 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
716 otherwise floating-point registers must also be 64-bit. */
717 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
718
719 /* Likewise for 32-bit regs. */
720 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
721
722 /* True if symbols are 64 bits wide. At present, n64 is the only
723 ABI for which this is true. */
724 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
725
726 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
727 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
728 || ISA_MIPS4 \
729 || ISA_MIPS64)
730
731 /* ISA has branch likely instructions (e.g. mips2). */
732 /* Disable branchlikely for tx39 until compare rewrite. They haven't
733 been generated up to this point. */
734 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
735
736 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
737 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
738 || TARGET_MIPS5400 \
739 || TARGET_MIPS5500 \
740 || TARGET_MIPS7000 \
741 || TARGET_MIPS9000 \
742 || TARGET_MAD \
743 || ISA_MIPS32 \
744 || ISA_MIPS32R2 \
745 || ISA_MIPS64) \
746 && !TARGET_MIPS16)
747
748 /* ISA has the floating-point conditional move instructions introduced
749 in mips4. */
750 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
751 || ISA_MIPS32 \
752 || ISA_MIPS32R2 \
753 || ISA_MIPS64) \
754 && !TARGET_MIPS5500 \
755 && !TARGET_MIPS16)
756
757 /* ISA has the integer conditional move instructions introduced in mips4 and
758 ST Loongson 2E/2F. */
759 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
760
761 /* ISA has LDC1 and SDC1. */
762 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
763
764 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
765 branch on CC, and move (both FP and non-FP) on CC. */
766 #define ISA_HAS_8CC (ISA_MIPS4 \
767 || ISA_MIPS32 \
768 || ISA_MIPS32R2 \
769 || ISA_MIPS64)
770
771 /* This is a catch all for other mips4 instructions: indexed load, the
772 FP madd and msub instructions, and the FP recip and recip sqrt
773 instructions. */
774 #define ISA_HAS_FP4 ((ISA_MIPS4 \
775 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
776 || ISA_MIPS64) \
777 && !TARGET_MIPS16)
778
779 /* ISA has paired-single instructions. */
780 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64)
781
782 /* ISA has conditional trap instructions. */
783 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
784 && !TARGET_MIPS16)
785
786 /* ISA has integer multiply-accumulate instructions, madd and msub. */
787 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
788 || ISA_MIPS32R2 \
789 || ISA_MIPS64) \
790 && !TARGET_MIPS16)
791
792 /* Integer multiply-accumulate instructions should be generated. */
793 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
794
795 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
796 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
797
798 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
799 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
800
801 /* ISA has floating-point nmadd and nmsub instructions
802 'd = -((a * b) [+-] c)'. */
803 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
804 ((ISA_MIPS4 \
805 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
806 || ISA_MIPS64) \
807 && (!TARGET_MIPS5400 || TARGET_MAD) \
808 && !TARGET_MIPS16)
809
810 /* ISA has floating-point nmadd and nmsub instructions
811 'c = -((a * b) [+-] c)'. */
812 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
813 TARGET_LOONGSON_2EF
814
815 /* ISA has count leading zeroes/ones instruction (not implemented). */
816 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
817 || ISA_MIPS32R2 \
818 || ISA_MIPS64) \
819 && !TARGET_MIPS16)
820
821 /* ISA has three operand multiply instructions that put
822 the high part in an accumulator: mulhi or mulhiu. */
823 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
824 || TARGET_MIPS5500 \
825 || TARGET_SR71K) \
826 && !TARGET_MIPS16)
827
828 /* ISA has three operand multiply instructions that
829 negates the result and puts the result in an accumulator. */
830 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
831 || TARGET_MIPS5500 \
832 || TARGET_SR71K) \
833 && !TARGET_MIPS16)
834
835 /* ISA has three operand multiply instructions that subtracts the
836 result from a 4th operand and puts the result in an accumulator. */
837 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
838 || TARGET_MIPS5500 \
839 || TARGET_SR71K) \
840 && !TARGET_MIPS16)
841
842 /* ISA has three operand multiply instructions that the result
843 from a 4th operand and puts the result in an accumulator. */
844 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
845 || TARGET_MIPS4130 \
846 || TARGET_MIPS5400 \
847 || TARGET_MIPS5500 \
848 || TARGET_SR71K) \
849 && !TARGET_MIPS16)
850
851 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
852 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
853 || TARGET_MIPS4130) \
854 && !TARGET_MIPS16)
855
856 /* ISA has the "ror" (rotate right) instructions. */
857 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
858 || TARGET_MIPS5400 \
859 || TARGET_MIPS5500 \
860 || TARGET_SR71K \
861 || TARGET_SMARTMIPS) \
862 && !TARGET_MIPS16)
863
864 /* ISA has data prefetch instructions. This controls use of 'pref'. */
865 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
866 || ISA_MIPS32 \
867 || ISA_MIPS32R2 \
868 || ISA_MIPS64) \
869 && !TARGET_MIPS16)
870
871 /* ISA has data indexed prefetch instructions. This controls use of
872 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
873 (prefx is a cop1x instruction, so can only be used if FP is
874 enabled.) */
875 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
876 || ISA_MIPS32R2 \
877 || ISA_MIPS64) \
878 && !TARGET_MIPS16)
879
880 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
881 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
882 also requires TARGET_DOUBLE_FLOAT. */
883 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
884
885 /* ISA includes the MIPS32r2 seb and seh instructions. */
886 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
887 && !TARGET_MIPS16)
888
889 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
890 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
891 && !TARGET_MIPS16)
892
893 /* ISA has instructions for accessing top part of 64-bit fp regs. */
894 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
895
896 /* ISA has lwxs instruction (load w/scaled index address. */
897 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
898
899 /* The DSP ASE is available. */
900 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
901
902 /* Revision 2 of the DSP ASE is available. */
903 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
904
905 /* True if the result of a load is not available to the next instruction.
906 A nop will then be needed between instructions like "lw $4,..."
907 and "addiu $4,$4,1". */
908 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
909 && !TARGET_MIPS3900 \
910 && !TARGET_MIPS16)
911
912 /* Likewise mtc1 and mfc1. */
913 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
914 && !TARGET_LOONGSON_2EF)
915
916 /* Likewise floating-point comparisons. */
917 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
918 && !TARGET_LOONGSON_2EF)
919
920 /* True if mflo and mfhi can be immediately followed by instructions
921 which write to the HI and LO registers.
922
923 According to MIPS specifications, MIPS ISAs I, II, and III need
924 (at least) two instructions between the reads of HI/LO and
925 instructions which write them, and later ISAs do not. Contradicting
926 the MIPS specifications, some MIPS IV processor user manuals (e.g.
927 the UM for the NEC Vr5000) document needing the instructions between
928 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
929 MIPS64 and later ISAs to have the interlocks, plus any specific
930 earlier-ISA CPUs for which CPU documentation declares that the
931 instructions are really interlocked. */
932 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
933 || ISA_MIPS32R2 \
934 || ISA_MIPS64 \
935 || TARGET_MIPS5500 \
936 || TARGET_LOONGSON_2EF)
937
938 /* ISA includes synci, jr.hb and jalr.hb. */
939 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
940
941 /* ISA includes sync. */
942 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
943 #define GENERATE_SYNC \
944 (target_flags_explicit & MASK_LLSC \
945 ? TARGET_LLSC && !TARGET_MIPS16 \
946 : ISA_HAS_SYNC)
947
948 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
949 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
950 instructions. */
951 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
952 #define GENERATE_LL_SC \
953 (target_flags_explicit & MASK_LLSC \
954 ? TARGET_LLSC && !TARGET_MIPS16 \
955 : ISA_HAS_LL_SC)
956 \f
957 /* Add -G xx support. */
958
959 #undef SWITCH_TAKES_ARG
960 #define SWITCH_TAKES_ARG(CHAR) \
961 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
962
963 #define OVERRIDE_OPTIONS mips_override_options ()
964
965 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
966
967 /* Show we can debug even without a frame pointer. */
968 #define CAN_DEBUG_WITHOUT_FP
969 \f
970 /* Tell collect what flags to pass to nm. */
971 #ifndef NM_FLAGS
972 #define NM_FLAGS "-Bn"
973 #endif
974
975 \f
976 #ifndef MIPS_ABI_DEFAULT
977 #define MIPS_ABI_DEFAULT ABI_32
978 #endif
979
980 /* Use the most portable ABI flag for the ASM specs. */
981
982 #if MIPS_ABI_DEFAULT == ABI_32
983 #define MULTILIB_ABI_DEFAULT "mabi=32"
984 #endif
985
986 #if MIPS_ABI_DEFAULT == ABI_O64
987 #define MULTILIB_ABI_DEFAULT "mabi=o64"
988 #endif
989
990 #if MIPS_ABI_DEFAULT == ABI_N32
991 #define MULTILIB_ABI_DEFAULT "mabi=n32"
992 #endif
993
994 #if MIPS_ABI_DEFAULT == ABI_64
995 #define MULTILIB_ABI_DEFAULT "mabi=64"
996 #endif
997
998 #if MIPS_ABI_DEFAULT == ABI_EABI
999 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1000 #endif
1001
1002 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1003 to the assembler. It may be overridden by subtargets. */
1004 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1005 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1006 %{noasmopt:-O0} \
1007 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1008 #endif
1009
1010 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1011 the assembler. It may be overridden by subtargets.
1012
1013 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1014 COFF debugging info. */
1015
1016 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1017 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1018 %{g} %{g0} %{g1} %{g2} %{g3} \
1019 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1020 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1021 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1022 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1023 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1024 #endif
1025
1026 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1027 overridden by subtargets. */
1028
1029 #ifndef SUBTARGET_ASM_SPEC
1030 #define SUBTARGET_ASM_SPEC ""
1031 #endif
1032
1033 #undef ASM_SPEC
1034 #define ASM_SPEC "\
1035 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1036 %{mips32} %{mips32r2} %{mips64} \
1037 %{mips16} %{mno-mips16:-no-mips16} \
1038 %{mips3d} %{mno-mips3d:-no-mips3d} \
1039 %{mdmx} %{mno-mdmx:-no-mdmx} \
1040 %{mdsp} %{mno-dsp} \
1041 %{mdspr2} %{mno-dspr2} \
1042 %{msmartmips} %{mno-smartmips} \
1043 %{mmt} %{mno-mt} \
1044 %{mfix-vr4120} %{mfix-vr4130} \
1045 %(subtarget_asm_optimizing_spec) \
1046 %(subtarget_asm_debugging_spec) \
1047 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1048 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1049 %{mfp32} %{mfp64} \
1050 %{mshared} %{mno-shared} \
1051 %{msym32} %{mno-sym32} \
1052 %{mtune=*} %{v} \
1053 %(subtarget_asm_spec)"
1054
1055 /* Extra switches sometimes passed to the linker. */
1056 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1057 will interpret it as a -b option. */
1058
1059 #ifndef LINK_SPEC
1060 #define LINK_SPEC "\
1061 %(endian_spec) \
1062 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1063 %{bestGnum} %{shared} %{non_shared}"
1064 #endif /* LINK_SPEC defined */
1065
1066
1067 /* Specs for the compiler proper */
1068
1069 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1070 overridden by subtargets. */
1071 #ifndef SUBTARGET_CC1_SPEC
1072 #define SUBTARGET_CC1_SPEC ""
1073 #endif
1074
1075 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1076
1077 #undef CC1_SPEC
1078 #define CC1_SPEC "\
1079 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1080 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1081 %{save-temps: } \
1082 %(subtarget_cc1_spec)"
1083
1084 /* Preprocessor specs. */
1085
1086 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1087 overridden by subtargets. */
1088 #ifndef SUBTARGET_CPP_SPEC
1089 #define SUBTARGET_CPP_SPEC ""
1090 #endif
1091
1092 #define CPP_SPEC "%(subtarget_cpp_spec)"
1093
1094 /* This macro defines names of additional specifications to put in the specs
1095 that can be used in various specifications like CC1_SPEC. Its definition
1096 is an initializer with a subgrouping for each command option.
1097
1098 Each subgrouping contains a string constant, that defines the
1099 specification name, and a string constant that used by the GCC driver
1100 program.
1101
1102 Do not define this macro if it does not need to do anything. */
1103
1104 #define EXTRA_SPECS \
1105 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1106 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1107 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1108 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1109 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1110 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1111 { "endian_spec", ENDIAN_SPEC }, \
1112 SUBTARGET_EXTRA_SPECS
1113
1114 #ifndef SUBTARGET_EXTRA_SPECS
1115 #define SUBTARGET_EXTRA_SPECS
1116 #endif
1117 \f
1118 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1119 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1120
1121 #ifndef PREFERRED_DEBUGGING_TYPE
1122 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1123 #endif
1124
1125 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1126
1127 /* By default, turn on GDB extensions. */
1128 #define DEFAULT_GDB_EXTENSIONS 1
1129
1130 /* Local compiler-generated symbols must have a prefix that the assembler
1131 understands. By default, this is $, although some targets (e.g.,
1132 NetBSD-ELF) need to override this. */
1133
1134 #ifndef LOCAL_LABEL_PREFIX
1135 #define LOCAL_LABEL_PREFIX "$"
1136 #endif
1137
1138 /* By default on the mips, external symbols do not have an underscore
1139 prepended, but some targets (e.g., NetBSD) require this. */
1140
1141 #ifndef USER_LABEL_PREFIX
1142 #define USER_LABEL_PREFIX ""
1143 #endif
1144
1145 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1146 since the length can run past this up to a continuation point. */
1147 #undef DBX_CONTIN_LENGTH
1148 #define DBX_CONTIN_LENGTH 1500
1149
1150 /* How to renumber registers for dbx and gdb. */
1151 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1152
1153 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1154 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1155
1156 /* The DWARF 2 CFA column which tracks the return address. */
1157 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1158
1159 /* Before the prologue, RA lives in r31. */
1160 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1161
1162 /* Describe how we implement __builtin_eh_return. */
1163 #define EH_RETURN_DATA_REGNO(N) \
1164 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1165
1166 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1167
1168 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1169 The default for this in 64-bit mode is 8, which causes problems with
1170 SFmode register saves. */
1171 #define DWARF_CIE_DATA_ALIGNMENT -4
1172
1173 /* Correct the offset of automatic variables and arguments. Note that
1174 the MIPS debug format wants all automatic variables and arguments
1175 to be in terms of the virtual frame pointer (stack pointer before
1176 any adjustment in the function), while the MIPS 3.0 linker wants
1177 the frame pointer to be the stack pointer after the initial
1178 adjustment. */
1179
1180 #define DEBUGGER_AUTO_OFFSET(X) \
1181 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1182 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1183 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1184 \f
1185 /* Target machine storage layout */
1186
1187 #define BITS_BIG_ENDIAN 0
1188 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1189 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1190
1191 /* Define this to set the endianness to use in libgcc2.c, which can
1192 not depend on target_flags. */
1193 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1194 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1195 #else
1196 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1197 #endif
1198
1199 #define MAX_BITS_PER_WORD 64
1200
1201 /* Width of a word, in units (bytes). */
1202 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1203 #ifndef IN_LIBGCC2
1204 #define MIN_UNITS_PER_WORD 4
1205 #endif
1206
1207 /* For MIPS, width of a floating point register. */
1208 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1209
1210 /* The number of consecutive floating-point registers needed to store the
1211 largest format supported by the FPU. */
1212 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1213
1214 /* The number of consecutive floating-point registers needed to store the
1215 smallest format supported by the FPU. */
1216 #define MIN_FPRS_PER_FMT \
1217 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1218
1219 /* The largest size of value that can be held in floating-point
1220 registers and moved with a single instruction. */
1221 #define UNITS_PER_HWFPVALUE \
1222 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1223
1224 /* The largest size of value that can be held in floating-point
1225 registers. */
1226 #define UNITS_PER_FPVALUE \
1227 (TARGET_SOFT_FLOAT_ABI ? 0 \
1228 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1229 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1230
1231 /* The number of bytes in a double. */
1232 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1233
1234 #define UNITS_PER_SIMD_WORD(MODE) \
1235 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1236
1237 /* Set the sizes of the core types. */
1238 #define SHORT_TYPE_SIZE 16
1239 #define INT_TYPE_SIZE 32
1240 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1241 #define LONG_LONG_TYPE_SIZE 64
1242
1243 #define FLOAT_TYPE_SIZE 32
1244 #define DOUBLE_TYPE_SIZE 64
1245 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1246
1247 /* Define the sizes of fixed-point types. */
1248 #define SHORT_FRACT_TYPE_SIZE 8
1249 #define FRACT_TYPE_SIZE 16
1250 #define LONG_FRACT_TYPE_SIZE 32
1251 #define LONG_LONG_FRACT_TYPE_SIZE 64
1252
1253 #define SHORT_ACCUM_TYPE_SIZE 16
1254 #define ACCUM_TYPE_SIZE 32
1255 #define LONG_ACCUM_TYPE_SIZE 64
1256 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1257 doesn't support 128-bit integers for MIPS32 currently. */
1258 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1259
1260 /* long double is not a fixed mode, but the idea is that, if we
1261 support long double, we also want a 128-bit integer type. */
1262 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1263
1264 #ifdef IN_LIBGCC2
1265 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1266 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1267 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1268 # else
1269 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1270 # endif
1271 #endif
1272
1273 /* Width in bits of a pointer. */
1274 #ifndef POINTER_SIZE
1275 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1276 #endif
1277
1278 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1279 #define PARM_BOUNDARY BITS_PER_WORD
1280
1281 /* Allocation boundary (in *bits*) for the code of a function. */
1282 #define FUNCTION_BOUNDARY 32
1283
1284 /* Alignment of field after `int : 0' in a structure. */
1285 #define EMPTY_FIELD_BOUNDARY 32
1286
1287 /* Every structure's size must be a multiple of this. */
1288 /* 8 is observed right on a DECstation and on riscos 4.02. */
1289 #define STRUCTURE_SIZE_BOUNDARY 8
1290
1291 /* There is no point aligning anything to a rounder boundary than this. */
1292 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1293
1294 /* All accesses must be aligned. */
1295 #define STRICT_ALIGNMENT 1
1296
1297 /* Define this if you wish to imitate the way many other C compilers
1298 handle alignment of bitfields and the structures that contain
1299 them.
1300
1301 The behavior is that the type written for a bit-field (`int',
1302 `short', or other integer type) imposes an alignment for the
1303 entire structure, as if the structure really did contain an
1304 ordinary field of that type. In addition, the bit-field is placed
1305 within the structure so that it would fit within such a field,
1306 not crossing a boundary for it.
1307
1308 Thus, on most machines, a bit-field whose type is written as `int'
1309 would not cross a four-byte boundary, and would force four-byte
1310 alignment for the whole structure. (The alignment used may not
1311 be four bytes; it is controlled by the other alignment
1312 parameters.)
1313
1314 If the macro is defined, its definition should be a C expression;
1315 a nonzero value for the expression enables this behavior. */
1316
1317 #define PCC_BITFIELD_TYPE_MATTERS 1
1318
1319 /* If defined, a C expression to compute the alignment given to a
1320 constant that is being placed in memory. CONSTANT is the constant
1321 and ALIGN is the alignment that the object would ordinarily have.
1322 The value of this macro is used instead of that alignment to align
1323 the object.
1324
1325 If this macro is not defined, then ALIGN is used.
1326
1327 The typical use of this macro is to increase alignment for string
1328 constants to be word aligned so that `strcpy' calls that copy
1329 constants can be done inline. */
1330
1331 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1332 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1333 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1334
1335 /* If defined, a C expression to compute the alignment for a static
1336 variable. TYPE is the data type, and ALIGN is the alignment that
1337 the object would ordinarily have. The value of this macro is used
1338 instead of that alignment to align the object.
1339
1340 If this macro is not defined, then ALIGN is used.
1341
1342 One use of this macro is to increase alignment of medium-size
1343 data to make it all fit in fewer cache lines. Another is to
1344 cause character arrays to be word-aligned so that `strcpy' calls
1345 that copy constants to character arrays can be done inline. */
1346
1347 #undef DATA_ALIGNMENT
1348 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1349 ((((ALIGN) < BITS_PER_WORD) \
1350 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1351 || TREE_CODE (TYPE) == UNION_TYPE \
1352 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1353
1354 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1355 character arrays to be word-aligned so that `strcpy' calls that copy
1356 constants to character arrays can be done inline, and 'strcmp' can be
1357 optimised to use word loads. */
1358 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1359 DATA_ALIGNMENT (TYPE, ALIGN)
1360
1361 #define PAD_VARARGS_DOWN \
1362 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1363
1364 /* Define if operations between registers always perform the operation
1365 on the full register even if a narrower mode is specified. */
1366 #define WORD_REGISTER_OPERATIONS
1367
1368 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1369 moves. All other references are zero extended. */
1370 #define LOAD_EXTEND_OP(MODE) \
1371 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1372 ? SIGN_EXTEND : ZERO_EXTEND)
1373
1374 /* Define this macro if it is advisable to hold scalars in registers
1375 in a wider mode than that declared by the program. In such cases,
1376 the value is constrained to be within the bounds of the declared
1377 type, but kept valid in the wider mode. The signedness of the
1378 extension may differ from that of the type. */
1379
1380 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1381 if (GET_MODE_CLASS (MODE) == MODE_INT \
1382 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1383 { \
1384 if ((MODE) == SImode) \
1385 (UNSIGNEDP) = 0; \
1386 (MODE) = Pmode; \
1387 }
1388
1389 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1390 Extensions of pointers to word_mode must be signed. */
1391 #define POINTERS_EXTEND_UNSIGNED false
1392
1393 /* Define if loading short immediate values into registers sign extends. */
1394 #define SHORT_IMMEDIATES_SIGN_EXTEND
1395
1396 /* The [d]clz instructions have the natural values at 0. */
1397
1398 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1399 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1400 \f
1401 /* Standard register usage. */
1402
1403 /* Number of hardware registers. We have:
1404
1405 - 32 integer registers
1406 - 32 floating point registers
1407 - 8 condition code registers
1408 - 2 accumulator registers (hi and lo)
1409 - 32 registers each for coprocessors 0, 2 and 3
1410 - 3 fake registers:
1411 - ARG_POINTER_REGNUM
1412 - FRAME_POINTER_REGNUM
1413 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1414 - 3 dummy entries that were used at various times in the past.
1415 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1416 - 6 DSP control registers */
1417
1418 #define FIRST_PSEUDO_REGISTER 188
1419
1420 /* By default, fix the kernel registers ($26 and $27), the global
1421 pointer ($28) and the stack pointer ($29). This can change
1422 depending on the command-line options.
1423
1424 Regarding coprocessor registers: without evidence to the contrary,
1425 it's best to assume that each coprocessor register has a unique
1426 use. This can be overridden, in, e.g., mips_override_options or
1427 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1428 for a particular target. */
1429
1430 #define FIXED_REGISTERS \
1431 { \
1432 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1433 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1434 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1435 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1436 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1437 /* COP0 registers */ \
1438 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1439 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1440 /* COP2 registers */ \
1441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1442 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1443 /* COP3 registers */ \
1444 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1445 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1446 /* 6 DSP accumulator registers & 6 control registers */ \
1447 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1448 }
1449
1450
1451 /* Set up this array for o32 by default.
1452
1453 Note that we don't mark $31 as a call-clobbered register. The idea is
1454 that it's really the call instructions themselves which clobber $31.
1455 We don't care what the called function does with it afterwards.
1456
1457 This approach makes it easier to implement sibcalls. Unlike normal
1458 calls, sibcalls don't clobber $31, so the register reaches the
1459 called function in tact. EPILOGUE_USES says that $31 is useful
1460 to the called function. */
1461
1462 #define CALL_USED_REGISTERS \
1463 { \
1464 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1465 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1466 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1467 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1468 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1469 /* COP0 registers */ \
1470 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1471 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1472 /* COP2 registers */ \
1473 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1474 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1475 /* COP3 registers */ \
1476 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1477 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1478 /* 6 DSP accumulator registers & 6 control registers */ \
1479 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1480 }
1481
1482
1483 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1484
1485 #define CALL_REALLY_USED_REGISTERS \
1486 { /* General registers. */ \
1487 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1488 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1489 /* Floating-point registers. */ \
1490 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1491 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1492 /* Others. */ \
1493 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1494 /* COP0 registers */ \
1495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1497 /* COP2 registers */ \
1498 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1499 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1500 /* COP3 registers */ \
1501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1503 /* 6 DSP accumulator registers & 6 control registers */ \
1504 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1505 }
1506
1507 /* Internal macros to classify a register number as to whether it's a
1508 general purpose register, a floating point register, a
1509 multiply/divide register, or a status register. */
1510
1511 #define GP_REG_FIRST 0
1512 #define GP_REG_LAST 31
1513 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1514 #define GP_DBX_FIRST 0
1515
1516 #define FP_REG_FIRST 32
1517 #define FP_REG_LAST 63
1518 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1519 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1520
1521 #define MD_REG_FIRST 64
1522 #define MD_REG_LAST 65
1523 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1524 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1525
1526 /* The DWARF 2 CFA column which tracks the return address from a
1527 signal handler context. This means that to maintain backwards
1528 compatibility, no hard register can be assigned this column if it
1529 would need to be handled by the DWARF unwinder. */
1530 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1531
1532 #define ST_REG_FIRST 67
1533 #define ST_REG_LAST 74
1534 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1535
1536
1537 /* FIXME: renumber. */
1538 #define COP0_REG_FIRST 80
1539 #define COP0_REG_LAST 111
1540 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1541
1542 #define COP2_REG_FIRST 112
1543 #define COP2_REG_LAST 143
1544 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1545
1546 #define COP3_REG_FIRST 144
1547 #define COP3_REG_LAST 175
1548 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1549 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1550 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1551
1552 #define DSP_ACC_REG_FIRST 176
1553 #define DSP_ACC_REG_LAST 181
1554 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1555
1556 #define AT_REGNUM (GP_REG_FIRST + 1)
1557 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1558 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1559
1560 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1561 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1562 should be used instead. */
1563 #define FPSW_REGNUM ST_REG_FIRST
1564
1565 #define GP_REG_P(REGNO) \
1566 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1567 #define M16_REG_P(REGNO) \
1568 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1569 #define FP_REG_P(REGNO) \
1570 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1571 #define MD_REG_P(REGNO) \
1572 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1573 #define ST_REG_P(REGNO) \
1574 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1575 #define COP0_REG_P(REGNO) \
1576 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1577 #define COP2_REG_P(REGNO) \
1578 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1579 #define COP3_REG_P(REGNO) \
1580 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1581 #define ALL_COP_REG_P(REGNO) \
1582 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1583 /* Test if REGNO is one of the 6 new DSP accumulators. */
1584 #define DSP_ACC_REG_P(REGNO) \
1585 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1586 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1587 #define ACC_REG_P(REGNO) \
1588 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1589
1590 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1591
1592 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1593 to initialize the mips16 gp pseudo register. */
1594 #define CONST_GP_P(X) \
1595 (GET_CODE (X) == CONST \
1596 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1597 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1598
1599 /* Return coprocessor number from register number. */
1600
1601 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1602 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1603 : COP3_REG_P (REGNO) ? '3' : '?')
1604
1605
1606 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1607
1608 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1609 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1610
1611 #define MODES_TIEABLE_P mips_modes_tieable_p
1612
1613 /* Register to use for pushing function arguments. */
1614 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1615
1616 /* These two registers don't really exist: they get eliminated to either
1617 the stack or hard frame pointer. */
1618 #define ARG_POINTER_REGNUM 77
1619 #define FRAME_POINTER_REGNUM 78
1620
1621 /* $30 is not available on the mips16, so we use $17 as the frame
1622 pointer. */
1623 #define HARD_FRAME_POINTER_REGNUM \
1624 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1625
1626 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1627
1628 /* Register in which static-chain is passed to a function. */
1629 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1630
1631 /* Registers used as temporaries in prologue/epilogue code. If we're
1632 generating mips16 code, these registers must come from the core set
1633 of 8. The prologue register mustn't conflict with any incoming
1634 arguments, the static chain pointer, or the frame pointer. The
1635 epilogue temporary mustn't conflict with the return registers, the
1636 frame pointer, the EH stack adjustment, or the EH data registers. */
1637
1638 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1639 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1640
1641 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1642 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1643
1644 /* Define this macro if it is as good or better to call a constant
1645 function address than to call an address kept in a register. */
1646 #define NO_FUNCTION_CSE 1
1647
1648 /* The ABI-defined global pointer. Sometimes we use a different
1649 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1650 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1651
1652 /* We normally use $28 as the global pointer. However, when generating
1653 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1654 register instead. They can then avoid saving and restoring $28
1655 and perhaps avoid using a frame at all.
1656
1657 When a leaf function uses something other than $28, mips_expand_prologue
1658 will modify pic_offset_table_rtx in place. Take the register number
1659 from there after reload. */
1660 #define PIC_OFFSET_TABLE_REGNUM \
1661 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1662
1663 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1664 \f
1665 /* Define the classes of registers for register constraints in the
1666 machine description. Also define ranges of constants.
1667
1668 One of the classes must always be named ALL_REGS and include all hard regs.
1669 If there is more than one class, another class must be named NO_REGS
1670 and contain no registers.
1671
1672 The name GENERAL_REGS must be the name of a class (or an alias for
1673 another name such as ALL_REGS). This is the class of registers
1674 that is allowed by "g" or "r" in a register constraint.
1675 Also, registers outside this class are allocated only when
1676 instructions express preferences for them.
1677
1678 The classes must be numbered in nondecreasing order; that is,
1679 a larger-numbered class must never be contained completely
1680 in a smaller-numbered class.
1681
1682 For any two classes, it is very desirable that there be another
1683 class that represents their union. */
1684
1685 enum reg_class
1686 {
1687 NO_REGS, /* no registers in set */
1688 M16_NA_REGS, /* mips16 regs not used to pass args */
1689 M16_REGS, /* mips16 directly accessible registers */
1690 T_REG, /* mips16 T register ($24) */
1691 M16_T_REGS, /* mips16 registers plus T register */
1692 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1693 V1_REG, /* Register $v1 ($3) used for TLS access. */
1694 LEA_REGS, /* Every GPR except $25 */
1695 GR_REGS, /* integer registers */
1696 FP_REGS, /* floating point registers */
1697 MD0_REG, /* first multiply/divide register */
1698 MD1_REG, /* second multiply/divide register */
1699 MD_REGS, /* multiply/divide registers (hi/lo) */
1700 COP0_REGS, /* generic coprocessor classes */
1701 COP2_REGS,
1702 COP3_REGS,
1703 HI_AND_GR_REGS, /* union classes */
1704 LO_AND_GR_REGS,
1705 HI_AND_FP_REGS,
1706 COP0_AND_GR_REGS,
1707 COP2_AND_GR_REGS,
1708 COP3_AND_GR_REGS,
1709 ALL_COP_REGS,
1710 ALL_COP_AND_GR_REGS,
1711 ST_REGS, /* status registers (fp status) */
1712 DSP_ACC_REGS, /* DSP accumulator registers */
1713 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1714 ALL_REGS, /* all registers */
1715 LIM_REG_CLASSES /* max value + 1 */
1716 };
1717
1718 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1719
1720 #define GENERAL_REGS GR_REGS
1721
1722 /* An initializer containing the names of the register classes as C
1723 string constants. These names are used in writing some of the
1724 debugging dumps. */
1725
1726 #define REG_CLASS_NAMES \
1727 { \
1728 "NO_REGS", \
1729 "M16_NA_REGS", \
1730 "M16_REGS", \
1731 "T_REG", \
1732 "M16_T_REGS", \
1733 "PIC_FN_ADDR_REG", \
1734 "V1_REG", \
1735 "LEA_REGS", \
1736 "GR_REGS", \
1737 "FP_REGS", \
1738 "MD0_REG", \
1739 "MD1_REG", \
1740 "MD_REGS", \
1741 /* coprocessor registers */ \
1742 "COP0_REGS", \
1743 "COP2_REGS", \
1744 "COP3_REGS", \
1745 "HI_AND_GR_REGS", \
1746 "LO_AND_GR_REGS", \
1747 "HI_AND_FP_REGS", \
1748 "COP0_AND_GR_REGS", \
1749 "COP2_AND_GR_REGS", \
1750 "COP3_AND_GR_REGS", \
1751 "ALL_COP_REGS", \
1752 "ALL_COP_AND_GR_REGS", \
1753 "ST_REGS", \
1754 "DSP_ACC_REGS", \
1755 "ACC_REGS", \
1756 "ALL_REGS" \
1757 }
1758
1759 /* An initializer containing the contents of the register classes,
1760 as integers which are bit masks. The Nth integer specifies the
1761 contents of class N. The way the integer MASK is interpreted is
1762 that register R is in the class if `MASK & (1 << R)' is 1.
1763
1764 When the machine has more than 32 registers, an integer does not
1765 suffice. Then the integers are replaced by sub-initializers,
1766 braced groupings containing several integers. Each
1767 sub-initializer must be suitable as an initializer for the type
1768 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1769
1770 #define REG_CLASS_CONTENTS \
1771 { \
1772 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1773 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1774 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1775 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1776 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1777 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1778 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1779 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1780 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1781 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1782 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1783 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1784 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1785 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1786 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1787 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1788 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1789 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1790 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1791 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1792 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1793 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1794 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1795 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1796 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1797 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1798 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1799 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1800 }
1801
1802
1803 /* A C expression whose value is a register class containing hard
1804 register REGNO. In general there is more that one such class;
1805 choose a class which is "minimal", meaning that no smaller class
1806 also contains the register. */
1807
1808 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1809
1810 /* A macro whose definition is the name of the class to which a
1811 valid base register must belong. A base register is one used in
1812 an address which is the register value plus a displacement. */
1813
1814 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1815
1816 /* A macro whose definition is the name of the class to which a
1817 valid index register must belong. An index register is one used
1818 in an address where its value is either multiplied by a scale
1819 factor or added to another register (as well as added to a
1820 displacement). */
1821
1822 #define INDEX_REG_CLASS NO_REGS
1823
1824 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1825 registers explicitly used in the rtl to be used as spill registers
1826 but prevents the compiler from extending the lifetime of these
1827 registers. */
1828
1829 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1830
1831 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1832 is the default value (allocate the registers in numeric order). We
1833 define it just so that we can override it for the mips16 target in
1834 ORDER_REGS_FOR_LOCAL_ALLOC. */
1835
1836 #define REG_ALLOC_ORDER \
1837 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1838 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1839 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1840 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1841 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1842 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1843 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1844 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1845 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1846 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1847 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1848 176,177,178,179,180,181,182,183,184,185,186,187 \
1849 }
1850
1851 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1852 to be rearranged based on a particular function. On the mips16, we
1853 want to allocate $24 (T_REG) before other registers for
1854 instructions for which it is possible. */
1855
1856 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1857
1858 /* True if VALUE is an unsigned 6-bit number. */
1859
1860 #define UIMM6_OPERAND(VALUE) \
1861 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1862
1863 /* True if VALUE is a signed 10-bit number. */
1864
1865 #define IMM10_OPERAND(VALUE) \
1866 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1867
1868 /* True if VALUE is a signed 16-bit number. */
1869
1870 #define SMALL_OPERAND(VALUE) \
1871 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1872
1873 /* True if VALUE is an unsigned 16-bit number. */
1874
1875 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1876 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1877
1878 /* True if VALUE can be loaded into a register using LUI. */
1879
1880 #define LUI_OPERAND(VALUE) \
1881 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1882 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1883
1884 /* Return a value X with the low 16 bits clear, and such that
1885 VALUE - X is a signed 16-bit value. */
1886
1887 #define CONST_HIGH_PART(VALUE) \
1888 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1889
1890 #define CONST_LOW_PART(VALUE) \
1891 ((VALUE) - CONST_HIGH_PART (VALUE))
1892
1893 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1894 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1895 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1896
1897 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1898 mips_preferred_reload_class (X, CLASS)
1899
1900 /* The HI and LO registers can only be reloaded via the general
1901 registers. Condition code registers can only be loaded to the
1902 general registers, and from the floating point registers. */
1903
1904 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1905 mips_secondary_reload_class (CLASS, MODE, X, true)
1906 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1907 mips_secondary_reload_class (CLASS, MODE, X, false)
1908
1909 /* Return the maximum number of consecutive registers
1910 needed to represent mode MODE in a register of class CLASS. */
1911
1912 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1913
1914 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1915 mips_cannot_change_mode_class (FROM, TO, CLASS)
1916 \f
1917 /* Stack layout; function entry, exit and calling. */
1918
1919 #define STACK_GROWS_DOWNWARD
1920
1921 /* The offset of the first local variable from the beginning of the frame.
1922 See mips_compute_frame_info for details about the frame layout. */
1923
1924 #define STARTING_FRAME_OFFSET \
1925 (crtl->outgoing_args_size \
1926 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1927
1928 #define RETURN_ADDR_RTX mips_return_addr
1929
1930 /* Since the mips16 ISA mode is encoded in the least-significant bit
1931 of the address, mask it off return addresses for purposes of
1932 finding exception handling regions. */
1933
1934 #define MASK_RETURN_ADDR GEN_INT (-2)
1935
1936
1937 /* Similarly, don't use the least-significant bit to tell pointers to
1938 code from vtable index. */
1939
1940 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1941
1942 /* The eliminations to $17 are only used for mips16 code. See the
1943 definition of HARD_FRAME_POINTER_REGNUM. */
1944
1945 #define ELIMINABLE_REGS \
1946 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1947 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1948 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1949 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1950 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1951 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1952
1953 /* Make sure that we're not trying to eliminate to the wrong hard frame
1954 pointer. */
1955 #define CAN_ELIMINATE(FROM, TO) \
1956 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
1957
1958 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1959 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1960
1961 /* Allocate stack space for arguments at the beginning of each function. */
1962 #define ACCUMULATE_OUTGOING_ARGS 1
1963
1964 /* The argument pointer always points to the first argument. */
1965 #define FIRST_PARM_OFFSET(FNDECL) 0
1966
1967 /* o32 and o64 reserve stack space for all argument registers. */
1968 #define REG_PARM_STACK_SPACE(FNDECL) \
1969 (TARGET_OLDABI \
1970 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1971 : 0)
1972
1973 /* Define this if it is the responsibility of the caller to
1974 allocate the area reserved for arguments passed in registers.
1975 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1976 of this macro is to determine whether the space is included in
1977 `crtl->outgoing_args_size'. */
1978 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1979
1980 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1981 \f
1982 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1983
1984 /* Symbolic macros for the registers used to return integer and floating
1985 point values. */
1986
1987 #define GP_RETURN (GP_REG_FIRST + 2)
1988 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1989
1990 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1991
1992 /* Symbolic macros for the first/last argument registers. */
1993
1994 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1995 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1996 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1997 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1998
1999 #define LIBCALL_VALUE(MODE) \
2000 mips_function_value (NULL_TREE, MODE)
2001
2002 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2003 mips_function_value (VALTYPE, VOIDmode)
2004
2005 /* 1 if N is a possible register number for a function value.
2006 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2007 Currently, R2 and F0 are only implemented here (C has no complex type) */
2008
2009 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2010 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2011 && (N) == FP_RETURN + 2))
2012
2013 /* 1 if N is a possible register number for function argument passing.
2014 We have no FP argument registers when soft-float. When FP registers
2015 are 32 bits, we can't directly reference the odd numbered ones. */
2016
2017 #define FUNCTION_ARG_REGNO_P(N) \
2018 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2019 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2020 && !fixed_regs[N])
2021 \f
2022 /* This structure has to cope with two different argument allocation
2023 schemes. Most MIPS ABIs view the arguments as a structure, of which
2024 the first N words go in registers and the rest go on the stack. If I
2025 < N, the Ith word might go in Ith integer argument register or in a
2026 floating-point register. For these ABIs, we only need to remember
2027 the offset of the current argument into the structure.
2028
2029 The EABI instead allocates the integer and floating-point arguments
2030 separately. The first N words of FP arguments go in FP registers,
2031 the rest go on the stack. Likewise, the first N words of the other
2032 arguments go in integer registers, and the rest go on the stack. We
2033 need to maintain three counts: the number of integer registers used,
2034 the number of floating-point registers used, and the number of words
2035 passed on the stack.
2036
2037 We could keep separate information for the two ABIs (a word count for
2038 the standard ABIs, and three separate counts for the EABI). But it
2039 seems simpler to view the standard ABIs as forms of EABI that do not
2040 allocate floating-point registers.
2041
2042 So for the standard ABIs, the first N words are allocated to integer
2043 registers, and mips_function_arg decides on an argument-by-argument
2044 basis whether that argument should really go in an integer register,
2045 or in a floating-point one. */
2046
2047 typedef struct mips_args {
2048 /* Always true for varargs functions. Otherwise true if at least
2049 one argument has been passed in an integer register. */
2050 int gp_reg_found;
2051
2052 /* The number of arguments seen so far. */
2053 unsigned int arg_number;
2054
2055 /* The number of integer registers used so far. For all ABIs except
2056 EABI, this is the number of words that have been added to the
2057 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2058 unsigned int num_gprs;
2059
2060 /* For EABI, the number of floating-point registers used so far. */
2061 unsigned int num_fprs;
2062
2063 /* The number of words passed on the stack. */
2064 unsigned int stack_words;
2065
2066 /* On the mips16, we need to keep track of which floating point
2067 arguments were passed in general registers, but would have been
2068 passed in the FP regs if this were a 32-bit function, so that we
2069 can move them to the FP regs if we wind up calling a 32-bit
2070 function. We record this information in fp_code, encoded in base
2071 four. A zero digit means no floating point argument, a one digit
2072 means an SFmode argument, and a two digit means a DFmode argument,
2073 and a three digit is not used. The low order digit is the first
2074 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2075 an SFmode argument. ??? A more sophisticated approach will be
2076 needed if MIPS_ABI != ABI_32. */
2077 int fp_code;
2078
2079 /* True if the function has a prototype. */
2080 int prototype;
2081 } CUMULATIVE_ARGS;
2082
2083 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2084 for a call to a function whose data type is FNTYPE.
2085 For a library call, FNTYPE is 0. */
2086
2087 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2088 mips_init_cumulative_args (&CUM, FNTYPE)
2089
2090 /* Update the data in CUM to advance over an argument
2091 of mode MODE and data type TYPE.
2092 (TYPE is null for libcalls where that information may not be available.) */
2093
2094 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2095 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2096
2097 /* Determine where to put an argument to a function.
2098 Value is zero to push the argument on the stack,
2099 or a hard register in which to store the argument.
2100
2101 MODE is the argument's machine mode.
2102 TYPE is the data type of the argument (as a tree).
2103 This is null for libcalls where that information may
2104 not be available.
2105 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2106 the preceding args and about the function being called.
2107 NAMED is nonzero if this argument is a named parameter
2108 (otherwise it is an extra parameter matching an ellipsis). */
2109
2110 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2111 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2112
2113 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2114
2115 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2116 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2117
2118 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2119 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2120
2121 /* True if using EABI and varargs can be passed in floating-point
2122 registers. Under these conditions, we need a more complex form
2123 of va_list, which tracks GPR, FPR and stack arguments separately. */
2124 #define EABI_FLOAT_VARARGS_P \
2125 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2126
2127 \f
2128 /* Say that the epilogue uses the return address register. Note that
2129 in the case of sibcalls, the values "used by the epilogue" are
2130 considered live at the start of the called function.
2131
2132 If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
2133 See the comment above load_call<mode> for details. */
2134 #define EPILOGUE_USES(REGNO) \
2135 ((REGNO) == 31 || (TARGET_USE_GOT && (REGNO) == GOT_VERSION_REGNUM))
2136
2137 /* Treat LOC as a byte offset from the stack pointer and round it up
2138 to the next fully-aligned offset. */
2139 #define MIPS_STACK_ALIGN(LOC) \
2140 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2141
2142 \f
2143 /* Output assembler code to FILE to increment profiler label # LABELNO
2144 for profiling a function entry. */
2145
2146 #define FUNCTION_PROFILER(FILE, LABELNO) \
2147 { \
2148 if (TARGET_MIPS16) \
2149 sorry ("mips16 function profiling"); \
2150 fprintf (FILE, "\t.set\tnoat\n"); \
2151 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2152 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2153 if (!TARGET_NEWABI) \
2154 { \
2155 fprintf (FILE, \
2156 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2157 TARGET_64BIT ? "dsubu" : "subu", \
2158 reg_names[STACK_POINTER_REGNUM], \
2159 reg_names[STACK_POINTER_REGNUM], \
2160 Pmode == DImode ? 16 : 8); \
2161 } \
2162 fprintf (FILE, "\tjal\t_mcount\n"); \
2163 fprintf (FILE, "\t.set\tat\n"); \
2164 }
2165
2166 /* The profiler preserves all interesting registers, including $31. */
2167 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2168
2169 /* No mips port has ever used the profiler counter word, so don't emit it
2170 or the label for it. */
2171
2172 #define NO_PROFILE_COUNTERS 1
2173
2174 /* Define this macro if the code for function profiling should come
2175 before the function prologue. Normally, the profiling code comes
2176 after. */
2177
2178 /* #define PROFILE_BEFORE_PROLOGUE */
2179
2180 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2181 the stack pointer does not matter. The value is tested only in
2182 functions that have frame pointers.
2183 No definition is equivalent to always zero. */
2184
2185 #define EXIT_IGNORE_STACK 1
2186
2187 \f
2188 /* A C statement to output, on the stream FILE, assembler code for a
2189 block of data that contains the constant parts of a trampoline.
2190 This code should not include a label--the label is taken care of
2191 automatically. */
2192
2193 #define TRAMPOLINE_TEMPLATE(STREAM) \
2194 { \
2195 if (ptr_mode == DImode) \
2196 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2197 else \
2198 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2199 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2200 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2201 if (ptr_mode == DImode) \
2202 { \
2203 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2204 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2205 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2206 } \
2207 else \
2208 { \
2209 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2210 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2211 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2212 } \
2213 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2214 if (ptr_mode == DImode) \
2215 { \
2216 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2217 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2218 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2219 } \
2220 else \
2221 { \
2222 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2223 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2224 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2225 } \
2226 }
2227
2228 /* A C expression for the size in bytes of the trampoline, as an
2229 integer. */
2230
2231 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2232
2233 /* Alignment required for trampolines, in bits. */
2234
2235 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2236
2237 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2238 program and data caches. */
2239
2240 #ifndef CACHE_FLUSH_FUNC
2241 #define CACHE_FLUSH_FUNC "_flush_cache"
2242 #endif
2243
2244 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2245 /* Flush both caches. We need to flush the data cache in case \
2246 the system has a write-back cache. */ \
2247 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2248 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2249 GEN_INT (3), TYPE_MODE (integer_type_node))
2250
2251 /* A C statement to initialize the variable parts of a trampoline.
2252 ADDR is an RTX for the address of the trampoline; FNADDR is an
2253 RTX for the address of the nested function; STATIC_CHAIN is an
2254 RTX for the static chain value that should be passed to the
2255 function when it is called. */
2256
2257 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2258 { \
2259 rtx func_addr, chain_addr, end_addr; \
2260 \
2261 func_addr = plus_constant (ADDR, 32); \
2262 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2263 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2264 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2265 end_addr = gen_reg_rtx (Pmode); \
2266 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2267 GEN_INT (TRAMPOLINE_SIZE))); \
2268 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2269 }
2270 \f
2271 /* Addressing modes, and classification of registers for them. */
2272
2273 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2274 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2275 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2276
2277 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2278 and check its validity for a certain class.
2279 We have two alternate definitions for each of them.
2280 The usual definition accepts all pseudo regs; the other rejects them all.
2281 The symbol REG_OK_STRICT causes the latter definition to be used.
2282
2283 Most source files want to accept pseudo regs in the hope that
2284 they will get allocated to the class that the insn wants them to be in.
2285 Some source files that are used after register allocation
2286 need to be strict. */
2287
2288 #ifndef REG_OK_STRICT
2289 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2290 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2291 #else
2292 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2293 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2294 #endif
2295
2296 #define REG_OK_FOR_INDEX_P(X) 0
2297
2298 \f
2299 /* Maximum number of registers that can appear in a valid memory address. */
2300
2301 #define MAX_REGS_PER_ADDRESS 1
2302
2303 #ifdef REG_OK_STRICT
2304 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2305 { \
2306 if (mips_legitimate_address_p (MODE, X, 1)) \
2307 goto ADDR; \
2308 }
2309 #else
2310 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2311 { \
2312 if (mips_legitimate_address_p (MODE, X, 0)) \
2313 goto ADDR; \
2314 }
2315 #endif
2316
2317 /* Check for constness inline but use mips_legitimate_address_p
2318 to check whether a constant really is an address. */
2319
2320 #define CONSTANT_ADDRESS_P(X) \
2321 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2322
2323 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2324
2325 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2326 do { \
2327 if (mips_legitimize_address (&(X), MODE)) \
2328 goto WIN; \
2329 } while (0)
2330
2331
2332 /* A C statement or compound statement with a conditional `goto
2333 LABEL;' executed if memory address X (an RTX) can have different
2334 meanings depending on the machine mode of the memory reference it
2335 is used for.
2336
2337 Autoincrement and autodecrement addresses typically have
2338 mode-dependent effects because the amount of the increment or
2339 decrement is the size of the operand being addressed. Some
2340 machines have other mode-dependent addresses. Many RISC machines
2341 have no mode-dependent addresses.
2342
2343 You may assume that ADDR is a valid address for the machine. */
2344
2345 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2346
2347 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2348 'the start of the function that this code is output in'. */
2349
2350 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2351 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2352 asm_fprintf ((FILE), "%U%s", \
2353 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2354 else \
2355 asm_fprintf ((FILE), "%U%s", (NAME))
2356 \f
2357 /* Flag to mark a function decl symbol that requires a long call. */
2358 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2359 #define SYMBOL_REF_LONG_CALL_P(X) \
2360 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2361
2362 /* True if we're generating a form of MIPS16 code in which jump tables
2363 are stored in the text section and encoded as 16-bit PC-relative
2364 offsets. This is only possible when general text loads are allowed,
2365 since the table access itself will be an "lh" instruction. */
2366 /* ??? 16-bit offsets can overflow in large functions. */
2367 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2368
2369 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2370
2371 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2372
2373 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2374
2375 /* Define this as 1 if `char' should by default be signed; else as 0. */
2376 #ifndef DEFAULT_SIGNED_CHAR
2377 #define DEFAULT_SIGNED_CHAR 1
2378 #endif
2379
2380 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2381 we generally don't want to use them for copying arbitrary data.
2382 A single N-word move is usually the same cost as N single-word moves. */
2383 #define MOVE_MAX UNITS_PER_WORD
2384 #define MAX_MOVE_MAX 8
2385
2386 /* Define this macro as a C expression which is nonzero if
2387 accessing less than a word of memory (i.e. a `char' or a
2388 `short') is no faster than accessing a word of memory, i.e., if
2389 such access require more than one instruction or if there is no
2390 difference in cost between byte and (aligned) word loads.
2391
2392 On RISC machines, it tends to generate better code to define
2393 this as 1, since it avoids making a QI or HI mode register.
2394
2395 But, generating word accesses for -mips16 is generally bad as shifts
2396 (often extended) would be needed for byte accesses. */
2397 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2398
2399 /* Define this to be nonzero if shift instructions ignore all but the low-order
2400 few bits. */
2401 #define SHIFT_COUNT_TRUNCATED 1
2402
2403 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2404 is done just by pretending it is already truncated. */
2405 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2406 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2407
2408
2409 /* Specify the machine mode that pointers have.
2410 After generation of rtl, the compiler makes no further distinction
2411 between pointers and any other objects of this machine mode. */
2412
2413 #ifndef Pmode
2414 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2415 #endif
2416
2417 /* Give call MEMs SImode since it is the "most permissive" mode
2418 for both 32-bit and 64-bit targets. */
2419
2420 #define FUNCTION_MODE SImode
2421
2422 \f
2423 /* A C expression for the cost of moving data from a register in
2424 class FROM to one in class TO. The classes are expressed using
2425 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2426 the default; other values are interpreted relative to that.
2427
2428 It is not required that the cost always equal 2 when FROM is the
2429 same as TO; on some machines it is expensive to move between
2430 registers if they are not general registers.
2431
2432 If reload sees an insn consisting of a single `set' between two
2433 hard registers, and if `REGISTER_MOVE_COST' applied to their
2434 classes returns a value of 2, reload does not check to ensure
2435 that the constraints of the insn are met. Setting a cost of
2436 other than 2 will allow reload to verify that the constraints are
2437 met. You should do this if the `movM' pattern's constraints do
2438 not allow such copying. */
2439
2440 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2441 mips_register_move_cost (MODE, FROM, TO)
2442
2443 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2444 (mips_cost->memory_latency \
2445 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2446
2447 /* Define if copies to/from condition code registers should be avoided.
2448
2449 This is needed for the MIPS because reload_outcc is not complete;
2450 it needs to handle cases where the source is a general or another
2451 condition code register. */
2452 #define AVOID_CCMODE_COPIES
2453
2454 /* A C expression for the cost of a branch instruction. A value of
2455 1 is the default; other values are interpreted relative to that. */
2456
2457 #define BRANCH_COST mips_branch_cost
2458 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2459
2460 /* If defined, modifies the length assigned to instruction INSN as a
2461 function of the context in which it is used. LENGTH is an lvalue
2462 that contains the initially computed length of the insn and should
2463 be updated with the correct length of the insn. */
2464 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2465 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2466
2467 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2468 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2469 its operands. */
2470 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2471 "%*" OPCODE "%?\t" OPERANDS "%/"
2472
2473 /* Return the asm template for a call. INSN is the instruction's mnemonic
2474 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2475 of the target.
2476
2477 When generating GOT code without explicit relocation operators,
2478 all calls should use assembly macros. Otherwise, all indirect
2479 calls should use "jr" or "jalr"; we will arrange to restore $gp
2480 afterwards if necessary. Finally, we can only generate direct
2481 calls for -mabicalls by temporarily switching to non-PIC mode. */
2482 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2483 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2484 ? "%*" INSN "\t%" #OPNO "%/" \
2485 : REG_P (OPERANDS[OPNO]) \
2486 ? "%*" INSN "r\t%" #OPNO "%/" \
2487 : TARGET_ABICALLS \
2488 ? (".option\tpic0\n\t" \
2489 "%*" INSN "\t%" #OPNO "%/\n\t" \
2490 ".option\tpic2") \
2491 : "%*" INSN "\t%" #OPNO "%/")
2492 \f
2493 /* Control the assembler format that we output. */
2494
2495 /* Output to assembler file text saying following lines
2496 may contain character constants, extra white space, comments, etc. */
2497
2498 #ifndef ASM_APP_ON
2499 #define ASM_APP_ON " #APP\n"
2500 #endif
2501
2502 /* Output to assembler file text saying following lines
2503 no longer contain unusual constructs. */
2504
2505 #ifndef ASM_APP_OFF
2506 #define ASM_APP_OFF " #NO_APP\n"
2507 #endif
2508
2509 #define REGISTER_NAMES \
2510 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2511 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2512 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2513 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2514 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2515 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2516 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2517 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2518 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2519 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2520 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2521 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2522 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2523 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2524 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2525 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2526 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2527 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2528 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2529 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2530 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2531 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2532 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2533 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2534
2535 /* List the "software" names for each register. Also list the numerical
2536 names for $fp and $sp. */
2537
2538 #define ADDITIONAL_REGISTER_NAMES \
2539 { \
2540 { "$29", 29 + GP_REG_FIRST }, \
2541 { "$30", 30 + GP_REG_FIRST }, \
2542 { "at", 1 + GP_REG_FIRST }, \
2543 { "v0", 2 + GP_REG_FIRST }, \
2544 { "v1", 3 + GP_REG_FIRST }, \
2545 { "a0", 4 + GP_REG_FIRST }, \
2546 { "a1", 5 + GP_REG_FIRST }, \
2547 { "a2", 6 + GP_REG_FIRST }, \
2548 { "a3", 7 + GP_REG_FIRST }, \
2549 { "t0", 8 + GP_REG_FIRST }, \
2550 { "t1", 9 + GP_REG_FIRST }, \
2551 { "t2", 10 + GP_REG_FIRST }, \
2552 { "t3", 11 + GP_REG_FIRST }, \
2553 { "t4", 12 + GP_REG_FIRST }, \
2554 { "t5", 13 + GP_REG_FIRST }, \
2555 { "t6", 14 + GP_REG_FIRST }, \
2556 { "t7", 15 + GP_REG_FIRST }, \
2557 { "s0", 16 + GP_REG_FIRST }, \
2558 { "s1", 17 + GP_REG_FIRST }, \
2559 { "s2", 18 + GP_REG_FIRST }, \
2560 { "s3", 19 + GP_REG_FIRST }, \
2561 { "s4", 20 + GP_REG_FIRST }, \
2562 { "s5", 21 + GP_REG_FIRST }, \
2563 { "s6", 22 + GP_REG_FIRST }, \
2564 { "s7", 23 + GP_REG_FIRST }, \
2565 { "t8", 24 + GP_REG_FIRST }, \
2566 { "t9", 25 + GP_REG_FIRST }, \
2567 { "k0", 26 + GP_REG_FIRST }, \
2568 { "k1", 27 + GP_REG_FIRST }, \
2569 { "gp", 28 + GP_REG_FIRST }, \
2570 { "sp", 29 + GP_REG_FIRST }, \
2571 { "fp", 30 + GP_REG_FIRST }, \
2572 { "ra", 31 + GP_REG_FIRST }, \
2573 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2574 }
2575
2576 /* This is meant to be redefined in the host dependent files. It is a
2577 set of alternative names and regnums for mips coprocessors. */
2578
2579 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2580
2581 #define PRINT_OPERAND mips_print_operand
2582 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2583 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2584
2585 /* A C statement, to be executed after all slot-filler instructions
2586 have been output. If necessary, call `dbr_sequence_length' to
2587 determine the number of slots filled in a sequence (zero if not
2588 currently outputting a sequence), to decide how many no-ops to
2589 output, or whatever.
2590
2591 Don't define this macro if it has nothing to do, but it is
2592 helpful in reading assembly output if the extent of the delay
2593 sequence is made explicit (e.g. with white space).
2594
2595 Note that output routines for instructions with delay slots must
2596 be prepared to deal with not being output as part of a sequence
2597 (i.e. when the scheduling pass is not run, or when no slot
2598 fillers could be found.) The variable `final_sequence' is null
2599 when not processing a sequence, otherwise it contains the
2600 `sequence' rtx being output. */
2601
2602 #define DBR_OUTPUT_SEQEND(STREAM) \
2603 do \
2604 { \
2605 if (set_nomacro > 0 && --set_nomacro == 0) \
2606 fputs ("\t.set\tmacro\n", STREAM); \
2607 \
2608 if (set_noreorder > 0 && --set_noreorder == 0) \
2609 fputs ("\t.set\treorder\n", STREAM); \
2610 \
2611 fputs ("\n", STREAM); \
2612 } \
2613 while (0)
2614
2615 /* How to tell the debugger about changes of source files. */
2616 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2617
2618 /* mips-tfile does not understand .stabd directives. */
2619 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2620 dbxout_begin_stabn_sline (LINE); \
2621 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2622 } while (0)
2623
2624 /* Use .loc directives for SDB line numbers. */
2625 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2626 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2627
2628 /* The MIPS implementation uses some labels for its own purpose. The
2629 following lists what labels are created, and are all formed by the
2630 pattern $L[a-z].*. The machine independent portion of GCC creates
2631 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2632
2633 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2634 $Lb[0-9]+ Begin blocks for MIPS debug support
2635 $Lc[0-9]+ Label for use in s<xx> operation.
2636 $Le[0-9]+ End blocks for MIPS debug support */
2637
2638 #undef ASM_DECLARE_OBJECT_NAME
2639 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2640 mips_declare_object (STREAM, NAME, "", ":\n")
2641
2642 /* Globalizing directive for a label. */
2643 #define GLOBAL_ASM_OP "\t.globl\t"
2644
2645 /* This says how to define a global common symbol. */
2646
2647 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2648
2649 /* This says how to define a local common symbol (i.e., not visible to
2650 linker). */
2651
2652 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2653 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2654 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2655 #endif
2656
2657 /* This says how to output an external. It would be possible not to
2658 output anything and let undefined symbol become external. However
2659 the assembler uses length information on externals to allocate in
2660 data/sdata bss/sbss, thereby saving exec time. */
2661
2662 #undef ASM_OUTPUT_EXTERNAL
2663 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2664 mips_output_external(STREAM,DECL,NAME)
2665
2666 /* This is how to declare a function name. The actual work of
2667 emitting the label is moved to function_prologue, so that we can
2668 get the line number correctly emitted before the .ent directive,
2669 and after any .file directives. Define as empty so that the function
2670 is not declared before the .ent directive elsewhere. */
2671
2672 #undef ASM_DECLARE_FUNCTION_NAME
2673 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2674
2675 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2676 #define FUNCTION_NAME_ALREADY_DECLARED 0
2677 #endif
2678
2679 /* This is how to store into the string LABEL
2680 the symbol_ref name of an internal numbered label where
2681 PREFIX is the class of label and NUM is the number within the class.
2682 This is suitable for output with `assemble_name'. */
2683
2684 #undef ASM_GENERATE_INTERNAL_LABEL
2685 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2686 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2687
2688 /* This is how to output an element of a case-vector that is absolute. */
2689
2690 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2691 fprintf (STREAM, "\t%s\t%sL%d\n", \
2692 ptr_mode == DImode ? ".dword" : ".word", \
2693 LOCAL_LABEL_PREFIX, \
2694 VALUE)
2695
2696 /* This is how to output an element of a case-vector. We can make the
2697 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2698 is supported. */
2699
2700 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2701 do { \
2702 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2703 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2704 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2705 else if (TARGET_GPWORD) \
2706 fprintf (STREAM, "\t%s\t%sL%d\n", \
2707 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2708 LOCAL_LABEL_PREFIX, VALUE); \
2709 else if (TARGET_RTP_PIC) \
2710 { \
2711 /* Make the entry relative to the start of the function. */ \
2712 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2713 fprintf (STREAM, "\t%s\t%sL%d-", \
2714 Pmode == DImode ? ".dword" : ".word", \
2715 LOCAL_LABEL_PREFIX, VALUE); \
2716 assemble_name (STREAM, XSTR (fnsym, 0)); \
2717 fprintf (STREAM, "\n"); \
2718 } \
2719 else \
2720 fprintf (STREAM, "\t%s\t%sL%d\n", \
2721 ptr_mode == DImode ? ".dword" : ".word", \
2722 LOCAL_LABEL_PREFIX, VALUE); \
2723 } while (0)
2724
2725 /* This is how to output an assembler line
2726 that says to advance the location counter
2727 to a multiple of 2**LOG bytes. */
2728
2729 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2730 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2731
2732 /* This is how to output an assembler line to advance the location
2733 counter by SIZE bytes. */
2734
2735 #undef ASM_OUTPUT_SKIP
2736 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2737 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2738
2739 /* This is how to output a string. */
2740 #undef ASM_OUTPUT_ASCII
2741 #define ASM_OUTPUT_ASCII mips_output_ascii
2742
2743 /* Output #ident as a in the read-only data section. */
2744 #undef ASM_OUTPUT_IDENT
2745 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2746 { \
2747 const char *p = STRING; \
2748 int size = strlen (p) + 1; \
2749 switch_to_section (readonly_data_section); \
2750 assemble_string (p, size); \
2751 }
2752 \f
2753 /* Default to -G 8 */
2754 #ifndef MIPS_DEFAULT_GVALUE
2755 #define MIPS_DEFAULT_GVALUE 8
2756 #endif
2757
2758 /* Define the strings to put out for each section in the object file. */
2759 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2760 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2761
2762 #undef READONLY_DATA_SECTION_ASM_OP
2763 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2764 \f
2765 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2766 do \
2767 { \
2768 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2769 TARGET_64BIT ? "daddiu" : "addiu", \
2770 reg_names[STACK_POINTER_REGNUM], \
2771 reg_names[STACK_POINTER_REGNUM], \
2772 TARGET_64BIT ? "sd" : "sw", \
2773 reg_names[REGNO], \
2774 reg_names[STACK_POINTER_REGNUM]); \
2775 } \
2776 while (0)
2777
2778 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2779 do \
2780 { \
2781 if (! set_noreorder) \
2782 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2783 \
2784 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2785 TARGET_64BIT ? "ld" : "lw", \
2786 reg_names[REGNO], \
2787 reg_names[STACK_POINTER_REGNUM], \
2788 TARGET_64BIT ? "daddu" : "addu", \
2789 reg_names[STACK_POINTER_REGNUM], \
2790 reg_names[STACK_POINTER_REGNUM]); \
2791 \
2792 if (! set_noreorder) \
2793 fprintf (STREAM, "\t.set\treorder\n"); \
2794 } \
2795 while (0)
2796
2797 /* How to start an assembler comment.
2798 The leading space is important (the mips native assembler requires it). */
2799 #ifndef ASM_COMMENT_START
2800 #define ASM_COMMENT_START " #"
2801 #endif
2802 \f
2803 /* Default definitions for size_t and ptrdiff_t. We must override the
2804 definitions from ../svr4.h on mips-*-linux-gnu. */
2805
2806 #undef SIZE_TYPE
2807 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2808
2809 #undef PTRDIFF_TYPE
2810 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2811
2812 /* The maximum number of bytes that can be copied by one iteration of
2813 a movmemsi loop; see mips_block_move_loop. */
2814 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2815 (UNITS_PER_WORD * 4)
2816
2817 /* The maximum number of bytes that can be copied by a straight-line
2818 implementation of movmemsi; see mips_block_move_straight. We want
2819 to make sure that any loop-based implementation will iterate at
2820 least twice. */
2821 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2822 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2823
2824 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2825 values were determined experimentally by benchmarking with CSiBE.
2826 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2827 for o32 where we have to restore $gp afterwards as well as make an
2828 indirect call), but in practice, bumping this up higher for
2829 TARGET_ABICALLS doesn't make much difference to code size. */
2830
2831 #define MIPS_CALL_RATIO 8
2832
2833 /* Any loop-based implementation of movmemsi will have at least
2834 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2835 moves, so allow individual copies of fewer elements.
2836
2837 When movmemsi is not available, use a value approximating
2838 the length of a memcpy call sequence, so that move_by_pieces
2839 will generate inline code if it is shorter than a function call.
2840 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2841 we'll have to generate a load/store pair for each, halve the
2842 value of MIPS_CALL_RATIO to take that into account. */
2843
2844 #define MOVE_RATIO \
2845 (HAVE_movmemsi \
2846 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2847 : MIPS_CALL_RATIO / 2)
2848
2849 /* movmemsi is meant to generate code that is at least as good as
2850 move_by_pieces. However, movmemsi effectively uses a by-pieces
2851 implementation both for moves smaller than a word and for word-aligned
2852 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2853 allow the tree-level optimisers to do such moves by pieces, as it
2854 often exposes other optimization opportunities. We might as well
2855 continue to use movmemsi at the rtl level though, as it produces
2856 better code when scheduling is disabled (such as at -O). */
2857
2858 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2859 (HAVE_movmemsi \
2860 ? (!currently_expanding_to_rtl \
2861 && ((ALIGN) < BITS_PER_WORD \
2862 ? (SIZE) < UNITS_PER_WORD \
2863 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2864 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2865 < (unsigned int) MOVE_RATIO))
2866
2867 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2868 of the length of a memset call, but use the default otherwise. */
2869
2870 #define CLEAR_RATIO \
2871 (optimize_size ? MIPS_CALL_RATIO : 15)
2872
2873 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2874 optimizing for size adjust the ratio to account for the overhead of
2875 loading the constant and replicating it across the word. */
2876
2877 #define SET_RATIO \
2878 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2879
2880 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2881 in that case each word takes 3 insns (lui, ori, sw), or more in
2882 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2883 and let the move_by_pieces code copy the string from read-only
2884 memory. In the future, this could be tuned further for multi-issue
2885 CPUs that can issue stores down one pipe and arithmetic instructions
2886 down another; in that case, the lui/ori/sw combination would be a
2887 win for long enough strings. */
2888
2889 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2890 \f
2891 #ifndef __mips16
2892 /* Since the bits of the _init and _fini function is spread across
2893 many object files, each potentially with its own GP, we must assume
2894 we need to load our GP. We don't preserve $gp or $ra, since each
2895 init/fini chunk is supposed to initialize $gp, and crti/crtn
2896 already take care of preserving $ra and, when appropriate, $gp. */
2897 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2898 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2899 asm (SECTION_OP "\n\
2900 .set noreorder\n\
2901 bal 1f\n\
2902 nop\n\
2903 1: .cpload $31\n\
2904 .set reorder\n\
2905 jal " USER_LABEL_PREFIX #FUNC "\n\
2906 " TEXT_SECTION_ASM_OP);
2907 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2908 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2909 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2910 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2911 asm (SECTION_OP "\n\
2912 .set noreorder\n\
2913 bal 1f\n\
2914 nop\n\
2915 1: .set reorder\n\
2916 .cpsetup $31, $2, 1b\n\
2917 jal " USER_LABEL_PREFIX #FUNC "\n\
2918 " TEXT_SECTION_ASM_OP);
2919 #endif
2920 #endif
2921
2922 #ifndef HAVE_AS_TLS
2923 #define HAVE_AS_TLS 0
2924 #endif
2925
2926 /* Return an asm string that atomically:
2927
2928 - Compares memory reference %1 to register %2 and, if they are
2929 equal, changes %1 to %3.
2930
2931 - Sets register %0 to the old value of memory reference %1.
2932
2933 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
2934 and OP is the instruction that should be used to load %3 into a
2935 register. */
2936 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
2937 "%(%<%[%|sync\n" \
2938 "1:\tll" SUFFIX "\t%0,%1\n" \
2939 "\tbne\t%0,%z2,2f\n" \
2940 "\t" OP "\t%@,%3\n" \
2941 "\tsc" SUFFIX "\t%@,%1\n" \
2942 "\tbeq\t%@,%.,1b\n" \
2943 "\tnop\n" \
2944 "\tsync%-%]%>%)\n" \
2945 "2:\n"
2946
2947 /* Return an asm string that atomically:
2948
2949 - Given that %2 contains a bit mask and %3 the inverted mask and
2950 that %4 and %5 have already been ANDed with %2.
2951
2952 - Compares the bits in memory reference %1 selected by mask %2 to
2953 register %4 and, if they are equal, changes the selected bits
2954 in memory to %5.
2955
2956 - Sets register %0 to the old value of memory reference %1.
2957
2958 OPS are the instructions needed to OR %5 with %@. */
2959 #define MIPS_COMPARE_AND_SWAP_12(OPS) \
2960 "%(%<%[%|sync\n" \
2961 "1:\tll\t%0,%1\n" \
2962 "\tand\t%@,%0,%2\n" \
2963 "\tbne\t%@,%z4,2f\n" \
2964 "\tand\t%@,%0,%3\n" \
2965 OPS \
2966 "\tsc\t%@,%1\n" \
2967 "\tbeq\t%@,%.,1b\n" \
2968 "\tnop\n" \
2969 "\tsync%-%]%>%)\n" \
2970 "2:\n"
2971
2972 #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
2973 #define MIPS_COMPARE_AND_SWAP_12_NONZERO_OP "\tor\t%@,%@,%5\n"
2974
2975
2976 /* Return an asm string that atomically:
2977
2978 - Sets memory reference %0 to %0 INSN %1.
2979
2980 SUFFIX is the suffix that should be added to "ll" and "sc"
2981 instructions. */
2982 #define MIPS_SYNC_OP(SUFFIX, INSN) \
2983 "%(%<%[%|sync\n" \
2984 "1:\tll" SUFFIX "\t%@,%0\n" \
2985 "\t" INSN "\t%@,%@,%1\n" \
2986 "\tsc" SUFFIX "\t%@,%0\n" \
2987 "\tbeq\t%@,%.,1b\n" \
2988 "\tnop\n" \
2989 "\tsync%-%]%>%)"
2990
2991 /* Return an asm string that atomically:
2992
2993 - Given that %1 contains a bit mask and %2 the inverted mask and
2994 that %3 has already been ANDed with %1.
2995
2996 - Sets the selected bits of memory reference %0 to %0 INSN %3.
2997
2998 - Uses scratch register %4.
2999
3000 NOT_OP are the optional instructions to do a bit-wise not
3001 operation in conjunction with an AND INSN to generate a sync_nand
3002 operation. */
3003 #define MIPS_SYNC_OP_12(INSN, NOT_OP) \
3004 "%(%<%[%|sync\n" \
3005 "1:\tll\t%4,%0\n" \
3006 "\tand\t%@,%4,%2\n" \
3007 NOT_OP \
3008 "\t" INSN "\t%4,%4,%z3\n" \
3009 "\tand\t%4,%4,%1\n" \
3010 "\tor\t%@,%@,%4\n" \
3011 "\tsc\t%@,%0\n" \
3012 "\tbeq\t%@,%.,1b\n" \
3013 "\tnop\n" \
3014 "\tsync%-%]%>%)"
3015
3016 #define MIPS_SYNC_OP_12_NOT_NOP ""
3017 #define MIPS_SYNC_OP_12_NOT_NOT "\tnor\t%4,%4,%.\n"
3018
3019 /* Return an asm string that atomically:
3020
3021 - Given that %2 contains a bit mask and %3 the inverted mask and
3022 that %4 has already been ANDed with %2.
3023
3024 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3025
3026 - Sets %0 to the original value of %1.
3027
3028 - Uses scratch register %5.
3029
3030 NOT_OP are the optional instructions to do a bit-wise not
3031 operation in conjunction with an AND INSN to generate a sync_nand
3032 operation.
3033
3034 REG is used in conjunction with NOT_OP and is used to select the
3035 register operated on by the INSN. */
3036 #define MIPS_SYNC_OLD_OP_12(INSN, NOT_OP, REG) \
3037 "%(%<%[%|sync\n" \
3038 "1:\tll\t%0,%1\n" \
3039 "\tand\t%@,%0,%3\n" \
3040 NOT_OP \
3041 "\t" INSN "\t%5," REG ",%z4\n" \
3042 "\tand\t%5,%5,%2\n" \
3043 "\tor\t%@,%@,%5\n" \
3044 "\tsc\t%@,%1\n" \
3045 "\tbeq\t%@,%.,1b\n" \
3046 "\tnop\n" \
3047 "\tsync%-%]%>%)"
3048
3049 #define MIPS_SYNC_OLD_OP_12_NOT_NOP ""
3050 #define MIPS_SYNC_OLD_OP_12_NOT_NOP_REG "%0"
3051 #define MIPS_SYNC_OLD_OP_12_NOT_NOT "\tnor\t%5,%0,%.\n"
3052 #define MIPS_SYNC_OLD_OP_12_NOT_NOT_REG "%5"
3053
3054 /* Return an asm string that atomically:
3055
3056 - Given that %2 contains a bit mask and %3 the inverted mask and
3057 that %4 has already been ANDed with %2.
3058
3059 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3060
3061 - Sets %0 to the new value of %1.
3062
3063 NOT_OP are the optional instructions to do a bit-wise not
3064 operation in conjunction with an AND INSN to generate a sync_nand
3065 operation. */
3066 #define MIPS_SYNC_NEW_OP_12(INSN, NOT_OP) \
3067 "%(%<%[%|sync\n" \
3068 "1:\tll\t%0,%1\n" \
3069 "\tand\t%@,%0,%3\n" \
3070 NOT_OP \
3071 "\t" INSN "\t%0,%0,%z4\n" \
3072 "\tand\t%0,%0,%2\n" \
3073 "\tor\t%@,%@,%0\n" \
3074 "\tsc\t%@,%1\n" \
3075 "\tbeq\t%@,%.,1b\n" \
3076 "\tnop\n" \
3077 "\tsync%-%]%>%)"
3078
3079 #define MIPS_SYNC_NEW_OP_12_NOT_NOP ""
3080 #define MIPS_SYNC_NEW_OP_12_NOT_NOT "\tnor\t%0,%0,%.\n"
3081
3082 /* Return an asm string that atomically:
3083
3084 - Sets memory reference %1 to %1 INSN %2.
3085
3086 - Sets register %0 to the old value of memory reference %1.
3087
3088 SUFFIX is the suffix that should be added to "ll" and "sc"
3089 instructions. */
3090 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
3091 "%(%<%[%|sync\n" \
3092 "1:\tll" SUFFIX "\t%0,%1\n" \
3093 "\t" INSN "\t%@,%0,%2\n" \
3094 "\tsc" SUFFIX "\t%@,%1\n" \
3095 "\tbeq\t%@,%.,1b\n" \
3096 "\tnop\n" \
3097 "\tsync%-%]%>%)"
3098
3099 /* Return an asm string that atomically:
3100
3101 - Sets memory reference %1 to %1 INSN %2.
3102
3103 - Sets register %0 to the new value of memory reference %1.
3104
3105 SUFFIX is the suffix that should be added to "ll" and "sc"
3106 instructions. */
3107 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3108 "%(%<%[%|sync\n" \
3109 "1:\tll" SUFFIX "\t%0,%1\n" \
3110 "\t" INSN "\t%@,%0,%2\n" \
3111 "\tsc" SUFFIX "\t%@,%1\n" \
3112 "\tbeq\t%@,%.,1b\n" \
3113 "\t" INSN "\t%0,%0,%2\n" \
3114 "\tsync%-%]%>%)"
3115
3116 /* Return an asm string that atomically:
3117
3118 - Sets memory reference %0 to ~%0 AND %1.
3119
3120 SUFFIX is the suffix that should be added to "ll" and "sc"
3121 instructions. INSN is the and instruction needed to and a register
3122 with %2. */
3123 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3124 "%(%<%[%|sync\n" \
3125 "1:\tll" SUFFIX "\t%@,%0\n" \
3126 "\tnor\t%@,%@,%.\n" \
3127 "\t" INSN "\t%@,%@,%1\n" \
3128 "\tsc" SUFFIX "\t%@,%0\n" \
3129 "\tbeq\t%@,%.,1b\n" \
3130 "\tnop\n" \
3131 "\tsync%-%]%>%)"
3132
3133 /* Return an asm string that atomically:
3134
3135 - Sets memory reference %1 to ~%1 AND %2.
3136
3137 - Sets register %0 to the old value of memory reference %1.
3138
3139 SUFFIX is the suffix that should be added to "ll" and "sc"
3140 instructions. INSN is the and instruction needed to and a register
3141 with %2. */
3142 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3143 "%(%<%[%|sync\n" \
3144 "1:\tll" SUFFIX "\t%0,%1\n" \
3145 "\tnor\t%@,%0,%.\n" \
3146 "\t" INSN "\t%@,%@,%2\n" \
3147 "\tsc" SUFFIX "\t%@,%1\n" \
3148 "\tbeq\t%@,%.,1b\n" \
3149 "\tnop\n" \
3150 "\tsync%-%]%>%)"
3151
3152 /* Return an asm string that atomically:
3153
3154 - Sets memory reference %1 to ~%1 AND %2.
3155
3156 - Sets register %0 to the new value of memory reference %1.
3157
3158 SUFFIX is the suffix that should be added to "ll" and "sc"
3159 instructions. INSN is the and instruction needed to and a register
3160 with %2. */
3161 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3162 "%(%<%[%|sync\n" \
3163 "1:\tll" SUFFIX "\t%0,%1\n" \
3164 "\tnor\t%0,%0,%.\n" \
3165 "\t" INSN "\t%@,%0,%2\n" \
3166 "\tsc" SUFFIX "\t%@,%1\n" \
3167 "\tbeq\t%@,%.,1b\n" \
3168 "\t" INSN "\t%0,%0,%2\n" \
3169 "\tsync%-%]%>%)"
3170
3171 /* Return an asm string that atomically:
3172
3173 - Sets memory reference %1 to %2.
3174
3175 - Sets register %0 to the old value of memory reference %1.
3176
3177 SUFFIX is the suffix that should be added to "ll" and "sc"
3178 instructions. OP is the and instruction that should be used to
3179 load %2 into a register. */
3180 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3181 "%(%<%[%|\n" \
3182 "1:\tll" SUFFIX "\t%0,%1\n" \
3183 "\t" OP "\t%@,%2\n" \
3184 "\tsc" SUFFIX "\t%@,%1\n" \
3185 "\tbeq\t%@,%.,1b\n" \
3186 "\tnop\n" \
3187 "\tsync%-%]%>%)"
3188
3189 /* Return an asm string that atomically:
3190
3191 - Given that %2 contains an inclusive mask, %3 and exclusive mask
3192 and %4 has already been ANDed with the inclusive mask.
3193
3194 - Sets bits selected by the inclusive mask of memory reference %1
3195 to %4.
3196
3197 - Sets register %0 to the old value of memory reference %1.
3198
3199 OPS are the instructions needed to OR %4 with %@.
3200
3201 Operand %2 is unused, but needed as to give the test_and_set_12
3202 insn the five operands expected by the expander. */
3203 #define MIPS_SYNC_EXCHANGE_12(OPS) \
3204 "%(%<%[%|\n" \
3205 "1:\tll\t%0,%1\n" \
3206 "\tand\t%@,%0,%3\n" \
3207 OPS \
3208 "\tsc\t%@,%1\n" \
3209 "\tbeq\t%@,%.,1b\n" \
3210 "\tnop\n" \
3211 "\tsync%-%]%>%)"
3212
3213 #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
3214 #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
3215
3216 #ifndef USED_FOR_TARGET
3217 extern const enum reg_class mips_regno_to_class[];
3218 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3219 extern bool mips_print_operand_punct[256];
3220 extern const char *current_function_file; /* filename current function is in */
3221 extern int num_source_filenames; /* current .file # */
3222 extern int set_noreorder; /* # of nested .set noreorder's */
3223 extern int set_nomacro; /* # of nested .set nomacro's */
3224 extern int mips_dbx_regno[];
3225 extern int mips_dwarf_regno[];
3226 extern bool mips_split_p[];
3227 extern GTY(()) rtx cmp_operands[2];
3228 extern enum processor_type mips_arch; /* which cpu to codegen for */
3229 extern enum processor_type mips_tune; /* which cpu to schedule for */
3230 extern int mips_isa; /* architectural level */
3231 extern int mips_abi; /* which ABI to use */
3232 extern const struct mips_cpu_info *mips_arch_info;
3233 extern const struct mips_cpu_info *mips_tune_info;
3234 extern const struct mips_rtx_cost_data *mips_cost;
3235 extern enum mips_code_readable_setting mips_code_readable;
3236 #endif
3237
3238 /* Enable querying of DFA units. */
3239 #define CPU_UNITS_QUERY 1
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