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* target.h (enum opt_levels, struct default_options): New.
[official-gcc.git] / gcc / config / mips / mips.h
blob1b4747f7b59264f49985734f8fd87f36f9f09b3a
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 #ifdef GENERATOR_FILE
30 /* This is used in some insn conditions, so needs to be declared, but
31 does not need to be defined. */
32 extern int target_flags_explicit;
33 #endif
34
35 /* MIPS external variables defined in mips.c. */
36
37 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
38 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
39 to work on a 64-bit machine. */
40
41 #define ABI_32 0
42 #define ABI_N32 1
43 #define ABI_64 2
44 #define ABI_EABI 3
45 #define ABI_O64 4
46
47 /* Masks that affect tuning.
48
49 PTF_AVOID_BRANCHLIKELY
50 Set if it is usually not profitable to use branch-likely instructions
51 for this target, typically because the branches are always predicted
52 taken and so incur a large overhead when not taken. */
53 #define PTF_AVOID_BRANCHLIKELY 0x1
54
55 /* Information about one recognized processor. Defined here for the
56 benefit of TARGET_CPU_CPP_BUILTINS. */
57 struct mips_cpu_info {
58 /* The 'canonical' name of the processor as far as GCC is concerned.
59 It's typically a manufacturer's prefix followed by a numerical
60 designation. It should be lowercase. */
61 const char *name;
62
63 /* The internal processor number that most closely matches this
64 entry. Several processors can have the same value, if there's no
65 difference between them from GCC's point of view. */
66 enum processor cpu;
67
68 /* The ISA level that the processor implements. */
69 int isa;
70
71 /* A mask of PTF_* values. */
72 unsigned int tune_flags;
73 };
74
75 /* Enumerates the setting of the -mcode-readable option. */
76 enum mips_code_readable_setting {
77 CODE_READABLE_NO,
78 CODE_READABLE_PCREL,
79 CODE_READABLE_YES
80 };
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* True if the output file is marked as ".abicalls; .option pic0"
96 (-call_nonpic). */
97 #define TARGET_ABICALLS_PIC0 \
98 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
99
100 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
101 #define TARGET_ABICALLS_PIC2 \
102 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
103
104 /* True if the call patterns should be split into a jalr followed by
105 an instruction to restore $gp. It is only safe to split the load
106 from the call when every use of $gp is explicit.
107
108 See mips_must_initialize_gp_p for details about how we manage the
109 global pointer. */
110
111 #define TARGET_SPLIT_CALLS \
112 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
113
114 /* True if we're generating a form of -mabicalls in which we can use
115 operators like %hi and %lo to refer to locally-binding symbols.
116 We can only do this for -mno-shared, and only then if we can use
117 relocation operations instead of assembly macros. It isn't really
118 worth using absolute sequences for 64-bit symbols because GOT
119 accesses are so much shorter. */
120
121 #define TARGET_ABSOLUTE_ABICALLS \
122 (TARGET_ABICALLS \
123 && !TARGET_SHARED \
124 && TARGET_EXPLICIT_RELOCS \
125 && !ABI_HAS_64BIT_SYMBOLS)
126
127 /* True if we can optimize sibling calls. For simplicity, we only
128 handle cases in which call_insn_operand will reject invalid
129 sibcall addresses. There are two cases in which this isn't true:
130
131 - TARGET_MIPS16. call_insn_operand accepts constant addresses
132 but there is no direct jump instruction. It isn't worth
133 using sibling calls in this case anyway; they would usually
134 be longer than normal calls.
135
136 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
137 accepts global constants, but all sibcalls must be indirect. */
138 #define TARGET_SIBCALLS \
139 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
140
141 /* True if we need to use a global offset table to access some symbols. */
142 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
143
144 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
145 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
146
147 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
148 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
149
150 /* True if we should use .cprestore to store to the cprestore slot.
151
152 We continue to use .cprestore for explicit-reloc code so that JALs
153 inside inline asms will work correctly. */
154 #define TARGET_CPRESTORE_DIRECTIVE \
155 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
156
157 /* True if we can use the J and JAL instructions. */
158 #define TARGET_ABSOLUTE_JUMPS \
159 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
160
161 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
162 This is true for both the PIC and non-PIC VxWorks RTP modes. */
163 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
164
165 /* True if .gpword or .gpdword should be used for switch tables.
166
167 Although GAS does understand .gpdword, the SGI linker mishandles
168 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
169 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
170 #define TARGET_GPWORD \
171 (TARGET_ABICALLS \
172 && !TARGET_ABSOLUTE_ABICALLS \
173 && !(mips_abi == ABI_64 && TARGET_IRIX6))
174
175 /* True if the output must have a writable .eh_frame.
176 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
177 #ifdef HAVE_LD_PERSONALITY_RELAXATION
178 #define TARGET_WRITABLE_EH_FRAME 0
179 #else
180 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
181 #endif
182
183 /* Generate mips16 code */
184 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
185 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
186 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
187 /* Generate mips16e register save/restore sequences. */
188 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
189
190 /* True if we're generating a form of MIPS16 code in which general
191 text loads are allowed. */
192 #define TARGET_MIPS16_TEXT_LOADS \
193 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
194
195 /* True if we're generating a form of MIPS16 code in which PC-relative
196 loads are allowed. */
197 #define TARGET_MIPS16_PCREL_LOADS \
198 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
199
200 /* Generic ISA defines. */
201 #define ISA_MIPS1 (mips_isa == 1)
202 #define ISA_MIPS2 (mips_isa == 2)
203 #define ISA_MIPS3 (mips_isa == 3)
204 #define ISA_MIPS4 (mips_isa == 4)
205 #define ISA_MIPS32 (mips_isa == 32)
206 #define ISA_MIPS32R2 (mips_isa == 33)
207 #define ISA_MIPS64 (mips_isa == 64)
208 #define ISA_MIPS64R2 (mips_isa == 65)
209
210 /* Architecture target defines. */
211 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
212 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
213 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
214 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
215 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
216 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
217 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
218 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
219 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
220 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
221 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
222 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
223 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
224 || mips_arch == PROCESSOR_SB1A)
225 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
226
227 /* Scheduling target defines. */
228 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
229 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
230 || mips_tune == PROCESSOR_24KF2_1 \
231 || mips_tune == PROCESSOR_24KF1_1)
232 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
233 || mips_tune == PROCESSOR_74KF2_1 \
234 || mips_tune == PROCESSOR_74KF1_1 \
235 || mips_tune == PROCESSOR_74KF3_2)
236 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
237 || mips_tune == PROCESSOR_LOONGSON_2F)
238 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
239 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
240 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
241 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
242 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
243 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
244 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
245 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
246 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
247 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
248 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
249 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
250 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
251 || mips_tune == PROCESSOR_SB1A)
252
253 /* Whether vector modes and intrinsics for ST Microelectronics
254 Loongson-2E/2F processors should be enabled. In o32 pairs of
255 floating-point registers provide 64-bit values. */
256 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
257 && TARGET_LOONGSON_2EF)
258
259 /* True if the pre-reload scheduler should try to create chains of
260 multiply-add or multiply-subtract instructions. For example,
261 suppose we have:
262
263 t1 = a * b
264 t2 = t1 + c * d
265 t3 = e * f
266 t4 = t3 - g * h
267
268 t1 will have a higher priority than t2 and t3 will have a higher
269 priority than t4. However, before reload, there is no dependence
270 between t1 and t3, and they can often have similar priorities.
271 The scheduler will then tend to prefer:
272
273 t1 = a * b
274 t3 = e * f
275 t2 = t1 + c * d
276 t4 = t3 - g * h
277
278 which stops us from making full use of macc/madd-style instructions.
279 This sort of situation occurs frequently in Fourier transforms and
280 in unrolled loops.
281
282 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
283 queue so that chained multiply-add and multiply-subtract instructions
284 appear ahead of any other instruction that is likely to clobber lo.
285 In the example above, if t2 and t3 become ready at the same time,
286 the code ensures that t2 is scheduled first.
287
288 Multiply-accumulate instructions are a bigger win for some targets
289 than others, so this macro is defined on an opt-in basis. */
290 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
291 || TUNE_MIPS4120 \
292 || TUNE_MIPS4130 \
293 || TUNE_24K)
294
295 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
296 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
297
298 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
299 directly accessible, while the command-line options select
300 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
301 in use. */
302 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
303 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
304
305 /* False if SC acts as a memory barrier with respect to itself,
306 otherwise a SYNC will be emitted after SC for atomic operations
307 that require ordering between the SC and following loads and
308 stores. It does not tell anything about ordering of loads and
309 stores prior to and following the SC, only about the SC itself and
310 those loads and stores follow it. */
311 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON)
312
313 /* IRIX specific stuff. */
314 #define TARGET_IRIX6 0
315
316 /* Define preprocessor macros for the -march and -mtune options.
317 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
318 processor. If INFO's canonical name is "foo", define PREFIX to
319 be "foo", and define an additional macro PREFIX_FOO. */
320 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
321 do \
322 { \
323 char *macro, *p; \
324 \
325 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
326 for (p = macro; *p != 0; p++) \
327 *p = TOUPPER (*p); \
328 \
329 builtin_define (macro); \
330 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
331 free (macro); \
332 } \
333 while (0)
334
335 /* Target CPU builtins. */
336 #define TARGET_CPU_CPP_BUILTINS() \
337 do \
338 { \
339 /* Everyone but IRIX defines this to mips. */ \
340 if (!TARGET_IRIX6) \
341 builtin_assert ("machine=mips"); \
342 \
343 builtin_assert ("cpu=mips"); \
344 builtin_define ("__mips__"); \
345 builtin_define ("_mips"); \
346 \
347 /* We do this here because __mips is defined below and so we \
348 can't use builtin_define_std. We don't ever want to define \
349 "mips" for VxWorks because some of the VxWorks headers \
350 construct include filenames from a root directory macro, \
351 an architecture macro and a filename, where the architecture \
352 macro expands to 'mips'. If we define 'mips' to 1, the \
353 architecture macro expands to 1 as well. */ \
354 if (!flag_iso && !TARGET_VXWORKS) \
355 builtin_define ("mips"); \
356 \
357 if (TARGET_64BIT) \
358 builtin_define ("__mips64"); \
359 \
360 if (!TARGET_IRIX6) \
361 { \
362 /* Treat _R3000 and _R4000 like register-size \
363 defines, which is how they've historically \
364 been used. */ \
365 if (TARGET_64BIT) \
366 { \
367 builtin_define_std ("R4000"); \
368 builtin_define ("_R4000"); \
369 } \
370 else \
371 { \
372 builtin_define_std ("R3000"); \
373 builtin_define ("_R3000"); \
374 } \
375 } \
376 if (TARGET_FLOAT64) \
377 builtin_define ("__mips_fpr=64"); \
378 else \
379 builtin_define ("__mips_fpr=32"); \
380 \
381 if (mips_base_mips16) \
382 builtin_define ("__mips16"); \
383 \
384 if (TARGET_MIPS3D) \
385 builtin_define ("__mips3d"); \
386 \
387 if (TARGET_SMARTMIPS) \
388 builtin_define ("__mips_smartmips"); \
389 \
390 if (TARGET_DSP) \
391 { \
392 builtin_define ("__mips_dsp"); \
393 if (TARGET_DSPR2) \
394 { \
395 builtin_define ("__mips_dspr2"); \
396 builtin_define ("__mips_dsp_rev=2"); \
397 } \
398 else \
399 builtin_define ("__mips_dsp_rev=1"); \
400 } \
401 \
402 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
403 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
404 \
405 if (ISA_MIPS1) \
406 { \
407 builtin_define ("__mips=1"); \
408 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
409 } \
410 else if (ISA_MIPS2) \
411 { \
412 builtin_define ("__mips=2"); \
413 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
414 } \
415 else if (ISA_MIPS3) \
416 { \
417 builtin_define ("__mips=3"); \
418 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
419 } \
420 else if (ISA_MIPS4) \
421 { \
422 builtin_define ("__mips=4"); \
423 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
424 } \
425 else if (ISA_MIPS32) \
426 { \
427 builtin_define ("__mips=32"); \
428 builtin_define ("__mips_isa_rev=1"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
430 } \
431 else if (ISA_MIPS32R2) \
432 { \
433 builtin_define ("__mips=32"); \
434 builtin_define ("__mips_isa_rev=2"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
436 } \
437 else if (ISA_MIPS64) \
438 { \
439 builtin_define ("__mips=64"); \
440 builtin_define ("__mips_isa_rev=1"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
442 } \
443 else if (ISA_MIPS64R2) \
444 { \
445 builtin_define ("__mips=64"); \
446 builtin_define ("__mips_isa_rev=2"); \
447 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
448 } \
449 \
450 switch (mips_abi) \
451 { \
452 case ABI_32: \
453 builtin_define ("_ABIO32=1"); \
454 builtin_define ("_MIPS_SIM=_ABIO32"); \
455 break; \
456 \
457 case ABI_N32: \
458 builtin_define ("_ABIN32=2"); \
459 builtin_define ("_MIPS_SIM=_ABIN32"); \
460 break; \
461 \
462 case ABI_64: \
463 builtin_define ("_ABI64=3"); \
464 builtin_define ("_MIPS_SIM=_ABI64"); \
465 break; \
466 \
467 case ABI_O64: \
468 builtin_define ("_ABIO64=4"); \
469 builtin_define ("_MIPS_SIM=_ABIO64"); \
470 break; \
471 } \
472 \
473 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
474 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
475 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
476 builtin_define_with_int_value ("_MIPS_FPSET", \
477 32 / MAX_FPRS_PER_FMT); \
478 \
479 /* These defines reflect the ABI in use, not whether the \
480 FPU is directly accessible. */ \
481 if (TARGET_NO_FLOAT) \
482 builtin_define ("__mips_no_float"); \
483 else if (TARGET_HARD_FLOAT_ABI) \
484 builtin_define ("__mips_hard_float"); \
485 else \
486 builtin_define ("__mips_soft_float"); \
487 \
488 if (TARGET_SINGLE_FLOAT) \
489 builtin_define ("__mips_single_float"); \
490 \
491 if (TARGET_PAIRED_SINGLE_FLOAT) \
492 builtin_define ("__mips_paired_single_float"); \
493 \
494 if (TARGET_BIG_ENDIAN) \
495 { \
496 builtin_define_std ("MIPSEB"); \
497 builtin_define ("_MIPSEB"); \
498 } \
499 else \
500 { \
501 builtin_define_std ("MIPSEL"); \
502 builtin_define ("_MIPSEL"); \
503 } \
504 \
505 /* Whether calls should go through $25. The separate __PIC__ \
506 macro indicates whether abicalls code might use a GOT. */ \
507 if (TARGET_ABICALLS) \
508 builtin_define ("__mips_abicalls"); \
509 \
510 /* Whether Loongson vector modes are enabled. */ \
511 if (TARGET_LOONGSON_VECTORS) \
512 builtin_define ("__mips_loongson_vector_rev"); \
513 \
514 /* Historical Octeon macro. */ \
515 if (TARGET_OCTEON) \
516 builtin_define ("__OCTEON__"); \
517 \
518 /* Macros dependent on the C dialect. */ \
519 if (preprocessing_asm_p ()) \
520 { \
521 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
522 builtin_define ("_LANGUAGE_ASSEMBLY"); \
523 } \
524 else if (c_dialect_cxx ()) \
525 { \
526 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
527 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
528 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
529 } \
530 else \
531 { \
532 builtin_define_std ("LANGUAGE_C"); \
533 builtin_define ("_LANGUAGE_C"); \
534 } \
535 if (c_dialect_objc ()) \
536 { \
537 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
538 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
539 /* Bizarre, but needed at least for Irix. */ \
540 builtin_define_std ("LANGUAGE_C"); \
541 builtin_define ("_LANGUAGE_C"); \
542 } \
543 \
544 if (mips_abi == ABI_EABI) \
545 builtin_define ("__mips_eabi"); \
546 \
547 if (TARGET_CACHE_BUILTIN) \
548 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
549 } \
550 while (0)
551
552 /* Default target_flags if no switches are specified */
553
554 #ifndef TARGET_DEFAULT
555 #define TARGET_DEFAULT 0
556 #endif
557
558 #ifndef TARGET_CPU_DEFAULT
559 #define TARGET_CPU_DEFAULT 0
560 #endif
561
562 #ifndef TARGET_ENDIAN_DEFAULT
563 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
564 #endif
565
566 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
567 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
568 #endif
569
570 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
571 #ifndef MIPS_ISA_DEFAULT
572 #ifndef MIPS_CPU_STRING_DEFAULT
573 #define MIPS_CPU_STRING_DEFAULT "from-abi"
574 #endif
575 #endif
576
577 #ifdef IN_LIBGCC2
578 #undef TARGET_64BIT
579 /* Make this compile time constant for libgcc2 */
580 #ifdef __mips64
581 #define TARGET_64BIT 1
582 #else
583 #define TARGET_64BIT 0
584 #endif
585 #endif /* IN_LIBGCC2 */
586
587 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
588 when compiled with hardware floating point. This is because MIPS16
589 code cannot save and restore the floating-point registers, which is
590 important if in a mixed MIPS16/non-MIPS16 environment. */
591
592 #ifdef IN_LIBGCC2
593 #if __mips_hard_float
594 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
595 #endif
596 #endif /* IN_LIBGCC2 */
597
598 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
599
600 #ifndef MULTILIB_ENDIAN_DEFAULT
601 #if TARGET_ENDIAN_DEFAULT == 0
602 #define MULTILIB_ENDIAN_DEFAULT "EL"
603 #else
604 #define MULTILIB_ENDIAN_DEFAULT "EB"
605 #endif
606 #endif
607
608 #ifndef MULTILIB_ISA_DEFAULT
609 # if MIPS_ISA_DEFAULT == 1
610 # define MULTILIB_ISA_DEFAULT "mips1"
611 # else
612 # if MIPS_ISA_DEFAULT == 2
613 # define MULTILIB_ISA_DEFAULT "mips2"
614 # else
615 # if MIPS_ISA_DEFAULT == 3
616 # define MULTILIB_ISA_DEFAULT "mips3"
617 # else
618 # if MIPS_ISA_DEFAULT == 4
619 # define MULTILIB_ISA_DEFAULT "mips4"
620 # else
621 # if MIPS_ISA_DEFAULT == 32
622 # define MULTILIB_ISA_DEFAULT "mips32"
623 # else
624 # if MIPS_ISA_DEFAULT == 33
625 # define MULTILIB_ISA_DEFAULT "mips32r2"
626 # else
627 # if MIPS_ISA_DEFAULT == 64
628 # define MULTILIB_ISA_DEFAULT "mips64"
629 # else
630 # if MIPS_ISA_DEFAULT == 65
631 # define MULTILIB_ISA_DEFAULT "mips64r2"
632 # else
633 # define MULTILIB_ISA_DEFAULT "mips1"
634 # endif
635 # endif
636 # endif
637 # endif
638 # endif
639 # endif
640 # endif
641 # endif
642 #endif
643
644 #ifndef MIPS_ABI_DEFAULT
645 #define MIPS_ABI_DEFAULT ABI_32
646 #endif
647
648 /* Use the most portable ABI flag for the ASM specs. */
649
650 #if MIPS_ABI_DEFAULT == ABI_32
651 #define MULTILIB_ABI_DEFAULT "mabi=32"
652 #endif
653
654 #if MIPS_ABI_DEFAULT == ABI_O64
655 #define MULTILIB_ABI_DEFAULT "mabi=o64"
656 #endif
657
658 #if MIPS_ABI_DEFAULT == ABI_N32
659 #define MULTILIB_ABI_DEFAULT "mabi=n32"
660 #endif
661
662 #if MIPS_ABI_DEFAULT == ABI_64
663 #define MULTILIB_ABI_DEFAULT "mabi=64"
664 #endif
665
666 #if MIPS_ABI_DEFAULT == ABI_EABI
667 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
668 #endif
669
670 #ifndef MULTILIB_DEFAULTS
671 #define MULTILIB_DEFAULTS \
672 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
673 #endif
674
675 /* We must pass -EL to the linker by default for little endian embedded
676 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
677 linker will default to using big-endian output files. The OUTPUT_FORMAT
678 line must be in the linker script, otherwise -EB/-EL will not work. */
679
680 #ifndef ENDIAN_SPEC
681 #if TARGET_ENDIAN_DEFAULT == 0
682 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
683 #else
684 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
685 #endif
686 #endif
687
688 /* A spec condition that matches all non-mips16 -mips arguments. */
689
690 #define MIPS_ISA_LEVEL_OPTION_SPEC \
691 "mips1|mips2|mips3|mips4|mips32*|mips64*"
692
693 /* A spec condition that matches all non-mips16 architecture arguments. */
694
695 #define MIPS_ARCH_OPTION_SPEC \
696 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
697
698 /* A spec that infers a -mips argument from an -march argument,
699 or injects the default if no architecture is specified. */
700
701 #define MIPS_ISA_LEVEL_SPEC \
702 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
703 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
704 %{march=mips2|march=r6000:-mips2} \
705 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
706 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
707 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
708 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
709 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
710 |march=34k*|march=74k*|march=1004k*: -mips32r2} \
711 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
712 |march=xlr: -mips64} \
713 %{march=mips64r2|march=octeon: -mips64r2} \
714 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
715
716 /* A spec that infers a -mhard-float or -msoft-float setting from an
717 -march argument. Note that soft-float and hard-float code are not
718 link-compatible. */
719
720 #define MIPS_ARCH_FLOAT_SPEC \
721 "%{mhard-float|msoft-float|march=mips*:; \
722 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
723 |march=34kc|march=74kc|march=1004kc|march=5kc \
724 |march=octeon|march=xlr: -msoft-float; \
725 march=*: -mhard-float}"
726
727 /* A spec condition that matches 32-bit options. It only works if
728 MIPS_ISA_LEVEL_SPEC has been applied. */
729
730 #define MIPS_32BIT_OPTION_SPEC \
731 "mips1|mips2|mips32*|mgp32"
732
733 #if MIPS_ABI_DEFAULT == ABI_O64 \
734 || MIPS_ABI_DEFAULT == ABI_N32 \
735 || MIPS_ABI_DEFAULT == ABI_64
736 #define OPT_ARCH64 "mabi=32|mgp32:;"
737 #define OPT_ARCH32 "mabi=32|mgp32"
738 #else
739 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
740 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
741 #endif
742
743 /* Support for a compile-time default CPU, et cetera. The rules are:
744 --with-arch is ignored if -march is specified or a -mips is specified
745 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
746 --with-tune is ignored if -mtune is specified; likewise
747 --with-tune-32 and --with-tune-64.
748 --with-abi is ignored if -mabi is specified.
749 --with-float is ignored if -mhard-float or -msoft-float are
750 specified.
751 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
752 specified. */
753 #define OPTION_DEFAULT_SPECS \
754 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
755 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
756 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
757 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
758 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
759 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
760 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
761 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
762 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
763 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
764 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
765 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
766
767
768 /* A spec that infers the -mdsp setting from an -march argument. */
769 #define BASE_DRIVER_SELF_SPECS \
770 "%{!mno-dsp: \
771 %{march=24ke*|march=34k*|march=1004k*: -mdsp} \
772 %{march=74k*:%{!mno-dspr2: -mdspr2 -mdsp}}}"
773
774 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
775
776 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
777 && ISA_HAS_COND_TRAP)
778
779 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
780
781 /* True if the ABI can only work with 64-bit integer registers. We
782 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
783 otherwise floating-point registers must also be 64-bit. */
784 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
785
786 /* Likewise for 32-bit regs. */
787 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
788
789 /* True if the file format uses 64-bit symbols. At present, this is
790 only true for n64, which uses 64-bit ELF. */
791 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
792
793 /* True if symbols are 64 bits wide. This is usually determined by
794 the ABI's file format, but it can be overridden by -msym32. Note that
795 overriding the size with -msym32 changes the ABI of relocatable objects,
796 although it doesn't change the ABI of a fully-linked object. */
797 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
798
799 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
800 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
801 || ISA_MIPS4 \
802 || ISA_MIPS64 \
803 || ISA_MIPS64R2)
804
805 /* ISA has branch likely instructions (e.g. mips2). */
806 /* Disable branchlikely for tx39 until compare rewrite. They haven't
807 been generated up to this point. */
808 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
809
810 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
811 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
812 || TARGET_MIPS5400 \
813 || TARGET_MIPS5500 \
814 || TARGET_MIPS7000 \
815 || TARGET_MIPS9000 \
816 || TARGET_MAD \
817 || ISA_MIPS32 \
818 || ISA_MIPS32R2 \
819 || ISA_MIPS64 \
820 || ISA_MIPS64R2) \
821 && !TARGET_MIPS16)
822
823 /* ISA has a three-operand multiplication instruction. */
824 #define ISA_HAS_DMUL3 (TARGET_64BIT \
825 && TARGET_OCTEON \
826 && !TARGET_MIPS16)
827
828 /* ISA has the floating-point conditional move instructions introduced
829 in mips4. */
830 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
831 || ISA_MIPS32 \
832 || ISA_MIPS32R2 \
833 || ISA_MIPS64 \
834 || ISA_MIPS64R2) \
835 && !TARGET_MIPS5500 \
836 && !TARGET_MIPS16)
837
838 /* ISA has the integer conditional move instructions introduced in mips4 and
839 ST Loongson 2E/2F. */
840 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
841
842 /* ISA has LDC1 and SDC1. */
843 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
844
845 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
846 branch on CC, and move (both FP and non-FP) on CC. */
847 #define ISA_HAS_8CC (ISA_MIPS4 \
848 || ISA_MIPS32 \
849 || ISA_MIPS32R2 \
850 || ISA_MIPS64 \
851 || ISA_MIPS64R2)
852
853 /* This is a catch all for other mips4 instructions: indexed load, the
854 FP madd and msub instructions, and the FP recip and recip sqrt
855 instructions. */
856 #define ISA_HAS_FP4 ((ISA_MIPS4 \
857 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
858 || ISA_MIPS64 \
859 || ISA_MIPS64R2) \
860 && !TARGET_MIPS16)
861
862 /* ISA has paired-single instructions. */
863 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
864
865 /* ISA has conditional trap instructions. */
866 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
867 && !TARGET_MIPS16)
868
869 /* ISA has integer multiply-accumulate instructions, madd and msub. */
870 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
871 || ISA_MIPS32R2 \
872 || ISA_MIPS64 \
873 || ISA_MIPS64R2) \
874 && !TARGET_MIPS16)
875
876 /* Integer multiply-accumulate instructions should be generated. */
877 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
878
879 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
880 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
881
882 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
883 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
884
885 /* ISA has floating-point nmadd and nmsub instructions
886 'd = -((a * b) [+-] c)'. */
887 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
888 ((ISA_MIPS4 \
889 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
890 || ISA_MIPS64 \
891 || ISA_MIPS64R2) \
892 && (!TARGET_MIPS5400 || TARGET_MAD) \
893 && !TARGET_MIPS16)
894
895 /* ISA has floating-point nmadd and nmsub instructions
896 'c = -((a * b) [+-] c)'. */
897 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
898 TARGET_LOONGSON_2EF
899
900 /* ISA has count leading zeroes/ones instruction (not implemented). */
901 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
902 || ISA_MIPS32R2 \
903 || ISA_MIPS64 \
904 || ISA_MIPS64R2) \
905 && !TARGET_MIPS16)
906
907 /* ISA has three operand multiply instructions that put
908 the high part in an accumulator: mulhi or mulhiu. */
909 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
910 || TARGET_MIPS5500 \
911 || TARGET_SR71K) \
912 && !TARGET_MIPS16)
913
914 /* ISA has three operand multiply instructions that
915 negates the result and puts the result in an accumulator. */
916 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
917 || TARGET_MIPS5500 \
918 || TARGET_SR71K) \
919 && !TARGET_MIPS16)
920
921 /* ISA has three operand multiply instructions that subtracts the
922 result from a 4th operand and puts the result in an accumulator. */
923 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
924 || TARGET_MIPS5500 \
925 || TARGET_SR71K) \
926 && !TARGET_MIPS16)
927
928 /* ISA has three operand multiply instructions that the result
929 from a 4th operand and puts the result in an accumulator. */
930 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
931 || TARGET_MIPS4130 \
932 || TARGET_MIPS5400 \
933 || TARGET_MIPS5500 \
934 || TARGET_SR71K) \
935 && !TARGET_MIPS16)
936
937 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
938 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
939 || TARGET_MIPS4130) \
940 && !TARGET_MIPS16)
941
942 /* ISA has the "ror" (rotate right) instructions. */
943 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
944 || ISA_MIPS64R2 \
945 || TARGET_MIPS5400 \
946 || TARGET_MIPS5500 \
947 || TARGET_SR71K \
948 || TARGET_SMARTMIPS) \
949 && !TARGET_MIPS16)
950
951 /* ISA has data prefetch instructions. This controls use of 'pref'. */
952 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
953 || TARGET_LOONGSON_2EF \
954 || ISA_MIPS32 \
955 || ISA_MIPS32R2 \
956 || ISA_MIPS64 \
957 || ISA_MIPS64R2) \
958 && !TARGET_MIPS16)
959
960 /* ISA has data indexed prefetch instructions. This controls use of
961 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
962 (prefx is a cop1x instruction, so can only be used if FP is
963 enabled.) */
964 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
965 || ISA_MIPS32R2 \
966 || ISA_MIPS64 \
967 || ISA_MIPS64R2) \
968 && !TARGET_MIPS16)
969
970 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
971 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
972 also requires TARGET_DOUBLE_FLOAT. */
973 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
974
975 /* ISA includes the MIPS32r2 seb and seh instructions. */
976 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
977 || ISA_MIPS64R2) \
978 && !TARGET_MIPS16)
979
980 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
981 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
982 || ISA_MIPS64R2) \
983 && !TARGET_MIPS16)
984
985 /* ISA has instructions for accessing top part of 64-bit fp regs. */
986 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
987 && (ISA_MIPS32R2 \
988 || ISA_MIPS64R2))
989
990 /* ISA has lwxs instruction (load w/scaled index address. */
991 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
992
993 /* The DSP ASE is available. */
994 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
995
996 /* Revision 2 of the DSP ASE is available. */
997 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
998
999 /* True if the result of a load is not available to the next instruction.
1000 A nop will then be needed between instructions like "lw $4,..."
1001 and "addiu $4,$4,1". */
1002 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1003 && !TARGET_MIPS3900 \
1004 && !TARGET_MIPS16)
1005
1006 /* Likewise mtc1 and mfc1. */
1007 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1008 && !TARGET_LOONGSON_2EF)
1009
1010 /* Likewise floating-point comparisons. */
1011 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1012 && !TARGET_LOONGSON_2EF)
1013
1014 /* True if mflo and mfhi can be immediately followed by instructions
1015 which write to the HI and LO registers.
1016
1017 According to MIPS specifications, MIPS ISAs I, II, and III need
1018 (at least) two instructions between the reads of HI/LO and
1019 instructions which write them, and later ISAs do not. Contradicting
1020 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1021 the UM for the NEC Vr5000) document needing the instructions between
1022 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1023 MIPS64 and later ISAs to have the interlocks, plus any specific
1024 earlier-ISA CPUs for which CPU documentation declares that the
1025 instructions are really interlocked. */
1026 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1027 || ISA_MIPS32R2 \
1028 || ISA_MIPS64 \
1029 || ISA_MIPS64R2 \
1030 || TARGET_MIPS5500 \
1031 || TARGET_LOONGSON_2EF)
1032
1033 /* ISA includes synci, jr.hb and jalr.hb. */
1034 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1035 || ISA_MIPS64R2) \
1036 && !TARGET_MIPS16)
1037
1038 /* ISA includes sync. */
1039 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1040 #define GENERATE_SYNC \
1041 (target_flags_explicit & MASK_LLSC \
1042 ? TARGET_LLSC && !TARGET_MIPS16 \
1043 : ISA_HAS_SYNC)
1044
1045 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1046 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1047 instructions. */
1048 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1049 #define GENERATE_LL_SC \
1050 (target_flags_explicit & MASK_LLSC \
1051 ? TARGET_LLSC && !TARGET_MIPS16 \
1052 : ISA_HAS_LL_SC)
1053
1054 /* ISA includes the baddu instruction. */
1055 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1056
1057 /* ISA includes the bbit* instructions. */
1058 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1059
1060 /* ISA includes the cins instruction. */
1061 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1062
1063 /* ISA includes the exts instruction. */
1064 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1065
1066 /* ISA includes the seq and sne instructions. */
1067 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1068
1069 /* ISA includes the pop instruction. */
1070 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1071
1072 /* The CACHE instruction is available in non-MIPS16 code. */
1073 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1074
1075 /* The CACHE instruction is available. */
1076 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1077 \f
1078 /* Add -G xx support. */
1079
1080 #undef SWITCH_TAKES_ARG
1081 #define SWITCH_TAKES_ARG(CHAR) \
1082 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1083
1084 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1085 \f
1086 /* Tell collect what flags to pass to nm. */
1087 #ifndef NM_FLAGS
1088 #define NM_FLAGS "-Bn"
1089 #endif
1090
1091 \f
1092 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1093 to the assembler. It may be overridden by subtargets. */
1094 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1095 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1096 %{noasmopt:-O0} \
1097 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1098 #endif
1099
1100 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1101 the assembler. It may be overridden by subtargets.
1102
1103 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1104 COFF debugging info. */
1105
1106 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1107 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1108 %{g} %{g0} %{g1} %{g2} %{g3} \
1109 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1110 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1111 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1112 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1113 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1114 #endif
1115
1116 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1117 overridden by subtargets. */
1118
1119 #ifndef SUBTARGET_ASM_SPEC
1120 #define SUBTARGET_ASM_SPEC ""
1121 #endif
1122
1123 #undef ASM_SPEC
1124 #define ASM_SPEC "\
1125 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1126 %{mips32*} %{mips64*} \
1127 %{mips16} %{mno-mips16:-no-mips16} \
1128 %{mips3d} %{mno-mips3d:-no-mips3d} \
1129 %{mdmx} %{mno-mdmx:-no-mdmx} \
1130 %{mdsp} %{mno-dsp} \
1131 %{mdspr2} %{mno-dspr2} \
1132 %{msmartmips} %{mno-smartmips} \
1133 %{mmt} %{mno-mt} \
1134 %{mfix-vr4120} %{mfix-vr4130} \
1135 %(subtarget_asm_optimizing_spec) \
1136 %(subtarget_asm_debugging_spec) \
1137 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1138 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1139 %{mfp32} %{mfp64} \
1140 %{mshared} %{mno-shared} \
1141 %{msym32} %{mno-sym32} \
1142 %{mtune=*} %{v} \
1143 %(subtarget_asm_spec)"
1144
1145 /* Extra switches sometimes passed to the linker. */
1146 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1147 will interpret it as a -b option. */
1148
1149 #ifndef LINK_SPEC
1150 #define LINK_SPEC "\
1151 %(endian_spec) \
1152 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1153 %{bestGnum} %{shared} %{non_shared}"
1154 #endif /* LINK_SPEC defined */
1155
1156
1157 /* Specs for the compiler proper */
1158
1159 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1160 overridden by subtargets. */
1161 #ifndef SUBTARGET_CC1_SPEC
1162 #define SUBTARGET_CC1_SPEC ""
1163 #endif
1164
1165 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1166
1167 #undef CC1_SPEC
1168 #define CC1_SPEC "\
1169 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1170 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1171 %{save-temps: } \
1172 %(subtarget_cc1_spec)"
1173
1174 /* Preprocessor specs. */
1175
1176 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1177 overridden by subtargets. */
1178 #ifndef SUBTARGET_CPP_SPEC
1179 #define SUBTARGET_CPP_SPEC ""
1180 #endif
1181
1182 #define CPP_SPEC "%(subtarget_cpp_spec)"
1183
1184 /* This macro defines names of additional specifications to put in the specs
1185 that can be used in various specifications like CC1_SPEC. Its definition
1186 is an initializer with a subgrouping for each command option.
1187
1188 Each subgrouping contains a string constant, that defines the
1189 specification name, and a string constant that used by the GCC driver
1190 program.
1191
1192 Do not define this macro if it does not need to do anything. */
1193
1194 #define EXTRA_SPECS \
1195 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1196 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1197 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1198 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1199 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1200 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1201 { "endian_spec", ENDIAN_SPEC }, \
1202 SUBTARGET_EXTRA_SPECS
1203
1204 #ifndef SUBTARGET_EXTRA_SPECS
1205 #define SUBTARGET_EXTRA_SPECS
1206 #endif
1207 \f
1208 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1209 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1210
1211 #ifndef PREFERRED_DEBUGGING_TYPE
1212 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1213 #endif
1214
1215 /* The size of DWARF addresses should be the same as the size of symbols
1216 in the target file format. They shouldn't depend on things like -msym32,
1217 because many DWARF consumers do not allow the mixture of address sizes
1218 that one would then get from linking -msym32 code with -msym64 code.
1219
1220 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1221 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1222 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1223
1224 /* By default, turn on GDB extensions. */
1225 #define DEFAULT_GDB_EXTENSIONS 1
1226
1227 /* Local compiler-generated symbols must have a prefix that the assembler
1228 understands. By default, this is $, although some targets (e.g.,
1229 NetBSD-ELF) need to override this. */
1230
1231 #ifndef LOCAL_LABEL_PREFIX
1232 #define LOCAL_LABEL_PREFIX "$"
1233 #endif
1234
1235 /* By default on the mips, external symbols do not have an underscore
1236 prepended, but some targets (e.g., NetBSD) require this. */
1237
1238 #ifndef USER_LABEL_PREFIX
1239 #define USER_LABEL_PREFIX ""
1240 #endif
1241
1242 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1243 since the length can run past this up to a continuation point. */
1244 #undef DBX_CONTIN_LENGTH
1245 #define DBX_CONTIN_LENGTH 1500
1246
1247 /* How to renumber registers for dbx and gdb. */
1248 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1249
1250 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1251 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1252
1253 /* The DWARF 2 CFA column which tracks the return address. */
1254 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1255
1256 /* Before the prologue, RA lives in r31. */
1257 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1258
1259 /* Describe how we implement __builtin_eh_return. */
1260 #define EH_RETURN_DATA_REGNO(N) \
1261 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1262
1263 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1264
1265 #define EH_USES(N) mips_eh_uses (N)
1266
1267 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1268 The default for this in 64-bit mode is 8, which causes problems with
1269 SFmode register saves. */
1270 #define DWARF_CIE_DATA_ALIGNMENT -4
1271
1272 /* Correct the offset of automatic variables and arguments. Note that
1273 the MIPS debug format wants all automatic variables and arguments
1274 to be in terms of the virtual frame pointer (stack pointer before
1275 any adjustment in the function), while the MIPS 3.0 linker wants
1276 the frame pointer to be the stack pointer after the initial
1277 adjustment. */
1278
1279 #define DEBUGGER_AUTO_OFFSET(X) \
1280 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1281 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1282 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1283 \f
1284 /* Target machine storage layout */
1285
1286 #define BITS_BIG_ENDIAN 0
1287 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1288 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1289
1290 /* Define this to set the endianness to use in libgcc2.c, which can
1291 not depend on target_flags. */
1292 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1293 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1294 #else
1295 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1296 #endif
1297
1298 #define MAX_BITS_PER_WORD 64
1299
1300 /* Width of a word, in units (bytes). */
1301 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1302 #ifndef IN_LIBGCC2
1303 #define MIN_UNITS_PER_WORD 4
1304 #endif
1305
1306 /* For MIPS, width of a floating point register. */
1307 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1308
1309 /* The number of consecutive floating-point registers needed to store the
1310 largest format supported by the FPU. */
1311 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1312
1313 /* The number of consecutive floating-point registers needed to store the
1314 smallest format supported by the FPU. */
1315 #define MIN_FPRS_PER_FMT \
1316 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1317 ? 1 : MAX_FPRS_PER_FMT)
1318
1319 /* The largest size of value that can be held in floating-point
1320 registers and moved with a single instruction. */
1321 #define UNITS_PER_HWFPVALUE \
1322 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1323
1324 /* The largest size of value that can be held in floating-point
1325 registers. */
1326 #define UNITS_PER_FPVALUE \
1327 (TARGET_SOFT_FLOAT_ABI ? 0 \
1328 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1329 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1330
1331 /* The number of bytes in a double. */
1332 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1333
1334 /* Set the sizes of the core types. */
1335 #define SHORT_TYPE_SIZE 16
1336 #define INT_TYPE_SIZE 32
1337 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1338 #define LONG_LONG_TYPE_SIZE 64
1339
1340 #define FLOAT_TYPE_SIZE 32
1341 #define DOUBLE_TYPE_SIZE 64
1342 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1343
1344 /* Define the sizes of fixed-point types. */
1345 #define SHORT_FRACT_TYPE_SIZE 8
1346 #define FRACT_TYPE_SIZE 16
1347 #define LONG_FRACT_TYPE_SIZE 32
1348 #define LONG_LONG_FRACT_TYPE_SIZE 64
1349
1350 #define SHORT_ACCUM_TYPE_SIZE 16
1351 #define ACCUM_TYPE_SIZE 32
1352 #define LONG_ACCUM_TYPE_SIZE 64
1353 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1354 doesn't support 128-bit integers for MIPS32 currently. */
1355 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1356
1357 /* long double is not a fixed mode, but the idea is that, if we
1358 support long double, we also want a 128-bit integer type. */
1359 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1360
1361 #ifdef IN_LIBGCC2
1362 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1363 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1364 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1365 # else
1366 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1367 # endif
1368 #endif
1369
1370 /* Width in bits of a pointer. */
1371 #ifndef POINTER_SIZE
1372 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1373 #endif
1374
1375 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1376 #define PARM_BOUNDARY BITS_PER_WORD
1377
1378 /* Allocation boundary (in *bits*) for the code of a function. */
1379 #define FUNCTION_BOUNDARY 32
1380
1381 /* Alignment of field after `int : 0' in a structure. */
1382 #define EMPTY_FIELD_BOUNDARY 32
1383
1384 /* Every structure's size must be a multiple of this. */
1385 /* 8 is observed right on a DECstation and on riscos 4.02. */
1386 #define STRUCTURE_SIZE_BOUNDARY 8
1387
1388 /* There is no point aligning anything to a rounder boundary than this. */
1389 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1390
1391 /* All accesses must be aligned. */
1392 #define STRICT_ALIGNMENT 1
1393
1394 /* Define this if you wish to imitate the way many other C compilers
1395 handle alignment of bitfields and the structures that contain
1396 them.
1397
1398 The behavior is that the type written for a bit-field (`int',
1399 `short', or other integer type) imposes an alignment for the
1400 entire structure, as if the structure really did contain an
1401 ordinary field of that type. In addition, the bit-field is placed
1402 within the structure so that it would fit within such a field,
1403 not crossing a boundary for it.
1404
1405 Thus, on most machines, a bit-field whose type is written as `int'
1406 would not cross a four-byte boundary, and would force four-byte
1407 alignment for the whole structure. (The alignment used may not
1408 be four bytes; it is controlled by the other alignment
1409 parameters.)
1410
1411 If the macro is defined, its definition should be a C expression;
1412 a nonzero value for the expression enables this behavior. */
1413
1414 #define PCC_BITFIELD_TYPE_MATTERS 1
1415
1416 /* If defined, a C expression to compute the alignment given to a
1417 constant that is being placed in memory. CONSTANT is the constant
1418 and ALIGN is the alignment that the object would ordinarily have.
1419 The value of this macro is used instead of that alignment to align
1420 the object.
1421
1422 If this macro is not defined, then ALIGN is used.
1423
1424 The typical use of this macro is to increase alignment for string
1425 constants to be word aligned so that `strcpy' calls that copy
1426 constants can be done inline. */
1427
1428 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1429 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1430 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1431
1432 /* If defined, a C expression to compute the alignment for a static
1433 variable. TYPE is the data type, and ALIGN is the alignment that
1434 the object would ordinarily have. The value of this macro is used
1435 instead of that alignment to align the object.
1436
1437 If this macro is not defined, then ALIGN is used.
1438
1439 One use of this macro is to increase alignment of medium-size
1440 data to make it all fit in fewer cache lines. Another is to
1441 cause character arrays to be word-aligned so that `strcpy' calls
1442 that copy constants to character arrays can be done inline. */
1443
1444 #undef DATA_ALIGNMENT
1445 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1446 ((((ALIGN) < BITS_PER_WORD) \
1447 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1448 || TREE_CODE (TYPE) == UNION_TYPE \
1449 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1450
1451 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1452 character arrays to be word-aligned so that `strcpy' calls that copy
1453 constants to character arrays can be done inline, and 'strcmp' can be
1454 optimised to use word loads. */
1455 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1456 DATA_ALIGNMENT (TYPE, ALIGN)
1457
1458 #define PAD_VARARGS_DOWN \
1459 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1460
1461 /* Define if operations between registers always perform the operation
1462 on the full register even if a narrower mode is specified. */
1463 #define WORD_REGISTER_OPERATIONS
1464
1465 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1466 moves. All other references are zero extended. */
1467 #define LOAD_EXTEND_OP(MODE) \
1468 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1469 ? SIGN_EXTEND : ZERO_EXTEND)
1470
1471 /* Define this macro if it is advisable to hold scalars in registers
1472 in a wider mode than that declared by the program. In such cases,
1473 the value is constrained to be within the bounds of the declared
1474 type, but kept valid in the wider mode. The signedness of the
1475 extension may differ from that of the type. */
1476
1477 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1478 if (GET_MODE_CLASS (MODE) == MODE_INT \
1479 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1480 { \
1481 if ((MODE) == SImode) \
1482 (UNSIGNEDP) = 0; \
1483 (MODE) = Pmode; \
1484 }
1485
1486 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1487 Extensions of pointers to word_mode must be signed. */
1488 #define POINTERS_EXTEND_UNSIGNED false
1489
1490 /* Define if loading short immediate values into registers sign extends. */
1491 #define SHORT_IMMEDIATES_SIGN_EXTEND
1492
1493 /* The [d]clz instructions have the natural values at 0. */
1494
1495 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1496 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1497 \f
1498 /* Standard register usage. */
1499
1500 /* Number of hardware registers. We have:
1501
1502 - 32 integer registers
1503 - 32 floating point registers
1504 - 8 condition code registers
1505 - 2 accumulator registers (hi and lo)
1506 - 32 registers each for coprocessors 0, 2 and 3
1507 - 4 fake registers:
1508 - ARG_POINTER_REGNUM
1509 - FRAME_POINTER_REGNUM
1510 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1511 - CPRESTORE_SLOT_REGNUM
1512 - 2 dummy entries that were used at various times in the past.
1513 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1514 - 6 DSP control registers */
1515
1516 #define FIRST_PSEUDO_REGISTER 188
1517
1518 /* By default, fix the kernel registers ($26 and $27), the global
1519 pointer ($28) and the stack pointer ($29). This can change
1520 depending on the command-line options.
1521
1522 Regarding coprocessor registers: without evidence to the contrary,
1523 it's best to assume that each coprocessor register has a unique
1524 use. This can be overridden, in, e.g., mips_option_override or
1525 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1526 for a particular target. */
1527
1528 #define FIXED_REGISTERS \
1529 { \
1530 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1532 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1533 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1534 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1535 /* COP0 registers */ \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1538 /* COP2 registers */ \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1541 /* COP3 registers */ \
1542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 /* 6 DSP accumulator registers & 6 control registers */ \
1545 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1546 }
1547
1548
1549 /* Set up this array for o32 by default.
1550
1551 Note that we don't mark $31 as a call-clobbered register. The idea is
1552 that it's really the call instructions themselves which clobber $31.
1553 We don't care what the called function does with it afterwards.
1554
1555 This approach makes it easier to implement sibcalls. Unlike normal
1556 calls, sibcalls don't clobber $31, so the register reaches the
1557 called function in tact. EPILOGUE_USES says that $31 is useful
1558 to the called function. */
1559
1560 #define CALL_USED_REGISTERS \
1561 { \
1562 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1563 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1564 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1565 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 /* COP0 registers */ \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1570 /* COP2 registers */ \
1571 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 /* COP3 registers */ \
1574 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 /* 6 DSP accumulator registers & 6 control registers */ \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1578 }
1579
1580
1581 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1582
1583 #define CALL_REALLY_USED_REGISTERS \
1584 { /* General registers. */ \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1586 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1587 /* Floating-point registers. */ \
1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1589 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1590 /* Others. */ \
1591 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1592 /* COP0 registers */ \
1593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1594 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1595 /* COP2 registers */ \
1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1597 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1598 /* COP3 registers */ \
1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1601 /* 6 DSP accumulator registers & 6 control registers */ \
1602 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1603 }
1604
1605 /* Internal macros to classify a register number as to whether it's a
1606 general purpose register, a floating point register, a
1607 multiply/divide register, or a status register. */
1608
1609 #define GP_REG_FIRST 0
1610 #define GP_REG_LAST 31
1611 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1612 #define GP_DBX_FIRST 0
1613 #define K0_REG_NUM (GP_REG_FIRST + 26)
1614 #define K1_REG_NUM (GP_REG_FIRST + 27)
1615 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1616
1617 #define FP_REG_FIRST 32
1618 #define FP_REG_LAST 63
1619 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1620 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1621
1622 #define MD_REG_FIRST 64
1623 #define MD_REG_LAST 65
1624 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1625 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1626
1627 /* The DWARF 2 CFA column which tracks the return address from a
1628 signal handler context. This means that to maintain backwards
1629 compatibility, no hard register can be assigned this column if it
1630 would need to be handled by the DWARF unwinder. */
1631 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1632
1633 #define ST_REG_FIRST 67
1634 #define ST_REG_LAST 74
1635 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1636
1637
1638 /* FIXME: renumber. */
1639 #define COP0_REG_FIRST 80
1640 #define COP0_REG_LAST 111
1641 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1642
1643 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1644 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1645 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1646
1647 #define COP2_REG_FIRST 112
1648 #define COP2_REG_LAST 143
1649 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1650
1651 #define COP3_REG_FIRST 144
1652 #define COP3_REG_LAST 175
1653 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1654 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1655 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1656
1657 #define DSP_ACC_REG_FIRST 176
1658 #define DSP_ACC_REG_LAST 181
1659 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1660
1661 #define AT_REGNUM (GP_REG_FIRST + 1)
1662 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1663 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1664
1665 /* A few bitfield locations for the coprocessor registers. */
1666 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1667 the cause register for the EIC interrupt mode. */
1668 #define CAUSE_IPL 10
1669 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1670 #define SR_IPL 10
1671 /* Exception Level is at bit 1 of the status register. */
1672 #define SR_EXL 1
1673 /* Interrupt Enable is at bit 0 of the status register. */
1674 #define SR_IE 0
1675
1676 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1677 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1678 should be used instead. */
1679 #define FPSW_REGNUM ST_REG_FIRST
1680
1681 #define GP_REG_P(REGNO) \
1682 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1683 #define M16_REG_P(REGNO) \
1684 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1685 #define FP_REG_P(REGNO) \
1686 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1687 #define MD_REG_P(REGNO) \
1688 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1689 #define ST_REG_P(REGNO) \
1690 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1691 #define COP0_REG_P(REGNO) \
1692 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1693 #define COP2_REG_P(REGNO) \
1694 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1695 #define COP3_REG_P(REGNO) \
1696 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1697 #define ALL_COP_REG_P(REGNO) \
1698 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1699 /* Test if REGNO is one of the 6 new DSP accumulators. */
1700 #define DSP_ACC_REG_P(REGNO) \
1701 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1702 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1703 #define ACC_REG_P(REGNO) \
1704 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1705
1706 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1707
1708 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1709 to initialize the mips16 gp pseudo register. */
1710 #define CONST_GP_P(X) \
1711 (GET_CODE (X) == CONST \
1712 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1713 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1714
1715 /* Return coprocessor number from register number. */
1716
1717 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1718 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1719 : COP3_REG_P (REGNO) ? '3' : '?')
1720
1721
1722 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1723
1724 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1725 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1726
1727 #define MODES_TIEABLE_P mips_modes_tieable_p
1728
1729 /* Register to use for pushing function arguments. */
1730 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1731
1732 /* These two registers don't really exist: they get eliminated to either
1733 the stack or hard frame pointer. */
1734 #define ARG_POINTER_REGNUM 77
1735 #define FRAME_POINTER_REGNUM 78
1736
1737 /* $30 is not available on the mips16, so we use $17 as the frame
1738 pointer. */
1739 #define HARD_FRAME_POINTER_REGNUM \
1740 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1741
1742 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1743 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1744
1745 /* Register in which static-chain is passed to a function. */
1746 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1747
1748 /* Registers used as temporaries in prologue/epilogue code:
1749
1750 - If a MIPS16 PIC function needs access to _gp, it first loads
1751 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1752
1753 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1754 register. The register must not conflict with MIPS16_PIC_TEMP.
1755
1756 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1757 register.
1758
1759 If we're generating MIPS16 code, these registers must come from the
1760 core set of 8. The prologue registers mustn't conflict with any
1761 incoming arguments, the static chain pointer, or the frame pointer.
1762 The epilogue temporary mustn't conflict with the return registers,
1763 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1764 or the EH data registers.
1765
1766 If we're generating interrupt handlers, we use K0 as a temporary register
1767 in prologue/epilogue code. */
1768
1769 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1770 #define MIPS_PROLOGUE_TEMP_REGNUM \
1771 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1772 #define MIPS_EPILOGUE_TEMP_REGNUM \
1773 (cfun->machine->interrupt_handler_p \
1774 ? K0_REG_NUM \
1775 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1776
1777 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1778 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1779 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1780
1781 /* Define this macro if it is as good or better to call a constant
1782 function address than to call an address kept in a register. */
1783 #define NO_FUNCTION_CSE 1
1784
1785 /* The ABI-defined global pointer. Sometimes we use a different
1786 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1787 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1788
1789 /* We normally use $28 as the global pointer. However, when generating
1790 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1791 register instead. They can then avoid saving and restoring $28
1792 and perhaps avoid using a frame at all.
1793
1794 When a leaf function uses something other than $28, mips_expand_prologue
1795 will modify pic_offset_table_rtx in place. Take the register number
1796 from there after reload. */
1797 #define PIC_OFFSET_TABLE_REGNUM \
1798 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1799
1800 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1801 \f
1802 /* Define the classes of registers for register constraints in the
1803 machine description. Also define ranges of constants.
1804
1805 One of the classes must always be named ALL_REGS and include all hard regs.
1806 If there is more than one class, another class must be named NO_REGS
1807 and contain no registers.
1808
1809 The name GENERAL_REGS must be the name of a class (or an alias for
1810 another name such as ALL_REGS). This is the class of registers
1811 that is allowed by "g" or "r" in a register constraint.
1812 Also, registers outside this class are allocated only when
1813 instructions express preferences for them.
1814
1815 The classes must be numbered in nondecreasing order; that is,
1816 a larger-numbered class must never be contained completely
1817 in a smaller-numbered class.
1818
1819 For any two classes, it is very desirable that there be another
1820 class that represents their union. */
1821
1822 enum reg_class
1823 {
1824 NO_REGS, /* no registers in set */
1825 M16_REGS, /* mips16 directly accessible registers */
1826 T_REG, /* mips16 T register ($24) */
1827 M16_T_REGS, /* mips16 registers plus T register */
1828 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1829 V1_REG, /* Register $v1 ($3) used for TLS access. */
1830 LEA_REGS, /* Every GPR except $25 */
1831 GR_REGS, /* integer registers */
1832 FP_REGS, /* floating point registers */
1833 MD0_REG, /* first multiply/divide register */
1834 MD1_REG, /* second multiply/divide register */
1835 MD_REGS, /* multiply/divide registers (hi/lo) */
1836 COP0_REGS, /* generic coprocessor classes */
1837 COP2_REGS,
1838 COP3_REGS,
1839 ST_REGS, /* status registers (fp status) */
1840 DSP_ACC_REGS, /* DSP accumulator registers */
1841 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1842 FRAME_REGS, /* $arg and $frame */
1843 GR_AND_MD0_REGS, /* union classes */
1844 GR_AND_MD1_REGS,
1845 GR_AND_MD_REGS,
1846 GR_AND_ACC_REGS,
1847 ALL_REGS, /* all registers */
1848 LIM_REG_CLASSES /* max value + 1 */
1849 };
1850
1851 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1852
1853 #define GENERAL_REGS GR_REGS
1854
1855 /* An initializer containing the names of the register classes as C
1856 string constants. These names are used in writing some of the
1857 debugging dumps. */
1858
1859 #define REG_CLASS_NAMES \
1860 { \
1861 "NO_REGS", \
1862 "M16_REGS", \
1863 "T_REG", \
1864 "M16_T_REGS", \
1865 "PIC_FN_ADDR_REG", \
1866 "V1_REG", \
1867 "LEA_REGS", \
1868 "GR_REGS", \
1869 "FP_REGS", \
1870 "MD0_REG", \
1871 "MD1_REG", \
1872 "MD_REGS", \
1873 /* coprocessor registers */ \
1874 "COP0_REGS", \
1875 "COP2_REGS", \
1876 "COP3_REGS", \
1877 "ST_REGS", \
1878 "DSP_ACC_REGS", \
1879 "ACC_REGS", \
1880 "FRAME_REGS", \
1881 "GR_AND_MD0_REGS", \
1882 "GR_AND_MD1_REGS", \
1883 "GR_AND_MD_REGS", \
1884 "GR_AND_ACC_REGS", \
1885 "ALL_REGS" \
1886 }
1887
1888 /* An initializer containing the contents of the register classes,
1889 as integers which are bit masks. The Nth integer specifies the
1890 contents of class N. The way the integer MASK is interpreted is
1891 that register R is in the class if `MASK & (1 << R)' is 1.
1892
1893 When the machine has more than 32 registers, an integer does not
1894 suffice. Then the integers are replaced by sub-initializers,
1895 braced groupings containing several integers. Each
1896 sub-initializer must be suitable as an initializer for the type
1897 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1898
1899 #define REG_CLASS_CONTENTS \
1900 { \
1901 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1902 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1903 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1904 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1905 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1906 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1907 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1908 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1909 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1910 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1911 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1912 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1913 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1914 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1915 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1916 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1917 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1918 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1919 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1920 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1921 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1922 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1923 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1924 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1925 }
1926
1927
1928 /* A C expression whose value is a register class containing hard
1929 register REGNO. In general there is more that one such class;
1930 choose a class which is "minimal", meaning that no smaller class
1931 also contains the register. */
1932
1933 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1934
1935 /* A macro whose definition is the name of the class to which a
1936 valid base register must belong. A base register is one used in
1937 an address which is the register value plus a displacement. */
1938
1939 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1940
1941 /* A macro whose definition is the name of the class to which a
1942 valid index register must belong. An index register is one used
1943 in an address where its value is either multiplied by a scale
1944 factor or added to another register (as well as added to a
1945 displacement). */
1946
1947 #define INDEX_REG_CLASS NO_REGS
1948
1949 /* We generally want to put call-clobbered registers ahead of
1950 call-saved ones. (IRA expects this.) */
1951
1952 #define REG_ALLOC_ORDER \
1953 { /* Accumulator registers. When GPRs and accumulators have equal \
1954 cost, we generally prefer to use accumulators. For example, \
1955 a division of multiplication result is better allocated to LO, \
1956 so that we put the MFLO at the point of use instead of at the \
1957 point of definition. It's also needed if we're to take advantage \
1958 of the extra accumulators available with -mdspr2. In some cases, \
1959 it can also help to reduce register pressure. */ \
1960 64, 65,176,177,178,179,180,181, \
1961 /* Call-clobbered GPRs. */ \
1962 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1963 24, 25, 31, \
1964 /* The global pointer. This is call-clobbered for o32 and o64 \
1965 abicalls, call-saved for n32 and n64 abicalls, and a program \
1966 invariant otherwise. Putting it between the call-clobbered \
1967 and call-saved registers should cope with all eventualities. */ \
1968 28, \
1969 /* Call-saved GPRs. */ \
1970 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1971 /* GPRs that can never be exposed to the register allocator. */ \
1972 0, 26, 27, 29, \
1973 /* Call-clobbered FPRs. */ \
1974 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1975 48, 49, 50, 51, \
1976 /* FPRs that are usually call-saved. The odd ones are actually \
1977 call-clobbered for n32, but listing them ahead of the even \
1978 registers might encourage the register allocator to fragment \
1979 the available FPR pairs. We need paired FPRs to store long \
1980 doubles, so it isn't clear that using a different order \
1981 for n32 would be a win. */ \
1982 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1983 /* None of the remaining classes have defined call-saved \
1984 registers. */ \
1985 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1986 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1987 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1988 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1989 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1990 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1991 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1992 182,183,184,185,186,187 \
1993 }
1994
1995 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order
1996 to be rearranged based on a particular function. On the mips16, we
1997 want to allocate $24 (T_REG) before other registers for
1998 instructions for which it is possible. */
1999
2000 #define ADJUST_REG_ALLOC_ORDER mips_order_regs_for_local_alloc ()
2001
2002 /* True if VALUE is an unsigned 6-bit number. */
2003
2004 #define UIMM6_OPERAND(VALUE) \
2005 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2006
2007 /* True if VALUE is a signed 10-bit number. */
2008
2009 #define IMM10_OPERAND(VALUE) \
2010 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2011
2012 /* True if VALUE is a signed 16-bit number. */
2013
2014 #define SMALL_OPERAND(VALUE) \
2015 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2016
2017 /* True if VALUE is an unsigned 16-bit number. */
2018
2019 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2020 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2021
2022 /* True if VALUE can be loaded into a register using LUI. */
2023
2024 #define LUI_OPERAND(VALUE) \
2025 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2026 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2027
2028 /* Return a value X with the low 16 bits clear, and such that
2029 VALUE - X is a signed 16-bit value. */
2030
2031 #define CONST_HIGH_PART(VALUE) \
2032 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2033
2034 #define CONST_LOW_PART(VALUE) \
2035 ((VALUE) - CONST_HIGH_PART (VALUE))
2036
2037 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2038 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2039 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2040
2041 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2042 mips_preferred_reload_class (X, CLASS)
2043
2044 /* The HI and LO registers can only be reloaded via the general
2045 registers. Condition code registers can only be loaded to the
2046 general registers, and from the floating point registers. */
2047
2048 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2049 mips_secondary_reload_class (CLASS, MODE, X, true)
2050 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2051 mips_secondary_reload_class (CLASS, MODE, X, false)
2052
2053 /* Return the maximum number of consecutive registers
2054 needed to represent mode MODE in a register of class CLASS. */
2055
2056 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2057
2058 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2059 mips_cannot_change_mode_class (FROM, TO, CLASS)
2060 \f
2061 /* Stack layout; function entry, exit and calling. */
2062
2063 #define STACK_GROWS_DOWNWARD
2064
2065 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2066
2067 /* Size of the area allocated in the frame to save the GP. */
2068
2069 #define MIPS_GP_SAVE_AREA_SIZE \
2070 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2071
2072 /* The offset of the first local variable from the frame pointer. See
2073 mips_compute_frame_info for details about the frame layout. */
2074
2075 #define STARTING_FRAME_OFFSET \
2076 (FRAME_GROWS_DOWNWARD \
2077 ? 0 \
2078 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2079
2080 #define RETURN_ADDR_RTX mips_return_addr
2081
2082 /* Mask off the MIPS16 ISA bit in unwind addresses.
2083
2084 The reason for this is a little subtle. When unwinding a call,
2085 we are given the call's return address, which on most targets
2086 is the address of the following instruction. However, what we
2087 actually want to find is the EH region for the call itself.
2088 The target-independent unwind code therefore searches for "RA - 1".
2089
2090 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2091 RA - 1 is therefore the real (even-valued) start of the return
2092 instruction. EH region labels are usually odd-valued MIPS16 symbols
2093 too, so a search for an even address within a MIPS16 region would
2094 usually work.
2095
2096 However, there is an exception. If the end of an EH region is also
2097 the end of a function, the end label is allowed to be even. This is
2098 necessary because a following non-MIPS16 function may also need EH
2099 information for its first instruction.
2100
2101 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2102 non-ISA-encoded address. This probably isn't ideal, but it is
2103 the traditional (legacy) behavior. It is therefore only safe
2104 to search MIPS EH regions for an _odd-valued_ address.
2105
2106 Masking off the ISA bit means that the target-independent code
2107 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2108 #define MASK_RETURN_ADDR GEN_INT (-2)
2109
2110
2111 /* Similarly, don't use the least-significant bit to tell pointers to
2112 code from vtable index. */
2113
2114 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2115
2116 /* The eliminations to $17 are only used for mips16 code. See the
2117 definition of HARD_FRAME_POINTER_REGNUM. */
2118
2119 #define ELIMINABLE_REGS \
2120 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2121 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2122 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2123 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2124 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2125 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2126
2127 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2128 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2129
2130 /* Allocate stack space for arguments at the beginning of each function. */
2131 #define ACCUMULATE_OUTGOING_ARGS 1
2132
2133 /* The argument pointer always points to the first argument. */
2134 #define FIRST_PARM_OFFSET(FNDECL) 0
2135
2136 /* o32 and o64 reserve stack space for all argument registers. */
2137 #define REG_PARM_STACK_SPACE(FNDECL) \
2138 (TARGET_OLDABI \
2139 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2140 : 0)
2141
2142 /* Define this if it is the responsibility of the caller to
2143 allocate the area reserved for arguments passed in registers.
2144 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2145 of this macro is to determine whether the space is included in
2146 `crtl->outgoing_args_size'. */
2147 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2148
2149 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2150 \f
2151 /* Symbolic macros for the registers used to return integer and floating
2152 point values. */
2153
2154 #define GP_RETURN (GP_REG_FIRST + 2)
2155 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2156
2157 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2158
2159 /* Symbolic macros for the first/last argument registers. */
2160
2161 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2162 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2163 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2164 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2165
2166 #define LIBCALL_VALUE(MODE) \
2167 mips_function_value (NULL_TREE, NULL_TREE, MODE)
2168
2169 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2170 mips_function_value (VALTYPE, FUNC, VOIDmode)
2171
2172 /* 1 if N is a possible register number for a function value.
2173 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2174 Currently, R2 and F0 are only implemented here (C has no complex type) */
2175
2176 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2177 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2178 && (N) == FP_RETURN + 2))
2179
2180 /* 1 if N is a possible register number for function argument passing.
2181 We have no FP argument registers when soft-float. When FP registers
2182 are 32 bits, we can't directly reference the odd numbered ones. */
2183
2184 #define FUNCTION_ARG_REGNO_P(N) \
2185 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2186 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2187 && !fixed_regs[N])
2188 \f
2189 /* This structure has to cope with two different argument allocation
2190 schemes. Most MIPS ABIs view the arguments as a structure, of which
2191 the first N words go in registers and the rest go on the stack. If I
2192 < N, the Ith word might go in Ith integer argument register or in a
2193 floating-point register. For these ABIs, we only need to remember
2194 the offset of the current argument into the structure.
2195
2196 The EABI instead allocates the integer and floating-point arguments
2197 separately. The first N words of FP arguments go in FP registers,
2198 the rest go on the stack. Likewise, the first N words of the other
2199 arguments go in integer registers, and the rest go on the stack. We
2200 need to maintain three counts: the number of integer registers used,
2201 the number of floating-point registers used, and the number of words
2202 passed on the stack.
2203
2204 We could keep separate information for the two ABIs (a word count for
2205 the standard ABIs, and three separate counts for the EABI). But it
2206 seems simpler to view the standard ABIs as forms of EABI that do not
2207 allocate floating-point registers.
2208
2209 So for the standard ABIs, the first N words are allocated to integer
2210 registers, and mips_function_arg decides on an argument-by-argument
2211 basis whether that argument should really go in an integer register,
2212 or in a floating-point one. */
2213
2214 typedef struct mips_args {
2215 /* Always true for varargs functions. Otherwise true if at least
2216 one argument has been passed in an integer register. */
2217 int gp_reg_found;
2218
2219 /* The number of arguments seen so far. */
2220 unsigned int arg_number;
2221
2222 /* The number of integer registers used so far. For all ABIs except
2223 EABI, this is the number of words that have been added to the
2224 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2225 unsigned int num_gprs;
2226
2227 /* For EABI, the number of floating-point registers used so far. */
2228 unsigned int num_fprs;
2229
2230 /* The number of words passed on the stack. */
2231 unsigned int stack_words;
2232
2233 /* On the mips16, we need to keep track of which floating point
2234 arguments were passed in general registers, but would have been
2235 passed in the FP regs if this were a 32-bit function, so that we
2236 can move them to the FP regs if we wind up calling a 32-bit
2237 function. We record this information in fp_code, encoded in base
2238 four. A zero digit means no floating point argument, a one digit
2239 means an SFmode argument, and a two digit means a DFmode argument,
2240 and a three digit is not used. The low order digit is the first
2241 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2242 an SFmode argument. ??? A more sophisticated approach will be
2243 needed if MIPS_ABI != ABI_32. */
2244 int fp_code;
2245
2246 /* True if the function has a prototype. */
2247 int prototype;
2248 } CUMULATIVE_ARGS;
2249
2250 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2251 for a call to a function whose data type is FNTYPE.
2252 For a library call, FNTYPE is 0. */
2253
2254 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2255 mips_init_cumulative_args (&CUM, FNTYPE)
2256
2257 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2258
2259 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2260 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2261
2262 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2263 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2264
2265 /* True if using EABI and varargs can be passed in floating-point
2266 registers. Under these conditions, we need a more complex form
2267 of va_list, which tracks GPR, FPR and stack arguments separately. */
2268 #define EABI_FLOAT_VARARGS_P \
2269 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2270
2271 \f
2272 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2273
2274 /* Treat LOC as a byte offset from the stack pointer and round it up
2275 to the next fully-aligned offset. */
2276 #define MIPS_STACK_ALIGN(LOC) \
2277 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2278
2279 \f
2280 /* Output assembler code to FILE to increment profiler label # LABELNO
2281 for profiling a function entry. */
2282
2283 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2284
2285 /* The profiler preserves all interesting registers, including $31. */
2286 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2287
2288 /* No mips port has ever used the profiler counter word, so don't emit it
2289 or the label for it. */
2290
2291 #define NO_PROFILE_COUNTERS 1
2292
2293 /* Define this macro if the code for function profiling should come
2294 before the function prologue. Normally, the profiling code comes
2295 after. */
2296
2297 /* #define PROFILE_BEFORE_PROLOGUE */
2298
2299 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2300 the stack pointer does not matter. The value is tested only in
2301 functions that have frame pointers.
2302 No definition is equivalent to always zero. */
2303
2304 #define EXIT_IGNORE_STACK 1
2305
2306 \f
2307 /* Trampolines are a block of code followed by two pointers. */
2308
2309 #define TRAMPOLINE_SIZE \
2310 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2311
2312 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2313 pointers from a single LUI base. */
2314
2315 #define TRAMPOLINE_ALIGNMENT 64
2316
2317 /* mips_trampoline_init calls this library function to flush
2318 program and data caches. */
2319
2320 #ifndef CACHE_FLUSH_FUNC
2321 #define CACHE_FLUSH_FUNC "_flush_cache"
2322 #endif
2323
2324 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2325 /* Flush both caches. We need to flush the data cache in case \
2326 the system has a write-back cache. */ \
2327 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2328 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2329 GEN_INT (3), TYPE_MODE (integer_type_node))
2330
2331 \f
2332 /* Addressing modes, and classification of registers for them. */
2333
2334 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2335 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2336 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2337
2338 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2339 and check its validity for a certain class.
2340 We have two alternate definitions for each of them.
2341 The usual definition accepts all pseudo regs; the other rejects them all.
2342 The symbol REG_OK_STRICT causes the latter definition to be used.
2343
2344 Most source files want to accept pseudo regs in the hope that
2345 they will get allocated to the class that the insn wants them to be in.
2346 Some source files that are used after register allocation
2347 need to be strict. */
2348
2349 #ifndef REG_OK_STRICT
2350 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2351 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2352 #else
2353 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2354 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2355 #endif
2356
2357 #define REG_OK_FOR_INDEX_P(X) 0
2358
2359 \f
2360 /* Maximum number of registers that can appear in a valid memory address. */
2361
2362 #define MAX_REGS_PER_ADDRESS 1
2363
2364 /* Check for constness inline but use mips_legitimate_address_p
2365 to check whether a constant really is an address. */
2366
2367 #define CONSTANT_ADDRESS_P(X) \
2368 (CONSTANT_P (X) && memory_address_p (SImode, X))
2369
2370 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2371
2372 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2373 'the start of the function that this code is output in'. */
2374
2375 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2376 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2377 asm_fprintf ((FILE), "%U%s", \
2378 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2379 else \
2380 asm_fprintf ((FILE), "%U%s", (NAME))
2381 \f
2382 /* Flag to mark a function decl symbol that requires a long call. */
2383 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2384 #define SYMBOL_REF_LONG_CALL_P(X) \
2385 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2386
2387 /* This flag marks functions that cannot be lazily bound. */
2388 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2389 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2390 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2391
2392 /* True if we're generating a form of MIPS16 code in which jump tables
2393 are stored in the text section and encoded as 16-bit PC-relative
2394 offsets. This is only possible when general text loads are allowed,
2395 since the table access itself will be an "lh" instruction. */
2396 /* ??? 16-bit offsets can overflow in large functions. */
2397 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2398
2399 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2400
2401 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2402
2403 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2404
2405 /* Define this as 1 if `char' should by default be signed; else as 0. */
2406 #ifndef DEFAULT_SIGNED_CHAR
2407 #define DEFAULT_SIGNED_CHAR 1
2408 #endif
2409
2410 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2411 we generally don't want to use them for copying arbitrary data.
2412 A single N-word move is usually the same cost as N single-word moves. */
2413 #define MOVE_MAX UNITS_PER_WORD
2414 #define MAX_MOVE_MAX 8
2415
2416 /* Define this macro as a C expression which is nonzero if
2417 accessing less than a word of memory (i.e. a `char' or a
2418 `short') is no faster than accessing a word of memory, i.e., if
2419 such access require more than one instruction or if there is no
2420 difference in cost between byte and (aligned) word loads.
2421
2422 On RISC machines, it tends to generate better code to define
2423 this as 1, since it avoids making a QI or HI mode register.
2424
2425 But, generating word accesses for -mips16 is generally bad as shifts
2426 (often extended) would be needed for byte accesses. */
2427 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2428
2429 /* Standard MIPS integer shifts truncate the shift amount to the
2430 width of the shifted operand. However, Loongson vector shifts
2431 do not truncate the shift amount at all. */
2432 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_2EF)
2433
2434 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2435 is done just by pretending it is already truncated. */
2436 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2437 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2438
2439
2440 /* Specify the machine mode that pointers have.
2441 After generation of rtl, the compiler makes no further distinction
2442 between pointers and any other objects of this machine mode. */
2443
2444 #ifndef Pmode
2445 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2446 #endif
2447
2448 /* Give call MEMs SImode since it is the "most permissive" mode
2449 for both 32-bit and 64-bit targets. */
2450
2451 #define FUNCTION_MODE SImode
2452
2453 \f
2454
2455 /* Define if copies to/from condition code registers should be avoided.
2456
2457 This is needed for the MIPS because reload_outcc is not complete;
2458 it needs to handle cases where the source is a general or another
2459 condition code register. */
2460 #define AVOID_CCMODE_COPIES
2461
2462 /* A C expression for the cost of a branch instruction. A value of
2463 1 is the default; other values are interpreted relative to that. */
2464
2465 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2466 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2467
2468 /* If defined, modifies the length assigned to instruction INSN as a
2469 function of the context in which it is used. LENGTH is an lvalue
2470 that contains the initially computed length of the insn and should
2471 be updated with the correct length of the insn. */
2472 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2473 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2474
2475 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2476 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2477 its operands. */
2478 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2479 "%*" OPCODE "%?\t" OPERANDS "%/"
2480
2481 /* Return an asm string that forces INSN to be treated as an absolute
2482 J or JAL instruction instead of an assembler macro. */
2483 #define MIPS_ABSOLUTE_JUMP(INSN) \
2484 (TARGET_ABICALLS_PIC2 \
2485 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2486 : INSN)
2487
2488 /* Return the asm template for a call. INSN is the instruction's mnemonic
2489 ("j" or "jal"), OPERANDS are its operands, TARGET_OPNO is the operand
2490 number of the target. SIZE_OPNO is the operand number of the argument size
2491 operand that can optionally hold the call attributes. If SIZE_OPNO is not
2492 -1 and the call is indirect, use the function symbol from the call
2493 attributes to attach a R_MIPS_JALR relocation to the call.
2494
2495 When generating GOT code without explicit relocation operators,
2496 all calls should use assembly macros. Otherwise, all indirect
2497 calls should use "jr" or "jalr"; we will arrange to restore $gp
2498 afterwards if necessary. Finally, we can only generate direct
2499 calls for -mabicalls by temporarily switching to non-PIC mode. */
2500 #define MIPS_CALL(INSN, OPERANDS, TARGET_OPNO, SIZE_OPNO) \
2501 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2502 ? "%*" INSN "\t%" #TARGET_OPNO "%/" \
2503 : (REG_P (OPERANDS[TARGET_OPNO]) \
2504 && mips_get_pic_call_symbol (OPERANDS, SIZE_OPNO)) \
2505 ? ("%*.reloc\t1f,R_MIPS_JALR,%" #SIZE_OPNO "\n" \
2506 "1:\t" INSN "r\t%" #TARGET_OPNO "%/") \
2507 : REG_P (OPERANDS[TARGET_OPNO]) \
2508 ? "%*" INSN "r\t%" #TARGET_OPNO "%/" \
2509 : MIPS_ABSOLUTE_JUMP ("%*" INSN "\t%" #TARGET_OPNO "%/"))
2510 \f
2511 /* Control the assembler format that we output. */
2512
2513 /* Output to assembler file text saying following lines
2514 may contain character constants, extra white space, comments, etc. */
2515
2516 #ifndef ASM_APP_ON
2517 #define ASM_APP_ON " #APP\n"
2518 #endif
2519
2520 /* Output to assembler file text saying following lines
2521 no longer contain unusual constructs. */
2522
2523 #ifndef ASM_APP_OFF
2524 #define ASM_APP_OFF " #NO_APP\n"
2525 #endif
2526
2527 #define REGISTER_NAMES \
2528 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2529 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2530 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2531 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2532 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2533 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2534 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2535 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2536 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2537 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2538 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2539 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2540 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2541 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2542 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2543 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2544 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2545 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2546 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2547 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2548 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2549 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2550 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2551 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2552
2553 /* List the "software" names for each register. Also list the numerical
2554 names for $fp and $sp. */
2555
2556 #define ADDITIONAL_REGISTER_NAMES \
2557 { \
2558 { "$29", 29 + GP_REG_FIRST }, \
2559 { "$30", 30 + GP_REG_FIRST }, \
2560 { "at", 1 + GP_REG_FIRST }, \
2561 { "v0", 2 + GP_REG_FIRST }, \
2562 { "v1", 3 + GP_REG_FIRST }, \
2563 { "a0", 4 + GP_REG_FIRST }, \
2564 { "a1", 5 + GP_REG_FIRST }, \
2565 { "a2", 6 + GP_REG_FIRST }, \
2566 { "a3", 7 + GP_REG_FIRST }, \
2567 { "t0", 8 + GP_REG_FIRST }, \
2568 { "t1", 9 + GP_REG_FIRST }, \
2569 { "t2", 10 + GP_REG_FIRST }, \
2570 { "t3", 11 + GP_REG_FIRST }, \
2571 { "t4", 12 + GP_REG_FIRST }, \
2572 { "t5", 13 + GP_REG_FIRST }, \
2573 { "t6", 14 + GP_REG_FIRST }, \
2574 { "t7", 15 + GP_REG_FIRST }, \
2575 { "s0", 16 + GP_REG_FIRST }, \
2576 { "s1", 17 + GP_REG_FIRST }, \
2577 { "s2", 18 + GP_REG_FIRST }, \
2578 { "s3", 19 + GP_REG_FIRST }, \
2579 { "s4", 20 + GP_REG_FIRST }, \
2580 { "s5", 21 + GP_REG_FIRST }, \
2581 { "s6", 22 + GP_REG_FIRST }, \
2582 { "s7", 23 + GP_REG_FIRST }, \
2583 { "t8", 24 + GP_REG_FIRST }, \
2584 { "t9", 25 + GP_REG_FIRST }, \
2585 { "k0", 26 + GP_REG_FIRST }, \
2586 { "k1", 27 + GP_REG_FIRST }, \
2587 { "gp", 28 + GP_REG_FIRST }, \
2588 { "sp", 29 + GP_REG_FIRST }, \
2589 { "fp", 30 + GP_REG_FIRST }, \
2590 { "ra", 31 + GP_REG_FIRST }, \
2591 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2592 }
2593
2594 /* This is meant to be redefined in the host dependent files. It is a
2595 set of alternative names and regnums for mips coprocessors. */
2596
2597 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2598
2599 #define DBR_OUTPUT_SEQEND(STREAM) \
2600 do \
2601 { \
2602 /* Undo the effect of '%*'. */ \
2603 mips_pop_asm_switch (&mips_nomacro); \
2604 mips_pop_asm_switch (&mips_noreorder); \
2605 /* Emit a blank line after the delay slot for emphasis. */ \
2606 fputs ("\n", STREAM); \
2607 } \
2608 while (0)
2609
2610 /* mips-tfile does not understand .stabd directives. */
2611 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2612 dbxout_begin_stabn_sline (LINE); \
2613 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2614 } while (0)
2615
2616 /* Use .loc directives for SDB line numbers. */
2617 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2618 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2619
2620 /* The MIPS implementation uses some labels for its own purpose. The
2621 following lists what labels are created, and are all formed by the
2622 pattern $L[a-z].*. The machine independent portion of GCC creates
2623 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2624
2625 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2626 $Lb[0-9]+ Begin blocks for MIPS debug support
2627 $Lc[0-9]+ Label for use in s<xx> operation.
2628 $Le[0-9]+ End blocks for MIPS debug support */
2629
2630 #undef ASM_DECLARE_OBJECT_NAME
2631 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2632 mips_declare_object (STREAM, NAME, "", ":\n")
2633
2634 /* Globalizing directive for a label. */
2635 #define GLOBAL_ASM_OP "\t.globl\t"
2636
2637 /* This says how to define a global common symbol. */
2638
2639 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2640
2641 /* This says how to define a local common symbol (i.e., not visible to
2642 linker). */
2643
2644 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2645 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2646 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2647 #endif
2648
2649 /* This says how to output an external. It would be possible not to
2650 output anything and let undefined symbol become external. However
2651 the assembler uses length information on externals to allocate in
2652 data/sdata bss/sbss, thereby saving exec time. */
2653
2654 #undef ASM_OUTPUT_EXTERNAL
2655 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2656 mips_output_external(STREAM,DECL,NAME)
2657
2658 /* This is how to declare a function name. The actual work of
2659 emitting the label is moved to function_prologue, so that we can
2660 get the line number correctly emitted before the .ent directive,
2661 and after any .file directives. Define as empty so that the function
2662 is not declared before the .ent directive elsewhere. */
2663
2664 #undef ASM_DECLARE_FUNCTION_NAME
2665 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2666
2667 /* This is how to store into the string LABEL
2668 the symbol_ref name of an internal numbered label where
2669 PREFIX is the class of label and NUM is the number within the class.
2670 This is suitable for output with `assemble_name'. */
2671
2672 #undef ASM_GENERATE_INTERNAL_LABEL
2673 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2674 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2675
2676 /* Print debug labels as "foo = ." rather than "foo:" because they should
2677 represent a byte pointer rather than an ISA-encoded address. This is
2678 particularly important for code like:
2679
2680 $LFBxxx = .
2681 .cfi_startproc
2682 ...
2683 .section .gcc_except_table,...
2684 ...
2685 .uleb128 foo-$LFBxxx
2686
2687 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2688 likewise a byte pointer rather than an ISA-encoded address.
2689
2690 At the time of writing, this hook is not used for the function end
2691 label:
2692
2693 $LFExxx:
2694 .end foo
2695
2696 But this doesn't matter, because GAS doesn't treat a pre-.end label
2697 as a MIPS16 one anyway. */
2698
2699 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2700 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2701
2702 /* This is how to output an element of a case-vector that is absolute. */
2703
2704 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2705 fprintf (STREAM, "\t%s\t%sL%d\n", \
2706 ptr_mode == DImode ? ".dword" : ".word", \
2707 LOCAL_LABEL_PREFIX, \
2708 VALUE)
2709
2710 /* This is how to output an element of a case-vector. We can make the
2711 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2712 is supported. */
2713
2714 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2715 do { \
2716 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2717 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2718 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2719 else if (TARGET_GPWORD) \
2720 fprintf (STREAM, "\t%s\t%sL%d\n", \
2721 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2722 LOCAL_LABEL_PREFIX, VALUE); \
2723 else if (TARGET_RTP_PIC) \
2724 { \
2725 /* Make the entry relative to the start of the function. */ \
2726 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2727 fprintf (STREAM, "\t%s\t%sL%d-", \
2728 Pmode == DImode ? ".dword" : ".word", \
2729 LOCAL_LABEL_PREFIX, VALUE); \
2730 assemble_name (STREAM, XSTR (fnsym, 0)); \
2731 fprintf (STREAM, "\n"); \
2732 } \
2733 else \
2734 fprintf (STREAM, "\t%s\t%sL%d\n", \
2735 ptr_mode == DImode ? ".dword" : ".word", \
2736 LOCAL_LABEL_PREFIX, VALUE); \
2737 } while (0)
2738
2739 /* This is how to output an assembler line
2740 that says to advance the location counter
2741 to a multiple of 2**LOG bytes. */
2742
2743 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2744 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2745
2746 /* This is how to output an assembler line to advance the location
2747 counter by SIZE bytes. */
2748
2749 #undef ASM_OUTPUT_SKIP
2750 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2751 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2752
2753 /* This is how to output a string. */
2754 #undef ASM_OUTPUT_ASCII
2755 #define ASM_OUTPUT_ASCII mips_output_ascii
2756
2757 /* Output #ident as a in the read-only data section. */
2758 #undef ASM_OUTPUT_IDENT
2759 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2760 { \
2761 const char *p = STRING; \
2762 int size = strlen (p) + 1; \
2763 switch_to_section (readonly_data_section); \
2764 assemble_string (p, size); \
2765 }
2766 \f
2767 /* Default to -G 8 */
2768 #ifndef MIPS_DEFAULT_GVALUE
2769 #define MIPS_DEFAULT_GVALUE 8
2770 #endif
2771
2772 /* Define the strings to put out for each section in the object file. */
2773 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2774 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2775
2776 #undef READONLY_DATA_SECTION_ASM_OP
2777 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2778 \f
2779 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2780 do \
2781 { \
2782 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2783 TARGET_64BIT ? "daddiu" : "addiu", \
2784 reg_names[STACK_POINTER_REGNUM], \
2785 reg_names[STACK_POINTER_REGNUM], \
2786 TARGET_64BIT ? "sd" : "sw", \
2787 reg_names[REGNO], \
2788 reg_names[STACK_POINTER_REGNUM]); \
2789 } \
2790 while (0)
2791
2792 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2793 do \
2794 { \
2795 mips_push_asm_switch (&mips_noreorder); \
2796 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2797 TARGET_64BIT ? "ld" : "lw", \
2798 reg_names[REGNO], \
2799 reg_names[STACK_POINTER_REGNUM], \
2800 TARGET_64BIT ? "daddu" : "addu", \
2801 reg_names[STACK_POINTER_REGNUM], \
2802 reg_names[STACK_POINTER_REGNUM]); \
2803 mips_pop_asm_switch (&mips_noreorder); \
2804 } \
2805 while (0)
2806
2807 /* How to start an assembler comment.
2808 The leading space is important (the mips native assembler requires it). */
2809 #ifndef ASM_COMMENT_START
2810 #define ASM_COMMENT_START " #"
2811 #endif
2812 \f
2813 /* Default definitions for size_t and ptrdiff_t. We must override the
2814 definitions from ../svr4.h on mips-*-linux-gnu. */
2815
2816 #undef SIZE_TYPE
2817 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2818
2819 #undef PTRDIFF_TYPE
2820 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2821
2822 /* The maximum number of bytes that can be copied by one iteration of
2823 a movmemsi loop; see mips_block_move_loop. */
2824 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2825 (UNITS_PER_WORD * 4)
2826
2827 /* The maximum number of bytes that can be copied by a straight-line
2828 implementation of movmemsi; see mips_block_move_straight. We want
2829 to make sure that any loop-based implementation will iterate at
2830 least twice. */
2831 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2832 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2833
2834 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2835 values were determined experimentally by benchmarking with CSiBE.
2836 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2837 for o32 where we have to restore $gp afterwards as well as make an
2838 indirect call), but in practice, bumping this up higher for
2839 TARGET_ABICALLS doesn't make much difference to code size. */
2840
2841 #define MIPS_CALL_RATIO 8
2842
2843 /* Any loop-based implementation of movmemsi will have at least
2844 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2845 moves, so allow individual copies of fewer elements.
2846
2847 When movmemsi is not available, use a value approximating
2848 the length of a memcpy call sequence, so that move_by_pieces
2849 will generate inline code if it is shorter than a function call.
2850 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2851 we'll have to generate a load/store pair for each, halve the
2852 value of MIPS_CALL_RATIO to take that into account. */
2853
2854 #define MOVE_RATIO(speed) \
2855 (HAVE_movmemsi \
2856 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2857 : MIPS_CALL_RATIO / 2)
2858
2859 /* movmemsi is meant to generate code that is at least as good as
2860 move_by_pieces. However, movmemsi effectively uses a by-pieces
2861 implementation both for moves smaller than a word and for word-aligned
2862 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2863 allow the tree-level optimisers to do such moves by pieces, as it
2864 often exposes other optimization opportunities. We might as well
2865 continue to use movmemsi at the rtl level though, as it produces
2866 better code when scheduling is disabled (such as at -O). */
2867
2868 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2869 (HAVE_movmemsi \
2870 ? (!currently_expanding_to_rtl \
2871 && ((ALIGN) < BITS_PER_WORD \
2872 ? (SIZE) < UNITS_PER_WORD \
2873 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2874 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2875 < (unsigned int) MOVE_RATIO (false)))
2876
2877 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2878 of the length of a memset call, but use the default otherwise. */
2879
2880 #define CLEAR_RATIO(speed)\
2881 ((speed) ? 15 : MIPS_CALL_RATIO)
2882
2883 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2884 optimizing for size adjust the ratio to account for the overhead of
2885 loading the constant and replicating it across the word. */
2886
2887 #define SET_RATIO(speed) \
2888 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2889
2890 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2891 in that case each word takes 3 insns (lui, ori, sw), or more in
2892 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2893 and let the move_by_pieces code copy the string from read-only
2894 memory. In the future, this could be tuned further for multi-issue
2895 CPUs that can issue stores down one pipe and arithmetic instructions
2896 down another; in that case, the lui/ori/sw combination would be a
2897 win for long enough strings. */
2898
2899 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2900 \f
2901 #ifndef __mips16
2902 /* Since the bits of the _init and _fini function is spread across
2903 many object files, each potentially with its own GP, we must assume
2904 we need to load our GP. We don't preserve $gp or $ra, since each
2905 init/fini chunk is supposed to initialize $gp, and crti/crtn
2906 already take care of preserving $ra and, when appropriate, $gp. */
2907 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2908 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2909 asm (SECTION_OP "\n\
2910 .set noreorder\n\
2911 bal 1f\n\
2912 nop\n\
2913 1: .cpload $31\n\
2914 .set reorder\n\
2915 jal " USER_LABEL_PREFIX #FUNC "\n\
2916 " TEXT_SECTION_ASM_OP);
2917 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2918 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2919 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2920 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2921 asm (SECTION_OP "\n\
2922 .set noreorder\n\
2923 bal 1f\n\
2924 nop\n\
2925 1: .set reorder\n\
2926 .cpsetup $31, $2, 1b\n\
2927 jal " USER_LABEL_PREFIX #FUNC "\n\
2928 " TEXT_SECTION_ASM_OP);
2929 #endif
2930 #endif
2931
2932 #ifndef HAVE_AS_TLS
2933 #define HAVE_AS_TLS 0
2934 #endif
2935
2936 #ifndef USED_FOR_TARGET
2937 /* Information about ".set noFOO; ...; .set FOO" blocks. */
2938 struct mips_asm_switch {
2939 /* The FOO in the description above. */
2940 const char *name;
2941
2942 /* The current block nesting level, or 0 if we aren't in a block. */
2943 int nesting_level;
2944 };
2945
2946 extern const enum reg_class mips_regno_to_class[];
2947 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
2948 extern const char *current_function_file; /* filename current function is in */
2949 extern int num_source_filenames; /* current .file # */
2950 extern struct mips_asm_switch mips_noreorder;
2951 extern struct mips_asm_switch mips_nomacro;
2952 extern struct mips_asm_switch mips_noat;
2953 extern int mips_dbx_regno[];
2954 extern int mips_dwarf_regno[];
2955 extern bool mips_split_p[];
2956 extern bool mips_split_hi_p[];
2957 extern enum processor mips_arch; /* which cpu to codegen for */
2958 extern enum processor mips_tune; /* which cpu to schedule for */
2959 extern int mips_isa; /* architectural level */
2960 extern int mips_abi; /* which ABI to use */
2961 extern const struct mips_cpu_info *mips_arch_info;
2962 extern const struct mips_cpu_info *mips_tune_info;
2963 extern bool mips_base_mips16;
2964 extern enum mips_code_readable_setting mips_code_readable;
2965 extern GTY(()) struct target_globals *mips16_globals;
2966 #endif
2967
2968 /* Enable querying of DFA units. */
2969 #define CPU_UNITS_QUERY 1
2970
2971 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2972 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
2973
2974 /* As on most targets, we want the .eh_frame section to be read-only where
2975 possible. And as on most targets, this means two things:
2976
2977 (a) Non-locally-binding pointers must have an indirect encoding,
2978 so that the addresses in the .eh_frame section itself become
2979 locally-binding.
2980
2981 (b) A shared library's .eh_frame section must encode locally-binding
2982 pointers in a relative (relocation-free) form.
2983
2984 However, MIPS has traditionally not allowed directives like:
2985
2986 .long x-.
2987
2988 in cases where "x" is in a different section, or is not defined in the
2989 same assembly file. We are therefore unable to emit the PC-relative
2990 form required by (b) at assembly time.
2991
2992 Fortunately, the linker is able to convert absolute addresses into
2993 PC-relative addresses on our behalf. Unfortunately, only certain
2994 versions of the linker know how to do this for indirect pointers,
2995 and for personality data. We must fall back on using writable
2996 .eh_frame sections for shared libraries if the linker does not
2997 support this feature. */
2998 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
2999 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3000
3001 /* For switching between MIPS16 and non-MIPS16 modes. */
3002 #define SWITCHABLE_TARGET 1
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