gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2014 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VD_RE (CREATE, create, 0)
  43   BUILTIN_VDC (COMBINE, combine, 0)
  44   BUILTIN_VB (BINOP, pmul, 0)
  45   BUILTIN_VDQF (UNOP, sqrt, 2)
  46   BUILTIN_VD_BHSI (BINOP, addp, 0)
  47   VAR1 (UNOP, addp, 0, di)
  48   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
  49
  50   BUILTIN_VALL (GETLANE, get_lane, 0)
  51   VAR1 (GETLANE, get_lane, 0, di)
  52   BUILTIN_VALL (GETLANE, be_checked_get_lane, 0)
  53
  54   BUILTIN_VD_RE (REINTERP, reinterpretdi, 0)
  55   BUILTIN_VDC (REINTERP, reinterpretv8qi, 0)
  56   BUILTIN_VDC (REINTERP, reinterpretv4hi, 0)
  57   BUILTIN_VDC (REINTERP, reinterpretv2si, 0)
  58   BUILTIN_VDC (REINTERP, reinterpretv2sf, 0)
  59   BUILTIN_VQ (REINTERP, reinterpretv16qi, 0)
  60   BUILTIN_VQ (REINTERP, reinterpretv8hi, 0)
  61   BUILTIN_VQ (REINTERP, reinterpretv4si, 0)
  62   BUILTIN_VQ (REINTERP, reinterpretv4sf, 0)
  63   BUILTIN_VQ (REINTERP, reinterpretv2di, 0)
  64   BUILTIN_VQ (REINTERP, reinterpretv2df, 0)
  65
  66   BUILTIN_VDQ_I (BINOP, dup_lane, 0)
  67   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  68   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  69   BUILTIN_VSDQ_I (BINOP, uqshl, 0)
  70   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  71   BUILTIN_VSDQ_I (BINOP, uqrshl, 0)
  72   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  73   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  74   BUILTIN_VSDQ_I (BINOP, uqadd, 0)
  75   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  76   BUILTIN_VSDQ_I (BINOP, uqsub, 0)
  77   /* Implemented by aarch64_<sur>qadd<mode>.  */
  78   BUILTIN_VSDQ_I (BINOP, suqadd, 0)
  79   BUILTIN_VSDQ_I (BINOP, usqadd, 0)
  80
  81   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  82   BUILTIN_VDC (GETLANE, get_dregoi, 0)
  83   BUILTIN_VDC (GETLANE, get_dregci, 0)
  84   BUILTIN_VDC (GETLANE, get_dregxi, 0)
  85   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  86   BUILTIN_VQ (GETLANE, get_qregoi, 0)
  87   BUILTIN_VQ (GETLANE, get_qregci, 0)
  88   BUILTIN_VQ (GETLANE, get_qregxi, 0)
  89   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
  90   BUILTIN_VQ (SETLANE, set_qregoi, 0)
  91   BUILTIN_VQ (SETLANE, set_qregci, 0)
  92   BUILTIN_VQ (SETLANE, set_qregxi, 0)
  93   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
  94   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
  95   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
  96   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
  97   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
  98   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
  99   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
 100   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
 101   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
 102   BUILTIN_VDC (STORESTRUCT, st2, 0)
 103   BUILTIN_VDC (STORESTRUCT, st3, 0)
 104   BUILTIN_VDC (STORESTRUCT, st4, 0)
 105   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
 106   BUILTIN_VQ (STORESTRUCT, st2, 0)
 107   BUILTIN_VQ (STORESTRUCT, st3, 0)
 108   BUILTIN_VQ (STORESTRUCT, st4, 0)
 109
 110   BUILTIN_VQW (BINOP, saddl2, 0)
 111   BUILTIN_VQW (BINOP, uaddl2, 0)
 112   BUILTIN_VQW (BINOP, ssubl2, 0)
 113   BUILTIN_VQW (BINOP, usubl2, 0)
 114   BUILTIN_VQW (BINOP, saddw2, 0)
 115   BUILTIN_VQW (BINOP, uaddw2, 0)
 116   BUILTIN_VQW (BINOP, ssubw2, 0)
 117   BUILTIN_VQW (BINOP, usubw2, 0)
 118   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 119   BUILTIN_VDW (BINOP, saddl, 0)
 120   BUILTIN_VDW (BINOP, uaddl, 0)
 121   BUILTIN_VDW (BINOP, ssubl, 0)
 122   BUILTIN_VDW (BINOP, usubl, 0)
 123   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 124   BUILTIN_VDW (BINOP, saddw, 0)
 125   BUILTIN_VDW (BINOP, uaddw, 0)
 126   BUILTIN_VDW (BINOP, ssubw, 0)
 127   BUILTIN_VDW (BINOP, usubw, 0)
 128   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 129   BUILTIN_VQ_S (BINOP, shadd, 0)
 130   BUILTIN_VQ_S (BINOP, uhadd, 0)
 131   BUILTIN_VQ_S (BINOP, srhadd, 0)
 132   BUILTIN_VQ_S (BINOP, urhadd, 0)
 133   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 134   BUILTIN_VQN (BINOP, addhn, 0)
 135   BUILTIN_VQN (BINOP, raddhn, 0)
 136   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 137   BUILTIN_VQN (TERNOP, addhn2, 0)
 138   BUILTIN_VQN (TERNOP, raddhn2, 0)
 139
 140   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 141   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 142   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 143   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 144   /* Implemented by aarch64_s<optab><mode>.  */
 145   BUILTIN_VSDQ_I_BHSI (UNOP, sqabs, 0)
 146   BUILTIN_VSDQ_I_BHSI (UNOP, sqneg, 0)
 147
 148   BUILTIN_VSD_HSI (QUADOP, sqdmlal_lane, 0)
 149   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_lane, 0)
 150   BUILTIN_VSD_HSI (QUADOP, sqdmlal_laneq, 0)
 151   BUILTIN_VSD_HSI (QUADOP, sqdmlsl_laneq, 0)
 152   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 153   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 154   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_lane, 0)
 155   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_lane, 0)
 156   BUILTIN_VQ_HSI (QUADOP, sqdmlal2_laneq, 0)
 157   BUILTIN_VQ_HSI (QUADOP, sqdmlsl2_laneq, 0)
 158   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 159   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 160   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 161   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 162   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 163   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 164   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 165   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 166
 167   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 168   BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
 169   BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0)
 170   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 171   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 172   BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
 173   BUILTIN_VQ_HSI (TERNOP, sqdmull2_laneq, 0)
 174   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 175   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 176   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 177   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 178   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 179   BUILTIN_VDQHS (TERNOP, sqdmulh_lane, 0)
 180   BUILTIN_VDQHS (TERNOP, sqdmulh_laneq, 0)
 181   BUILTIN_VDQHS (TERNOP, sqrdmulh_lane, 0)
 182   BUILTIN_VDQHS (TERNOP, sqrdmulh_laneq, 0)
 183   BUILTIN_SD_HSI (TERNOP, sqdmulh_lane, 0)
 184   BUILTIN_SD_HSI (TERNOP, sqrdmulh_lane, 0)
 185
 186   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 187   /* Implemented by aarch64_<sur>shl<mode>.  */
 188   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 189   BUILTIN_VSDQ_I_DI (BINOP, ushl, 0)
 190   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 191   BUILTIN_VSDQ_I_DI (BINOP, urshl, 0)
 192
 193   BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
 194   VAR1 (SHIFTIMM, ashr_simd, 0, di)
 195   BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
 196   VAR1 (USHIFTIMM, lshr_simd, 0, di)
 197   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 198   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 199   BUILTIN_VSDQ_I_DI (SHIFTIMM, urshr_n, 0)
 200   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 201   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 202   BUILTIN_VSDQ_I_DI (SHIFTACC, usra_n, 0)
 203   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 204   BUILTIN_VSDQ_I_DI (SHIFTACC, ursra_n, 0)
 205   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 206   BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
 207   BUILTIN_VDW (SHIFTIMM, ushll_n, 0)
 208   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 209   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 210   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 211   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 212   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 213   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 214   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 215   BUILTIN_VSQN_HSDI (SHIFTIMM, uqshrn_n, 0)
 216   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 217   BUILTIN_VSQN_HSDI (SHIFTIMM, uqrshrn_n, 0)
 218   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 219   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 220   BUILTIN_VSDQ_I_DI (SHIFTINSERT, usri_n, 0)
 221   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 222   BUILTIN_VSDQ_I_DI (SHIFTINSERT, usli_n, 0)
 223   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 224   BUILTIN_VSDQ_I (SHIFTIMM, sqshlu_n, 0)
 225   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 226   BUILTIN_VSDQ_I (SHIFTIMM, uqshl_n, 0)
 227
 228   /* Implemented by aarch64_cm<cmp><mode>.  */
 229   BUILTIN_VALLDI (BINOP, cmeq, 0)
 230   BUILTIN_VALLDI (BINOP, cmge, 0)
 231   BUILTIN_VALLDI (BINOP, cmgt, 0)
 232   BUILTIN_VALLDI (BINOP, cmle, 0)
 233   BUILTIN_VALLDI (BINOP, cmlt, 0)
 234   /* Implemented by aarch64_cm<cmp><mode>.  */
 235   BUILTIN_VSDQ_I_DI (BINOP, cmgeu, 0)
 236   BUILTIN_VSDQ_I_DI (BINOP, cmgtu, 0)
 237   BUILTIN_VSDQ_I_DI (BINOP, cmtst, 0)
 238
 239   /* Implemented by reduc_<sur>plus_<mode>.  */
 240   BUILTIN_VALL (UNOP, reduc_splus_, 10)
 241   BUILTIN_VDQ (UNOP, reduc_uplus_, 10)
 242
 243   /* Implemented by reduc_<maxmin_uns>_<mode>.  */
 244   BUILTIN_VDQIF (UNOP, reduc_smax_, 10)
 245   BUILTIN_VDQIF (UNOP, reduc_smin_, 10)
 246   BUILTIN_VDQ_BHSI (UNOP, reduc_umax_, 10)
 247   BUILTIN_VDQ_BHSI (UNOP, reduc_umin_, 10)
 248   BUILTIN_VDQF (UNOP, reduc_smax_nan_, 10)
 249   BUILTIN_VDQF (UNOP, reduc_smin_nan_, 10)
 250
 251   /* Implemented by <maxmin><mode>3.
 252      smax variants map to fmaxnm,
 253      smax_nan variants map to fmax.  */
 254   BUILTIN_VDQIF (BINOP, smax, 3)
 255   BUILTIN_VDQIF (BINOP, smin, 3)
 256   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 257   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 258   BUILTIN_VDQF (BINOP, smax_nan, 3)
 259   BUILTIN_VDQF (BINOP, smin_nan, 3)
 260
 261   /* Implemented by <frint_pattern><mode>2.  */
 262   BUILTIN_VDQF (UNOP, btrunc, 2)
 263   BUILTIN_VDQF (UNOP, ceil, 2)
 264   BUILTIN_VDQF (UNOP, floor, 2)
 265   BUILTIN_VDQF (UNOP, nearbyint, 2)
 266   BUILTIN_VDQF (UNOP, rint, 2)
 267   BUILTIN_VDQF (UNOP, round, 2)
 268   BUILTIN_VDQF (UNOP, frintn, 2)
 269
 270   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
 271   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
 272   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
 273   VAR1 (UNOP, lbtruncv2df, 2, v2di)
 274
 275   VAR1 (UNOP, lbtruncuv2sf, 2, v2si)
 276   VAR1 (UNOP, lbtruncuv4sf, 2, v4si)
 277   VAR1 (UNOP, lbtruncuv2df, 2, v2di)
 278
 279   VAR1 (UNOP, lroundv2sf, 2, v2si)
 280   VAR1 (UNOP, lroundv4sf, 2, v4si)
 281   VAR1 (UNOP, lroundv2df, 2, v2di)
 282   /* Implemented by l<fcvt_pattern><su_optab><GPF:mode><GPI:mode>2.  */
 283   VAR1 (UNOP, lroundsf, 2, si)
 284   VAR1 (UNOP, lrounddf, 2, di)
 285
 286   VAR1 (UNOP, lrounduv2sf, 2, v2si)
 287   VAR1 (UNOP, lrounduv4sf, 2, v4si)
 288   VAR1 (UNOP, lrounduv2df, 2, v2di)
 289   VAR1 (UNOP, lroundusf, 2, si)
 290   VAR1 (UNOP, lroundudf, 2, di)
 291
 292   VAR1 (UNOP, lceilv2sf, 2, v2si)
 293   VAR1 (UNOP, lceilv4sf, 2, v4si)
 294   VAR1 (UNOP, lceilv2df, 2, v2di)
 295
 296   VAR1 (UNOP, lceiluv2sf, 2, v2si)
 297   VAR1 (UNOP, lceiluv4sf, 2, v4si)
 298   VAR1 (UNOP, lceiluv2df, 2, v2di)
 299   VAR1 (UNOP, lceilusf, 2, si)
 300   VAR1 (UNOP, lceiludf, 2, di)
 301
 302   VAR1 (UNOP, lfloorv2sf, 2, v2si)
 303   VAR1 (UNOP, lfloorv4sf, 2, v4si)
 304   VAR1 (UNOP, lfloorv2df, 2, v2di)
 305
 306   VAR1 (UNOP, lflooruv2sf, 2, v2si)
 307   VAR1 (UNOP, lflooruv4sf, 2, v4si)
 308   VAR1 (UNOP, lflooruv2df, 2, v2di)
 309   VAR1 (UNOP, lfloorusf, 2, si)
 310   VAR1 (UNOP, lfloorudf, 2, di)
 311
 312   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
 313   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
 314   VAR1 (UNOP, lfrintnv2df, 2, v2di)
 315   VAR1 (UNOP, lfrintnsf, 2, si)
 316   VAR1 (UNOP, lfrintndf, 2, di)
 317
 318   VAR1 (UNOP, lfrintnuv2sf, 2, v2si)
 319   VAR1 (UNOP, lfrintnuv4sf, 2, v4si)
 320   VAR1 (UNOP, lfrintnuv2df, 2, v2di)
 321   VAR1 (UNOP, lfrintnusf, 2, si)
 322   VAR1 (UNOP, lfrintnudf, 2, di)
 323
 324   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
 325   VAR1 (UNOP, floatv2si, 2, v2sf)
 326   VAR1 (UNOP, floatv4si, 2, v4sf)
 327   VAR1 (UNOP, floatv2di, 2, v2df)
 328
 329   VAR1 (UNOP, floatunsv2si, 2, v2sf)
 330   VAR1 (UNOP, floatunsv4si, 2, v4sf)
 331   VAR1 (UNOP, floatunsv2di, 2, v2df)
 332
 333   /* Implemented by
 334      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 335   BUILTIN_VALL (BINOP, zip1, 0)
 336   BUILTIN_VALL (BINOP, zip2, 0)
 337   BUILTIN_VALL (BINOP, uzp1, 0)
 338   BUILTIN_VALL (BINOP, uzp2, 0)
 339   BUILTIN_VALL (BINOP, trn1, 0)
 340   BUILTIN_VALL (BINOP, trn2, 0)
 341
 342   /* Implemented by
 343      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 344   BUILTIN_GPF (UNOP, frecpe, 0)
 345   BUILTIN_GPF (BINOP, frecps, 0)
 346   BUILTIN_GPF (UNOP, frecpx, 0)
 347
 348   BUILTIN_VDQF (UNOP, frecpe, 0)
 349   BUILTIN_VDQF (BINOP, frecps, 0)
 350
 351   BUILTIN_VALLDI (UNOP, abs, 2)
 352
 353   VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
 354   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
 355
 356   VAR1 (UNOP, float_extend_lo_, 0, v2df)
 357   VAR1 (UNOP, float_truncate_lo_, 0, v2sf)
 358
 359   /* Implemented by aarch64_ld1<VALL:mode>.  */
 360   BUILTIN_VALL (LOAD1, ld1, 0)
 361
 362   /* Implemented by aarch64_st1<VALL:mode>.  */
 363   BUILTIN_VALL (STORE1, st1, 0)
 364
 365   /* Implemented by fma<mode>4.  */
 366   BUILTIN_VDQF (TERNOP, fma, 4)
 367
 368   /* Implemented by aarch64_simd_bsl<mode>.  */
 369   BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
 370   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
 371   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
 372
 373   /* Implemented by aarch64_crypto_aes<op><mode>.  */
 374   VAR1 (BINOPU, crypto_aese, 0, v16qi)
 375   VAR1 (BINOPU, crypto_aesd, 0, v16qi)
 376   VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
 377   VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
 378
 379   /* Implemented by aarch64_crypto_sha1<op><mode>.  */
 380   VAR1 (UNOPU, crypto_sha1h, 0, si)
 381   VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
 382   VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
 383   VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
 384   VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
 385   VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
 386
 387   /* Implemented by aarch64_crypto_sha256<op><mode>.  */
 388   VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
 389   VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
 390   VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
 391   VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
 392
 393   /* Implemented by aarch64_crypto_pmull<mode>.  */
 394   VAR1 (BINOPP, crypto_pmull, 0, di)
 395   VAR1 (BINOPP, crypto_pmull, 0, v2di)