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* target.h (struct gcc_target): Add calls.pass_by_reference.
[official-gcc.git] / gcc / config / sh / sh.h
blobe38361f186a18bfedd00215d31e2c3c5514c736c
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH3: \
52 builtin_define ("__sh3__"); \
53 builtin_define ("__SH3__"); \
54 if (TARGET_HARD_SH4) \
55 builtin_define ("__SH4_NOFPU__"); \
56 break; \
57 case PROCESSOR_SH3E: \
58 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
59 break; \
60 case PROCESSOR_SH4: \
61 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
62 break; \
63 case PROCESSOR_SH5: \
64 { \
65 builtin_define_with_value ("__SH5__", \
66 TARGET_SHMEDIA64 ? "64" : "32", 0); \
67 builtin_define_with_value ("__SHMEDIA__", \
68 TARGET_SHMEDIA ? "1" : "0", 0); \
69 if (! TARGET_FPU_DOUBLE) \
70 builtin_define ("__SH4_NOFPU__"); \
71 } \
72 } \
73 if (TARGET_HITACHI) \
74 builtin_define ("__HITACHI__"); \
75 builtin_define (TARGET_LITTLE_ENDIAN \
76 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
77 if (flag_pic) \
78 { \
79 builtin_define ("__pic__"); \
80 builtin_define ("__PIC__"); \
81 } \
82 } while (0)
83
84 /* We can not debug without a frame pointer. */
85 /* #define CAN_DEBUG_WITHOUT_FP */
86
87 #define CONDITIONAL_REGISTER_USAGE do \
88 { \
89 int regno; \
90 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
91 if (! VALID_REGISTER_P (regno)) \
92 fixed_regs[regno] = call_used_regs[regno] = 1; \
93 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
94 if (TARGET_SH5) \
95 call_used_regs[FIRST_GENERAL_REG + 8] \
96 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
97 if (TARGET_SHMEDIA) \
98 { \
99 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
100 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
101 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
102 } \
103 if (flag_pic) \
104 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
105 /* Renesas saves and restores mac registers on call. */ \
106 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
107 { \
108 call_used_regs[MACH_REG] = 0; \
109 call_used_regs[MACL_REG] = 0; \
110 } \
111 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
112 regno <= LAST_FP_REG; regno += 2) \
113 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
114 if (TARGET_SHMEDIA) \
115 { \
116 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
117 if (! fixed_regs[regno] && call_used_regs[regno]) \
118 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
119 } \
120 else \
121 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
122 if (! fixed_regs[regno] && call_used_regs[regno]) \
123 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
124 } while (0)
125 \f
126 /* ??? Need to write documentation for all SH options and add it to the
127 invoke.texi file. */
128
129 /* Run-time compilation parameters selecting different hardware subsets. */
130
131 extern int target_flags;
132 #define ISIZE_BIT (1<<1)
133 #define DALIGN_BIT (1<<6)
134 #define SH1_BIT (1<<8)
135 #define SH2_BIT (1<<9)
136 #define SH3_BIT (1<<10)
137 #define SH_E_BIT (1<<11)
138 #define HARD_SH4_BIT (1<<5)
139 #define FPU_SINGLE_BIT (1<<7)
140 #define SH4_BIT (1<<12)
141 #define FMOVD_BIT (1<<4)
142 #define SH5_BIT (1<<0)
143 #define SPACE_BIT (1<<13)
144 #define BIGTABLE_BIT (1<<14)
145 #define RELAX_BIT (1<<15)
146 #define USERMODE_BIT (1<<16)
147 #define HITACHI_BIT (1<<22)
148 #define NOMACSAVE_BIT (1<<23)
149 #define PREFERGOT_BIT (1<<24)
150 #define PADSTRUCT_BIT (1<<28)
151 #define LITTLE_ENDIAN_BIT (1<<29)
152 #define IEEE_BIT (1<<30)
153 #define SAVE_ALL_TR_BIT (1<<2)
154
155 /* Nonzero if this is an ELF target - compile time only */
156 #define TARGET_ELF 0
157
158 /* Nonzero if we should dump out instruction size info. */
159 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
160
161 /* Nonzero to align doubles on 64 bit boundaries. */
162 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
163
164 /* Nonzero if we should generate code using type 1 insns. */
165 #define TARGET_SH1 (target_flags & SH1_BIT)
166
167 /* Nonzero if we should generate code using type 2 insns. */
168 #define TARGET_SH2 (target_flags & SH2_BIT)
169
170 /* Nonzero if we should generate code using type 2E insns. */
171 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
172
173 /* Nonzero if we should generate code using type 3 insns. */
174 #define TARGET_SH3 (target_flags & SH3_BIT)
175
176 /* Nonzero if we should generate code using type 3E insns. */
177 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
178
179 /* Nonzero if the cache line size is 32. */
180 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
181
182 /* Nonzero if we schedule for a superscalar implementation. */
183 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
184
185 /* Nonzero if the target has separate instruction and data caches. */
186 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
187
188 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
189 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
190
191 /* Nonzero if the default precision of th FPU is single */
192 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
193
194 /* Nonzero if a double-precision FPU is available. */
195 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
196
197 /* Nonzero if an FPU is available. */
198 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
199
200 /* Nonzero if we should generate code using type 4 insns. */
201 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
202
203 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
204 #define TARGET_SH5 (target_flags & SH5_BIT)
205
206 /* Nonzero if we should generate code using the SHcompact instruction
207 set and 32-bit ABI. */
208 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
209
210 /* Nonzero if we should generate code using the SHmedia instruction
211 set and ABI. */
212 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
213
214 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
215 ABI. */
216 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
217 && (target_flags & SH_E_BIT))
218
219 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
220 ABI. */
221 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
222 && ! (target_flags & SH_E_BIT))
223
224 /* Nonzero if we should generate code using SHmedia FPU instructions. */
225 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
226 /* Nonzero if we should generate fmovd. */
227 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
228
229 /* Nonzero if we respect NANs. */
230 #define TARGET_IEEE (target_flags & IEEE_BIT)
231
232 /* Nonzero if we should generate smaller code rather than faster code. */
233 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
234
235 /* Nonzero to use long jump tables. */
236 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
237
238 /* Nonzero to generate pseudo-ops needed by the assembler and linker
239 to do function call relaxing. */
240 #define TARGET_RELAX (target_flags & RELAX_BIT)
241
242 /* Nonzero if using Renesas's calling convention. */
243 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
244
245 /* Nonzero if not saving macl/mach when using -mhitachi */
246 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
247
248 /* Nonzero if padding structures to a multiple of 4 bytes. This is
249 incompatible with Renesas's compiler, and gives unusual structure layouts
250 which confuse programmers.
251 ??? This option is not useful, but is retained in case there are people
252 who are still relying on it. It may be deleted in the future. */
253 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
254
255 /* Nonzero if generating code for a little endian SH. */
256 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
257
258 /* Nonzero if we should do everything in userland. */
259 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
260
261 /* Nonzero if we should prefer @GOT calls when generating PIC. */
262 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
263
264 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
265
266 /* This is not used by the SH2E calling convention */
267 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
268 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
269 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
270
271 #ifndef TARGET_CPU_DEFAULT
272 #define TARGET_CPU_DEFAULT SELECT_SH1
273 #define SUPPORT_SH1
274 #define SUPPORT_SH2E
275 #define SUPPORT_SH4
276 #define SUPPORT_SH4_SINGLE
277 #endif
278
279 #define SELECT_SH1 (SH1_BIT)
280 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
281 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
282 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
283 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
284 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
285 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
286 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
287 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
288 #define SELECT_SH5_64MEDIA (SH5_BIT | SH4_BIT)
289 #define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
290 #define SELECT_SH5_32MEDIA (SH5_BIT | SH4_BIT | SH_E_BIT)
291 #define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
292 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
293 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
294
295 /* Disable processor switches for which we have no suitable multilibs. */
296 #ifndef SUPPORT_SH1
297 #define TARGET_SWITCH_SH1
298 #ifndef SUPPORT_SH2
299 #define TARGET_SWITCH_SH2
300 #ifndef SUPPORT_SH3
301 #define TARGET_SWITCH_SH3
302 #ifndef SUPPORT_SH4_NOFPU
303 #define TARGET_SWITCH_SH4_NOFPU
304 #endif
305 #endif
306 #endif
307 #endif
308
309 #ifndef SUPPORT_SH2E
310 #define TARGET_SWITCH_SH2E
311 #ifndef SUPPORT_SH3E
312 #define TARGET_SWITCH_SH3E
313 #ifndef SUPPORT_SH4_SINGLE_ONLY
314 #define TARGET_SWITCH_SH4_SINGLE_ONLY
315 #endif
316 #endif
317 #endif
318
319 #ifndef SUPPORT_SH4
320 #define TARGET_SWITCH_SH4
321 #endif
322
323 #ifndef SUPPORT_SH4_SINGLE
324 #define TARGET_SWITCH_SH4_SINGLE
325 #endif
326
327 #ifndef SUPPORT_SH5_64MEDIA
328 #define TARGET_SWITCH_SH5_64MEDIA
329 #endif
330
331 #ifndef SUPPORT_SH5_64MEDIA_NOFPU
332 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU
333 #endif
334
335 #if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
336 #define TARGET_SWITCHES_SH5_32MEDIA
337 #endif
338
339 #if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
340 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
341 #endif
342
343 /* Reset all target-selection flags. */
344 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
345 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
346
347 #ifndef TARGET_SWITCH_SH1
348 #define TARGET_SWITCH_SH1 \
349 {"1", TARGET_NONE, "" }, \
350 {"1", SELECT_SH1, "Generate SH1 code" },
351 #endif
352 #ifndef TARGET_SWITCH_SH2
353 #define TARGET_SWITCH_SH2 \
354 {"2", TARGET_NONE, "" }, \
355 {"2", SELECT_SH2, "Generate SH2 code" },
356 #endif
357 #ifndef TARGET_SWITCH_SH2E
358 #define TARGET_SWITCH_SH2E \
359 {"2e", TARGET_NONE, "" }, \
360 {"2e", SELECT_SH2E, "Generate SH2e code" },
361 #endif
362 #ifndef TARGET_SWITCH_SH3
363 #define TARGET_SWITCH_SH3 \
364 {"3", TARGET_NONE, "" }, \
365 {"3", SELECT_SH3, "Generate SH3 code" },
366 #endif
367 #ifndef TARGET_SWITCH_SH3E
368 #define TARGET_SWITCH_SH3E \
369 {"3e", TARGET_NONE, "" }, \
370 {"3e", SELECT_SH3E, "Generate SH3e code" },
371 #endif
372 #ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
373 #define TARGET_SWITCH_SH4_SINGLE_ONLY \
374 {"4-single-only", TARGET_NONE, "" }, \
375 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
376 #endif
377 #ifndef TARGET_SWITCH_SH4_SINGLE
378 #define TARGET_SWITCH_SH4_SINGLE \
379 {"4-single", TARGET_NONE, "" }, \
380 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
381 #endif
382 #ifndef TARGET_SWITCH_SH4_NOFPU
383 #define TARGET_SWITCH_SH4_NOFPU \
384 {"4-nofpu", TARGET_NONE, "" }, \
385 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
386 #endif
387 #ifndef TARGET_SWITCH_SH4
388 #define TARGET_SWITCH_SH4 \
389 {"4", TARGET_NONE, "" }, \
390 {"4", SELECT_SH4, "Generate SH4 code" },
391 #endif
392 #ifndef TARGET_SWITCH_SH5_64MEDIA
393 #define TARGET_SWITCH_SH5_64MEDIA \
394 {"5-64media", TARGET_NONE, "" }, \
395 {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
396 #endif
397 #ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
398 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
399 {"5-64media-nofpu", TARGET_NONE, "" }, \
400 {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
401 #endif
402 #ifndef TARGET_SWITCHES_SH5_32MEDIA
403 #define TARGET_SWITCHES_SH5_32MEDIA \
404 {"5-32media", TARGET_NONE, "" }, \
405 {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
406 {"5-compact", TARGET_NONE, "" }, \
407 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" },
408 #endif
409 #ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
410 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
411 {"5-32media-nofpu", TARGET_NONE, "" }, \
412 {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
413 {"5-compact-nofpu", TARGET_NONE, "" }, \
414 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
415 #endif
416
417 #define TARGET_SWITCHES \
418 { TARGET_SWITCH_SH1 \
419 TARGET_SWITCH_SH2 \
420 TARGET_SWITCH_SH2E \
421 TARGET_SWITCH_SH3 \
422 TARGET_SWITCH_SH3E \
423 TARGET_SWITCH_SH4_SINGLE_ONLY \
424 TARGET_SWITCH_SH4_SINGLE \
425 TARGET_SWITCH_SH4_NOFPU \
426 TARGET_SWITCH_SH4 \
427 TARGET_SWITCH_SH5_64MEDIA \
428 TARGET_SWITCH_SH5_64MEDIA_NOFPU \
429 TARGET_SWITCHES_SH5_32MEDIA \
430 TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
431 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
432 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
433 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
434 {"fmovd", FMOVD_BIT, "" }, \
435 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
436 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
437 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
438 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
439 {"isize", ISIZE_BIT, "" }, \
440 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
441 {"no-ieee", -IEEE_BIT, "" }, \
442 {"padstruct", PADSTRUCT_BIT, "" }, \
443 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
444 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
445 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
446 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
447 SUBTARGET_SWITCHES \
448 {"", TARGET_DEFAULT, "" } \
449 }
450
451 /* This are meant to be redefined in the host dependent files */
452 #define SUBTARGET_SWITCHES
453
454 /* This defaults us to big-endian. */
455 #ifndef TARGET_ENDIAN_DEFAULT
456 #define TARGET_ENDIAN_DEFAULT 0
457 #endif
458
459 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
460
461 #ifndef SH_MULTILIB_CPU_DEFAULT
462 #define SH_MULTILIB_CPU_DEFAULT "m1"
463 #endif
464
465 #if TARGET_ENDIAN_DEFAULT
466 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
467 #else
468 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
469 #endif
470
471 #define CPP_SPEC " %(subtarget_cpp_spec) "
472
473 #ifndef SUBTARGET_CPP_SPEC
474 #define SUBTARGET_CPP_SPEC ""
475 #endif
476
477 #ifndef SUBTARGET_EXTRA_SPECS
478 #define SUBTARGET_EXTRA_SPECS
479 #endif
480
481 #define EXTRA_SPECS \
482 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
483 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
484 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
485 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
486 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
487 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
488 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
489 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
490 SUBTARGET_EXTRA_SPECS
491
492 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
493 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
494 #else
495 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
496 #endif
497
498 #define SH_ASM_SPEC \
499 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
500 %(subtarget_asm_isa_spec)"
501
502 #define ASM_SPEC SH_ASM_SPEC
503
504 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
505 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
506 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
507 #else
508 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
509 #endif
510 #endif
511
512 #define SUBTARGET_ASM_ISA_SPEC ""
513
514 #define LINK_EMUL_PREFIX "sh%{ml:l}"
515
516 #if TARGET_CPU_DEFAULT & SH5_BIT
517 #if TARGET_CPU_DEFAULT & SH_E_BIT
518 #define LINK_DEFAULT_CPU_EMUL "32"
519 #if TARGET_CPU_DEFAULT & SH1_BIT
520 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
521 #else
522 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
523 #endif /* SH1_BIT */
524 #else /* !SH_E_BIT */
525 #define LINK_DEFAULT_CPU_EMUL "64"
526 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
527 #endif /* SH_E_BIT */
528 #define ASM_ISA_DEFAULT_SPEC \
529 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
530 #else /* !SH5_BIT */
531 #define LINK_DEFAULT_CPU_EMUL ""
532 #define ASM_ISA_DEFAULT_SPEC ""
533 #endif /* SH5_BIT */
534
535 #define SUBTARGET_LINK_EMUL_SUFFIX ""
536 #define SUBTARGET_LINK_SPEC ""
537
538 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
539 so that we can undo the damage without code replication. */
540 #define LINK_SPEC SH_LINK_SPEC
541
542 #define SH_LINK_SPEC "\
543 -m %(link_emul_prefix)\
544 %{m5-compact*|m5-32media*:32}\
545 %{m5-64media*:64}\
546 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
547 %(subtarget_link_emul_suffix) \
548 %{mrelax:-relax} %(subtarget_link_spec)"
549
550 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
551 do { \
552 if (LEVEL) \
553 flag_omit_frame_pointer = -1; \
554 if (SIZE) \
555 target_flags |= SPACE_BIT; \
556 if (TARGET_SHMEDIA && LEVEL > 1) \
557 { \
558 flag_branch_target_load_optimize = 1; \
559 if (! (SIZE)) \
560 target_flags |= SAVE_ALL_TR_BIT; \
561 } \
562 } while (0)
563
564 #define ASSEMBLER_DIALECT assembler_dialect
565
566 extern int assembler_dialect;
567
568 #define OVERRIDE_OPTIONS \
569 do { \
570 int regno; \
571 \
572 sh_cpu = CPU_SH1; \
573 assembler_dialect = 0; \
574 if (TARGET_SH2) \
575 sh_cpu = CPU_SH2; \
576 if (TARGET_SH2E) \
577 sh_cpu = CPU_SH2E; \
578 if (TARGET_SH3) \
579 sh_cpu = CPU_SH3; \
580 if (TARGET_SH3E) \
581 sh_cpu = CPU_SH3E; \
582 if (TARGET_SH4) \
583 { \
584 assembler_dialect = 1; \
585 sh_cpu = CPU_SH4; \
586 } \
587 if (TARGET_SH5) \
588 { \
589 sh_cpu = CPU_SH5; \
590 target_flags |= DALIGN_BIT; \
591 if (TARGET_FPU_ANY \
592 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
593 target_flags |= FMOVD_BIT; \
594 if (TARGET_SHMEDIA) \
595 { \
596 /* There are no delay slots on SHmedia. */ \
597 flag_delayed_branch = 0; \
598 /* Relaxation isn't yet supported for SHmedia */ \
599 target_flags &= ~RELAX_BIT; \
600 } \
601 /* -fprofile-arcs needs a working libgcov . In unified tree \
602 configurations with newlib, this requires to configure with \
603 --with-newlib --with-headers. But there is no way to check \
604 here we have a working libgcov, so just assume that we have. */\
605 if (profile_flag) \
606 { \
607 warning ("Profiling is not supported on this target."); \
608 profile_flag = profile_arc_flag = 0; \
609 } \
610 } \
611 else \
612 { \
613 /* Only the sh64-elf assembler fully supports .quad properly. */\
614 targetm.asm_out.aligned_op.di = NULL; \
615 targetm.asm_out.unaligned_op.di = NULL; \
616 } \
617 if (TARGET_FMOVD) \
618 reg_class_from_letter['e' - 'a'] = NO_REGS; \
619 \
620 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
621 if (! VALID_REGISTER_P (regno)) \
622 sh_register_names[regno][0] = '\0'; \
623 \
624 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
625 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
626 sh_additional_register_names[regno][0] = '\0'; \
627 \
628 if (flag_omit_frame_pointer < 0) \
629 { \
630 /* The debugging information is sufficient, \
631 but gdb doesn't implement this yet */ \
632 if (0) \
633 flag_omit_frame_pointer \
634 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
635 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
636 else \
637 flag_omit_frame_pointer = 0; \
638 } \
639 \
640 if (flag_pic && ! TARGET_PREFERGOT) \
641 flag_no_function_cse = 1; \
642 \
643 if (SMALL_REGISTER_CLASSES) \
644 { \
645 /* Never run scheduling before reload, since that can \
646 break global alloc, and generates slower code anyway due \
647 to the pressure on R0. */ \
648 /* Enable sched1 for SH4; ready queue will be reordered by \
649 the target hooks when pressure is high. We can not do this for \
650 SH3 and lower as they give spill failures for R0. */ \
651 if (!TARGET_HARD_SH4) \
652 flag_schedule_insns = 0; \
653 } \
654 \
655 if (align_loops == 0) \
656 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
657 if (align_jumps == 0) \
658 align_jumps = 1 << CACHE_LOG; \
659 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
660 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
661 \
662 /* Allocation boundary (in *bytes*) for the code of a function. \
663 SH1: 32 bit alignment is faster, because instructions are always \
664 fetched as a pair from a longword boundary. \
665 SH2 .. SH5 : align to cache line start. */ \
666 if (align_functions == 0) \
667 align_functions \
668 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
669 /* The linker relaxation code breaks when a function contains \
670 alignments that are larger than that at the start of a \
671 compilation unit. */ \
672 if (TARGET_RELAX) \
673 { \
674 int min_align \
675 = align_loops > align_jumps ? align_loops : align_jumps; \
676 \
677 /* Also take possible .long constants / mova tables int account. */\
678 if (min_align < 4) \
679 min_align = 4; \
680 if (align_functions < min_align) \
681 align_functions = min_align; \
682 } \
683 } while (0)
684 \f
685 /* Target machine storage layout. */
686
687 /* Define this if most significant bit is lowest numbered
688 in instructions that operate on numbered bit-fields. */
689
690 #define BITS_BIG_ENDIAN 0
691
692 /* Define this if most significant byte of a word is the lowest numbered. */
693 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
694
695 /* Define this if most significant word of a multiword number is the lowest
696 numbered. */
697 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
698
699 /* Define this to set the endianness to use in libgcc2.c, which can
700 not depend on target_flags. */
701 #if defined(__LITTLE_ENDIAN__)
702 #define LIBGCC2_WORDS_BIG_ENDIAN 0
703 #else
704 #define LIBGCC2_WORDS_BIG_ENDIAN 1
705 #endif
706
707 #define MAX_BITS_PER_WORD 64
708
709 /* Width in bits of an `int'. We want just 32-bits, even if words are
710 longer. */
711 #define INT_TYPE_SIZE 32
712
713 /* Width in bits of a `long'. */
714 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
715
716 /* Width in bits of a `long long'. */
717 #define LONG_LONG_TYPE_SIZE 64
718
719 /* Width in bits of a `long double'. */
720 #define LONG_DOUBLE_TYPE_SIZE 64
721
722 /* Width of a word, in units (bytes). */
723 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
724 #define MIN_UNITS_PER_WORD 4
725
726 /* Scaling factor for Dwarf data offsets for CFI information.
727 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
728 SHmedia; however, since we do partial register saves for the registers
729 visible to SHcompact, and for target registers for SHMEDIA32, we have
730 to allow saves that are only 4-byte aligned. */
731 #define DWARF_CIE_DATA_ALIGNMENT -4
732
733 /* Width in bits of a pointer.
734 See also the macro `Pmode' defined below. */
735 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
736
737 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
738 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
739
740 /* Boundary (in *bits*) on which stack pointer should be aligned. */
741 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
742
743 /* The log (base 2) of the cache line size, in bytes. Processors prior to
744 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
745 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
746 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
747
748 /* ABI given & required minimum allocation boundary (in *bits*) for the
749 code of a function. */
750 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
751
752 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
753 the vbit must go into the delta field of
754 pointers-to-member-functions. */
755 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
756 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
757
758 /* Alignment of field after `int : 0' in a structure. */
759 #define EMPTY_FIELD_BOUNDARY 32
760
761 /* No data type wants to be aligned rounder than this. */
762 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
763
764 /* The best alignment to use in cases where we have a choice. */
765 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
766
767 /* Make strings word-aligned so strcpy from constants will be faster. */
768 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
769 ((TREE_CODE (EXP) == STRING_CST \
770 && (ALIGN) < FASTEST_ALIGNMENT) \
771 ? FASTEST_ALIGNMENT : (ALIGN))
772
773 /* get_mode_alignment assumes complex values are always held in multiple
774 registers, but that is not the case on the SH; CQImode and CHImode are
775 held in a single integer register. SH5 also holds CSImode and SCmode
776 values in integer registers. This is relevant for argument passing on
777 SHcompact as we use a stack temp in order to pass CSImode by reference. */
778 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
779 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
780 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
781 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
782 : (unsigned) ALIGN)
783
784 /* Make arrays of chars word-aligned for the same reasons. */
785 #define DATA_ALIGNMENT(TYPE, ALIGN) \
786 (TREE_CODE (TYPE) == ARRAY_TYPE \
787 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
788 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
789
790 /* Number of bits which any structure or union's size must be a
791 multiple of. Each structure or union's size is rounded up to a
792 multiple of this. */
793 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
794
795 /* Set this nonzero if move instructions will actually fail to work
796 when given unaligned data. */
797 #define STRICT_ALIGNMENT 1
798
799 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
800 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
801 barrier_align (LABEL_AFTER_BARRIER)
802
803 #define LOOP_ALIGN(A_LABEL) \
804 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
805 ? 0 : sh_loop_align (A_LABEL))
806
807 #define LABEL_ALIGN(A_LABEL) \
808 ( \
809 (PREV_INSN (A_LABEL) \
810 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
811 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
812 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
813 /* explicit alignment insn in constant tables. */ \
814 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
815 : 0)
816
817 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
818 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
819
820 /* The base two logarithm of the known minimum alignment of an insn length. */
821 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
822 (GET_CODE (A_INSN) == INSN \
823 ? 1 << TARGET_SHMEDIA \
824 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
825 ? 1 << TARGET_SHMEDIA \
826 : CACHE_LOG)
827 \f
828 /* Standard register usage. */
829
830 /* Register allocation for the Renesas calling convention:
831
832 r0 arg return
833 r1..r3 scratch
834 r4..r7 args in
835 r8..r13 call saved
836 r14 frame pointer/call saved
837 r15 stack pointer
838 ap arg pointer (doesn't really exist, always eliminated)
839 pr subroutine return address
840 t t bit
841 mach multiply/accumulate result, high part
842 macl multiply/accumulate result, low part.
843 fpul fp/int communication register
844 rap return address pointer register
845 fr0 fp arg return
846 fr1..fr3 scratch floating point registers
847 fr4..fr11 fp args in
848 fr12..fr15 call saved floating point registers */
849
850 #define MAX_REGISTER_NAME_LENGTH 5
851 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
852
853 #define SH_REGISTER_NAMES_INITIALIZER \
854 { \
855 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
856 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
857 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
858 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
859 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
860 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
861 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
862 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
863 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
864 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
865 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
866 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
867 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
868 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
869 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
870 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
871 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
872 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
873 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
874 "rap" \
875 }
876
877 #define REGNAMES_ARR_INDEX_1(index) \
878 (sh_register_names[index])
879 #define REGNAMES_ARR_INDEX_2(index) \
880 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
881 #define REGNAMES_ARR_INDEX_4(index) \
882 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
883 #define REGNAMES_ARR_INDEX_8(index) \
884 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
885 #define REGNAMES_ARR_INDEX_16(index) \
886 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
887 #define REGNAMES_ARR_INDEX_32(index) \
888 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
889 #define REGNAMES_ARR_INDEX_64(index) \
890 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
891
892 #define REGISTER_NAMES \
893 { \
894 REGNAMES_ARR_INDEX_64 (0), \
895 REGNAMES_ARR_INDEX_64 (64), \
896 REGNAMES_ARR_INDEX_8 (128), \
897 REGNAMES_ARR_INDEX_8 (136), \
898 REGNAMES_ARR_INDEX_8 (144), \
899 REGNAMES_ARR_INDEX_1 (152) \
900 }
901
902 #define ADDREGNAMES_SIZE 32
903 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
904 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
905 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
906
907 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
908 { \
909 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
910 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
911 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
912 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
913 }
914
915 #define ADDREGNAMES_REGNO(index) \
916 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
917 : (-1))
918
919 #define ADDREGNAMES_ARR_INDEX_1(index) \
920 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
921 #define ADDREGNAMES_ARR_INDEX_2(index) \
922 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
923 #define ADDREGNAMES_ARR_INDEX_4(index) \
924 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
925 #define ADDREGNAMES_ARR_INDEX_8(index) \
926 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
927 #define ADDREGNAMES_ARR_INDEX_16(index) \
928 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
929 #define ADDREGNAMES_ARR_INDEX_32(index) \
930 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
931
932 #define ADDITIONAL_REGISTER_NAMES \
933 { \
934 ADDREGNAMES_ARR_INDEX_32 (0) \
935 }
936
937 /* Number of actual hardware registers.
938 The hardware registers are assigned numbers for the compiler
939 from 0 to just below FIRST_PSEUDO_REGISTER.
940 All registers that the compiler knows about must be given numbers,
941 even those that are not normally considered general registers. */
942
943 /* There are many other relevant definitions in sh.md's md_constants. */
944
945 #define FIRST_GENERAL_REG R0_REG
946 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
947 #define FIRST_FP_REG DR0_REG
948 #define LAST_FP_REG (FIRST_FP_REG + \
949 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
950 #define FIRST_XD_REG XD0_REG
951 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
952 #define FIRST_TARGET_REG TR0_REG
953 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
954
955 #define GENERAL_REGISTER_P(REGNO) \
956 IN_RANGE ((REGNO), \
957 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
958 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
959
960 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
961 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
962
963 #define FP_REGISTER_P(REGNO) \
964 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
965
966 #define XD_REGISTER_P(REGNO) \
967 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
968
969 #define FP_OR_XD_REGISTER_P(REGNO) \
970 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
971
972 #define FP_ANY_REGISTER_P(REGNO) \
973 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
974
975 #define SPECIAL_REGISTER_P(REGNO) \
976 ((REGNO) == GBR_REG || (REGNO) == T_REG \
977 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
978
979 #define TARGET_REGISTER_P(REGNO) \
980 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
981
982 #define SHMEDIA_REGISTER_P(REGNO) \
983 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
984 || TARGET_REGISTER_P (REGNO))
985
986 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
987 that should be fixed. */
988 #define VALID_REGISTER_P(REGNO) \
989 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
990 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
991 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
992 || (TARGET_SH2E && (REGNO) == FPUL_REG))
993
994 /* The mode that should be generally used to store a register by
995 itself in the stack, or to load it back. */
996 #define REGISTER_NATURAL_MODE(REGNO) \
997 (FP_REGISTER_P (REGNO) ? SFmode \
998 : XD_REGISTER_P (REGNO) ? DFmode \
999 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1000 ? DImode \
1001 : SImode)
1002
1003 #define FIRST_PSEUDO_REGISTER 153
1004
1005 /* 1 for registers that have pervasive standard uses
1006 and are not available for the register allocator.
1007
1008 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1009 It is 32 bits wide for SH2. */
1010
1011 #define FIXED_REGISTERS \
1012 { \
1013 /* Regular registers. */ \
1014 0, 0, 0, 0, 0, 0, 0, 0, \
1015 0, 0, 0, 0, 0, 0, 0, 1, \
1016 /* r16 is reserved, r18 is the former pr. */ \
1017 1, 0, 0, 0, 0, 0, 0, 0, \
1018 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1019 /* r26 is a global variable data pointer; r27 is for constants. */ \
1020 1, 1, 1, 1, 0, 0, 0, 0, \
1021 0, 0, 0, 0, 0, 0, 0, 0, \
1022 0, 0, 0, 0, 0, 0, 0, 0, \
1023 0, 0, 0, 0, 0, 0, 0, 0, \
1024 0, 0, 0, 0, 0, 0, 0, 1, \
1025 /* FP registers. */ \
1026 0, 0, 0, 0, 0, 0, 0, 0, \
1027 0, 0, 0, 0, 0, 0, 0, 0, \
1028 0, 0, 0, 0, 0, 0, 0, 0, \
1029 0, 0, 0, 0, 0, 0, 0, 0, \
1030 0, 0, 0, 0, 0, 0, 0, 0, \
1031 0, 0, 0, 0, 0, 0, 0, 0, \
1032 0, 0, 0, 0, 0, 0, 0, 0, \
1033 0, 0, 0, 0, 0, 0, 0, 0, \
1034 /* Branch target registers. */ \
1035 0, 0, 0, 0, 0, 0, 0, 0, \
1036 /* XD registers. */ \
1037 0, 0, 0, 0, 0, 0, 0, 0, \
1038 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1039 1, 1, 1, 1, 1, 1, 0, 1, \
1040 /*"rap" */ \
1041 1, \
1042 }
1043
1044 /* 1 for registers not available across function calls.
1045 These must include the FIXED_REGISTERS and also any
1046 registers that can be used without being saved.
1047 The latter must include the registers where values are returned
1048 and the register where structure-value addresses are passed.
1049 Aside from that, you can include as many other registers as you like. */
1050
1051 #define CALL_USED_REGISTERS \
1052 { \
1053 /* Regular registers. */ \
1054 1, 1, 1, 1, 1, 1, 1, 1, \
1055 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1056 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1057 across SH5 function calls. */ \
1058 0, 0, 0, 0, 0, 0, 0, 1, \
1059 1, 1, 1, 1, 1, 1, 1, 1, \
1060 1, 1, 1, 1, 0, 0, 0, 0, \
1061 0, 0, 0, 0, 1, 1, 1, 1, \
1062 1, 1, 1, 1, 0, 0, 0, 0, \
1063 0, 0, 0, 0, 0, 0, 0, 0, \
1064 0, 0, 0, 0, 1, 1, 1, 1, \
1065 /* FP registers. */ \
1066 1, 1, 1, 1, 1, 1, 1, 1, \
1067 1, 1, 1, 1, 0, 0, 0, 0, \
1068 1, 1, 1, 1, 1, 1, 1, 1, \
1069 1, 1, 1, 1, 1, 1, 1, 1, \
1070 1, 1, 1, 1, 0, 0, 0, 0, \
1071 0, 0, 0, 0, 0, 0, 0, 0, \
1072 0, 0, 0, 0, 0, 0, 0, 0, \
1073 0, 0, 0, 0, 0, 0, 0, 0, \
1074 /* Branch target registers. */ \
1075 1, 1, 1, 1, 1, 0, 0, 0, \
1076 /* XD registers. */ \
1077 1, 1, 1, 1, 1, 1, 0, 0, \
1078 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1079 1, 1, 1, 1, 1, 1, 1, 1, \
1080 /*"rap" */ \
1081 1, \
1082 }
1083
1084 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1085 across SHcompact function calls. We can't tell whether a called
1086 function is SHmedia or SHcompact, so we assume it may be when
1087 compiling SHmedia code with the 32-bit ABI, since that's the only
1088 ABI that can be linked with SHcompact code. */
1089 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1090 (TARGET_SHMEDIA32 \
1091 && GET_MODE_SIZE (MODE) > 4 \
1092 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1093 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1094 || TARGET_REGISTER_P (REGNO) \
1095 || (REGNO) == PR_MEDIA_REG))
1096
1097 /* Return number of consecutive hard regs needed starting at reg REGNO
1098 to hold something of mode MODE.
1099 This is ordinarily the length in words of a value of mode MODE
1100 but can be less for certain modes in special long registers.
1101
1102 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1103
1104 #define HARD_REGNO_NREGS(REGNO, MODE) \
1105 (XD_REGISTER_P (REGNO) \
1106 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1107 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1108 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1109 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1110
1111 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1112 We can allow any mode in any general register. The special registers
1113 only allow SImode. Don't allow any mode in the PR. */
1114
1115 /* We cannot hold DCmode values in the XD registers because alter_reg
1116 handles subregs of them incorrectly. We could work around this by
1117 spacing the XD registers like the DR registers, but this would require
1118 additional memory in every compilation to hold larger register vectors.
1119 We could hold SFmode / SCmode values in XD registers, but that
1120 would require a tertiary reload when reloading from / to memory,
1121 and a secondary reload to reload from / to general regs; that
1122 seems to be a loosing proposition. */
1123 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1124 it won't be ferried through GP registers first. */
1125 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1126 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1127 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1128 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1129 ? 1 \
1130 : (MODE) == V2SFmode \
1131 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1132 || GENERAL_REGISTER_P (REGNO)) \
1133 : (MODE) == V4SFmode \
1134 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1135 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1136 : (MODE) == V16SFmode \
1137 ? (TARGET_SHMEDIA \
1138 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1139 : (REGNO) == FIRST_XD_REG) \
1140 : FP_REGISTER_P (REGNO) \
1141 ? ((MODE) == SFmode || (MODE) == SImode \
1142 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1143 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
1144 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1145 || (MODE) == V2SFmode || (MODE) == TImode))) \
1146 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1147 : XD_REGISTER_P (REGNO) \
1148 ? (MODE) == DFmode \
1149 : TARGET_REGISTER_P (REGNO) \
1150 ? ((MODE) == DImode || (MODE) == SImode) \
1151 : (REGNO) == PR_REG ? (MODE) == SImode \
1152 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1153 : 1)
1154
1155 /* Value is 1 if MODE is a supported vector mode. */
1156 #define VECTOR_MODE_SUPPORTED_P(MODE) \
1157 ((TARGET_FPU_ANY \
1158 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
1159 || (TARGET_SHMEDIA \
1160 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
1161 || (MODE) == V2SImode)))
1162
1163 /* Value is 1 if it is a good idea to tie two pseudo registers
1164 when one has mode MODE1 and one has mode MODE2.
1165 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1166 for any hard reg, then this must be 0 for correct output.
1167 That's the case for xd registers: we don't hold SFmode values in
1168 them, so we can't tie an SFmode pseudos with one in another
1169 floating-point mode. */
1170
1171 #define MODES_TIEABLE_P(MODE1, MODE2) \
1172 ((MODE1) == (MODE2) \
1173 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1174 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1175 && (GET_MODE_SIZE (MODE2) <= 4)) \
1176 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1177
1178 /* A C expression that is nonzero if hard register NEW_REG can be
1179 considered for use as a rename register for OLD_REG register */
1180
1181 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1182 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1183
1184 /* Specify the registers used for certain standard purposes.
1185 The values of these macros are register numbers. */
1186
1187 /* Define this if the program counter is overloaded on a register. */
1188 /* #define PC_REGNUM 15*/
1189
1190 /* Register to use for pushing function arguments. */
1191 #define STACK_POINTER_REGNUM SP_REG
1192
1193 /* Base register for access to local variables of the function. */
1194 #define FRAME_POINTER_REGNUM FP_REG
1195
1196 /* Fake register that holds the address on the stack of the
1197 current function's return address. */
1198 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1199
1200 /* Register to hold the addressing base for position independent
1201 code access to data items. */
1202 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1203
1204 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1205
1206 /* Value should be nonzero if functions must have frame pointers.
1207 Zero means the frame pointer need not be set up (and parms may be accessed
1208 via the stack pointer) in functions that seem suitable. */
1209
1210 #define FRAME_POINTER_REQUIRED 0
1211
1212 /* Definitions for register eliminations.
1213
1214 We have three registers that can be eliminated on the SH. First, the
1215 frame pointer register can often be eliminated in favor of the stack
1216 pointer register. Secondly, the argument pointer register can always be
1217 eliminated; it is replaced with either the stack or frame pointer.
1218 Third, there is the return address pointer, which can also be replaced
1219 with either the stack or the frame pointer. */
1220
1221 /* This is an array of structures. Each structure initializes one pair
1222 of eliminable registers. The "from" register number is given first,
1223 followed by "to". Eliminations of the same "from" register are listed
1224 in order of preference. */
1225
1226 /* If you add any registers here that are not actually hard registers,
1227 and that have any alternative of elimination that doesn't always
1228 apply, you need to amend calc_live_regs to exclude it, because
1229 reload spills all eliminable registers where it sees an
1230 can_eliminate == 0 entry, thus making them 'live' .
1231 If you add any hard registers that can be eliminated in different
1232 ways, you have to patch reload to spill them only when all alternatives
1233 of elimination fail. */
1234
1235 #define ELIMINABLE_REGS \
1236 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1237 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1238 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1239 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1240 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1241
1242 /* Given FROM and TO register numbers, say whether this elimination
1243 is allowed. */
1244 #define CAN_ELIMINATE(FROM, TO) \
1245 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1246
1247 /* Define the offset between two registers, one to be eliminated, and the other
1248 its replacement, at the start of a routine. */
1249
1250 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1251 OFFSET = initial_elimination_offset ((FROM), (TO))
1252
1253 /* Base register for access to arguments of the function. */
1254 #define ARG_POINTER_REGNUM AP_REG
1255
1256 /* Register in which the static-chain is passed to a function. */
1257 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1258
1259 /* Don't default to pcc-struct-return, because we have already specified
1260 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1261 target hook. */
1262
1263 #define DEFAULT_PCC_STRUCT_RETURN 0
1264
1265 #define SHMEDIA_REGS_STACK_ADJUST() \
1266 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1267 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1268 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1269 : 0)
1270
1271 \f
1272 /* Define the classes of registers for register constraints in the
1273 machine description. Also define ranges of constants.
1274
1275 One of the classes must always be named ALL_REGS and include all hard regs.
1276 If there is more than one class, another class must be named NO_REGS
1277 and contain no registers.
1278
1279 The name GENERAL_REGS must be the name of a class (or an alias for
1280 another name such as ALL_REGS). This is the class of registers
1281 that is allowed by "g" or "r" in a register constraint.
1282 Also, registers outside this class are allocated only when
1283 instructions express preferences for them.
1284
1285 The classes must be numbered in nondecreasing order; that is,
1286 a larger-numbered class must never be contained completely
1287 in a smaller-numbered class.
1288
1289 For any two classes, it is very desirable that there be another
1290 class that represents their union. */
1291
1292 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1293 be used as the destination of some of the arithmetic ops. There are
1294 also some special purpose registers; the T bit register, the
1295 Procedure Return Register and the Multiply Accumulate Registers. */
1296 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1297 reg_class_subunion. We don't want to have an actual union class
1298 of these, because it would only be used when both classes are calculated
1299 to give the same cost, but there is only one FPUL register.
1300 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1301 applying to the actual instruction alternative considered. E.g., the
1302 y/r alternative of movsi_ie is considered to have no more cost that
1303 the r/r alternative, which is patently untrue. */
1304
1305 enum reg_class
1306 {
1307 NO_REGS,
1308 R0_REGS,
1309 PR_REGS,
1310 T_REGS,
1311 MAC_REGS,
1312 FPUL_REGS,
1313 SIBCALL_REGS,
1314 GENERAL_REGS,
1315 FP0_REGS,
1316 FP_REGS,
1317 DF_HI_REGS,
1318 DF_REGS,
1319 FPSCR_REGS,
1320 GENERAL_FP_REGS,
1321 TARGET_REGS,
1322 ALL_REGS,
1323 LIM_REG_CLASSES
1324 };
1325
1326 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1327
1328 /* Give names of register classes as strings for dump file. */
1329 #define REG_CLASS_NAMES \
1330 { \
1331 "NO_REGS", \
1332 "R0_REGS", \
1333 "PR_REGS", \
1334 "T_REGS", \
1335 "MAC_REGS", \
1336 "FPUL_REGS", \
1337 "SIBCALL_REGS", \
1338 "GENERAL_REGS", \
1339 "FP0_REGS", \
1340 "FP_REGS", \
1341 "DF_HI_REGS", \
1342 "DF_REGS", \
1343 "FPSCR_REGS", \
1344 "GENERAL_FP_REGS", \
1345 "TARGET_REGS", \
1346 "ALL_REGS", \
1347 }
1348
1349 /* Define which registers fit in which classes.
1350 This is an initializer for a vector of HARD_REG_SET
1351 of length N_REG_CLASSES. */
1352
1353 #define REG_CLASS_CONTENTS \
1354 { \
1355 /* NO_REGS: */ \
1356 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1357 /* R0_REGS: */ \
1358 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1359 /* PR_REGS: */ \
1360 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1361 /* T_REGS: */ \
1362 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1363 /* MAC_REGS: */ \
1364 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1365 /* FPUL_REGS: */ \
1366 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1367 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1368 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1369 /* GENERAL_REGS: */ \
1370 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1371 /* FP0_REGS: */ \
1372 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1373 /* FP_REGS: */ \
1374 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1375 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1376 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1377 /* DF_REGS: */ \
1378 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1379 /* FPSCR_REGS: */ \
1380 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1381 /* GENERAL_FP_REGS: */ \
1382 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1383 /* TARGET_REGS: */ \
1384 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1385 /* ALL_REGS: */ \
1386 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1387 }
1388
1389 /* The same information, inverted:
1390 Return the class number of the smallest class containing
1391 reg number REGNO. This could be a conditional expression
1392 or could index an array. */
1393
1394 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1395 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1396
1397 /* When defined, the compiler allows registers explicitly used in the
1398 rtl to be used as spill registers but prevents the compiler from
1399 extending the lifetime of these registers. */
1400
1401 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1402
1403 /* The order in which register should be allocated. */
1404 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1405 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1406 spilled or used otherwise, we better have the FP_REGS allocated first. */
1407 #define REG_ALLOC_ORDER \
1408 {/* Caller-saved FPRs */ \
1409 65, 66, 67, 68, 69, 70, 71, 64, \
1410 72, 73, 74, 75, 80, 81, 82, 83, \
1411 84, 85, 86, 87, 88, 89, 90, 91, \
1412 92, 93, 94, 95, 96, 97, 98, 99, \
1413 /* Callee-saved FPRs */ \
1414 76, 77, 78, 79,100,101,102,103, \
1415 104,105,106,107,108,109,110,111, \
1416 112,113,114,115,116,117,118,119, \
1417 120,121,122,123,124,125,126,127, \
1418 136,137,138,139,140,141,142,143, \
1419 /* FPSCR */ 151, \
1420 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1421 1, 2, 3, 7, 6, 5, 4, 0, \
1422 8, 9, 17, 19, 20, 21, 22, 23, \
1423 36, 37, 38, 39, 40, 41, 42, 43, \
1424 60, 61, 62, \
1425 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1426 10, 11, 12, 13, 14, 18, \
1427 /* SH5 callee-saved GPRs */ \
1428 28, 29, 30, 31, 32, 33, 34, 35, \
1429 44, 45, 46, 47, 48, 49, 50, 51, \
1430 52, 53, 54, 55, 56, 57, 58, 59, \
1431 /* FPUL */ 150, \
1432 /* SH5 branch target registers */ \
1433 128,129,130,131,132,133,134,135, \
1434 /* Fixed registers */ \
1435 15, 16, 24, 25, 26, 27, 63,144, \
1436 145,146,147,148,149,152 }
1437
1438 /* The class value for index registers, and the one for base regs. */
1439 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1440 #define BASE_REG_CLASS GENERAL_REGS
1441
1442 /* Get reg_class from a letter such as appears in the machine
1443 description. */
1444 extern enum reg_class reg_class_from_letter[];
1445
1446 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1447 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1448 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1449 \f
1450 /* Overview of uppercase letter constraints:
1451 A: Addresses (constraint len == 3)
1452 Ac4: sh4 cache operations
1453 Ac5: sh5 cache operations
1454 Bxx: miscellaneous constraints
1455 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1456 fldi0 / fldi0 cases
1457 C: Constants other than only CONST_INT (constraint len == 3)
1458 C16: 16 bit constant, literal or symbolic
1459 Csy: label or symbol
1460 Cpg: non-explicit constants that can be directly loaded into a general
1461 purpose register in PIC code. like 's' except we don't allow
1462 PIC_DIRECT_ADDR_P
1463 IJKLMNOP: CONT_INT constants
1464 Ixx: signed xx bit
1465 J16: 0xffffffff00000000 | 0x00000000ffffffff
1466 Kxx: unsigned xx bit
1467 M: 1
1468 N: 0
1469 P27: 1 | 2 | 8 | 16
1470 Q: pc relative load operand
1471 Rxx: reserved for exotic register classes.
1472 S: extra memory (storage) constraints (constraint len == 3)
1473 Sua: unaligned memory operations
1474 W: vector
1475 Z: zero in any mode
1476
1477 unused CONST_INT constraint letters: LO
1478 unused EXTRA_CONSTRAINT letters: D T U Y */
1479
1480 #if 1 /* check that the transition went well. */
1481 #define CONSTRAINT_LEN(C,STR) \
1482 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1483 || (C) == 'Y' \
1484 || ((C) == 'I' \
1485 && (((STR)[1] != '0' && (STR)[1] != '1') \
1486 || (STR)[2] < '0' || (STR)[2] > '9')) \
1487 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1488 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1489 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1490 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1491 ? -1 \
1492 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1493 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1494 || (C) == 'R' || (C) == 'S') \
1495 ? 3 \
1496 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1497 #else
1498 #define CONSTRAINT_LEN(C,STR) \
1499 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1500 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1501 || (C) == 'R' || (C) == 'S') \
1502 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1503 #endif
1504
1505 /* The letters I, J, K, L and M in a register constraint string
1506 can be used to stand for particular ranges of immediate operands.
1507 This macro defines what the ranges are.
1508 C is the letter, and VALUE is a constant value.
1509 Return 1 if VALUE is in the range specified by C.
1510 I08: arithmetic operand -127..128, as used in add, sub, etc
1511 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1512 P27: shift operand 1,2,8 or 16
1513 K08: logical operand 0..255, as used in and, or, etc.
1514 M: constant 1
1515 N: constant 0
1516 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1517 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1518 */
1519
1520 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1521 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1522 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1523 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1524 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1525 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1526 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1527 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1528 #define CONST_OK_FOR_I(VALUE, STR) \
1529 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1530 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1531 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1532 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1533 : 0)
1534
1535 #define CONST_OK_FOR_J16(VALUE) \
1536 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1537 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1538 #define CONST_OK_FOR_J(VALUE, STR) \
1539 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1540 : 0)
1541
1542 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1543 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1544 #define CONST_OK_FOR_K(VALUE, STR) \
1545 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1546 : 0)
1547 #define CONST_OK_FOR_P27(VALUE) \
1548 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1549 #define CONST_OK_FOR_P(VALUE, STR) \
1550 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1551 : 0)
1552 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1553 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1554 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1555 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1556 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1557 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1558 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1559 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1560 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1561 : 0)
1562
1563 /* Similar, but for floating constants, and defining letters G and H.
1564 Here VALUE is the CONST_DOUBLE rtx itself. */
1565
1566 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1567 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1568 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1569 : (C) == 'F')
1570
1571 /* Given an rtx X being reloaded into a reg required to be
1572 in class CLASS, return the class of reg to actually use.
1573 In general this is just CLASS; but on some machines
1574 in some cases it is preferable to use a more restrictive class. */
1575
1576 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1577 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1578 && (GET_CODE (X) == CONST_DOUBLE \
1579 || GET_CODE (X) == SYMBOL_REF) \
1580 ? GENERAL_REGS \
1581 : (CLASS)) \
1582
1583 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1584 ((((REGCLASS_HAS_FP_REG (CLASS) \
1585 && (GET_CODE (X) == REG \
1586 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1587 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1588 && TARGET_FMOVD)))) \
1589 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1590 && GET_CODE (X) == REG \
1591 && FP_REGISTER_P (REGNO (X)))) \
1592 && ! TARGET_SHMEDIA \
1593 && ((MODE) == SFmode || (MODE) == SImode)) \
1594 ? FPUL_REGS \
1595 : (((CLASS) == FPUL_REGS \
1596 || (REGCLASS_HAS_FP_REG (CLASS) \
1597 && ! TARGET_SHMEDIA && MODE == SImode)) \
1598 && (GET_CODE (X) == MEM \
1599 || (GET_CODE (X) == REG \
1600 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1601 || REGNO (X) == T_REG \
1602 || system_reg_operand (X, VOIDmode))))) \
1603 ? GENERAL_REGS \
1604 : ((CLASS) == TARGET_REGS \
1605 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1606 ? ((target_operand ((X), (MODE)) \
1607 && ! target_reg_operand ((X), (MODE))) \
1608 ? NO_REGS : GENERAL_REGS) \
1609 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1610 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1611 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1612 ? GENERAL_REGS \
1613 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1614 && TARGET_REGISTER_P (REGNO (X))) \
1615 ? GENERAL_REGS : NO_REGS)
1616
1617 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1618 ((REGCLASS_HAS_FP_REG (CLASS) \
1619 && ! TARGET_SHMEDIA \
1620 && immediate_operand ((X), (MODE)) \
1621 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1622 && (MODE) == SFmode && fldi_ok ())) \
1623 ? R0_REGS \
1624 : (CLASS == FPUL_REGS \
1625 && ((GET_CODE (X) == REG \
1626 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1627 || REGNO (X) == T_REG)) \
1628 || GET_CODE (X) == PLUS)) \
1629 ? GENERAL_REGS \
1630 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1631 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1632 ? GENERAL_REGS \
1633 : R0_REGS) \
1634 : (CLASS == FPSCR_REGS \
1635 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1636 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1637 ? GENERAL_REGS \
1638 : (REGCLASS_HAS_FP_REG (CLASS) \
1639 && TARGET_SHMEDIA \
1640 && immediate_operand ((X), (MODE)) \
1641 && (X) != CONST0_RTX (GET_MODE (X)) \
1642 && GET_MODE (X) != V4SFmode) \
1643 ? GENERAL_REGS \
1644 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1645
1646 /* Return the maximum number of consecutive registers
1647 needed to represent mode MODE in a register of class CLASS.
1648
1649 If TARGET_SHMEDIA, we need two FP registers per word.
1650 Otherwise we will need at most one register per word. */
1651 #define CLASS_MAX_NREGS(CLASS, MODE) \
1652 (TARGET_SHMEDIA \
1653 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1654 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1655 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1656
1657 /* If defined, gives a class of registers that cannot be used as the
1658 operand of a SUBREG that changes the mode of the object illegally. */
1659 /* ??? We need to renumber the internal numbers for the frnn registers
1660 when in little endian in order to allow mode size changes. */
1661
1662 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1663 sh_cannot_change_mode_class (FROM, TO, CLASS)
1664 \f
1665 /* Stack layout; function entry, exit and calling. */
1666
1667 /* Define the number of registers that can hold parameters.
1668 These macros are used only in other macro definitions below. */
1669
1670 #define NPARM_REGS(MODE) \
1671 (TARGET_FPU_ANY && (MODE) == SFmode \
1672 ? (TARGET_SH5 ? 12 : 8) \
1673 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1674 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1675 ? (TARGET_SH5 ? 12 : 8) \
1676 : (TARGET_SH5 ? 8 : 4))
1677
1678 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1679 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1680
1681 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1682 #define FIRST_FP_RET_REG FIRST_FP_REG
1683
1684 /* Define this if pushing a word on the stack
1685 makes the stack pointer a smaller address. */
1686 #define STACK_GROWS_DOWNWARD
1687
1688 /* Define this macro if the addresses of local variable slots are at
1689 negative offsets from the frame pointer.
1690
1691 The SH only has positive indexes, so grow the frame up. */
1692 /* #define FRAME_GROWS_DOWNWARD */
1693
1694 /* Offset from the frame pointer to the first local variable slot to
1695 be allocated. */
1696 #define STARTING_FRAME_OFFSET 0
1697
1698 /* If we generate an insn to push BYTES bytes,
1699 this says how many the stack pointer really advances by. */
1700 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1701 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1702 do correct alignment. */
1703 #if 0
1704 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1705 #endif
1706
1707 /* Offset of first parameter from the argument pointer register value. */
1708 #define FIRST_PARM_OFFSET(FNDECL) 0
1709
1710 /* Value is the number of byte of arguments automatically
1711 popped when returning from a subroutine call.
1712 FUNDECL is the declaration node of the function (as a tree),
1713 FUNTYPE is the data type of the function (as a tree),
1714 or for a library call it is an identifier node for the subroutine name.
1715 SIZE is the number of bytes of arguments passed on the stack.
1716
1717 On the SH, the caller does not pop any of its arguments that were passed
1718 on the stack. */
1719 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1720
1721 /* Value is the number of bytes of arguments automatically popped when
1722 calling a subroutine.
1723 CUM is the accumulated argument list.
1724
1725 On SHcompact, the call trampoline pops arguments off the stack. */
1726 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1727
1728 /* Some subroutine macros specific to this machine. */
1729
1730 #define BASE_RETURN_VALUE_REG(MODE) \
1731 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1732 ? FIRST_FP_RET_REG \
1733 : TARGET_FPU_ANY && (MODE) == SCmode \
1734 ? FIRST_FP_RET_REG \
1735 : (TARGET_FPU_DOUBLE \
1736 && ((MODE) == DFmode || (MODE) == SFmode \
1737 || (MODE) == DCmode || (MODE) == SCmode )) \
1738 ? FIRST_FP_RET_REG \
1739 : FIRST_RET_REG)
1740
1741 #define BASE_ARG_REG(MODE) \
1742 ((TARGET_SH2E && ((MODE) == SFmode)) \
1743 ? FIRST_FP_PARM_REG \
1744 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1745 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1746 ? FIRST_FP_PARM_REG \
1747 : FIRST_PARM_REG)
1748
1749 /* Define how to find the value returned by a function.
1750 VALTYPE is the data type of the value (as a tree).
1751 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1752 otherwise, FUNC is 0.
1753 For the SH, this is like LIBCALL_VALUE, except that we must change the
1754 mode like PROMOTE_MODE does.
1755 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1756 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1757
1758 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1759 gen_rtx_REG ( \
1760 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1761 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1762 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1763 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1764 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1765 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1766 || TREE_CODE (VALTYPE) == REAL_TYPE \
1767 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1768 && sh_promote_prototypes (VALTYPE) \
1769 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1770 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1771
1772 /* Define how to find the value returned by a library function
1773 assuming the value has mode MODE. */
1774 #define LIBCALL_VALUE(MODE) \
1775 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1776
1777 /* 1 if N is a possible register number for a function value. */
1778 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1779 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1780 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1781
1782 /* 1 if N is a possible register number for function argument passing. */
1783 /* ??? There are some callers that pass REGNO as int, and others that pass
1784 it as unsigned. We get warnings unless we do casts everywhere. */
1785 #define FUNCTION_ARG_REGNO_P(REGNO) \
1786 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1787 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1788 || (TARGET_FPU_ANY \
1789 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1790 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1791 + NPARM_REGS (SFmode))))
1792 \f
1793 /* Define a data type for recording info about an argument list
1794 during the scan of that argument list. This data type should
1795 hold all necessary information about the function itself
1796 and about the args processed so far, enough to enable macros
1797 such as FUNCTION_ARG to determine where the next arg should go.
1798
1799 On SH, this is a single integer, which is a number of words
1800 of arguments scanned so far (including the invisible argument,
1801 if any, which holds the structure-value-address).
1802 Thus NARGREGS or more means all following args should go on the stack. */
1803
1804 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1805 struct sh_args {
1806 int arg_count[2];
1807 int force_mem;
1808 /* Nonzero if a prototype is available for the function. */
1809 int prototype_p;
1810 /* The number of an odd floating-point register, that should be used
1811 for the next argument of type float. */
1812 int free_single_fp_reg;
1813 /* Whether we're processing an outgoing function call. */
1814 int outgoing;
1815 /* The number of general-purpose registers that should have been
1816 used to pass partial arguments, that are passed totally on the
1817 stack. On SHcompact, a call trampoline will pop them off the
1818 stack before calling the actual function, and, if the called
1819 function is implemented in SHcompact mode, the incoming arguments
1820 decoder will push such arguments back onto the stack. For
1821 incoming arguments, STACK_REGS also takes into account other
1822 arguments passed by reference, that the decoder will also push
1823 onto the stack. */
1824 int stack_regs;
1825 /* The number of general-purpose registers that should have been
1826 used to pass arguments, if the arguments didn't have to be passed
1827 by reference. */
1828 int byref_regs;
1829 /* Set as by shcompact_byref if the current argument is to be passed
1830 by reference. */
1831 int byref;
1832
1833 /* call_cookie is a bitmask used by call expanders, as well as
1834 function prologue and epilogues, to allow SHcompact to comply
1835 with the SH5 32-bit ABI, that requires 64-bit registers to be
1836 used even though only the lower 32-bit half is visible in
1837 SHcompact mode. The strategy is to call SHmedia trampolines.
1838
1839 The alternatives for each of the argument-passing registers are
1840 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1841 contents from the address in it; (d) add 8 to it, storing the
1842 result in the next register, then (c); (e) copy it from some
1843 floating-point register,
1844
1845 Regarding copies from floating-point registers, r2 may only be
1846 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1847 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1848 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1849 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1850 dr10.
1851
1852 The bit mask is structured as follows:
1853
1854 - 1 bit to tell whether to set up a return trampoline.
1855
1856 - 3 bits to count the number consecutive registers to pop off the
1857 stack.
1858
1859 - 4 bits for each of r9, r8, r7 and r6.
1860
1861 - 3 bits for each of r5, r4, r3 and r2.
1862
1863 - 3 bits set to 0 (the most significant ones)
1864
1865 3 2 1 0
1866 1098 7654 3210 9876 5432 1098 7654 3210
1867 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1868 2223 3344 4555 6666 7777 8888 9999 SSS-
1869
1870 - If F is set, the register must be copied from an FP register,
1871 whose number is encoded in the remaining bits.
1872
1873 - Else, if L is set, the register must be loaded from the address
1874 contained in it. If the P bit is *not* set, the address of the
1875 following dword should be computed first, and stored in the
1876 following register.
1877
1878 - Else, if P is set, the register alone should be popped off the
1879 stack.
1880
1881 - After all this processing, the number of registers represented
1882 in SSS will be popped off the stack. This is an optimization
1883 for pushing/popping consecutive registers, typically used for
1884 varargs and large arguments partially passed in registers.
1885
1886 - If T is set, a return trampoline will be set up for 64-bit
1887 return values to be split into 2 32-bit registers. */
1888 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1889 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1890 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1891 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1892 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1893 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1894 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1895 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1896 #define CALL_COOKIE_INT_REG(REG, VAL) \
1897 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1898 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1899 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1900 long call_cookie;
1901
1902 /* This is set to nonzero when the call in question must use the Renesas ABI,
1903 even without the -mrenesas option. */
1904 int renesas_abi;
1905 };
1906
1907 #define CUMULATIVE_ARGS struct sh_args
1908
1909 #define GET_SH_ARG_CLASS(MODE) \
1910 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1911 ? SH_ARG_FLOAT \
1912 /* There's no mention of complex float types in the SH5 ABI, so we
1913 should presumably handle them as aggregate types. */ \
1914 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1915 ? SH_ARG_INT \
1916 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1917 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1918 ? SH_ARG_FLOAT : SH_ARG_INT)
1919
1920 #define ROUND_ADVANCE(SIZE) \
1921 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1922
1923 /* Round a register number up to a proper boundary for an arg of mode
1924 MODE.
1925
1926 The SH doesn't care about double alignment, so we only
1927 round doubles to even regs when asked to explicitly. */
1928
1929 #define ROUND_REG(CUM, MODE) \
1930 (((TARGET_ALIGN_DOUBLE \
1931 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1932 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1933 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1934 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1935 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1936 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1937
1938 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1939 for a call to a function whose data type is FNTYPE.
1940 For a library call, FNTYPE is 0.
1941
1942 On SH, the offset always starts at 0: the first parm reg is always
1943 the same reg for a given argument class.
1944
1945 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1946
1947 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1948 do { \
1949 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1950 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1951 (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0; \
1952 (CUM).force_mem \
1953 = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE) \
1954 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
1955 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1956 (CUM).arg_count[(int) SH_ARG_INT] \
1957 = (TARGET_SH5 && (FNTYPE) \
1958 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
1959 (CUM).free_single_fp_reg = 0; \
1960 (CUM).outgoing = 1; \
1961 (CUM).stack_regs = 0; \
1962 (CUM).byref_regs = 0; \
1963 (CUM).byref = 0; \
1964 (CUM).call_cookie \
1965 = (CALL_COOKIE_RET_TRAMP \
1966 (TARGET_SHCOMPACT && (FNTYPE) \
1967 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1968 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1969 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1970 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1971 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1972 (FNTYPE))) \
1973 == FIRST_RET_REG))); \
1974 } while (0)
1975
1976 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1977 do { \
1978 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0, 0); \
1979 (CUM).call_cookie \
1980 = (CALL_COOKIE_RET_TRAMP \
1981 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1982 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1983 } while (0)
1984
1985 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1986 do { \
1987 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0, 0); \
1988 (CUM).outgoing = 0; \
1989 } while (0)
1990
1991 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1992 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1993 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1994 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1995
1996 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1997 This macro is only used in this file. */
1998
1999 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2000 (((TYPE) == 0 \
2001 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2002 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2003 || ! (AGGREGATE_TYPE_P (TYPE) \
2004 || (!TARGET_FPU_ANY \
2005 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2006 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2007 && ! (CUM).force_mem \
2008 && (TARGET_SH2E \
2009 ? ((MODE) == BLKmode \
2010 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2011 + int_size_in_bytes (TYPE)) \
2012 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2013 : ((ROUND_REG((CUM), (MODE)) \
2014 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2015 <= NPARM_REGS (MODE))) \
2016 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2017
2018 /* By accident we got stuck with passing SCmode on SH4 little endian
2019 in two registers that are nominally successive - which is different from
2020 two single SFmode values, where we take endianness translation into
2021 account. That does not work at all if an odd number of registers is
2022 already in use, so that got fixed, but library functions are still more
2023 likely to use complex numbers without mixing them with SFmode arguments
2024 (which in C would have to be structures), so for the sake of ABI
2025 compatibility the way SCmode values are passed when an even number of
2026 FP registers is in use remains different from a pair of SFmode values for
2027 now.
2028 I.e.:
2029 foo (double); a: fr5,fr4
2030 foo (float a, float b); a: fr5 b: fr4
2031 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2032 this should be the other way round...
2033 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2034 #define FUNCTION_ARG_SCmode_WART 1
2035
2036 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2037 register in SHcompact mode, it must be padded in the most
2038 significant end. This means that passing it by reference wouldn't
2039 pad properly on a big-endian machine. In this particular case, we
2040 pass this argument on the stack, in a way that the call trampoline
2041 will load its value into the appropriate register. */
2042 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2043 ((MODE) == BLKmode \
2044 && TARGET_SHCOMPACT \
2045 && ! TARGET_LITTLE_ENDIAN \
2046 && int_size_in_bytes (TYPE) > 4 \
2047 && int_size_in_bytes (TYPE) < 8)
2048
2049 /* Minimum alignment for an argument to be passed by callee-copy
2050 reference. We need such arguments to be aligned to 8 byte
2051 boundaries, because they'll be loaded using quad loads. */
2052 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2053
2054 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2055 ((CUM).outgoing \
2056 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2057 : GET_MODE_ALIGNMENT (MODE)) \
2058 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2059
2060 /* The SH5 ABI requires floating-point arguments to be passed to
2061 functions without a prototype in both an FP register and a regular
2062 register or the stack. When passing the argument in both FP and
2063 general-purpose registers, list the FP register first. */
2064 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2065 (gen_rtx_PARALLEL \
2066 ((MODE), \
2067 gen_rtvec (2, \
2068 gen_rtx_EXPR_LIST \
2069 (VOIDmode, \
2070 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2071 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2072 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2073 : NULL_RTX), \
2074 const0_rtx), \
2075 gen_rtx_EXPR_LIST \
2076 (VOIDmode, \
2077 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2078 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2079 + (CUM).arg_count[(int) SH_ARG_INT]) \
2080 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2081 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2082 const0_rtx))))
2083
2084 /* The SH5 ABI requires regular registers or stack slots to be
2085 reserved for floating-point arguments. Registers are taken care of
2086 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2087 Unfortunately, there's no way to just reserve a stack slot, so
2088 we'll end up needlessly storing a copy of the argument in the
2089 stack. For incoming arguments, however, the PARALLEL will be
2090 optimized to the register-only form, and the value in the stack
2091 slot won't be used at all. */
2092 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2093 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2094 ? gen_rtx_REG ((MODE), (REG)) \
2095 : gen_rtx_PARALLEL ((MODE), \
2096 gen_rtvec (2, \
2097 gen_rtx_EXPR_LIST \
2098 (VOIDmode, NULL_RTX, \
2099 const0_rtx), \
2100 gen_rtx_EXPR_LIST \
2101 (VOIDmode, gen_rtx_REG ((MODE), \
2102 (REG)), \
2103 const0_rtx))))
2104
2105 /* For an arg passed partly in registers and partly in memory,
2106 this is the number of registers used.
2107 For args passed entirely in registers or entirely in memory, zero.
2108
2109 We sometimes split args. */
2110
2111 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2112 ((! TARGET_SH5 \
2113 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2114 && ! TARGET_SH4 \
2115 && (ROUND_REG ((CUM), (MODE)) \
2116 + ((MODE) != BLKmode \
2117 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2118 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2119 > NPARM_REGS (MODE))) \
2120 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2121 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2122 && ! TARGET_SHCOMPACT) \
2123 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2124 : 0)
2125
2126 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2127 (TARGET_SH5 \
2128 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2129 || (MODE) == DCmode) \
2130 && ((CUM).arg_count[(int) SH_ARG_INT] \
2131 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2132
2133 /* Perform any needed actions needed for a function that is receiving a
2134 variable number of arguments. */
2135
2136 /* Implement `va_start' for varargs and stdarg. */
2137 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2138 sh_va_start (valist, nextarg)
2139
2140 /* Call the function profiler with a given profile label.
2141 We use two .aligns, so as to make sure that both the .long is aligned
2142 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2143 from the trapa instruction. */
2144
2145 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2146 { \
2147 fprintf((STREAM), "\t.align\t2\n"); \
2148 fprintf((STREAM), "\ttrapa\t#33\n"); \
2149 fprintf((STREAM), "\t.align\t2\n"); \
2150 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2151 }
2152
2153 /* Define this macro if the code for function profiling should come
2154 before the function prologue. Normally, the profiling code comes
2155 after. */
2156
2157 #define PROFILE_BEFORE_PROLOGUE
2158
2159 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2160 the stack pointer does not matter. The value is tested only in
2161 functions that have frame pointers.
2162 No definition is equivalent to always zero. */
2163
2164 #define EXIT_IGNORE_STACK 1
2165
2166 /*
2167 On the SH, the trampoline looks like
2168 2 0002 D202 mov.l l2,r2
2169 1 0000 D301 mov.l l1,r3
2170 3 0004 422B jmp @r2
2171 4 0006 0009 nop
2172 5 0008 00000000 l1: .long area
2173 6 000c 00000000 l2: .long function */
2174
2175 /* Length in units of the trampoline for entering a nested function. */
2176 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2177
2178 /* Alignment required for a trampoline in bits . */
2179 #define TRAMPOLINE_ALIGNMENT \
2180 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2181 : TARGET_SHMEDIA ? 256 : 64)
2182
2183 /* Emit RTL insns to initialize the variable parts of a trampoline.
2184 FNADDR is an RTX for the address of the function's pure code.
2185 CXT is an RTX for the static chain value for the function. */
2186
2187 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2188 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2189
2190 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2191
2192 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2193 { \
2194 if (TARGET_SHMEDIA) \
2195 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2196 gen_reg_rtx (Pmode), 0, \
2197 OPTAB_LIB_WIDEN); \
2198 } while (0)
2199
2200 /* A C expression whose value is RTL representing the value of the return
2201 address for the frame COUNT steps up from the current frame.
2202 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2203 can ignore COUNT. */
2204
2205 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2206 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2207
2208 /* A C expression whose value is RTL representing the location of the
2209 incoming return address at the beginning of any function, before the
2210 prologue. This RTL is either a REG, indicating that the return
2211 value is saved in REG, or a MEM representing a location in
2212 the stack. */
2213 #define INCOMING_RETURN_ADDR_RTX \
2214 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2215 \f
2216 /* Addressing modes, and classification of registers for them. */
2217 #define HAVE_POST_INCREMENT TARGET_SH1
2218 #define HAVE_PRE_DECREMENT TARGET_SH1
2219
2220 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2221 ? 0 : TARGET_SH1)
2222 #define USE_LOAD_PRE_DECREMENT(mode) 0
2223 #define USE_STORE_POST_INCREMENT(mode) 0
2224 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2225 ? 0 : TARGET_SH1)
2226
2227 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2228 < (TARGET_SMALLCODE ? 2 : \
2229 ((ALIGN >= 32) ? 16 : 2)))
2230
2231 /* Macros to check register numbers against specific register classes. */
2232
2233 /* These assume that REGNO is a hard or pseudo reg number.
2234 They give nonzero only if REGNO is a hard reg of the suitable class
2235 or a pseudo reg currently allocated to a suitable hard reg.
2236 Since they use reg_renumber, they are safe only once reg_renumber
2237 has been allocated, which happens in local-alloc.c. */
2238
2239 #define REGNO_OK_FOR_BASE_P(REGNO) \
2240 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2241 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2242 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2243 (TARGET_SHMEDIA \
2244 ? (GENERAL_REGISTER_P (REGNO) \
2245 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2246 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2247
2248 /* Maximum number of registers that can appear in a valid memory
2249 address. */
2250
2251 #define MAX_REGS_PER_ADDRESS 2
2252
2253 /* Recognize any constant value that is a valid address. */
2254
2255 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2256
2257 /* Nonzero if the constant value X is a legitimate general operand. */
2258
2259 #define LEGITIMATE_CONSTANT_P(X) \
2260 (TARGET_SHMEDIA \
2261 ? ((GET_MODE (X) != DFmode \
2262 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2263 || (X) == CONST0_RTX (GET_MODE (X)) \
2264 || ! TARGET_SHMEDIA_FPU \
2265 || TARGET_SHMEDIA64) \
2266 : (GET_CODE (X) != CONST_DOUBLE \
2267 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2268 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2269
2270 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2271 and check its validity for a certain class.
2272 We have two alternate definitions for each of them.
2273 The usual definition accepts all pseudo regs; the other rejects
2274 them unless they have been allocated suitable hard regs.
2275 The symbol REG_OK_STRICT causes the latter definition to be used. */
2276
2277 #ifndef REG_OK_STRICT
2278
2279 /* Nonzero if X is a hard reg that can be used as a base reg
2280 or if it is a pseudo reg. */
2281 #define REG_OK_FOR_BASE_P(X) \
2282 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2283
2284 /* Nonzero if X is a hard reg that can be used as an index
2285 or if it is a pseudo reg. */
2286 #define REG_OK_FOR_INDEX_P(X) \
2287 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2288 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2289
2290 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2291 or if X is a pseudo reg. */
2292 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2293 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2294 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2295
2296 #else
2297
2298 /* Nonzero if X is a hard reg that can be used as a base reg. */
2299 #define REG_OK_FOR_BASE_P(X) \
2300 REGNO_OK_FOR_BASE_P (REGNO (X))
2301
2302 /* Nonzero if X is a hard reg that can be used as an index. */
2303 #define REG_OK_FOR_INDEX_P(X) \
2304 REGNO_OK_FOR_INDEX_P (REGNO (X))
2305
2306 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2307 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2308 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2309
2310 #endif
2311
2312 /* The 'Q' constraint is a pc relative load operand. */
2313 #define EXTRA_CONSTRAINT_Q(OP) \
2314 (GET_CODE (OP) == MEM \
2315 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2316 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2317 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2318 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2319 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2320
2321 /* Extra address constraints. */
2322 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2323
2324 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2325 operand is not SCRATCH (i.e. REG) then R0 is probably being
2326 used, hence mova is being used, hence do not select this pattern */
2327 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2328 #define EXTRA_CONSTRAINT_B(OP, STR) \
2329 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2330 : 0)
2331
2332 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2333 #define EXTRA_CONSTRAINT_C16(OP) \
2334 (GET_CODE (OP) == CONST \
2335 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2336 && GET_MODE (XEXP ((OP), 0)) == DImode \
2337 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2338 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2339 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2340 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2341 && (MOVI_SHORI_BASE_OPERAND_P \
2342 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2343 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2344 1)) == CONST_INT)))
2345
2346 /* Check whether OP is a datalabel unspec. */
2347 #define DATALABEL_REF_NO_CONST_P(OP) \
2348 (GET_CODE (OP) == UNSPEC \
2349 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2350 && XVECLEN ((OP), 0) == 1 \
2351 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2352 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2353
2354 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2355 CONST. */
2356 #define DATALABEL_REF_P(OP) \
2357 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2358 || DATALABEL_REF_NO_CONST_P (OP))
2359
2360 #define GOT_ENTRY_P(OP) \
2361 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2362 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2363
2364 #define GOTPLT_ENTRY_P(OP) \
2365 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2366 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2367
2368 #define UNSPEC_GOTOFF_P(OP) \
2369 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2370
2371 #define GOTOFF_P(OP) \
2372 (GET_CODE (OP) == CONST \
2373 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2374 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2375 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2376 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2377
2378 #define PIC_ADDR_P(OP) \
2379 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2380 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2381
2382 #define PIC_OFFSET_P(OP) \
2383 (PIC_ADDR_P (OP) \
2384 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2385 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2386
2387 #define PIC_DIRECT_ADDR_P(OP) \
2388 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2389
2390 #define NON_PIC_REFERENCE_P(OP) \
2391 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2392 || DATALABEL_REF_P (OP) \
2393 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2394 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2395 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2396 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2397
2398 #define PIC_REFERENCE_P(OP) \
2399 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2400 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2401
2402 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2403 (flag_pic \
2404 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2405 || PIC_OFFSET_P (OP)) \
2406 : NON_PIC_REFERENCE_P (OP))
2407
2408 /* The `Csy' constraint is a label or a symbol. */
2409 #define EXTRA_CONSTRAINT_Csy(OP) \
2410 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2411
2412 /* A zero in any shape or form. */
2413 #define EXTRA_CONSTRAINT_Z(OP) \
2414 ((OP) == CONST0_RTX (GET_MODE (OP)))
2415
2416 /* Any vector constant we can handle. */
2417 #define EXTRA_CONSTRAINT_W(OP) \
2418 (GET_CODE (OP) == CONST_VECTOR \
2419 && (sh_rep_vec ((OP), VOIDmode) \
2420 || (HOST_BITS_PER_WIDE_INT >= 64 \
2421 ? sh_const_vec ((OP), VOIDmode) \
2422 : sh_1el_vec ((OP), VOIDmode))))
2423
2424 /* A non-explicit constant that can be loaded directly into a general purpose
2425 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2426 #define EXTRA_CONSTRAINT_Cpg(OP) \
2427 (CONSTANT_P (OP) \
2428 && GET_CODE (OP) != CONST_INT \
2429 && GET_CODE (OP) != CONST_DOUBLE \
2430 && (!flag_pic \
2431 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2432 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2433 && GET_CODE (OP) != LABEL_REF)))
2434 #define EXTRA_CONSTRAINT_C(OP, STR) \
2435 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2436 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2437 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2438 : 0)
2439
2440 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2441 #define EXTRA_CONSTRAINT_Sr0(OP) \
2442 (memory_operand((OP), GET_MODE (OP)) \
2443 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2444 #define EXTRA_CONSTRAINT_S(OP, STR) \
2445 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2446 : 0)
2447
2448 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2449 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2450 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2451 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2452 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2453 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2454 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2455 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2456 : 0)
2457 \f
2458 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2459 that is a valid memory address for an instruction.
2460 The MODE argument is the machine mode for the MEM expression
2461 that wants to use this address. */
2462
2463 #define MODE_DISP_OK_4(X,MODE) \
2464 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2465 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2466
2467 #define MODE_DISP_OK_8(X,MODE) \
2468 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2469 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2470
2471 #define BASE_REGISTER_RTX_P(X) \
2472 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2473 || (GET_CODE (X) == SUBREG \
2474 && GET_CODE (SUBREG_REG (X)) == REG \
2475 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2476
2477 /* Since this must be r0, which is a single register class, we must check
2478 SUBREGs more carefully, to be sure that we don't accept one that extends
2479 outside the class. */
2480 #define INDEX_REGISTER_RTX_P(X) \
2481 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2482 || (GET_CODE (X) == SUBREG \
2483 && GET_CODE (SUBREG_REG (X)) == REG \
2484 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2485
2486 /* Jump to LABEL if X is a valid address RTX. This must also take
2487 REG_OK_STRICT into account when deciding about valid registers, but it uses
2488 the above macros so we are in luck.
2489
2490 Allow REG
2491 REG+disp
2492 REG+r0
2493 REG++
2494 --REG */
2495
2496 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2497 into the FRx registers. We implement this by setting the maximum offset
2498 to zero when the value is SFmode. This also restricts loading of SFmode
2499 values into the integer registers, but that can't be helped. */
2500
2501 /* The SH allows a displacement in a QI or HI amode, but only when the
2502 other operand is R0. GCC doesn't handle this very well, so we forgo
2503 all of that.
2504
2505 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2506 DI can be any number 0..60. */
2507
2508 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2509 do { \
2510 if (GET_CODE (OP) == CONST_INT) \
2511 { \
2512 if (TARGET_SHMEDIA) \
2513 { \
2514 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2515 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2516 && INTVAL (OP) >= -512 * MODE_SIZE \
2517 && INTVAL (OP) < 512 * MODE_SIZE) \
2518 goto LABEL; \
2519 else \
2520 break; \
2521 } \
2522 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2523 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2524 } \
2525 } while(0)
2526
2527 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2528 { \
2529 if (BASE_REGISTER_RTX_P (X)) \
2530 goto LABEL; \
2531 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2532 && ! TARGET_SHMEDIA \
2533 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2534 goto LABEL; \
2535 else if (GET_CODE (X) == PLUS \
2536 && ((MODE) != PSImode || reload_completed)) \
2537 { \
2538 rtx xop0 = XEXP ((X), 0); \
2539 rtx xop1 = XEXP ((X), 1); \
2540 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2541 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2542 if (GET_MODE_SIZE (MODE) <= 4 \
2543 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2544 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2545 { \
2546 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2547 goto LABEL; \
2548 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2549 goto LABEL; \
2550 } \
2551 } \
2552 }
2553 \f
2554 /* Try machine-dependent ways of modifying an illegitimate address
2555 to be legitimate. If we find one, return the new, valid address.
2556 This macro is used in only one place: `memory_address' in explow.c.
2557
2558 OLDX is the address as it was before break_out_memory_refs was called.
2559 In some cases it is useful to look at this to decide what needs to be done.
2560
2561 MODE and WIN are passed so that this macro can use
2562 GO_IF_LEGITIMATE_ADDRESS.
2563
2564 It is always safe for this macro to do nothing. It exists to recognize
2565 opportunities to optimize the output.
2566
2567 For the SH, if X is almost suitable for indexing, but the offset is
2568 out of range, convert it into a normal form so that cse has a chance
2569 of reducing the number of address registers used. */
2570
2571 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2572 { \
2573 if (flag_pic) \
2574 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2575 if (GET_CODE (X) == PLUS \
2576 && (GET_MODE_SIZE (MODE) == 4 \
2577 || GET_MODE_SIZE (MODE) == 8) \
2578 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2579 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2580 && ! TARGET_SHMEDIA \
2581 && ! (TARGET_SH4 && (MODE) == DFmode) \
2582 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2583 { \
2584 rtx index_rtx = XEXP ((X), 1); \
2585 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2586 rtx sum; \
2587 \
2588 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2589 /* On rare occasions, we might get an unaligned pointer \
2590 that is indexed in a way to give an aligned address. \
2591 Therefore, keep the lower two bits in offset_base. */ \
2592 /* Instead of offset_base 128..131 use 124..127, so that \
2593 simple add suffices. */ \
2594 if (offset > 127) \
2595 { \
2596 offset_base = ((offset + 4) & ~60) - 4; \
2597 } \
2598 else \
2599 offset_base = offset & ~60; \
2600 /* Sometimes the normal form does not suit DImode. We \
2601 could avoid that by using smaller ranges, but that \
2602 would give less optimized code when SImode is \
2603 prevalent. */ \
2604 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2605 { \
2606 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2607 GEN_INT (offset_base), NULL_RTX, 0, \
2608 OPTAB_LIB_WIDEN); \
2609 \
2610 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2611 goto WIN; \
2612 } \
2613 } \
2614 }
2615
2616 /* A C compound statement that attempts to replace X, which is an address
2617 that needs reloading, with a valid memory address for an operand of
2618 mode MODE. WIN is a C statement label elsewhere in the code.
2619
2620 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2621 of the address. That will allow inheritance of the address reloads. */
2622
2623 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2624 { \
2625 if (GET_CODE (X) == PLUS \
2626 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2627 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2628 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2629 && ! TARGET_SHMEDIA \
2630 && ! (TARGET_SH4 && (MODE) == DFmode) \
2631 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2632 { \
2633 rtx index_rtx = XEXP (X, 1); \
2634 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2635 rtx sum; \
2636 \
2637 if (TARGET_SH2E && MODE == SFmode) \
2638 { \
2639 X = copy_rtx (X); \
2640 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2641 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2642 (TYPE)); \
2643 goto WIN; \
2644 } \
2645 /* Instead of offset_base 128..131 use 124..127, so that \
2646 simple add suffices. */ \
2647 if (offset > 127) \
2648 { \
2649 offset_base = ((offset + 4) & ~60) - 4; \
2650 } \
2651 else \
2652 offset_base = offset & ~60; \
2653 /* Sometimes the normal form does not suit DImode. We \
2654 could avoid that by using smaller ranges, but that \
2655 would give less optimized code when SImode is \
2656 prevalent. */ \
2657 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2658 { \
2659 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2660 GEN_INT (offset_base)); \
2661 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2662 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2663 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2664 (TYPE)); \
2665 goto WIN; \
2666 } \
2667 } \
2668 /* We must re-recognize what we created before. */ \
2669 else if (GET_CODE (X) == PLUS \
2670 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2671 && GET_CODE (XEXP (X, 0)) == PLUS \
2672 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2673 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2674 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2675 && ! TARGET_SHMEDIA \
2676 && ! (TARGET_SH2E && MODE == SFmode)) \
2677 { \
2678 /* Because this address is so complex, we know it must have \
2679 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2680 it is already unshared, and needs no further unsharing. */ \
2681 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2682 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2683 goto WIN; \
2684 } \
2685 }
2686
2687 /* Go to LABEL if ADDR (a legitimate address expression)
2688 has an effect that depends on the machine mode it is used for.
2689
2690 ??? Strictly speaking, we should also include all indexed addressing,
2691 because the index scale factor is the length of the operand.
2692 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2693 high if we did that. So we rely on reload to fix things up. */
2694
2695 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2696 { \
2697 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2698 goto LABEL; \
2699 }
2700 \f
2701 /* Specify the machine mode that this machine uses
2702 for the index in the tablejump instruction. */
2703 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2704
2705 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2706 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2707 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2708 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2709 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2710 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2711 : SImode)
2712
2713 /* Define as C expression which evaluates to nonzero if the tablejump
2714 instruction expects the table to contain offsets from the address of the
2715 table.
2716 Do not define this if the table should contain absolute addresses. */
2717 #define CASE_VECTOR_PC_RELATIVE 1
2718
2719 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2720 #define FLOAT_TYPE_SIZE 32
2721
2722 /* Since the SH2e has only `float' support, it is desirable to make all
2723 floating point types equivalent to `float'. */
2724 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
2725
2726 /* 'char' is signed by default. */
2727 #define DEFAULT_SIGNED_CHAR 1
2728
2729 /* The type of size_t unsigned int. */
2730 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2731
2732 #undef PTRDIFF_TYPE
2733 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2734
2735 #define WCHAR_TYPE "short unsigned int"
2736 #define WCHAR_TYPE_SIZE 16
2737
2738 #define SH_ELF_WCHAR_TYPE "long int"
2739
2740 /* Max number of bytes we can move from memory to memory
2741 in one reasonably fast instruction. */
2742 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2743
2744 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2745 MOVE_MAX is not a compile-time constant. */
2746 #define MAX_MOVE_MAX 8
2747
2748 /* Max number of bytes we want move_by_pieces to be able to copy
2749 efficiently. */
2750 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2751
2752 /* Define if operations between registers always perform the operation
2753 on the full register even if a narrower mode is specified. */
2754 #define WORD_REGISTER_OPERATIONS
2755
2756 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2757 will either zero-extend or sign-extend. The value of this macro should
2758 be the code that says which one of the two operations is implicitly
2759 done, NIL if none. */
2760 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2761 /* FP registers can load SImode values, but don't implicitly sign-extend
2762 them to DImode. */
2763 #define LOAD_EXTEND_OP(MODE) \
2764 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2765 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2766
2767 /* Define if loading short immediate values into registers sign extends. */
2768 #define SHORT_IMMEDIATES_SIGN_EXTEND
2769
2770 /* Nonzero if access to memory by bytes is no faster than for words. */
2771 #define SLOW_BYTE_ACCESS 1
2772
2773 /* Immediate shift counts are truncated by the output routines (or was it
2774 the assembler?). Shift counts in a register are truncated by SH. Note
2775 that the native compiler puts too large (> 32) immediate shift counts
2776 into a register and shifts by the register, letting the SH decide what
2777 to do instead of doing that itself. */
2778 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2779 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2780 expects - the sign bit is significant - so it appears that we need to
2781 leave this zero for correct SH3 code. */
2782 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2783
2784 /* All integers have the same format so truncation is easy. */
2785 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2786
2787 /* Define this if addresses of constant functions
2788 shouldn't be put through pseudo regs where they can be cse'd.
2789 Desirable on machines where ordinary constants are expensive
2790 but a CALL with constant address is cheap. */
2791 /*#define NO_FUNCTION_CSE 1*/
2792
2793 /* The machine modes of pointers and functions. */
2794 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2795 #define FUNCTION_MODE Pmode
2796
2797 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2798 are actually function calls with some special constraints on arguments
2799 and register usage.
2800
2801 These macros tell reorg that the references to arguments and
2802 register clobbers for insns of type sfunc do not appear to happen
2803 until after the millicode call. This allows reorg to put insns
2804 which set the argument registers into the delay slot of the millicode
2805 call -- thus they act more like traditional CALL_INSNs.
2806
2807 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2808 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2809 in particular. */
2810
2811 #define INSN_SETS_ARE_DELAYED(X) \
2812 ((GET_CODE (X) == INSN \
2813 && GET_CODE (PATTERN (X)) != SEQUENCE \
2814 && GET_CODE (PATTERN (X)) != USE \
2815 && GET_CODE (PATTERN (X)) != CLOBBER \
2816 && get_attr_is_sfunc (X)))
2817
2818 #define INSN_REFERENCES_ARE_DELAYED(X) \
2819 ((GET_CODE (X) == INSN \
2820 && GET_CODE (PATTERN (X)) != SEQUENCE \
2821 && GET_CODE (PATTERN (X)) != USE \
2822 && GET_CODE (PATTERN (X)) != CLOBBER \
2823 && get_attr_is_sfunc (X)))
2824
2825 \f
2826 /* Position Independent Code. */
2827
2828 /* We can't directly access anything that contains a symbol,
2829 nor can we indirect via the constant pool. */
2830 #define LEGITIMATE_PIC_OPERAND_P(X) \
2831 ((! nonpic_symbol_mentioned_p (X) \
2832 && (GET_CODE (X) != SYMBOL_REF \
2833 || ! CONSTANT_POOL_ADDRESS_P (X) \
2834 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2835 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2836
2837 #define SYMBOLIC_CONST_P(X) \
2838 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2839 && nonpic_symbol_mentioned_p (X))
2840 \f
2841 /* Compute extra cost of moving data between one register class
2842 and another. */
2843
2844 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2845 uses this information. Hence, the general register <-> floating point
2846 register information here is not used for SFmode. */
2847
2848 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2849 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2850 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2851
2852 #define REGCLASS_HAS_FP_REG(CLASS) \
2853 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2854 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2855
2856 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2857 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2858
2859 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2860 would be so that people with slow memory systems could generate
2861 different code that does fewer memory accesses. */
2862
2863 /* A C expression for the cost of a branch instruction. A value of 1
2864 is the default; other values are interpreted relative to that.
2865 The SH1 does not have delay slots, hence we get a pipeline stall
2866 at every branch. The SH4 is superscalar, so the single delay slot
2867 is not sufficient to keep both pipelines filled. */
2868 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2869 \f
2870 /* Assembler output control. */
2871
2872 /* A C string constant describing how to begin a comment in the target
2873 assembler language. The compiler assumes that the comment will end at
2874 the end of the line. */
2875 #define ASM_COMMENT_START "!"
2876
2877 #define ASM_APP_ON ""
2878 #define ASM_APP_OFF ""
2879 #define FILE_ASM_OP "\t.file\n"
2880 #define SET_ASM_OP "\t.set\t"
2881
2882 /* How to change between sections. */
2883
2884 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2885 #define DATA_SECTION_ASM_OP "\t.data"
2886
2887 #if defined CRT_BEGIN || defined CRT_END
2888 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2889 # undef TEXT_SECTION_ASM_OP
2890 # if __SHMEDIA__ == 1 && __SH5__ == 32
2891 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2892 # else
2893 # define TEXT_SECTION_ASM_OP "\t.text"
2894 # endif
2895 #endif
2896
2897
2898 /* If defined, a C expression whose value is a string containing the
2899 assembler operation to identify the following data as
2900 uninitialized global data. If not defined, and neither
2901 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2902 uninitialized global data will be output in the data section if
2903 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2904 used. */
2905 #ifndef BSS_SECTION_ASM_OP
2906 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2907 #endif
2908
2909 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2910 separate, explicit argument. If you define this macro, it is used
2911 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2912 handling the required alignment of the variable. The alignment is
2913 specified as the number of bits.
2914
2915 Try to use function `asm_output_aligned_bss' defined in file
2916 `varasm.c' when defining this macro. */
2917 #ifndef ASM_OUTPUT_ALIGNED_BSS
2918 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2919 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2920 #endif
2921
2922 /* Define this so that jump tables go in same section as the current function,
2923 which could be text or it could be a user defined section. */
2924 #define JUMP_TABLES_IN_TEXT_SECTION 1
2925
2926 #undef DO_GLOBAL_CTORS_BODY
2927 #define DO_GLOBAL_CTORS_BODY \
2928 { \
2929 typedef (*pfunc)(); \
2930 extern pfunc __ctors[]; \
2931 extern pfunc __ctors_end[]; \
2932 pfunc *p; \
2933 for (p = __ctors_end; p > __ctors; ) \
2934 { \
2935 (*--p)(); \
2936 } \
2937 }
2938
2939 #undef DO_GLOBAL_DTORS_BODY
2940 #define DO_GLOBAL_DTORS_BODY \
2941 { \
2942 typedef (*pfunc)(); \
2943 extern pfunc __dtors[]; \
2944 extern pfunc __dtors_end[]; \
2945 pfunc *p; \
2946 for (p = __dtors; p < __dtors_end; p++) \
2947 { \
2948 (*p)(); \
2949 } \
2950 }
2951
2952 #define ASM_OUTPUT_REG_PUSH(file, v) \
2953 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
2954
2955 #define ASM_OUTPUT_REG_POP(file, v) \
2956 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
2957
2958 /* DBX register number for a given compiler register number. */
2959 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2960 to match gdb. */
2961 /* svr4.h undefines this macro, yet we really want to use the same numbers
2962 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2963 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2964 register exists, so we should return -1 for invalid register numbers. */
2965 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2966
2967 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2968 used to use the encodings 245..260, but that doesn't make sense:
2969 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2970 the FP registers stay the same when switching between compact and media
2971 mode. Hence, we also need to use the same dwarf frame columns.
2972 Likewise, we need to support unwind information for SHmedia registers
2973 even in compact code. */
2974 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2975 (IN_RANGE ((REGNO), \
2976 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2977 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2978 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2979 : ((int) (REGNO) >= FIRST_FP_REG \
2980 && ((int) (REGNO) \
2981 <= (FIRST_FP_REG + \
2982 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2983 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2984 + (TARGET_SH5 ? 77 : 25)) \
2985 : XD_REGISTER_P (REGNO) \
2986 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2987 : TARGET_REGISTER_P (REGNO) \
2988 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2989 : (REGNO) == PR_REG \
2990 ? (TARGET_SH5 ? 18 : 17) \
2991 : (REGNO) == PR_MEDIA_REG \
2992 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2993 : (REGNO) == T_REG \
2994 ? (TARGET_SH5 ? 242 : 18) \
2995 : (REGNO) == GBR_REG \
2996 ? (TARGET_SH5 ? 238 : 19) \
2997 : (REGNO) == MACH_REG \
2998 ? (TARGET_SH5 ? 239 : 20) \
2999 : (REGNO) == MACL_REG \
3000 ? (TARGET_SH5 ? 240 : 21) \
3001 : (REGNO) == FPUL_REG \
3002 ? (TARGET_SH5 ? 244 : 23) \
3003 : (unsigned) -1)
3004
3005 /* This is how to output a reference to a symbol_ref. On SH5,
3006 references to non-code symbols must be preceded by `datalabel'. */
3007 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3008 do \
3009 { \
3010 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3011 fputs ("datalabel ", (FILE)); \
3012 assemble_name ((FILE), XSTR ((SYM), 0)); \
3013 } \
3014 while (0)
3015
3016 /* This is how to output an assembler line
3017 that says to advance the location counter
3018 to a multiple of 2**LOG bytes. */
3019
3020 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3021 if ((LOG) != 0) \
3022 fprintf ((FILE), "\t.align %d\n", (LOG))
3023
3024 /* Globalizing directive for a label. */
3025 #define GLOBAL_ASM_OP "\t.global\t"
3026
3027 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3028
3029 /* Output a relative address table. */
3030
3031 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3032 switch (GET_MODE (BODY)) \
3033 { \
3034 case SImode: \
3035 if (TARGET_SH5) \
3036 { \
3037 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3038 (VALUE), (REL)); \
3039 break; \
3040 } \
3041 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3042 break; \
3043 case HImode: \
3044 if (TARGET_SH5) \
3045 { \
3046 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3047 (VALUE), (REL)); \
3048 break; \
3049 } \
3050 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3051 break; \
3052 case QImode: \
3053 if (TARGET_SH5) \
3054 { \
3055 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3056 (VALUE), (REL)); \
3057 break; \
3058 } \
3059 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3060 break; \
3061 default: \
3062 break; \
3063 }
3064
3065 /* Output an absolute table element. */
3066
3067 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3068 if (! optimize || TARGET_BIGTABLE) \
3069 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3070 else \
3071 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3072
3073 \f
3074 /* A C statement to be executed just prior to the output of
3075 assembler code for INSN, to modify the extracted operands so
3076 they will be output differently.
3077
3078 Here the argument OPVEC is the vector containing the operands
3079 extracted from INSN, and NOPERANDS is the number of elements of
3080 the vector which contain meaningful data for this insn.
3081 The contents of this vector are what will be used to convert the insn
3082 template into assembler code, so you can change the assembler output
3083 by changing the contents of the vector. */
3084
3085 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3086 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3087
3088 /* Print operand X (an rtx) in assembler syntax to file FILE.
3089 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3090 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3091
3092 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3093
3094 /* Print a memory address as an operand to reference that memory location. */
3095
3096 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3097
3098 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3099 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3100 || (CHAR) == '$'|| (CHAR) == '\'')
3101
3102 /* Recognize machine-specific patterns that may appear within
3103 constants. Used for PIC-specific UNSPECs. */
3104 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3105 do \
3106 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3107 { \
3108 switch (XINT ((X), 1)) \
3109 { \
3110 case UNSPEC_DATALABEL: \
3111 fputs ("datalabel ", (STREAM)); \
3112 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3113 break; \
3114 case UNSPEC_PIC: \
3115 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3116 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3117 break; \
3118 case UNSPEC_GOT: \
3119 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3120 fputs ("@GOT", (STREAM)); \
3121 break; \
3122 case UNSPEC_GOTOFF: \
3123 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3124 fputs ("@GOTOFF", (STREAM)); \
3125 break; \
3126 case UNSPEC_PLT: \
3127 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3128 fputs ("@PLT", (STREAM)); \
3129 break; \
3130 case UNSPEC_GOTPLT: \
3131 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3132 fputs ("@GOTPLT", (STREAM)); \
3133 break; \
3134 case UNSPEC_DTPOFF: \
3135 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3136 fputs ("@DTPOFF", (STREAM)); \
3137 break; \
3138 case UNSPEC_GOTTPOFF: \
3139 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3140 fputs ("@GOTTPOFF", (STREAM)); \
3141 break; \
3142 case UNSPEC_TPOFF: \
3143 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3144 fputs ("@TPOFF", (STREAM)); \
3145 break; \
3146 case UNSPEC_CALLER: \
3147 { \
3148 char name[32]; \
3149 /* LPCS stands for Label for PIC Call Site. */ \
3150 ASM_GENERATE_INTERNAL_LABEL \
3151 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3152 assemble_name ((STREAM), name); \
3153 } \
3154 break; \
3155 default: \
3156 goto FAIL; \
3157 } \
3158 break; \
3159 } \
3160 else \
3161 goto FAIL; \
3162 while (0)
3163
3164 \f
3165 extern struct rtx_def *sh_compare_op0;
3166 extern struct rtx_def *sh_compare_op1;
3167
3168 /* Which processor to schedule for. The elements of the enumeration must
3169 match exactly the cpu attribute in the sh.md file. */
3170
3171 enum processor_type {
3172 PROCESSOR_SH1,
3173 PROCESSOR_SH2,
3174 PROCESSOR_SH2E,
3175 PROCESSOR_SH3,
3176 PROCESSOR_SH3E,
3177 PROCESSOR_SH4,
3178 PROCESSOR_SH5
3179 };
3180
3181 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3182 extern enum processor_type sh_cpu;
3183
3184 extern int optimize; /* needed for gen_casesi. */
3185
3186 enum mdep_reorg_phase_e
3187 {
3188 SH_BEFORE_MDEP_REORG,
3189 SH_INSERT_USES_LABELS,
3190 SH_SHORTEN_BRANCHES0,
3191 SH_FIXUP_PCLOAD,
3192 SH_SHORTEN_BRANCHES1,
3193 SH_AFTER_MDEP_REORG
3194 };
3195
3196 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3197
3198 /* Handle Renesas compiler's pragmas. */
3199 #define REGISTER_TARGET_PRAGMAS() do { \
3200 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3201 c_register_pragma (0, "trapa", sh_pr_trapa); \
3202 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3203 } while (0)
3204
3205 /* Set when processing a function with pragma interrupt turned on. */
3206
3207 extern int pragma_interrupt;
3208
3209 /* Set when processing a function with interrupt attribute. */
3210
3211 extern int current_function_interrupt;
3212
3213 /* Set to an RTX containing the address of the stack to switch to
3214 for interrupt functions. */
3215 extern struct rtx_def *sp_switch;
3216
3217 extern int rtx_equal_function_value_matters;
3218
3219 \f
3220 /* Instructions with unfilled delay slots take up an
3221 extra two bytes for the nop in the delay slot.
3222 sh-dsp parallel processing insns are four bytes long. */
3223
3224 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3225 (LENGTH) += sh_insn_length_adjustment (X);
3226 \f
3227 /* Define the codes that are matched by predicates in sh.c. */
3228 #define PREDICATE_CODES \
3229 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3230 {"any_register_operand", {SUBREG, REG}}, \
3231 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3232 {"arith_reg_dest", {SUBREG, REG}}, \
3233 {"arith_reg_operand", {SUBREG, REG}}, \
3234 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3235 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3236 {"binary_logical_operator", {AND, IOR, XOR}}, \
3237 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
3238 {"commutative_float_operator", {PLUS, MULT}}, \
3239 {"equality_comparison_operator", {EQ,NE}}, \
3240 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3241 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3242 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3243 {"fpscr_operand", {REG}}, \
3244 {"fpul_operand", {REG}}, \
3245 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3246 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3247 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3248 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3249 {"int_gpr_dest", {SUBREG, REG}}, \
3250 {"inqhi_operand", {TRUNCATE}}, \
3251 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3252 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3253 {"mextr_bit_offset", {CONST_INT}}, \
3254 {"noncommutative_float_operator", {MINUS, DIV}}, \
3255 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3256 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3257 {"target_reg_operand", {SUBREG, REG}}, \
3258 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3259 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3260 {"register_operand", {SUBREG, REG}}, \
3261 {"sh_const_vec", {CONST_VECTOR}}, \
3262 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3263 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3264 {"symbol_ref_operand", {SYMBOL_REF}}, \
3265 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3266
3267 #define SPECIAL_MODE_PREDICATES \
3268 "any_register_operand", \
3269 "int_gpr_dest", \
3270 "trunc_hi_operand", \
3271 /* This line intentionally left blank. */
3272
3273 #define any_register_operand register_operand
3274
3275 /* Define this macro if it is advisable to hold scalars in registers
3276 in a wider mode than that declared by the program. In such cases,
3277 the value is constrained to be within the bounds of the declared
3278 type, but kept valid in the wider mode. The signedness of the
3279 extension may differ from that of the type.
3280
3281 Leaving the unsignedp unchanged gives better code than always setting it
3282 to 0. This is despite the fact that we have only signed char and short
3283 load instructions. */
3284 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3285 if (GET_MODE_CLASS (MODE) == MODE_INT \
3286 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3287 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3288 (MODE) = (TARGET_SH1 ? SImode : DImode);
3289
3290 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3291
3292 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3293 and popping arguments. However, we do have push/pop instructions, and
3294 rather limited offsets (4 bits) in load/store instructions, so it isn't
3295 clear if this would give better code. If implemented, should check for
3296 compatibility problems. */
3297
3298 #define SH_DYNAMIC_SHIFT_COST \
3299 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3300
3301
3302 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3303
3304 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3305
3306 #define ACTUAL_NORMAL_MODE(ENTITY) \
3307 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3308
3309 #define NORMAL_MODE(ENTITY) \
3310 (sh_cfun_interrupt_handler_p () \
3311 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3312 : ACTUAL_NORMAL_MODE (ENTITY))
3313
3314 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3315
3316 #define MODE_EXIT(ENTITY) \
3317 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3318
3319 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3320 && (REGNO) == FPSCR_REG)
3321
3322 #define MODE_NEEDED(ENTITY, INSN) \
3323 (recog_memoized (INSN) >= 0 \
3324 ? get_attr_fp_mode (INSN) \
3325 : FP_MODE_NONE)
3326
3327 #define MODE_AFTER(MODE, INSN) \
3328 (TARGET_HITACHI \
3329 && recog_memoized (INSN) >= 0 \
3330 && get_attr_fp_set (INSN) != FP_SET_NONE \
3331 ? (int) get_attr_fp_set (INSN) \
3332 : (MODE))
3333
3334 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3335 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3336
3337 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3338 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3339
3340 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3341 sh_can_redirect_branch ((INSN), (SEQ))
3342
3343 #define DWARF_FRAME_RETURN_COLUMN \
3344 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3345
3346 #define EH_RETURN_DATA_REGNO(N) \
3347 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3348
3349 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3350 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3351
3352 /* We have to distinguish between code and data, so that we apply
3353 datalabel where and only where appropriate. Use textrel for code. */
3354 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3355 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3356 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3357
3358 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3359 indirect are handled automatically. */
3360 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3361 do { \
3362 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3363 { \
3364 encoding &= ~DW_EH_PE_textrel; \
3365 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3366 if (GET_CODE (ADDR) != SYMBOL_REF) \
3367 abort (); \
3368 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3369 if (0) goto DONE; \
3370 } \
3371 } while (0)
3372
3373 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3374 /* SH constant pool breaks the devices in crtstuff.c to control section
3375 in where code resides. We have to write it as asm code. */
3376 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3377 asm (SECTION_OP "\n\
3378 mov.l 1f,r1\n\
3379 mova 2f,r0\n\
3380 braf r1\n\
3381 lds r0,pr\n\
3382 0: .p2align 2\n\
3383 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3384 2:\n" TEXT_SECTION_ASM_OP);
3385 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3386
3387 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3388 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3389 ? (current_function_is_leaf \
3390 && ! sh_pr_n_sets () \
3391 && ! (TARGET_SHCOMPACT \
3392 && ((current_function_args_info.call_cookie \
3393 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3394 || current_function_has_nonlocal_label)) \
3395 ? (hard_reg) \
3396 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \
3397 : NULL_RTX)
3398
3399 #endif /* ! GCC_SH_H */
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