1 ;; GCC machine description for CRIS cpu cores.
2 ;; Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 ;; 2008, 2009 Free Software Foundation, Inc.
4 ;; Contributed by Axis Communications.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; The original PO technology requires these to be ordered by speed,
23 ;; so that assigner will pick the fastest.
25 ;; See files "md.texi" and "rtl.def" for documentation on define_insn,
28 ;; The function cris_notice_update_cc in cris.c handles condition code
29 ;; updates for most instructions, helped by the "cc" attribute.
31 ;; There are several instructions that are orthogonal in size, and seems
32 ;; they could be matched by a single pattern without a specified size
33 ;; for the operand that is orthogonal. However, this did not work on
34 ;; gcc-2.7.2 (and probably not on gcc-2.8.1), relating to that when a
35 ;; constant is substituted into an operand, the actual mode must be
36 ;; deduced from the pattern. There is reasonable hope that that has been
37 ;; fixed, so FIXME: try again.
39 ;; You will notice that three-operand alternatives ("=r", "r", "!To")
40 ;; are marked with a "!" constraint modifier to avoid being reloaded
41 ;; into. This is because gcc would otherwise prefer to use the constant
42 ;; pool and its offsettable address instead of reloading to an
43 ;; ("=r", "0", "i") alternative. Also, the constant-pool support was not
44 ;; only suboptimal but also buggy in 2.7.2, ??? maybe only in 2.6.3.
46 ;; All insns that look like (set (...) (plus (...) (reg:SI 8)))
47 ;; get problems when reloading r8 (frame pointer) to r14 + offs (stack
48 ;; pointer). Thus the instructions that get into trouble have specific
49 ;; checks against matching frame_pointer_rtx.
50 ;; ??? But it should be re-checked for gcc > 2.7.2
51 ;; FIXME: This changed some time ago (from 2000-03-16) for gcc-2.9x.
53 ;; FIXME: When PIC, all [rX=rY+S] could be enabled to match
54 ;; [rX=gotless_symbol].
55 ;; The movsi for a gotless symbol could be split (post reload).
60 ;; PLT reference from call expansion: operand 0 is the address,
61 ;; the mode is VOIDmode. Always wrapped in CONST.
62 ;; The value is relative to the GOT.
63 (CRIS_UNSPEC_PLT_GOTREL 0)
65 ;; PLT reference from call expansion: operand 0 is the address,
66 ;; the mode is VOIDmode. Always wrapped in CONST.
67 ;; The value is relative to the PC. It's arch-dependent whether
68 ;; the offset counts from the start or the end of the current item.
69 (CRIS_UNSPEC_PLT_PCREL 1)
71 ;; The address of the global offset table as a source operand.
74 ;; The offset from the global offset table to the operand.
75 (CRIS_UNSPEC_GOTREL 3)
77 ;; The PC-relative offset to the operand. It's arch-dependent whether
78 ;; the offset counts from the start or the end of the current item.
81 ;; The index into the global offset table of a symbol, while
82 ;; also generating a GOT entry for the symbol.
83 (CRIS_UNSPEC_GOTREAD 5)
85 ;; Similar to CRIS_UNSPEC_GOTREAD, but also generating a PLT entry.
86 (CRIS_UNSPEC_PLTGOTREAD 6)
88 ;; Condition for v32 casesi jump, since it needs to have if_then_else
89 ;; form with register as one branch and default label as other.
90 ;; Operand 0 is const_int 0.
91 (CRIS_UNSPEC_CASESI 7)
93 ;; Stack frame deallocation barrier.
94 (CRIS_UNSPEC_FRAME_DEALLOC 8)
96 ;; Swap all 32 bits of the operand; 31 <=> 0, 30 <=> 1...
97 (CRIS_UNSPEC_SWAP_BITS 9)
103 (CRIS_STATIC_CHAIN_REGNUM 7)
110 (CRIS_CC0_REGNUM 19)]
113 ;; We need an attribute to define whether an instruction can be put in
114 ;; a branch-delay slot or not, and whether it has a delay slot.
116 ;; Branches and return instructions have a delay slot, and cannot
117 ;; themselves be put in a delay slot. This has changed *for short
118 ;; branches only* between architecture variants, but the possible win
119 ;; is presumed negligible compared to the added complexity of the machine
120 ;; description: one would have to add always-correct infrastructure to
121 ;; distinguish short branches.
123 ;; Whether an instruction can be put in a delay slot depends on the
124 ;; instruction (all short instructions except jumps and branches)
125 ;; and the addressing mode (must not be prefixed or referring to pc).
126 ;; In short, any "slottable" instruction must be 16 bit and not refer
127 ;; to pc, or alter it.
129 ;; The possible values are "yes", "no", "has_slot", "has_return_slot"
130 ;; and "has_call_slot".
131 ;; Yes/no tells whether the insn is slottable or not. Has_call_slot means
132 ;; that the insn is a call insn, which for CRIS v32 has a delay-slot.
133 ;; Of special concern is that no RTX_FRAME_RELATED insn must go in that
134 ;; call delay slot, as it's located in the address *after* the call insn,
135 ;; and the unwind machinery doesn't know about delay slots.
136 ;; Has_slot means that the insn is a branch insn (which are
137 ;; not considered slottable since that is generally true). Having the
138 ;; seemingly illogical value "has_slot" means we do not have to add
139 ;; another attribute just to say that an insn has a delay-slot, since it
140 ;; also infers that it is not slottable. Better names for the attribute
141 ;; were found to be longer and not add readability to the machine
143 ;; Has_return_slot is similar, for the return insn.
145 ;; The default that is defined here for this attribute is "no", not
146 ;; slottable, not having a delay-slot, so there's no need to worry about
147 ;; it being wrong for non-branch and return instructions.
148 ;; The default could depend on the kind of insn and the addressing
149 ;; mode, but that would need more attributes and hairier, more error
152 ;; There is an extra memory constraint, 'Q', which recognizes an indirect
153 ;; register. The constraints 'Q' and '>' together match all possible
154 ;; memory operands that are slottable.
155 ;; For other operands, you need to check if it has a valid "slottable"
156 ;; quick-immediate operand, where the particular signedness-variation
157 ;; may match the constraints 'I' or 'J'.), and include it in the
158 ;; constraint pattern for the slottable pattern. An alternative using
159 ;; only "r" constraints is most often slottable.
161 (define_attr "slottable" "no,yes,has_slot,has_return_slot,has_call_slot"
164 ;; We also need attributes to sanely determine the condition code
165 ;; state. See cris_notice_update_cc for how this is used.
167 (define_attr "cc" "none,clobber,normal,noov32,rev" (const_string "normal"))
169 ;; At the moment, this attribute is just used to help bb-reorder do its
170 ;; work; the default 0 doesn't help it. Many insns have other lengths,
171 ;; though none are shorter.
172 (define_attr "length" "" (const_int 2))
174 ;; A branch has one delay-slot. The instruction in the
175 ;; delay-slot is always executed, independent of whether the branch is
176 ;; taken or not. Note that besides setting "slottable" to "has_slot",
177 ;; there also has to be a "%#" at the end of a "delayed" instruction
178 ;; output pattern (for "jump" this means "ba %l0%#"), so print_operand can
179 ;; catch it and print a "nop" if necessary. This method was stolen from
182 (define_delay (eq_attr "slottable" "has_slot")
183 [(eq_attr "slottable" "yes") (nil) (nil)])
185 ;; We can't put prologue insns in call-insn delay-slots when
186 ;; DWARF2 unwind info is emitted, because the unwinder matches the
187 ;; address after the insn. It must see the return address of a call at
188 ;; a position at least *one byte after* the insn, or it'll think that
189 ;; the insn hasn't been executed. If the insn is in a delay-slot of a
190 ;; call, it's just *exactly* after the insn.
192 (define_delay (eq_attr "slottable" "has_call_slot")
193 [(and (eq_attr "slottable" "yes")
194 (ior (eq (symbol_ref "RTX_FRAME_RELATED_P (insn)")
196 (eq (symbol_ref "flag_exceptions")
200 ;; The insn in the return insn slot must not be the
201 ;; return-address-register restore. FIXME: Use has_slot and express
202 ;; as a parallel with a use of the return-address-register (currently
203 ;; only SRP). However, this requires an amount of fixing tests for
204 ;; naked RETURN in middle-end.
205 (define_delay (eq_attr "slottable" "has_return_slot")
206 [(and (eq_attr "slottable" "yes")
207 (eq (symbol_ref "dead_or_set_regno_p (insn, CRIS_SRP_REGNUM)")
212 ;; Iterator definitions.
214 ;; For the "usual" pattern size alternatives.
215 (define_mode_iterator BWD [SI HI QI])
216 (define_mode_iterator WD [SI HI])
217 (define_mode_iterator BW [HI QI])
218 (define_mode_attr S [(SI "HI") (HI "QI")])
219 (define_mode_attr s [(SI "hi") (HI "qi")])
220 (define_mode_attr m [(SI ".d") (HI ".w") (QI ".b")])
221 (define_mode_attr mm [(SI ".w") (HI ".b")])
222 (define_mode_attr nbitsm1 [(SI "31") (HI "15") (QI "7")])
224 ;; For the sign_extend+zero_extend variants.
225 (define_code_iterator szext [sign_extend zero_extend])
226 (define_code_attr u [(sign_extend "") (zero_extend "u")])
227 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
229 ;; For the shift variants.
230 (define_code_iterator shift [ashiftrt lshiftrt ashift])
231 (define_code_iterator shiftrt [ashiftrt lshiftrt])
232 (define_code_attr shlr [(ashiftrt "ashr") (lshiftrt "lshr") (ashift "ashl")])
233 (define_code_attr slr [(ashiftrt "asr") (lshiftrt "lsr") (ashift "lsl")])
235 (define_code_iterator ncond [eq ne gtu ltu geu leu])
236 (define_code_iterator ocond [gt le])
237 (define_code_iterator rcond [lt ge])
238 (define_code_attr CC [(eq "eq") (ne "ne") (gt "gt") (gtu "hi") (lt "lt")
239 (ltu "lo") (ge "ge") (geu "hs") (le "le") (leu "ls")])
240 (define_code_attr rCC [(eq "ne") (ne "eq") (gt "le") (gtu "ls") (lt "ge")
241 (ltu "hs") (ge "lt") (geu "lo") (le "gt") (leu "hi")])
242 (define_code_attr oCC [(lt "mi") (ge "pl")])
243 (define_code_attr roCC [(lt "pl") (ge "mi")])
245 ;; Operand and operator predicates.
247 (include "predicates.md")
251 ;; No test insns with side-effect on the mem addressing.
253 ;; See note on cmp-insns with side-effects (or lack of them)
255 ;; Normal named test patterns from SI on.
257 (define_insn "*tstsi"
259 (compare (match_operand:SI 0 "nonimmediate_operand" "r,Q>,m")
263 if (which_alternative == 0 && TARGET_V32)
267 [(set_attr "slottable" "yes,yes,no")])
269 (define_insn "*tst<mode>_cmp"
271 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m")
273 "cris_cc0_user_requires_cmp (insn)"
278 [(set_attr "slottable" "no,yes,no")])
280 (define_insn "*tst<mode>_non_cmp"
282 (compare (match_operand:BW 0 "nonimmediate_operand" "r,Q>,m")
284 "!cris_cc0_user_requires_cmp (insn)"
289 [(set_attr "slottable" "yes,yes,no")
290 (set_attr "cc" "noov32,*,*")])
292 ;; It seems that the position of the sign-bit and the fact that 0.0 is
293 ;; all 0-bits would make "tstsf" a straight-forward implementation;
294 ;; either "test.d" it for positive/negative or "btstq 30,r" it for
297 ;; FIXME: Do that some time; check next_cc0_user to determine if
298 ;; zero or negative is tested for.
302 ;; We could optimize the sizes of the immediate operands for various
303 ;; cases, but that is not worth it because of the very little usage of
304 ;; DImode for anything else but a structure/block-mode. Just do the
305 ;; obvious stuff for the straight-forward constraint letters.
307 (define_insn "*cmpdi_non_v32"
309 (compare (match_operand:DI 0 "nonimmediate_operand" "rm,r,r,r,r,r,r,o")
310 (match_operand:DI 1 "general_operand" "M,Kc,I,P,n,r,o,r")))]
313 test.d %M0\;ax\;test.d %H0
314 cmpq %1,%M0\;ax\;cmpq 0,%H0
315 cmpq %1,%M0\;ax\;cmpq -1,%H0
316 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
317 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
318 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
319 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
320 cmp.d %M0,%M1\;ax\;cmp.d %H0,%H1")
322 (define_insn "*cmpdi_v32"
324 (compare (match_operand:DI 0 "register_operand" "r,r,r,r,r")
325 (match_operand:DI 1 "nonmemory_operand" "Kc,I,P,n,r")))]
328 cmpq %1,%M0\;ax\;cmpq 0,%H0
329 cmpq %1,%M0\;ax\;cmpq -1,%H0
330 cmp%e1.%z1 %1,%M0\;ax\;cmpq %H1,%H0
331 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0
332 cmp.d %M1,%M0\;ax\;cmp.d %H1,%H0")
334 ;; Note that compare insns with side effect addressing mode (e.g.):
336 ;; cmp.S [rx=ry+i],rz;
337 ;; cmp.S [%3=%1+%2],%0
339 ;; are *not* usable for gcc since the reloader *does not accept*
340 ;; cc0-changing insns with side-effects other than setting the condition
341 ;; codes. The reason is that the reload stage *may* cause another insn to
342 ;; be output after the main instruction, in turn invalidating cc0 for the
343 ;; insn using the test. (This does not apply to the CRIS case, since a
344 ;; reload for output -- move to memory -- does not change the condition
345 ;; code. Unfortunately we have no way to describe that at the moment. I
346 ;; think code would improve being in the order of one percent faster.
348 ;; We have cmps and cmpu (compare reg w. sign/zero extended mem).
349 ;; These are mostly useful for compares in SImode, using 8 or 16-bit
350 ;; constants, but sometimes gcc will find its way to use it for other
351 ;; (memory) operands. Avoid side-effect patterns, though (see above).
353 (define_insn "*cmp_ext<mode>"
356 (match_operand:SI 0 "register_operand" "r,r")
357 (match_operator:SI 2 "cris_extend_operator"
358 [(match_operand:BW 1 "memory_operand" "Q>,m")])))]
361 [(set_attr "slottable" "yes,no")])
363 ;; Swap operands; it seems the canonical look (if any) is not enforced.
365 ;; FIXME: Investigate that.
367 (define_insn "*cmp_swapext<mode>"
370 (match_operator:SI 2 "cris_extend_operator"
371 [(match_operand:BW 0 "memory_operand" "Q>,m")])
372 (match_operand:SI 1 "register_operand" "r,r")))]
375 [(set_attr "slottable" "yes,no")
376 (set_attr "cc" "rev")])
378 ;; The "normal" compare patterns, from SI on. Special-cases with zero
379 ;; are covered above.
381 (define_insn "*cmpsi"
384 (match_operand:SI 0 "nonimmediate_operand" "r,r,r, Q>,r,r,m")
385 (match_operand:SI 1 "general_operand" "I,r,Q>,r, P,g,r")))]
395 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")
396 (set_attr "cc" "normal,normal,normal,rev,normal,normal,rev")])
398 (define_insn "*cmp<mode>"
400 (compare (match_operand:BW 0 "nonimmediate_operand" "r,r, Q>,r,m")
401 (match_operand:BW 1 "general_operand" "r,Q>,r, g,r")))]
409 [(set_attr "slottable" "yes,yes,yes,no,no")
410 (set_attr "cc" "normal,normal,rev,normal,rev")])
412 ;; Pattern matching the BTST insn.
413 ;; It is useful for "if (i & val)" constructs, where val is an exact
414 ;; power of 2, or if val + 1 is a power of two, where we check for a bunch
415 ;; of zeros starting at bit 0).
417 ;; SImode. This mode is the only one needed, since gcc automatically
418 ;; extends subregs for lower-size modes. FIXME: Add testcase.
423 (match_operand:SI 0 "nonmemory_operand" "r, r,r, r,r, r,Kp")
424 (match_operand:SI 1 "const_int_operand" "Kc,n,Kc,n,Kc,n,n")
425 (match_operand:SI 2 "nonmemory_operand" "M, M,Kc,n,r, r,r"))
427 ;; Either it is a single bit, or consecutive ones starting at 0.
428 ;; The btst ones depend on stuff in NOTICE_UPDATE_CC.
429 "CONST_INT_P (operands[1])
430 && (operands[1] == const1_rtx || operands[2] == const0_rtx)
431 && (REG_S_P (operands[0])
432 || (operands[1] == const1_rtx
433 && REG_S_P (operands[2])
434 && CONST_INT_P (operands[0])
435 && exact_log2 (INTVAL (operands[0])) >= 0))
438 ;; The next-to-last "&&" condition above should be caught by some kind of
439 ;; canonicalization in gcc, but we can easily help with it here.
440 ;; It results from expressions of the type
441 ;; "power_of_2_value & (1 << y)".
443 ;; Since there may be codes with tests in on bits (in constant position)
444 ;; beyond the size of a word, handle that by assuming those bits are 0.
445 ;; GCC should handle that, but it's a matter of easily-added belts while
446 ;; having suspenders.
456 [(set_attr "slottable" "yes")
457 (set_attr "cc" "noov32")])
461 ;; The whole mandatory movdi family is here; expander, "anonymous"
462 ;; recognizer and splitter. We're forced to have a movdi pattern,
463 ;; although GCC should be able to split it up itself. Normally it can,
464 ;; but if other insns have DI operands (as is the case here), reload
465 ;; must be able to generate or match a movdi. many testcases fail at
466 ;; -O3 or -fssa if we don't have this. FIXME: Fix GCC... See
467 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00104.html>.
468 ;; However, a patch from Richard Kenner (similar to the cause of
469 ;; discussion at the URL above), indicates otherwise. See
470 ;; <URL:http://gcc.gnu.org/ml/gcc-patches/2000-04/msg00554.html>.
471 ;; The truth has IMO is not been decided yet, so check from time to
472 ;; time by disabling the movdi patterns.
474 ;; To appease testcase gcc.c-torture/execute/920501-2.c (and others) at
475 ;; -O0, we need a movdi as a temporary measure. Here's how things fail:
476 ;; A cmpdi RTX needs reloading (global):
477 ;; (insn 185 326 186 (set (cc0)
478 ;; (compare (mem/f:DI (reg/v:SI 22) 0)
479 ;; (const_int 1 [0x1]))) 4 {cmpdi} (nil)
481 ;; Now, reg 22 is reloaded for input address, and the mem is also moved
482 ;; out of the instruction (into a register), since one of the operands
483 ;; must be a register. Reg 22 is reloaded (into reg 10), and the mem is
484 ;; moved out and synthesized in SImode parts (reg 9, reg 10 - should be ok
485 ;; wrt. overlap). The bad things happen with the synthesis in
486 ;; emit_move_insn_1; the location where to substitute reg 10 is lost into
487 ;; two new RTX:es, both still having reg 22. Later on, the left-over reg
488 ;; 22 is recognized to have an equivalent in memory which is substituted
489 ;; straight in, and we end up with an unrecognizable insn:
490 ;; (insn 325 324 326 (set (reg:SI 9 r9)
491 ;; (mem/f:SI (mem:SI (plus:SI (reg:SI 8 r8)
492 ;; (const_int -84 [0xffffffac])) 0) 0)) -1 (nil)
494 ;; which is the first part of the reloaded synthesized "movdi".
495 ;; The right thing would be to add equivalent replacement locations for
496 ;; insn with pseudos that need more reloading. The question is where.
498 (define_expand "movdi"
499 [(set (match_operand:DI 0 "nonimmediate_operand" "")
500 (match_operand:DI 1 "general_operand" ""))]
503 if (MEM_P (operands[0])
504 && operands[1] != const0_rtx
505 && (!TARGET_V32 || (!REG_P (operands[1]) && can_create_pseudo_p ())))
506 operands[1] = copy_to_mode_reg (DImode, operands[1]);
508 /* Some other ports (as of 2001-09-10 for example mcore and romp) also
509 prefer to split up constants early, like this. The testcase in
510 gcc.c-torture/execute/961213-1.c shows that CSE2 gets confused by the
511 resulting subreg sets when using the construct from mcore (as of FSF
512 CVS, version -r 1.5), and it believes that the high part (the last one
513 emitted) is the final value. */
514 if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
515 && ! reload_completed
516 && ! reload_in_progress)
519 rtx op0 = operands[0];
520 rtx op1 = operands[1];
523 emit_move_insn (operand_subword (op0, 0, 1, DImode),
524 operand_subword (op1, 0, 1, DImode));
525 emit_move_insn (operand_subword (op0, 1, 1, DImode),
526 operand_subword (op1, 1, 1, DImode));
527 insns = get_insns ();
535 (define_insn_and_split "*movdi_insn_non_v32"
536 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rx,m")
537 (match_operand:DI 1 "general_operand" "rx,g,rxM"))]
538 "(register_operand (operands[0], DImode)
539 || register_operand (operands[1], DImode)
540 || operands[1] == const0_rtx)
543 "&& reload_completed"
545 "operands[2] = cris_split_movdx (operands);")
547 ;; Overlapping (but non-identical) source memory address and destination
548 ;; register would be a compiler bug, so we don't have to specify that.
549 (define_insn "*movdi_v32"
551 (match_operand:DI 0 "nonimmediate_operand" "=r,rx,&r,>, m,r,x,m")
552 (match_operand:DI 1 "general_operand" "rxi,r>,m, rx,r,m,m,x"))]
555 switch (which_alternative)
557 /* FIXME: 1) Use autoincrement where possible. 2) Have peephole2,
558 particularly for cases where the address register is dead. */
560 if (REGNO (operands[0]) == REGNO (XEXP (operands[1], 0)))
561 return "addq 4,%L1\;move.d %1,%H0\;subq 4,%L1\;move.d %1,%M0";
562 gcc_assert (REGNO (operands[0]) + 1 == REGNO (XEXP (operands[1], 0)));
563 return "move.d [%L1+],%M0\;move.d [%L1],%H0";
565 /* We could do away with the addq if we knew the address-register
566 isn't ACR. If we knew the address-register is dead, we could do
567 away with the subq too. */
568 return "move.d [%L1],%M0\;addq 4,%L1\;move.d [%L1],%H0\;subq 4,%L1";
570 return "move.d %M1,[%L0]\;addq 4,%L0\;move.d %H1,[%L0]\;subq 4,%L0";
572 return "move [%L1],%M0\;addq 4,%L1\;move [%L1],%H0\;subq 4,%L1";
574 return "move %M1,[%L0]\;addq 4,%L0\;move %H1,[%L0]\;subq 4,%L0";
580 ;; The non-split cases clobber cc0 because of their adds and subs.
581 ;; Beware that NOTICE_UPDATE_CC is called before the forced split happens.
582 [(set_attr "cc" "*,*,clobber,*,clobber,clobber,*,*")])
584 ;; Much like "*movdi_insn_non_v32". Overlapping registers and constants
585 ;; is handled so much better in cris_split_movdx.
587 [(set (match_operand:DI 0 "nonimmediate_operand" "")
588 (match_operand:DI 1 "general_operand" ""))]
591 && (!MEM_P (operands[0]) || !REG_P (XEXP (operands[0], 0)))
592 && (!MEM_P (operands[1]) || !REG_P (XEXP (operands[1], 0)))"
594 "operands[2] = cris_split_movdx (operands);")
596 ;; Side-effect patterns for move.S1 [rx=ry+rx.S2],rw
597 ;; and move.S1 [rx=ry+i],rz
598 ;; Then movs.S1 and movu.S1 for both modes.
600 ;; move.S1 [rx=ry+rz.S],rw avoiding when rx is ry, or rw is rx
601 ;; FIXME: These could have anonymous mode for operand 0.
602 ;; FIXME: Special registers' alternatives too.
604 (define_insn "*mov_side<mode>_biap"
605 [(set (match_operand:BW 0 "register_operand" "=r,r")
607 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
608 (match_operand:SI 2 "const_int_operand" "n,n"))
609 (match_operand:SI 3 "register_operand" "r,r"))))
610 (set (match_operand:SI 4 "register_operand" "=*3,r")
611 (plus:SI (mult:SI (match_dup 1)
614 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
617 move<m> [%4=%3+%1%T2],%0")
619 (define_insn "*mov_sidesisf_biap"
620 [(set (match_operand 0 "register_operand" "=r,r,x,x")
622 (mult:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
623 (match_operand:SI 2 "const_int_operand" "n,n,n,n"))
624 (match_operand:SI 3 "register_operand" "r,r,r,r"))))
625 (set (match_operand:SI 4 "register_operand" "=*3,r,*3,r")
626 (plus:SI (mult:SI (match_dup 1)
629 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
630 && cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
633 move.%s0 [%4=%3+%1%T2],%0
635 move [%4=%3+%1%T2],%0")
637 ;; move.S1 [rx=ry+i],rz
638 ;; avoiding move.S1 [ry=ry+i],rz
639 ;; and move.S1 [rz=ry+i],rz
640 ;; Note that "i" is allowed to be a register.
642 (define_insn "*mov_side<mode>"
643 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
645 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
646 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r"))))
647 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
648 (plus:SI (match_dup 1)
650 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
652 if ((which_alternative == 0 || which_alternative == 3)
653 && (!CONST_INT_P (operands[2])
654 || INTVAL (operands[2]) > 127
655 || INTVAL (operands[2]) < -128
656 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
657 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
659 if (which_alternative == 4)
660 return "move<m> [%3=%2%S1],%0";
661 return "move<m> [%3=%1%S2],%0";
664 (define_insn "*mov_sidesisf"
665 [(set (match_operand 0 "register_operand" "=r,r,r,x,x,x,r,r,x,x")
668 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,r,r,r,R,R,R,R")
669 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r>Rn,r,>Rn,r,r,r,r"))))
670 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*1,r,r,*2,r,*2,r")
671 (plus:SI (match_dup 1)
673 "GET_MODE_SIZE (GET_MODE (operands[0])) == UNITS_PER_WORD
674 && cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
676 if ((which_alternative == 0
677 || which_alternative == 3
678 || which_alternative == 6
679 || which_alternative == 8)
680 && (!CONST_INT_P (operands[2])
681 || INTVAL (operands[2]) > 127
682 || INTVAL (operands[2]) < -128
683 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
684 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
686 if (which_alternative < 3)
687 return "move.%s0 [%3=%1%S2],%0";
688 if (which_alternative == 7)
689 return "move.%s0 [%3=%2%S1],%0";
690 if (which_alternative == 9)
691 return "move [%3=%2%S1],%0";
692 return "move [%3=%1%S2],%0";
695 ;; Other way around; move to memory.
697 ;; Note that the condition (which for side-effect patterns is usually a
698 ;; call to cris_side_effect_mode_ok), isn't consulted for register
699 ;; allocation preferences -- constraints is the method for that. The
700 ;; drawback is that we can't exclude register allocation to cause
701 ;; "move.s rw,[rx=ry+rz.S]" when rw==rx without also excluding rx==ry or
702 ;; rx==rz if we use an earlyclobber modifier for the constraint for rx.
703 ;; Instead of that, we recognize and split the cases where dangerous
704 ;; register combinations are spotted: where a register is set in the
705 ;; side-effect, and used in the main insn. We don't handle the case where
706 ;; the set in the main insn overlaps the set in the side-effect; that case
707 ;; must be handled in gcc. We handle just the case where the set in the
708 ;; side-effect overlaps the input operand of the main insn (i.e. just
712 ;; move.s rz,[ry=rx+rw.S]
714 (define_insn "*mov_side<mode>_biap_mem"
715 [(set (mem:BW (plus:SI
716 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r")
717 (match_operand:SI 1 "const_int_operand" "n,n,n"))
718 (match_operand:SI 2 "register_operand" "r,r,r")))
719 (match_operand:BW 3 "register_operand" "r,r,r"))
720 (set (match_operand:SI 4 "register_operand" "=*2,!3,r")
721 (plus:SI (mult:SI (match_dup 0)
724 "cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
728 move<m> %3,[%4=%2+%0%T1]")
730 (define_insn "*mov_sidesisf_biap_mem"
732 (mult:SI (match_operand:SI 0 "register_operand" "r,r,r,r,r,r")
733 (match_operand:SI 1 "const_int_operand" "n,n,n,n,n,n"))
734 (match_operand:SI 2 "register_operand" "r,r,r,r,r,r")))
735 (match_operand 3 "register_operand" "r,r,r,x,x,x"))
736 (set (match_operand:SI 4 "register_operand" "=*2,!3,r,*2,!3,r")
737 (plus:SI (mult:SI (match_dup 0)
740 "GET_MODE_SIZE (GET_MODE (operands[3])) == UNITS_PER_WORD
741 && cris_side_effect_mode_ok (MULT, operands, 4, 2, 0, 1, 3)"
745 move.%s3 %3,[%4=%2+%0%T1]
748 move %3,[%4=%2+%0%T1]")
750 ;; Split for the case above where we're out of luck with register
751 ;; allocation (again, the condition isn't checked for that), and we end up
752 ;; with the set in the side-effect getting the same register as the input
757 [(set (match_operator
760 (mult:SI (match_operand:SI 0 "register_operand" "")
761 (match_operand:SI 1 "const_int_operand" ""))
762 (match_operand:SI 2 "register_operand" ""))])
763 (match_operand 3 "register_operand" ""))
764 (set (match_operand:SI 4 "register_operand" "")
765 (plus:SI (mult:SI (match_dup 0)
768 "reload_completed && reg_overlap_mentioned_p (operands[4], operands[3])"
769 [(set (match_dup 5) (match_dup 3))
770 (set (match_dup 4) (match_dup 2))
772 (plus:SI (mult:SI (match_dup 0)
776 = replace_equiv_address (operands[6],
777 gen_rtx_PLUS (SImode,
778 gen_rtx_MULT (SImode,
783 ;; move.s rx,[ry=rz+i]
784 ;; FIXME: These could have anonymous mode for operand 2.
788 (define_insn "*mov_side<mode>_mem"
790 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,r,R,R,R")
791 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r>Rn,r,>Rn,r,r,r")))
792 (match_operand:BW 2 "register_operand" "r,r,r,r,r,r,r"))
793 (set (match_operand:SI 3 "register_operand" "=*0,!*2,r,r,*1,!*2,r")
794 (plus:SI (match_dup 0)
796 "cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
798 if ((which_alternative == 0 || which_alternative == 4)
799 && (!CONST_INT_P (operands[1])
800 || INTVAL (operands[1]) > 127
801 || INTVAL (operands[1]) < -128
802 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
803 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
805 if (which_alternative == 1 || which_alternative == 5)
807 if (which_alternative == 6)
808 return "move.%s2 %2,[%3=%1%S0]";
809 return "move<m> %2,[%3=%0%S1]";
814 (define_insn "*mov_sidesisf_mem"
818 0 "cris_bdap_operand"
819 "%r, r, r,r, r, r,r, R,R, R,R, R")
821 1 "cris_bdap_operand"
822 "r>Rn,r>Rn,r,>Rn,r>Rn,r,>Rn,r,r, r,r, r")))
823 (match_operand 2 "register_operand"
824 "r, r, r,r, x, x,x, r,r, r,x, x"))
825 (set (match_operand:SI 3 "register_operand"
826 "=*0,!2, r,r, *0, r,r, *1,!*2,r,*1,r")
827 (plus:SI (match_dup 0)
829 "GET_MODE_SIZE (GET_MODE (operands[2])) == UNITS_PER_WORD
830 && cris_side_effect_mode_ok (PLUS, operands, 3, 0, 1, -1, 2)"
832 if ((which_alternative == 0 || which_alternative == 4)
833 && (!CONST_INT_P (operands[1])
834 || INTVAL (operands[1]) > 127
835 || INTVAL (operands[1]) < -128
836 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
837 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
839 if (which_alternative == 1
840 || which_alternative == 7
841 || which_alternative == 8
842 || which_alternative == 10)
844 if (which_alternative < 4)
845 return "move.%s2 %2,[%3=%0%S1]";
846 if (which_alternative == 9)
847 return "move.%s2 %2,[%3=%1%S0]";
848 if (which_alternative == 11)
849 return "move %2,[%3=%1%S0]";
850 return "move %2,[%3=%0%S1]";
853 ;; Like the biap case, a split where the set in the side-effect gets the
854 ;; same register as the input register to the main insn, since the
855 ;; condition isn't checked at register allocation.
859 [(set (match_operator
862 (match_operand:SI 0 "cris_bdap_operand" "")
863 (match_operand:SI 1 "cris_bdap_operand" ""))])
864 (match_operand 2 "register_operand" ""))
865 (set (match_operand:SI 3 "register_operand" "")
866 (plus:SI (match_dup 0) (match_dup 1)))])]
867 "reload_completed && reg_overlap_mentioned_p (operands[3], operands[2])"
868 [(set (match_dup 4) (match_dup 2))
869 (set (match_dup 3) (match_dup 0))
870 (set (match_dup 3) (plus:SI (match_dup 3) (match_dup 1)))]
873 ;; Clear memory side-effect patterns. It is hard to get to the mode if
874 ;; the MEM was anonymous, so there will be one for each mode.
876 ;; clear.[bwd] [ry=rx+rw.s2]
878 (define_insn "*clear_side<mode>_biap"
879 [(set (mem:BWD (plus:SI
880 (mult:SI (match_operand:SI 0 "register_operand" "r,r")
881 (match_operand:SI 1 "const_int_operand" "n,n"))
882 (match_operand:SI 2 "register_operand" "r,r")))
884 (set (match_operand:SI 3 "register_operand" "=*2,r")
885 (plus:SI (mult:SI (match_dup 0)
888 "cris_side_effect_mode_ok (MULT, operands, 3, 2, 0, 1, -1)"
891 clear<m> [%3=%2+%0%T1]")
893 ;; clear.[bwd] [ry=rz+i]
895 (define_insn "*clear_side<mode>"
897 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r,r,r,R,R")
898 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
900 (set (match_operand:SI 2 "register_operand" "=*0,r,r,*1,r")
901 (plus:SI (match_dup 0)
903 "cris_side_effect_mode_ok (PLUS, operands, 2, 0, 1, -1, -1)"
905 if ((which_alternative == 0 || which_alternative == 3)
906 && (!CONST_INT_P (operands[1])
907 || INTVAL (operands[1]) > 127
908 || INTVAL (operands[1]) < -128
909 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'N')
910 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'J')))
912 if (which_alternative == 4)
913 return "clear<m> [%2=%1%S0]";
914 return "clear<m> [%2=%0%S1]";
917 ;; Normal move patterns from SI on.
919 (define_expand "movsi"
921 (match_operand:SI 0 "nonimmediate_operand" "")
922 (match_operand:SI 1 "cris_general_operand_or_symbol" ""))]
925 /* If the output goes to a MEM, make sure we have zero or a register as
927 if (MEM_P (operands[0])
928 && ! REG_S_P (operands[1])
929 && operands[1] != const0_rtx
930 && can_create_pseudo_p ())
931 operands[1] = force_reg (SImode, operands[1]);
933 /* If we're generating PIC and have an incoming symbol, validize it to a
934 general operand or something that will match a special pattern.
936 FIXME: Do we *have* to recognize anything that would normally be a
937 valid symbol? Can we exclude global PIC addresses with an added
940 && CONSTANT_ADDRESS_P (operands[1])
941 && !cris_valid_pic_const (operands[1], false))
943 enum cris_pic_symbol_type t = cris_pic_symbol_type_of (operands[1]);
945 gcc_assert (t != cris_no_symbol);
947 if (! REG_S_P (operands[0]))
949 /* We must have a register as destination for what we're about to
950 do, and for the patterns we generate. */
951 CRIS_ASSERT (can_create_pseudo_p ());
952 operands[1] = force_reg (SImode, operands[1]);
956 /* FIXME: add a REG_EQUAL (or is it REG_EQUIV) note to the
957 destination register for the symbol. It might not be
958 worth it. Measure. */
959 crtl->uses_pic_offset_table = 1;
960 if (t == cris_rel_symbol)
962 /* Change a "move.d sym(+offs),rN" into (allocate register rM)
964 "move.d (const (plus (unspec [sym]
965 CRIS_UNSPEC_GOTREL) offs)),rM" "add.d rPIC,rM,rN"
967 "move.d (const (plus (unspec [sym]
968 CRIS_UNSPEC_PCREL) offs)),rN". */
969 rtx tem, rm, rn = operands[0];
970 rtx sym = GET_CODE (operands[1]) != CONST
971 ? operands[1] : get_related_value (operands[1]);
972 HOST_WIDE_INT offs = get_integer_term (operands[1]);
974 gcc_assert (can_create_pseudo_p ());
978 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
981 tem = plus_constant (tem, offs);
983 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
987 /* We still uses GOT-relative addressing for
989 crtl->uses_pic_offset_table = 1;
990 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym),
993 tem = plus_constant (tem, offs);
994 rm = gen_reg_rtx (Pmode);
995 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
996 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
997 rn, 0, OPTAB_LIB_WIDEN) != rn)
998 internal_error ("expand_binop failed in movsi gotrel");
1002 else if (t == cris_got_symbol)
1004 /* Change a "move.d sym,rN" into (allocate register rM, rO)
1005 "move.d (const (unspec [sym] CRIS_UNSPEC_GOTREAD)),rM"
1006 "add.d rPIC,rM,rO", "move.d [rO],rN" with
1007 the memory access marked as read-only. */
1008 rtx tem, mem, rm, ro, rn = operands[0];
1009 gcc_assert (can_create_pseudo_p ());
1010 tem = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
1011 CRIS_UNSPEC_GOTREAD);
1012 rm = gen_reg_rtx (Pmode);
1013 emit_move_insn (rm, gen_rtx_CONST (Pmode, tem));
1014 ro = gen_reg_rtx (Pmode);
1015 if (expand_binop (Pmode, add_optab, rm, pic_offset_table_rtx,
1016 ro, 0, OPTAB_LIB_WIDEN) != ro)
1017 internal_error ("expand_binop failed in movsi got");
1018 mem = gen_rtx_MEM (Pmode, ro);
1020 /* This MEM doesn't alias anything. Whether it
1021 aliases other same symbols is unimportant. */
1022 set_mem_alias_set (mem, new_alias_set ());
1023 MEM_NOTRAP_P (mem) = 1;
1025 /* We can set the GOT memory read of a non-called symbol
1026 to readonly, but not that of a call symbol, as those
1027 are subject to lazy evaluation and usually have the value
1028 changed from the first call to the second (but
1029 constant thereafter). */
1030 MEM_READONLY_P (mem) = 1;
1031 emit_move_insn (rn, mem);
1036 /* We get here when we have to change something that would
1037 be recognizable if it wasn't PIC. A ``sym'' is ok for
1038 PIC symbols both with and without a GOT entry. And ``sym
1039 + offset'' is ok for local symbols, so the only thing it
1040 could be, is a global symbol with an offset. Check and
1042 rtx reg = gen_reg_rtx (Pmode);
1043 rtx sym = get_related_value (operands[1]);
1044 HOST_WIDE_INT offs = get_integer_term (operands[1]);
1046 gcc_assert (can_create_pseudo_p ()
1047 && t == cris_got_symbol_needing_fixup
1048 && sym != NULL_RTX && offs != 0);
1050 emit_move_insn (reg, sym);
1051 if (expand_binop (SImode, add_optab, reg,
1052 GEN_INT (offs), operands[0], 0,
1053 OPTAB_LIB_WIDEN) != operands[0])
1054 internal_error ("expand_binop failed in movsi got+offs");
1061 (define_insn "*movsi_got_load"
1062 [(set (reg:SI CRIS_GOT_REGNUM) (unspec:SI [(const_int 0)] CRIS_UNSPEC_GOT))]
1066 ? "lapc _GLOBAL_OFFSET_TABLE_,%:"
1067 : "move.d $pc,%:\;sub.d .:GOTOFF,%:";
1069 [(set_attr "cc" "clobber")])
1071 (define_insn "*movsi_internal"
1073 (match_operand:SI 0 "nonimmediate_operand"
1074 "=r,r, r,Q>,r,Q>,g,r,r, r,g,rQ>,x, m,x")
1075 (match_operand:SI 1 "cris_general_operand_or_pic_source"
1076 "r,Q>,M,M, I,r, M,n,!S,g,r,x, rQ>,x,gi"))]
1077 ;; Note that we prefer not to use the S alternative (if for some reason
1078 ;; it competes with others) above, but g matches S.
1081 /* Better to have c-switch here; it is worth it to optimize the size of
1082 move insns. The alternative would be to try to find more constraint
1083 letters. FIXME: Check again. It seems this could shrink a bit. */
1084 switch (which_alternative)
1090 && (GET_CODE (operands[1]) == SYMBOL_REF
1091 || GET_CODE (operands[1]) == LABEL_REF
1092 || GET_CODE (operands[1]) == CONST))
1094 /* FIXME: Express this through (set_attr cc none) instead,
1095 since we can't express the ``none'' at this point. FIXME:
1096 Use lapc for everything except const_int and when next cc0
1097 user would want the flag setting. */
1099 return "lapc %1,%0";
1102 && GET_CODE (operands[1]) == CONST
1103 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
1104 && XINT (XEXP (operands[1], 0), 1) == CRIS_UNSPEC_GOTREAD)
1105 return "movu.w %1,%0";
1112 return "move.d %1,%0";
1118 return "move %d1,%0";
1123 return "clear.d %0";
1125 /* Constants -32..31 except 0. */
1127 return "moveq %1,%0";
1129 /* We can win a little on constants -32768..-33, 32..65535. */
1131 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) < 65536)
1133 if (INTVAL (operands[1]) < 256)
1134 return "movu.b %1,%0";
1135 return "movu.w %1,%0";
1137 else if (INTVAL (operands[1]) >= -32768 && INTVAL (operands[1]) < 32768)
1139 if (INTVAL (operands[1]) >= -128 && INTVAL (operands[1]) < 128)
1140 return "movs.b %1,%0";
1141 return "movs.w %1,%0";
1143 return "move.d %1,%0";
1147 rtx tem = operands[1];
1148 gcc_assert (GET_CODE (tem) == CONST);
1149 tem = XEXP (tem, 0);
1150 if (GET_CODE (tem) == PLUS
1151 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1152 && (XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1153 || XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_PCREL)
1154 && CONST_INT_P (XEXP (tem, 1)))
1155 tem = XEXP (tem, 0);
1156 gcc_assert (GET_CODE (tem) == UNSPEC);
1157 switch (XINT (tem, 1))
1159 case CRIS_UNSPEC_GOTREAD:
1160 case CRIS_UNSPEC_PLTGOTREAD:
1161 /* Using sign-extend mostly to be consistent with the
1162 indexed addressing mode. */
1164 return "movs.w %1,%0";
1165 return "move.d %1,%0";
1167 case CRIS_UNSPEC_GOTREL:
1168 case CRIS_UNSPEC_PLT_GOTREL:
1169 gcc_assert (!TARGET_V32);
1170 return "move.d %1,%0";
1172 case CRIS_UNSPEC_PCREL:
1173 case CRIS_UNSPEC_PLT_PCREL:
1174 gcc_assert (TARGET_V32);
1175 return "lapc %1,%0";
1182 return "BOGUS: %1 to %0";
1185 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,no,no,no,yes,yes,no,no")
1186 (set_attr "cc" "*,*,*,*,*,*,*,*,*,*,*,none,none,none,none")])
1188 ;; Extend operations with side-effect from mem to register, using
1189 ;; MOVS/MOVU. These are from mem to register only.
1195 ;; FIXME: Can we omit extend to HImode, since GCC should truncate for
1196 ;; HImode by itself? Perhaps use only anonymous modes?
1198 (define_insn "*ext_sideqihi_biap"
1199 [(set (match_operand:HI 0 "register_operand" "=r,r")
1201 5 "cris_extend_operator"
1203 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1204 (match_operand:SI 2 "const_int_operand" "n,n"))
1205 (match_operand:SI 3 "register_operand" "r,r")))]))
1206 (set (match_operand:SI 4 "register_operand" "=*3,r")
1207 (plus:SI (mult:SI (match_dup 1)
1210 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1213 mov%e5.%m5 [%4=%3+%1%T2],%0")
1215 (define_insn "*ext_side<mode>si_biap"
1216 [(set (match_operand:SI 0 "register_operand" "=r,r")
1218 5 "cris_extend_operator"
1220 (mult:SI (match_operand:SI 1 "register_operand" "r,r")
1221 (match_operand:SI 2 "const_int_operand" "n,n"))
1222 (match_operand:SI 3 "register_operand" "r,r")))]))
1223 (set (match_operand:SI 4 "register_operand" "=*3,r")
1224 (plus:SI (mult:SI (match_dup 1)
1227 "cris_side_effect_mode_ok (MULT, operands, 4, 3, 1, 2, 0)"
1230 mov%e5<m> [%4=%3+%1%T2],%0")
1232 ;; Same but [rx=ry+i]
1236 (define_insn "*ext_sideqihi"
1237 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
1239 4 "cris_extend_operator"
1241 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1242 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1243 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1244 (plus:SI (match_dup 1)
1246 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1248 if ((which_alternative == 0 || which_alternative == 3)
1249 && (!CONST_INT_P (operands[2])
1250 || INTVAL (operands[2]) > 127
1251 || INTVAL (operands[2]) < -128
1252 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1253 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1255 if (which_alternative == 4)
1256 return "mov%e4.%m4 [%3=%2%S1],%0";
1257 return "mov%e4.%m4 [%3=%1%S2],%0";
1260 (define_insn "*ext_side<mode>si"
1261 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
1263 4 "cris_extend_operator"
1265 (match_operand:SI 1 "cris_bdap_operand" "%r,r,r,R,R")
1266 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1267 (set (match_operand:SI 3 "register_operand" "=*1,r,r,*2,r")
1268 (plus:SI (match_dup 1)
1270 "cris_side_effect_mode_ok (PLUS, operands, 3, 1, 2, -1, 0)"
1272 if ((which_alternative == 0 || which_alternative == 3)
1273 && (!CONST_INT_P (operands[2])
1274 || INTVAL (operands[2]) > 127
1275 || INTVAL (operands[2]) < -128
1276 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
1277 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
1279 if (which_alternative == 4)
1280 return "mov%e4<m> [%3=%2%S1],%0";
1281 return "mov%e4<m> [%3=%1%S2],%0";
1284 ;; FIXME: See movsi.
1286 (define_insn "movhi"
1288 (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r,r,x")
1289 (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g,x,r"))]
1292 switch (which_alternative)
1299 return "move.w %1,%0";
1302 return "move %1,%0";
1306 return "clear.w %0";
1308 return "moveq %1,%0";
1311 if (INTVAL (operands[1]) < 256 && INTVAL (operands[1]) >= -128)
1313 if (INTVAL (operands[1]) > 0)
1314 return "movu.b %1,%0";
1315 return "movs.b %1,%0";
1317 return "move.w %1,%0";
1319 return "movEq %b1,%0";
1321 return "BOGUS: %1 to %0";
1324 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,yes,no,no,no,no,yes,yes")
1325 (set_attr "cc" "*,*,none,none,*,none,*,clobber,*,none,none,*,none,none")])
1327 (define_insn "movstricthi"
1330 (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
1331 (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
1342 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1344 (define_expand "reload_in<mode>"
1345 [(set (match_operand:BW 2 "register_operand" "=r")
1346 (match_operand:BW 1 "memory_operand" "m"))
1347 (set (match_operand:BW 0 "register_operand" "=x")
1352 (define_expand "reload_out<mode>"
1353 [(set (match_operand:BW 2 "register_operand" "=&r")
1354 (match_operand:BW 1 "register_operand" "x"))
1355 (set (match_operand:BW 0 "memory_operand" "=m")
1360 (define_insn "movqi"
1361 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r,r,x")
1362 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g,x,r"))]
1377 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,no,no,yes,no,yes,yes")
1378 (set_attr "cc" "*,*,*,*,*,*,*,*,clobber,*,none,none")])
1380 (define_insn "movstrictqi"
1381 [(set (strict_low_part
1382 (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
1383 (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
1394 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
1396 ;; The valid "quick" bit-patterns are, except for 0.0, denormalized
1397 ;; values REALLY close to 0, and some NaN:s (I think; their exponent is
1398 ;; all ones); the worthwhile one is "0.0".
1399 ;; It will use clear, so we know ALL types of immediate 0 never change cc.
1401 (define_insn "movsf"
1402 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r,r,x,Q>,m,x, x")
1403 (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g,x,r,x, x,Q>,g"))]
1420 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no,yes,yes,yes,no,yes,no")])
1422 ;; Movem patterns. Primarily for use in function prologue and epilogue.
1423 ;; The V32 variants have an ordering matching the expectations of the
1424 ;; standard names "load_multiple" and "store_multiple"; pre-v32 movem
1425 ;; store R0 in the highest memory location.
1427 (define_expand "load_multiple"
1428 [(match_operand:SI 0 "register_operand" "")
1429 (match_operand:SI 1 "memory_operand" "")
1430 (match_operand:SI 2 "const_int_operand" "")]
1435 /* Apparently the predicate isn't checked, so we need to do so
1436 manually. Once happened for libstdc++-v3 locale_facets.tcc. */
1437 if (!MEM_P (operands[1]))
1440 indreg = XEXP (operands[1], 0);
1442 if (GET_CODE (indreg) == POST_INC)
1443 indreg = XEXP (indreg, 0);
1445 || GET_CODE (operands[2]) != CONST_INT
1446 || !REG_P (operands[0])
1447 || REGNO (operands[0]) != 0
1448 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1449 || (int) REGNO (indreg) < INTVAL (operands[2]))
1452 emit_insn (cris_gen_movem_load (operands[1], operands[2], 0));
1456 (define_expand "store_multiple"
1457 [(match_operand:SI 0 "memory_operand" "")
1458 (match_operand:SI 1 "register_operand" "")
1459 (match_operand:SI 2 "const_int_operand" "")]
1464 /* See load_multiple. */
1465 if (!MEM_P (operands[0]))
1468 indreg = XEXP (operands[0], 0);
1470 if (GET_CODE (indreg) == POST_INC)
1471 indreg = XEXP (indreg, 0);
1473 || GET_CODE (operands[2]) != CONST_INT
1474 || !REG_P (operands[1])
1475 || REGNO (operands[1]) != 0
1476 || INTVAL (operands[2]) > CRIS_SP_REGNUM
1477 || (int) REGNO (indreg) < INTVAL (operands[2]))
1480 cris_emit_movem_store (operands[0], operands[2], 0, false);
1484 (define_insn "*cris_load_multiple"
1485 [(match_parallel 0 "cris_load_multiple_op"
1486 [(set (match_operand:SI 1 "register_operand" "=r,r")
1487 (match_operand:SI 2 "memory_operand" "Q,m"))])]
1490 [(set_attr "cc" "none")
1491 (set_attr "slottable" "yes,no")
1492 ;; Not true, but setting the length to 0 causes return sequences (ret
1493 ;; movem) to have the cost they had when (return) included the movem
1494 ;; and reduces the performance penalty taken for needing to emit an
1495 ;; epilogue (in turn copied by bb-reorder) instead of return patterns.
1496 ;; FIXME: temporary change until all insn lengths are correctly
1497 ;; described. FIXME: have better target control over bb-reorder.
1498 (set_attr "length" "0")])
1500 (define_insn "*cris_store_multiple"
1501 [(match_parallel 0 "cris_store_multiple_op"
1502 [(set (match_operand:SI 2 "memory_operand" "=Q,m")
1503 (match_operand:SI 1 "register_operand" "r,r"))])]
1506 [(set_attr "cc" "none")
1507 (set_attr "slottable" "yes,no")])
1510 ;; Sign- and zero-extend insns with standard names.
1511 ;; Those for integer source operand are ordered with the widest source
1516 (define_insn "extendsidi2"
1517 [(set (match_operand:DI 0 "register_operand" "=r")
1518 (sign_extend:DI (match_operand:SI 1 "general_operand" "g")))]
1520 "move.d %1,%M0\;smi %H0\;neg.d %H0,%H0")
1522 (define_insn "extend<mode>di2"
1523 [(set (match_operand:DI 0 "register_operand" "=r")
1524 (sign_extend:DI (match_operand:BW 1 "general_operand" "g")))]
1526 "movs<m> %1,%M0\;smi %H0\;neg.d %H0,%H0")
1528 (define_insn "extend<mode>si2"
1529 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1530 (sign_extend:SI (match_operand:BW 1 "general_operand" "r,Q>,g")))]
1533 [(set_attr "slottable" "yes,yes,no")])
1535 ;; To do a byte->word extension, extend to dword, exept that the top half
1536 ;; of the register will be clobbered. FIXME: Perhaps this is not needed.
1538 (define_insn "extendqihi2"
1539 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1540 (sign_extend:HI (match_operand:QI 1 "general_operand" "r,Q>,g")))]
1543 [(set_attr "slottable" "yes,yes,no")])
1546 ;; Zero-extend. The DImode ones are synthesized by gcc, so we don't
1547 ;; specify them here.
1549 (define_insn "zero_extend<mode>si2"
1550 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1552 (match_operand:BW 1 "nonimmediate_operand" "r,Q>,m")))]
1555 [(set_attr "slottable" "yes,yes,no")])
1557 ;; Same comment as sign-extend QImode to HImode above applies.
1559 (define_insn "zero_extendqihi2"
1560 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
1562 (match_operand:QI 1 "nonimmediate_operand" "r,Q>,m")))]
1565 [(set_attr "slottable" "yes,yes,no")])
1567 ;; All kinds of arithmetic and logical instructions.
1569 ;; First, anonymous patterns to match addressing modes with
1572 ;; op.S [rx=ry+I],rz; (add, sub, or, and, bound).
1576 (define_insn "*op_side<mode>_biap"
1577 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1579 6 "cris_orthogonal_operator"
1580 [(match_operand:BWD 1 "register_operand" "0,0")
1582 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1583 (match_operand:SI 3 "const_int_operand" "n,n"))
1584 (match_operand:SI 4 "register_operand" "r,r")))]))
1585 (set (match_operand:SI 5 "register_operand" "=*4,r")
1586 (plus:SI (mult:SI (match_dup 2)
1589 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1592 %x6<m> [%5=%4+%2%T3],%0")
1594 ;; [rx=ry+i] ([%4=%2+%3])
1596 (define_insn "*op_side<mode>"
1597 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1599 5 "cris_orthogonal_operator"
1600 [(match_operand:BWD 1 "register_operand" "0,0,0,0,0")
1602 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1603 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))]))
1604 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1605 (plus:SI (match_dup 2)
1607 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1609 if ((which_alternative == 0 || which_alternative == 3)
1610 && (!CONST_INT_P (operands[3])
1611 || INTVAL (operands[3]) > 127
1612 || INTVAL (operands[3]) < -128
1613 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1614 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1616 if (which_alternative == 4)
1617 return "%x5.%s0 [%4=%3%S2],%0";
1618 return "%x5<m> [%4=%2%S3],%0";
1621 ;; To match all cases for commutative operations we may have to have the
1622 ;; following pattern for add, or & and. I do not know really, but it does
1623 ;; not break anything.
1625 ;; FIXME: This really ought to be checked.
1627 ;; op.S [rx=ry+I],rz;
1631 (define_insn "*op_swap_side<mode>_biap"
1632 [(set (match_operand:BWD 0 "register_operand" "=r,r")
1634 6 "cris_commutative_orth_op"
1636 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
1637 (match_operand:SI 3 "const_int_operand" "n,n"))
1638 (match_operand:SI 4 "register_operand" "r,r")))
1639 (match_operand:BWD 1 "register_operand" "0,0")]))
1640 (set (match_operand:SI 5 "register_operand" "=*4,r")
1641 (plus:SI (mult:SI (match_dup 2)
1644 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
1647 %x6<m> [%5=%4+%2%T3],%0")
1649 ;; [rx=ry+i] ([%4=%2+%3])
1650 ;; FIXME: These could have anonymous mode for operand 0.
1654 (define_insn "*op_swap_side<mode>"
1655 [(set (match_operand:BWD 0 "register_operand" "=r,r,r,r,r")
1657 5 "cris_commutative_orth_op"
1659 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
1660 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))
1661 (match_operand:BWD 1 "register_operand" "0,0,0,0,0")]))
1662 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
1663 (plus:SI (match_dup 2)
1665 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
1667 if ((which_alternative == 0 || which_alternative == 3)
1668 && (!CONST_INT_P (operands[3])
1669 || INTVAL (operands[3]) > 127
1670 || INTVAL (operands[3]) < -128
1671 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
1672 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
1674 if (which_alternative == 4)
1675 return "%x5<m> [%4=%3%S2],%0";
1676 return "%x5<m> [%4=%2%S3],%0";
1679 ;; Add operations, standard names.
1681 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1682 ;; output the insn through the 'A' output modifier as "adds.w" and "addq",
1684 (define_expand "adddi3"
1685 [(set (match_operand:DI 0 "register_operand")
1686 (plus:DI (match_operand:DI 1 "register_operand")
1687 (match_operand:DI 2 "general_operand")))]
1690 if (MEM_P (operands[2]) && TARGET_V32)
1691 operands[2] = force_reg (DImode, operands[2]);
1694 (define_insn "*adddi3_non_v32"
1695 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1696 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,r")
1697 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1700 addq %2,%M0\;ax\;addq 0,%H0
1701 subq %n2,%M0\;ax\;subq 0,%H0
1702 add%e2.%z2 %2,%M0\;ax\;%A2 %H2,%H0
1703 add.d %M2,%M0\;ax\;add.d %H2,%H0
1704 add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
1706 ; It seems no use allowing a memory operand for this one, because we'd
1707 ; need a scratch register for incrementing the address.
1708 (define_insn "*adddi3_v32"
1709 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1710 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0,0,0")
1711 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r,n")))]
1714 addq %2,%M0\;addc 0,%H0
1715 subq %n2,%M0\;ax\;subq 0,%H0
1716 add%e2.%z2 %2,%M0\;addc %H2,%H0
1717 add.d %M2,%M0\;addc %H2,%H0
1718 add.d %M2,%M0\;addc %H2,%H0")
1720 (define_expand "add<mode>3"
1721 [(set (match_operand:BWD 0 "register_operand")
1723 (match_operand:BWD 1 "register_operand")
1724 (match_operand:BWD 2 "general_operand")))]
1728 (define_insn "*addsi3_non_v32"
1729 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r, r,r, r")
1731 (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0, 0,r, r")
1732 (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,!S,g,!To,0")))]
1734 ;; The last constraint is due to that after reload, the '%' is not
1735 ;; honored, and canonicalization doesn't care about keeping the same
1736 ;; register as in destination. This will happen after insn splitting.
1737 ;; gcc <= 2.7.2. FIXME: Check for gcc-2.9x
1741 switch (which_alternative)
1745 return "add.d %2,%0";
1747 return "addq %2,%0";
1749 return "subq %n2,%0";
1751 /* 'Known value', but not in -63..63.
1752 Check if addu/subu may be used. */
1753 if (INTVAL (operands[2]) > 0)
1755 if (INTVAL (operands[2]) < 256)
1756 return "addu.b %2,%0";
1757 if (INTVAL (operands[2]) < 65536)
1758 return "addu.w %2,%0";
1762 if (INTVAL (operands[2]) >= -255)
1763 return "subu.b %n2,%0";
1764 if (INTVAL (operands[2]) >= -65535)
1765 return "subu.w %n2,%0";
1767 return "add.d %2,%0";
1770 rtx tem = operands[2];
1771 gcc_assert (GET_CODE (tem) == CONST);
1772 tem = XEXP (tem, 0);
1773 if (GET_CODE (tem) == PLUS
1774 && GET_CODE (XEXP (tem, 0)) == UNSPEC
1775 /* We don't allow CRIS_UNSPEC_PCREL here; we can't have a
1776 pc-relative operand in an add insn. */
1777 && XINT (XEXP (tem, 0), 1) == CRIS_UNSPEC_GOTREL
1778 && CONST_INT_P (XEXP (tem, 1)))
1779 tem = XEXP (tem, 0);
1780 gcc_assert (GET_CODE (tem) == UNSPEC);
1781 switch (XINT (tem, 1))
1783 case CRIS_UNSPEC_GOTREAD:
1784 case CRIS_UNSPEC_PLTGOTREAD:
1785 /* Using sign-extend mostly to be consistent with the
1786 indexed addressing mode. */
1788 return "adds.w %2,%0";
1789 return "add.d %2,%0";
1791 case CRIS_UNSPEC_PLT_GOTREL:
1792 case CRIS_UNSPEC_GOTREL:
1793 return "add.d %2,%0";
1799 return "add%u2 %2,%0";
1801 return "add.d %2,%1,%0";
1803 return "add.d %1,%0";
1805 return "BOGUS addsi %2+%1 to %0";
1808 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no,yes")])
1810 ; FIXME: Check what's best: having the three-operand ACR alternative
1811 ; before or after the corresponding-operand2 alternative. Check for
1812 ; *all* insns. FIXME: constant constraint letter for -128..127.
1813 (define_insn "*addsi3_v32"
1814 [(set (match_operand:SI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,!a,r,r,r,!a")
1816 (match_operand:SI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r, 0,0,0,r")
1817 (match_operand:SI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,L,L, P,n,g,g")))]
1833 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no,no,no,no,no")
1834 (set_attr "cc" "*,none,*,none,*,*,none,*,*,*,*,*,none")])
1836 (define_insn "*addhi3_non_v32"
1837 [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
1838 (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
1839 (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
1848 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
1849 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
1851 (define_insn "*addhi3_v32"
1852 [(set (match_operand:HI 0 "register_operand" "=r, !a,r,!a, r,r,!a,r,!a")
1854 (match_operand:HI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,r")
1855 (match_operand:HI 2 "general_operand" "r, r, Q>,Q>,J,N,NJ,g,g")))]
1867 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,no,no")
1868 (set_attr "cc" "*,none,*,none,clobber,clobber,none,*,none")])
1870 (define_insn "*addqi3_non_v32"
1871 [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
1872 (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
1873 (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
1883 [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no")
1884 (set_attr "cc" "normal,normal,clobber,clobber,clobber,normal,normal")])
1886 (define_insn "*addqi3_v32"
1887 [(set (match_operand:QI 0 "register_operand" "=r,!a,r,!a, r,r,!a,r,r,!a")
1889 (match_operand:QI 1 "register_operand" "%0,r, 0, r, 0,0,r, 0,0,r")
1890 (match_operand:QI 2 "general_operand" "r,r, Q>,Q>,J,N,NJ,O,g,g")))]
1903 [(set_attr "slottable" "yes,yes,yes,yes,yes,yes,yes,yes,no,no")
1904 (set_attr "cc" "*,none,*,none,clobber,clobber,none,clobber,*,none")])
1908 ;; Note that because of insn canonicalization these will *seldom* but
1909 ;; rarely be used with a known constant as an operand.
1911 ;; Note that for the 'P' constraint, the high part can be -1 or 0. We
1912 ;; output the insn through the 'D' output modifier as "subs.w" and "subq",
1914 (define_expand "subdi3"
1915 [(set (match_operand:DI 0 "register_operand")
1916 (minus:DI (match_operand:DI 1 "register_operand")
1917 (match_operand:DI 2 "general_operand")))]
1920 if (TARGET_V32 && MEM_P (operands[2]))
1921 operands[2] = force_reg (DImode, operands[2]);
1924 (define_insn "*subdi3_non_v32"
1925 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r,&r")
1926 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0,r")
1927 (match_operand:DI 2 "general_operand" "J,N,P,g,!To")))]
1930 subq %2,%M0\;ax\;subq 0,%H0
1931 addq %n2,%M0\;ax\;addq 0,%H0
1932 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1933 sub.d %M2,%M0\;ax\;sub.d %H2,%H0
1934 sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
1936 (define_insn "*subdi3_v32"
1937 [(set (match_operand:DI 0 "register_operand" "=r,r,r,&r")
1938 (minus:DI (match_operand:DI 1 "register_operand" "0,0,0,0")
1939 (match_operand:DI 2 "nonmemory_operand" "J,N,P,r")))]
1942 subq %2,%M0\;ax\;subq 0,%H0
1943 addq %n2,%M0\;ax\;addq 0,%H0
1944 sub%e2.%z2 %2,%M0\;ax\;%D2 %H2,%H0
1945 sub.d %M2,%M0\;ax\;sub.d %H2,%H0")
1947 (define_expand "sub<mode>3"
1948 [(set (match_operand:BWD 0 "register_operand")
1950 (match_operand:BWD 1 "register_operand")
1951 (match_operand:BWD 2 "general_operand")))]
1955 (define_insn "*subsi3_non_v32"
1956 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
1958 (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
1959 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
1962 ;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
1963 ;; But then again, %2 should not be negative.
1974 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
1976 (define_insn "*subsi3_v32"
1977 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
1979 (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0")
1980 (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g")))]
1990 [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
1992 (define_insn "*sub<mode>3_nonv32"
1993 [(set (match_operand:BW 0 "register_operand" "=r,r, r,r,r,r")
1994 (minus:BW (match_operand:BW 1 "register_operand" "0,0, 0,0,0,r")
1995 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g,!To")))]
2004 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2005 (set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
2007 (define_insn "*sub<mode>3_v32"
2008 [(set (match_operand:BW 0 "register_operand" "=r,r,r,r,r")
2009 (minus:BW (match_operand:BW 1 "register_operand" "0,0,0,0,0")
2010 (match_operand:BW 2 "general_operand" "r,Q>,J,N,g")))]
2018 [(set_attr "slottable" "yes,yes,yes,yes,no")
2019 (set_attr "cc" "normal,normal,clobber,clobber,normal")])
2021 ;; CRIS has some add/sub-with-sign/zero-extend instructions.
2022 ;; Although these perform sign/zero-extension to SImode, they are
2023 ;; equally applicable for the HImode case.
2024 ;; FIXME: Check; GCC should handle the widening.
2025 ;; Note that these must be located after the normal add/sub patterns,
2026 ;; so not to get constants into any less specific operands.
2028 ;; Extend with add/sub and side-effect.
2030 ;; ADDS/SUBS/ADDU/SUBU and BOUND, which needs a check for zero_extend
2032 ;; adds/subs/addu/subu bound [rx=ry+rz.S]
2035 ;; FIXME: GCC should widen.
2037 (define_insn "*extopqihi_side_biap"
2038 [(set (match_operand:HI 0 "register_operand" "=r,r")
2040 6 "cris_additive_operand_extend_operator"
2041 [(match_operand:HI 1 "register_operand" "0,0")
2043 7 "cris_extend_operator"
2045 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2046 (match_operand:SI 3 "const_int_operand" "n,n"))
2047 (match_operand:SI 4 "register_operand" "r,r")))])]))
2048 (set (match_operand:SI 5 "register_operand" "=*4,r")
2049 (plus:SI (mult:SI (match_dup 2)
2052 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2055 %x6%e7.%m7 [%5=%4+%2%T3],%0")
2057 (define_insn "*extop<mode>si_side_biap"
2058 [(set (match_operand:SI 0 "register_operand" "=r,r")
2060 6 "cris_operand_extend_operator"
2061 [(match_operand:SI 1 "register_operand" "0,0")
2063 7 "cris_extend_operator"
2065 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2066 (match_operand:SI 3 "const_int_operand" "n,n"))
2067 (match_operand:SI 4 "register_operand" "r,r")))])]))
2068 (set (match_operand:SI 5 "register_operand" "=*4,r")
2069 (plus:SI (mult:SI (match_dup 2)
2072 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[7]) == ZERO_EXTEND)
2073 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2076 %x6%e7<m> [%5=%4+%2%T3],%0")
2083 (define_insn "*extopqihi_side"
2084 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2086 5 "cris_additive_operand_extend_operator"
2087 [(match_operand:HI 1 "register_operand" "0,0,0,0,0")
2089 6 "cris_extend_operator"
2091 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2092 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2094 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2095 (plus:SI (match_dup 2)
2097 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2099 if ((which_alternative == 0 || which_alternative == 3)
2100 && (!CONST_INT_P (operands[3])
2101 || INTVAL (operands[3]) > 127
2102 || INTVAL (operands[3]) < -128
2103 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2104 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2106 if (which_alternative == 4)
2107 return "%x5%E6.%m6 [%4=%3%S2],%0";
2108 return "%x5%E6.%m6 [%4=%2%S3],%0";
2111 (define_insn "*extop<mode>si_side"
2112 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2114 5 "cris_operand_extend_operator"
2115 [(match_operand:SI 1 "register_operand" "0,0,0,0,0")
2117 6 "cris_extend_operator"
2119 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2120 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")
2122 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2123 (plus:SI (match_dup 2)
2125 "(GET_CODE (operands[5]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2126 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2128 if ((which_alternative == 0 || which_alternative == 3)
2129 && (!CONST_INT_P (operands[3])
2130 || INTVAL (operands[3]) > 127
2131 || INTVAL (operands[3]) < -128
2132 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2133 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2135 if (which_alternative == 4)
2136 return "%x5%E6<m> [%4=%3%S2],%0";
2137 return "%x5%E6<m> [%4=%2%S3],%0";
2141 ;; As with op.S we may have to add special pattern to match commuted
2142 ;; operands to adds/addu and bound
2144 ;; adds/addu/bound [rx=ry+rz.S]
2147 ;; FIXME: GCC should widen.
2149 (define_insn "*extopqihi_swap_side_biap"
2150 [(set (match_operand:HI 0 "register_operand" "=r,r")
2153 6 "cris_extend_operator"
2155 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2156 (match_operand:SI 3 "const_int_operand" "n,n"))
2157 (match_operand:SI 4 "register_operand" "r,r")))])
2158 (match_operand:HI 1 "register_operand" "0,0")))
2159 (set (match_operand:SI 5 "register_operand" "=*4,r")
2160 (plus:SI (mult:SI (match_dup 2)
2163 "cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2166 add%e6.b [%5=%4+%2%T3],%0")
2168 (define_insn "*extop<mode>si_swap_side_biap"
2169 [(set (match_operand:SI 0 "register_operand" "=r,r")
2171 7 "cris_plus_or_bound_operator"
2173 6 "cris_extend_operator"
2175 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2176 (match_operand:SI 3 "const_int_operand" "n,n"))
2177 (match_operand:SI 4 "register_operand" "r,r")))])
2178 (match_operand:SI 1 "register_operand" "0,0")]))
2179 (set (match_operand:SI 5 "register_operand" "=*4,r")
2180 (plus:SI (mult:SI (match_dup 2)
2183 "(GET_CODE (operands[7]) != UMIN || GET_CODE (operands[6]) == ZERO_EXTEND)
2184 && cris_side_effect_mode_ok (MULT, operands, 5, 4, 2, 3, 0)"
2187 %x7%E6<m> [%5=%4+%2%T3],%0")
2190 ;; FIXME: GCC should widen.
2194 (define_insn "*extopqihi_swap_side"
2195 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
2198 5 "cris_extend_operator"
2200 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2201 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2202 (match_operand:HI 1 "register_operand" "0,0,0,0,0")))
2203 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2204 (plus:SI (match_dup 2)
2206 "cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2208 if ((which_alternative == 0 || which_alternative == 3)
2209 && (!CONST_INT_P (operands[3])
2210 || INTVAL (operands[3]) > 127
2211 || INTVAL (operands[3]) < -128
2212 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2213 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2215 if (which_alternative == 4)
2216 return "add%e5.b [%4=%3%S2],%0";
2217 return "add%e5.b [%4=%2%S3],%0";
2220 (define_insn "*extop<mode>si_swap_side"
2221 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
2223 6 "cris_plus_or_bound_operator"
2225 5 "cris_extend_operator"
2227 (match_operand:SI 2 "cris_bdap_operand" "%r,r,r,R,R")
2228 (match_operand:SI 3 "cris_bdap_operand" "r>Rn,r,>Rn,r,r")))])
2229 (match_operand:SI 1 "register_operand" "0,0,0,0,0")]))
2230 (set (match_operand:SI 4 "register_operand" "=*2,r,r,*3,r")
2231 (plus:SI (match_dup 2)
2233 "(GET_CODE (operands[6]) != UMIN || GET_CODE (operands[5]) == ZERO_EXTEND)
2234 && cris_side_effect_mode_ok (PLUS, operands, 4, 2, 3, -1, 0)"
2236 if ((which_alternative == 0 || which_alternative == 3)
2237 && (!CONST_INT_P (operands[3])
2238 || INTVAL (operands[3]) > 127
2239 || INTVAL (operands[3]) < -128
2240 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'N')
2241 || CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'J')))
2243 if (which_alternative == 4)
2244 return \"%x6%E5.%m5 [%4=%3%S2],%0\";
2245 return "%x6%E5<m> [%4=%2%S3],%0";
2248 ;; Extend versions (zero/sign) of normal add/sub (no side-effects).
2251 ;; FIXME: GCC should widen.
2253 (define_insn "*extopqihi_non_v32"
2254 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2256 3 "cris_additive_operand_extend_operator"
2257 [(match_operand:HI 1 "register_operand" "0,0,0,r")
2259 4 "cris_extend_operator"
2260 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2261 "!TARGET_V32 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2262 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2267 %x3%E4.%m4 %2,%1,%0"
2268 [(set_attr "slottable" "yes,yes,no,no")
2269 (set_attr "cc" "clobber")])
2271 (define_insn "*extopqihi_v32"
2272 [(set (match_operand:HI 0 "register_operand" "=r,r")
2274 3 "cris_additive_operand_extend_operator"
2275 [(match_operand:HI 1 "register_operand" "0,0")
2277 4 "cris_extend_operator"
2278 [(match_operand:QI 2 "nonimmediate_operand" "r,m")])]))]
2281 [(set_attr "slottable" "yes")
2282 (set_attr "cc" "clobber")])
2286 (define_insn "*extop<mode>si_non_v32"
2287 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2289 3 "cris_operand_extend_operator"
2290 [(match_operand:SI 1 "register_operand" "0,0,0,r")
2292 4 "cris_extend_operator"
2293 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])]))]
2295 && (GET_CODE (operands[3]) != UMIN || GET_CODE (operands[4]) == ZERO_EXTEND)
2296 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
2297 && (operands[1] != frame_pointer_rtx || GET_CODE (operands[3]) != PLUS)"
2303 [(set_attr "slottable" "yes,yes,no,no")])
2305 (define_insn "*extop<mode>si_v32"
2306 [(set (match_operand:SI 0 "register_operand" "=r,r")
2308 3 "cris_additive_operand_extend_operator"
2309 [(match_operand:SI 1 "register_operand" "0,0")
2311 4 "cris_extend_operator"
2312 [(match_operand:BW 2 "nonimmediate_operand" "r,m")])]))]
2315 [(set_attr "slottable" "yes")])
2317 ;; As with the side-effect patterns, may have to have swapped operands for add.
2318 ;; For commutative operands, these are the canonical forms.
2322 (define_insn "*addxqihi_swap_non_v32"
2323 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
2326 3 "cris_extend_operator"
2327 [(match_operand:QI 2 "nonimmediate_operand" "r,Q>,m,!To")])
2328 (match_operand:HI 1 "register_operand" "0,0,0,r")))]
2329 "!TARGET_V32 && operands[1] != frame_pointer_rtx"
2335 [(set_attr "slottable" "yes,yes,no,no")
2336 (set_attr "cc" "clobber")])
2338 ;; A case for v32, to catch the "addo" insn in addition to "adds". We
2339 ;; only care to match the canonical form; there should be no other.
2341 (define_insn "*addsbw_v32"
2342 [(set (match_operand:HI 0 "register_operand" "=r,r,!a")
2345 (match_operand:QI 2 "nonimmediate_operand" "r,m,m"))
2346 (match_operand:HI 1 "register_operand" "0,0,r")))]
2352 [(set_attr "slottable" "yes")
2353 (set_attr "cc" "clobber,clobber,none")])
2355 (define_insn "*addubw_v32"
2356 [(set (match_operand:HI 0 "register_operand" "=r,r")
2359 (match_operand:QI 2 "nonimmediate_operand" "r,m"))
2360 (match_operand:HI 1 "register_operand" "0,0")))]
2363 [(set_attr "slottable" "yes")
2364 (set_attr "cc" "clobber")])
2366 (define_insn "*extop<mode>si_swap_non_v32"
2367 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2369 4 "cris_plus_or_bound_operator"
2371 3 "cris_extend_operator"
2372 [(match_operand:BW 2 "nonimmediate_operand" "r,Q>,m,!To")])
2373 (match_operand:SI 1 "register_operand" "0,0,0,r")]))]
2375 && (GET_CODE (operands[4]) != UMIN || GET_CODE (operands[3]) == ZERO_EXTEND)
2376 && operands[1] != frame_pointer_rtx"
2382 [(set_attr "slottable" "yes,yes,no,no")])
2384 (define_insn "*adds<mode>_v32"
2385 [(set (match_operand:SI 0 "register_operand" "=r,r,!a")
2388 (match_operand:BW 2 "nonimmediate_operand" "r,m,m"))
2389 (match_operand:SI 1 "register_operand" "0,0,r")))]
2395 [(set_attr "slottable" "yes")
2396 (set_attr "cc" "*,*,none")])
2398 (define_insn "*addu<mode>_v32"
2399 [(set (match_operand:SI 0 "register_operand" "=r,r")
2402 (match_operand:BW 2 "nonimmediate_operand" "r,m"))
2403 (match_operand:SI 1 "register_operand" "0,0")))]
2404 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2406 [(set_attr "slottable" "yes")])
2408 (define_insn "*bound<mode>_v32"
2409 [(set (match_operand:SI 0 "register_operand" "=r")
2412 (match_operand:BW 2 "register_operand" "r"))
2413 (match_operand:SI 1 "register_operand" "0")))]
2414 "TARGET_V32 && operands[1] != frame_pointer_rtx"
2416 [(set_attr "slottable" "yes")])
2418 ;; This is the special case when we use what corresponds to the
2419 ;; instruction above in "casesi". Do *not* change it to use the generic
2420 ;; pattern and "REG 15" as pc; I did that and it led to madness and
2421 ;; maintenance problems: Instead of (as imagined) recognizing and removing
2422 ;; or replacing this pattern with something simpler, other variant
2423 ;; patterns were recognized or combined, including some prefix variants
2424 ;; where the value in pc is not that of the next instruction (which means
2425 ;; this instruction actually *is* special and *should* be marked as such).
2426 ;; When switching from the "generic pattern match" approach to this simpler
2427 ;; approach, there were insignificant differences in gcc, ipps and
2428 ;; product code, somehow due to scratching reload behind the ear or
2429 ;; something. Testcase "gcc" looked .01% slower and 4 bytes bigger;
2430 ;; product code became .001% smaller but "looked better". The testcase
2431 ;; "ipps" was just different at register allocation).
2433 ;; Assumptions in the jump optimizer forces us to use IF_THEN_ELSE in this
2434 ;; pattern with the default-label as the else, with the "if" being
2435 ;; index-is-less-than the max number of cases plus one. The default-label
2436 ;; is attached to the end of the case-table at time of output.
2438 (define_insn "*casesi_adds_w"
2441 (ltu (match_operand:SI 0 "register_operand" "r")
2442 (match_operand:SI 1 "const_int_operand" "n"))
2443 (plus:SI (sign_extend:SI
2445 (plus:SI (mult:SI (match_dup 0) (const_int 2))
2448 (label_ref (match_operand 2 "" ""))))
2449 (use (label_ref (match_operand 3 "" "")))]
2450 "!TARGET_V32 && operands[0] != frame_pointer_rtx"
2451 "adds.w [$pc+%0.w],$pc"
2452 [(set_attr "cc" "clobber")])
2454 ;; For V32, we just have a jump, but we need to mark the table as used,
2455 ;; and the jump insn must have the if_then_else form expected by core
2456 ;; GCC. Since we don't want to prolong the lifetime of the original
2457 ;; index value, we compare against "unspec 0". It's a pity we have to
2458 ;; jump through to get the default label in place and to keep the jump
2459 ;; table around. FIXME: Look into it some time.
2461 (define_insn "*casesi_jump_v32"
2464 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI)
2465 (match_operand:SI 0 "const_int_operand" "n"))
2466 (match_operand:SI 1 "register_operand" "r")
2467 (label_ref (match_operand 2 "" ""))))
2468 (use (label_ref (match_operand 3 "" "")))]
2471 [(set_attr "cc" "clobber")
2472 (set_attr "slottable" "has_slot")])
2474 ;; Multiply instructions.
2476 ;; Sometimes powers of 2 (which are normally canonicalized to a
2477 ;; left-shift) appear here, as a result of address reloading.
2478 ;; As a special, for values 3 and 5, we can match with an addi, so add those.
2480 ;; FIXME: This may be unnecessary now.
2481 ;; Explicitly named for convenience of having a gen_... function.
2483 (define_insn "addi_mul"
2484 [(set (match_operand:SI 0 "register_operand" "=r")
2486 (match_operand:SI 1 "register_operand" "%0")
2487 (match_operand:SI 2 "const_int_operand" "n")))]
2488 "operands[0] != frame_pointer_rtx
2489 && operands[1] != frame_pointer_rtx
2490 && CONST_INT_P (operands[2])
2491 && (INTVAL (operands[2]) == 2
2492 || INTVAL (operands[2]) == 4 || INTVAL (operands[2]) == 3
2493 || INTVAL (operands[2]) == 5)"
2495 if (INTVAL (operands[2]) == 2)
2497 else if (INTVAL (operands[2]) == 4)
2499 else if (INTVAL (operands[2]) == 3)
2500 return "addi %0.w,%0";
2501 else if (INTVAL (operands[2]) == 5)
2502 return "addi %0.d,%0";
2503 return "BAD: adr_mulsi: %0=%1*%2";
2505 [(set_attr "slottable" "yes")
2506 ;; No flags are changed if this insn is "addi", but it does not seem
2507 ;; worth the trouble to distinguish that to the lslq cases.
2508 (set_attr "cc" "clobber")])
2510 ;; The addi insn as it is normally used.
2512 ;; Make the the ACR alternative taste bad enough to not choose it as a
2513 ;; preference to avoid spilling problems (unwind-dw2-fde.c at build).
2514 ;; FIXME: Revisit for new register allocator.
2516 (define_insn "*addi"
2517 [(set (match_operand:SI 0 "register_operand" "=r,!a")
2519 (mult:SI (match_operand:SI 2 "register_operand" "r,r")
2520 (match_operand:SI 3 "const_int_operand" "n,n"))
2521 (match_operand:SI 1 "register_operand" "0,r")))]
2522 "operands[0] != frame_pointer_rtx
2523 && operands[1] != frame_pointer_rtx
2524 && CONST_INT_P (operands[3])
2525 && (INTVAL (operands[3]) == 1
2526 || INTVAL (operands[3]) == 2 || INTVAL (operands[3]) == 4)"
2530 [(set_attr "slottable" "yes")
2531 (set_attr "cc" "none")])
2533 ;; The mstep instruction. Probably not useful by itself; it's to
2534 ;; non-linear wrt. the other insns. We used to expand to it, so at least
2537 (define_insn "mstep_shift"
2538 [(set (match_operand:SI 0 "register_operand" "=r")
2540 (lt:SI (cc0) (const_int 0))
2541 (plus:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2543 (match_operand:SI 2 "register_operand" "r"))
2544 (ashift:SI (match_operand:SI 3 "register_operand" "0")
2548 [(set_attr "slottable" "yes")])
2550 ;; When illegitimate addresses are legitimized, sometimes gcc forgets
2551 ;; to canonicalize the multiplications.
2553 ;; FIXME: Check gcc > 2.7.2, remove and possibly fix in gcc.
2555 (define_insn "mstep_mul"
2556 [(set (match_operand:SI 0 "register_operand" "=r")
2558 (lt:SI (cc0) (const_int 0))
2559 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2561 (match_operand:SI 2 "register_operand" "r"))
2562 (mult:SI (match_operand:SI 3 "register_operand" "0")
2565 && operands[0] != frame_pointer_rtx
2566 && operands[1] != frame_pointer_rtx
2567 && operands[2] != frame_pointer_rtx
2568 && operands[3] != frame_pointer_rtx"
2570 [(set_attr "slottable" "yes")])
2572 (define_insn "<u>mul<s><mode>3"
2573 [(set (match_operand:WD 0 "register_operand" "=r")
2575 (szext:WD (match_operand:<S> 1 "register_operand" "%0"))
2576 (szext:WD (match_operand:<S> 2 "register_operand" "r"))))
2577 (clobber (match_scratch:SI 3 "=h"))]
2578 "TARGET_HAS_MUL_INSNS"
2579 "%!mul<su><mm> %2,%0"
2580 [(set (attr "slottable")
2581 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2583 (const_string "yes")))
2584 ;; For umuls.[bwd] it's just N unusable here, but let's be safe.
2585 ;; For muls.b, this really extends to SImode, so cc should be
2586 ;; considered clobbered.
2587 ;; For muls.w, it's just N unusable here, but let's be safe.
2588 (set_attr "cc" "clobber")])
2590 ;; Note that gcc does not make use of such a thing as umulqisi3. It gets
2591 ;; confused and will erroneously use it instead of umulhisi3, failing (at
2592 ;; least) gcc.c-torture/execute/arith-rand.c at all optimization levels.
2593 ;; Inspection of optab code shows that there must be only one widening
2594 ;; multiplication per mode widened to.
2596 (define_insn "mulsi3"
2597 [(set (match_operand:SI 0 "register_operand" "=r")
2598 (mult:SI (match_operand:SI 1 "register_operand" "%0")
2599 (match_operand:SI 2 "register_operand" "r")))
2600 (clobber (match_scratch:SI 3 "=h"))]
2601 "TARGET_HAS_MUL_INSNS"
2603 [(set (attr "slottable")
2604 (if_then_else (ne (symbol_ref "TARGET_MUL_BUG") (const_int 0))
2606 (const_string "yes")))
2607 ;; Just N unusable here, but let's be safe.
2608 (set_attr "cc" "clobber")])
2610 ;; A few multiply variations.
2612 ;; When needed, we can get the high 32 bits from the overflow
2613 ;; register. We don't care to split and optimize these.
2615 ;; Note that cc0 is still valid after the move-from-overflow-register
2616 ;; insn; no special precaution need to be taken in cris_notice_update_cc.
2618 (define_insn "<u>mulsidi3"
2619 [(set (match_operand:DI 0 "register_operand" "=r")
2621 (szext:DI (match_operand:SI 1 "register_operand" "%0"))
2622 (szext:DI (match_operand:SI 2 "register_operand" "r"))))
2623 (clobber (match_scratch:SI 3 "=h"))]
2624 "TARGET_HAS_MUL_INSNS"
2625 "%!mul<su>.d %2,%M0\;move $mof,%H0")
2627 ;; These two patterns may be expressible by other means, perhaps by making
2628 ;; [u]?mulsidi3 a define_expand.
2630 ;; Due to register allocation braindamage, the clobber 1,2 alternatives
2631 ;; cause a move into the clobbered register *before* the insn, then
2632 ;; after the insn, mof is moved too, rather than the clobber assigned
2633 ;; the last mof target. This became apparent when making MOF and SRP
2634 ;; visible registers, with the necessary tweak to smulsi3_highpart.
2635 ;; Because these patterns are used in division by constants, that damage
2636 ;; is visible (ipps regression tests). Therefore the last two
2637 ;; alternatives, "helping" reload to avoid an unnecessary move, but
2638 ;; punished by force of one "?". Check code from "int d (int a) {return
2639 ;; a / 1000;}" and unsigned. FIXME: Comment above was for 3.2, revisit.
2641 (define_insn "<su>mulsi3_highpart"
2642 [(set (match_operand:SI 0 "register_operand" "=h,h,?r,?r")
2646 (szext:DI (match_operand:SI 1 "register_operand" "r,r,0,r"))
2647 (szext:DI (match_operand:SI 2 "register_operand" "r,r,r,0")))
2649 (clobber (match_scratch:SI 3 "=1,2,h,h"))]
2650 "TARGET_HAS_MUL_INSNS"
2654 %!mul<su>.d %2,%1\;move $mof,%0
2655 %!mul<su>.d %1,%2\;move $mof,%0"
2656 [(set_attr "slottable" "yes,yes,no,no")
2657 (set_attr "cc" "clobber")])
2659 ;; Divide and modulus instructions. CRIS only has a step instruction.
2661 (define_insn "dstep_shift"
2662 [(set (match_operand:SI 0 "register_operand" "=r")
2664 (geu:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
2666 (match_operand:SI 2 "register_operand" "r"))
2667 (minus:SI (ashift:SI (match_operand:SI 3 "register_operand" "0")
2669 (match_operand:SI 4 "register_operand" "2"))
2670 (ashift:SI (match_operand:SI 5 "register_operand" "0")
2674 [(set_attr "slottable" "yes")
2675 (set_attr "cc" "noov32")])
2677 ;; Here's a variant with mult instead of ashift.
2679 ;; FIXME: This should be investigated. Which one matches through combination?
2681 (define_insn "dstep_mul"
2682 [(set (match_operand:SI 0 "register_operand" "=r")
2684 (geu:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2686 (match_operand:SI 2 "register_operand" "r"))
2687 (minus:SI (mult:SI (match_operand:SI 3 "register_operand" "0")
2689 (match_operand:SI 4 "register_operand" "2"))
2690 (mult:SI (match_operand:SI 5 "register_operand" "0")
2692 "operands[0] != frame_pointer_rtx
2693 && operands[1] != frame_pointer_rtx
2694 && operands[2] != frame_pointer_rtx
2695 && operands[3] != frame_pointer_rtx"
2697 [(set_attr "slottable" "yes")
2698 (set_attr "cc" "noov32")])
2700 ;; Logical operators.
2704 ;; There is no use in defining "anddi3", because gcc can expand this by
2705 ;; itself, and make reasonable code without interference.
2707 ;; If the first operand is memory or a register and is the same as the
2708 ;; second operand, and the third operand is -256 or -65536, we can use
2709 ;; CLEAR instead. Or, if the first operand is a register, and the third
2710 ;; operand is 255 or 65535, we can zero_extend.
2711 ;; GCC isn't smart enough to recognize these cases (yet), and they seem
2712 ;; to be common enough to be worthwhile.
2713 ;; FIXME: This should be made obsolete.
2715 (define_expand "andsi3"
2716 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2717 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2718 (match_operand:SI 2 "general_operand" "")))]
2721 if (! (CONST_INT_P (operands[2])
2722 && (((INTVAL (operands[2]) == -256
2723 || INTVAL (operands[2]) == -65536)
2724 && rtx_equal_p (operands[1], operands[0]))
2725 || ((INTVAL (operands[2]) == 255
2726 || INTVAL (operands[2]) == 65535)
2727 && REG_P (operands[0])))))
2729 /* Make intermediate steps if operand0 is not a register or
2730 operand1 is not a register, and hope that the reload pass will
2731 make something useful out of it. Note that the operands are
2732 *not* canonicalized. For the moment, I chicken out on this,
2733 because all or most ports do not describe 'and' with
2734 canonicalized operands, and I seem to remember magic in reload,
2735 checking that operand1 has constraint '%0', in which case
2736 operand0 and operand1 must have similar predicates.
2737 FIXME: Investigate. */
2738 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (SImode);
2739 rtx reg1 = operands[1];
2743 emit_move_insn (reg0, reg1);
2747 emit_insn (gen_rtx_SET (SImode, reg0,
2748 gen_rtx_AND (SImode, reg1, operands[2])));
2750 /* Make sure we get the right *final* destination. */
2751 if (! REG_P (operands[0]))
2752 emit_move_insn (operands[0], reg0);
2758 ;; Some special cases of andsi3.
2760 (define_insn "*andsi_movu"
2761 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
2762 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%r,Q,To")
2763 (match_operand:SI 2 "const_int_operand" "n,n,n")))]
2764 "(INTVAL (operands[2]) == 255 || INTVAL (operands[2]) == 65535)
2765 && !side_effects_p (operands[1])"
2767 [(set_attr "slottable" "yes,yes,no")])
2769 (define_insn "*andsi_clear"
2770 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,Q,Q,To,To")
2771 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0")
2772 (match_operand:SI 2 "const_int_operand" "P,n,P,n,P,n")))]
2773 "(INTVAL (operands[2]) == -65536 || INTVAL (operands[2]) == -256)
2774 && !side_effects_p (operands[0])"
2782 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2783 (set_attr "cc" "none")])
2785 ;; This is a catch-all pattern, taking care of everything that was not
2786 ;; matched in the insns above.
2788 ;; Sidenote: the tightening from "nonimmediate_operand" to
2789 ;; "register_operand" for operand 1 actually increased the register
2790 ;; pressure (worse code). That will hopefully change with an
2791 ;; improved reload pass.
2793 (define_insn "*expanded_andsi_non_v32"
2794 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
2795 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
2796 (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
2804 [(set_attr "slottable" "yes,yes,yes,no,no")])
2806 (define_insn "*expanded_andsi_v32"
2807 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2808 (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
2809 (match_operand:SI 2 "general_operand" "I,r,Q>,g")))]
2816 [(set_attr "slottable" "yes,yes,yes,no")
2817 (set_attr "cc" "noov32")])
2819 ;; For both QI and HI we may use the quick patterns. This results in
2820 ;; useless condition codes, but that is used rarely enough for it to
2821 ;; normally be a win (could check ahead for use of cc0, but seems to be
2822 ;; more pain than win).
2824 ;; FIXME: See note for andsi3
2826 (define_expand "andhi3"
2827 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2828 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
2829 (match_operand:HI 2 "general_operand" "")))]
2832 if (! (CONST_INT_P (operands[2])
2833 && (((INTVAL (operands[2]) == -256
2834 || INTVAL (operands[2]) == 65280)
2835 && rtx_equal_p (operands[1], operands[0]))
2836 || (INTVAL (operands[2]) == 255
2837 && REG_P (operands[0])))))
2839 /* See comment for andsi3. */
2840 rtx reg0 = REG_P (operands[0]) ? operands[0] : gen_reg_rtx (HImode);
2841 rtx reg1 = operands[1];
2845 emit_move_insn (reg0, reg1);
2849 emit_insn (gen_rtx_SET (HImode, reg0,
2850 gen_rtx_AND (HImode, reg1, operands[2])));
2852 /* Make sure we get the right destination. */
2853 if (! REG_P (operands[0]))
2854 emit_move_insn (operands[0], reg0);
2860 ;; Some fast andhi3 special cases.
2862 (define_insn "*andhi_movu"
2863 [(set (match_operand:HI 0 "register_operand" "=r,r,r")
2864 (and:HI (match_operand:HI 1 "nonimmediate_operand" "r,Q,To")
2866 "!side_effects_p (operands[1])"
2868 [(set_attr "slottable" "yes,yes,no")])
2870 (define_insn "*andhi_clear"
2871 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,Q,To")
2872 (and:HI (match_operand:HI 1 "nonimmediate_operand" "0,0,0")
2874 "!side_effects_p (operands[0])"
2876 [(set_attr "slottable" "yes,yes,no")
2877 (set_attr "cc" "none")])
2879 ;; Catch-all andhi3 pattern.
2881 (define_insn "*expanded_andhi_non_v32"
2882 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
2883 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
2884 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
2886 ;; Sidenote: the tightening from "general_operand" to
2887 ;; "register_operand" for operand 1 actually increased the register
2888 ;; pressure (worse code). That will hopefully change with an
2889 ;; improved reload pass.
2900 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
2901 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
2903 (define_insn "*expanded_andhi_v32"
2904 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
2905 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
2906 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
2915 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
2916 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
2918 ;; A strict_low_part pattern.
2920 (define_insn "*andhi_lowpart_non_v32"
2921 [(set (strict_low_part
2922 (match_operand:HI 0 "register_operand" "+r,r, r,r,r,r"))
2923 (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
2924 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
2933 [(set_attr "slottable" "yes,yes,no,yes,no,no")
2934 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
2936 (define_insn "*andhi_lowpart_v32"
2937 [(set (strict_low_part
2938 (match_operand:HI 0 "register_operand" "+r,r,r,r,r"))
2939 (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0")
2940 (match_operand:HI 2 "general_operand" "r,Q>,L,O,g")))]
2948 [(set_attr "slottable" "yes,yes,no,yes,no")
2949 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
2951 (define_expand "andqi3"
2952 [(set (match_operand:QI 0 "register_operand")
2953 (and:QI (match_operand:QI 1 "register_operand")
2954 (match_operand:QI 2 "general_operand")))]
2958 (define_insn "*andqi3_non_v32"
2959 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
2960 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
2961 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
2970 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
2971 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
2973 (define_insn "*andqi3_v32"
2974 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
2975 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
2976 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
2984 [(set_attr "slottable" "yes,yes,yes,yes,no")
2985 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
2987 (define_insn "*andqi_lowpart_non_v32"
2988 [(set (strict_low_part
2989 (match_operand:QI 0 "register_operand" "+r,r, r,r,r"))
2990 (and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
2991 (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
2999 [(set_attr "slottable" "yes,yes,yes,no,no")
3000 (set_attr "cc" "normal,normal,clobber,normal,normal")])
3002 (define_insn "*andqi_lowpart_v32"
3003 [(set (strict_low_part
3004 (match_operand:QI 0 "register_operand" "+r,r,r,r"))
3005 (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0")
3006 (match_operand:QI 2 "general_operand" "r,Q>,O,g")))]
3013 [(set_attr "slottable" "yes,yes,yes,no")
3014 (set_attr "cc" "noov32,noov32,clobber,noov32")])
3018 ;; Same comment as anddi3 applies here - no need for such a pattern.
3020 ;; It seems there's no need to jump through hoops to get good code such as
3023 (define_expand "ior<mode>3"
3024 [(set (match_operand:BWD 0 "register_operand")
3025 (ior:BWD (match_operand:BWD 1 "register_operand")
3026 (match_operand:BWD 2 "general_operand")))]
3030 (define_insn "*iorsi3_non_v32"
3031 [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
3032 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
3033 (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))]
3042 [(set_attr "slottable" "yes,yes,yes,no,no,no")
3043 (set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
3045 (define_insn "*iorsi3_v32"
3046 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
3047 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0")
3048 (match_operand:SI 2 "general_operand" "I,r,Q>,n,g")))]
3056 [(set_attr "slottable" "yes,yes,yes,no,no")
3057 (set_attr "cc" "noov32,noov32,noov32,clobber,noov32")])
3059 (define_insn "*iorhi3_non_v32"
3060 [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
3061 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
3062 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
3072 [(set_attr "slottable" "yes,yes,yes,no,yes,no,no")
3073 (set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
3075 (define_insn "*iorhi3_v32"
3076 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
3077 (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0")
3078 (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g")))]
3087 [(set_attr "slottable" "yes,yes,yes,no,yes,no")
3088 (set_attr "cc" "clobber,noov32,noov32,noov32,clobber,noov32")])
3090 (define_insn "*iorqi3_non_v32"
3091 [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
3092 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
3093 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
3102 [(set_attr "slottable" "yes,yes,yes,yes,no,no")
3103 (set_attr "cc" "clobber,normal,normal,clobber,normal,normal")])
3105 (define_insn "*iorqi3_v32"
3106 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
3107 (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0")
3108 (match_operand:QI 2 "general_operand" "I,r,Q>,O,g")))]
3116 [(set_attr "slottable" "yes,yes,yes,yes,no")
3117 (set_attr "cc" "clobber,noov32,noov32,clobber,noov32")])
3121 ;; See comment about "anddi3" for xordi3 - no need for such a pattern.
3122 ;; FIXME: Do we really need the shorter variants?
3124 (define_insn "xorsi3"
3125 [(set (match_operand:SI 0 "register_operand" "=r")
3126 (xor:SI (match_operand:SI 1 "register_operand" "%0")
3127 (match_operand:SI 2 "register_operand" "r")))]
3130 [(set_attr "slottable" "yes")
3131 (set_attr "cc" "noov32")])
3133 (define_insn "xor<mode>3"
3134 [(set (match_operand:BW 0 "register_operand" "=r")
3135 (xor:BW (match_operand:BW 1 "register_operand" "%0")
3136 (match_operand:BW 2 "register_operand" "r")))]
3139 [(set_attr "slottable" "yes")
3140 (set_attr "cc" "clobber")])
3144 ;; Questionable use, here mostly as a (slightly usable) define_expand
3147 (define_expand "negsf2"
3150 (parallel [(set (match_operand:SF 0 "register_operand" "=r")
3151 (neg:SF (match_operand:SF 1
3152 "register_operand" "0")))
3153 (use (match_dup 2))])]
3156 operands[2] = gen_reg_rtx (SImode);
3157 operands[3] = GEN_INT (1 << 31);
3160 (define_insn "*expanded_negsf2"
3161 [(set (match_operand:SF 0 "register_operand" "=r")
3162 (neg:SF (match_operand:SF 1 "register_operand" "0")))
3163 (use (match_operand:SI 2 "register_operand" "r"))]
3166 [(set_attr "slottable" "yes")])
3168 ;; No "negdi2" although we could make one up that may be faster than
3169 ;; the one in libgcc.
3171 (define_insn "neg<mode>2"
3172 [(set (match_operand:BWD 0 "register_operand" "=r")
3173 (neg:BWD (match_operand:BWD 1 "register_operand" "r")))]
3176 [(set_attr "slottable" "yes")])
3180 ;; See comment on anddi3 - no need for a DImode pattern.
3181 ;; See also xor comment.
3183 (define_insn "one_cmplsi2"
3184 [(set (match_operand:SI 0 "register_operand" "=r")
3185 (not:SI (match_operand:SI 1 "register_operand" "0")))]
3188 [(set_attr "slottable" "yes")
3189 (set_attr "cc" "noov32")])
3191 (define_insn "one_cmpl<mode>2"
3192 [(set (match_operand:BW 0 "register_operand" "=r")
3193 (not:BW (match_operand:BW 1 "register_operand" "0")))]
3196 [(set_attr "slottable" "yes")
3197 (set_attr "cc" "clobber")])
3199 ;; Arithmetic/Logical shift right (and SI left).
3201 (define_insn "<shlr>si3"
3202 [(set (match_operand:SI 0 "register_operand" "=r")
3203 (shift:SI (match_operand:SI 1 "register_operand" "0")
3204 (match_operand:SI 2 "nonmemory_operand" "Kcr")))]
3207 if (REG_S_P (operands[2]))
3208 return "<slr>.d %2,%0";
3210 return "<slr>q %2,%0";
3212 [(set_attr "slottable" "yes")
3213 (set_attr "cc" "noov32")])
3215 ;; Since gcc gets lost, and forgets to zero-extend the source (or mask
3216 ;; the destination) when it changes shifts of lower modes into SImode,
3217 ;; it is better to make these expands an anonymous patterns instead of
3218 ;; the more correct define_insns. This occurs when gcc thinks that is
3219 ;; is better to widen to SImode and use immediate shift count.
3221 ;; FIXME: Is this legacy or still true for gcc >= 2.7.2?
3223 ;; FIXME: Can't parametrize sign_extend and zero_extend (before
3224 ;; mentioning "shiftrt"), so we need two patterns.
3225 (define_expand "ashr<mode>3"
3227 (sign_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3229 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3230 (set (match_dup 5) (ashiftrt:SI (match_dup 3) (match_dup 4)))
3231 (set (match_operand:BW 0 "general_operand" "")
3232 (subreg:BW (match_dup 5) 0))]
3237 for (i = 3; i < 6; i++)
3238 operands[i] = gen_reg_rtx (SImode);
3241 (define_expand "lshr<mode>3"
3243 (zero_extend:SI (match_operand:BW 1 "nonimmediate_operand" "")))
3245 (zero_extend:SI (match_operand:BW 2 "nonimmediate_operand" "")))
3246 (set (match_dup 5) (lshiftrt:SI (match_dup 3) (match_dup 4)))
3247 (set (match_operand:BW 0 "general_operand" "")
3248 (subreg:BW (match_dup 5) 0))]
3253 for (i = 3; i < 6; i++)
3254 operands[i] = gen_reg_rtx (SImode);
3257 (define_insn "*expanded_<shlr><mode>"
3258 [(set (match_operand:BW 0 "register_operand" "=r")
3259 (shiftrt:BW (match_operand:BW 1 "register_operand" "0")
3260 (match_operand:BW 2 "register_operand" "r")))]
3263 [(set_attr "slottable" "yes")
3264 (set_attr "cc" "noov32")])
3266 (define_insn "*<shlr><mode>_lowpart"
3267 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3268 (shiftrt:BW (match_dup 0)
3269 (match_operand:BW 1 "register_operand" "r")))]
3272 [(set_attr "slottable" "yes")
3273 (set_attr "cc" "noov32")])
3275 ;; Arithmetic/logical shift left.
3277 ;; For narrower modes than SI, we can use lslq although it makes cc
3278 ;; unusable. The win is that we do not have to reload the shift-count
3281 (define_insn "ashl<mode>3"
3282 [(set (match_operand:BW 0 "register_operand" "=r,r")
3283 (ashift:BW (match_operand:BW 1 "register_operand" "0,0")
3284 (match_operand:BW 2 "nonmemory_operand" "r,Kc")))]
3288 (CONST_INT_P (operands[2]) && INTVAL (operands[2]) > <nbitsm1>)
3290 : (CONSTANT_P (operands[2])
3291 ? "lslq %2,%0" : "lsl<m> %2,%0");
3293 [(set_attr "slottable" "yes")
3294 (set_attr "cc" "noov32,clobber")])
3296 ;; A strict_low_part matcher.
3298 (define_insn "*ashl<mode>_lowpart"
3299 [(set (strict_low_part (match_operand:BW 0 "register_operand" "+r"))
3300 (ashift:BW (match_dup 0)
3301 (match_operand:HI 1 "register_operand" "r")))]
3304 [(set_attr "slottable" "yes")
3305 (set_attr "cc" "noov32")])
3307 ;; Various strange insns that gcc likes.
3309 ;; Fortunately, it is simple to construct an abssf (although it may not
3310 ;; be very much used in practice).
3312 (define_insn "abssf2"
3313 [(set (match_operand:SF 0 "register_operand" "=r")
3314 (abs:SF (match_operand:SF 1 "register_operand" "0")))]
3316 "lslq 1,%0\;lsrq 1,%0")
3318 (define_insn "abssi2"
3319 [(set (match_operand:SI 0 "register_operand" "=r")
3320 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
3323 [(set_attr "slottable" "yes")
3324 (set_attr "cc" "noov32")])
3326 ;; FIXME: GCC should be able to do these expansions itself.
3328 (define_expand "abs<mode>2"
3330 (sign_extend:SI (match_operand:BW 1 "general_operand" "")))
3331 (set (match_dup 3) (abs:SI (match_dup 2)))
3332 (set (match_operand:BW 0 "register_operand" "")
3333 (subreg:BW (match_dup 3) 0))]
3335 "operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode);")
3337 (define_insn "clzsi2"
3338 [(set (match_operand:SI 0 "register_operand" "=r")
3339 (clz:SI (match_operand:SI 1 "register_operand" "r")))]
3342 [(set_attr "slottable" "yes")
3343 (set_attr "cc" "noov32")])
3345 (define_insn "bswapsi2"
3346 [(set (match_operand:SI 0 "register_operand" "=r")
3347 (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
3350 [(set_attr "slottable" "yes")
3351 (set_attr "cc" "noov32")])
3353 ;; This instruction swaps all bits in a register.
3354 ;; That means that the most significant bit is put in the place
3355 ;; of the least significant bit, and so on.
3357 (define_insn "cris_swap_bits"
3358 [(set (match_operand:SI 0 "register_operand" "=r")
3359 (unspec:SI [(match_operand:SI 1 "register_operand" "0")]
3360 CRIS_UNSPEC_SWAP_BITS))]
3363 [(set_attr "slottable" "yes")
3364 (set_attr "cc" "noov32")])
3366 ;; Implement ctz using two instructions, one for bit swap and one for clz.
3367 ;; Defines a scratch register to avoid clobbering input.
3369 (define_expand "ctzsi2"
3371 (match_operand:SI 1 "register_operand"))
3373 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_SWAP_BITS))
3374 (set (match_operand:SI 0 "register_operand")
3375 (clz:SI (match_dup 2)))]
3376 "TARGET_HAS_LZ && TARGET_HAS_SWAP"
3377 "operands[2] = gen_reg_rtx (SImode);")
3379 ;; Bound-insn. Defined to be the same as an unsigned minimum, which is an
3380 ;; operation supported by gcc. Used in casesi, but used now and then in
3383 (define_expand "uminsi3"
3384 [(set (match_operand:SI 0 "register_operand" "")
3385 (umin:SI (match_operand:SI 1 "register_operand" "")
3386 (match_operand:SI 2 "general_operand" "")))]
3389 if (MEM_P (operands[2]) && TARGET_V32)
3390 operands[2] = force_reg (SImode, operands[2]);
3393 (define_insn "*uminsi3_non_v32"
3394 [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
3395 (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
3396 (match_operand:SI 2 "general_operand" "r,Q>,g,!To")))]
3399 if (CONST_INT_P (operands[2]))
3401 /* Constant operands are zero-extended, so only 32-bit operands
3403 if (INTVAL (operands[2]) >= 0)
3405 if (INTVAL (operands[2]) < 256)
3406 return "bound.b %2,%0";
3408 if (INTVAL (operands[2]) < 65536)
3409 return "bound.w %2,%0";
3412 else if (which_alternative == 3)
3413 return "bound.d %2,%1,%0";
3415 return "bound.d %2,%0";
3417 [(set_attr "slottable" "yes,yes,no,no")])
3419 (define_insn "*uminsi3_v32"
3420 [(set (match_operand:SI 0 "register_operand" "=r,r")
3421 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
3422 (match_operand:SI 2 "nonmemory_operand" "r,i")))]
3425 if (GET_CODE (operands[2]) == CONST_INT)
3427 /* Constant operands are zero-extended, so only 32-bit operands
3429 if (INTVAL (operands[2]) >= 0)
3431 if (INTVAL (operands[2]) < 256)
3432 return "bound.b %2,%0";
3434 if (INTVAL (operands[2]) < 65536)
3435 return "bound.w %2,%0";
3439 return "bound.d %2,%0";
3441 [(set_attr "slottable" "yes,no")])
3443 ;; Jump and branch insns.
3447 (label_ref (match_operand 0 "" "")))]
3450 [(set_attr "slottable" "has_slot")])
3452 ;; Testcase gcc.c-torture/compile/991213-3.c fails if we allow a constant
3453 ;; here, since the insn is not recognized as an indirect jump by
3454 ;; jmp_uses_reg_or_mem used by computed_jump_p. Perhaps it is a kludge to
3455 ;; change from general_operand to nonimmediate_operand (at least the docs
3456 ;; should be changed), but then again the pattern is called indirect_jump.
3457 (define_expand "indirect_jump"
3458 [(set (pc) (match_operand:SI 0 "nonimmediate_operand"))]
3461 if (TARGET_V32 && MEM_P (operands[0]))
3462 operands[0] = force_reg (SImode, operands[0]);
3465 (define_insn "*indirect_jump_non_v32"
3466 [(set (pc) (match_operand:SI 0 "nonimmediate_operand" "rm"))]
3470 (define_insn "*indirect_jump_v32"
3471 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
3474 [(set_attr "slottable" "has_slot")])
3476 ;; Return insn. Used whenever the epilogue is very simple; if it is only
3477 ;; a single ret or jump [sp+]. No allocated stack space or saved
3478 ;; registers are allowed.
3479 ;; Note that for this pattern, although named, it is ok to check the
3480 ;; context of the insn in the test, not only compiler switches.
3482 (define_expand "return"
3484 "cris_simple_epilogue ()"
3485 "cris_expand_return (cris_return_address_on_stack ()); DONE;")
3487 (define_insn "*return_expanded"
3491 return cris_return_address_on_stack_for_return ()
3492 ? "jump [$sp+]" : "ret%#";
3494 [(set (attr "slottable")
3497 "(cris_return_address_on_stack_for_return ())")
3500 (const_string "has_return_slot")))])
3502 (define_expand "prologue"
3504 "TARGET_PROLOGUE_EPILOGUE"
3505 "cris_expand_prologue (); DONE;")
3507 ;; Note that the (return) from the expander itself is always the last
3508 ;; insn in the epilogue.
3509 (define_expand "epilogue"
3511 "TARGET_PROLOGUE_EPILOGUE"
3512 "cris_expand_epilogue (); DONE;")
3514 ;; Conditional branches.
3516 (define_expand "cbranch<mode>4"
3517 [(set (cc0) (compare
3518 (match_operand:BWD 1 "nonimmediate_operand")
3519 (match_operand:BWD 2 "general_operand")))
3521 (if_then_else (match_operator 0 "ordered_comparison_operator"
3522 [(cc0) (const_int 0)])
3523 (label_ref (match_operand 3 "" ""))
3528 (define_expand "cbranchdi4"
3530 (compare (match_operand:DI 1 "nonimmediate_operand" "")
3531 (match_operand:DI 2 "general_operand" "")))
3533 (if_then_else (match_operator 0 "ordered_comparison_operator"
3534 [(cc0) (const_int 0)])
3535 (label_ref (match_operand 3 "" ""))
3539 if (TARGET_V32 && !REG_P (operands[1]))
3540 operands[1] = force_reg (DImode, operands[1]);
3541 if (TARGET_V32 && MEM_P (operands[2]))
3542 operands[2] = force_reg (DImode, operands[2]);
3546 ;; We suffer from the same overflow-bit-gets-in-the-way problem as
3547 ;; e.g. m68k, so we have to check if overflow bit is set on all "signed"
3550 (define_insn "b<ncond:code>"
3552 (if_then_else (ncond (cc0)
3554 (label_ref (match_operand 0 "" ""))
3558 [(set_attr "slottable" "has_slot")])
3560 (define_insn "b<ocond:code>"
3562 (if_then_else (ocond (cc0)
3564 (label_ref (match_operand 0 "" ""))
3569 (cc_prev_status.flags & CC_NO_OVERFLOW)
3570 ? 0 : "b<CC> %l0%#";
3572 [(set_attr "slottable" "has_slot")])
3574 (define_insn "b<rcond:code>"
3576 (if_then_else (rcond (cc0)
3578 (label_ref (match_operand 0 "" ""))
3583 (cc_prev_status.flags & CC_NO_OVERFLOW)
3584 ? "b<oCC> %l0%#" : "b<CC> %l0%#";
3586 [(set_attr "slottable" "has_slot")])
3588 ;; Reversed anonymous patterns to the ones above, as mandated.
3590 (define_insn "*b<ncond:code>_reversed"
3592 (if_then_else (ncond (cc0)
3595 (label_ref (match_operand 0 "" ""))))]
3598 [(set_attr "slottable" "has_slot")])
3600 (define_insn "*b<ocond:code>_reversed"
3602 (if_then_else (ocond (cc0)
3605 (label_ref (match_operand 0 "" ""))))]
3609 (cc_prev_status.flags & CC_NO_OVERFLOW)
3610 ? 0 : "b<rCC> %l0%#";
3612 [(set_attr "slottable" "has_slot")])
3614 (define_insn "*b<rcond:code>_reversed"
3616 (if_then_else (rcond (cc0)
3619 (label_ref (match_operand 0 "" ""))))]
3623 (cc_prev_status.flags & CC_NO_OVERFLOW)
3624 ? "b<roCC> %l0%#" : "b<rCC> %l0%#";
3626 [(set_attr "slottable" "has_slot")])
3628 ;; Set on condition: sCC.
3630 (define_expand "cstoredi4"
3631 [(set (cc0) (compare
3632 (match_operand:DI 2 "nonimmediate_operand")
3633 (match_operand:DI 3 "general_operand")))
3634 (set (match_operand:SI 0 "register_operand")
3635 (match_operator:SI 1 "ordered_comparison_operator"
3636 [(cc0) (const_int 0)]))]
3639 if (TARGET_V32 && !REG_P (operands[2]))
3640 operands[2] = force_reg (DImode, operands[2]);
3641 if (TARGET_V32 && MEM_P (operands[3]))
3642 operands[3] = force_reg (DImode, operands[3]);
3645 (define_expand "cstore<mode>4"
3646 [(set (cc0) (compare
3647 (match_operand:BWD 2 "nonimmediate_operand")
3648 (match_operand:BWD 3 "general_operand")))
3649 (set (match_operand:SI 0 "register_operand")
3650 (match_operator:SI 1 "ordered_comparison_operator"
3651 [(cc0) (const_int 0)]))]
3655 ;; Like bCC, we have to check the overflow bit for
3656 ;; signed conditions.
3658 (define_insn "s<ncond:code>"
3659 [(set (match_operand:SI 0 "register_operand" "=r")
3660 (ncond:SI (cc0) (const_int 0)))]
3663 [(set_attr "slottable" "yes")
3664 (set_attr "cc" "none")])
3666 (define_insn "s<rcond:code>"
3667 [(set (match_operand:SI 0 "register_operand" "=r")
3668 (rcond:SI (cc0) (const_int 0)))]
3672 (cc_prev_status.flags & CC_NO_OVERFLOW)
3673 ? "s<oCC> %0" : "s<CC> %0";
3675 [(set_attr "slottable" "yes")
3676 (set_attr "cc" "none")])
3678 (define_insn "s<ocond:code>"
3679 [(set (match_operand:SI 0 "register_operand" "=r")
3680 (ocond:SI (cc0) (const_int 0)))]
3684 (cc_prev_status.flags & CC_NO_OVERFLOW)
3687 [(set_attr "slottable" "yes")
3688 (set_attr "cc" "none")])
3692 ;; We need to make these patterns "expand", since the real operand is
3693 ;; hidden in a (mem:QI ) inside operand[0] (call_value: operand[1]),
3694 ;; and cannot be checked if it were a "normal" pattern.
3695 ;; Note that "call" and "call_value" are *always* called with a
3696 ;; mem-operand for operand 0 and 1 respective. What happens for combined
3697 ;; instructions is a different issue.
3699 (define_expand "call"
3700 [(parallel [(call (match_operand:QI 0 "cris_mem_call_operand" "")
3701 (match_operand 1 "general_operand" ""))
3702 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3705 gcc_assert (MEM_P (operands[0]));
3707 cris_expand_pic_call_address (&operands[0]);
3710 ;; Accept *anything* as operand 1. Accept operands for operand 0 in
3711 ;; order of preference.
3713 (define_insn "*expanded_call_non_v32"
3714 [(call (mem:QI (match_operand:SI 0 "general_operand" "r,Q>,g"))
3715 (match_operand 1 "" ""))
3716 (clobber (reg:SI CRIS_SRP_REGNUM))]
3720 (define_insn "*expanded_call_v32"
3723 (match_operand:SI 0 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3724 (match_operand 1 "" ""))
3725 (clobber (reg:SI CRIS_SRP_REGNUM))]
3732 [(set_attr "slottable" "has_call_slot")])
3734 ;; Parallel when calculating and reusing address of indirect pointer
3735 ;; with simple offset. (Makes most sense with PIC.) It looks a bit
3736 ;; wrong not to have the clobber last, but that's the way combine
3737 ;; generates it (except it doesn' look into the *inner* mem, so this
3738 ;; just matches a peephole2). FIXME: investigate that.
3739 (define_insn "*expanded_call_side"
3742 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "%r, r,r")
3743 (match_operand:SI 1 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3744 (match_operand 2 "" ""))
3745 (clobber (reg:SI CRIS_SRP_REGNUM))
3746 (set (match_operand:SI 3 "register_operand" "=*0,r,r")
3747 (plus:SI (match_dup 0)
3749 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3752 (define_expand "call_value"
3753 [(parallel [(set (match_operand 0 "" "")
3754 (call (match_operand:QI 1 "cris_mem_call_operand" "")
3755 (match_operand 2 "" "")))
3756 (clobber (reg:SI CRIS_SRP_REGNUM))])]
3759 gcc_assert (MEM_P (operands[1]));
3761 cris_expand_pic_call_address (&operands[1]);
3764 ;; Accept *anything* as operand 2. The validity other than "general" of
3765 ;; operand 0 will be checked elsewhere. Accept operands for operand 1 in
3766 ;; order of preference (Q includes r, but r is shorter, faster).
3767 ;; We also accept a PLT symbol. We output it as [rPIC+sym:GOTPLT] rather
3768 ;; than requiring getting rPIC + sym:PLT into a register.
3770 (define_insn "*expanded_call_value_non_v32"
3771 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3772 (call (mem:QI (match_operand:SI 1 "general_operand" "r,Q>,g"))
3773 (match_operand 2 "" "")))
3774 (clobber (reg:SI CRIS_SRP_REGNUM))]
3777 [(set_attr "cc" "clobber")])
3779 ;; See similar call special-case.
3780 (define_insn "*expanded_call_value_side"
3781 [(set (match_operand 0 "nonimmediate_operand" "=g,g,g")
3785 (plus:SI (match_operand:SI 1 "cris_bdap_operand" "%r, r,r")
3786 (match_operand:SI 2 "cris_bdap_operand" "r>Rn,r,>Rn"))))
3787 (match_operand 3 "" "")))
3788 (clobber (reg:SI CRIS_SRP_REGNUM))
3789 (set (match_operand:SI 4 "register_operand" "=*1,r,r")
3790 (plus:SI (match_dup 1)
3792 "!TARGET_AVOID_GOTPLT && !TARGET_V32"
3794 [(set_attr "cc" "clobber")])
3796 (define_insn "*expanded_call_value_v32"
3798 (match_operand 0 "nonimmediate_operand" "=g,g,g,g")
3801 (match_operand:SI 1 "cris_nonmemory_operand_or_callable_symbol" "n,r,U,i"))
3802 (match_operand 2 "" "")))
3803 (clobber (reg:SI 16))]
3810 [(set_attr "cc" "clobber")
3811 (set_attr "slottable" "has_call_slot")])
3813 ;; Used in debugging. No use for the direct pattern; unfilled
3814 ;; delayed-branches are taken care of by other means.
3820 [(set_attr "cc" "none")])
3822 ;; We need to stop accesses to the stack after the memory is
3823 ;; deallocated. Unfortunately, reorg doesn't look at naked clobbers,
3824 ;; e.g. (insn ... (clobber (mem:BLK (stack_pointer_rtx)))) and we don't
3825 ;; want to use a naked (unspec_volatile) as that would stop any
3826 ;; scheduling in the epilogue. Hence we model it as a "real" insn that
3827 ;; sets the memory in an unspecified manner. FIXME: Unfortunately it
3828 ;; still has the effect of an unspec_volatile.
3829 (define_insn "cris_frame_deallocated_barrier"
3830 [(set (mem:BLK (reg:SI CRIS_SP_REGNUM))
3831 (unspec:BLK [(const_int 0)] CRIS_UNSPEC_FRAME_DEALLOC))]
3834 [(set_attr "length" "0")])
3836 ;; We expand on casesi so we can use "bound" and "add offset fetched from
3837 ;; a table to pc" (adds.w [pc+%0.w],pc).
3839 ;; Note: if you change the "parallel" (or add anything after it) in
3840 ;; this expansion, you must change the macro ASM_OUTPUT_CASE_END
3841 ;; accordingly, to add the default case at the end of the jump-table.
3843 (define_expand "cris_casesi_non_v32"
3844 [(set (match_dup 5) (match_operand:SI 0 "general_operand" ""))
3846 (minus:SI (match_dup 5)
3847 (match_operand:SI 1 "const_int_operand" "n")))
3849 (umin:SI (match_dup 6)
3850 (match_operand:SI 2 "const_int_operand" "n")))
3854 (ltu (match_dup 7) (match_dup 2))
3855 (plus:SI (sign_extend:SI
3857 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3860 (label_ref (match_operand 4 "" ""))))
3861 (use (label_ref (match_operand 3 "" "")))])]
3864 operands[2] = plus_constant (operands[2], 1);
3865 operands[5] = gen_reg_rtx (SImode);
3866 operands[6] = gen_reg_rtx (SImode);
3867 operands[7] = gen_reg_rtx (SImode);
3870 ;; FIXME: Check effect of not JUMP_TABLES_IN_TEXT_SECTION.
3871 (define_expand "cris_casesi_v32"
3872 [(set (match_dup 5) (match_operand:SI 0 "general_operand"))
3874 (minus:SI (match_dup 5)
3875 (match_operand:SI 1 "const_int_operand")))
3877 (umin:SI (match_dup 6)
3878 (match_operand:SI 2 "const_int_operand")))
3879 (set (match_dup 8) (match_dup 11))
3881 (plus:SI (mult:SI (match_dup 7) (const_int 2))
3884 (plus:SI (sign_extend:SI (mem:HI (match_dup 9)))
3889 (ltu (unspec [(const_int 0)] CRIS_UNSPEC_CASESI) (match_dup 2))
3891 (label_ref (match_operand 4 "" ""))))
3892 (use (label_ref (match_dup 3)))])]
3896 rtx xlabel = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
3897 for (i = 5; i <= 10; i++)
3898 operands[i] = gen_reg_rtx (SImode);
3899 operands[2] = plus_constant (operands[2], 1);
3901 /* Don't forget to decorate labels too, for PIC. */
3902 operands[11] = flag_pic
3903 ? gen_rtx_CONST (Pmode,
3904 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, xlabel),
3909 (define_expand "casesi"
3910 [(match_operand:SI 0 "general_operand")
3911 (match_operand:SI 1 "const_int_operand")
3912 (match_operand:SI 2 "const_int_operand")
3913 (match_operand 3 "" "")
3914 (match_operand 4 "" "")]
3918 emit_insn (gen_cris_casesi_v32 (operands[0], operands[1], operands[2],
3919 operands[3], operands[4]));
3921 emit_insn (gen_cris_casesi_non_v32 (operands[0], operands[1], operands[2],
3922 operands[3], operands[4]));
3926 ;; Split-patterns. Some of them have modes unspecified. This
3927 ;; should always be ok; if for no other reason sparc.md has it as
3930 ;; When register_operand is specified for an operand, we can get a
3931 ;; subreg as well (Axis-990331), so don't just assume that REG_P is true
3932 ;; for a register_operand and that REGNO can be used as is. It is best to
3933 ;; guard with REG_P, unless it is worth it to adjust for the subreg case.
3935 ;; op [rx + 0],ry,rz
3936 ;; The index to rx is optimized into zero, and gone.
3938 ;; First, recognize bound [rx],ry,rz; where [rx] is zero-extended,
3939 ;; and add/sub [rx],ry,rz, with zero or sign-extend on [rx].
3943 ;; Lose if rz=ry or rx=rz.
3944 ;; Call this op-extend-split.
3945 ;; Do not match for V32; the addo and addi shouldn't be split
3949 [(set (match_operand 0 "register_operand" "")
3951 4 "cris_operand_extend_operator"
3952 [(match_operand 1 "register_operand" "")
3954 3 "cris_extend_operator"
3955 [(match_operand 2 "memory_operand" "")])]))]
3957 && REG_P (operands[0])
3958 && REG_P (operands[1])
3959 && REGNO (operands[1]) != REGNO (operands[0])
3960 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3961 && REG_P (XEXP (operands[2], 0))
3962 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
3968 (match_op_dup 3 [(match_dup 2)])]))]
3971 ;; As op-extend-split, but recognize and split op [rz],ry,rz into
3974 ;; Do this for plus or bound only, being commutative operations, since we
3975 ;; have swapped the operands.
3976 ;; Call this op-extend-split-rx=rz
3979 [(set (match_operand 0 "register_operand" "")
3981 4 "cris_plus_or_bound_operator"
3982 [(match_operand 1 "register_operand" "")
3984 3 "cris_extend_operator"
3985 [(match_operand 2 "memory_operand" "")])]))]
3987 && REG_P (operands[0])
3988 && REG_P (operands[1])
3989 && REGNO (operands[1]) != REGNO (operands[0])
3990 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
3991 && REG_P (XEXP (operands[2], 0))
3992 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
3994 (match_op_dup 3 [(match_dup 2)]))
4001 ;; As the op-extend-split, but swapped operands, and only for
4002 ;; plus or bound, being the commutative extend-operators. FIXME: Why is
4003 ;; this needed? Is it?
4004 ;; Call this op-extend-split-swapped
4007 [(set (match_operand 0 "register_operand" "")
4009 4 "cris_plus_or_bound_operator"
4011 3 "cris_extend_operator"
4012 [(match_operand 2 "memory_operand" "")])
4013 (match_operand 1 "register_operand" "")]))]
4015 && REG_P (operands[0])
4016 && REG_P (operands[1])
4017 && REGNO (operands[1]) != REGNO (operands[0])
4018 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4019 && REG_P (XEXP (operands[2], 0))
4020 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4026 (match_op_dup 3 [(match_dup 2)])]))]
4029 ;; As op-extend-split-rx=rz, but swapped operands, only for plus or
4030 ;; bound. Call this op-extend-split-swapped-rx=rz.
4033 [(set (match_operand 0 "register_operand" "")
4035 4 "cris_plus_or_bound_operator"
4037 3 "cris_extend_operator"
4038 [(match_operand 2 "memory_operand" "")])
4039 (match_operand 1 "register_operand" "")]))]
4041 && REG_P (operands[0])
4042 && REG_P (operands[1])
4043 && REGNO (operands[1]) != REGNO (operands[0])
4044 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4045 && REG_P (XEXP (operands[2], 0))
4046 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4048 (match_op_dup 3 [(match_dup 2)]))
4055 ;; As op-extend-split, but the mem operand is not extended.
4057 ;; op [rx],ry,rz changed into
4060 ;; lose if ry=rz or rx=rz
4061 ;; Call this op-extend.
4064 [(set (match_operand 0 "register_operand" "")
4066 3 "cris_orthogonal_operator"
4067 [(match_operand 1 "register_operand" "")
4068 (match_operand 2 "memory_operand" "")]))]
4070 && REG_P (operands[0])
4071 && REG_P (operands[1])
4072 && REGNO (operands[1]) != REGNO (operands[0])
4073 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4074 && REG_P (XEXP (operands[2], 0))
4075 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4084 ;; As op-extend-split-rx=rz, non-extended.
4085 ;; Call this op-split-rx=rz
4088 [(set (match_operand 0 "register_operand" "")
4090 3 "cris_commutative_orth_op"
4091 [(match_operand 2 "memory_operand" "")
4092 (match_operand 1 "register_operand" "")]))]
4094 && REG_P (operands[0])
4095 && REG_P (operands[1])
4096 && REGNO (operands[1]) != REGNO (operands[0])
4097 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4098 && REG_P (XEXP (operands[2], 0))
4099 && REGNO (XEXP (operands[2], 0)) != REGNO (operands[0])"
4108 ;; As op-extend-split-swapped, nonextended.
4109 ;; Call this op-split-swapped.
4112 [(set (match_operand 0 "register_operand" "")
4114 3 "cris_commutative_orth_op"
4115 [(match_operand 1 "register_operand" "")
4116 (match_operand 2 "memory_operand" "")]))]
4118 && REG_P (operands[0]) && REG_P (operands[1])
4119 && REGNO (operands[1]) != REGNO (operands[0])
4120 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4121 && REG_P (XEXP (operands[2], 0))
4122 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4131 ;; As op-extend-split-swapped-rx=rz, non-extended.
4132 ;; Call this op-split-swapped-rx=rz.
4135 [(set (match_operand 0 "register_operand" "")
4137 3 "cris_orthogonal_operator"
4138 [(match_operand 2 "memory_operand" "")
4139 (match_operand 1 "register_operand" "")]))]
4141 && REG_P (operands[0]) && REG_P (operands[1])
4142 && REGNO (operands[1]) != REGNO (operands[0])
4143 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4144 && REG_P (XEXP (operands[2], 0))
4145 && REGNO (XEXP (operands[2], 0)) == REGNO (operands[0])"
4154 ;; Splits for all cases in side-effect insns where (possibly after reload
4155 ;; and register allocation) rx and ry in [rx=ry+i] are equal.
4157 ;; move.S1 [rx=rx+rz.S2],ry
4161 [(set (match_operand 0 "register_operand" "")
4165 (mult:SI (match_operand:SI 1 "register_operand" "")
4166 (match_operand:SI 2 "const_int_operand" ""))
4167 (match_operand:SI 3 "register_operand" ""))]))
4168 (set (match_operand:SI 4 "register_operand" "")
4169 (plus:SI (mult:SI (match_dup 1)
4172 "REG_P (operands[3]) && REG_P (operands[4])
4173 && REGNO (operands[3]) == REGNO (operands[4])"
4174 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4176 (set (match_dup 0) (match_dup 5))]
4177 "operands[5] = replace_equiv_address (operands[6], operands[3]);")
4179 ;; move.S1 [rx=rx+i],ry
4183 [(set (match_operand 0 "register_operand" "")
4186 [(plus:SI (match_operand:SI 1 "cris_bdap_operand" "")
4187 (match_operand:SI 2 "cris_bdap_operand" ""))]))
4188 (set (match_operand:SI 3 "register_operand" "")
4189 (plus:SI (match_dup 1)
4191 "(rtx_equal_p (operands[3], operands[1])
4192 || rtx_equal_p (operands[3], operands[2]))"
4193 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4194 (set (match_dup 0) (match_dup 4))]
4196 operands[4] = replace_equiv_address (operands[5], operands[3]);
4197 cris_order_for_addsi3 (operands, 1);
4200 ;; move.S1 ry,[rx=rx+rz.S2]
4204 [(set (match_operator
4207 (mult:SI (match_operand:SI 0 "register_operand" "")
4208 (match_operand:SI 1 "const_int_operand" ""))
4209 (match_operand:SI 2 "register_operand" ""))])
4210 (match_operand 3 "register_operand" ""))
4211 (set (match_operand:SI 4 "register_operand" "")
4212 (plus:SI (mult:SI (match_dup 0)
4215 "REG_P (operands[2]) && REG_P (operands[4])
4216 && REGNO (operands[4]) == REGNO (operands[2])"
4217 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4219 (set (match_dup 5) (match_dup 3))]
4220 "operands[5] = replace_equiv_address (operands[6], operands[4]);")
4222 ;; move.S1 ry,[rx=rx+i]
4226 [(set (match_operator
4228 [(plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4229 (match_operand:SI 1 "cris_bdap_operand" ""))])
4230 (match_operand 2 "register_operand" ""))
4231 (set (match_operand:SI 3 "register_operand" "")
4232 (plus:SI (match_dup 0)
4234 "(rtx_equal_p (operands[3], operands[0])
4235 || rtx_equal_p (operands[3], operands[1]))"
4236 [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1)))
4237 (set (match_dup 5) (match_dup 2))]
4239 operands[5] = replace_equiv_address (operands[6], operands[3]);
4240 cris_order_for_addsi3 (operands, 0);
4243 ;; clear.[bwd] [rx=rx+rz.S2]
4247 [(set (mem:BWD (plus:SI
4248 (mult:SI (match_operand:SI 0 "register_operand" "")
4249 (match_operand:SI 1 "const_int_operand" ""))
4250 (match_operand:SI 2 "register_operand" "")))
4252 (set (match_operand:SI 3 "register_operand" "")
4253 (plus:SI (mult:SI (match_dup 0)
4256 "REG_P (operands[2]) && REG_P (operands[3])
4257 && REGNO (operands[3]) == REGNO (operands[2])"
4258 [(set (match_dup 3) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
4260 (set (mem:BWD (match_dup 3)) (const_int 0))]
4263 ;; clear.[bwd] [rx=rx+i]
4268 (plus:SI (match_operand:SI 0 "cris_bdap_operand" "")
4269 (match_operand:SI 1 "cris_bdap_operand" "")))
4271 (set (match_operand:SI 2 "register_operand" "")
4272 (plus:SI (match_dup 0)
4274 "(rtx_equal_p (operands[0], operands[2])
4275 || rtx_equal_p (operands[2], operands[1]))"
4276 [(set (match_dup 2) (plus:SI (match_dup 0) (match_dup 1)))
4277 (set (mem:BWD (match_dup 2)) (const_int 0))]
4278 "cris_order_for_addsi3 (operands, 0);")
4280 ;; mov(s|u).S1 [rx=rx+rz.S2],ry
4284 [(set (match_operand 0 "register_operand" "")
4286 5 "cris_extend_operator"
4288 (mult:SI (match_operand:SI 1 "register_operand" "")
4289 (match_operand:SI 2 "const_int_operand" ""))
4290 (match_operand:SI 3 "register_operand" "")))]))
4291 (set (match_operand:SI 4 "register_operand" "")
4292 (plus:SI (mult:SI (match_dup 1)
4295 "REG_P (operands[3])
4296 && REG_P (operands[4])
4297 && REGNO (operands[3]) == REGNO (operands[4])"
4298 [(set (match_dup 4) (plus:SI (mult:SI (match_dup 1) (match_dup 2))
4300 (set (match_dup 0) (match_op_dup 5 [(match_dup 6)]))]
4301 "operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);")
4303 ;; mov(s|u).S1 [rx=rx+i],ry
4307 [(set (match_operand 0 "register_operand" "")
4309 4 "cris_extend_operator"
4311 (match_operand:SI 1 "cris_bdap_operand" "")
4312 (match_operand:SI 2 "cris_bdap_operand" "")))]))
4313 (set (match_operand:SI 3 "register_operand" "")
4314 (plus:SI (match_dup 1)
4316 "(rtx_equal_p (operands[1], operands[3])
4317 || rtx_equal_p (operands[2], operands[3]))"
4318 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))
4319 (set (match_dup 0) (match_op_dup 4 [(match_dup 5)]))]
4321 operands[5] = replace_equiv_address (XEXP (operands[4], 0), operands[3]);
4322 cris_order_for_addsi3 (operands, 1);
4325 ;; op.S1 [rx=rx+i],ry
4329 [(set (match_operand 0 "register_operand" "")
4331 5 "cris_orthogonal_operator"
4332 [(match_operand 1 "register_operand" "")
4334 (match_operand:SI 2 "cris_bdap_operand" "")
4335 (match_operand:SI 3 "cris_bdap_operand" "")))]))
4336 (set (match_operand:SI 4 "register_operand" "")
4337 (plus:SI (match_dup 2)
4339 "(rtx_equal_p (operands[4], operands[2])
4340 || rtx_equal_p (operands[4], operands[3]))"
4341 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4342 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 6)]))]
4344 operands[6] = replace_equiv_address (XEXP (operands[5], 1), operands[4]);
4345 cris_order_for_addsi3 (operands, 2);
4348 ;; op.S1 [rx=rx+rz.S2],ry
4352 [(set (match_operand 0 "register_operand" "")
4354 6 "cris_orthogonal_operator"
4355 [(match_operand 1 "register_operand" "")
4357 (mult:SI (match_operand:SI 2 "register_operand" "")
4358 (match_operand:SI 3 "const_int_operand" ""))
4359 (match_operand:SI 4 "register_operand" "")))]))
4360 (set (match_operand:SI 5 "register_operand" "")
4361 (plus:SI (mult:SI (match_dup 2)
4364 "REG_P (operands[4])
4365 && REG_P (operands[5])
4366 && REGNO (operands[5]) == REGNO (operands[4])"
4367 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4369 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 7)]))]
4370 "operands[7] = replace_equiv_address (XEXP (operands[6], 1), operands[5]);")
4372 ;; op.S1 [rx=rx+rz.S2],ry (swapped)
4376 [(set (match_operand 0 "register_operand" "")
4378 6 "cris_commutative_orth_op"
4380 (mult:SI (match_operand:SI 2 "register_operand" "")
4381 (match_operand:SI 3 "const_int_operand" ""))
4382 (match_operand:SI 4 "register_operand" "")))
4383 (match_operand 1 "register_operand" "")]))
4384 (set (match_operand:SI 5 "register_operand" "")
4385 (plus:SI (mult:SI (match_dup 2)
4388 "REG_P (operands[4])
4389 && REG_P (operands[5])
4390 && REGNO (operands[5]) == REGNO (operands[4])"
4391 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4393 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4394 "operands[7] = replace_equiv_address (XEXP (operands[6], 0), operands[5]);")
4396 ;; op.S1 [rx=rx+i],ry (swapped)
4400 [(set (match_operand 0 "register_operand" "")
4402 5 "cris_commutative_orth_op"
4404 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4405 (match_operand:SI 3 "cris_bdap_operand" "")))
4406 (match_operand 1 "register_operand" "")]))
4407 (set (match_operand:SI 4 "register_operand" "")
4408 (plus:SI (match_dup 2)
4410 "(rtx_equal_p (operands[4], operands[2])
4411 || rtx_equal_p (operands[4], operands[3]))"
4412 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4413 (set (match_dup 0) (match_op_dup 5 [(match_dup 6) (match_dup 1)]))]
4415 operands[6] = replace_equiv_address (XEXP (operands[5], 0), operands[4]);
4416 cris_order_for_addsi3 (operands, 2);
4419 ;; op(s|u).S1 [rx=rx+rz.S2],ry
4423 [(set (match_operand 0 "register_operand" "")
4425 6 "cris_operand_extend_operator"
4426 [(match_operand 1 "register_operand" "")
4428 7 "cris_extend_operator"
4430 (mult:SI (match_operand:SI 2 "register_operand" "")
4431 (match_operand:SI 3 "const_int_operand" ""))
4432 (match_operand:SI 4 "register_operand" "")))])]))
4433 (set (match_operand:SI 5 "register_operand" "")
4434 (plus:SI (mult:SI (match_dup 2)
4437 "REG_P (operands[4])
4438 && REG_P (operands[5])
4439 && REGNO (operands[5]) == REGNO (operands[4])"
4440 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4442 (set (match_dup 0) (match_op_dup 6 [(match_dup 1) (match_dup 8)]))]
4443 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[7]), GET_MODE (operands[7]),
4444 replace_equiv_address (XEXP (operands[7], 0),
4447 ;; op(s|u).S1 [rx=rx+i],ry
4451 [(set (match_operand 0 "register_operand" "")
4453 5 "cris_operand_extend_operator"
4454 [(match_operand 1 "register_operand" "")
4456 6 "cris_extend_operator"
4458 (plus:SI (match_operand:SI 2 "cris_bdap_operand" "")
4459 (match_operand:SI 3 "cris_bdap_operand" "")
4461 (set (match_operand:SI 4 "register_operand" "")
4462 (plus:SI (match_dup 2)
4464 "(rtx_equal_p (operands[4], operands[2])
4465 || rtx_equal_p (operands[4], operands[3]))"
4466 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4467 (set (match_dup 0) (match_op_dup 5 [(match_dup 1) (match_dup 7)]))]
4469 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4470 replace_equiv_address (XEXP (operands[6], 0),
4472 cris_order_for_addsi3 (operands, 2);
4475 ;; op(s|u).S1 [rx=rx+rz.S2],ry (swapped, plus or bound)
4479 [(set (match_operand 0 "register_operand" "")
4481 7 "cris_plus_or_bound_operator"
4483 6 "cris_extend_operator"
4485 (mult:SI (match_operand:SI 2 "register_operand" "")
4486 (match_operand:SI 3 "const_int_operand" ""))
4487 (match_operand:SI 4 "register_operand" "")))])
4488 (match_operand 1 "register_operand" "")]))
4489 (set (match_operand:SI 5 "register_operand" "")
4490 (plus:SI (mult:SI (match_dup 2)
4493 "REG_P (operands[4]) && REG_P (operands[5])
4494 && REGNO (operands[5]) == REGNO (operands[4])"
4495 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 2) (match_dup 3))
4497 (set (match_dup 0) (match_op_dup 6 [(match_dup 8) (match_dup 1)]))]
4498 "operands[8] = gen_rtx_fmt_e (GET_CODE (operands[6]), GET_MODE (operands[6]),
4499 replace_equiv_address (XEXP (operands[6], 0),
4502 ;; op(s|u).S1 [rx=rx+i],ry (swapped, plus or bound)
4506 [(set (match_operand 0 "register_operand" "")
4508 6 "cris_plus_or_bound_operator"
4510 5 "cris_extend_operator"
4512 (match_operand:SI 2 "cris_bdap_operand" "")
4513 (match_operand:SI 3 "cris_bdap_operand" "")))])
4514 (match_operand 1 "register_operand" "")]))
4515 (set (match_operand:SI 4 "register_operand" "")
4516 (plus:SI (match_dup 2)
4518 "(rtx_equal_p (operands[4], operands[2])
4519 || rtx_equal_p (operands[4], operands[3]))"
4520 [(set (match_dup 4) (plus:SI (match_dup 2) (match_dup 3)))
4521 (set (match_dup 0) (match_op_dup 6 [(match_dup 7) (match_dup 1)]))]
4523 operands[7] = gen_rtx_fmt_e (GET_CODE (operands[5]), GET_MODE (operands[5]),
4524 replace_equiv_address (XEXP (operands[5], 0),
4526 cris_order_for_addsi3 (operands, 2);
4529 ;; Splits for addressing prefixes that have no side-effects, so we can
4530 ;; fill a delay slot. Never split if we lose something, though.
4533 ;; move [indirect_ref],rx
4534 ;; where indirect ref = {const, [r+], [r]}, it costs as much as
4535 ;; move indirect_ref,rx
4537 ;; Take care not to allow indirect_ref = register.
4539 ;; We're not allowed to generate copies of registers with different mode
4540 ;; until after reload; copying pseudos upsets reload. CVS as of
4541 ;; 2001-08-24, unwind-dw2-fde.c, _Unwind_Find_FDE ICE in
4542 ;; cselib_invalidate_regno.
4544 (define_split ; indir_to_reg_split
4545 [(set (match_operand 0 "register_operand" "")
4546 (match_operand 1 "indirect_operand" ""))]
4548 && REG_P (operands[0])
4549 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4550 && (MEM_P (XEXP (operands[1], 0)) || CONSTANT_P (XEXP (operands[1], 0)))
4551 && REGNO (operands[0]) < CRIS_LAST_GENERAL_REGISTER"
4552 [(set (match_dup 2) (match_dup 4))
4553 (set (match_dup 0) (match_dup 3))]
4554 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4555 operands[3] = replace_equiv_address (operands[1], operands[2]);
4556 operands[4] = XEXP (operands[1], 0);")
4558 ;; As the above, but MOVS and MOVU.
4561 [(set (match_operand 0 "register_operand" "")
4563 4 "cris_extend_operator"
4564 [(match_operand 1 "indirect_operand" "")]))]
4566 && REG_P (operands[0])
4567 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
4568 && (MEM_P (XEXP (operands[1], 0))
4569 || CONSTANT_P (XEXP (operands[1], 0)))"
4570 [(set (match_dup 2) (match_dup 5))
4571 (set (match_dup 0) (match_op_dup 4 [(match_dup 3)]))]
4572 "operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
4573 operands[3] = replace_equiv_address (XEXP (operands[4], 0), operands[2]);
4574 operands[5] = XEXP (operands[1], 0);")
4576 ;; Various peephole optimizations.
4578 ;; Watch out: when you exchange one set of instructions for another, the
4579 ;; condition codes setting must be the same, or you have to CC_INIT or
4580 ;; whatever is appropriate, in the pattern before you emit the
4581 ;; assembly text. This is best done here, not in cris_notice_update_cc,
4582 ;; to keep changes local to their cause.
4584 ;; Do not add patterns that you do not know will be matched.
4585 ;; Please also add a self-contained testcase.
4587 ;; We have trouble with and:s and shifts. Maybe something is broken in
4588 ;; gcc? Or it could just be that bit-field insn expansion is a bit
4589 ;; suboptimal when not having extzv insns.
4590 ;; Testcase for the following four peepholes: gcc.dg/cris-peep2-xsrand.c
4592 (define_peephole2 ; asrandb (peephole casesi+31)
4593 [(set (match_operand:SI 0 "register_operand" "")
4594 (ashiftrt:SI (match_dup 0)
4595 (match_operand:SI 1 "const_int_operand" "")))
4597 (and:SI (match_dup 0)
4598 (match_operand 2 "const_int_operand" "")))]
4599 "INTVAL (operands[2]) > 31
4600 && INTVAL (operands[2]) < 255
4601 && INTVAL (operands[1]) > 23
4602 /* Check that the and-operation enables us to use logical-shift. */
4603 && (INTVAL (operands[2])
4604 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4605 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4606 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4607 ;; FIXME: CC0 is valid except for the M bit.
4609 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4610 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4613 (define_peephole2 ; asrandw (peephole casesi+32)
4614 [(set (match_operand:SI 0 "register_operand" "")
4615 (ashiftrt:SI (match_dup 0)
4616 (match_operand:SI 1 "const_int_operand" "")))
4618 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4619 "INTVAL (operands[2]) > 31
4620 && INTVAL (operands[2]) < 65535
4621 && INTVAL (operands[2]) != 255
4622 && INTVAL (operands[1]) > 15
4623 /* Check that the and-operation enables us to use logical-shift. */
4624 && (INTVAL (operands[2])
4625 & ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
4626 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4627 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4628 ;; FIXME: CC0 is valid except for the M bit.
4630 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4631 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4634 (define_peephole2 ; lsrandb (peephole casesi+33)
4635 [(set (match_operand:SI 0 "register_operand" "")
4636 (lshiftrt:SI (match_dup 0)
4637 (match_operand:SI 1 "const_int_operand" "")))
4639 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4640 "INTVAL (operands[2]) > 31
4641 && INTVAL (operands[2]) < 255
4642 && INTVAL (operands[1]) > 23"
4643 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4644 (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
4645 ;; FIXME: CC0 is valid except for the M bit.
4647 operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
4648 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
4651 (define_peephole2 ; lsrandw (peephole casesi+34)
4652 [(set (match_operand:SI 0 "register_operand" "")
4653 (lshiftrt:SI (match_dup 0)
4654 (match_operand:SI 1 "const_int_operand" "")))
4656 (and:SI (match_dup 0) (match_operand 2 "const_int_operand" "")))]
4657 "INTVAL (operands[2]) > 31 && INTVAL (operands[2]) < 65535
4658 && INTVAL (operands[2]) != 255
4659 && INTVAL (operands[1]) > 15"
4660 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
4661 (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
4662 ;; FIXME: CC0 is valid except for the M bit.
4664 operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
4665 operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
4673 ;; move [rx=rx+n],ry
4674 ;; when -128 <= n <= 127.
4675 ;; This will reduce the size of the assembler code for n = [-128..127],
4676 ;; and speed up accordingly. Don't match if the previous insn is
4677 ;; (set rx rz) because that combination is matched by another peephole.
4678 ;; No stable test-case.
4680 (define_peephole2 ; moversideqi (peephole casesi+35)
4681 [(set (match_operand:SI 0 "register_operand" "")
4682 (plus:SI (match_operand:SI 1 "register_operand" "")
4683 (match_operand:SI 2 "const_int_operand" "")))
4684 (set (match_operand 3 "register_operand" "")
4685 (match_operator 4 "cris_mem_op" [(match_dup 0)]))]
4686 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4687 && REGNO (operands[3]) != REGNO (operands[0])
4688 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4689 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4690 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4691 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4692 && TARGET_SIDE_EFFECT_PREFIXES"
4694 [(set (match_dup 3) (match_dup 5))
4695 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4696 ;; Checking the previous insn is a bit too awkward for the condition.
4698 rtx prev = prev_nonnote_insn (curr_insn);
4699 if (prev != NULL_RTX)
4701 rtx set = single_set (prev);
4703 && REG_S_P (SET_DEST (set))
4704 && REGNO (SET_DEST (set)) == REGNO (operands[0])
4705 && REG_S_P (SET_SRC (set)))
4709 = replace_equiv_address (operands[4],
4710 gen_rtx_PLUS (SImode,
4711 operands[1], operands[2]));
4714 ;; Vice versa: move ry,[rx=rx+n]
4716 (define_peephole2 ; movemsideqi (peephole casesi+36)
4717 [(set (match_operand:SI 0 "register_operand" "")
4718 (plus:SI (match_operand:SI 1 "register_operand" "")
4719 (match_operand:SI 2 "const_int_operand" "")))
4720 (set (match_operator 3 "cris_mem_op" [(match_dup 0)])
4721 (match_operand 4 "register_operand" ""))]
4722 "GET_MODE_SIZE (GET_MODE (operands[4])) <= UNITS_PER_WORD
4723 && REGNO (operands[4]) != REGNO (operands[0])
4724 && (BASE_P (operands[1]) || BASE_P (operands[2]))
4725 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4726 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4727 && (INTVAL (operands[2]) >= -128 && INTVAL (operands[2]) < 128)
4728 && TARGET_SIDE_EFFECT_PREFIXES"
4730 [(set (match_dup 5) (match_dup 4))
4731 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4733 = replace_equiv_address (operands[3],
4734 gen_rtx_PLUS (SImode,
4735 operands[1], operands[2]));")
4737 ;; As above, change:
4741 ;; op.d [rx=rx+n],ry
4742 ;; Saves when n = [-128..127].
4744 ;; Splitting and joining combinations for side-effect modes are slightly
4745 ;; out of hand. They probably will not save the time they take typing in,
4746 ;; not to mention the bugs that creep in. FIXME: Get rid of as many of
4747 ;; the splits and peepholes as possible.
4748 ;; No stable test-case.
4750 (define_peephole2 ; mover2side (peephole casesi+37)
4751 [(set (match_operand:SI 0 "register_operand" "")
4752 (plus:SI (match_operand:SI 1 "register_operand" "")
4753 (match_operand:SI 2 "const_int_operand" "")))
4754 (set (match_operand 3 "register_operand" "")
4755 (match_operator 4 "cris_orthogonal_operator"
4758 5 "cris_mem_op" [(match_dup 0)])]))]
4759 ;; FIXME: What about DFmode?
4760 ;; Change to GET_MODE_SIZE (GET_MODE (operands[3])) <= UNITS_PER_WORD?
4761 "GET_MODE (operands[3]) != DImode
4762 && REGNO (operands[0]) != REGNO (operands[3])
4763 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')
4764 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'N')
4765 && INTVAL (operands[2]) >= -128
4766 && INTVAL (operands[2]) <= 127
4767 && TARGET_SIDE_EFFECT_PREFIXES"
4769 [(set (match_dup 3) (match_op_dup 4 [(match_dup 3) (match_dup 6)]))
4770 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])]
4772 = replace_equiv_address (operands[5],
4773 gen_rtx_PLUS (SImode,
4774 operands[1], operands[2]));")
4776 ;; Sometimes, for some reason the pattern
4780 ;; will occur. Solve this, and likewise for to-memory.
4781 ;; No stable test-case.
4783 (define_peephole2 ; moverside (peephole casesi+38)
4784 [(set (match_operand:SI 0 "register_operand" "")
4785 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4787 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4788 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4789 (set (match_operand 4 "register_operand" "")
4790 (match_operator 5 "cris_mem_op" [(match_dup 0)]))]
4791 "(rtx_equal_p (operands[2], operands[0])
4792 || rtx_equal_p (operands[3], operands[0]))
4793 && cris_side_effect_mode_ok (PLUS, operands, 0,
4794 (REG_S_P (operands[1])
4796 : (rtx_equal_p (operands[2], operands[0])
4798 (! REG_S_P (operands[1])
4800 : (rtx_equal_p (operands[2], operands[0])
4804 [(set (match_dup 4) (match_dup 6))
4805 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4808 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4810 /* Make sure we have canonical RTX so we match the insn pattern -
4811 not a constant in the first operand. We also require the order
4812 (plus reg mem) to match the final pattern. */
4813 if (CONSTANT_P (otherop) || MEM_P (otherop))
4815 operands[7] = operands[1];
4816 operands[8] = otherop;
4820 operands[7] = otherop;
4821 operands[8] = operands[1];
4824 = replace_equiv_address (operands[5],
4825 gen_rtx_PLUS (SImode,
4826 operands[7], operands[8]));
4829 ;; As above but to memory.
4830 ;; FIXME: Split movemside and moverside into variants and prune
4831 ;; the ones that don't trig.
4832 ;; No stable test-case.
4834 (define_peephole2 ; movemside (peephole casesi+39)
4835 [(set (match_operand:SI 0 "register_operand" "")
4836 (match_operand:SI 1 "cris_bdap_biap_operand" ""))
4838 (plus:SI (match_operand:SI 2 "cris_bdap_biap_operand" "")
4839 (match_operand:SI 3 "cris_bdap_biap_operand" "")))
4840 (set (match_operator 4 "cris_mem_op" [(match_dup 0)])
4841 (match_operand 5 "register_operand" ""))]
4842 "(rtx_equal_p (operands[2], operands[0])
4843 || rtx_equal_p (operands[3], operands[0]))
4844 && cris_side_effect_mode_ok (PLUS, operands, 0,
4845 (REG_S_P (operands[1])
4847 : (rtx_equal_p (operands[2], operands[0])
4849 (! REG_S_P (operands[1])
4851 : (rtx_equal_p (operands[2], operands[0])
4855 [(set (match_dup 6) (match_dup 5))
4856 (set (match_dup 0) (plus:SI (match_dup 7) (match_dup 8)))])]
4859 = rtx_equal_p (operands[2], operands[0]) ? operands[3] : operands[2];
4861 /* Make sure we have canonical RTX so we match the insn pattern -
4862 not a constant in the first operand. We also require the order
4863 (plus reg mem) to match the final pattern. */
4864 if (CONSTANT_P (otherop) || MEM_P (otherop))
4866 operands[7] = operands[1];
4867 operands[8] = otherop;
4871 operands[7] = otherop;
4872 operands[8] = operands[1];
4875 = replace_equiv_address (operands[4],
4876 gen_rtx_PLUS (SImode,
4877 operands[7], operands[8]));
4880 ;; Another spotted bad code:
4883 ;; No stable test-case.
4885 (define_peephole2 ; movei (peephole casesi+42)
4886 [(set (match_operand:SI 0 "register_operand" "")
4887 (match_operand:SI 1 "register_operand" ""))
4888 (set (match_operand 2 "register_operand" "")
4889 (match_operator 3 "cris_mem_op" [(match_dup 0)]))]
4890 "REGNO (operands[0]) == REGNO (operands[2])
4891 && (REGNO_REG_CLASS (REGNO (operands[0]))
4892 == REGNO_REG_CLASS (REGNO (operands[1])))
4893 && GET_MODE_SIZE (GET_MODE (operands[2])) <= UNITS_PER_WORD"
4894 [(set (match_dup 2) (match_dup 4))]
4895 "operands[4] = replace_equiv_address (operands[3], operands[1]);")
4897 ;; move.d [r10+16],r9
4900 ;; and.d [r10+16],r12,r9
4901 ;; With generalization of the operation, the size and the addressing mode.
4902 ;; This seems to be the result of a quirk in register allocation
4903 ;; missing the three-operand cases when having different predicates.
4904 ;; Maybe that it matters that it is a commutative operation.
4905 ;; This pattern helps that situation, but there's still the increased
4906 ;; register pressure.
4907 ;; Note that adding the noncommutative variant did not show any matches
4908 ;; in ipps and cc1, so it's not here.
4909 ;; No stable test-case.
4911 (define_peephole2 ; op3 (peephole casesi+44)
4912 [(set (match_operand 0 "register_operand" "")
4916 (match_operand:SI 1 "cris_bdap_biap_operand" "")
4917 (match_operand:SI 2 "cris_bdap_biap_operand" ""))]))
4920 5 "cris_commutative_orth_op"
4921 [(match_operand 3 "register_operand" "")
4922 (match_operand 4 "register_operand" "")]))]
4923 "(rtx_equal_p (operands[3], operands[0])
4924 || rtx_equal_p (operands[4], operands[0]))
4925 && ! rtx_equal_p (operands[3], operands[4])
4926 && (REG_S_P (operands[1]) || REG_S_P (operands[2]))
4927 && GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD"
4928 [(set (match_dup 0) (match_op_dup 5 [(match_dup 7) (match_dup 6)]))]
4930 = rtx_equal_p (operands[3], operands[0]) ? operands[4] : operands[3];")
4932 ;; I cannot tell GCC (2.1, 2.7.2) how to correctly reload an instruction
4934 ;; and.b some_byte,const,reg_32
4935 ;; where reg_32 is the destination of the "three-address" code optimally.
4937 ;; movu.b some_byte,reg_32
4938 ;; and.b const,reg_32
4939 ;; but is turns into:
4940 ;; move.b some_byte,reg_32
4941 ;; and.d const,reg_32
4943 ;; Testcases: gcc.dg/cris-peep2-andu1.c gcc.dg/cris-peep2-andu2.c
4945 (define_peephole2 ; andu (casesi+45)
4946 [(set (match_operand:SI 0 "register_operand" "")
4947 (match_operand:SI 1 "nonimmediate_operand" ""))
4948 (set (match_operand:SI 2 "register_operand" "")
4949 (and:SI (match_dup 0)
4950 (match_operand:SI 3 "const_int_operand" "")))]
4951 ;; Since the size of the memory access could be made different here,
4952 ;; don't do this for a mem-volatile access.
4953 "REGNO (operands[2]) == REGNO (operands[0])
4954 && INTVAL (operands[3]) <= 65535 && INTVAL (operands[3]) >= 0
4955 && !CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'I')
4956 && !side_effects_p (operands[1])"
4957 ;; FIXME: CC0 valid except for M (i.e. CC_NOT_NEGATIVE).
4958 [(set (match_dup 0) (match_dup 4))
4959 (set (match_dup 5) (match_dup 6))]
4961 enum machine_mode zmode = INTVAL (operands[3]) <= 255 ? QImode : HImode;
4962 enum machine_mode amode
4963 = CRIS_CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'O') ? SImode : zmode;
4965 = (REG_S_P (operands[1])
4966 ? gen_rtx_REG (zmode, REGNO (operands[1]))
4967 : adjust_address (operands[1], zmode, 0));
4969 = gen_rtx_ZERO_EXTEND (SImode, op1);
4970 operands[5] = gen_rtx_REG (amode, REGNO (operands[0]));
4972 = gen_rtx_AND (amode, gen_rtx_REG (amode, REGNO (operands[0])),
4973 GEN_INT (trunc_int_for_mode (INTVAL (operands[3]),
4975 ? QImode : amode)));
4978 ;; Try and avoid GOTPLT reads escaping a call: transform them into
4979 ;; PLT. Curiously (but thankfully), peepholes for instructions
4980 ;; *without side-effects* that just feed a call (or call_value) are
4981 ;; not matched neither in a build or test-suite, so those patterns are
4984 ;; A "normal" move where we don't check the consumer.
4986 (define_peephole2 ; gotplt-to-plt
4988 (match_operand:SI 0 "register_operand" "")
4992 (reg:SI CRIS_GOT_REGNUM)
4994 (unspec:SI [(match_operand:SI 2 "cris_general_operand_or_symbol" "")]
4995 CRIS_UNSPEC_PLTGOTREAD)))]))]
4997 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
4998 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
4999 [(set (match_dup 0) (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
5000 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
5003 ;; And one set with a side-effect getting the PLTGOT offset.
5004 ;; First call and call_value variants.
5006 (define_peephole2 ; gotplt-to-plt-side-call
5009 (match_operand:SI 0 "register_operand" "")
5013 (reg:SI CRIS_GOT_REGNUM)
5015 (unspec:SI [(match_operand:SI
5016 2 "cris_general_operand_or_symbol" "")]
5017 CRIS_UNSPEC_PLTGOTREAD)))]))
5018 (set (match_operand:SI 3 "register_operand" "")
5019 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5021 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5022 (parallel [(call (mem:QI (match_dup 0))
5023 (match_operand 4 "" ""))
5024 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5026 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5027 && peep2_reg_dead_p (2, operands[0])"
5028 [(parallel [(call (mem:QI (match_dup 1))
5030 (clobber (reg:SI CRIS_SRP_REGNUM))
5032 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5034 (unspec:SI [(match_dup 2)]
5035 CRIS_UNSPEC_PLTGOTREAD))))])]
5038 (define_peephole2 ; gotplt-to-plt-side-call-value
5041 (match_operand:SI 0 "register_operand" "")
5045 (reg:SI CRIS_GOT_REGNUM)
5047 (unspec:SI [(match_operand:SI
5048 2 "cris_general_operand_or_symbol" "")]
5049 CRIS_UNSPEC_PLTGOTREAD)))]))
5050 (set (match_operand:SI 3 "register_operand" "")
5051 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5053 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])
5054 (parallel [(set (match_operand 5 "" "")
5055 (call (mem:QI (match_dup 0))
5056 (match_operand 4 "" "")))
5057 (clobber (reg:SI CRIS_SRP_REGNUM))])]
5059 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5060 && peep2_reg_dead_p (2, operands[0])"
5061 [(parallel [(set (match_dup 5)
5062 (call (mem:QI (match_dup 1))
5064 (clobber (reg:SI CRIS_SRP_REGNUM))
5066 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5068 (unspec:SI [(match_dup 2)]
5069 CRIS_UNSPEC_PLTGOTREAD))))])]
5072 (define_peephole2 ; gotplt-to-plt-side
5075 (match_operand:SI 0 "register_operand" "")
5079 (reg:SI CRIS_GOT_REGNUM)
5081 (unspec:SI [(match_operand:SI
5082 2 "cris_general_operand_or_symbol" "")]
5083 CRIS_UNSPEC_PLTGOTREAD)))]))
5084 (set (match_operand:SI 3 "register_operand" "")
5085 (plus:SI (reg:SI CRIS_GOT_REGNUM)
5087 (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD))))])]
5089 && cris_valid_pic_const (XEXP (XEXP (operands[1], 0), 1), true)
5090 && REGNO_REG_CLASS (REGNO (operands[0])) == REGNO_REG_CLASS (0)"
5092 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLTGOTREAD)))
5093 (set (match_dup 3) (plus:SI (match_dup 3) (reg:SI CRIS_GOT_REGNUM)))
5095 (const:SI (unspec:SI [(match_dup 2)] CRIS_UNSPEC_PLT_GOTREL)))
5096 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI CRIS_GOT_REGNUM)))]
5101 ;; comment-start: ";; "
5102 ;; eval: (set-syntax-table (copy-sequence (syntax-table)))
5103 ;; eval: (modify-syntax-entry ?[ "(]")
5104 ;; eval: (modify-syntax-entry ?] ")[")
5105 ;; eval: (modify-syntax-entry ?{ "(}")
5106 ;; eval: (modify-syntax-entry ?} "){")
5107 ;; eval: (setq indent-tabs-mode t)