PR rtl-optimization/88018
[official-gcc.git] / gcc / config / rs6000 / rs6000.h
blobf59c0b6b68550640d9ef923f06f3a1c70f64f1e7
1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2018 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
29 #ifndef RS6000_OPTS_H
30 #include "config/rs6000/rs6000-opts.h"
31 #endif
33 /* 128-bit floating point precision values. */
34 #ifndef RS6000_MODES_H
35 #include "config/rs6000/rs6000-modes.h"
36 #endif
38 /* Definitions for the object file format. These are set at
39 compile-time. */
41 #define OBJECT_XCOFF 1
42 #define OBJECT_ELF 2
43 #define OBJECT_PEF 3
44 #define OBJECT_MACHO 4
46 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
47 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
48 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
49 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
51 #ifndef TARGET_AIX
52 #define TARGET_AIX 0
53 #endif
55 #ifndef TARGET_AIX_OS
56 #define TARGET_AIX_OS 0
57 #endif
59 /* Control whether function entry points use a "dot" symbol when
60 ABI_AIX. */
61 #define DOT_SYMBOLS 1
63 /* Default string to use for cpu if not specified. */
64 #ifndef TARGET_CPU_DEFAULT
65 #define TARGET_CPU_DEFAULT ((char *)0)
66 #endif
68 /* If configured for PPC405, support PPC405CR Erratum77. */
69 #ifdef CONFIG_PPC405CR
70 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
71 #else
72 #define PPC405_ERRATUM77 0
73 #endif
75 /* Common ASM definitions used by ASM_SPEC among the various targets for
76 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
77 provide the default assembler options if the user uses -mcpu=native, so if
78 you make changes here, make them also there. PR63177: Do not pass -mpower8
79 to the assembler if -mpower9-vector was also used. */
80 #define ASM_CPU_SPEC \
81 "%{!mcpu*: \
82 %{mpowerpc64*: -mppc64} \
83 %{!mpowerpc64*: %(asm_default)}} \
84 %{mcpu=native: %(asm_cpu_native)} \
85 %{mcpu=cell: -mcell} \
86 %{mcpu=power3: -mppc64} \
87 %{mcpu=power4: -mpower4} \
88 %{mcpu=power5: -mpower5} \
89 %{mcpu=power5+: -mpower5} \
90 %{mcpu=power6: -mpower6 -maltivec} \
91 %{mcpu=power6x: -mpower6 -maltivec} \
92 %{mcpu=power7: -mpower7} \
93 %{mcpu=power8: %{!mpower9-vector: -mpower8}} \
94 %{mcpu=power9: -mpower9} \
95 %{mcpu=a2: -ma2} \
96 %{mcpu=powerpc: -mppc} \
97 %{mcpu=powerpc64le: -mpower8} \
98 %{mcpu=rs64a: -mppc64} \
99 %{mcpu=401: -mppc} \
100 %{mcpu=403: -m403} \
101 %{mcpu=405: -m405} \
102 %{mcpu=405fp: -m405} \
103 %{mcpu=440: -m440} \
104 %{mcpu=440fp: -m440} \
105 %{mcpu=464: -m440} \
106 %{mcpu=464fp: -m440} \
107 %{mcpu=476: -m476} \
108 %{mcpu=476fp: -m476} \
109 %{mcpu=505: -mppc} \
110 %{mcpu=601: -m601} \
111 %{mcpu=602: -mppc} \
112 %{mcpu=603: -mppc} \
113 %{mcpu=603e: -mppc} \
114 %{mcpu=ec603e: -mppc} \
115 %{mcpu=604: -mppc} \
116 %{mcpu=604e: -mppc} \
117 %{mcpu=620: -mppc64} \
118 %{mcpu=630: -mppc64} \
119 %{mcpu=740: -mppc} \
120 %{mcpu=750: -mppc} \
121 %{mcpu=G3: -mppc} \
122 %{mcpu=7400: -mppc -maltivec} \
123 %{mcpu=7450: -mppc -maltivec} \
124 %{mcpu=G4: -mppc -maltivec} \
125 %{mcpu=801: -mppc} \
126 %{mcpu=821: -mppc} \
127 %{mcpu=823: -mppc} \
128 %{mcpu=860: -mppc} \
129 %{mcpu=970: -mpower4 -maltivec} \
130 %{mcpu=G5: -mpower4 -maltivec} \
131 %{mcpu=8540: -me500} \
132 %{mcpu=8548: -me500} \
133 %{mcpu=e300c2: -me300} \
134 %{mcpu=e300c3: -me300} \
135 %{mcpu=e500mc: -me500mc} \
136 %{mcpu=e500mc64: -me500mc64} \
137 %{mcpu=e5500: -me5500} \
138 %{mcpu=e6500: -me6500} \
139 %{maltivec: -maltivec} \
140 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: -mpower7}} \
141 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: -mpower8}} \
142 %{mpower9-vector: %{!mcpu*|mcpu=power8: -mpower9}} \
143 -many"
145 #define CPP_DEFAULT_SPEC ""
147 #define ASM_DEFAULT_SPEC ""
149 /* This macro defines names of additional specifications to put in the specs
150 that can be used in various specifications like CC1_SPEC. Its definition
151 is an initializer with a subgrouping for each command option.
153 Each subgrouping contains a string constant, that defines the
154 specification name, and a string constant that used by the GCC driver
155 program.
157 Do not define this macro if it does not need to do anything. */
159 #define SUBTARGET_EXTRA_SPECS
161 #define EXTRA_SPECS \
162 { "cpp_default", CPP_DEFAULT_SPEC }, \
163 { "asm_cpu", ASM_CPU_SPEC }, \
164 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
165 { "asm_default", ASM_DEFAULT_SPEC }, \
166 { "cc1_cpu", CC1_CPU_SPEC }, \
167 SUBTARGET_EXTRA_SPECS
169 /* -mcpu=native handling only makes sense with compiler running on
170 an PowerPC chip. If changing this condition, also change
171 the condition in driver-rs6000.c. */
172 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
173 /* In driver-rs6000.c. */
174 extern const char *host_detect_local_cpu (int argc, const char **argv);
175 #define EXTRA_SPEC_FUNCTIONS \
176 { "local_cpu_detect", host_detect_local_cpu },
177 #define HAVE_LOCAL_CPU_DETECT
178 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
180 #else
181 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
182 #endif
184 #ifndef CC1_CPU_SPEC
185 #ifdef HAVE_LOCAL_CPU_DETECT
186 #define CC1_CPU_SPEC \
187 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
188 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
189 #else
190 #define CC1_CPU_SPEC ""
191 #endif
192 #endif
194 /* Architecture type. */
196 /* Define TARGET_MFCRF if the target assembler does not support the
197 optional field operand for mfcr. */
199 #ifndef HAVE_AS_MFCRF
200 #undef TARGET_MFCRF
201 #define TARGET_MFCRF 0
202 #endif
204 /* Define TARGET_TLS_MARKERS if the target assembler does not support
205 arg markers for __tls_get_addr calls. */
206 #ifndef HAVE_AS_TLS_MARKERS
207 #undef TARGET_TLS_MARKERS
208 #define TARGET_TLS_MARKERS 0
209 #else
210 #define TARGET_TLS_MARKERS tls_markers
211 #endif
213 #ifndef TARGET_SECURE_PLT
214 #define TARGET_SECURE_PLT 0
215 #endif
217 #ifndef TARGET_CMODEL
218 #define TARGET_CMODEL CMODEL_SMALL
219 #endif
221 #define TARGET_32BIT (! TARGET_64BIT)
223 #ifndef HAVE_AS_TLS
224 #define HAVE_AS_TLS 0
225 #endif
227 #ifndef TARGET_LINK_STACK
228 #define TARGET_LINK_STACK 0
229 #endif
231 #ifndef SET_TARGET_LINK_STACK
232 #define SET_TARGET_LINK_STACK(X) do { } while (0)
233 #endif
235 #ifndef TARGET_FLOAT128_ENABLE_TYPE
236 #define TARGET_FLOAT128_ENABLE_TYPE 0
237 #endif
239 /* Return 1 for a symbol ref for a thread-local storage symbol. */
240 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
241 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
243 #ifdef IN_LIBGCC2
244 /* For libgcc2 we make sure this is a compile time constant */
245 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
246 #undef TARGET_POWERPC64
247 #define TARGET_POWERPC64 1
248 #else
249 #undef TARGET_POWERPC64
250 #define TARGET_POWERPC64 0
251 #endif
252 #else
253 /* The option machinery will define this. */
254 #endif
256 #define TARGET_DEFAULT (MASK_MULTIPLE)
258 /* Define generic processor types based upon current deployment. */
259 #define PROCESSOR_COMMON PROCESSOR_PPC601
260 #define PROCESSOR_POWERPC PROCESSOR_PPC604
261 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
263 /* Define the default processor. This is overridden by other tm.h files. */
264 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
265 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
267 /* Specify the dialect of assembler to use. Only new mnemonics are supported
268 starting with GCC 4.8, i.e. just one dialect, but for backwards
269 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
270 defined. */
271 #define ASSEMBLER_DIALECT 1
273 /* Debug support */
274 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
275 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
276 #define MASK_DEBUG_REG 0x04 /* debug register handling */
277 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
278 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
279 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
280 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
281 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
282 | MASK_DEBUG_ARG \
283 | MASK_DEBUG_REG \
284 | MASK_DEBUG_ADDR \
285 | MASK_DEBUG_COST \
286 | MASK_DEBUG_TARGET \
287 | MASK_DEBUG_BUILTIN)
289 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
290 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
291 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
292 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
293 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
294 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
295 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
297 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
298 long double format that uses a pair of doubles, or IEEE 128-bit floating
299 point. KFmode was added as a way to represent IEEE 128-bit floating point,
300 even if the default for long double is the IBM long double format.
301 Similarly IFmode is the IBM long double format even if the default is IEEE
302 128-bit. Don't allow IFmode if -msoft-float. */
303 #define FLOAT128_IEEE_P(MODE) \
304 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
305 && ((MODE) == TFmode || (MODE) == TCmode)) \
306 || ((MODE) == KFmode) || ((MODE) == KCmode))
308 #define FLOAT128_IBM_P(MODE) \
309 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
310 && ((MODE) == TFmode || (MODE) == TCmode)) \
311 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
313 /* Helper macros to say whether a 128-bit floating point type can go in a
314 single vector register, or whether it needs paired scalar values. */
315 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
317 #define FLOAT128_2REG_P(MODE) \
318 (FLOAT128_IBM_P (MODE) \
319 || ((MODE) == TDmode) \
320 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
322 /* Return true for floating point that does not use a vector register. */
323 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
324 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
326 /* Describe the vector unit used for arithmetic operations. */
327 extern enum rs6000_vector rs6000_vector_unit[];
329 #define VECTOR_UNIT_NONE_P(MODE) \
330 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
332 #define VECTOR_UNIT_VSX_P(MODE) \
333 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
335 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
336 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
338 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
339 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
341 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
342 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
343 (int)VECTOR_VSX, \
344 (int)VECTOR_P8_VECTOR))
346 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
347 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
348 compatible, so allow it as well, rather than changing all of the uses of the
349 macro. */
350 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
351 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
352 (int)VECTOR_ALTIVEC, \
353 (int)VECTOR_P8_VECTOR))
355 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
356 same unit as the vector unit we are using, but we may want to migrate to
357 using VSX style loads even for types handled by altivec. */
358 extern enum rs6000_vector rs6000_vector_mem[];
360 #define VECTOR_MEM_NONE_P(MODE) \
361 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
363 #define VECTOR_MEM_VSX_P(MODE) \
364 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
366 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
367 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
369 #define VECTOR_MEM_ALTIVEC_P(MODE) \
370 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
372 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
373 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
374 (int)VECTOR_VSX, \
375 (int)VECTOR_P8_VECTOR))
377 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
378 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
379 (int)VECTOR_ALTIVEC, \
380 (int)VECTOR_P8_VECTOR))
382 /* Return the alignment of a given vector type, which is set based on the
383 vector unit use. VSX for instance can load 32 or 64 bit aligned words
384 without problems, while Altivec requires 128-bit aligned vectors. */
385 extern int rs6000_vector_align[];
387 #define VECTOR_ALIGN(MODE) \
388 ((rs6000_vector_align[(MODE)] != 0) \
389 ? rs6000_vector_align[(MODE)] \
390 : (int)GET_MODE_BITSIZE ((MODE)))
392 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
393 with scalar instructions. */
394 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
396 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
397 with the ISA 3.0 MFVSRLD instructions. */
398 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
400 /* Alignment options for fields in structures for sub-targets following
401 AIX-like ABI.
402 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
403 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
405 Override the macro definitions when compiling libobjc to avoid undefined
406 reference to rs6000_alignment_flags due to library's use of GCC alignment
407 macros which use the macros below. */
409 #ifndef IN_TARGET_LIBS
410 #define MASK_ALIGN_POWER 0x00000000
411 #define MASK_ALIGN_NATURAL 0x00000001
412 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
413 #else
414 #define TARGET_ALIGN_NATURAL 0
415 #endif
417 /* We use values 126..128 to pick the appropriate long double type (IFmode,
418 KFmode, TFmode). */
419 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
420 #define TARGET_IEEEQUAD rs6000_ieeequad
421 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
422 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
424 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
425 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
426 #define TARGET_FCFID (TARGET_POWERPC64 \
427 || TARGET_PPC_GPOPT /* 970/power4 */ \
428 || TARGET_POPCNTB /* ISA 2.02 */ \
429 || TARGET_CMPB /* ISA 2.05 */ \
430 || TARGET_POPCNTD) /* ISA 2.06 */
432 #define TARGET_FCTIDZ TARGET_FCFID
433 #define TARGET_STFIWX TARGET_PPC_GFXOPT
434 #define TARGET_LFIWAX TARGET_CMPB
435 #define TARGET_LFIWZX TARGET_POPCNTD
436 #define TARGET_FCFIDS TARGET_POPCNTD
437 #define TARGET_FCFIDU TARGET_POPCNTD
438 #define TARGET_FCFIDUS TARGET_POPCNTD
439 #define TARGET_FCTIDUZ TARGET_POPCNTD
440 #define TARGET_FCTIWUZ TARGET_POPCNTD
441 #define TARGET_CTZ TARGET_MODULO
442 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
443 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
445 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
446 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
447 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
448 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
449 && TARGET_POWERPC64)
450 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
451 && TARGET_POWERPC64)
453 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
454 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
455 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
457 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
458 loads are slow. */
459 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
461 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
462 in power7, so conditionalize them on p8 features. TImode syncs need quad
463 memory support. */
464 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
465 || TARGET_QUAD_MEMORY_ATOMIC \
466 || TARGET_DIRECT_MOVE)
468 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
470 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
471 to allocate the SDmode stack slot to get the value into the proper location
472 in the register. */
473 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
475 /* ISA 3.0 has new min/max functions that don't need fast math that are being
476 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
477 answers if the arguments are not in the normal range. */
478 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
479 && (TARGET_P9_MINMAX || !flag_trapping_math))
481 /* In switching from using target_flags to using rs6000_isa_flags, the options
482 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
483 OPTION_MASK_<xxx> back into MASK_<xxx>. */
484 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
485 #define MASK_CMPB OPTION_MASK_CMPB
486 #define MASK_CRYPTO OPTION_MASK_CRYPTO
487 #define MASK_DFP OPTION_MASK_DFP
488 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
489 #define MASK_DLMZB OPTION_MASK_DLMZB
490 #define MASK_EABI OPTION_MASK_EABI
491 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
492 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
493 #define MASK_FPRND OPTION_MASK_FPRND
494 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
495 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
496 #define MASK_HTM OPTION_MASK_HTM
497 #define MASK_ISEL OPTION_MASK_ISEL
498 #define MASK_MFCRF OPTION_MASK_MFCRF
499 #define MASK_MFPGPR OPTION_MASK_MFPGPR
500 #define MASK_MULHW OPTION_MASK_MULHW
501 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
502 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
503 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
504 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
505 #define MASK_P9_MISC OPTION_MASK_P9_MISC
506 #define MASK_POPCNTB OPTION_MASK_POPCNTB
507 #define MASK_POPCNTD OPTION_MASK_POPCNTD
508 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
509 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
510 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
511 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
512 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
513 #define MASK_UPDATE OPTION_MASK_UPDATE
514 #define MASK_VSX OPTION_MASK_VSX
516 #ifndef IN_LIBGCC2
517 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
518 #endif
520 #ifdef TARGET_64BIT
521 #define MASK_64BIT OPTION_MASK_64BIT
522 #endif
524 #ifdef TARGET_LITTLE_ENDIAN
525 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
526 #endif
528 #ifdef TARGET_REGNAMES
529 #define MASK_REGNAMES OPTION_MASK_REGNAMES
530 #endif
532 #ifdef TARGET_PROTOTYPE
533 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
534 #endif
536 #ifdef TARGET_MODULO
537 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
538 #endif
541 /* For power systems, we want to enable Altivec and VSX builtins even if the
542 user did not use -maltivec or -mvsx to allow the builtins to be used inside
543 of #pragma GCC target or the target attribute to change the code level for a
544 given system. */
546 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
547 || TARGET_PPC_GPOPT /* 970/power4 */ \
548 || TARGET_POPCNTB /* ISA 2.02 */ \
549 || TARGET_CMPB /* ISA 2.05 */ \
550 || TARGET_POPCNTD /* ISA 2.06 */ \
551 || TARGET_ALTIVEC \
552 || TARGET_VSX \
553 || TARGET_HARD_FLOAT)
555 /* E500 cores only support plain "sync", not lwsync. */
556 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
557 || rs6000_cpu == PROCESSOR_PPC8548)
560 /* Which machine supports the various reciprocal estimate instructions. */
561 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
563 #define TARGET_FRE (TARGET_HARD_FLOAT \
564 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
566 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
567 && TARGET_PPC_GFXOPT)
569 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
570 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
572 /* Macro to say whether we can do optimizations where we need to do parts of
573 the calculation in 64-bit GPRs and then is transfered to the vector
574 registers. */
575 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
576 && TARGET_P8_VECTOR \
577 && TARGET_POWERPC64)
579 /* Whether the various reciprocal divide/square root estimate instructions
580 exist, and whether we should automatically generate code for the instruction
581 by default. */
582 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
583 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
584 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
585 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
587 extern unsigned char rs6000_recip_bits[];
589 #define RS6000_RECIP_HAVE_RE_P(MODE) \
590 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
592 #define RS6000_RECIP_AUTO_RE_P(MODE) \
593 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
595 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
596 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
598 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
599 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
601 /* The default CPU for TARGET_OPTION_OVERRIDE. */
602 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
604 /* Target pragma. */
605 #define REGISTER_TARGET_PRAGMAS() do { \
606 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
607 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
608 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
609 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
610 } while (0)
612 /* Target #defines. */
613 #define TARGET_CPU_CPP_BUILTINS() \
614 rs6000_cpu_cpp_builtins (pfile)
616 /* Target CPU versions for D. */
617 #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions
619 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
620 we're compiling for. Some configurations may need to override it. */
621 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
622 do \
624 if (BYTES_BIG_ENDIAN) \
626 builtin_define ("__BIG_ENDIAN__"); \
627 builtin_define ("_BIG_ENDIAN"); \
628 builtin_assert ("machine=bigendian"); \
630 else \
632 builtin_define ("__LITTLE_ENDIAN__"); \
633 builtin_define ("_LITTLE_ENDIAN"); \
634 builtin_assert ("machine=littleendian"); \
637 while (0)
639 /* Target machine storage layout. */
641 /* Define this macro if it is advisable to hold scalars in registers
642 in a wider mode than that declared by the program. In such cases,
643 the value is constrained to be within the bounds of the declared
644 type, but kept valid in the wider mode. The signedness of the
645 extension may differ from that of the type. */
647 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
648 if (GET_MODE_CLASS (MODE) == MODE_INT \
649 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
650 (MODE) = TARGET_32BIT ? SImode : DImode;
652 /* Define this if most significant bit is lowest numbered
653 in instructions that operate on numbered bit-fields. */
654 /* That is true on RS/6000. */
655 #define BITS_BIG_ENDIAN 1
657 /* Define this if most significant byte of a word is the lowest numbered. */
658 /* That is true on RS/6000. */
659 #define BYTES_BIG_ENDIAN 1
661 /* Define this if most significant word of a multiword number is lowest
662 numbered.
664 For RS/6000 we can decide arbitrarily since there are no machine
665 instructions for them. Might as well be consistent with bits and bytes. */
666 #define WORDS_BIG_ENDIAN 1
668 /* This says that for the IBM long double the larger magnitude double
669 comes first. It's really a two element double array, and arrays
670 don't index differently between little- and big-endian. */
671 #define LONG_DOUBLE_LARGE_FIRST 1
673 #define MAX_BITS_PER_WORD 64
675 /* Width of a word, in units (bytes). */
676 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
677 #ifdef IN_LIBGCC2
678 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
679 #else
680 #define MIN_UNITS_PER_WORD 4
681 #endif
682 #define UNITS_PER_FP_WORD 8
683 #define UNITS_PER_ALTIVEC_WORD 16
684 #define UNITS_PER_VSX_WORD 16
686 /* Type used for ptrdiff_t, as a string used in a declaration. */
687 #define PTRDIFF_TYPE "int"
689 /* Type used for size_t, as a string used in a declaration. */
690 #define SIZE_TYPE "long unsigned int"
692 /* Type used for wchar_t, as a string used in a declaration. */
693 #define WCHAR_TYPE "short unsigned int"
695 /* Width of wchar_t in bits. */
696 #define WCHAR_TYPE_SIZE 16
698 /* A C expression for the size in bits of the type `short' on the
699 target machine. If you don't define this, the default is half a
700 word. (If this would be less than one storage unit, it is
701 rounded up to one unit.) */
702 #define SHORT_TYPE_SIZE 16
704 /* A C expression for the size in bits of the type `int' on the
705 target machine. If you don't define this, the default is one
706 word. */
707 #define INT_TYPE_SIZE 32
709 /* A C expression for the size in bits of the type `long' on the
710 target machine. If you don't define this, the default is one
711 word. */
712 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
714 /* A C expression for the size in bits of the type `long long' on the
715 target machine. If you don't define this, the default is two
716 words. */
717 #define LONG_LONG_TYPE_SIZE 64
719 /* A C expression for the size in bits of the type `float' on the
720 target machine. If you don't define this, the default is one
721 word. */
722 #define FLOAT_TYPE_SIZE 32
724 /* A C expression for the size in bits of the type `double' on the
725 target machine. If you don't define this, the default is two
726 words. */
727 #define DOUBLE_TYPE_SIZE 64
729 /* A C expression for the size in bits of the type `long double' on the target
730 machine. If you don't define this, the default is two words. */
731 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
733 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
734 #define WIDEST_HARDWARE_FP_SIZE 64
736 /* Width in bits of a pointer.
737 See also the macro `Pmode' defined below. */
738 extern unsigned rs6000_pointer_size;
739 #define POINTER_SIZE rs6000_pointer_size
741 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
742 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
744 /* Boundary (in *bits*) on which stack pointer should be aligned. */
745 #define STACK_BOUNDARY \
746 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
747 ? 64 : 128)
749 /* Allocation boundary (in *bits*) for the code of a function. */
750 #define FUNCTION_BOUNDARY 32
752 /* No data type wants to be aligned rounder than this. */
753 #define BIGGEST_ALIGNMENT 128
755 /* Alignment of field after `int : 0' in a structure. */
756 #define EMPTY_FIELD_BOUNDARY 32
758 /* Every structure's size must be a multiple of this. */
759 #define STRUCTURE_SIZE_BOUNDARY 8
761 /* A bit-field declared as `int' forces `int' alignment for the struct. */
762 #define PCC_BITFIELD_TYPE_MATTERS 1
764 enum data_align { align_abi, align_opt, align_both };
766 /* A C expression to compute the alignment for a variables in the
767 local store. TYPE is the data type, and ALIGN is the alignment
768 that the object would ordinarily have. */
769 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
770 rs6000_data_alignment (TYPE, ALIGN, align_both)
772 /* Make arrays of chars word-aligned for the same reasons. */
773 #define DATA_ALIGNMENT(TYPE, ALIGN) \
774 rs6000_data_alignment (TYPE, ALIGN, align_opt)
776 /* Align vectors to 128 bits. */
777 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
778 rs6000_data_alignment (TYPE, ALIGN, align_abi)
780 /* Nonzero if move instructions will actually fail to work
781 when given unaligned data. */
782 #define STRICT_ALIGNMENT 0
784 /* Standard register usage. */
786 /* Number of actual hardware registers.
787 The hardware registers are assigned numbers for the compiler
788 from 0 to just below FIRST_PSEUDO_REGISTER.
789 All registers that the compiler knows about must be given numbers,
790 even those that are not normally considered general registers.
792 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
793 a count register, a link register, and 8 condition register fields,
794 which we view here as separate registers. AltiVec adds 32 vector
795 registers and a VRsave register.
797 In addition, the difference between the frame and argument pointers is
798 a function of the number of registers saved, so we need to have a
799 register for AP that will later be eliminated in favor of SP or FP.
800 This is a normal register, but it is fixed.
802 We also create a pseudo register for float/int conversions, that will
803 really represent the memory location used. It is represented here as
804 a register, in order to work around problems in allocating stack storage
805 in inline functions.
807 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
808 pointer, which is eventually eliminated in favor of SP or FP.
810 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
812 #define FIRST_PSEUDO_REGISTER 115
814 /* This must be included for pre gcc 3.0 glibc compatibility. */
815 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
817 /* The sfp register and 3 HTM registers
818 aren't included in DWARF_FRAME_REGISTERS. */
819 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
821 /* Use standard DWARF numbering for DWARF debugging information. */
822 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
824 /* Use gcc hard register numbering for eh_frame. */
825 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
827 /* Map register numbers held in the call frame info that gcc has
828 collected using DWARF_FRAME_REGNUM to those that should be output in
829 .debug_frame and .eh_frame. */
830 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
831 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1)
833 /* 1 for registers that have pervasive standard uses
834 and are not available for the register allocator.
836 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
837 as a local register; for all other OS's r2 is the TOC pointer.
839 On System V implementations, r13 is fixed and not available for use. */
841 #define FIXED_REGISTERS \
842 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
843 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
844 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
845 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
846 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
847 /* AltiVec registers. */ \
848 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
849 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
850 1, 1 \
851 , 1, 1, 1, 1 \
854 /* 1 for registers not available across function calls.
855 These must include the FIXED_REGISTERS and also any
856 registers that can be used without being saved.
857 The latter must include the registers where values are returned
858 and the register where structure-value addresses are passed.
859 Aside from that, you can include as many other registers as you like. */
861 #define CALL_USED_REGISTERS \
862 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
863 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
864 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
865 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
866 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
867 /* AltiVec registers. */ \
868 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
869 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
870 1, 1 \
871 , 1, 1, 1, 1 \
874 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
875 the entire set of `FIXED_REGISTERS' be included.
876 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
877 This macro is optional. If not specified, it defaults to the value
878 of `CALL_USED_REGISTERS'. */
880 #define CALL_REALLY_USED_REGISTERS \
881 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
882 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
883 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
884 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
885 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
886 /* AltiVec registers. */ \
887 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
888 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
889 0, 0 \
890 , 0, 0, 0, 0 \
893 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
895 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
896 #define FIRST_SAVED_FP_REGNO (14+32)
897 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
899 /* List the order in which to allocate registers. Each register must be
900 listed once, even those in FIXED_REGISTERS.
902 We allocate in the following order:
903 fp0 (not saved or used for anything)
904 fp13 - fp2 (not saved; incoming fp arg registers)
905 fp1 (not saved; return value)
906 fp31 - fp14 (saved; order given to save least number)
907 cr7, cr5 (not saved or special)
908 cr6 (not saved, but used for vector operations)
909 cr1 (not saved, but used for FP operations)
910 cr0 (not saved, but used for arithmetic operations)
911 cr4, cr3, cr2 (saved)
912 r9 (not saved; best for TImode)
913 r10, r8-r4 (not saved; highest first for less conflict with params)
914 r3 (not saved; return value register)
915 r11 (not saved; later alloc to help shrink-wrap)
916 r0 (not saved; cannot be base reg)
917 r31 - r13 (saved; order given to save least number)
918 r12 (not saved; if used for DImode or DFmode would use r13)
919 ctr (not saved; when we have the choice ctr is better)
920 lr (saved)
921 r1, r2, ap, ca (fixed)
922 v0 - v1 (not saved or used for anything)
923 v13 - v3 (not saved; incoming vector arg registers)
924 v2 (not saved; incoming vector arg reg; return value)
925 v19 - v14 (not saved or used for anything)
926 v31 - v20 (saved; order given to save least number)
927 vrsave, vscr (fixed)
928 sfp (fixed)
929 tfhar (fixed)
930 tfiar (fixed)
931 texasr (fixed)
934 #if FIXED_R2 == 1
935 #define MAYBE_R2_AVAILABLE
936 #define MAYBE_R2_FIXED 2,
937 #else
938 #define MAYBE_R2_AVAILABLE 2,
939 #define MAYBE_R2_FIXED
940 #endif
942 #if FIXED_R13 == 1
943 #define EARLY_R12 12,
944 #define LATE_R12
945 #else
946 #define EARLY_R12
947 #define LATE_R12 12,
948 #endif
950 #define REG_ALLOC_ORDER \
951 {32, \
952 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
953 /* not use fr14 which is a saved register. */ \
954 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
955 33, \
956 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
957 50, 49, 48, 47, 46, \
958 68, 75, 73, 74, 69, 72, 71, 70, \
959 MAYBE_R2_AVAILABLE \
960 9, 10, 8, 7, 6, 5, 4, \
961 3, EARLY_R12 11, 0, \
962 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
963 18, 17, 16, 15, 14, 13, LATE_R12 \
964 66, 65, \
965 1, MAYBE_R2_FIXED 67, 76, \
966 /* AltiVec registers. */ \
967 77, 78, \
968 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
969 79, \
970 96, 95, 94, 93, 92, 91, \
971 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
972 109, 110, \
973 111, 112, 113, 114 \
976 /* True if register is floating-point. */
977 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
979 /* True if register is a condition register. */
980 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
982 /* True if register is a condition register, but not cr0. */
983 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
985 /* True if register is an integer register. */
986 #define INT_REGNO_P(N) \
987 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
989 /* True if register is the CA register. */
990 #define CA_REGNO_P(N) ((N) == CA_REGNO)
992 /* True if register is an AltiVec register. */
993 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
995 /* True if register is a VSX register. */
996 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
998 /* Alternate name for any vector register supporting floating point, no matter
999 which instruction set(s) are available. */
1000 #define VFLOAT_REGNO_P(N) \
1001 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1003 /* Alternate name for any vector register supporting integer, no matter which
1004 instruction set(s) are available. */
1005 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1007 /* Alternate name for any vector register supporting logical operations, no
1008 matter which instruction set(s) are available. Allow GPRs as well as the
1009 vector registers. */
1010 #define VLOGICAL_REGNO_P(N) \
1011 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1012 || (TARGET_VSX && FP_REGNO_P (N))) \
1014 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1015 enough space to account for vectors in FP regs. However, TFmode/TDmode
1016 should not use VSX instructions to do a caller save. */
1017 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1018 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1019 ? (MODE) \
1020 : TARGET_VSX \
1021 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1022 && FP_REGNO_P (REGNO) \
1023 ? V2DFmode \
1024 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1025 ? DFmode \
1026 : (MODE) == TDmode && FP_REGNO_P (REGNO) \
1027 ? DImode \
1028 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1030 #define VSX_VECTOR_MODE(MODE) \
1031 ((MODE) == V4SFmode \
1032 || (MODE) == V2DFmode) \
1034 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1035 really a vector, but we want to treat it as a vector for moves, and
1036 such. */
1038 #define ALTIVEC_VECTOR_MODE(MODE) \
1039 ((MODE) == V16QImode \
1040 || (MODE) == V8HImode \
1041 || (MODE) == V4SFmode \
1042 || (MODE) == V4SImode \
1043 || FLOAT128_VECTOR_P (MODE))
1045 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1046 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1047 || (MODE) == V2DImode || (MODE) == V1TImode)
1049 /* Post-reload, we can't use any new AltiVec registers, as we already
1050 emitted the vrsave mask. */
1052 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1053 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1055 /* Specify the cost of a branch insn; roughly the number of extra insns that
1056 should be added to avoid a branch.
1058 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1059 unscheduled conditional branch. */
1061 #define BRANCH_COST(speed_p, predictable_p) 3
1063 /* Override BRANCH_COST heuristic which empirically produces worse
1064 performance for removing short circuiting from the logical ops. */
1066 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1068 /* Specify the registers used for certain standard purposes.
1069 The values of these macros are register numbers. */
1071 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1072 /* #define PC_REGNUM */
1074 /* Register to use for pushing function arguments. */
1075 #define STACK_POINTER_REGNUM 1
1077 /* Base register for access to local variables of the function. */
1078 #define HARD_FRAME_POINTER_REGNUM 31
1080 /* Base register for access to local variables of the function. */
1081 #define FRAME_POINTER_REGNUM 111
1083 /* Base register for access to arguments of the function. */
1084 #define ARG_POINTER_REGNUM 67
1086 /* Place to put static chain when calling a function that requires it. */
1087 #define STATIC_CHAIN_REGNUM 11
1089 /* Base register for access to thread local storage variables. */
1090 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1093 /* Define the classes of registers for register constraints in the
1094 machine description. Also define ranges of constants.
1096 One of the classes must always be named ALL_REGS and include all hard regs.
1097 If there is more than one class, another class must be named NO_REGS
1098 and contain no registers.
1100 The name GENERAL_REGS must be the name of a class (or an alias for
1101 another name such as ALL_REGS). This is the class of registers
1102 that is allowed by "g" or "r" in a register constraint.
1103 Also, registers outside this class are allocated only when
1104 instructions express preferences for them.
1106 The classes must be numbered in nondecreasing order; that is,
1107 a larger-numbered class must never be contained completely
1108 in a smaller-numbered class.
1110 For any two classes, it is very desirable that there be another
1111 class that represents their union. */
1113 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1114 condition registers, plus three special registers, CTR, and the link
1115 register. AltiVec adds a vector register class. VSX registers overlap the
1116 FPR registers and the Altivec registers.
1118 However, r0 is special in that it cannot be used as a base register.
1119 So make a class for registers valid as base registers.
1121 Also, cr0 is the only condition code register that can be used in
1122 arithmetic insns, so make a separate class for it. */
1124 enum reg_class
1126 NO_REGS,
1127 BASE_REGS,
1128 GENERAL_REGS,
1129 FLOAT_REGS,
1130 ALTIVEC_REGS,
1131 VSX_REGS,
1132 VRSAVE_REGS,
1133 VSCR_REGS,
1134 SPR_REGS,
1135 NON_SPECIAL_REGS,
1136 LINK_REGS,
1137 CTR_REGS,
1138 LINK_OR_CTR_REGS,
1139 SPECIAL_REGS,
1140 SPEC_OR_GEN_REGS,
1141 CR0_REGS,
1142 CR_REGS,
1143 NON_FLOAT_REGS,
1144 CA_REGS,
1145 ALL_REGS,
1146 LIM_REG_CLASSES
1149 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1151 /* Give names of register classes as strings for dump file. */
1153 #define REG_CLASS_NAMES \
1155 "NO_REGS", \
1156 "BASE_REGS", \
1157 "GENERAL_REGS", \
1158 "FLOAT_REGS", \
1159 "ALTIVEC_REGS", \
1160 "VSX_REGS", \
1161 "VRSAVE_REGS", \
1162 "VSCR_REGS", \
1163 "SPR_REGS", \
1164 "NON_SPECIAL_REGS", \
1165 "LINK_REGS", \
1166 "CTR_REGS", \
1167 "LINK_OR_CTR_REGS", \
1168 "SPECIAL_REGS", \
1169 "SPEC_OR_GEN_REGS", \
1170 "CR0_REGS", \
1171 "CR_REGS", \
1172 "NON_FLOAT_REGS", \
1173 "CA_REGS", \
1174 "ALL_REGS" \
1177 /* Define which registers fit in which classes.
1178 This is an initializer for a vector of HARD_REG_SET
1179 of length N_REG_CLASSES. */
1181 #define REG_CLASS_CONTENTS \
1183 /* NO_REGS. */ \
1184 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1185 /* BASE_REGS. */ \
1186 { 0xfffffffe, 0x00000000, 0x00000008, 0x00008000 }, \
1187 /* GENERAL_REGS. */ \
1188 { 0xffffffff, 0x00000000, 0x00000008, 0x00008000 }, \
1189 /* FLOAT_REGS. */ \
1190 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
1191 /* ALTIVEC_REGS. */ \
1192 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, \
1193 /* VSX_REGS. */ \
1194 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, \
1195 /* VRSAVE_REGS. */ \
1196 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
1197 /* VSCR_REGS. */ \
1198 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, \
1199 /* SPR_REGS. */ \
1200 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, \
1201 /* NON_SPECIAL_REGS. */ \
1202 { 0xffffffff, 0xffffffff, 0x00000008, 0x00008000 }, \
1203 /* LINK_REGS. */ \
1204 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, \
1205 /* CTR_REGS. */ \
1206 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, \
1207 /* LINK_OR_CTR_REGS. */ \
1208 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, \
1209 /* SPECIAL_REGS. */ \
1210 { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, \
1211 /* SPEC_OR_GEN_REGS. */ \
1212 { 0xffffffff, 0x00000000, 0x0000000e, 0x0000a000 }, \
1213 /* CR0_REGS. */ \
1214 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, \
1215 /* CR_REGS. */ \
1216 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, \
1217 /* NON_FLOAT_REGS. */ \
1218 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00008000 }, \
1219 /* CA_REGS. */ \
1220 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, \
1221 /* ALL_REGS. */ \
1222 { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0001ffff } \
1225 /* The same information, inverted:
1226 Return the class number of the smallest class containing
1227 reg number REGNO. This could be a conditional expression
1228 or could index an array. */
1230 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER];
1232 #define REGNO_REG_CLASS(REGNO) \
1233 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1234 rs6000_regno_regclass[(REGNO)])
1236 /* Register classes for various constraints that are based on the target
1237 switches. */
1238 enum r6000_reg_class_enum {
1239 RS6000_CONSTRAINT_d, /* fpr registers for double values */
1240 RS6000_CONSTRAINT_f, /* fpr registers for single values */
1241 RS6000_CONSTRAINT_v, /* Altivec registers */
1242 RS6000_CONSTRAINT_wa, /* Any VSX register */
1243 RS6000_CONSTRAINT_wb, /* Altivec register if ISA 3.0 vector. */
1244 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */
1245 RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
1246 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */
1247 RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */
1248 RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */
1249 RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */
1250 RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */
1251 RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */
1252 RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */
1253 RS6000_CONSTRAINT_wm, /* VSX register for direct move */
1254 RS6000_CONSTRAINT_wo, /* VSX register for power9 vector. */
1255 RS6000_CONSTRAINT_wp, /* VSX reg for IEEE 128-bit fp TFmode. */
1256 RS6000_CONSTRAINT_wq, /* VSX reg for IEEE 128-bit fp KFmode. */
1257 RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
1258 RS6000_CONSTRAINT_ws, /* VSX register for DF */
1259 RS6000_CONSTRAINT_wt, /* VSX register for TImode */
1260 RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */
1261 RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */
1262 RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */
1263 RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
1264 RS6000_CONSTRAINT_wy, /* VSX register for SF */
1265 RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */
1266 RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
1267 RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
1268 RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
1269 RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */
1270 RS6000_CONSTRAINT_wK, /* Altivec register for 16/32-bit integers. */
1271 RS6000_CONSTRAINT_MAX
1274 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
1276 /* The class value for index registers, and the one for base regs. */
1277 #define INDEX_REG_CLASS GENERAL_REGS
1278 #define BASE_REG_CLASS BASE_REGS
1280 /* Return whether a given register class can hold VSX objects. */
1281 #define VSX_REG_CLASS_P(CLASS) \
1282 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1284 /* Return whether a given register class targets general purpose registers. */
1285 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1287 /* Given an rtx X being reloaded into a reg required to be
1288 in class CLASS, return the class of reg to actually use.
1289 In general this is just CLASS; but on some machines
1290 in some cases it is preferable to use a more restrictive class.
1292 On the RS/6000, we have to return NO_REGS when we want to reload a
1293 floating-point CONST_DOUBLE to force it to be copied to memory.
1295 We also don't want to reload integer values into floating-point
1296 registers if we can at all help it. In fact, this can
1297 cause reload to die, if it tries to generate a reload of CTR
1298 into a FP register and discovers it doesn't have the memory location
1299 required.
1301 ??? Would it be a good idea to have reload do the converse, that is
1302 try to reload floating modes into FP registers if possible?
1305 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1306 rs6000_preferred_reload_class_ptr (X, CLASS)
1308 /* Return the register class of a scratch register needed to copy IN into
1309 or out of a register in CLASS in MODE. If it can be done directly,
1310 NO_REGS is returned. */
1312 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1313 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1315 /* Return the maximum number of consecutive registers
1316 needed to represent mode MODE in a register of class CLASS.
1318 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1319 a single reg is enough for two words, unless we have VSX, where the FP
1320 registers can hold 128 bits. */
1321 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1323 /* Stack layout; function entry, exit and calling. */
1325 /* Define this if pushing a word on the stack
1326 makes the stack pointer a smaller address. */
1327 #define STACK_GROWS_DOWNWARD 1
1329 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1330 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1332 /* Define this to nonzero if the nominal address of the stack frame
1333 is at the high-address end of the local variables;
1334 that is, each additional local variable allocated
1335 goes at a more negative offset in the frame.
1337 On the RS/6000, we grow upwards, from the area after the outgoing
1338 arguments. */
1339 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1340 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1342 /* Size of the fixed area on the stack */
1343 #define RS6000_SAVE_AREA \
1344 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1345 << (TARGET_64BIT ? 1 : 0))
1347 /* Stack offset for toc save slot. */
1348 #define RS6000_TOC_SAVE_SLOT \
1349 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1351 /* Align an address */
1352 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1354 /* Offset within stack frame to start allocating local variables at.
1355 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1356 first local allocated. Otherwise, it is the offset to the BEGINNING
1357 of the first local allocated.
1359 On the RS/6000, the frame pointer is the same as the stack pointer,
1360 except for dynamic allocations. So we start after the fixed area and
1361 outgoing parameter area.
1363 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1364 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1365 sizes of the fixed area and the parameter area must be a multiple of
1366 STACK_BOUNDARY. */
1368 #define RS6000_STARTING_FRAME_OFFSET \
1369 (cfun->calls_alloca \
1370 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1371 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1372 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1373 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1374 + RS6000_SAVE_AREA))
1376 /* Offset from the stack pointer register to an item dynamically
1377 allocated on the stack, e.g., by `alloca'.
1379 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1380 length of the outgoing arguments. The default is correct for most
1381 machines. See `function.c' for details.
1383 This value must be a multiple of STACK_BOUNDARY (hard coded in
1384 `emit-rtl.c'). */
1385 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1386 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1387 + STACK_POINTER_OFFSET, \
1388 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1390 /* If we generate an insn to push BYTES bytes,
1391 this says how many the stack pointer really advances by.
1392 On RS/6000, don't define this because there are no push insns. */
1393 /* #define PUSH_ROUNDING(BYTES) */
1395 /* Offset of first parameter from the argument pointer register value.
1396 On the RS/6000, we define the argument pointer to the start of the fixed
1397 area. */
1398 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1400 /* Offset from the argument pointer register value to the top of
1401 stack. This is different from FIRST_PARM_OFFSET because of the
1402 register save area. */
1403 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1405 /* Define this if stack space is still allocated for a parameter passed
1406 in a register. The value is the number of bytes allocated to this
1407 area. */
1408 #define REG_PARM_STACK_SPACE(FNDECL) \
1409 rs6000_reg_parm_stack_space ((FNDECL), false)
1411 /* Define this macro if space guaranteed when compiling a function body
1412 is different to space required when making a call, a situation that
1413 can arise with K&R style function definitions. */
1414 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1415 rs6000_reg_parm_stack_space ((FNDECL), true)
1417 /* Define this if the above stack space is to be considered part of the
1418 space allocated by the caller. */
1419 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1421 /* This is the difference between the logical top of stack and the actual sp.
1423 For the RS/6000, sp points past the fixed area. */
1424 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1426 /* Define this if the maximum size of all the outgoing args is to be
1427 accumulated and pushed during the prologue. The amount can be
1428 found in the variable crtl->outgoing_args_size. */
1429 #define ACCUMULATE_OUTGOING_ARGS 1
1431 /* Define how to find the value returned by a library function
1432 assuming the value has mode MODE. */
1434 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1436 /* DRAFT_V4_STRUCT_RET defaults off. */
1437 #define DRAFT_V4_STRUCT_RET 0
1439 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1440 #define DEFAULT_PCC_STRUCT_RETURN 0
1442 /* Mode of stack savearea.
1443 FUNCTION is VOIDmode because calling convention maintains SP.
1444 BLOCK needs Pmode for SP.
1445 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1446 #define STACK_SAVEAREA_MODE(LEVEL) \
1447 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1448 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1450 /* Minimum and maximum general purpose registers used to hold arguments. */
1451 #define GP_ARG_MIN_REG 3
1452 #define GP_ARG_MAX_REG 10
1453 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1455 /* Minimum and maximum floating point registers used to hold arguments. */
1456 #define FP_ARG_MIN_REG 33
1457 #define FP_ARG_AIX_MAX_REG 45
1458 #define FP_ARG_V4_MAX_REG 40
1459 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1460 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1461 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1463 /* Minimum and maximum AltiVec registers used to hold arguments. */
1464 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1465 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1466 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1468 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1469 #define AGGR_ARG_NUM_REG 8
1471 /* Return registers */
1472 #define GP_ARG_RETURN GP_ARG_MIN_REG
1473 #define FP_ARG_RETURN FP_ARG_MIN_REG
1474 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1475 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1476 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1477 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1478 ? (ALTIVEC_ARG_RETURN \
1479 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1480 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1482 /* Flags for the call/call_value rtl operations set up by function_arg */
1483 #define CALL_NORMAL 0x00000000 /* no special processing */
1484 /* Bits in 0x00000001 are unused. */
1485 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1486 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1487 #define CALL_LONG 0x00000008 /* always call indirect */
1488 #define CALL_LIBCALL 0x00000010 /* libcall */
1490 /* We don't have prologue and epilogue functions to save/restore
1491 everything for most ABIs. */
1492 #define WORLD_SAVE_P(INFO) 0
1494 /* 1 if N is a possible register number for a function value
1495 as seen by the caller.
1497 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1498 #define FUNCTION_VALUE_REGNO_P(N) \
1499 ((N) == GP_ARG_RETURN \
1500 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1501 && TARGET_HARD_FLOAT) \
1502 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1503 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1505 /* 1 if N is a possible register number for function argument passing.
1506 On RS/6000, these are r3-r10 and fp1-fp13.
1507 On AltiVec, v2 - v13 are used for passing vectors. */
1508 #define FUNCTION_ARG_REGNO_P(N) \
1509 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1510 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1511 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1512 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1513 && TARGET_HARD_FLOAT))
1515 /* Define a data type for recording info about an argument list
1516 during the scan of that argument list. This data type should
1517 hold all necessary information about the function itself
1518 and about the args processed so far, enough to enable macros
1519 such as FUNCTION_ARG to determine where the next arg should go.
1521 On the RS/6000, this is a structure. The first element is the number of
1522 total argument words, the second is used to store the next
1523 floating-point register number, and the third says how many more args we
1524 have prototype types for.
1526 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1527 the next available GP register, `fregno' is the next available FP
1528 register, and `words' is the number of words used on the stack.
1530 The varargs/stdarg support requires that this structure's size
1531 be a multiple of sizeof(int). */
1533 typedef struct rs6000_args
1535 int words; /* # words used for passing GP registers */
1536 int fregno; /* next available FP register */
1537 int vregno; /* next available AltiVec register */
1538 int nargs_prototype; /* # args left in the current prototype */
1539 int prototype; /* Whether a prototype was defined */
1540 int stdarg; /* Whether function is a stdarg function. */
1541 int call_cookie; /* Do special things for this call */
1542 int sysv_gregno; /* next available GP register */
1543 int intoffset; /* running offset in struct (darwin64) */
1544 int use_stack; /* any part of struct on stack (darwin64) */
1545 int floats_in_gpr; /* count of SFmode floats taking up
1546 GPR space (darwin64) */
1547 int named; /* false for varargs params */
1548 int escapes; /* if function visible outside tu */
1549 int libcall; /* If this is a compiler generated call. */
1550 } CUMULATIVE_ARGS;
1552 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1553 for a call to a function whose data type is FNTYPE.
1554 For a library call, FNTYPE is 0. */
1556 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1557 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1558 N_NAMED_ARGS, FNDECL, VOIDmode)
1560 /* Similar, but when scanning the definition of a procedure. We always
1561 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1563 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1564 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1565 1000, current_function_decl, VOIDmode)
1567 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1569 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1570 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1571 0, NULL_TREE, MODE)
1573 #define PAD_VARARGS_DOWN \
1574 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1576 /* Output assembler code to FILE to increment profiler label # LABELNO
1577 for profiling a function entry. */
1579 #define FUNCTION_PROFILER(FILE, LABELNO) \
1580 output_function_profiler ((FILE), (LABELNO));
1582 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1583 the stack pointer does not matter. No definition is equivalent to
1584 always zero.
1586 On the RS/6000, this is nonzero because we can restore the stack from
1587 its backpointer, which we maintain. */
1588 #define EXIT_IGNORE_STACK 1
1590 /* Define this macro as a C expression that is nonzero for registers
1591 that are used by the epilogue or the return' pattern. The stack
1592 and frame pointer registers are already be assumed to be used as
1593 needed. */
1595 #define EPILOGUE_USES(REGNO) \
1596 ((reload_completed && (REGNO) == LR_REGNO) \
1597 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1598 || (crtl->calls_eh_return \
1599 && TARGET_AIX \
1600 && (REGNO) == 2))
1603 /* Length in units of the trampoline for entering a nested function. */
1605 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1607 /* Definitions for __builtin_return_address and __builtin_frame_address.
1608 __builtin_return_address (0) should give link register (LR_REGNO), enable
1609 this. */
1610 /* This should be uncommented, so that the link register is used, but
1611 currently this would result in unmatched insns and spilling fixed
1612 registers so we'll leave it for another day. When these problems are
1613 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1614 (mrs) */
1615 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1617 /* Number of bytes into the frame return addresses can be found. See
1618 rs6000_stack_info in rs6000.c for more information on how the different
1619 abi's store the return address. */
1620 #define RETURN_ADDRESS_OFFSET \
1621 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1623 /* The current return address is in link register (65). The return address
1624 of anything farther back is accessed normally at an offset of 8 from the
1625 frame pointer. */
1626 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1627 (rs6000_return_addr (COUNT, FRAME))
1630 /* Definitions for register eliminations.
1632 We have two registers that can be eliminated on the RS/6000. First, the
1633 frame pointer register can often be eliminated in favor of the stack
1634 pointer register. Secondly, the argument pointer register can always be
1635 eliminated; it is replaced with either the stack or frame pointer.
1637 In addition, we use the elimination mechanism to see if r30 is needed
1638 Initially we assume that it isn't. If it is, we spill it. This is done
1639 by making it an eliminable register. We replace it with itself so that
1640 if it isn't needed, then existing uses won't be modified. */
1642 /* This is an array of structures. Each structure initializes one pair
1643 of eliminable registers. The "from" register number is given first,
1644 followed by "to". Eliminations of the same "from" register are listed
1645 in order of preference. */
1646 #define ELIMINABLE_REGS \
1647 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1648 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1649 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1650 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1651 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1652 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1654 /* Define the offset between two registers, one to be eliminated, and the other
1655 its replacement, at the start of a routine. */
1656 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1657 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1659 /* Addressing modes, and classification of registers for them. */
1661 #define HAVE_PRE_DECREMENT 1
1662 #define HAVE_PRE_INCREMENT 1
1663 #define HAVE_PRE_MODIFY_DISP 1
1664 #define HAVE_PRE_MODIFY_REG 1
1666 /* Macros to check register numbers against specific register classes. */
1668 /* These assume that REGNO is a hard or pseudo reg number.
1669 They give nonzero only if REGNO is a hard reg of the suitable class
1670 or a pseudo reg currently allocated to a suitable hard reg.
1671 Since they use reg_renumber, they are safe only once reg_renumber
1672 has been allocated, which happens in reginfo.c during register
1673 allocation. */
1675 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1676 ((REGNO) < FIRST_PSEUDO_REGISTER \
1677 ? (REGNO) <= 31 || (REGNO) == 67 \
1678 || (REGNO) == FRAME_POINTER_REGNUM \
1679 : (reg_renumber[REGNO] >= 0 \
1680 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1681 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1683 #define REGNO_OK_FOR_BASE_P(REGNO) \
1684 ((REGNO) < FIRST_PSEUDO_REGISTER \
1685 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1686 || (REGNO) == FRAME_POINTER_REGNUM \
1687 : (reg_renumber[REGNO] > 0 \
1688 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1689 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1691 /* Nonzero if X is a hard reg that can be used as an index
1692 or if it is a pseudo reg in the non-strict case. */
1693 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1694 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1695 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1697 /* Nonzero if X is a hard reg that can be used as a base reg
1698 or if it is a pseudo reg in the non-strict case. */
1699 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1700 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1701 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1704 /* Maximum number of registers that can appear in a valid memory address. */
1706 #define MAX_REGS_PER_ADDRESS 2
1708 /* Recognize any constant value that is a valid address. */
1710 #define CONSTANT_ADDRESS_P(X) \
1711 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1712 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1713 || GET_CODE (X) == HIGH)
1715 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1716 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1717 && EASY_VECTOR_15((n) >> 1) \
1718 && ((n) & 1) == 0)
1720 #define EASY_VECTOR_MSB(n,mode) \
1721 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1722 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1725 /* Try a machine-dependent way of reloading an illegitimate address
1726 operand. If we find one, push the reload and jump to WIN. This
1727 macro is used in only one place: `find_reloads_address' in reload.c.
1729 Implemented on rs6000 by rs6000_legitimize_reload_address.
1730 Note that (X) is evaluated twice; this is safe in current usage. */
1732 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1733 do { \
1734 int win; \
1735 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1736 (int)(TYPE), (IND_LEVELS), &win); \
1737 if ( win ) \
1738 goto WIN; \
1739 } while (0)
1741 #define FIND_BASE_TERM rs6000_find_base_term
1743 /* The register number of the register used to address a table of
1744 static data addresses in memory. In some cases this register is
1745 defined by a processor's "application binary interface" (ABI).
1746 When this macro is defined, RTL is generated for this register
1747 once, as with the stack pointer and frame pointer registers. If
1748 this macro is not defined, it is up to the machine-dependent files
1749 to allocate such a register (if necessary). */
1751 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1752 #define PIC_OFFSET_TABLE_REGNUM \
1753 (TARGET_TOC ? TOC_REGISTER \
1754 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1755 : INVALID_REGNUM)
1757 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1759 /* Define this macro if the register defined by
1760 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1761 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1763 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1765 /* A C expression that is nonzero if X is a legitimate immediate
1766 operand on the target machine when generating position independent
1767 code. You can assume that X satisfies `CONSTANT_P', so you need
1768 not check this. You can also assume FLAG_PIC is true, so you need
1769 not check it either. You need not define this macro if all
1770 constants (including `SYMBOL_REF') can be immediate operands when
1771 generating position independent code. */
1773 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1775 /* Specify the machine mode that this machine uses
1776 for the index in the tablejump instruction. */
1777 #define CASE_VECTOR_MODE SImode
1779 /* Define as C expression which evaluates to nonzero if the tablejump
1780 instruction expects the table to contain offsets from the address of the
1781 table.
1782 Do not define this if the table should contain absolute addresses. */
1783 #define CASE_VECTOR_PC_RELATIVE 1
1785 /* Define this as 1 if `char' should by default be signed; else as 0. */
1786 #define DEFAULT_SIGNED_CHAR 0
1788 /* An integer expression for the size in bits of the largest integer machine
1789 mode that should actually be used. */
1791 /* Allow pairs of registers to be used, which is the intent of the default. */
1792 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1794 /* Max number of bytes we can move from memory to memory
1795 in one reasonably fast instruction. */
1796 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1797 #define MAX_MOVE_MAX 8
1799 /* Nonzero if access to memory by bytes is no faster than for words.
1800 Also nonzero if doing byte operations (specifically shifts) in registers
1801 is undesirable. */
1802 #define SLOW_BYTE_ACCESS 1
1804 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1805 will either zero-extend or sign-extend. The value of this macro should
1806 be the code that says which one of the two operations is implicitly
1807 done, UNKNOWN if none. */
1808 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1810 /* Define if loading short immediate values into registers sign extends. */
1811 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1813 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1814 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1815 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1817 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1818 zero. The hardware instructions added in Power9 and the sequences using
1819 popcount return 32 or 64. */
1820 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1821 (TARGET_CTZ || TARGET_POPCNTD \
1822 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1823 : ((VALUE) = -1, 2))
1825 /* Specify the machine mode that pointers have.
1826 After generation of rtl, the compiler makes no further distinction
1827 between pointers and any other objects of this machine mode. */
1828 extern scalar_int_mode rs6000_pmode;
1829 #define Pmode rs6000_pmode
1831 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1832 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1834 /* Mode of a function address in a call instruction (for indexing purposes).
1835 Doesn't matter on RS/6000. */
1836 #define FUNCTION_MODE SImode
1838 /* Define this if addresses of constant functions
1839 shouldn't be put through pseudo regs where they can be cse'd.
1840 Desirable on machines where ordinary constants are expensive
1841 but a CALL with constant address is cheap. */
1842 #define NO_FUNCTION_CSE 1
1844 /* Define this to be nonzero if shift instructions ignore all but the low-order
1845 few bits.
1847 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1848 have been dropped from the PowerPC architecture. */
1849 #define SHIFT_COUNT_TRUNCATED 0
1851 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1852 should be adjusted to reflect any required changes. This macro is used when
1853 there is some systematic length adjustment required that would be difficult
1854 to express in the length attribute. */
1856 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1858 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1859 COMPARE, return the mode to be used for the comparison. For
1860 floating-point, CCFPmode should be used. CCUNSmode should be used
1861 for unsigned comparisons. CCEQmode should be used when we are
1862 doing an inequality comparison on the result of a
1863 comparison. CCmode should be used in all other cases. */
1865 #define SELECT_CC_MODE(OP,X,Y) \
1866 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1867 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1868 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1869 ? CCEQmode : CCmode))
1871 /* Can the condition code MODE be safely reversed? This is safe in
1872 all cases on this port, because at present it doesn't use the
1873 trapping FP comparisons (fcmpo). */
1874 #define REVERSIBLE_CC_MODE(MODE) 1
1876 /* Given a condition code and a mode, return the inverse condition. */
1877 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1880 /* Target cpu costs. */
1882 struct processor_costs {
1883 const int mulsi; /* cost of SImode multiplication. */
1884 const int mulsi_const; /* cost of SImode multiplication by constant. */
1885 const int mulsi_const9; /* cost of SImode mult by short constant. */
1886 const int muldi; /* cost of DImode multiplication. */
1887 const int divsi; /* cost of SImode division. */
1888 const int divdi; /* cost of DImode division. */
1889 const int fp; /* cost of simple SFmode and DFmode insns. */
1890 const int dmul; /* cost of DFmode multiplication (and fmadd). */
1891 const int sdiv; /* cost of SFmode division (fdivs). */
1892 const int ddiv; /* cost of DFmode division (fdiv). */
1893 const int cache_line_size; /* cache line size in bytes. */
1894 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
1895 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
1896 const int simultaneous_prefetches; /* number of parallel prefetch
1897 operations. */
1898 const int sfdf_convert; /* cost of SF->DF conversion. */
1901 extern const struct processor_costs *rs6000_cost;
1903 /* Control the assembler format that we output. */
1905 /* A C string constant describing how to begin a comment in the target
1906 assembler language. The compiler assumes that the comment will end at
1907 the end of the line. */
1908 #define ASM_COMMENT_START " #"
1910 /* Flag to say the TOC is initialized */
1911 extern int toc_initialized;
1913 /* Macro to output a special constant pool entry. Go to WIN if we output
1914 it. Otherwise, it is written the usual way.
1916 On the RS/6000, toc entries are handled this way. */
1918 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1919 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1921 output_toc (FILE, X, LABELNO, MODE); \
1922 goto WIN; \
1926 #ifdef HAVE_GAS_WEAK
1927 #define RS6000_WEAK 1
1928 #else
1929 #define RS6000_WEAK 0
1930 #endif
1932 #if RS6000_WEAK
1933 /* Used in lieu of ASM_WEAKEN_LABEL. */
1934 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1935 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
1936 #endif
1938 #if HAVE_GAS_WEAKREF
1939 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1940 do \
1942 fputs ("\t.weakref\t", (FILE)); \
1943 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1944 fputs (", ", (FILE)); \
1945 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1946 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1947 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1949 fputs ("\n\t.weakref\t.", (FILE)); \
1950 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1951 fputs (", .", (FILE)); \
1952 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1954 fputc ('\n', (FILE)); \
1955 } while (0)
1956 #endif
1958 /* This implements the `alias' attribute. */
1959 #undef ASM_OUTPUT_DEF_FROM_DECLS
1960 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1961 do \
1963 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1964 const char *name = IDENTIFIER_POINTER (TARGET); \
1965 if (TREE_CODE (DECL) == FUNCTION_DECL \
1966 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1968 if (TREE_PUBLIC (DECL)) \
1970 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1972 fputs ("\t.globl\t.", FILE); \
1973 RS6000_OUTPUT_BASENAME (FILE, alias); \
1974 putc ('\n', FILE); \
1977 else if (TARGET_XCOFF) \
1979 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1981 fputs ("\t.lglobl\t.", FILE); \
1982 RS6000_OUTPUT_BASENAME (FILE, alias); \
1983 putc ('\n', FILE); \
1984 fputs ("\t.lglobl\t", FILE); \
1985 RS6000_OUTPUT_BASENAME (FILE, alias); \
1986 putc ('\n', FILE); \
1989 fputs ("\t.set\t.", FILE); \
1990 RS6000_OUTPUT_BASENAME (FILE, alias); \
1991 fputs (",.", FILE); \
1992 RS6000_OUTPUT_BASENAME (FILE, name); \
1993 fputc ('\n', FILE); \
1995 ASM_OUTPUT_DEF (FILE, alias, name); \
1997 while (0)
1999 #define TARGET_ASM_FILE_START rs6000_file_start
2001 /* Output to assembler file text saying following lines
2002 may contain character constants, extra white space, comments, etc. */
2004 #define ASM_APP_ON ""
2006 /* Output to assembler file text saying following lines
2007 no longer contain unusual constructs. */
2009 #define ASM_APP_OFF ""
2011 /* How to refer to registers in assembler output.
2012 This sequence is indexed by compiler's hard-register-number (see above). */
2014 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */
2016 #define REGISTER_NAMES \
2018 &rs6000_reg_names[ 0][0], /* r0 */ \
2019 &rs6000_reg_names[ 1][0], /* r1 */ \
2020 &rs6000_reg_names[ 2][0], /* r2 */ \
2021 &rs6000_reg_names[ 3][0], /* r3 */ \
2022 &rs6000_reg_names[ 4][0], /* r4 */ \
2023 &rs6000_reg_names[ 5][0], /* r5 */ \
2024 &rs6000_reg_names[ 6][0], /* r6 */ \
2025 &rs6000_reg_names[ 7][0], /* r7 */ \
2026 &rs6000_reg_names[ 8][0], /* r8 */ \
2027 &rs6000_reg_names[ 9][0], /* r9 */ \
2028 &rs6000_reg_names[10][0], /* r10 */ \
2029 &rs6000_reg_names[11][0], /* r11 */ \
2030 &rs6000_reg_names[12][0], /* r12 */ \
2031 &rs6000_reg_names[13][0], /* r13 */ \
2032 &rs6000_reg_names[14][0], /* r14 */ \
2033 &rs6000_reg_names[15][0], /* r15 */ \
2034 &rs6000_reg_names[16][0], /* r16 */ \
2035 &rs6000_reg_names[17][0], /* r17 */ \
2036 &rs6000_reg_names[18][0], /* r18 */ \
2037 &rs6000_reg_names[19][0], /* r19 */ \
2038 &rs6000_reg_names[20][0], /* r20 */ \
2039 &rs6000_reg_names[21][0], /* r21 */ \
2040 &rs6000_reg_names[22][0], /* r22 */ \
2041 &rs6000_reg_names[23][0], /* r23 */ \
2042 &rs6000_reg_names[24][0], /* r24 */ \
2043 &rs6000_reg_names[25][0], /* r25 */ \
2044 &rs6000_reg_names[26][0], /* r26 */ \
2045 &rs6000_reg_names[27][0], /* r27 */ \
2046 &rs6000_reg_names[28][0], /* r28 */ \
2047 &rs6000_reg_names[29][0], /* r29 */ \
2048 &rs6000_reg_names[30][0], /* r30 */ \
2049 &rs6000_reg_names[31][0], /* r31 */ \
2051 &rs6000_reg_names[32][0], /* fr0 */ \
2052 &rs6000_reg_names[33][0], /* fr1 */ \
2053 &rs6000_reg_names[34][0], /* fr2 */ \
2054 &rs6000_reg_names[35][0], /* fr3 */ \
2055 &rs6000_reg_names[36][0], /* fr4 */ \
2056 &rs6000_reg_names[37][0], /* fr5 */ \
2057 &rs6000_reg_names[38][0], /* fr6 */ \
2058 &rs6000_reg_names[39][0], /* fr7 */ \
2059 &rs6000_reg_names[40][0], /* fr8 */ \
2060 &rs6000_reg_names[41][0], /* fr9 */ \
2061 &rs6000_reg_names[42][0], /* fr10 */ \
2062 &rs6000_reg_names[43][0], /* fr11 */ \
2063 &rs6000_reg_names[44][0], /* fr12 */ \
2064 &rs6000_reg_names[45][0], /* fr13 */ \
2065 &rs6000_reg_names[46][0], /* fr14 */ \
2066 &rs6000_reg_names[47][0], /* fr15 */ \
2067 &rs6000_reg_names[48][0], /* fr16 */ \
2068 &rs6000_reg_names[49][0], /* fr17 */ \
2069 &rs6000_reg_names[50][0], /* fr18 */ \
2070 &rs6000_reg_names[51][0], /* fr19 */ \
2071 &rs6000_reg_names[52][0], /* fr20 */ \
2072 &rs6000_reg_names[53][0], /* fr21 */ \
2073 &rs6000_reg_names[54][0], /* fr22 */ \
2074 &rs6000_reg_names[55][0], /* fr23 */ \
2075 &rs6000_reg_names[56][0], /* fr24 */ \
2076 &rs6000_reg_names[57][0], /* fr25 */ \
2077 &rs6000_reg_names[58][0], /* fr26 */ \
2078 &rs6000_reg_names[59][0], /* fr27 */ \
2079 &rs6000_reg_names[60][0], /* fr28 */ \
2080 &rs6000_reg_names[61][0], /* fr29 */ \
2081 &rs6000_reg_names[62][0], /* fr30 */ \
2082 &rs6000_reg_names[63][0], /* fr31 */ \
2084 &rs6000_reg_names[64][0], /* was mq */ \
2085 &rs6000_reg_names[65][0], /* lr */ \
2086 &rs6000_reg_names[66][0], /* ctr */ \
2087 &rs6000_reg_names[67][0], /* ap */ \
2089 &rs6000_reg_names[68][0], /* cr0 */ \
2090 &rs6000_reg_names[69][0], /* cr1 */ \
2091 &rs6000_reg_names[70][0], /* cr2 */ \
2092 &rs6000_reg_names[71][0], /* cr3 */ \
2093 &rs6000_reg_names[72][0], /* cr4 */ \
2094 &rs6000_reg_names[73][0], /* cr5 */ \
2095 &rs6000_reg_names[74][0], /* cr6 */ \
2096 &rs6000_reg_names[75][0], /* cr7 */ \
2098 &rs6000_reg_names[76][0], /* ca */ \
2100 &rs6000_reg_names[77][0], /* v0 */ \
2101 &rs6000_reg_names[78][0], /* v1 */ \
2102 &rs6000_reg_names[79][0], /* v2 */ \
2103 &rs6000_reg_names[80][0], /* v3 */ \
2104 &rs6000_reg_names[81][0], /* v4 */ \
2105 &rs6000_reg_names[82][0], /* v5 */ \
2106 &rs6000_reg_names[83][0], /* v6 */ \
2107 &rs6000_reg_names[84][0], /* v7 */ \
2108 &rs6000_reg_names[85][0], /* v8 */ \
2109 &rs6000_reg_names[86][0], /* v9 */ \
2110 &rs6000_reg_names[87][0], /* v10 */ \
2111 &rs6000_reg_names[88][0], /* v11 */ \
2112 &rs6000_reg_names[89][0], /* v12 */ \
2113 &rs6000_reg_names[90][0], /* v13 */ \
2114 &rs6000_reg_names[91][0], /* v14 */ \
2115 &rs6000_reg_names[92][0], /* v15 */ \
2116 &rs6000_reg_names[93][0], /* v16 */ \
2117 &rs6000_reg_names[94][0], /* v17 */ \
2118 &rs6000_reg_names[95][0], /* v18 */ \
2119 &rs6000_reg_names[96][0], /* v19 */ \
2120 &rs6000_reg_names[97][0], /* v20 */ \
2121 &rs6000_reg_names[98][0], /* v21 */ \
2122 &rs6000_reg_names[99][0], /* v22 */ \
2123 &rs6000_reg_names[100][0], /* v23 */ \
2124 &rs6000_reg_names[101][0], /* v24 */ \
2125 &rs6000_reg_names[102][0], /* v25 */ \
2126 &rs6000_reg_names[103][0], /* v26 */ \
2127 &rs6000_reg_names[104][0], /* v27 */ \
2128 &rs6000_reg_names[105][0], /* v28 */ \
2129 &rs6000_reg_names[106][0], /* v29 */ \
2130 &rs6000_reg_names[107][0], /* v30 */ \
2131 &rs6000_reg_names[108][0], /* v31 */ \
2132 &rs6000_reg_names[109][0], /* vrsave */ \
2133 &rs6000_reg_names[110][0], /* vscr */ \
2134 &rs6000_reg_names[111][0], /* sfp */ \
2135 &rs6000_reg_names[112][0], /* tfhar */ \
2136 &rs6000_reg_names[113][0], /* tfiar */ \
2137 &rs6000_reg_names[114][0], /* texasr */ \
2140 /* Table of additional register names to use in user input. */
2142 #define ADDITIONAL_REGISTER_NAMES \
2143 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2144 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2145 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2146 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2147 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2148 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2149 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2150 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2151 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2152 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2153 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2154 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2155 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2156 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2157 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2158 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2159 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2160 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2161 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2162 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2163 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2164 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2165 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2166 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2167 {"vrsave", 109}, {"vscr", 110}, \
2168 /* no additional names for: lr, ctr, ap */ \
2169 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2170 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2171 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2172 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2173 {"xer", 76}, \
2174 /* VSX registers overlaid on top of FR, Altivec registers */ \
2175 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2176 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2177 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2178 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2179 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2180 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2181 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2182 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2183 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2184 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2185 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2186 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2187 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2188 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2189 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2190 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
2191 /* Transactional Memory Facility (HTM) Registers. */ \
2192 {"tfhar", 112}, {"tfiar", 113}, {"texasr", 114}, \
2195 /* This is how to output an element of a case-vector that is relative. */
2197 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2198 do { char buf[100]; \
2199 fputs ("\t.long ", FILE); \
2200 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2201 assemble_name (FILE, buf); \
2202 putc ('-', FILE); \
2203 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2204 assemble_name (FILE, buf); \
2205 putc ('\n', FILE); \
2206 } while (0)
2208 /* This is how to output an assembler line
2209 that says to advance the location counter
2210 to a multiple of 2**LOG bytes. */
2212 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2213 if ((LOG) != 0) \
2214 fprintf (FILE, "\t.align %d\n", (LOG))
2216 /* How to align the given loop. */
2217 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2219 /* Alignment guaranteed by __builtin_malloc. */
2220 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2221 However, specifying the stronger guarantee currently leads to
2222 a regression in SPEC CPU2006 437.leslie3d. The stronger
2223 guarantee should be implemented here once that's fixed. */
2224 #define MALLOC_ABI_ALIGNMENT (64)
2226 /* Pick up the return address upon entry to a procedure. Used for
2227 dwarf2 unwind information. This also enables the table driven
2228 mechanism. */
2230 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2231 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2233 /* Describe how we implement __builtin_eh_return. */
2234 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2235 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2237 /* Print operand X (an rtx) in assembler syntax to file FILE.
2238 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2239 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2241 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2243 /* Define which CODE values are valid. */
2245 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2247 /* Print a memory address as an operand to reference that memory location. */
2249 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2251 /* For switching between functions with different target attributes. */
2252 #define SWITCHABLE_TARGET 1
2254 /* uncomment for disabling the corresponding default options */
2255 /* #define MACHINE_no_sched_interblock */
2256 /* #define MACHINE_no_sched_speculative */
2257 /* #define MACHINE_no_sched_speculative_load */
2259 /* General flags. */
2260 extern int frame_pointer_needed;
2262 /* Classification of the builtin functions as to which switches enable the
2263 builtin, and what attributes it should have. We used to use the target
2264 flags macros, but we've run out of bits, so we now map the options into new
2265 settings used here. */
2267 /* Builtin attributes. */
2268 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2269 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2270 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2271 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2272 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2273 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2274 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2275 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2277 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2278 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor
2279 modifies global state. */
2280 #define RS6000_BTC_PURE 0x00000200 /* reads global
2281 state/mem and does
2282 not modify global state. */
2283 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2284 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2286 /* Miscellaneous information. */
2287 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
2288 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
2289 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */
2290 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */
2291 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
2293 /* Convenience macros to document the instruction type. */
2294 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2295 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2297 /* Builtin targets. For now, we reuse the masks for those options that are in
2298 target flags, and pick a random bit for ldbl128, which isn't in
2299 target_flags. */
2300 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2301 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2302 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
2303 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2304 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2305 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
2306 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
2307 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2308 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2309 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2310 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2311 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2312 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2313 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2314 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2315 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2316 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2317 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2318 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
2319 #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */
2320 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_KEYWORD /* IEEE 128-bit float. */
2321 #define RS6000_BTM_FLOAT128_HW MASK_FLOAT128_HW /* IEEE 128-bit float h/w. */
2323 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2324 | RS6000_BTM_VSX \
2325 | RS6000_BTM_P8_VECTOR \
2326 | RS6000_BTM_P9_VECTOR \
2327 | RS6000_BTM_P9_MISC \
2328 | RS6000_BTM_MODULO \
2329 | RS6000_BTM_CRYPTO \
2330 | RS6000_BTM_FRE \
2331 | RS6000_BTM_FRES \
2332 | RS6000_BTM_FRSQRTE \
2333 | RS6000_BTM_FRSQRTES \
2334 | RS6000_BTM_HTM \
2335 | RS6000_BTM_POPCNTD \
2336 | RS6000_BTM_CELL \
2337 | RS6000_BTM_DFP \
2338 | RS6000_BTM_HARD_FLOAT \
2339 | RS6000_BTM_LDBL128 \
2340 | RS6000_BTM_POWERPC64 \
2341 | RS6000_BTM_FLOAT128 \
2342 | RS6000_BTM_FLOAT128_HW)
2344 /* Define builtin enum index. */
2346 #undef RS6000_BUILTIN_0
2347 #undef RS6000_BUILTIN_1
2348 #undef RS6000_BUILTIN_2
2349 #undef RS6000_BUILTIN_3
2350 #undef RS6000_BUILTIN_A
2351 #undef RS6000_BUILTIN_D
2352 #undef RS6000_BUILTIN_H
2353 #undef RS6000_BUILTIN_P
2354 #undef RS6000_BUILTIN_X
2356 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2357 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2358 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2359 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2360 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2361 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2362 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2363 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2364 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2366 enum rs6000_builtins
2368 #include "rs6000-builtin.def"
2370 RS6000_BUILTIN_COUNT
2373 #undef RS6000_BUILTIN_0
2374 #undef RS6000_BUILTIN_1
2375 #undef RS6000_BUILTIN_2
2376 #undef RS6000_BUILTIN_3
2377 #undef RS6000_BUILTIN_A
2378 #undef RS6000_BUILTIN_D
2379 #undef RS6000_BUILTIN_H
2380 #undef RS6000_BUILTIN_P
2381 #undef RS6000_BUILTIN_X
2383 enum rs6000_builtin_type_index
2385 RS6000_BTI_NOT_OPAQUE,
2386 RS6000_BTI_opaque_V4SI,
2387 RS6000_BTI_V16QI, /* __vector signed char */
2388 RS6000_BTI_V1TI,
2389 RS6000_BTI_V2DI,
2390 RS6000_BTI_V2DF,
2391 RS6000_BTI_V4HI,
2392 RS6000_BTI_V4SI,
2393 RS6000_BTI_V4SF,
2394 RS6000_BTI_V8HI,
2395 RS6000_BTI_unsigned_V16QI, /* __vector unsigned char */
2396 RS6000_BTI_unsigned_V1TI,
2397 RS6000_BTI_unsigned_V8HI,
2398 RS6000_BTI_unsigned_V4SI,
2399 RS6000_BTI_unsigned_V2DI,
2400 RS6000_BTI_bool_char, /* __bool char */
2401 RS6000_BTI_bool_short, /* __bool short */
2402 RS6000_BTI_bool_int, /* __bool int */
2403 RS6000_BTI_bool_long_long, /* __bool long long */
2404 RS6000_BTI_pixel, /* __pixel (16 bits arranged as 4
2405 channels of 1, 5, 5, and 5 bits
2406 respectively as packed with the
2407 vpkpx insn. __pixel is only
2408 meaningful as a vector type.
2409 There is no corresponding scalar
2410 __pixel data type.) */
2411 RS6000_BTI_bool_V16QI, /* __vector __bool char */
2412 RS6000_BTI_bool_V8HI, /* __vector __bool short */
2413 RS6000_BTI_bool_V4SI, /* __vector __bool int */
2414 RS6000_BTI_bool_V2DI, /* __vector __bool long */
2415 RS6000_BTI_pixel_V8HI, /* __vector __pixel */
2416 RS6000_BTI_long, /* long_integer_type_node */
2417 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */
2418 RS6000_BTI_long_long, /* long_long_integer_type_node */
2419 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */
2420 RS6000_BTI_INTQI, /* (signed) intQI_type_node */
2421 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */
2422 RS6000_BTI_INTHI, /* intHI_type_node */
2423 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */
2424 RS6000_BTI_INTSI, /* intSI_type_node (signed) */
2425 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */
2426 RS6000_BTI_INTDI, /* intDI_type_node */
2427 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */
2428 RS6000_BTI_INTTI, /* intTI_type_node */
2429 RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */
2430 RS6000_BTI_float, /* float_type_node */
2431 RS6000_BTI_double, /* double_type_node */
2432 RS6000_BTI_long_double, /* long_double_type_node */
2433 RS6000_BTI_dfloat64, /* dfloat64_type_node */
2434 RS6000_BTI_dfloat128, /* dfloat128_type_node */
2435 RS6000_BTI_void, /* void_type_node */
2436 RS6000_BTI_ieee128_float, /* ieee 128-bit floating point */
2437 RS6000_BTI_ibm128_float, /* IBM 128-bit floating point */
2438 RS6000_BTI_const_str, /* pointer to const char * */
2439 RS6000_BTI_MAX
2443 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2444 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2445 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2446 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2447 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2448 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2449 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2450 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2451 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2452 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2453 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2454 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2455 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2456 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2457 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2458 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2459 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2460 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2461 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2462 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2463 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2464 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2465 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2466 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2468 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2469 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2470 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2471 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2472 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2473 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2474 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2475 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2476 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2477 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2478 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2479 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2480 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2481 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2482 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2483 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2484 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2485 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2486 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2487 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2488 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2489 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2490 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2492 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX];
2493 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
2495 #define TARGET_SUPPORTS_WIDE_INT 1
2497 #if (GCC_VERSION >= 3000)
2498 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128
2499 #endif