| blob | 49503d180efe5946470916b7358ebdd54f5e92a9 |
1 /* Definitions of target machine for GNU compiler for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
27 #define TARGET_VERSION \
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
44 break; \
45 case PROCESSOR_SH2: \
47 break; \
48 case PROCESSOR_SH2E: \
50 break; \
51 case PROCESSOR_SH3: \
54 if (TARGET_HARD_SH4) \
56 break; \
57 case PROCESSOR_SH3E: \
59 break; \
60 case PROCESSOR_SH4: \
62 break; \
63 case PROCESSOR_SH5: \
64 { \
69 if (! TARGET_FPU_DOUBLE) \
71 } \
72 } \
73 if (TARGET_HITACHI) \
75 builtin_define (TARGET_LITTLE_ENDIAN \
77 if (flag_pic) \
78 { \
81 } \
82 TARGET_OBJFMT_CPP_BUILTINS (); \
83 } while (0)
85 /* We can not debug without a frame pointer. */
86 /* #define CAN_DEBUG_WITHOUT_FP */
88 #define CONDITIONAL_REGISTER_USAGE do \
89 { \
90 int regno; \
91 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
92 if (! VALID_REGISTER_P (regno)) \
93 fixed_regs[regno] = call_used_regs[regno] = 1; \
95 if (TARGET_SH5) \
96 call_used_regs[FIRST_GENERAL_REG + 8] \
97 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
98 if (TARGET_SHMEDIA) \
99 { \
100 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
101 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
102 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
103 } \
104 if (flag_pic) \
105 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
107 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
108 { \
109 call_used_regs[MACH_REG] = 0; \
110 call_used_regs[MACL_REG] = 0; \
111 } \
112 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
113 regno <= LAST_FP_REG; regno += 2) \
114 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
115 if (TARGET_SHMEDIA) \
116 { \
117 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
118 if (! fixed_regs[regno] && call_used_regs[regno]) \
119 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
120 } \
121 else \
122 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
123 if (! fixed_regs[regno] && call_used_regs[regno]) \
124 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
125 } while (0)
126 \f
127 /* ??? Need to write documentation for all SH options and add it to the
128 invoke.texi file. */
130 /* Run-time compilation parameters selecting different hardware subsets. */
133 #define ISIZE_BIT (1<<1)
134 #define DALIGN_BIT (1<<6)
135 #define SH1_BIT (1<<8)
136 #define SH2_BIT (1<<9)
137 #define SH3_BIT (1<<10)
138 #define SH_E_BIT (1<<11)
139 #define HARD_SH4_BIT (1<<5)
140 #define FPU_SINGLE_BIT (1<<7)
141 #define SH4_BIT (1<<12)
142 #define FMOVD_BIT (1<<4)
143 #define SH5_BIT (1<<0)
144 #define SPACE_BIT (1<<13)
145 #define BIGTABLE_BIT (1<<14)
146 #define RELAX_BIT (1<<15)
147 #define USERMODE_BIT (1<<16)
148 #define HITACHI_BIT (1<<22)
149 #define NOMACSAVE_BIT (1<<23)
150 #define PREFERGOT_BIT (1<<24)
151 #define PADSTRUCT_BIT (1<<28)
152 #define LITTLE_ENDIAN_BIT (1<<29)
153 #define IEEE_BIT (1<<30)
155 /* Nonzero if we should dump out instruction size info. */
156 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
158 /* Nonzero to align doubles on 64 bit boundaries. */
159 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
161 /* Nonzero if we should generate code using type 1 insns. */
162 #define TARGET_SH1 (target_flags & SH1_BIT)
164 /* Nonzero if we should generate code using type 2 insns. */
165 #define TARGET_SH2 (target_flags & SH2_BIT)
167 /* Nonzero if we should generate code using type 2E insns. */
168 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
170 /* Nonzero if we should generate code using type 3 insns. */
171 #define TARGET_SH3 (target_flags & SH3_BIT)
173 /* Nonzero if we should generate code using type 3E insns. */
174 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
176 /* Nonzero if the cache line size is 32. */
177 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
179 /* Nonzero if we schedule for a superscalar implementation. */
180 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
182 /* Nonzero if the target has separate instruction and data caches. */
183 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
185 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
186 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
188 /* Nonzero if the default precision of th FPU is single */
189 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
191 /* Nonzero if a double-precision FPU is available. */
192 #define TARGET_FPU_DOUBLE (target_flags & SH4_BIT)
194 /* Nonzero if an FPU is available. */
195 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
197 /* Nonzero if we should generate code using type 4 insns. */
198 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
200 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
201 #define TARGET_SH5 (target_flags & SH5_BIT)
203 /* Nonzero if we should generate code using the SHcompact instruction
204 set and 32-bit ABI. */
205 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
207 /* Nonzero if we should generate code using the SHmedia instruction
208 set and ABI. */
209 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
211 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
212 ABI. */
213 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
214 && (target_flags & SH_E_BIT))
216 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
217 ABI. */
218 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
219 && ! (target_flags & SH_E_BIT))
221 /* Nonzero if we should generate code using SHmedia FPU instructions. */
222 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
223 /* Nonzero if we should generate fmovd. */
224 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
226 /* Nonzero if we respect NANs. */
227 #define TARGET_IEEE (target_flags & IEEE_BIT)
229 /* Nonzero if we should generate smaller code rather than faster code. */
230 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
232 /* Nonzero to use long jump tables. */
233 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
235 /* Nonzero to generate pseudo-ops needed by the assembler and linker
236 to do function call relaxing. */
237 #define TARGET_RELAX (target_flags & RELAX_BIT)
239 /* Nonzero if using Hitachi's calling convention. */
240 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
242 /* Nonzero if not saving macl/mach when using -mhitachi */
243 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
245 /* Nonzero if padding structures to a multiple of 4 bytes. This is
246 incompatible with Hitachi's compiler, and gives unusual structure layouts
247 which confuse programmers.
248 ??? This option is not useful, but is retained in case there are people
249 who are still relying on it. It may be deleted in the future. */
250 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
252 /* Nonzero if generating code for a little endian SH. */
253 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
255 /* Nonzero if we should do everything in userland. */
256 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
258 /* Nonzero if we should prefer @GOT calls when generating PIC. */
259 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
261 #define SELECT_SH1 (SH1_BIT)
262 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
263 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
264 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
265 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
266 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
267 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
268 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
269 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
270 #define SELECT_SH5_64 (SH5_BIT | SH4_BIT)
271 #define SELECT_SH5_64_NOFPU (SH5_BIT)
272 #define SELECT_SH5_32 (SH5_BIT | SH4_BIT | SH_E_BIT)
273 #define SELECT_SH5_32_NOFPU (SH5_BIT | SH_E_BIT)
274 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
275 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
277 /* Reset all target-selection flags. */
278 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
279 | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
281 #define TARGET_SWITCHES \
327 SUBTARGET_SWITCHES \
329 }
331 /* This are meant to be redefined in the host dependent files */
332 #define SUBTARGET_SWITCHES
334 /* This defaults us to big-endian. */
335 #ifndef TARGET_ENDIAN_DEFAULT
336 #define TARGET_ENDIAN_DEFAULT 0
337 #endif
339 #ifndef TARGET_CPU_DEFAULT
340 #define TARGET_CPU_DEFAULT SELECT_SH1
341 #endif
343 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
347 #ifndef SUBTARGET_CPP_SPEC
349 #endif
351 #ifndef SUBTARGET_EXTRA_SPECS
352 #define SUBTARGET_EXTRA_SPECS
353 #endif
355 #define EXTRA_SPECS \
364 SUBTARGET_EXTRA_SPECS
366 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
368 #else
370 #endif
372 #define SH_ASM_SPEC \
373 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
374 %(subtarget_asm_isa_spec)"
376 #define ASM_SPEC SH_ASM_SPEC
378 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
379 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
381 #else
383 #endif
384 #endif
390 #if TARGET_CPU_DEFAULT & SH5_BIT
391 #if TARGET_CPU_DEFAULT & SH_E_BIT
393 #else
396 #else
403 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
404 so that we can undo the damage without code replication. */
405 #define LINK_SPEC SH_LINK_SPEC
408 -m %(link_emul_prefix)\
409 %{m5-compact*|m5-32media*:32}\
410 %{m5-64media*:64}\
411 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
412 %(subtarget_link_emul_suffix) \
413 %{mrelax:-relax} %(subtarget_link_spec)"
415 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
416 do { \
417 if (LEVEL) \
418 flag_omit_frame_pointer = -1; \
419 if (SIZE) \
420 target_flags |= SPACE_BIT; \
421 } while (0)
423 #define ASSEMBLER_DIALECT assembler_dialect
427 #define OVERRIDE_OPTIONS \
428 do { \
429 int regno; \
430 \
431 sh_cpu = CPU_SH1; \
432 assembler_dialect = 0; \
433 if (TARGET_SH2) \
434 sh_cpu = CPU_SH2; \
435 if (TARGET_SH2E) \
436 sh_cpu = CPU_SH2E; \
437 if (TARGET_SH3) \
438 sh_cpu = CPU_SH3; \
439 if (TARGET_SH3E) \
440 sh_cpu = CPU_SH3E; \
441 if (TARGET_SH4) \
442 { \
443 assembler_dialect = 1; \
444 sh_cpu = CPU_SH4; \
445 } \
446 if (TARGET_SH5) \
447 { \
448 sh_cpu = CPU_SH5; \
449 target_flags |= DALIGN_BIT; \
450 if (TARGET_FPU_ANY \
451 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
452 target_flags |= FMOVD_BIT; \
453 if (TARGET_SHMEDIA) \
454 { \
456 flag_delayed_branch = 0; \
458 target_flags &= ~RELAX_BIT; \
459 } \
460 if (profile_flag || profile_arc_flag) \
461 { \
463 profile_flag = profile_arc_flag = 0; \
464 } \
465 } \
466 else \
467 { \
469 targetm.asm_out.aligned_op.di = NULL; \
470 targetm.asm_out.unaligned_op.di = NULL; \
471 } \
472 if (TARGET_FMOVD) \
474 \
475 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
476 if (! VALID_REGISTER_P (regno)) \
478 \
479 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
480 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
482 \
483 if (flag_omit_frame_pointer < 0) \
484 { \
485 /* The debugging information is sufficient, \
487 if (0) \
488 flag_omit_frame_pointer \
489 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
490 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
491 else \
492 flag_omit_frame_pointer = 0; \
493 } \
494 \
495 if (flag_pic && ! TARGET_PREFERGOT) \
496 flag_no_function_cse = 1; \
497 \
498 if (SMALL_REGISTER_CLASSES) \
499 { \
500 /* Never run scheduling before reload, since that can \
501 break global alloc, and generates slower code anyway due \
503 flag_schedule_insns = 0; \
504 } \
505 \
506 if (align_loops == 0) \
507 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
508 if (align_jumps == 0) \
509 align_jumps = 1 << CACHE_LOG; \
510 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
511 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
512 \
513 /* Allocation boundary (in *bytes*) for the code of a function. \
514 SH1: 32 bit alignment is faster, because instructions are always \
515 fetched as a pair from a longword boundary. \
517 if (align_functions == 0) \
518 align_functions \
519 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
520 /* The linker relaxation code breaks when a function contains \
521 alignments that are larger than that at the start of a \
523 if (TARGET_RELAX) \
524 { \
525 int min_align \
526 = align_loops > align_jumps ? align_loops : align_jumps; \
527 \
529 if (min_align < 4) \
530 min_align = 4; \
531 if (align_functions < min_align) \
532 align_functions = min_align; \
533 } \
534 } while (0)
535 \f
536 /* Target machine storage layout. */
538 /* Define this if most significant bit is lowest numbered
539 in instructions that operate on numbered bit-fields. */
541 #define BITS_BIG_ENDIAN 0
543 /* Define this if most significant byte of a word is the lowest numbered. */
544 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
546 /* Define this if most significant word of a multiword number is the lowest
547 numbered. */
548 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
550 /* Define this to set the endianness to use in libgcc2.c, which can
551 not depend on target_flags. */
552 #if defined(__LITTLE_ENDIAN__)
553 #define LIBGCC2_WORDS_BIG_ENDIAN 0
554 #else
555 #define LIBGCC2_WORDS_BIG_ENDIAN 1
556 #endif
558 #define MAX_BITS_PER_WORD 64
560 #define MAX_LONG_TYPE_SIZE MAX_BITS_PER_WORD
562 /* Width in bits of an `int'. We want just 32-bits, even if words are
563 longer. */
564 #define INT_TYPE_SIZE 32
566 /* Width in bits of a `long'. */
567 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
569 /* Width in bits of a `long long'. */
570 #define LONG_LONG_TYPE_SIZE 64
572 /* Width in bits of a `long double'. */
573 #define LONG_DOUBLE_TYPE_SIZE 64
575 /* Width of a word, in units (bytes). */
576 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
577 #define MIN_UNITS_PER_WORD 4
579 /* Width in bits of a pointer.
580 See also the macro `Pmode' defined below. */
581 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
583 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
584 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
586 /* Boundary (in *bits*) on which stack pointer should be aligned. */
587 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
589 /* The log (base 2) of the cache line size, in bytes. Processors prior to
590 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
591 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
592 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
594 /* ABI given & required minimum allocation boundary (in *bits*) for the
595 code of a function. */
596 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
598 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
599 the vbit must go into the delta field of
600 pointers-to-member-functions. */
601 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
602 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
604 /* Alignment of field after `int : 0' in a structure. */
605 #define EMPTY_FIELD_BOUNDARY 32
607 /* No data type wants to be aligned rounder than this. */
608 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
610 /* The best alignment to use in cases where we have a choice. */
611 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
613 /* Make strings word-aligned so strcpy from constants will be faster. */
614 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
615 ((TREE_CODE (EXP) == STRING_CST \
616 && (ALIGN) < FASTEST_ALIGNMENT) \
617 ? FASTEST_ALIGNMENT : (ALIGN))
619 /* Make arrays of chars word-aligned for the same reasons. */
620 #define DATA_ALIGNMENT(TYPE, ALIGN) \
621 (TREE_CODE (TYPE) == ARRAY_TYPE \
622 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
623 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
625 /* Number of bits which any structure or union's size must be a
626 multiple of. Each structure or union's size is rounded up to a
627 multiple of this. */
628 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
630 /* Set this nonzero if move instructions will actually fail to work
631 when given unaligned data. */
632 #define STRICT_ALIGNMENT 1
634 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
635 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
636 barrier_align (LABEL_AFTER_BARRIER)
638 #define LOOP_ALIGN(A_LABEL) \
639 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
640 ? 0 : sh_loop_align (A_LABEL))
642 #define LABEL_ALIGN(A_LABEL) \
643 ( \
644 (PREV_INSN (A_LABEL) \
645 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
646 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
647 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
649 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
650 : 0)
652 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
653 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
655 /* The base two logarithm of the known minimum alignment of an insn length. */
656 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
657 (GET_CODE (A_INSN) == INSN \
658 ? 1 << TARGET_SHMEDIA \
659 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
660 ? 1 << TARGET_SHMEDIA \
661 : CACHE_LOG)
662 \f
663 /* Standard register usage. */
665 /* Register allocation for the Hitachi calling convention:
667 r0 arg return
668 r1..r3 scratch
669 r4..r7 args in
670 r8..r13 call saved
671 r14 frame pointer/call saved
672 r15 stack pointer
673 ap arg pointer (doesn't really exist, always eliminated)
674 pr subroutine return address
675 t t bit
676 mach multiply/accumulate result, high part
677 macl multiply/accumulate result, low part.
678 fpul fp/int communication register
679 rap return address pointer register
680 fr0 fp arg return
681 fr1..fr3 scratch floating point registers
682 fr4..fr11 fp args in
683 fr12..fr15 call saved floating point registers */
685 #define MAX_REGISTER_NAME_LENGTH 5
688 #define SH_REGISTER_NAMES_INITIALIZER \
689 { \
710 }
712 #define DEBUG_REGISTER_NAMES SH_REGISTER_NAMES_INITIALIZER
714 #define REGNAMES_ARR_INDEX_1(index) \
715 (sh_register_names[index])
716 #define REGNAMES_ARR_INDEX_2(index) \
717 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
718 #define REGNAMES_ARR_INDEX_4(index) \
719 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
720 #define REGNAMES_ARR_INDEX_8(index) \
721 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
722 #define REGNAMES_ARR_INDEX_16(index) \
723 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
724 #define REGNAMES_ARR_INDEX_32(index) \
725 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
726 #define REGNAMES_ARR_INDEX_64(index) \
727 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
729 #define REGISTER_NAMES \
730 { \
731 REGNAMES_ARR_INDEX_64 (0), \
732 REGNAMES_ARR_INDEX_64 (64), \
733 REGNAMES_ARR_INDEX_8 (128), \
734 REGNAMES_ARR_INDEX_8 (136), \
735 REGNAMES_ARR_INDEX_8 (144), \
736 REGNAMES_ARR_INDEX_1 (152) \
737 }
739 #define ADDREGNAMES_SIZE 32
740 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
744 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
745 { \
750 }
752 #define ADDREGNAMES_REGNO(index) \
753 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
754 : (-1))
756 #define ADDREGNAMES_ARR_INDEX_1(index) \
757 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
758 #define ADDREGNAMES_ARR_INDEX_2(index) \
759 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
760 #define ADDREGNAMES_ARR_INDEX_4(index) \
761 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
762 #define ADDREGNAMES_ARR_INDEX_8(index) \
763 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
764 #define ADDREGNAMES_ARR_INDEX_16(index) \
765 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
766 #define ADDREGNAMES_ARR_INDEX_32(index) \
767 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
769 #define ADDITIONAL_REGISTER_NAMES \
770 { \
771 ADDREGNAMES_ARR_INDEX_32 (0) \
772 }
774 /* Number of actual hardware registers.
775 The hardware registers are assigned numbers for the compiler
776 from 0 to just below FIRST_PSEUDO_REGISTER.
777 All registers that the compiler knows about must be given numbers,
778 even those that are not normally considered general registers. */
780 /* There are many other relevant definitions in sh.md's md_constants. */
782 #define FIRST_GENERAL_REG R0_REG
783 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
784 #define FIRST_FP_REG DR0_REG
785 #define LAST_FP_REG (FIRST_FP_REG + \
786 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
787 #define FIRST_XD_REG XD0_REG
788 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
789 #define FIRST_TARGET_REG TR0_REG
790 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
792 #define GENERAL_REGISTER_P(REGNO) \
793 IN_RANGE ((REGNO), FIRST_GENERAL_REG, LAST_GENERAL_REG)
795 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
796 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
798 #define FP_REGISTER_P(REGNO) \
799 ((REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG)
801 #define XD_REGISTER_P(REGNO) \
802 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG)
804 #define FP_OR_XD_REGISTER_P(REGNO) \
805 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
807 #define FP_ANY_REGISTER_P(REGNO) \
808 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
810 #define SPECIAL_REGISTER_P(REGNO) \
811 ((REGNO) == GBR_REG || (REGNO) == T_REG \
812 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
814 #define TARGET_REGISTER_P(REGNO) \
815 ((REGNO) >= FIRST_TARGET_REG && (REGNO) <= LAST_TARGET_REG)
817 #define SHMEDIA_REGISTER_P(REGNO) \
818 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
819 || TARGET_REGISTER_P (REGNO))
821 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
822 that should be fixed. */
823 #define VALID_REGISTER_P(REGNO) \
824 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
825 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
826 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
827 || (TARGET_SH2E && (REGNO) == FPUL_REG))
829 /* The mode that should be generally used to store a register by
830 itself in the stack, or to load it back. */
831 #define REGISTER_NATURAL_MODE(REGNO) \
832 (FP_REGISTER_P (REGNO) ? SFmode \
833 : XD_REGISTER_P (REGNO) ? DFmode \
834 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
835 ? DImode \
836 : SImode)
838 #define FIRST_PSEUDO_REGISTER 153
840 /* 1 for registers that have pervasive standard uses
841 and are not available for the register allocator.
843 Mach register is fixed 'cause it's only 10 bits wide for SH1.
844 It is 32 bits wide for SH2. */
846 #define FIXED_REGISTERS \
847 { \
849 0, 0, 0, 0, 0, 0, 0, 0, \
850 0, 0, 0, 0, 0, 0, 0, 1, \
852 1, 0, 0, 0, 0, 0, 0, 0, \
855 1, 1, 1, 1, 0, 0, 0, 0, \
856 0, 0, 0, 0, 0, 0, 0, 0, \
857 0, 0, 0, 0, 0, 0, 0, 0, \
858 0, 0, 0, 0, 0, 0, 0, 0, \
859 0, 0, 0, 0, 0, 0, 0, 1, \
861 0, 0, 0, 0, 0, 0, 0, 0, \
862 0, 0, 0, 0, 0, 0, 0, 0, \
863 0, 0, 0, 0, 0, 0, 0, 0, \
864 0, 0, 0, 0, 0, 0, 0, 0, \
865 0, 0, 0, 0, 0, 0, 0, 0, \
866 0, 0, 0, 0, 0, 0, 0, 0, \
867 0, 0, 0, 0, 0, 0, 0, 0, \
868 0, 0, 0, 0, 0, 0, 0, 0, \
870 0, 0, 0, 0, 0, 0, 0, 0, \
872 0, 0, 0, 0, 0, 0, 0, 0, \
874 1, 1, 1, 1, 1, 1, 0, 1, \
876 1, \
877 }
879 /* 1 for registers not available across function calls.
880 These must include the FIXED_REGISTERS and also any
881 registers that can be used without being saved.
882 The latter must include the registers where values are returned
883 and the register where structure-value addresses are passed.
884 Aside from that, you can include as many other registers as you like. */
886 #define CALL_USED_REGISTERS \
887 { \
889 1, 1, 1, 1, 1, 1, 1, 1, \
890 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
891 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
893 0, 0, 0, 0, 0, 0, 0, 1, \
894 1, 1, 0, 1, 1, 1, 1, 1, \
895 1, 1, 1, 1, 0, 0, 0, 0, \
896 0, 0, 0, 0, 1, 1, 1, 1, \
897 1, 1, 1, 1, 0, 0, 0, 0, \
898 0, 0, 0, 0, 0, 0, 0, 0, \
899 0, 0, 0, 0, 1, 1, 1, 1, \
901 1, 1, 1, 1, 1, 1, 1, 1, \
902 1, 1, 1, 1, 0, 0, 0, 0, \
903 1, 1, 1, 1, 1, 1, 1, 1, \
904 1, 1, 1, 1, 1, 1, 1, 1, \
905 1, 1, 1, 1, 0, 0, 0, 0, \
906 0, 0, 0, 0, 0, 0, 0, 0, \
907 0, 0, 0, 0, 0, 0, 0, 0, \
908 0, 0, 0, 0, 0, 0, 0, 0, \
910 1, 1, 1, 1, 1, 0, 0, 0, \
912 1, 1, 1, 1, 1, 1, 0, 0, \
914 1, 1, 0, 1, 1, 1, 1, 1, \
916 1, \
917 }
919 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
920 across SHcompact function calls. We can't tell whether a called
921 function is SHmedia or SHcompact, so we assume it may be when
922 compiling SHmedia code with the 32-bit ABI, since that's the only
923 ABI that can be linked with SHcompact code. */
924 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
925 (TARGET_SHMEDIA32 \
926 && GET_MODE_SIZE (MODE) > 4 \
927 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
928 && (REGNO) <= FIRST_GENERAL_REG + 14) \
929 || (REGNO) == PR_MEDIA_REG))
931 /* Return number of consecutive hard regs needed starting at reg REGNO
932 to hold something of mode MODE.
933 This is ordinarily the length in words of a value of mode MODE
934 but can be less for certain modes in special long registers.
936 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
938 #define HARD_REGNO_NREGS(REGNO, MODE) \
939 (XD_REGISTER_P (REGNO) \
940 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
941 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
942 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
943 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
945 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
946 We can allow any mode in any general register. The special registers
947 only allow SImode. Don't allow any mode in the PR. */
949 /* We cannot hold DCmode values in the XD registers because alter_reg
950 handles subregs of them incorrectly. We could work around this by
951 spacing the XD registers like the DR registers, but this would require
952 additional memory in every compilation to hold larger register vectors.
953 We could hold SFmode / SCmode values in XD registers, but that
954 would require a tertiary reload when reloading from / to memory,
955 and a secondary reload to reload from / to general regs; that
956 seems to be a loosing proposition. */
957 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
958 it won't be ferried through GP registers first. */
959 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
960 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
961 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
962 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
963 ? 1 \
964 : (MODE) == V2SFmode \
965 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
966 || GENERAL_REGISTER_P (REGNO)) \
967 : (MODE) == V4SFmode \
968 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
969 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
970 : (MODE) == V16SFmode \
971 ? (TARGET_SHMEDIA \
972 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
973 : (REGNO) == FIRST_XD_REG) \
974 : FP_REGISTER_P (REGNO) \
975 ? ((MODE) == SFmode || (MODE) == SImode \
976 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
977 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode \
978 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
979 || (MODE) == V2SFmode || (MODE) == TImode))) \
980 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
981 : XD_REGISTER_P (REGNO) \
982 ? (MODE) == DFmode \
983 : TARGET_REGISTER_P (REGNO) \
984 ? ((MODE) == DImode || (MODE) == SImode) \
985 : (REGNO) == PR_REG ? 0 \
986 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
987 : 1)
989 /* Value is 1 if MODE is a supported vector mode. */
990 #define VECTOR_MODE_SUPPORTED_P(MODE) \
991 ((TARGET_FPU_ANY \
992 && ((MODE) == V2SFmode || (MODE) == V4SFmode || (MODE) == V16SFmode)) \
993 || (TARGET_SHMEDIA \
994 && ((MODE) == V8QImode || (MODE) == V2HImode || (MODE) == V4HImode \
995 || (MODE) == V2SImode)))
997 /* Value is 1 if it is a good idea to tie two pseudo registers
998 when one has mode MODE1 and one has mode MODE2.
999 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1000 for any hard reg, then this must be 0 for correct output.
1001 That's the case for xd registers: we don't hold SFmode values in
1002 them, so we can't tie an SFmode pseudos with one in another
1003 floating-point mode. */
1005 #define MODES_TIEABLE_P(MODE1, MODE2) \
1006 ((MODE1) == (MODE2) \
1007 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1008 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1009 && (GET_MODE_SIZE (MODE2) <= 4)) \
1010 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1012 /* A C expression that is nonzero if hard register NEW_REG can be
1013 considered for use as a rename register for OLD_REG register */
1015 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1016 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1018 /* Specify the registers used for certain standard purposes.
1019 The values of these macros are register numbers. */
1021 /* Define this if the program counter is overloaded on a register. */
1022 /* #define PC_REGNUM 15*/
1024 /* Register to use for pushing function arguments. */
1025 #define STACK_POINTER_REGNUM SP_REG
1027 /* Base register for access to local variables of the function. */
1028 #define FRAME_POINTER_REGNUM FP_REG
1030 /* Fake register that holds the address on the stack of the
1031 current function's return address. */
1032 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1034 /* Register to hold the addressing base for position independent
1035 code access to data items. */
1036 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1040 /* Value should be nonzero if functions must have frame pointers.
1041 Zero means the frame pointer need not be set up (and parms may be accessed
1042 via the stack pointer) in functions that seem suitable. */
1044 #define FRAME_POINTER_REQUIRED 0
1046 /* Definitions for register eliminations.
1048 We have three registers that can be eliminated on the SH. First, the
1049 frame pointer register can often be eliminated in favor of the stack
1050 pointer register. Secondly, the argument pointer register can always be
1051 eliminated; it is replaced with either the stack or frame pointer.
1052 Third, there is the return address pointer, which can also be replaced
1053 with either the stack or the frame pointer. */
1055 /* This is an array of structures. Each structure initializes one pair
1056 of eliminable registers. The "from" register number is given first,
1057 followed by "to". Eliminations of the same "from" register are listed
1058 in order of preference. */
1060 /* If you add any registers here that are not actually hard registers,
1061 and that have any alternative of elimination that doesn't always
1062 apply, you need to amend calc_live_regs to exclude it, because
1063 reload spills all eliminable registers where it sees an
1064 can_eliminate == 0 entry, thus making them 'live' .
1065 If you add any hard registers that can be eliminated in different
1066 ways, you have to patch reload to spill them only when all alternatives
1067 of elimination fail. */
1069 #define ELIMINABLE_REGS \
1070 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1071 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1072 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1073 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1074 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1076 /* Given FROM and TO register numbers, say whether this elimination
1077 is allowed. */
1078 #define CAN_ELIMINATE(FROM, TO) \
1079 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1081 /* Define the offset between two registers, one to be eliminated, and the other
1082 its replacement, at the start of a routine. */
1084 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1085 OFFSET = initial_elimination_offset ((FROM), (TO))
1087 /* Base register for access to arguments of the function. */
1088 #define ARG_POINTER_REGNUM AP_REG
1090 /* Register in which the static-chain is passed to a function. */
1091 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1093 /* The register in which a struct value address is passed. */
1095 #define STRUCT_VALUE_REGNUM 2
1097 /* If the structure value address is not passed in a register, define
1098 `STRUCT_VALUE' as an expression returning an RTX for the place
1099 where the address is passed. If it returns 0, the address is
1100 passed as an "invisible" first argument. */
1102 /* The Hitachi calling convention doesn't quite fit into this scheme since
1103 the address is passed like an invisible argument, but one that is always
1104 passed in memory. */
1105 #define STRUCT_VALUE \
1106 (TARGET_HITACHI ? 0 : gen_rtx_REG (Pmode, STRUCT_VALUE_REGNUM))
1108 #define RETURN_IN_MEMORY(TYPE) \
1109 (TARGET_SH5 \
1110 ? ((TYPE_MODE (TYPE) == BLKmode \
1111 ? (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) \
1112 : GET_MODE_SIZE (TYPE_MODE (TYPE))) > 8) \
1113 : (TYPE_MODE (TYPE) == BLKmode \
1114 || TARGET_HITACHI && TREE_CODE (TYPE) == RECORD_TYPE))
1116 /* Don't default to pcc-struct-return, because we have already specified
1117 exactly how to return structures in the RETURN_IN_MEMORY macro. */
1119 #define DEFAULT_PCC_STRUCT_RETURN 0
1121 #define SHMEDIA_REGS_STACK_ADJUST() \
1122 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1125 : 0)
1127 \f
1128 /* Define the classes of registers for register constraints in the
1129 machine description. Also define ranges of constants.
1131 One of the classes must always be named ALL_REGS and include all hard regs.
1132 If there is more than one class, another class must be named NO_REGS
1133 and contain no registers.
1135 The name GENERAL_REGS must be the name of a class (or an alias for
1136 another name such as ALL_REGS). This is the class of registers
1137 that is allowed by "g" or "r" in a register constraint.
1138 Also, registers outside this class are allocated only when
1139 instructions express preferences for them.
1141 The classes must be numbered in nondecreasing order; that is,
1142 a larger-numbered class must never be contained completely
1143 in a smaller-numbered class.
1145 For any two classes, it is very desirable that there be another
1146 class that represents their union. */
1148 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1149 be used as the destination of some of the arithmetic ops. There are
1150 also some special purpose registers; the T bit register, the
1151 Procedure Return Register and the Multiply Accumulate Registers. */
1152 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1153 reg_class_subunion. We don't want to have an actual union class
1154 of these, because it would only be used when both classes are calculated
1155 to give the same cost, but there is only one FPUL register.
1156 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1157 applying to the actual instruction alternative considered. E.g., the
1158 y/r alternative of movsi_ie is considered to have no more cost that
1159 the r/r alternative, which is patently untrue. */
1161 enum reg_class
1162 {
1163 NO_REGS,
1164 R0_REGS,
1165 PR_REGS,
1166 T_REGS,
1167 MAC_REGS,
1168 FPUL_REGS,
1169 SIBCALL_REGS,
1170 GENERAL_REGS,
1171 FP0_REGS,
1172 FP_REGS,
1173 DF_HI_REGS,
1174 DF_REGS,
1175 FPSCR_REGS,
1176 GENERAL_FP_REGS,
1177 TARGET_REGS,
1178 ALL_REGS,
1179 LIM_REG_CLASSES
1180 };
1182 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1184 /* Give names of register classes as strings for dump file. */
1185 #define REG_CLASS_NAMES \
1186 { \
1203 }
1205 /* Define which registers fit in which classes.
1206 This is an initializer for a vector of HARD_REG_SET
1207 of length N_REG_CLASSES. */
1209 #define REG_CLASS_CONTENTS \
1210 { \
1212 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1214 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1216 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1218 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1220 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1222 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1224 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1226 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1228 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1230 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1232 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1234 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1236 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1238 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1240 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1242 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1243 }
1245 /* The same information, inverted:
1246 Return the class number of the smallest class containing
1247 reg number REGNO. This could be a conditional expression
1248 or could index an array. */
1251 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1253 /* When defined, the compiler allows registers explicitly used in the
1254 rtl to be used as spill registers but prevents the compiler from
1255 extending the lifetime of these registers. */
1257 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1259 /* The order in which register should be allocated. */
1260 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1261 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1262 spilled or used otherwise, we better have the FP_REGS allocated first. */
1263 #define REG_ALLOC_ORDER \
1264 { 65, 66, 67, 68, 69, 70, 71, 64, \
1265 72, 73, 74, 75, 76, 77, 78, 79, \
1266 136,137,138,139,140,141,142,143, \
1267 80, 81, 82, 83, 84, 85, 86, 87, \
1268 88, 89, 90, 91, 92, 93, 94, 95, \
1269 96, 97, 98, 99,100,101,102,103, \
1270 104,105,106,107,108,109,110,111, \
1271 112,113,114,115,116,117,118,119, \
1272 120,121,122,123,124,125,126,127, \
1273 151, 1, 2, 3, 7, 6, 5, 4, \
1274 0, 8, 9, 10, 11, 12, 13, 14, \
1275 16, 17, 18, 19, 20, 21, 22, 23, \
1276 24, 25, 26, 27, 28, 29, 30, 31, \
1277 32, 33, 34, 35, 36, 37, 38, 39, \
1278 40, 41, 42, 43, 44, 45, 46, 47, \
1279 48, 49, 50, 51, 52, 53, 54, 55, \
1280 56, 57, 58, 59, 60, 61, 62, 63, \
1281 150, 15,145,146,147,144,148,149, \
1282 128,129,130,131,132,133,134,135, \
1283 152 }
1285 /* The class value for index registers, and the one for base regs. */
1286 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1287 #define BASE_REG_CLASS GENERAL_REGS
1289 /* Get reg_class from a letter such as appears in the machine
1290 description. */
1293 #define REG_CLASS_FROM_LETTER(C) \
1295 \f
1296 /* The letters I, J, K, L and M in a register constraint string
1297 can be used to stand for particular ranges of immediate operands.
1298 This macro defines what the ranges are.
1299 C is the letter, and VALUE is a constant value.
1300 Return 1 if VALUE is in the range specified by C.
1301 I: arithmetic operand -127..128, as used in add, sub, etc
1302 J: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1303 K: shift operand 1,2,8 or 16
1304 L: logical operand 0..255, as used in and, or, etc.
1305 M: constant 1
1306 N: constant 0
1307 O: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1308 P: arithmetic operand -512..511, as used in SHmedia andi, ori
1309 */
1311 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1312 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1313 #define CONST_OK_FOR_J(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1314 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1315 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1316 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1317 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1318 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1319 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1320 #define CONST_OK_FOR_O(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1321 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1322 #define CONST_OK_FOR_P(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1323 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1324 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1333 : 0)
1335 /* Similar, but for floating constants, and defining letters G and H.
1336 Here VALUE is the CONST_DOUBLE rtx itself. */
1338 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1343 /* Given an rtx X being reloaded into a reg required to be
1344 in class CLASS, return the class of reg to actually use.
1345 In general this is just CLASS; but on some machines
1346 in some cases it is preferable to use a more restrictive class. */
1348 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1349 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1350 && (GET_CODE (X) == CONST_DOUBLE \
1351 || GET_CODE (X) == SYMBOL_REF) \
1352 ? GENERAL_REGS \
1353 : (CLASS)) \
1355 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1356 ((((REGCLASS_HAS_FP_REG (CLASS) \
1357 && (GET_CODE (X) == REG \
1358 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1359 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1360 && TARGET_FMOVD)))) \
1361 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1362 && GET_CODE (X) == REG \
1363 && FP_REGISTER_P (REGNO (X)))) \
1364 && ! TARGET_SHMEDIA \
1365 && ((MODE) == SFmode || (MODE) == SImode)) \
1366 ? FPUL_REGS \
1367 : (((CLASS) == FPUL_REGS \
1368 || (REGCLASS_HAS_FP_REG (CLASS) \
1369 && ! TARGET_SHMEDIA && MODE == SImode)) \
1370 && (GET_CODE (X) == MEM \
1371 || (GET_CODE (X) == REG \
1372 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1373 || REGNO (X) == T_REG \
1374 || system_reg_operand (X, VOIDmode))))) \
1375 ? GENERAL_REGS \
1376 : ((CLASS) == TARGET_REGS \
1377 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1378 ? ((target_operand ((X), (MODE)) \
1379 && ! target_reg_operand ((X), (MODE))) \
1380 ? NO_REGS : GENERAL_REGS) \
1381 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1382 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1383 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1384 ? GENERAL_REGS \
1385 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1386 && TARGET_REGISTER_P (REGNO (X))) \
1387 ? GENERAL_REGS : NO_REGS)
1389 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1390 ((REGCLASS_HAS_FP_REG (CLASS) \
1391 && ! TARGET_SHMEDIA \
1392 && immediate_operand ((X), (MODE)) \
1393 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1394 && (MODE) == SFmode && fldi_ok ())) \
1395 ? R0_REGS \
1396 : (CLASS == FPUL_REGS \
1397 && ((GET_CODE (X) == REG \
1398 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1399 || REGNO (X) == T_REG)) \
1400 || GET_CODE (X) == PLUS)) \
1401 ? GENERAL_REGS \
1402 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1403 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
1404 ? GENERAL_REGS \
1405 : R0_REGS) \
1406 : (CLASS == FPSCR_REGS \
1407 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1408 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1409 ? GENERAL_REGS \
1410 : (REGCLASS_HAS_FP_REG (CLASS) \
1411 && TARGET_SHMEDIA \
1412 && immediate_operand ((X), (MODE)) \
1413 && (X) != CONST0_RTX (GET_MODE (X)) \
1414 && GET_MODE (X) != V4SFmode) \
1415 ? GENERAL_REGS \
1416 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1418 /* Return the maximum number of consecutive registers
1419 needed to represent mode MODE in a register of class CLASS.
1421 If TARGET_SHMEDIA, we need two FP registers per word.
1422 Otherwise we will need at most one register per word. */
1423 #define CLASS_MAX_NREGS(CLASS, MODE) \
1424 (TARGET_SHMEDIA \
1425 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1426 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1427 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1429 /* If defined, gives a class of registers that cannot be used as the
1430 operand of a SUBREG that changes the mode of the object illegally. */
1431 /* ??? We need to renumber the internal numbers for the frnn registers
1432 when in little endian in order to allow mode size changes. */
1434 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1435 sh_cannot_change_mode_class (FROM, TO, CLASS)
1436 \f
1437 /* Stack layout; function entry, exit and calling. */
1439 /* Define the number of registers that can hold parameters.
1440 These macros are used only in other macro definitions below. */
1442 #define NPARM_REGS(MODE) \
1443 (TARGET_FPU_ANY && (MODE) == SFmode \
1444 ? (TARGET_SH5 ? 12 : 8) \
1445 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1446 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1447 ? (TARGET_SH5 ? 12 : 8) \
1448 : (TARGET_SH5 ? 8 : 4))
1450 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1451 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1453 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1454 #define FIRST_FP_RET_REG FIRST_FP_REG
1456 /* Define this if pushing a word on the stack
1457 makes the stack pointer a smaller address. */
1458 #define STACK_GROWS_DOWNWARD
1460 /* Define this macro if the addresses of local variable slots are at
1461 negative offsets from the frame pointer.
1463 The SH only has positive indexes, so grow the frame up. */
1464 /* #define FRAME_GROWS_DOWNWARD */
1466 /* Offset from the frame pointer to the first local variable slot to
1467 be allocated. */
1468 #define STARTING_FRAME_OFFSET 0
1470 /* If we generate an insn to push BYTES bytes,
1471 this says how many the stack pointer really advances by. */
1472 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1473 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1474 do correct alignment. */
1475 #if 0
1476 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1477 #endif
1479 /* Offset of first parameter from the argument pointer register value. */
1480 #define FIRST_PARM_OFFSET(FNDECL) 0
1482 /* Value is the number of byte of arguments automatically
1483 popped when returning from a subroutine call.
1484 FUNDECL is the declaration node of the function (as a tree),
1485 FUNTYPE is the data type of the function (as a tree),
1486 or for a library call it is an identifier node for the subroutine name.
1487 SIZE is the number of bytes of arguments passed on the stack.
1489 On the SH, the caller does not pop any of its arguments that were passed
1490 on the stack. */
1491 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1493 /* Value is the number of bytes of arguments automatically popped when
1494 calling a subroutine.
1495 CUM is the accumulated argument list.
1497 On SHcompact, the call trampoline pops arguments off the stack. */
1498 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1500 /* Nonzero if we do not know how to pass TYPE solely in registers.
1501 Values that come in registers with inconvenient padding are stored
1502 to memory at the function start. */
1504 #define MUST_PASS_IN_STACK(MODE,TYPE) \
1505 ((TYPE) != 0 \
1506 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
1507 || TREE_ADDRESSABLE (TYPE)))
1508 /* Some subroutine macros specific to this machine. */
1510 #define BASE_RETURN_VALUE_REG(MODE) \
1511 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1512 ? FIRST_FP_RET_REG \
1513 : TARGET_FPU_ANY && (MODE) == SCmode \
1514 ? FIRST_FP_RET_REG \
1515 : (TARGET_FPU_DOUBLE \
1516 && ((MODE) == DFmode || (MODE) == SFmode \
1517 || (MODE) == DCmode || (MODE) == SCmode )) \
1518 ? FIRST_FP_RET_REG \
1519 : FIRST_RET_REG)
1521 #define BASE_ARG_REG(MODE) \
1522 ((TARGET_SH2E && ((MODE) == SFmode)) \
1523 ? FIRST_FP_PARM_REG \
1524 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1525 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1526 ? FIRST_FP_PARM_REG \
1527 : FIRST_PARM_REG)
1529 /* Define how to find the value returned by a function.
1530 VALTYPE is the data type of the value (as a tree).
1531 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1532 otherwise, FUNC is 0.
1533 For the SH, this is like LIBCALL_VALUE, except that we must change the
1534 mode like PROMOTE_MODE does.
1535 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1536 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1538 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1539 gen_rtx (REG, \
1540 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1541 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1542 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1543 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1544 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1545 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1546 || TREE_CODE (VALTYPE) == REAL_TYPE \
1547 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1548 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1549 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1551 /* Define how to find the value returned by a library function
1552 assuming the value has mode MODE. */
1553 #define LIBCALL_VALUE(MODE) \
1554 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1556 /* 1 if N is a possible register number for a function value. */
1557 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1558 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1559 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1561 /* 1 if N is a possible register number for function argument passing. */
1562 #define FUNCTION_ARG_REGNO_P(REGNO) \
1563 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG \
1564 + NPARM_REGS (SImode))) \
1565 || (TARGET_FPU_ANY \
1566 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG \
1567 + NPARM_REGS (SFmode))))
1568 \f
1569 /* Define a data type for recording info about an argument list
1570 during the scan of that argument list. This data type should
1571 hold all necessary information about the function itself
1572 and about the args processed so far, enough to enable macros
1573 such as FUNCTION_ARG to determine where the next arg should go.
1575 On SH, this is a single integer, which is a number of words
1576 of arguments scanned so far (including the invisible argument,
1577 if any, which holds the structure-value-address).
1578 Thus NARGREGS or more means all following args should go on the stack. */
1584 /* Nonzero if a prototype is available for the function. */
1586 /* The number of an odd floating-point register, that should be used
1587 for the next argument of type float. */
1589 /* Whether we're processing an outgoing function call. */
1591 /* The number of general-purpose registers that should have been
1592 used to pass partial arguments, that are passed totally on the
1593 stack. On SHcompact, a call trampoline will pop them off the
1594 stack before calling the actual function, and, if the called
1595 function is implemented in SHcompact mode, the incoming arguments
1596 decoder will push such arguments back onto the stack. For
1597 incoming arguments, STACK_REGS also takes into account other
1598 arguments passed by reference, that the decoder will also push
1599 onto the stack. */
1601 /* The number of general-purpose registers that should have been
1602 used to pass arguments, if the arguments didn't have to be passed
1603 by reference. */
1605 /* Set by SHCOMPACT_BYREF if the current argument is to be passed by
1606 reference. */
1609 /* call_cookie is a bitmask used by call expanders, as well as
1610 function prologue and epilogues, to allow SHcompact to comply
1611 with the SH5 32-bit ABI, that requires 64-bit registers to be
1612 used even though only the lower 32-bit half is visible in
1613 SHcompact mode. The strategy is to call SHmedia trampolines.
1615 The alternatives for each of the argument-passing registers are
1616 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1617 contents from the address in it; (d) add 8 to it, storing the
1618 result in the next register, then (c); (e) copy it from some
1619 floating-point register,
1621 Regarding copies from floating-point registers, r2 may only be
1622 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1623 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1624 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1625 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1626 dr10.
1628 The bit mask is structured as follows:
1630 - 1 bit to tell whether to set up a return trampoline.
1632 - 3 bits to count the number consecutive registers to pop off the
1633 stack.
1635 - 4 bits for each of r9, r8, r7 and r6.
1637 - 3 bits for each of r5, r4, r3 and r2.
1639 - 3 bits set to 0 (the most significant ones)
1641 3 2 1 0
1642 1098 7654 3210 9876 5432 1098 7654 3210
1643 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1644 2223 3344 4555 6666 7777 8888 9999 SSS-
1646 - If F is set, the register must be copied from an FP register,
1647 whose number is encoded in the remaining bits.
1649 - Else, if L is set, the register must be loaded from the address
1650 contained in it. If the P bit is *not* set, the address of the
1651 following dword should be computed first, and stored in the
1652 following register.
1654 - Else, if P is set, the register alone should be popped off the
1655 stack.
1657 - After all this processing, the number of registers represented
1658 in SSS will be popped off the stack. This is an optimization
1659 for pushing/popping consecutive registers, typically used for
1660 varargs and large arguments partially passed in registers.
1662 - If T is set, a return trampoline will be set up for 64-bit
1663 return values to be split into 2 32-bit registers. */
1664 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1665 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1666 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1667 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1668 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1669 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1670 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1671 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1672 #define CALL_COOKIE_INT_REG(REG, VAL) \
1673 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1674 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1675 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1677 };
1679 #define CUMULATIVE_ARGS struct sh_args
1681 #define GET_SH_ARG_CLASS(MODE) \
1682 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1683 ? SH_ARG_FLOAT \
1684 /* There's no mention of complex float types in the SH5 ABI, so we
1686 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1687 ? SH_ARG_INT \
1688 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1689 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1690 ? SH_ARG_FLOAT : SH_ARG_INT)
1692 #define ROUND_ADVANCE(SIZE) \
1693 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1695 /* Round a register number up to a proper boundary for an arg of mode
1696 MODE.
1698 The SH doesn't care about double alignment, so we only
1699 round doubles to even regs when asked to explicitly. */
1701 #define ROUND_REG(CUM, MODE) \
1702 (((TARGET_ALIGN_DOUBLE \
1703 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
1704 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1705 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1706 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1707 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1708 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1710 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1711 for a call to a function whose data type is FNTYPE.
1712 For a library call, FNTYPE is 0.
1714 On SH, the offset always starts at 0: the first parm reg is always
1715 the same reg for a given argument class.
1717 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1719 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1720 do { \
1721 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
1722 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
1723 (CUM).force_mem \
1724 = (TARGET_HITACHI && FNTYPE \
1725 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1726 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
1727 (CUM).arg_count[(int) SH_ARG_INT] \
1728 = (TARGET_SH5 && (FNTYPE) \
1729 && aggregate_value_p (TREE_TYPE (FNTYPE))); \
1730 (CUM).free_single_fp_reg = 0; \
1731 (CUM).outgoing = 1; \
1732 (CUM).stack_regs = 0; \
1733 (CUM).byref_regs = 0; \
1734 (CUM).byref = 0; \
1735 (CUM).call_cookie \
1736 = (CALL_COOKIE_RET_TRAMP \
1737 (TARGET_SHCOMPACT && (FNTYPE) \
1738 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
1739 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
1740 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
1741 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
1742 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
1743 (FNTYPE))) \
1744 == FIRST_RET_REG))); \
1745 } while (0)
1747 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1748 do { \
1749 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0); \
1750 (CUM).call_cookie \
1751 = (CALL_COOKIE_RET_TRAMP \
1752 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
1753 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
1754 } while (0)
1756 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1757 do { \
1758 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0); \
1759 (CUM).outgoing = 0; \
1760 } while (0)
1762 /* Update the data in CUM to advance over an argument
1763 of mode MODE and data type TYPE.
1764 (TYPE is null for libcalls where that information may not be
1765 available.) */
1767 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1768 if ((CUM).force_mem) \
1769 (CUM).force_mem = 0; \
1770 else if (TARGET_SH5) \
1771 { \
1772 tree TYPE_ = ((CUM).byref && (TYPE) \
1773 ? TREE_TYPE (TYPE) \
1774 : (TYPE)); \
1775 enum machine_mode MODE_ = ((CUM).byref && (TYPE) \
1776 ? TYPE_MODE (TYPE_) \
1777 : (MODE)); \
1778 int dwords = (((CUM).byref \
1779 ? (CUM).byref \
1780 : (MODE_) == BLKmode \
1781 ? int_size_in_bytes (TYPE_) \
1782 : GET_MODE_SIZE (MODE_)) + 7) / 8; \
1783 int numregs = MIN (dwords, NPARM_REGS (SImode) \
1784 - (CUM).arg_count[(int) SH_ARG_INT]); \
1785 \
1786 if (numregs) \
1787 { \
1788 (CUM).arg_count[(int) SH_ARG_INT] += numregs; \
1789 if (TARGET_SHCOMPACT \
1790 && SHCOMPACT_FORCE_ON_STACK (MODE_, TYPE_)) \
1791 { \
1792 (CUM).call_cookie \
1793 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1794 - numregs), 1); \
1796 (CUM).stack_regs += numregs; \
1797 } \
1798 else if ((CUM).byref) \
1799 { \
1800 if (! (CUM).outgoing) \
1801 (CUM).stack_regs += numregs; \
1802 (CUM).byref_regs += numregs; \
1803 (CUM).byref = 0; \
1804 do \
1805 (CUM).call_cookie \
1806 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1807 - numregs), 2); \
1808 while (--numregs); \
1809 (CUM).call_cookie \
1810 |= CALL_COOKIE_INT_REG (((CUM).arg_count[(int) SH_ARG_INT] \
1811 - 1), 1); \
1812 } \
1813 else if (dwords > numregs) \
1814 { \
1815 int pushregs = numregs; \
1816 \
1817 if (TARGET_SHCOMPACT) \
1818 (CUM).stack_regs += numregs; \
1819 while (pushregs < NPARM_REGS (SImode) - 1 \
1820 && (CALL_COOKIE_INT_REG_GET \
1821 ((CUM).call_cookie, \
1822 NPARM_REGS (SImode) - pushregs) \
1823 == 1)) \
1824 { \
1825 (CUM).call_cookie \
1826 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode) \
1827 - pushregs, 1); \
1828 pushregs++; \
1829 } \
1830 if (numregs == NPARM_REGS (SImode)) \
1831 (CUM).call_cookie \
1832 |= CALL_COOKIE_INT_REG (0, 1) \
1833 | CALL_COOKIE_STACKSEQ (numregs - 1); \
1834 else \
1835 (CUM).call_cookie \
1836 |= CALL_COOKIE_STACKSEQ (numregs); \
1837 } \
1838 } \
1839 if (GET_SH_ARG_CLASS (MODE_) == SH_ARG_FLOAT \
1840 && ((NAMED) || ! (CUM).prototype_p)) \
1841 { \
1842 if ((MODE_) == SFmode && (CUM).free_single_fp_reg) \
1843 (CUM).free_single_fp_reg = 0; \
1844 else if ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1845 < NPARM_REGS (SFmode)) \
1846 { \
1847 int numfpregs \
1848 = MIN ((GET_MODE_SIZE (MODE_) + 7) / 8 * 2, \
1849 NPARM_REGS (SFmode) \
1850 - (CUM).arg_count[(int) SH_ARG_FLOAT]); \
1851 \
1852 (CUM).arg_count[(int) SH_ARG_FLOAT] += numfpregs; \
1853 \
1854 if (TARGET_SHCOMPACT && ! (CUM).prototype_p) \
1855 { \
1856 if ((CUM).outgoing && numregs > 0) \
1857 do \
1858 { \
1859 (CUM).call_cookie \
1860 |= (CALL_COOKIE_INT_REG \
1861 ((CUM).arg_count[(int) SH_ARG_INT] \
1862 - numregs + ((numfpregs - 2) / 2), \
1863 4 + ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1864 - numfpregs) / 2)); \
1865 } \
1866 while (numfpregs -= 2); \
1867 } \
1868 else if ((MODE_) == SFmode && (NAMED) \
1869 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1870 < NPARM_REGS (SFmode))) \
1871 (CUM).free_single_fp_reg \
1872 = FIRST_FP_PARM_REG - numfpregs \
1873 + (CUM).arg_count[(int) SH_ARG_FLOAT] + 1; \
1874 } \
1875 } \
1876 } \
1877 else if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1878 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1879 = (ROUND_REG ((CUM), (MODE)) \
1880 + ((MODE) == BLKmode \
1881 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1882 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1884 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1885 This macro is only used in this file. */
1887 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1888 (((TYPE) == 0 \
1889 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1890 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE)))) \
1891 && ! (CUM).force_mem \
1892 && (TARGET_SH2E \
1893 ? ((MODE) == BLKmode \
1894 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1895 + int_size_in_bytes (TYPE)) \
1896 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1897 : ((ROUND_REG((CUM), (MODE)) \
1898 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1899 <= NPARM_REGS (MODE))) \
1900 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1902 /* Define where to put the arguments to a function.
1903 Value is zero to push the argument on the stack,
1904 or a hard register in which to store the argument.
1906 MODE is the argument's machine mode.
1907 TYPE is the data type of the argument (as a tree).
1908 This is null for libcalls where that information may
1909 not be available.
1910 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1911 the preceding args and about the function being called.
1912 NAMED is nonzero if this argument is a named parameter
1913 (otherwise it is an extra parameter matching an ellipsis).
1915 On SH the first args are normally in registers
1916 and the rest are pushed. Any arg that starts within the first
1917 NPARM_REGS words is at least partially passed in a register unless
1918 its data type forbids. */
1920 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1921 ((! TARGET_SH5 \
1922 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1923 && ((NAMED) || !TARGET_HITACHI)) \
1924 ? gen_rtx_REG ((MODE), \
1925 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1926 ^ ((MODE) == SFmode && TARGET_SH4 \
1927 && TARGET_LITTLE_ENDIAN != 0))) \
1928 : TARGET_SH5 \
1929 ? ((MODE) == VOIDmode && TARGET_SHCOMPACT \
1930 ? GEN_INT ((CUM).call_cookie) \
1931 /* The following test assumes unnamed arguments are promoted to \
1933 : (MODE) == SFmode && (CUM).free_single_fp_reg \
1934 ? SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), (CUM).free_single_fp_reg) \
1935 : (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1936 && ((NAMED) || ! (CUM).prototype_p) \
1937 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (SFmode)) \
1938 ? ((! (CUM).prototype_p && TARGET_SHMEDIA) \
1939 ? SH5_PROTOTYPELESS_FLOAT_ARG ((CUM), (MODE)) \
1940 : SH5_PROTOTYPED_FLOAT_ARG ((CUM), (MODE), \
1941 FIRST_FP_PARM_REG \
1942 + (CUM).arg_count[(int) SH_ARG_FLOAT])) \
1943 : ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1944 && (! TARGET_SHCOMPACT \
1945 || (! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1946 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1947 (TYPE), (NAMED))))) \
1948 ? gen_rtx_REG ((MODE), (FIRST_PARM_REG \
1949 + (CUM).arg_count[(int) SH_ARG_INT])) \
1950 : 0) \
1951 : 0)
1953 /* Whether an argument must be passed by reference. On SHcompact, we
1954 pretend arguments wider than 32-bits that would have been passed in
1955 registers are passed by reference, so that an SHmedia trampoline
1956 loads them into the full 64-bits registers. */
1957 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM,MODE,TYPE,NAMED) \
1958 (MUST_PASS_IN_STACK ((MODE), (TYPE)) \
1959 || SHCOMPACT_BYREF ((CUM), (MODE), (TYPE), (NAMED)))
1961 #define SHCOMPACT_BYREF(CUM, MODE, TYPE, NAMED) \
1962 ((CUM).byref \
1963 = (TARGET_SHCOMPACT \
1964 && (CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1965 && (! (NAMED) || GET_SH_ARG_CLASS (MODE) == SH_ARG_INT \
1966 || (GET_SH_ARG_CLASS (MODE) == SH_ARG_FLOAT \
1967 && ((CUM).arg_count[(int) SH_ARG_FLOAT] \
1968 >= NPARM_REGS (SFmode)))) \
1969 && ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1970 : GET_MODE_SIZE (MODE)) > 4 \
1971 && ! SHCOMPACT_FORCE_ON_STACK ((MODE), (TYPE)) \
1972 && ! SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), \
1973 (TYPE), (NAMED))) \
1974 ? ((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1975 : GET_MODE_SIZE (MODE)) \
1976 : 0)
1978 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1979 register in SHcompact mode, it must be padded in the most
1980 significant end. This means that passing it by reference wouldn't
1981 pad properly on a big-endian machine. In this particular case, we
1982 pass this argument on the stack, in a way that the call trampoline
1983 will load its value into the appropriate register. */
1984 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1985 ((MODE) == BLKmode \
1986 && TARGET_SHCOMPACT \
1987 && ! TARGET_LITTLE_ENDIAN \
1988 && int_size_in_bytes (TYPE) > 4 \
1989 && int_size_in_bytes (TYPE) < 8)
1991 /* Minimum alignment for an argument to be passed by callee-copy
1992 reference. We need such arguments to be aligned to 8 byte
1993 boundaries, because they'll be loaded using quad loads. */
1994 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1996 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
1997 ((CUM).outgoing \
1998 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
1999 : GET_MODE_ALIGNMENT (MODE)) \
2000 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2002 /* The SH5 ABI requires floating-point arguments to be passed to
2003 functions without a prototype in both an FP register and a regular
2004 register or the stack. When passing the argument in both FP and
2005 general-purpose registers, list the FP register first. */
2006 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2007 (gen_rtx_PARALLEL \
2008 ((MODE), \
2009 gen_rtvec (2, \
2010 gen_rtx_EXPR_LIST \
2011 (VOIDmode, \
2012 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2013 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2014 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2015 : NULL_RTX), \
2016 const0_rtx), \
2017 gen_rtx_EXPR_LIST \
2018 (VOIDmode, \
2019 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2020 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2021 + (CUM).arg_count[(int) SH_ARG_INT]) \
2022 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2023 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2024 const0_rtx))))
2026 /* The SH5 ABI requires regular registers or stack slots to be
2027 reserved for floating-point arguments. Registers are taken care of
2028 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2029 Unfortunately, there's no way to just reserve a stack slot, so
2030 we'll end up needlessly storing a copy of the argument in the
2031 stack. For incoming arguments, however, the PARALLEL will be
2032 optimized to the register-only form, and the value in the stack
2033 slot won't be used at all. */
2034 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2035 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2036 ? gen_rtx_REG ((MODE), (REG)) \
2037 : gen_rtx_PARALLEL ((MODE), \
2038 gen_rtvec (2, \
2039 gen_rtx_EXPR_LIST \
2040 (VOIDmode, NULL_RTX, \
2041 const0_rtx), \
2042 gen_rtx_EXPR_LIST \
2043 (VOIDmode, gen_rtx_REG ((MODE), \
2044 (REG)), \
2045 const0_rtx))))
2047 #define STRICT_ARGUMENT_NAMING TARGET_SH5
2049 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI && ! TARGET_SH5)
2051 /* For an arg passed partly in registers and partly in memory,
2052 this is the number of registers used.
2053 For args passed entirely in registers or entirely in memory, zero.
2055 We sometimes split args. */
2057 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2058 ((! TARGET_SH5 \
2059 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2060 && ! TARGET_SH4 \
2061 && (ROUND_REG ((CUM), (MODE)) \
2062 + ((MODE) != BLKmode \
2063 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2064 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2065 > NPARM_REGS (MODE))) \
2066 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2067 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2068 && ! TARGET_SHCOMPACT) \
2069 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2070 : 0)
2072 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2073 (TARGET_SH5 && ((MODE) == BLKmode || (MODE) == TImode) \
2074 && ((CUM).arg_count[(int) SH_ARG_INT] \
2075 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2077 /* Perform any needed actions needed for a function that is receiving a
2078 variable number of arguments. */
2080 /* We actually emit the code in sh_expand_prologue. We used to use
2081 a static variable to flag that we need to emit this code, but that
2082 doesn't when inlining, when functions are deferred and then emitted
2083 later. Fortunately, we already have two flags that are part of struct
2084 function that tell if a function uses varargs or stdarg. */
2085 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) do \
2086 if (! current_function_stdarg) \
2087 abort (); \
2088 while (0)
2090 /* Define the `__builtin_va_list' type for the ABI. */
2091 #define BUILD_VA_LIST_TYPE(VALIST) \
2092 (VALIST) = sh_build_va_list ()
2094 /* Implement `va_start' for varargs and stdarg. */
2095 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2096 sh_va_start (valist, nextarg)
2098 /* Implement `va_arg'. */
2099 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2100 sh_va_arg (valist, type)
2102 /* Call the function profiler with a given profile label.
2103 We use two .aligns, so as to make sure that both the .long is aligned
2104 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2105 from the trapa instruction. */
2107 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2108 { \
2113 }
2115 /* Define this macro if the code for function profiling should come
2116 before the function prologue. Normally, the profiling code comes
2117 after. */
2119 #define PROFILE_BEFORE_PROLOGUE
2121 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2122 the stack pointer does not matter. The value is tested only in
2123 functions that have frame pointers.
2124 No definition is equivalent to always zero. */
2126 #define EXIT_IGNORE_STACK 1
2128 /*
2129 On the SH, the trampoline looks like
2130 2 0002 D202 mov.l l2,r2
2131 1 0000 D301 mov.l l1,r3
2132 3 0004 422B jmp @r2
2133 4 0006 0009 nop
2134 5 0008 00000000 l1: .long area
2135 6 000c 00000000 l2: .long function */
2137 /* Length in units of the trampoline for entering a nested function. */
2138 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2140 /* Alignment required for a trampoline in bits . */
2141 #define TRAMPOLINE_ALIGNMENT \
2142 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2143 : TARGET_SHMEDIA ? 256 : 64)
2145 /* Emit RTL insns to initialize the variable parts of a trampoline.
2146 FNADDR is an RTX for the address of the function's pure code.
2147 CXT is an RTX for the static chain value for the function. */
2149 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2150 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2152 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2154 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2155 { \
2156 if (TARGET_SHMEDIA) \
2157 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), GEN_INT (1), \
2158 gen_reg_rtx (Pmode), 0, \
2159 OPTAB_LIB_WIDEN); \
2160 } while (0)
2162 /* A C expression whose value is RTL representing the value of the return
2163 address for the frame COUNT steps up from the current frame.
2164 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2165 can ignore COUNT. */
2167 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2168 (((COUNT) == 0) \
2169 ? get_hard_reg_initial_val (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
2170 : (rtx) 0)
2172 /* A C expression whose value is RTL representing the location of the
2173 incoming return address at the beginning of any function, before the
2174 prologue. This RTL is either a REG, indicating that the return
2175 value is saved in REG, or a MEM representing a location in
2176 the stack. */
2177 #define INCOMING_RETURN_ADDR_RTX \
2178 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2179 \f
2180 /* Generate necessary RTL for __builtin_saveregs(). */
2181 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
2182 \f
2183 /* Addressing modes, and classification of registers for them. */
2184 #define HAVE_POST_INCREMENT TARGET_SH1
2185 #define HAVE_PRE_DECREMENT TARGET_SH1
2187 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2188 ? 0 : TARGET_SH1)
2189 #define USE_LOAD_PRE_DECREMENT(mode) 0
2190 #define USE_STORE_POST_INCREMENT(mode) 0
2191 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2192 ? 0 : TARGET_SH1)
2194 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
2195 < (TARGET_SMALLCODE ? 2 : \
2196 ((ALIGN >= 32) ? 16 : 2)))
2198 /* Macros to check register numbers against specific register classes. */
2200 /* These assume that REGNO is a hard or pseudo reg number.
2201 They give nonzero only if REGNO is a hard reg of the suitable class
2202 or a pseudo reg currently allocated to a suitable hard reg.
2203 Since they use reg_renumber, they are safe only once reg_renumber
2204 has been allocated, which happens in local-alloc.c. */
2206 #define REGNO_OK_FOR_BASE_P(REGNO) \
2207 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2208 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2209 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2210 (TARGET_SHMEDIA \
2211 ? (GENERAL_REGISTER_P (REGNO) \
2212 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2213 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2215 /* Maximum number of registers that can appear in a valid memory
2216 address. */
2218 #define MAX_REGS_PER_ADDRESS 2
2220 /* Recognize any constant value that is a valid address. */
2222 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2224 /* Nonzero if the constant value X is a legitimate general operand. */
2226 #define LEGITIMATE_CONSTANT_P(X) \
2227 (TARGET_SHMEDIA \
2228 ? ((GET_MODE (X) != DFmode \
2229 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2230 || (X) == CONST0_RTX (GET_MODE (X)) \
2231 || ! TARGET_SHMEDIA_FPU \
2232 || TARGET_SHMEDIA64) \
2233 : (GET_CODE (X) != CONST_DOUBLE \
2234 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2235 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2237 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2238 and check its validity for a certain class.
2239 We have two alternate definitions for each of them.
2240 The usual definition accepts all pseudo regs; the other rejects
2241 them unless they have been allocated suitable hard regs.
2242 The symbol REG_OK_STRICT causes the latter definition to be used. */
2244 #ifndef REG_OK_STRICT
2246 /* Nonzero if X is a hard reg that can be used as a base reg
2247 or if it is a pseudo reg. */
2248 #define REG_OK_FOR_BASE_P(X) \
2249 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2251 /* Nonzero if X is a hard reg that can be used as an index
2252 or if it is a pseudo reg. */
2253 #define REG_OK_FOR_INDEX_P(X) \
2254 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2255 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2257 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2258 or if X is a pseudo reg. */
2259 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2260 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2261 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2263 #else
2265 /* Nonzero if X is a hard reg that can be used as a base reg. */
2266 #define REG_OK_FOR_BASE_P(X) \
2267 REGNO_OK_FOR_BASE_P (REGNO (X))
2269 /* Nonzero if X is a hard reg that can be used as an index. */
2270 #define REG_OK_FOR_INDEX_P(X) \
2271 REGNO_OK_FOR_INDEX_P (REGNO (X))
2273 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2274 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2275 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2277 #endif
2279 /* The 'Q' constraint is a pc relative load operand. */
2280 #define EXTRA_CONSTRAINT_Q(OP) \
2281 (GET_CODE (OP) == MEM \
2282 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2283 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2284 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2285 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2286 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2288 /* The `S' constraint is a 16-bit constant, literal or symbolic. */
2289 #define EXTRA_CONSTRAINT_S(OP) \
2290 (GET_CODE (OP) == CONST \
2291 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2292 && GET_MODE (XEXP ((OP), 0)) == DImode \
2293 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2294 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2295 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2296 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2297 && (MOVI_SHORI_BASE_OPERAND_P \
2298 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2299 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2300 1)) == CONST_INT)))
2302 /* Check whether OP is a datalabel unspec. */
2303 #define DATALABEL_REF_NO_CONST_P(OP) \
2304 (GET_CODE (OP) == UNSPEC \
2305 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2306 && XVECLEN ((OP), 0) == 1 \
2307 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2308 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2310 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2311 CONST. */
2312 #define DATALABEL_REF_P(OP) \
2313 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2314 || DATALABEL_REF_NO_CONST_P (OP))
2316 #define GOT_ENTRY_P(OP) \
2317 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2318 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2320 #define GOTPLT_ENTRY_P(OP) \
2321 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2322 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2324 #define UNSPEC_GOTOFF_P(OP) \
2325 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2327 #define GOTOFF_P(OP) \
2328 (GET_CODE (OP) == CONST \
2329 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2330 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2331 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2332 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2334 #define PIC_ADDR_P(OP) \
2335 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2336 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2338 #define NON_PIC_REFERENCE_P(OP) \
2339 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2340 || DATALABEL_REF_P (OP) \
2341 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2342 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2343 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2344 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2346 #define PIC_REFERENCE_P(OP) \
2347 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2348 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2350 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2351 (flag_pic ? PIC_REFERENCE_P (OP) : NON_PIC_REFERENCE_P (OP))
2353 /* The `T' constraint is a label or a symbol. */
2354 #define EXTRA_CONSTRAINT_T(OP) \
2355 (NON_PIC_REFERENCE_P (OP))
2357 /* A zero in any shape or form. */
2358 #define EXTRA_CONSTRAINT_U(OP) \
2359 ((OP) == CONST0_RTX (GET_MODE (OP)))
2361 /* Any vector constant we can handle. */
2362 #define EXTRA_CONSTRAINT_W(OP) \
2363 (GET_CODE (OP) == CONST_VECTOR \
2364 && (sh_rep_vec ((OP), VOIDmode) \
2365 || (HOST_BITS_PER_WIDE_INT >= 64 \
2366 ? sh_const_vec ((OP), VOIDmode) \
2367 : sh_1el_vec ((OP), VOIDmode))))
2369 #define EXTRA_CONSTRAINT_Z(OP) \
2370 (GET_CODE (OP) == CONST_INT \
2371 && (INTVAL (OP) == (unsigned) 0xffffffff \
2372 || INTVAL (OP) == (HOST_WIDE_INT) -1 << 32))
2374 #define EXTRA_CONSTRAINT(OP, C) \
2381 : 0)
2382 \f
2383 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2384 that is a valid memory address for an instruction.
2385 The MODE argument is the machine mode for the MEM expression
2386 that wants to use this address. */
2388 #define MODE_DISP_OK_4(X,MODE) \
2389 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2390 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2392 #define MODE_DISP_OK_8(X,MODE) \
2393 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2394 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2396 #define BASE_REGISTER_RTX_P(X) \
2397 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2398 || (GET_CODE (X) == SUBREG \
2399 && GET_CODE (SUBREG_REG (X)) == REG \
2400 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2402 /* Since this must be r0, which is a single register class, we must check
2403 SUBREGs more carefully, to be sure that we don't accept one that extends
2404 outside the class. */
2405 #define INDEX_REGISTER_RTX_P(X) \
2406 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2407 || (GET_CODE (X) == SUBREG \
2408 && GET_CODE (SUBREG_REG (X)) == REG \
2409 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2411 /* Jump to LABEL if X is a valid address RTX. This must also take
2412 REG_OK_STRICT into account when deciding about valid registers, but it uses
2413 the above macros so we are in luck.
2415 Allow REG
2416 REG+disp
2417 REG+r0
2418 REG++
2419 --REG */
2421 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2422 into the FRx registers. We implement this by setting the maximum offset
2423 to zero when the value is SFmode. This also restricts loading of SFmode
2424 values into the integer registers, but that can't be helped. */
2426 /* The SH allows a displacement in a QI or HI amode, but only when the
2427 other operand is R0. GCC doesn't handle this very well, so we forgo
2428 all of that.
2430 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2431 DI can be any number 0..60. */
2433 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2434 do { \
2435 if (GET_CODE (OP) == CONST_INT) \
2436 { \
2437 if (TARGET_SHMEDIA) \
2438 { \
2439 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2440 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2441 && INTVAL (OP) >= -512 * MODE_SIZE \
2442 && INTVAL (OP) < 512 * MODE_SIZE) \
2443 goto LABEL; \
2444 else \
2445 break; \
2446 } \
2447 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2448 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2449 } \
2450 } while(0)
2452 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2453 { \
2454 if (BASE_REGISTER_RTX_P (X)) \
2455 goto LABEL; \
2456 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2457 && ! TARGET_SHMEDIA \
2458 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2459 goto LABEL; \
2460 else if (GET_CODE (X) == PLUS \
2461 && ((MODE) != PSImode || reload_completed)) \
2462 { \
2463 rtx xop0 = XEXP ((X), 0); \
2464 rtx xop1 = XEXP ((X), 1); \
2465 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2466 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2467 if (GET_MODE_SIZE (MODE) <= 4 \
2468 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2469 || (TARGET_SH4 && TARGET_FMOVD && MODE == DFmode)) \
2470 { \
2471 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2472 goto LABEL; \
2473 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2474 goto LABEL; \
2475 } \
2476 } \
2477 }
2478 \f
2479 /* Try machine-dependent ways of modifying an illegitimate address
2480 to be legitimate. If we find one, return the new, valid address.
2481 This macro is used in only one place: `memory_address' in explow.c.
2483 OLDX is the address as it was before break_out_memory_refs was called.
2484 In some cases it is useful to look at this to decide what needs to be done.
2486 MODE and WIN are passed so that this macro can use
2487 GO_IF_LEGITIMATE_ADDRESS.
2489 It is always safe for this macro to do nothing. It exists to recognize
2490 opportunities to optimize the output.
2492 For the SH, if X is almost suitable for indexing, but the offset is
2493 out of range, convert it into a normal form so that cse has a chance
2494 of reducing the number of address registers used. */
2496 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2497 { \
2498 if (flag_pic) \
2499 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2500 if (GET_CODE (X) == PLUS \
2501 && (GET_MODE_SIZE (MODE) == 4 \
2502 || GET_MODE_SIZE (MODE) == 8) \
2503 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2504 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2505 && ! TARGET_SHMEDIA \
2506 && ! (TARGET_SH4 && (MODE) == DFmode) \
2507 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2508 { \
2509 rtx index_rtx = XEXP ((X), 1); \
2510 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2511 rtx sum; \
2512 \
2513 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2514 /* On rare occasions, we might get an unaligned pointer \
2515 that is indexed in a way to give an aligned address. \
2517 /* Instead of offset_base 128..131 use 124..127, so that \
2519 if (offset > 127) \
2520 { \
2521 offset_base = ((offset + 4) & ~60) - 4; \
2522 } \
2523 else \
2524 offset_base = offset & ~60; \
2525 /* Sometimes the normal form does not suit DImode. We \
2526 could avoid that by using smaller ranges, but that \
2527 would give less optimized code when SImode is \
2529 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2530 { \
2531 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2532 GEN_INT (offset_base), NULL_RTX, 0, \
2533 OPTAB_LIB_WIDEN); \
2534 \
2535 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2536 goto WIN; \
2537 } \
2538 } \
2539 }
2541 /* A C compound statement that attempts to replace X, which is an address
2542 that needs reloading, with a valid memory address for an operand of
2543 mode MODE. WIN is a C statement label elsewhere in the code.
2545 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2546 of the address. That will allow inheritance of the address reloads. */
2548 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2549 { \
2550 if (GET_CODE (X) == PLUS \
2551 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2552 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2553 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2554 && ! TARGET_SHMEDIA \
2555 && ! (TARGET_SH4 && (MODE) == DFmode) \
2556 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2557 { \
2558 rtx index_rtx = XEXP (X, 1); \
2559 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2560 rtx sum; \
2561 \
2562 if (TARGET_SH2E && MODE == SFmode) \
2563 { \
2564 X = copy_rtx (X); \
2565 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2566 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2567 (TYPE)); \
2568 goto WIN; \
2569 } \
2570 /* Instead of offset_base 128..131 use 124..127, so that \
2572 if (offset > 127) \
2573 { \
2574 offset_base = ((offset + 4) & ~60) - 4; \
2575 } \
2576 else \
2577 offset_base = offset & ~60; \
2578 /* Sometimes the normal form does not suit DImode. We \
2579 could avoid that by using smaller ranges, but that \
2580 would give less optimized code when SImode is \
2582 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2583 { \
2584 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
2585 GEN_INT (offset_base)); \
2586 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
2587 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2588 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2589 (TYPE)); \
2590 goto WIN; \
2591 } \
2592 } \
2594 else if (GET_CODE (X) == PLUS \
2595 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2596 && GET_CODE (XEXP (X, 0)) == PLUS \
2597 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2598 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2599 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2600 && ! TARGET_SHMEDIA \
2601 && ! (TARGET_SH2E && MODE == SFmode)) \
2602 { \
2603 /* Because this address is so complex, we know it must have \
2604 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2606 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2607 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2608 goto WIN; \
2609 } \
2610 }
2612 /* Go to LABEL if ADDR (a legitimate address expression)
2613 has an effect that depends on the machine mode it is used for.
2615 ??? Strictly speaking, we should also include all indexed addressing,
2616 because the index scale factor is the length of the operand.
2617 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2618 high if we did that. So we rely on reload to fix things up. */
2620 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2621 { \
2622 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2623 goto LABEL; \
2624 }
2625 \f
2626 /* Specify the machine mode that this machine uses
2627 for the index in the tablejump instruction. */
2628 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2630 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2631 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2632 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2633 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2634 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2635 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2636 : SImode)
2638 /* Define as C expression which evaluates to nonzero if the tablejump
2639 instruction expects the table to contain offsets from the address of the
2640 table.
2641 Do not define this if the table should contain absolute addresses. */
2642 #define CASE_VECTOR_PC_RELATIVE 1
2644 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2645 #define FLOAT_TYPE_SIZE 32
2647 /* Since the SH2e has only `float' support, it is desirable to make all
2648 floating point types equivalent to `float'. */
2649 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4) ? 32 : 64)
2651 /* 'char' is signed by default. */
2652 #define DEFAULT_SIGNED_CHAR 1
2654 /* The type of size_t unsigned int. */
2657 #undef PTRDIFF_TYPE
2661 #define WCHAR_TYPE_SIZE 16
2665 /* Don't cse the address of the function being compiled. */
2666 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
2668 /* Max number of bytes we can move from memory to memory
2669 in one reasonably fast instruction. */
2670 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2672 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2673 MOVE_MAX is not a compile-time constant. */
2674 #define MAX_MOVE_MAX 8
2676 /* Max number of bytes we want move_by_pieces to be able to copy
2677 efficiently. */
2678 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2680 /* Define if operations between registers always perform the operation
2681 on the full register even if a narrower mode is specified. */
2682 #define WORD_REGISTER_OPERATIONS
2684 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2685 will either zero-extend or sign-extend. The value of this macro should
2686 be the code that says which one of the two operations is implicitly
2687 done, NIL if none. */
2688 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2689 /* FP registers can load SImode values, but don't implicitly sign-extend
2690 them to DImode. */
2691 #define LOAD_EXTEND_OP(MODE) \
2692 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2693 : (MODE) != SImode ? SIGN_EXTEND : NIL)
2695 /* Define if loading short immediate values into registers sign extends. */
2696 #define SHORT_IMMEDIATES_SIGN_EXTEND
2698 /* Nonzero if access to memory by bytes is no faster than for words. */
2699 #define SLOW_BYTE_ACCESS 1
2701 /* We assume that the store-condition-codes instructions store 0 for false
2702 and some other value for true. This is the value stored for true. */
2704 #define STORE_FLAG_VALUE 1
2706 /* Immediate shift counts are truncated by the output routines (or was it
2707 the assembler?). Shift counts in a register are truncated by SH. Note
2708 that the native compiler puts too large (> 32) immediate shift counts
2709 into a register and shifts by the register, letting the SH decide what
2710 to do instead of doing that itself. */
2711 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2712 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2713 expects - the sign bit is significant - so it appears that we need to
2714 leave this zero for correct SH3 code. */
2715 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
2717 /* All integers have the same format so truncation is easy. */
2718 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2720 /* Define this if addresses of constant functions
2721 shouldn't be put through pseudo regs where they can be cse'd.
2722 Desirable on machines where ordinary constants are expensive
2723 but a CALL with constant address is cheap. */
2724 /*#define NO_FUNCTION_CSE 1*/
2726 /* Chars and shorts should be passed as ints. */
2727 #define PROMOTE_PROTOTYPES 1
2729 /* The machine modes of pointers and functions. */
2730 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2731 #define FUNCTION_MODE Pmode
2733 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2734 are actually function calls with some special constraints on arguments
2735 and register usage.
2737 These macros tell reorg that the references to arguments and
2738 register clobbers for insns of type sfunc do not appear to happen
2739 until after the millicode call. This allows reorg to put insns
2740 which set the argument registers into the delay slot of the millicode
2741 call -- thus they act more like traditional CALL_INSNs.
2743 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2744 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2745 in particular. */
2747 #define INSN_SETS_ARE_DELAYED(X) \
2748 ((GET_CODE (X) == INSN \
2749 && GET_CODE (PATTERN (X)) != SEQUENCE \
2750 && GET_CODE (PATTERN (X)) != USE \
2751 && GET_CODE (PATTERN (X)) != CLOBBER \
2752 && get_attr_is_sfunc (X)))
2754 #define INSN_REFERENCES_ARE_DELAYED(X) \
2755 ((GET_CODE (X) == INSN \
2756 && GET_CODE (PATTERN (X)) != SEQUENCE \
2757 && GET_CODE (PATTERN (X)) != USE \
2758 && GET_CODE (PATTERN (X)) != CLOBBER \
2759 && get_attr_is_sfunc (X)))
2761 \f
2762 /* Position Independent Code. */
2764 /* The prefix used to mark SYMBOL_REFs that refer to data symbols. */
2767 /* Return true if SYM_NAME starts with SH_DATALABEL_ENCODING. */
2768 #define DATALABEL_SYMNAME_P(SYM_NAME) \
2769 (SH_DATALABEL_ENCODING[1] ? (abort (), 0) : \
2770 (SYM_NAME)[0] == SH_DATALABEL_ENCODING[0])
2772 /* Skip an optional SH_DATALABEL_ENCODING in the beginning of
2773 SYM_NAME. Then, remove a leading *, like the default definition in
2774 output.h. */
2775 #define STRIP_DATALABEL_ENCODING(VAR, SYM_NAME) \
2776 (VAR) = (SYM_NAME) + (DATALABEL_SYMNAME_P (SYM_NAME) \
2777 ? strlen (SH_DATALABEL_ENCODING) : 0)
2779 /* We can't directly access anything that contains a symbol,
2780 nor can we indirect via the constant pool. */
2781 #define LEGITIMATE_PIC_OPERAND_P(X) \
2782 (! nonpic_symbol_mentioned_p (X) \
2783 && (GET_CODE (X) != SYMBOL_REF \
2784 || ! CONSTANT_POOL_ADDRESS_P (X) \
2785 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))
2787 #define SYMBOLIC_CONST_P(X) \
2788 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2789 && nonpic_symbol_mentioned_p (X))
2790 \f
2791 /* TLS. */
2793 /* The prefix used to mark SYMBOL_REFs that refer to TLS symbols. */
2796 /* Return true if SYM_NAME starts with SH_TLS_ENCODING. */
2797 #define TLS_SYMNAME_P(SYM_NAME) \
2798 ((SYM_NAME)[0] == SH_TLS_ENCODING[0])
2800 /* Skip an optional SH_TLS_ENCODING in the beginning of SYM_NAME. */
2801 #define STRIP_TLS_ENCODING(VAR, SYM_NAME) \
2802 (VAR) = (SYM_NAME) + (TLS_SYMNAME_P (SYM_NAME) \
2803 ? strlen (SH_TLS_ENCODING) + 1 : 0)
2804 \f
2805 /* Compute extra cost of moving data between one register class
2806 and another. */
2808 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2809 uses this information. Hence, the general register <-> floating point
2810 register information here is not used for SFmode. */
2812 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2813 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2814 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2816 #define REGCLASS_HAS_FP_REG(CLASS) \
2817 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2818 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2820 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2821 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2823 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2824 would be so that people with slow memory systems could generate
2825 different code that does fewer memory accesses. */
2827 /* A C expression for the cost of a branch instruction. A value of 1
2828 is the default; other values are interpreted relative to that.
2829 The SH1 does not have delay slots, hence we get a pipeline stall
2830 at every branch. The SH4 is superscalar, so the single delay slot
2831 is not sufficient to keep both pipelines filled. */
2832 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2833 \f
2834 /* Assembler output control. */
2836 /* A C string constant describing how to begin a comment in the target
2837 assembler language. The compiler assumes that the comment will end at
2838 the end of the line. */
2841 /* The text to go at the start of the assembler file. */
2842 #define ASM_FILE_START(STREAM) \
2843 output_file_start (STREAM)
2850 /* How to change between sections. */
2852 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2855 #if defined CRT_BEGIN || defined CRT_END
2856 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2857 # undef TEXT_SECTION_ASM_OP
2858 # if __SHMEDIA__ == 1 && __SH5__ == 32
2860 # else
2862 # endif
2863 #endif
2866 /* If defined, a C expression whose value is a string containing the
2867 assembler operation to identify the following data as
2868 uninitialized global data. If not defined, and neither
2869 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2870 uninitialized global data will be output in the data section if
2871 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2872 used. */
2873 #ifndef BSS_SECTION_ASM_OP
2875 #endif
2877 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2878 separate, explicit argument. If you define this macro, it is used
2879 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2880 handling the required alignment of the variable. The alignment is
2881 specified as the number of bits.
2883 Try to use function `asm_output_aligned_bss' defined in file
2884 `varasm.c' when defining this macro. */
2885 #ifndef ASM_OUTPUT_ALIGNED_BSS
2886 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2887 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2888 #endif
2890 /* Define this so that jump tables go in same section as the current function,
2891 which could be text or it could be a user defined section. */
2892 #define JUMP_TABLES_IN_TEXT_SECTION 1
2894 #undef DO_GLOBAL_CTORS_BODY
2895 #define DO_GLOBAL_CTORS_BODY \
2896 { \
2897 typedef (*pfunc)(); \
2898 extern pfunc __ctors[]; \
2899 extern pfunc __ctors_end[]; \
2900 pfunc *p; \
2901 for (p = __ctors_end; p > __ctors; ) \
2902 { \
2903 (*--p)(); \
2904 } \
2905 }
2907 #undef DO_GLOBAL_DTORS_BODY
2908 #define DO_GLOBAL_DTORS_BODY \
2909 { \
2910 typedef (*pfunc)(); \
2911 extern pfunc __dtors[]; \
2912 extern pfunc __dtors_end[]; \
2913 pfunc *p; \
2914 for (p = __dtors; p < __dtors_end; p++) \
2915 { \
2916 (*p)(); \
2917 } \
2918 }
2920 #define ASM_OUTPUT_REG_PUSH(file, v) \
2923 #define ASM_OUTPUT_REG_POP(file, v) \
2926 /* DBX register number for a given compiler register number. */
2927 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2928 to match gdb. */
2929 /* svr4.h undefines this macro, yet we really want to use the same numbers
2930 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2931 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2932 register exists, so we should return -1 for invalid register numbers. */
2933 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2935 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2936 (GENERAL_REGISTER_P (REGNO) \
2937 ? ((REGNO) - FIRST_GENERAL_REG) \
2938 : FP_REGISTER_P (REGNO) \
2939 ? ((REGNO) - FIRST_FP_REG + (TARGET_SH5 ? (TARGET_SHCOMPACT ? 245 \
2940 : 77) : 25)) \
2941 : XD_REGISTER_P (REGNO) \
2942 ? ((REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2943 : TARGET_REGISTER_P (REGNO) \
2944 ? ((REGNO) - FIRST_TARGET_REG + 68) \
2945 : (REGNO) == PR_REG \
2946 ? (TARGET_SH5 ? 241 : 17) \
2947 : (REGNO) == PR_MEDIA_REG \
2948 ? (TARGET_SH5 ? 18 : -1) \
2949 : (REGNO) == T_REG \
2950 ? (TARGET_SH5 ? 242 : 18) \
2951 : (REGNO) == GBR_REG \
2952 ? (TARGET_SH5 ? 238 : 19) \
2953 : (REGNO) == MACH_REG \
2954 ? (TARGET_SH5 ? 239 : 20) \
2955 : (REGNO) == MACL_REG \
2956 ? (TARGET_SH5 ? 240 : 21) \
2957 : (REGNO) == FPUL_REG \
2958 ? (TARGET_SH5 ? 244 : 23) \
2959 : -1)
2961 /* This is how to output a reference to a user-level label named NAME. */
2962 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
2963 do \
2964 { \
2965 const char * lname; \
2966 \
2967 STRIP_DATALABEL_ENCODING (lname, (NAME)); \
2968 STRIP_TLS_ENCODING (lname, lname); \
2970 fputs (lname + 1, (FILE)); \
2971 else \
2973 } \
2974 while (0)
2976 /* This is how to output a reference to a symbol_ref. On SH5,
2977 references to non-code symbols must be preceded by `datalabel'. */
2978 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2979 do \
2980 { \
2981 if (TARGET_SH5 \
2982 && (DATALABEL_SYMNAME_P (XSTR ((SYM), 0)) \
2983 || CONSTANT_POOL_ADDRESS_P (SYM))) \
2985 assemble_name ((FILE), XSTR ((SYM), 0)); \
2986 } \
2987 while (0)
2989 /* This is how to output an assembler line
2990 that says to advance the location counter
2991 to a multiple of 2**LOG bytes. */
2993 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2994 if ((LOG) != 0) \
2997 /* Globalizing directive for a label. */
3000 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3002 /* Output a relative address table. */
3004 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3005 switch (GET_MODE (BODY)) \
3006 { \
3007 case SImode: \
3008 if (TARGET_SH5) \
3009 { \
3011 (VALUE), (REL)); \
3012 break; \
3013 } \
3015 break; \
3016 case HImode: \
3017 if (TARGET_SH5) \
3018 { \
3020 (VALUE), (REL)); \
3021 break; \
3022 } \
3024 break; \
3025 case QImode: \
3026 if (TARGET_SH5) \
3027 { \
3029 (VALUE), (REL)); \
3030 break; \
3031 } \
3033 break; \
3034 default: \
3035 break; \
3036 }
3038 /* Output an absolute table element. */
3040 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3041 if (! optimize || TARGET_BIGTABLE) \
3043 else \
3046 \f
3047 /* A C statement to be executed just prior to the output of
3048 assembler code for INSN, to modify the extracted operands so
3049 they will be output differently.
3051 Here the argument OPVEC is the vector containing the operands
3052 extracted from INSN, and NOPERANDS is the number of elements of
3053 the vector which contain meaningful data for this insn.
3054 The contents of this vector are what will be used to convert the insn
3055 template into assembler code, so you can change the assembler output
3056 by changing the contents of the vector. */
3058 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3059 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3061 /* Print operand X (an rtx) in assembler syntax to file FILE.
3062 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3063 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3065 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3067 /* Print a memory address as an operand to reference that memory location. */
3069 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3071 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3075 /* Recognize machine-specific patterns that may appear within
3076 constants. Used for PIC-specific UNSPECs. */
3077 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3078 do \
3079 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3080 { \
3081 switch (XINT ((X), 1)) \
3082 { \
3083 case UNSPEC_DATALABEL: \
3085 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3086 break; \
3087 case UNSPEC_PIC: \
3089 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3090 break; \
3091 case UNSPEC_GOT: \
3092 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3094 break; \
3095 case UNSPEC_GOTOFF: \
3096 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3098 break; \
3099 case UNSPEC_PLT: \
3100 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3102 break; \
3103 case UNSPEC_GOTPLT: \
3104 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3106 break; \
3107 case UNSPEC_DTPOFF: \
3108 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3110 break; \
3111 case UNSPEC_GOTTPOFF: \
3112 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3114 break; \
3115 case UNSPEC_TPOFF: \
3116 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3118 break; \
3119 case UNSPEC_CALLER: \
3120 { \
3121 char name[32]; \
3123 ASM_GENERATE_INTERNAL_LABEL \
3125 assemble_name ((STREAM), name); \
3126 } \
3127 break; \
3128 default: \
3129 goto FAIL; \
3130 } \
3131 break; \
3132 } \
3133 else \
3134 goto FAIL; \
3135 while (0)
3137 \f
3141 /* Which processor to schedule for. The elements of the enumeration must
3142 match exactly the cpu attribute in the sh.md file. */
3145 PROCESSOR_SH1,
3146 PROCESSOR_SH2,
3147 PROCESSOR_SH2E,
3148 PROCESSOR_SH3,
3149 PROCESSOR_SH3E,
3150 PROCESSOR_SH4,
3151 PROCESSOR_SH5
3152 };
3154 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3159 enum mdep_reorg_phase_e
3160 {
3161 SH_BEFORE_MDEP_REORG,
3162 SH_INSERT_USES_LABELS,
3163 SH_SHORTEN_BRANCHES0,
3164 SH_FIXUP_PCLOAD,
3165 SH_SHORTEN_BRANCHES1,
3166 SH_AFTER_MDEP_REORG
3167 };
3171 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
3173 /* Generate calls to memcpy, memcmp and memset. */
3175 #define TARGET_MEM_FUNCTIONS
3177 /* Handle Hitachi compiler's pragmas. */
3178 #define REGISTER_TARGET_PRAGMAS() do { \
3182 } while (0)
3184 /* Set when processing a function with pragma interrupt turned on. */
3188 /* Set when processing a function with interrupt attribute. */
3192 /* Set to an RTX containing the address of the stack to switch to
3193 for interrupt functions. */
3198 \f
3199 /* Instructions with unfilled delay slots take up an
3200 extra two bytes for the nop in the delay slot.
3201 sh-dsp parallel processing insns are four bytes long. */
3203 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3204 (LENGTH) += sh_insn_length_adjustment (X);
3205 \f
3206 /* Define the codes that are matched by predicates in sh.c. */
3207 #define PREDICATE_CODES \
3245 #define SPECIAL_MODE_PREDICATES \
3249 /* This line intentionally left blank. */
3251 #define any_register_operand register_operand
3253 /* Define this macro if it is advisable to hold scalars in registers
3254 in a wider mode than that declared by the program. In such cases,
3255 the value is constrained to be within the bounds of the declared
3256 type, but kept valid in the wider mode. The signedness of the
3257 extension may differ from that of the type.
3259 Leaving the unsignedp unchanged gives better code than always setting it
3260 to 0. This is despite the fact that we have only signed char and short
3261 load instructions. */
3262 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3263 if (GET_MODE_CLASS (MODE) == MODE_INT \
3264 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3265 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3266 (MODE) = (TARGET_SH1 ? SImode : DImode);
3268 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
3269 extensions applied to char/short functions arguments. Defining
3270 PROMOTE_FUNCTION_RETURN does the same for function returns. */
3272 #define PROMOTE_FUNCTION_ARGS
3273 #define PROMOTE_FUNCTION_RETURN
3275 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3277 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3278 and poping arguments. However, we do have push/pop instructions, and
3279 rather limited offsets (4 bits) in load/store instructions, so it isn't
3280 clear if this would give better code. If implemented, should check for
3281 compatibility problems. */
3283 #define SH_DYNAMIC_SHIFT_COST \
3284 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3287 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3289 #define OPTIMIZE_MODE_SWITCHING(ENTITY) TARGET_SH4
3291 #define NORMAL_MODE(ENTITY) \
3292 (sh_cfun_interrupt_handler_p () ? FP_MODE_NONE \
3293 : TARGET_FPU_SINGLE ? FP_MODE_SINGLE \
3294 : FP_MODE_DOUBLE)
3296 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3297 && (REGNO) == FPSCR_REG)
3299 #define MODE_NEEDED(ENTITY, INSN) \
3300 (recog_memoized (INSN) >= 0 \
3301 ? get_attr_fp_mode (INSN) \
3302 : FP_MODE_NONE)
3304 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3305 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3307 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3308 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3310 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3311 sh_can_redirect_branch ((INSN), (SEQ))
3313 #define DWARF_FRAME_RETURN_COLUMN \
3314 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3316 #define EH_RETURN_DATA_REGNO(N) \
3317 ((N) < 4 ? (N) + (TARGET_SH5 ? 2 : 4) : INVALID_REGNUM)
3319 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)
3321 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3322 /* SH constant pool breaks the devices in crtstuff.c to control section
3323 in where code resides. We have to write it as asm code. */
3324 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3335 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3336 (REGNO (hard_reg) == (TARGET_SH5 ? PR_MEDIA_REG : PR_REG) \
3337 ? (current_function_is_leaf && ! sh_pr_n_sets () \
3338 ? (hard_reg) \
3339 : gen_rtx_MEM (Pmode, TARGET_SH5 \
3340 ? (plus_constant (arg_pointer_rtx, \
3341 TARGET_SHMEDIA64 ? -8 : -4)) \
3342 : frame_pointer_rtx)) \
3343 : NULL_RTX)