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fortran frontend:
[official-gcc.git] / gcc / config / mips / mips.h
blob0e90d030d3478d9c0538ab8d95b87cded38082fc
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
24 Boston, MA 02110-1301, USA. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF,
45 PROCESSOR_24KX,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF,
48 PROCESSOR_74KX,
49 PROCESSOR_M4K,
50 PROCESSOR_R3900,
51 PROCESSOR_R6000,
52 PROCESSOR_R4000,
53 PROCESSOR_R4100,
54 PROCESSOR_R4111,
55 PROCESSOR_R4120,
56 PROCESSOR_R4130,
57 PROCESSOR_R4300,
58 PROCESSOR_R4600,
59 PROCESSOR_R4650,
60 PROCESSOR_R5000,
61 PROCESSOR_R5400,
62 PROCESSOR_R5500,
63 PROCESSOR_R7000,
64 PROCESSOR_R8000,
65 PROCESSOR_R9000,
66 PROCESSOR_SB1,
67 PROCESSOR_SB1A,
68 PROCESSOR_SR71000,
69 PROCESSOR_MAX
70 };
71
72 /* Costs of various operations on the different architectures. */
73
74 struct mips_rtx_cost_data
75 {
76 unsigned short fp_add;
77 unsigned short fp_mult_sf;
78 unsigned short fp_mult_df;
79 unsigned short fp_div_sf;
80 unsigned short fp_div_df;
81 unsigned short int_mult_si;
82 unsigned short int_mult_di;
83 unsigned short int_div_si;
84 unsigned short int_div_di;
85 unsigned short branch_cost;
86 unsigned short memory_latency;
87 };
88
89 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
90 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
91 to work on a 64-bit machine. */
92
93 #define ABI_32 0
94 #define ABI_N32 1
95 #define ABI_64 2
96 #define ABI_EABI 3
97 #define ABI_O64 4
98
99 /* Information about one recognized processor. Defined here for the
100 benefit of TARGET_CPU_CPP_BUILTINS. */
101 struct mips_cpu_info {
102 /* The 'canonical' name of the processor as far as GCC is concerned.
103 It's typically a manufacturer's prefix followed by a numerical
104 designation. It should be lowercase. */
105 const char *name;
106
107 /* The internal processor number that most closely matches this
108 entry. Several processors can have the same value, if there's no
109 difference between them from GCC's point of view. */
110 enum processor_type cpu;
111
112 /* The ISA level that the processor implements. */
113 int isa;
114 };
115
116 #ifndef USED_FOR_TARGET
117 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
118 extern const char *current_function_file; /* filename current function is in */
119 extern int num_source_filenames; /* current .file # */
120 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
121 extern int sym_lineno; /* sgi next label # for each stmt */
122 extern int set_noreorder; /* # of nested .set noreorder's */
123 extern int set_nomacro; /* # of nested .set nomacro's */
124 extern int set_noat; /* # of nested .set noat's */
125 extern int set_volatile; /* # of nested .set volatile's */
126 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
127 extern int mips_dbx_regno[]; /* Map register # to debug register # */
128 extern bool mips_split_p[];
129 extern GTY(()) rtx cmp_operands[2];
130 extern enum processor_type mips_arch; /* which cpu to codegen for */
131 extern enum processor_type mips_tune; /* which cpu to schedule for */
132 extern int mips_isa; /* architectural level */
133 extern int mips_abi; /* which ABI to use */
134 extern int mips16_hard_float; /* mips16 without -msoft-float */
135 extern const struct mips_cpu_info mips_cpu_info_table[];
136 extern const struct mips_cpu_info *mips_arch_info;
137 extern const struct mips_cpu_info *mips_tune_info;
138 extern const struct mips_rtx_cost_data *mips_cost;
139 #endif
140
141 /* Macros to silence warnings about numbers being signed in traditional
142 C and unsigned in ISO C when compiled on 32-bit hosts. */
143
144 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
145 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
146 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
147
148 \f
149 /* Run-time compilation parameters selecting different hardware subsets. */
150
151 /* True if we are generating position-independent VxWorks RTP code. */
152 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
153
154 /* True if the call patterns should be split into a jalr followed by
155 an instruction to restore $gp. It is only safe to split the load
156 from the call when every use of $gp is explicit. */
157
158 #define TARGET_SPLIT_CALLS \
159 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
160
161 /* True if we're generating a form of -mabicalls in which we can use
162 operators like %hi and %lo to refer to locally-binding symbols.
163 We can only do this for -mno-shared, and only then if we can use
164 relocation operations instead of assembly macros. It isn't really
165 worth using absolute sequences for 64-bit symbols because GOT
166 accesses are so much shorter. */
167
168 #define TARGET_ABSOLUTE_ABICALLS \
169 (TARGET_ABICALLS \
170 && !TARGET_SHARED \
171 && TARGET_EXPLICIT_RELOCS \
172 && !ABI_HAS_64BIT_SYMBOLS)
173
174 /* True if we can optimize sibling calls. For simplicity, we only
175 handle cases in which call_insn_operand will reject invalid
176 sibcall addresses. There are two cases in which this isn't true:
177
178 - TARGET_MIPS16. call_insn_operand accepts constant addresses
179 but there is no direct jump instruction. It isn't worth
180 using sibling calls in this case anyway; they would usually
181 be longer than normal calls.
182
183 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
184 accepts global constants, but all sibcalls must be indirect. */
185 #define TARGET_SIBCALLS \
186 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
187
188 /* True if we need to use a global offset table to access some symbols. */
189 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
190
191 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
192 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
193
194 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
195 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
196
197 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
198 This is true for both the PIC and non-PIC VxWorks RTP modes. */
199 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
200
201 /* True if .gpword or .gpdword should be used for switch tables.
202
203 Although GAS does understand .gpdword, the SGI linker mishandles
204 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
205 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
206 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
207
208 /* Generate mips16 code */
209 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
210 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
211 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
212
213 /* Generic ISA defines. */
214 #define ISA_MIPS1 (mips_isa == 1)
215 #define ISA_MIPS2 (mips_isa == 2)
216 #define ISA_MIPS3 (mips_isa == 3)
217 #define ISA_MIPS4 (mips_isa == 4)
218 #define ISA_MIPS32 (mips_isa == 32)
219 #define ISA_MIPS32R2 (mips_isa == 33)
220 #define ISA_MIPS64 (mips_isa == 64)
221
222 /* Architecture target defines. */
223 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
224 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
225 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
226 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
227 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
228 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
229 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
230 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
231 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
232 || mips_arch == PROCESSOR_SB1A)
233 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
234
235 /* Scheduling target defines. */
236 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
237 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
238 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
239 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
240 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
241 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
242 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
243 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
244 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
245 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
246 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
247 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
248 || mips_tune == PROCESSOR_SB1A)
249 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
250 || mips_tune == PROCESSOR_74KF \
251 || mips_tune == PROCESSOR_74KX)
252
253 /* True if the pre-reload scheduler should try to create chains of
254 multiply-add or multiply-subtract instructions. For example,
255 suppose we have:
256
257 t1 = a * b
258 t2 = t1 + c * d
259 t3 = e * f
260 t4 = t3 - g * h
261
262 t1 will have a higher priority than t2 and t3 will have a higher
263 priority than t4. However, before reload, there is no dependence
264 between t1 and t3, and they can often have similar priorities.
265 The scheduler will then tend to prefer:
266
267 t1 = a * b
268 t3 = e * f
269 t2 = t1 + c * d
270 t4 = t3 - g * h
271
272 which stops us from making full use of macc/madd-style instructions.
273 This sort of situation occurs frequently in Fourier transforms and
274 in unrolled loops.
275
276 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
277 queue so that chained multiply-add and multiply-subtract instructions
278 appear ahead of any other instruction that is likely to clobber lo.
279 In the example above, if t2 and t3 become ready at the same time,
280 the code ensures that t2 is scheduled first.
281
282 Multiply-accumulate instructions are a bigger win for some targets
283 than others, so this macro is defined on an opt-in basis. */
284 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
285 || TUNE_MIPS4120 \
286 || TUNE_MIPS4130)
287
288 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
289 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
290
291 /* Similar to TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT, but reflect the ABI
292 in use rather than whether the FPU is directly accessible. */
293 #define TARGET_HARD_FLOAT_ABI (TARGET_HARD_FLOAT || mips16_hard_float)
294 #define TARGET_SOFT_FLOAT_ABI (!TARGET_HARD_FLOAT_ABI)
295
296 /* IRIX specific stuff. */
297 #define TARGET_IRIX 0
298 #define TARGET_IRIX6 0
299
300 /* Define preprocessor macros for the -march and -mtune options.
301 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
302 processor. If INFO's canonical name is "foo", define PREFIX to
303 be "foo", and define an additional macro PREFIX_FOO. */
304 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
305 do \
306 { \
307 char *macro, *p; \
308 \
309 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
310 for (p = macro; *p != 0; p++) \
311 *p = TOUPPER (*p); \
312 \
313 builtin_define (macro); \
314 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
315 free (macro); \
316 } \
317 while (0)
318
319 /* Target CPU builtins. */
320 #define TARGET_CPU_CPP_BUILTINS() \
321 do \
322 { \
323 /* Everyone but IRIX defines this to mips. */ \
324 if (!TARGET_IRIX) \
325 builtin_assert ("machine=mips"); \
326 \
327 builtin_assert ("cpu=mips"); \
328 builtin_define ("__mips__"); \
329 builtin_define ("_mips"); \
330 \
331 /* We do this here because __mips is defined below \
332 and so we can't use builtin_define_std. */ \
333 if (!flag_iso) \
334 builtin_define ("mips"); \
335 \
336 if (TARGET_64BIT) \
337 builtin_define ("__mips64"); \
338 \
339 if (!TARGET_IRIX) \
340 { \
341 /* Treat _R3000 and _R4000 like register-size \
342 defines, which is how they've historically \
343 been used. */ \
344 if (TARGET_64BIT) \
345 { \
346 builtin_define_std ("R4000"); \
347 builtin_define ("_R4000"); \
348 } \
349 else \
350 { \
351 builtin_define_std ("R3000"); \
352 builtin_define ("_R3000"); \
353 } \
354 } \
355 if (TARGET_FLOAT64) \
356 builtin_define ("__mips_fpr=64"); \
357 else \
358 builtin_define ("__mips_fpr=32"); \
359 \
360 if (TARGET_MIPS16) \
361 builtin_define ("__mips16"); \
362 \
363 if (TARGET_MIPS3D) \
364 builtin_define ("__mips3d"); \
365 \
366 if (TARGET_DSP) \
367 builtin_define ("__mips_dsp"); \
368 \
369 if (TARGET_DSPR2) \
370 builtin_define ("__mips_dspr2"); \
371 \
372 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
373 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
374 \
375 if (ISA_MIPS1) \
376 { \
377 builtin_define ("__mips=1"); \
378 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
379 } \
380 else if (ISA_MIPS2) \
381 { \
382 builtin_define ("__mips=2"); \
383 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
384 } \
385 else if (ISA_MIPS3) \
386 { \
387 builtin_define ("__mips=3"); \
388 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
389 } \
390 else if (ISA_MIPS4) \
391 { \
392 builtin_define ("__mips=4"); \
393 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
394 } \
395 else if (ISA_MIPS32) \
396 { \
397 builtin_define ("__mips=32"); \
398 builtin_define ("__mips_isa_rev=1"); \
399 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
400 } \
401 else if (ISA_MIPS32R2) \
402 { \
403 builtin_define ("__mips=32"); \
404 builtin_define ("__mips_isa_rev=2"); \
405 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
406 } \
407 else if (ISA_MIPS64) \
408 { \
409 builtin_define ("__mips=64"); \
410 builtin_define ("__mips_isa_rev=1"); \
411 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
412 } \
413 \
414 /* These defines reflect the ABI in use, not whether the \
415 FPU is directly accessible. */ \
416 if (TARGET_HARD_FLOAT_ABI) \
417 builtin_define ("__mips_hard_float"); \
418 else \
419 builtin_define ("__mips_soft_float"); \
420 \
421 if (TARGET_SINGLE_FLOAT) \
422 builtin_define ("__mips_single_float"); \
423 \
424 if (TARGET_PAIRED_SINGLE_FLOAT) \
425 builtin_define ("__mips_paired_single_float"); \
426 \
427 if (TARGET_BIG_ENDIAN) \
428 { \
429 builtin_define_std ("MIPSEB"); \
430 builtin_define ("_MIPSEB"); \
431 } \
432 else \
433 { \
434 builtin_define_std ("MIPSEL"); \
435 builtin_define ("_MIPSEL"); \
436 } \
437 \
438 /* Macros dependent on the C dialect. */ \
439 if (preprocessing_asm_p ()) \
440 { \
441 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
442 builtin_define ("_LANGUAGE_ASSEMBLY"); \
443 } \
444 else if (c_dialect_cxx ()) \
445 { \
446 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
447 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
448 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
449 } \
450 else \
451 { \
452 builtin_define_std ("LANGUAGE_C"); \
453 builtin_define ("_LANGUAGE_C"); \
454 } \
455 if (c_dialect_objc ()) \
456 { \
457 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
458 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
459 /* Bizarre, but needed at least for Irix. */ \
460 builtin_define_std ("LANGUAGE_C"); \
461 builtin_define ("_LANGUAGE_C"); \
462 } \
463 \
464 if (mips_abi == ABI_EABI) \
465 builtin_define ("__mips_eabi"); \
466 \
467 } while (0)
468
469 /* Default target_flags if no switches are specified */
470
471 #ifndef TARGET_DEFAULT
472 #define TARGET_DEFAULT 0
473 #endif
474
475 #ifndef TARGET_CPU_DEFAULT
476 #define TARGET_CPU_DEFAULT 0
477 #endif
478
479 #ifndef TARGET_ENDIAN_DEFAULT
480 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
481 #endif
482
483 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
484 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
485 #endif
486
487 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
488 #ifndef MIPS_ISA_DEFAULT
489 #ifndef MIPS_CPU_STRING_DEFAULT
490 #define MIPS_CPU_STRING_DEFAULT "from-abi"
491 #endif
492 #endif
493
494 #ifdef IN_LIBGCC2
495 #undef TARGET_64BIT
496 /* Make this compile time constant for libgcc2 */
497 #ifdef __mips64
498 #define TARGET_64BIT 1
499 #else
500 #define TARGET_64BIT 0
501 #endif
502 #endif /* IN_LIBGCC2 */
503
504 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
505
506 #ifndef MULTILIB_ENDIAN_DEFAULT
507 #if TARGET_ENDIAN_DEFAULT == 0
508 #define MULTILIB_ENDIAN_DEFAULT "EL"
509 #else
510 #define MULTILIB_ENDIAN_DEFAULT "EB"
511 #endif
512 #endif
513
514 #ifndef MULTILIB_ISA_DEFAULT
515 # if MIPS_ISA_DEFAULT == 1
516 # define MULTILIB_ISA_DEFAULT "mips1"
517 # else
518 # if MIPS_ISA_DEFAULT == 2
519 # define MULTILIB_ISA_DEFAULT "mips2"
520 # else
521 # if MIPS_ISA_DEFAULT == 3
522 # define MULTILIB_ISA_DEFAULT "mips3"
523 # else
524 # if MIPS_ISA_DEFAULT == 4
525 # define MULTILIB_ISA_DEFAULT "mips4"
526 # else
527 # if MIPS_ISA_DEFAULT == 32
528 # define MULTILIB_ISA_DEFAULT "mips32"
529 # else
530 # if MIPS_ISA_DEFAULT == 33
531 # define MULTILIB_ISA_DEFAULT "mips32r2"
532 # else
533 # if MIPS_ISA_DEFAULT == 64
534 # define MULTILIB_ISA_DEFAULT "mips64"
535 # else
536 # define MULTILIB_ISA_DEFAULT "mips1"
537 # endif
538 # endif
539 # endif
540 # endif
541 # endif
542 # endif
543 # endif
544 #endif
545
546 #ifndef MULTILIB_DEFAULTS
547 #define MULTILIB_DEFAULTS \
548 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
549 #endif
550
551 /* We must pass -EL to the linker by default for little endian embedded
552 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
553 linker will default to using big-endian output files. The OUTPUT_FORMAT
554 line must be in the linker script, otherwise -EB/-EL will not work. */
555
556 #ifndef ENDIAN_SPEC
557 #if TARGET_ENDIAN_DEFAULT == 0
558 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
559 #else
560 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
561 #endif
562 #endif
563
564 /* Support for a compile-time default CPU, et cetera. The rules are:
565 --with-arch is ignored if -march is specified or a -mips is specified
566 (other than -mips16).
567 --with-tune is ignored if -mtune is specified.
568 --with-abi is ignored if -mabi is specified.
569 --with-float is ignored if -mhard-float or -msoft-float are
570 specified.
571 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
572 specified. */
573 #define OPTION_DEFAULT_SPECS \
574 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
575 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
576 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
577 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
578 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
579
580
581 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
582 && ISA_HAS_COND_TRAP)
583
584 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
585 && !TARGET_SR71K \
586 && !TARGET_MIPS16)
587
588 /* True if the ABI can only work with 64-bit integer registers. We
589 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
590 otherwise floating-point registers must also be 64-bit. */
591 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
592
593 /* Likewise for 32-bit regs. */
594 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
595
596 /* True if symbols are 64 bits wide. At present, n64 is the only
597 ABI for which this is true. */
598 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
599
600 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
601 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
602 || ISA_MIPS4 \
603 || ISA_MIPS64)
604
605 /* ISA has branch likely instructions (e.g. mips2). */
606 /* Disable branchlikely for tx39 until compare rewrite. They haven't
607 been generated up to this point. */
608 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
609
610 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
611 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
612 || TARGET_MIPS5400 \
613 || TARGET_MIPS5500 \
614 || TARGET_MIPS7000 \
615 || TARGET_MIPS9000 \
616 || TARGET_MAD \
617 || ISA_MIPS32 \
618 || ISA_MIPS32R2 \
619 || ISA_MIPS64) \
620 && !TARGET_MIPS16)
621
622 /* ISA has the conditional move instructions introduced in mips4. */
623 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
624 || ISA_MIPS32 \
625 || ISA_MIPS32R2 \
626 || ISA_MIPS64) \
627 && !TARGET_MIPS5500 \
628 && !TARGET_MIPS16)
629
630 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
631 branch on CC, and move (both FP and non-FP) on CC. */
632 #define ISA_HAS_8CC (ISA_MIPS4 \
633 || ISA_MIPS32 \
634 || ISA_MIPS32R2 \
635 || ISA_MIPS64)
636
637 /* This is a catch all for other mips4 instructions: indexed load, the
638 FP madd and msub instructions, and the FP recip and recip sqrt
639 instructions. */
640 #define ISA_HAS_FP4 ((ISA_MIPS4 \
641 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
642 || ISA_MIPS64) \
643 && !TARGET_MIPS16)
644
645 /* ISA has conditional trap instructions. */
646 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
647 && !TARGET_MIPS16)
648
649 /* ISA has integer multiply-accumulate instructions, madd and msub. */
650 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
651 || ISA_MIPS32R2 \
652 || ISA_MIPS64) \
653 && !TARGET_MIPS16)
654
655 /* Integer multiply-accumulate instructions should be generated. */
656 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
657
658 /* ISA has floating-point nmadd and nmsub instructions. */
659 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
660 || ISA_MIPS64) \
661 && (!TARGET_MIPS5400 || TARGET_MAD) \
662 && !TARGET_MIPS16)
663
664 /* ISA has count leading zeroes/ones instruction (not implemented). */
665 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
666 || ISA_MIPS32R2 \
667 || ISA_MIPS64) \
668 && !TARGET_MIPS16)
669
670 /* ISA has three operand multiply instructions that put
671 the high part in an accumulator: mulhi or mulhiu. */
672 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
673 || TARGET_MIPS5500 \
674 || TARGET_SR71K) \
675 && !TARGET_MIPS16)
676
677 /* ISA has three operand multiply instructions that
678 negates the result and puts the result in an accumulator. */
679 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
680 || TARGET_MIPS5500 \
681 || TARGET_SR71K) \
682 && !TARGET_MIPS16)
683
684 /* ISA has three operand multiply instructions that subtracts the
685 result from a 4th operand and puts the result in an accumulator. */
686 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
687 || TARGET_MIPS5500 \
688 || TARGET_SR71K) \
689 && !TARGET_MIPS16)
690
691 /* ISA has three operand multiply instructions that the result
692 from a 4th operand and puts the result in an accumulator. */
693 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
694 || TARGET_MIPS4130 \
695 || TARGET_MIPS5400 \
696 || TARGET_MIPS5500 \
697 || TARGET_SR71K) \
698 && !TARGET_MIPS16)
699
700 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
701 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
702 || TARGET_MIPS4130) \
703 && !TARGET_MIPS16)
704
705 /* ISA has the "ror" (rotate right) instructions. */
706 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
707 || TARGET_MIPS5400 \
708 || TARGET_MIPS5500 \
709 || TARGET_SR71K) \
710 && !TARGET_MIPS16)
711
712 /* ISA has data prefetch instructions. This controls use of 'pref'. */
713 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
714 || ISA_MIPS32 \
715 || ISA_MIPS32R2 \
716 || ISA_MIPS64) \
717 && !TARGET_MIPS16)
718
719 /* ISA has data indexed prefetch instructions. This controls use of
720 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
721 (prefx is a cop1x instruction, so can only be used if FP is
722 enabled.) */
723 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
724 || ISA_MIPS32R2 \
725 || ISA_MIPS64) \
726 && !TARGET_MIPS16)
727
728 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
729 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
730 also requires TARGET_DOUBLE_FLOAT. */
731 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
732
733 /* ISA includes the MIPS32r2 seb and seh instructions. */
734 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
735 && !TARGET_MIPS16)
736
737 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
738 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
739 && !TARGET_MIPS16)
740
741 /* ISA has instructions for accessing top part of 64-bit fp regs. */
742 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
743
744 /* True if the result of a load is not available to the next instruction.
745 A nop will then be needed between instructions like "lw $4,..."
746 and "addiu $4,$4,1". */
747 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
748 && !TARGET_MIPS3900 \
749 && !TARGET_MIPS16)
750
751 /* Likewise mtc1 and mfc1. */
752 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
753
754 /* Likewise floating-point comparisons. */
755 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
756
757 /* True if mflo and mfhi can be immediately followed by instructions
758 which write to the HI and LO registers.
759
760 According to MIPS specifications, MIPS ISAs I, II, and III need
761 (at least) two instructions between the reads of HI/LO and
762 instructions which write them, and later ISAs do not. Contradicting
763 the MIPS specifications, some MIPS IV processor user manuals (e.g.
764 the UM for the NEC Vr5000) document needing the instructions between
765 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
766 MIPS64 and later ISAs to have the interlocks, plus any specific
767 earlier-ISA CPUs for which CPU documentation declares that the
768 instructions are really interlocked. */
769 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
770 || ISA_MIPS32R2 \
771 || ISA_MIPS64 \
772 || TARGET_MIPS5500)
773 \f
774 /* Add -G xx support. */
775
776 #undef SWITCH_TAKES_ARG
777 #define SWITCH_TAKES_ARG(CHAR) \
778 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
779
780 #define OVERRIDE_OPTIONS override_options ()
781
782 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
783
784 /* Show we can debug even without a frame pointer. */
785 #define CAN_DEBUG_WITHOUT_FP
786 \f
787 /* Tell collect what flags to pass to nm. */
788 #ifndef NM_FLAGS
789 #define NM_FLAGS "-Bn"
790 #endif
791
792 \f
793 #ifndef MIPS_ABI_DEFAULT
794 #define MIPS_ABI_DEFAULT ABI_32
795 #endif
796
797 /* Use the most portable ABI flag for the ASM specs. */
798
799 #if MIPS_ABI_DEFAULT == ABI_32
800 #define MULTILIB_ABI_DEFAULT "mabi=32"
801 #endif
802
803 #if MIPS_ABI_DEFAULT == ABI_O64
804 #define MULTILIB_ABI_DEFAULT "mabi=o64"
805 #endif
806
807 #if MIPS_ABI_DEFAULT == ABI_N32
808 #define MULTILIB_ABI_DEFAULT "mabi=n32"
809 #endif
810
811 #if MIPS_ABI_DEFAULT == ABI_64
812 #define MULTILIB_ABI_DEFAULT "mabi=64"
813 #endif
814
815 #if MIPS_ABI_DEFAULT == ABI_EABI
816 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
817 #endif
818
819 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
820 to the assembler. It may be overridden by subtargets. */
821 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
822 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
823 %{noasmopt:-O0} \
824 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
825 #endif
826
827 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
828 the assembler. It may be overridden by subtargets.
829
830 Beginning with gas 2.13, -mdebug must be passed to correctly handle
831 COFF debugging info. */
832
833 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
834 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
835 %{g} %{g0} %{g1} %{g2} %{g3} \
836 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
837 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
838 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
839 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
840 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
841 #endif
842
843 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
844 overridden by subtargets. */
845
846 #ifndef SUBTARGET_ASM_SPEC
847 #define SUBTARGET_ASM_SPEC ""
848 #endif
849
850 #undef ASM_SPEC
851 #define ASM_SPEC "\
852 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
853 %{mips32} %{mips32r2} %{mips64} \
854 %{mips16} %{mno-mips16:-no-mips16} \
855 %{mips3d} %{mno-mips3d:-no-mips3d} \
856 %{mdmx} %{mno-mdmx:-no-mdmx} \
857 %{mdsp} %{mno-dsp} \
858 %{mdspr2} %{mno-dspr2} \
859 %{mmt} %{mno-mt} \
860 %{mfix-vr4120} %{mfix-vr4130} \
861 %(subtarget_asm_optimizing_spec) \
862 %(subtarget_asm_debugging_spec) \
863 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
864 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
865 %{mfp32} %{mfp64} \
866 %{mshared} %{mno-shared} \
867 %{msym32} %{mno-sym32} \
868 %{mtune=*} %{v} \
869 %(subtarget_asm_spec)"
870
871 /* Extra switches sometimes passed to the linker. */
872 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
873 will interpret it as a -b option. */
874
875 #ifndef LINK_SPEC
876 #define LINK_SPEC "\
877 %(endian_spec) \
878 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
879 %{bestGnum} %{shared} %{non_shared}"
880 #endif /* LINK_SPEC defined */
881
882
883 /* Specs for the compiler proper */
884
885 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
886 overridden by subtargets. */
887 #ifndef SUBTARGET_CC1_SPEC
888 #define SUBTARGET_CC1_SPEC ""
889 #endif
890
891 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
892
893 #undef CC1_SPEC
894 #define CC1_SPEC "\
895 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
896 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
897 %{save-temps: } \
898 %(subtarget_cc1_spec)"
899
900 /* Preprocessor specs. */
901
902 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
903 overridden by subtargets. */
904 #ifndef SUBTARGET_CPP_SPEC
905 #define SUBTARGET_CPP_SPEC ""
906 #endif
907
908 #define CPP_SPEC "%(subtarget_cpp_spec)"
909
910 /* This macro defines names of additional specifications to put in the specs
911 that can be used in various specifications like CC1_SPEC. Its definition
912 is an initializer with a subgrouping for each command option.
913
914 Each subgrouping contains a string constant, that defines the
915 specification name, and a string constant that used by the GCC driver
916 program.
917
918 Do not define this macro if it does not need to do anything. */
919
920 #define EXTRA_SPECS \
921 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
922 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
923 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
924 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
925 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
926 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
927 { "endian_spec", ENDIAN_SPEC }, \
928 SUBTARGET_EXTRA_SPECS
929
930 #ifndef SUBTARGET_EXTRA_SPECS
931 #define SUBTARGET_EXTRA_SPECS
932 #endif
933 \f
934 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
935 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
936 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
937
938 #ifndef PREFERRED_DEBUGGING_TYPE
939 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
940 #endif
941
942 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
943
944 /* By default, turn on GDB extensions. */
945 #define DEFAULT_GDB_EXTENSIONS 1
946
947 /* Local compiler-generated symbols must have a prefix that the assembler
948 understands. By default, this is $, although some targets (e.g.,
949 NetBSD-ELF) need to override this. */
950
951 #ifndef LOCAL_LABEL_PREFIX
952 #define LOCAL_LABEL_PREFIX "$"
953 #endif
954
955 /* By default on the mips, external symbols do not have an underscore
956 prepended, but some targets (e.g., NetBSD) require this. */
957
958 #ifndef USER_LABEL_PREFIX
959 #define USER_LABEL_PREFIX ""
960 #endif
961
962 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
963 since the length can run past this up to a continuation point. */
964 #undef DBX_CONTIN_LENGTH
965 #define DBX_CONTIN_LENGTH 1500
966
967 /* How to renumber registers for dbx and gdb. */
968 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
969
970 /* The mapping from gcc register number to DWARF 2 CFA column number. */
971 #define DWARF_FRAME_REGNUM(REG) (REG)
972
973 /* The DWARF 2 CFA column which tracks the return address. */
974 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
975
976 /* The DWARF 2 CFA column which tracks the return address from a
977 signal handler context. */
978 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
979
980 /* Before the prologue, RA lives in r31. */
981 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
982
983 /* Describe how we implement __builtin_eh_return. */
984 #define EH_RETURN_DATA_REGNO(N) \
985 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
986
987 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
988
989 /* Offsets recorded in opcodes are a multiple of this alignment factor.
990 The default for this in 64-bit mode is 8, which causes problems with
991 SFmode register saves. */
992 #define DWARF_CIE_DATA_ALIGNMENT -4
993
994 /* Correct the offset of automatic variables and arguments. Note that
995 the MIPS debug format wants all automatic variables and arguments
996 to be in terms of the virtual frame pointer (stack pointer before
997 any adjustment in the function), while the MIPS 3.0 linker wants
998 the frame pointer to be the stack pointer after the initial
999 adjustment. */
1000
1001 #define DEBUGGER_AUTO_OFFSET(X) \
1002 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1003 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1004 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1005 \f
1006 /* Target machine storage layout */
1007
1008 #define BITS_BIG_ENDIAN 0
1009 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1010 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1011
1012 /* Define this to set the endianness to use in libgcc2.c, which can
1013 not depend on target_flags. */
1014 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1015 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1016 #else
1017 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1018 #endif
1019
1020 #define MAX_BITS_PER_WORD 64
1021
1022 /* Width of a word, in units (bytes). */
1023 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1024 #ifndef IN_LIBGCC2
1025 #define MIN_UNITS_PER_WORD 4
1026 #endif
1027
1028 /* For MIPS, width of a floating point register. */
1029 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1030
1031 /* The number of consecutive floating-point registers needed to store the
1032 largest format supported by the FPU. */
1033 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1034
1035 /* The number of consecutive floating-point registers needed to store the
1036 smallest format supported by the FPU. */
1037 #define MIN_FPRS_PER_FMT \
1038 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1039
1040 /* The largest size of value that can be held in floating-point
1041 registers and moved with a single instruction. */
1042 #define UNITS_PER_HWFPVALUE \
1043 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1044
1045 /* The largest size of value that can be held in floating-point
1046 registers. */
1047 #define UNITS_PER_FPVALUE \
1048 (TARGET_SOFT_FLOAT_ABI ? 0 \
1049 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1050 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1051
1052 /* The number of bytes in a double. */
1053 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1054
1055 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1056
1057 /* Set the sizes of the core types. */
1058 #define SHORT_TYPE_SIZE 16
1059 #define INT_TYPE_SIZE 32
1060 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1061 #define LONG_LONG_TYPE_SIZE 64
1062
1063 #define FLOAT_TYPE_SIZE 32
1064 #define DOUBLE_TYPE_SIZE 64
1065 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1066
1067 /* long double is not a fixed mode, but the idea is that, if we
1068 support long double, we also want a 128-bit integer type. */
1069 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1070
1071 #ifdef IN_LIBGCC2
1072 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1073 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1074 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1075 # else
1076 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1077 # endif
1078 #endif
1079
1080 /* Width in bits of a pointer. */
1081 #ifndef POINTER_SIZE
1082 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1083 #endif
1084
1085 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1086 #define PARM_BOUNDARY BITS_PER_WORD
1087
1088 /* Allocation boundary (in *bits*) for the code of a function. */
1089 #define FUNCTION_BOUNDARY 32
1090
1091 /* Alignment of field after `int : 0' in a structure. */
1092 #define EMPTY_FIELD_BOUNDARY 32
1093
1094 /* Every structure's size must be a multiple of this. */
1095 /* 8 is observed right on a DECstation and on riscos 4.02. */
1096 #define STRUCTURE_SIZE_BOUNDARY 8
1097
1098 /* There is no point aligning anything to a rounder boundary than this. */
1099 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1100
1101 /* All accesses must be aligned. */
1102 #define STRICT_ALIGNMENT 1
1103
1104 /* Define this if you wish to imitate the way many other C compilers
1105 handle alignment of bitfields and the structures that contain
1106 them.
1107
1108 The behavior is that the type written for a bit-field (`int',
1109 `short', or other integer type) imposes an alignment for the
1110 entire structure, as if the structure really did contain an
1111 ordinary field of that type. In addition, the bit-field is placed
1112 within the structure so that it would fit within such a field,
1113 not crossing a boundary for it.
1114
1115 Thus, on most machines, a bit-field whose type is written as `int'
1116 would not cross a four-byte boundary, and would force four-byte
1117 alignment for the whole structure. (The alignment used may not
1118 be four bytes; it is controlled by the other alignment
1119 parameters.)
1120
1121 If the macro is defined, its definition should be a C expression;
1122 a nonzero value for the expression enables this behavior. */
1123
1124 #define PCC_BITFIELD_TYPE_MATTERS 1
1125
1126 /* If defined, a C expression to compute the alignment given to a
1127 constant that is being placed in memory. CONSTANT is the constant
1128 and ALIGN is the alignment that the object would ordinarily have.
1129 The value of this macro is used instead of that alignment to align
1130 the object.
1131
1132 If this macro is not defined, then ALIGN is used.
1133
1134 The typical use of this macro is to increase alignment for string
1135 constants to be word aligned so that `strcpy' calls that copy
1136 constants can be done inline. */
1137
1138 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1139 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1140 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1141
1142 /* If defined, a C expression to compute the alignment for a static
1143 variable. TYPE is the data type, and ALIGN is the alignment that
1144 the object would ordinarily have. The value of this macro is used
1145 instead of that alignment to align the object.
1146
1147 If this macro is not defined, then ALIGN is used.
1148
1149 One use of this macro is to increase alignment of medium-size
1150 data to make it all fit in fewer cache lines. Another is to
1151 cause character arrays to be word-aligned so that `strcpy' calls
1152 that copy constants to character arrays can be done inline. */
1153
1154 #undef DATA_ALIGNMENT
1155 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1156 ((((ALIGN) < BITS_PER_WORD) \
1157 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1158 || TREE_CODE (TYPE) == UNION_TYPE \
1159 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1160
1161
1162 #define PAD_VARARGS_DOWN \
1163 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1164
1165 /* Define if operations between registers always perform the operation
1166 on the full register even if a narrower mode is specified. */
1167 #define WORD_REGISTER_OPERATIONS
1168
1169 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1170 moves. All other references are zero extended. */
1171 #define LOAD_EXTEND_OP(MODE) \
1172 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1173 ? SIGN_EXTEND : ZERO_EXTEND)
1174
1175 /* Define this macro if it is advisable to hold scalars in registers
1176 in a wider mode than that declared by the program. In such cases,
1177 the value is constrained to be within the bounds of the declared
1178 type, but kept valid in the wider mode. The signedness of the
1179 extension may differ from that of the type. */
1180
1181 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1182 if (GET_MODE_CLASS (MODE) == MODE_INT \
1183 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1184 { \
1185 if ((MODE) == SImode) \
1186 (UNSIGNEDP) = 0; \
1187 (MODE) = Pmode; \
1188 }
1189
1190 /* Define if loading short immediate values into registers sign extends. */
1191 #define SHORT_IMMEDIATES_SIGN_EXTEND
1192
1193 /* The [d]clz instructions have the natural values at 0. */
1194
1195 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1196 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1197 \f
1198 /* Standard register usage. */
1199
1200 /* Number of hardware registers. We have:
1201
1202 - 32 integer registers
1203 - 32 floating point registers
1204 - 8 condition code registers
1205 - 2 accumulator registers (hi and lo)
1206 - 32 registers each for coprocessors 0, 2 and 3
1207 - 3 fake registers:
1208 - ARG_POINTER_REGNUM
1209 - FRAME_POINTER_REGNUM
1210 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1211 - 3 dummy entries that were used at various times in the past.
1212 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1213 - 6 DSP control registers */
1214
1215 #define FIRST_PSEUDO_REGISTER 188
1216
1217 /* By default, fix the kernel registers ($26 and $27), the global
1218 pointer ($28) and the stack pointer ($29). This can change
1219 depending on the command-line options.
1220
1221 Regarding coprocessor registers: without evidence to the contrary,
1222 it's best to assume that each coprocessor register has a unique
1223 use. This can be overridden, in, e.g., override_options() or
1224 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1225 for a particular target. */
1226
1227 #define FIXED_REGISTERS \
1228 { \
1229 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1233 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1234 /* COP0 registers */ \
1235 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1236 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1237 /* COP2 registers */ \
1238 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1239 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1240 /* COP3 registers */ \
1241 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1242 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1243 /* 6 DSP accumulator registers & 6 control registers */ \
1244 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1245 }
1246
1247
1248 /* Set up this array for o32 by default.
1249
1250 Note that we don't mark $31 as a call-clobbered register. The idea is
1251 that it's really the call instructions themselves which clobber $31.
1252 We don't care what the called function does with it afterwards.
1253
1254 This approach makes it easier to implement sibcalls. Unlike normal
1255 calls, sibcalls don't clobber $31, so the register reaches the
1256 called function in tact. EPILOGUE_USES says that $31 is useful
1257 to the called function. */
1258
1259 #define CALL_USED_REGISTERS \
1260 { \
1261 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1262 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1263 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1264 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1265 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1266 /* COP0 registers */ \
1267 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1268 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1269 /* COP2 registers */ \
1270 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1271 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1272 /* COP3 registers */ \
1273 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1274 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1275 /* 6 DSP accumulator registers & 6 control registers */ \
1276 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1277 }
1278
1279
1280 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1281
1282 #define CALL_REALLY_USED_REGISTERS \
1283 { /* General registers. */ \
1284 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1285 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1286 /* Floating-point registers. */ \
1287 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1288 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1289 /* Others. */ \
1290 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1291 /* COP0 registers */ \
1292 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1293 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1294 /* COP2 registers */ \
1295 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1296 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1297 /* COP3 registers */ \
1298 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1299 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1300 /* 6 DSP accumulator registers & 6 control registers */ \
1301 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1302 }
1303
1304 /* Internal macros to classify a register number as to whether it's a
1305 general purpose register, a floating point register, a
1306 multiply/divide register, or a status register. */
1307
1308 #define GP_REG_FIRST 0
1309 #define GP_REG_LAST 31
1310 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1311 #define GP_DBX_FIRST 0
1312
1313 #define FP_REG_FIRST 32
1314 #define FP_REG_LAST 63
1315 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1316 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1317
1318 #define MD_REG_FIRST 64
1319 #define MD_REG_LAST 65
1320 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1321 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1322
1323 #define ST_REG_FIRST 67
1324 #define ST_REG_LAST 74
1325 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1326
1327
1328 /* FIXME: renumber. */
1329 #define COP0_REG_FIRST 80
1330 #define COP0_REG_LAST 111
1331 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1332
1333 #define COP2_REG_FIRST 112
1334 #define COP2_REG_LAST 143
1335 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1336
1337 #define COP3_REG_FIRST 144
1338 #define COP3_REG_LAST 175
1339 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1340 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1341 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1342
1343 #define DSP_ACC_REG_FIRST 176
1344 #define DSP_ACC_REG_LAST 181
1345 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1346
1347 #define AT_REGNUM (GP_REG_FIRST + 1)
1348 #define HI_REGNUM (MD_REG_FIRST + 0)
1349 #define LO_REGNUM (MD_REG_FIRST + 1)
1350 #define AC1HI_REGNUM (DSP_ACC_REG_FIRST + 0)
1351 #define AC1LO_REGNUM (DSP_ACC_REG_FIRST + 1)
1352 #define AC2HI_REGNUM (DSP_ACC_REG_FIRST + 2)
1353 #define AC2LO_REGNUM (DSP_ACC_REG_FIRST + 3)
1354 #define AC3HI_REGNUM (DSP_ACC_REG_FIRST + 4)
1355 #define AC3LO_REGNUM (DSP_ACC_REG_FIRST + 5)
1356
1357 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1358 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1359 should be used instead. */
1360 #define FPSW_REGNUM ST_REG_FIRST
1361
1362 #define GP_REG_P(REGNO) \
1363 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1364 #define M16_REG_P(REGNO) \
1365 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1366 #define FP_REG_P(REGNO) \
1367 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1368 #define MD_REG_P(REGNO) \
1369 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1370 #define ST_REG_P(REGNO) \
1371 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1372 #define COP0_REG_P(REGNO) \
1373 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1374 #define COP2_REG_P(REGNO) \
1375 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1376 #define COP3_REG_P(REGNO) \
1377 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1378 #define ALL_COP_REG_P(REGNO) \
1379 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1380 /* Test if REGNO is one of the 6 new DSP accumulators. */
1381 #define DSP_ACC_REG_P(REGNO) \
1382 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1383 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1384 #define ACC_REG_P(REGNO) \
1385 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1386 /* Test if REGNO is HI or the first register of 3 new DSP accumulator pairs. */
1387 #define ACC_HI_REG_P(REGNO) \
1388 ((REGNO) == HI_REGNUM || (REGNO) == AC1HI_REGNUM || (REGNO) == AC2HI_REGNUM \
1389 || (REGNO) == AC3HI_REGNUM)
1390
1391 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1392
1393 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1394 to initialize the mips16 gp pseudo register. */
1395 #define CONST_GP_P(X) \
1396 (GET_CODE (X) == CONST \
1397 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1398 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1399
1400 /* Return coprocessor number from register number. */
1401
1402 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1403 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1404 : COP3_REG_P (REGNO) ? '3' : '?')
1405
1406
1407 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1408
1409 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1410 array built in override_options. Because machmodes.h is not yet
1411 included before this file is processed, the MODE bound can't be
1412 expressed here. */
1413
1414 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1415
1416 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1417 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1418
1419 /* Value is 1 if it is a good idea to tie two pseudo registers
1420 when one has mode MODE1 and one has mode MODE2.
1421 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1422 for any hard reg, then this must be 0 for correct output. */
1423 #define MODES_TIEABLE_P(MODE1, MODE2) \
1424 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1425 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1426 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1427 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1428
1429 /* Register to use for pushing function arguments. */
1430 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1431
1432 /* These two registers don't really exist: they get eliminated to either
1433 the stack or hard frame pointer. */
1434 #define ARG_POINTER_REGNUM 77
1435 #define FRAME_POINTER_REGNUM 78
1436
1437 /* $30 is not available on the mips16, so we use $17 as the frame
1438 pointer. */
1439 #define HARD_FRAME_POINTER_REGNUM \
1440 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1441
1442 /* Value should be nonzero if functions must have frame pointers.
1443 Zero means the frame pointer need not be set up (and parms
1444 may be accessed via the stack pointer) in functions that seem suitable.
1445 This is computed in `reload', in reload1.c. */
1446 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1447
1448 /* Register in which static-chain is passed to a function. */
1449 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1450
1451 /* Registers used as temporaries in prologue/epilogue code. If we're
1452 generating mips16 code, these registers must come from the core set
1453 of 8. The prologue register mustn't conflict with any incoming
1454 arguments, the static chain pointer, or the frame pointer. The
1455 epilogue temporary mustn't conflict with the return registers, the
1456 frame pointer, the EH stack adjustment, or the EH data registers. */
1457
1458 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1459 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1460
1461 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1462 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1463
1464 /* Define this macro if it is as good or better to call a constant
1465 function address than to call an address kept in a register. */
1466 #define NO_FUNCTION_CSE 1
1467
1468 /* The ABI-defined global pointer. Sometimes we use a different
1469 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1470 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1471
1472 /* We normally use $28 as the global pointer. However, when generating
1473 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1474 register instead. They can then avoid saving and restoring $28
1475 and perhaps avoid using a frame at all.
1476
1477 When a leaf function uses something other than $28, mips_expand_prologue
1478 will modify pic_offset_table_rtx in place. Take the register number
1479 from there after reload. */
1480 #define PIC_OFFSET_TABLE_REGNUM \
1481 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1482
1483 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1484 \f
1485 /* Define the classes of registers for register constraints in the
1486 machine description. Also define ranges of constants.
1487
1488 One of the classes must always be named ALL_REGS and include all hard regs.
1489 If there is more than one class, another class must be named NO_REGS
1490 and contain no registers.
1491
1492 The name GENERAL_REGS must be the name of a class (or an alias for
1493 another name such as ALL_REGS). This is the class of registers
1494 that is allowed by "g" or "r" in a register constraint.
1495 Also, registers outside this class are allocated only when
1496 instructions express preferences for them.
1497
1498 The classes must be numbered in nondecreasing order; that is,
1499 a larger-numbered class must never be contained completely
1500 in a smaller-numbered class.
1501
1502 For any two classes, it is very desirable that there be another
1503 class that represents their union. */
1504
1505 enum reg_class
1506 {
1507 NO_REGS, /* no registers in set */
1508 M16_NA_REGS, /* mips16 regs not used to pass args */
1509 M16_REGS, /* mips16 directly accessible registers */
1510 T_REG, /* mips16 T register ($24) */
1511 M16_T_REGS, /* mips16 registers plus T register */
1512 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1513 V1_REG, /* Register $v1 ($3) used for TLS access. */
1514 LEA_REGS, /* Every GPR except $25 */
1515 GR_REGS, /* integer registers */
1516 FP_REGS, /* floating point registers */
1517 HI_REG, /* hi register */
1518 LO_REG, /* lo register */
1519 MD_REGS, /* multiply/divide registers (hi/lo) */
1520 COP0_REGS, /* generic coprocessor classes */
1521 COP2_REGS,
1522 COP3_REGS,
1523 HI_AND_GR_REGS, /* union classes */
1524 LO_AND_GR_REGS,
1525 HI_AND_FP_REGS,
1526 COP0_AND_GR_REGS,
1527 COP2_AND_GR_REGS,
1528 COP3_AND_GR_REGS,
1529 ALL_COP_REGS,
1530 ALL_COP_AND_GR_REGS,
1531 ST_REGS, /* status registers (fp status) */
1532 DSP_ACC_REGS, /* DSP accumulator registers */
1533 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1534 ALL_REGS, /* all registers */
1535 LIM_REG_CLASSES /* max value + 1 */
1536 };
1537
1538 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1539
1540 #define GENERAL_REGS GR_REGS
1541
1542 /* An initializer containing the names of the register classes as C
1543 string constants. These names are used in writing some of the
1544 debugging dumps. */
1545
1546 #define REG_CLASS_NAMES \
1547 { \
1548 "NO_REGS", \
1549 "M16_NA_REGS", \
1550 "M16_REGS", \
1551 "T_REG", \
1552 "M16_T_REGS", \
1553 "PIC_FN_ADDR_REG", \
1554 "V1_REG", \
1555 "LEA_REGS", \
1556 "GR_REGS", \
1557 "FP_REGS", \
1558 "HI_REG", \
1559 "LO_REG", \
1560 "MD_REGS", \
1561 /* coprocessor registers */ \
1562 "COP0_REGS", \
1563 "COP2_REGS", \
1564 "COP3_REGS", \
1565 "HI_AND_GR_REGS", \
1566 "LO_AND_GR_REGS", \
1567 "HI_AND_FP_REGS", \
1568 "COP0_AND_GR_REGS", \
1569 "COP2_AND_GR_REGS", \
1570 "COP3_AND_GR_REGS", \
1571 "ALL_COP_REGS", \
1572 "ALL_COP_AND_GR_REGS", \
1573 "ST_REGS", \
1574 "DSP_ACC_REGS", \
1575 "ACC_REGS", \
1576 "ALL_REGS" \
1577 }
1578
1579 /* An initializer containing the contents of the register classes,
1580 as integers which are bit masks. The Nth integer specifies the
1581 contents of class N. The way the integer MASK is interpreted is
1582 that register R is in the class if `MASK & (1 << R)' is 1.
1583
1584 When the machine has more than 32 registers, an integer does not
1585 suffice. Then the integers are replaced by sub-initializers,
1586 braced groupings containing several integers. Each
1587 sub-initializer must be suitable as an initializer for the type
1588 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1589
1590 #define REG_CLASS_CONTENTS \
1591 { \
1592 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1593 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1594 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1595 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1596 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1597 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1598 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1599 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1600 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1601 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1602 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1603 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1604 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1605 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1606 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1607 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1608 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1609 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1610 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1611 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1612 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1613 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1614 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1615 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1616 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1617 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1618 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1619 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1620 }
1621
1622
1623 /* A C expression whose value is a register class containing hard
1624 register REGNO. In general there is more that one such class;
1625 choose a class which is "minimal", meaning that no smaller class
1626 also contains the register. */
1627
1628 extern const enum reg_class mips_regno_to_class[];
1629
1630 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1631
1632 /* A macro whose definition is the name of the class to which a
1633 valid base register must belong. A base register is one used in
1634 an address which is the register value plus a displacement. */
1635
1636 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1637
1638 /* A macro whose definition is the name of the class to which a
1639 valid index register must belong. An index register is one used
1640 in an address where its value is either multiplied by a scale
1641 factor or added to another register (as well as added to a
1642 displacement). */
1643
1644 #define INDEX_REG_CLASS NO_REGS
1645
1646 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1647 registers explicitly used in the rtl to be used as spill registers
1648 but prevents the compiler from extending the lifetime of these
1649 registers. */
1650
1651 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1652
1653 /* This macro is used later on in the file. */
1654 #define GR_REG_CLASS_P(CLASS) \
1655 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1656 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1657 || (CLASS) == V1_REG \
1658 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1659
1660 /* This macro is also used later on in the file. */
1661 #define COP_REG_CLASS_P(CLASS) \
1662 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1663
1664 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1665 is the default value (allocate the registers in numeric order). We
1666 define it just so that we can override it for the mips16 target in
1667 ORDER_REGS_FOR_LOCAL_ALLOC. */
1668
1669 #define REG_ALLOC_ORDER \
1670 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1671 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1672 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1673 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1674 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1675 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1676 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1677 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1678 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1679 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1680 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1681 176,177,178,179,180,181,182,183,184,185,186,187 \
1682 }
1683
1684 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1685 to be rearranged based on a particular function. On the mips16, we
1686 want to allocate $24 (T_REG) before other registers for
1687 instructions for which it is possible. */
1688
1689 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1690
1691 /* True if VALUE is an unsigned 6-bit number. */
1692
1693 #define UIMM6_OPERAND(VALUE) \
1694 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1695
1696 /* True if VALUE is a signed 10-bit number. */
1697
1698 #define IMM10_OPERAND(VALUE) \
1699 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1700
1701 /* True if VALUE is a signed 16-bit number. */
1702
1703 #define SMALL_OPERAND(VALUE) \
1704 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1705
1706 /* True if VALUE is an unsigned 16-bit number. */
1707
1708 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1709 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1710
1711 /* True if VALUE can be loaded into a register using LUI. */
1712
1713 #define LUI_OPERAND(VALUE) \
1714 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1715 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1716
1717 /* Return a value X with the low 16 bits clear, and such that
1718 VALUE - X is a signed 16-bit value. */
1719
1720 #define CONST_HIGH_PART(VALUE) \
1721 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1722
1723 #define CONST_LOW_PART(VALUE) \
1724 ((VALUE) - CONST_HIGH_PART (VALUE))
1725
1726 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1727 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1728 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1729
1730 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1731 mips_preferred_reload_class (X, CLASS)
1732
1733 /* Certain machines have the property that some registers cannot be
1734 copied to some other registers without using memory. Define this
1735 macro on those machines to be a C expression that is nonzero if
1736 objects of mode MODE in registers of CLASS1 can only be copied to
1737 registers of class CLASS2 by storing a register of CLASS1 into
1738 memory and loading that memory location into a register of CLASS2.
1739
1740 Do not define this macro if its value would always be zero. */
1741 #if 0
1742 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1743 ((!TARGET_DEBUG_H_MODE \
1744 && GET_MODE_CLASS (MODE) == MODE_INT \
1745 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
1746 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
1747 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
1748 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
1749 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
1750 #endif
1751 /* The HI and LO registers can only be reloaded via the general
1752 registers. Condition code registers can only be loaded to the
1753 general registers, and from the floating point registers. */
1754
1755 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1756 mips_secondary_reload_class (CLASS, MODE, X, 1)
1757 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1758 mips_secondary_reload_class (CLASS, MODE, X, 0)
1759
1760 /* Return the maximum number of consecutive registers
1761 needed to represent mode MODE in a register of class CLASS. */
1762
1763 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1764
1765 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1766 mips_cannot_change_mode_class (FROM, TO, CLASS)
1767 \f
1768 /* Stack layout; function entry, exit and calling. */
1769
1770 #define STACK_GROWS_DOWNWARD
1771
1772 /* The offset of the first local variable from the beginning of the frame.
1773 See compute_frame_size for details about the frame layout.
1774
1775 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1776 we assume that we will need 16 bytes of argument space. This is because
1777 the value profiling code may emit calls to cmpdi2 in leaf functions.
1778 Without this hack, the local variables will start at sp+8 and the gp save
1779 area will be at sp+16, and thus they will overlap. compute_frame_size is
1780 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1781 will end up as 24 instead of 8. This won't be needed if profiling code is
1782 inserted before virtual register instantiation. */
1783
1784 #define STARTING_FRAME_OFFSET \
1785 ((flag_profile_values && ! TARGET_64BIT \
1786 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1787 : current_function_outgoing_args_size) \
1788 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1789
1790 #define RETURN_ADDR_RTX mips_return_addr
1791
1792 /* Since the mips16 ISA mode is encoded in the least-significant bit
1793 of the address, mask it off return addresses for purposes of
1794 finding exception handling regions. */
1795
1796 #define MASK_RETURN_ADDR GEN_INT (-2)
1797
1798
1799 /* Similarly, don't use the least-significant bit to tell pointers to
1800 code from vtable index. */
1801
1802 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1803
1804 /* The eliminations to $17 are only used for mips16 code. See the
1805 definition of HARD_FRAME_POINTER_REGNUM. */
1806
1807 #define ELIMINABLE_REGS \
1808 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1809 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1810 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1811 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1812 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1813 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1814
1815 /* We can always eliminate to the hard frame pointer. We can eliminate
1816 to the stack pointer unless a frame pointer is needed.
1817
1818 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1819 reload may be unable to compute the address of a local variable,
1820 since there is no way to add a large constant to the stack pointer
1821 without using a temporary register. */
1822 #define CAN_ELIMINATE(FROM, TO) \
1823 ((TO) == HARD_FRAME_POINTER_REGNUM \
1824 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1825 && (!TARGET_MIPS16 \
1826 || compute_frame_size (get_frame_size ()) < 32768)))
1827
1828 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1829 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1830
1831 /* Allocate stack space for arguments at the beginning of each function. */
1832 #define ACCUMULATE_OUTGOING_ARGS 1
1833
1834 /* The argument pointer always points to the first argument. */
1835 #define FIRST_PARM_OFFSET(FNDECL) 0
1836
1837 /* o32 and o64 reserve stack space for all argument registers. */
1838 #define REG_PARM_STACK_SPACE(FNDECL) \
1839 (TARGET_OLDABI \
1840 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1841 : 0)
1842
1843 /* Define this if it is the responsibility of the caller to
1844 allocate the area reserved for arguments passed in registers.
1845 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1846 of this macro is to determine whether the space is included in
1847 `current_function_outgoing_args_size'. */
1848 #define OUTGOING_REG_PARM_STACK_SPACE 1
1849
1850 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1851 \f
1852 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1853
1854 /* Symbolic macros for the registers used to return integer and floating
1855 point values. */
1856
1857 #define GP_RETURN (GP_REG_FIRST + 2)
1858 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1859
1860 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1861
1862 /* Symbolic macros for the first/last argument registers. */
1863
1864 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1865 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1866 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1867 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1868
1869 #define LIBCALL_VALUE(MODE) \
1870 mips_function_value (NULL_TREE, NULL, (MODE))
1871
1872 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1873 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1874
1875 /* 1 if N is a possible register number for a function value.
1876 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1877 Currently, R2 and F0 are only implemented here (C has no complex type) */
1878
1879 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1880 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1881 && (N) == FP_RETURN + 2))
1882
1883 /* 1 if N is a possible register number for function argument passing.
1884 We have no FP argument registers when soft-float. When FP registers
1885 are 32 bits, we can't directly reference the odd numbered ones. */
1886
1887 #define FUNCTION_ARG_REGNO_P(N) \
1888 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1889 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1890 && !fixed_regs[N])
1891 \f
1892 /* This structure has to cope with two different argument allocation
1893 schemes. Most MIPS ABIs view the arguments as a structure, of which
1894 the first N words go in registers and the rest go on the stack. If I
1895 < N, the Ith word might go in Ith integer argument register or in a
1896 floating-point register. For these ABIs, we only need to remember
1897 the offset of the current argument into the structure.
1898
1899 The EABI instead allocates the integer and floating-point arguments
1900 separately. The first N words of FP arguments go in FP registers,
1901 the rest go on the stack. Likewise, the first N words of the other
1902 arguments go in integer registers, and the rest go on the stack. We
1903 need to maintain three counts: the number of integer registers used,
1904 the number of floating-point registers used, and the number of words
1905 passed on the stack.
1906
1907 We could keep separate information for the two ABIs (a word count for
1908 the standard ABIs, and three separate counts for the EABI). But it
1909 seems simpler to view the standard ABIs as forms of EABI that do not
1910 allocate floating-point registers.
1911
1912 So for the standard ABIs, the first N words are allocated to integer
1913 registers, and function_arg decides on an argument-by-argument basis
1914 whether that argument should really go in an integer register, or in
1915 a floating-point one. */
1916
1917 typedef struct mips_args {
1918 /* Always true for varargs functions. Otherwise true if at least
1919 one argument has been passed in an integer register. */
1920 int gp_reg_found;
1921
1922 /* The number of arguments seen so far. */
1923 unsigned int arg_number;
1924
1925 /* The number of integer registers used so far. For all ABIs except
1926 EABI, this is the number of words that have been added to the
1927 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1928 unsigned int num_gprs;
1929
1930 /* For EABI, the number of floating-point registers used so far. */
1931 unsigned int num_fprs;
1932
1933 /* The number of words passed on the stack. */
1934 unsigned int stack_words;
1935
1936 /* On the mips16, we need to keep track of which floating point
1937 arguments were passed in general registers, but would have been
1938 passed in the FP regs if this were a 32-bit function, so that we
1939 can move them to the FP regs if we wind up calling a 32-bit
1940 function. We record this information in fp_code, encoded in base
1941 four. A zero digit means no floating point argument, a one digit
1942 means an SFmode argument, and a two digit means a DFmode argument,
1943 and a three digit is not used. The low order digit is the first
1944 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1945 an SFmode argument. ??? A more sophisticated approach will be
1946 needed if MIPS_ABI != ABI_32. */
1947 int fp_code;
1948
1949 /* True if the function has a prototype. */
1950 int prototype;
1951 } CUMULATIVE_ARGS;
1952
1953 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1954 for a call to a function whose data type is FNTYPE.
1955 For a library call, FNTYPE is 0. */
1956
1957 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1958 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1959
1960 /* Update the data in CUM to advance over an argument
1961 of mode MODE and data type TYPE.
1962 (TYPE is null for libcalls where that information may not be available.) */
1963
1964 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1965 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1966
1967 /* Determine where to put an argument to a function.
1968 Value is zero to push the argument on the stack,
1969 or a hard register in which to store the argument.
1970
1971 MODE is the argument's machine mode.
1972 TYPE is the data type of the argument (as a tree).
1973 This is null for libcalls where that information may
1974 not be available.
1975 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1976 the preceding args and about the function being called.
1977 NAMED is nonzero if this argument is a named parameter
1978 (otherwise it is an extra parameter matching an ellipsis). */
1979
1980 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1981 function_arg( &CUM, MODE, TYPE, NAMED)
1982
1983 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
1984
1985 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1986 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
1987
1988 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1989 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
1990
1991 /* True if using EABI and varargs can be passed in floating-point
1992 registers. Under these conditions, we need a more complex form
1993 of va_list, which tracks GPR, FPR and stack arguments separately. */
1994 #define EABI_FLOAT_VARARGS_P \
1995 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
1996
1997 \f
1998 /* Say that the epilogue uses the return address register. Note that
1999 in the case of sibcalls, the values "used by the epilogue" are
2000 considered live at the start of the called function. */
2001 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2002
2003 /* Treat LOC as a byte offset from the stack pointer and round it up
2004 to the next fully-aligned offset. */
2005 #define MIPS_STACK_ALIGN(LOC) \
2006 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2007
2008 \f
2009 /* Implement `va_start' for varargs and stdarg. */
2010 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2011 mips_va_start (valist, nextarg)
2012 \f
2013 /* Output assembler code to FILE to increment profiler label # LABELNO
2014 for profiling a function entry. */
2015
2016 #define FUNCTION_PROFILER(FILE, LABELNO) \
2017 { \
2018 if (TARGET_MIPS16) \
2019 sorry ("mips16 function profiling"); \
2020 fprintf (FILE, "\t.set\tnoat\n"); \
2021 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2022 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2023 if (!TARGET_NEWABI) \
2024 { \
2025 fprintf (FILE, \
2026 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2027 TARGET_64BIT ? "dsubu" : "subu", \
2028 reg_names[STACK_POINTER_REGNUM], \
2029 reg_names[STACK_POINTER_REGNUM], \
2030 Pmode == DImode ? 16 : 8); \
2031 } \
2032 fprintf (FILE, "\tjal\t_mcount\n"); \
2033 fprintf (FILE, "\t.set\tat\n"); \
2034 }
2035
2036 /* No mips port has ever used the profiler counter word, so don't emit it
2037 or the label for it. */
2038
2039 #define NO_PROFILE_COUNTERS 1
2040
2041 /* Define this macro if the code for function profiling should come
2042 before the function prologue. Normally, the profiling code comes
2043 after. */
2044
2045 /* #define PROFILE_BEFORE_PROLOGUE */
2046
2047 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2048 the stack pointer does not matter. The value is tested only in
2049 functions that have frame pointers.
2050 No definition is equivalent to always zero. */
2051
2052 #define EXIT_IGNORE_STACK 1
2053
2054 \f
2055 /* A C statement to output, on the stream FILE, assembler code for a
2056 block of data that contains the constant parts of a trampoline.
2057 This code should not include a label--the label is taken care of
2058 automatically. */
2059
2060 #define TRAMPOLINE_TEMPLATE(STREAM) \
2061 { \
2062 if (ptr_mode == DImode) \
2063 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2064 else \
2065 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2066 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2067 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2068 if (ptr_mode == DImode) \
2069 { \
2070 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2071 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2072 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2073 } \
2074 else \
2075 { \
2076 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2077 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2078 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2079 } \
2080 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2081 if (ptr_mode == DImode) \
2082 { \
2083 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2084 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2085 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2086 } \
2087 else \
2088 { \
2089 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2090 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2091 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2092 } \
2093 }
2094
2095 /* A C expression for the size in bytes of the trampoline, as an
2096 integer. */
2097
2098 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2099
2100 /* Alignment required for trampolines, in bits. */
2101
2102 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2103
2104 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2105 program and data caches. */
2106
2107 #ifndef CACHE_FLUSH_FUNC
2108 #define CACHE_FLUSH_FUNC "_flush_cache"
2109 #endif
2110
2111 /* A C statement to initialize the variable parts of a trampoline.
2112 ADDR is an RTX for the address of the trampoline; FNADDR is an
2113 RTX for the address of the nested function; STATIC_CHAIN is an
2114 RTX for the static chain value that should be passed to the
2115 function when it is called. */
2116
2117 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2118 { \
2119 rtx func_addr, chain_addr; \
2120 \
2121 func_addr = plus_constant (ADDR, 32); \
2122 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2123 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2124 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2125 \
2126 /* Flush both caches. We need to flush the data cache in case \
2127 the system has a write-back cache. */ \
2128 /* ??? Should check the return value for errors. */ \
2129 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2130 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2131 0, VOIDmode, 3, ADDR, Pmode, \
2132 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2133 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2134 }
2135 \f
2136 /* Addressing modes, and classification of registers for them. */
2137
2138 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2139 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2140 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2141
2142 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2143 and check its validity for a certain class.
2144 We have two alternate definitions for each of them.
2145 The usual definition accepts all pseudo regs; the other rejects them all.
2146 The symbol REG_OK_STRICT causes the latter definition to be used.
2147
2148 Most source files want to accept pseudo regs in the hope that
2149 they will get allocated to the class that the insn wants them to be in.
2150 Some source files that are used after register allocation
2151 need to be strict. */
2152
2153 #ifndef REG_OK_STRICT
2154 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2155 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2156 #else
2157 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2158 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2159 #endif
2160
2161 #define REG_OK_FOR_INDEX_P(X) 0
2162
2163 \f
2164 /* Maximum number of registers that can appear in a valid memory address. */
2165
2166 #define MAX_REGS_PER_ADDRESS 1
2167
2168 #ifdef REG_OK_STRICT
2169 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2170 { \
2171 if (mips_legitimate_address_p (MODE, X, 1)) \
2172 goto ADDR; \
2173 }
2174 #else
2175 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2176 { \
2177 if (mips_legitimate_address_p (MODE, X, 0)) \
2178 goto ADDR; \
2179 }
2180 #endif
2181
2182 /* Check for constness inline but use mips_legitimate_address_p
2183 to check whether a constant really is an address. */
2184
2185 #define CONSTANT_ADDRESS_P(X) \
2186 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2187
2188 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2189
2190 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2191 do { \
2192 if (mips_legitimize_address (&(X), MODE)) \
2193 goto WIN; \
2194 } while (0)
2195
2196
2197 /* A C statement or compound statement with a conditional `goto
2198 LABEL;' executed if memory address X (an RTX) can have different
2199 meanings depending on the machine mode of the memory reference it
2200 is used for.
2201
2202 Autoincrement and autodecrement addresses typically have
2203 mode-dependent effects because the amount of the increment or
2204 decrement is the size of the operand being addressed. Some
2205 machines have other mode-dependent addresses. Many RISC machines
2206 have no mode-dependent addresses.
2207
2208 You may assume that ADDR is a valid address for the machine. */
2209
2210 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2211
2212 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2213 'the start of the function that this code is output in'. */
2214
2215 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2216 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2217 asm_fprintf ((FILE), "%U%s", \
2218 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2219 else \
2220 asm_fprintf ((FILE), "%U%s", (NAME))
2221 \f
2222 /* Flag to mark a function decl symbol that requires a long call. */
2223 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2224 #define SYMBOL_REF_LONG_CALL_P(X) \
2225 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2226
2227 /* Specify the machine mode that this machine uses
2228 for the index in the tablejump instruction.
2229 ??? Using HImode in mips16 mode can cause overflow. */
2230 #define CASE_VECTOR_MODE \
2231 (TARGET_MIPS16 ? HImode : ptr_mode)
2232
2233 /* Define as C expression which evaluates to nonzero if the tablejump
2234 instruction expects the table to contain offsets from the address of the
2235 table.
2236 Do not define this if the table should contain absolute addresses. */
2237 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2238
2239 /* Define this as 1 if `char' should by default be signed; else as 0. */
2240 #ifndef DEFAULT_SIGNED_CHAR
2241 #define DEFAULT_SIGNED_CHAR 1
2242 #endif
2243
2244 /* Max number of bytes we can move from memory to memory
2245 in one reasonably fast instruction. */
2246 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2247 #define MAX_MOVE_MAX 8
2248
2249 /* Define this macro as a C expression which is nonzero if
2250 accessing less than a word of memory (i.e. a `char' or a
2251 `short') is no faster than accessing a word of memory, i.e., if
2252 such access require more than one instruction or if there is no
2253 difference in cost between byte and (aligned) word loads.
2254
2255 On RISC machines, it tends to generate better code to define
2256 this as 1, since it avoids making a QI or HI mode register.
2257
2258 But, generating word accesses for -mips16 is generally bad as shifts
2259 (often extended) would be needed for byte accesses. */
2260 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2261
2262 /* Define this to be nonzero if shift instructions ignore all but the low-order
2263 few bits. */
2264 #define SHIFT_COUNT_TRUNCATED 1
2265
2266 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2267 is done just by pretending it is already truncated. */
2268 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2269 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2270
2271
2272 /* Specify the machine mode that pointers have.
2273 After generation of rtl, the compiler makes no further distinction
2274 between pointers and any other objects of this machine mode. */
2275
2276 #ifndef Pmode
2277 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2278 #endif
2279
2280 /* Give call MEMs SImode since it is the "most permissive" mode
2281 for both 32-bit and 64-bit targets. */
2282
2283 #define FUNCTION_MODE SImode
2284
2285 \f
2286 /* The cost of loading values from the constant pool. It should be
2287 larger than the cost of any constant we want to synthesize in-line. */
2288
2289 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2290
2291 /* A C expression for the cost of moving data from a register in
2292 class FROM to one in class TO. The classes are expressed using
2293 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2294 the default; other values are interpreted relative to that.
2295
2296 It is not required that the cost always equal 2 when FROM is the
2297 same as TO; on some machines it is expensive to move between
2298 registers if they are not general registers.
2299
2300 If reload sees an insn consisting of a single `set' between two
2301 hard registers, and if `REGISTER_MOVE_COST' applied to their
2302 classes returns a value of 2, reload does not check to ensure
2303 that the constraints of the insn are met. Setting a cost of
2304 other than 2 will allow reload to verify that the constraints are
2305 met. You should do this if the `movM' pattern's constraints do
2306 not allow such copying. */
2307
2308 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2309 mips_register_move_cost (MODE, FROM, TO)
2310
2311 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2312 (mips_cost->memory_latency \
2313 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2314
2315 /* Define if copies to/from condition code registers should be avoided.
2316
2317 This is needed for the MIPS because reload_outcc is not complete;
2318 it needs to handle cases where the source is a general or another
2319 condition code register. */
2320 #define AVOID_CCMODE_COPIES
2321
2322 /* A C expression for the cost of a branch instruction. A value of
2323 1 is the default; other values are interpreted relative to that. */
2324
2325 #define BRANCH_COST mips_cost->branch_cost
2326 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2327
2328 /* If defined, modifies the length assigned to instruction INSN as a
2329 function of the context in which it is used. LENGTH is an lvalue
2330 that contains the initially computed length of the insn and should
2331 be updated with the correct length of the insn. */
2332 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2333 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2334
2335 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2336 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2337 its operands. */
2338 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2339 "%*" OPCODE "%?\t" OPERANDS "%/"
2340
2341 /* Return the asm template for a call. INSN is the instruction's mnemonic
2342 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2343 of the target.
2344
2345 When generating GOT code without explicit relocation operators,
2346 all calls should use assembly macros. Otherwise, all indirect
2347 calls should use "jr" or "jalr"; we will arrange to restore $gp
2348 afterwards if necessary. Finally, we can only generate direct
2349 calls for -mabicalls by temporarily switching to non-PIC mode. */
2350 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2351 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2352 ? "%*" INSN "\t%" #OPNO "%/" \
2353 : REG_P (OPERANDS[OPNO]) \
2354 ? "%*" INSN "r\t%" #OPNO "%/" \
2355 : TARGET_ABICALLS \
2356 ? (".option\tpic0\n\t" \
2357 "%*" INSN "\t%" #OPNO "%/\n\t" \
2358 ".option\tpic2") \
2359 : "%*" INSN "\t%" #OPNO "%/")
2360 \f
2361 /* Control the assembler format that we output. */
2362
2363 /* Output to assembler file text saying following lines
2364 may contain character constants, extra white space, comments, etc. */
2365
2366 #ifndef ASM_APP_ON
2367 #define ASM_APP_ON " #APP\n"
2368 #endif
2369
2370 /* Output to assembler file text saying following lines
2371 no longer contain unusual constructs. */
2372
2373 #ifndef ASM_APP_OFF
2374 #define ASM_APP_OFF " #NO_APP\n"
2375 #endif
2376
2377 #define REGISTER_NAMES \
2378 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2379 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2380 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2381 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2382 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2383 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2384 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2385 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2386 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2387 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2388 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2389 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2390 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2391 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2392 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2393 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2394 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2395 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2396 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2397 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2398 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2399 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2400 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2401 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2402
2403 /* List the "software" names for each register. Also list the numerical
2404 names for $fp and $sp. */
2405
2406 #define ADDITIONAL_REGISTER_NAMES \
2407 { \
2408 { "$29", 29 + GP_REG_FIRST }, \
2409 { "$30", 30 + GP_REG_FIRST }, \
2410 { "at", 1 + GP_REG_FIRST }, \
2411 { "v0", 2 + GP_REG_FIRST }, \
2412 { "v1", 3 + GP_REG_FIRST }, \
2413 { "a0", 4 + GP_REG_FIRST }, \
2414 { "a1", 5 + GP_REG_FIRST }, \
2415 { "a2", 6 + GP_REG_FIRST }, \
2416 { "a3", 7 + GP_REG_FIRST }, \
2417 { "t0", 8 + GP_REG_FIRST }, \
2418 { "t1", 9 + GP_REG_FIRST }, \
2419 { "t2", 10 + GP_REG_FIRST }, \
2420 { "t3", 11 + GP_REG_FIRST }, \
2421 { "t4", 12 + GP_REG_FIRST }, \
2422 { "t5", 13 + GP_REG_FIRST }, \
2423 { "t6", 14 + GP_REG_FIRST }, \
2424 { "t7", 15 + GP_REG_FIRST }, \
2425 { "s0", 16 + GP_REG_FIRST }, \
2426 { "s1", 17 + GP_REG_FIRST }, \
2427 { "s2", 18 + GP_REG_FIRST }, \
2428 { "s3", 19 + GP_REG_FIRST }, \
2429 { "s4", 20 + GP_REG_FIRST }, \
2430 { "s5", 21 + GP_REG_FIRST }, \
2431 { "s6", 22 + GP_REG_FIRST }, \
2432 { "s7", 23 + GP_REG_FIRST }, \
2433 { "t8", 24 + GP_REG_FIRST }, \
2434 { "t9", 25 + GP_REG_FIRST }, \
2435 { "k0", 26 + GP_REG_FIRST }, \
2436 { "k1", 27 + GP_REG_FIRST }, \
2437 { "gp", 28 + GP_REG_FIRST }, \
2438 { "sp", 29 + GP_REG_FIRST }, \
2439 { "fp", 30 + GP_REG_FIRST }, \
2440 { "ra", 31 + GP_REG_FIRST }, \
2441 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2442 }
2443
2444 /* This is meant to be redefined in the host dependent files. It is a
2445 set of alternative names and regnums for mips coprocessors. */
2446
2447 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2448
2449 /* A C compound statement to output to stdio stream STREAM the
2450 assembler syntax for an instruction operand X. X is an RTL
2451 expression.
2452
2453 CODE is a value that can be used to specify one of several ways
2454 of printing the operand. It is used when identical operands
2455 must be printed differently depending on the context. CODE
2456 comes from the `%' specification that was used to request
2457 printing of the operand. If the specification was just `%DIGIT'
2458 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2459 is the ASCII code for LTR.
2460
2461 If X is a register, this macro should print the register's name.
2462 The names can be found in an array `reg_names' whose type is
2463 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2464
2465 When the machine description has a specification `%PUNCT' (a `%'
2466 followed by a punctuation character), this macro is called with
2467 a null pointer for X and the punctuation character for CODE.
2468
2469 See mips.c for the MIPS specific codes. */
2470
2471 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2472
2473 /* A C expression which evaluates to true if CODE is a valid
2474 punctuation character for use in the `PRINT_OPERAND' macro. If
2475 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2476 punctuation characters (except for the standard one, `%') are
2477 used in this way. */
2478
2479 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2480
2481 /* A C compound statement to output to stdio stream STREAM the
2482 assembler syntax for an instruction operand that is a memory
2483 reference whose address is ADDR. ADDR is an RTL expression. */
2484
2485 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2486
2487
2488 /* A C statement, to be executed after all slot-filler instructions
2489 have been output. If necessary, call `dbr_sequence_length' to
2490 determine the number of slots filled in a sequence (zero if not
2491 currently outputting a sequence), to decide how many no-ops to
2492 output, or whatever.
2493
2494 Don't define this macro if it has nothing to do, but it is
2495 helpful in reading assembly output if the extent of the delay
2496 sequence is made explicit (e.g. with white space).
2497
2498 Note that output routines for instructions with delay slots must
2499 be prepared to deal with not being output as part of a sequence
2500 (i.e. when the scheduling pass is not run, or when no slot
2501 fillers could be found.) The variable `final_sequence' is null
2502 when not processing a sequence, otherwise it contains the
2503 `sequence' rtx being output. */
2504
2505 #define DBR_OUTPUT_SEQEND(STREAM) \
2506 do \
2507 { \
2508 if (set_nomacro > 0 && --set_nomacro == 0) \
2509 fputs ("\t.set\tmacro\n", STREAM); \
2510 \
2511 if (set_noreorder > 0 && --set_noreorder == 0) \
2512 fputs ("\t.set\treorder\n", STREAM); \
2513 \
2514 fputs ("\n", STREAM); \
2515 } \
2516 while (0)
2517
2518
2519 /* How to tell the debugger about changes of source files. */
2520 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2521 mips_output_filename (STREAM, NAME)
2522
2523 /* mips-tfile does not understand .stabd directives. */
2524 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2525 dbxout_begin_stabn_sline (LINE); \
2526 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2527 } while (0)
2528
2529 /* Use .loc directives for SDB line numbers. */
2530 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2531 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2532
2533 /* The MIPS implementation uses some labels for its own purpose. The
2534 following lists what labels are created, and are all formed by the
2535 pattern $L[a-z].*. The machine independent portion of GCC creates
2536 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2537
2538 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2539 $Lb[0-9]+ Begin blocks for MIPS debug support
2540 $Lc[0-9]+ Label for use in s<xx> operation.
2541 $Le[0-9]+ End blocks for MIPS debug support */
2542
2543 #undef ASM_DECLARE_OBJECT_NAME
2544 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2545 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2546
2547 /* Globalizing directive for a label. */
2548 #define GLOBAL_ASM_OP "\t.globl\t"
2549
2550 /* This says how to define a global common symbol. */
2551
2552 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2553
2554 /* This says how to define a local common symbol (i.e., not visible to
2555 linker). */
2556
2557 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2558 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2559 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2560 #endif
2561
2562 /* This says how to output an external. It would be possible not to
2563 output anything and let undefined symbol become external. However
2564 the assembler uses length information on externals to allocate in
2565 data/sdata bss/sbss, thereby saving exec time. */
2566
2567 #undef ASM_OUTPUT_EXTERNAL
2568 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2569 mips_output_external(STREAM,DECL,NAME)
2570
2571 /* This is how to declare a function name. The actual work of
2572 emitting the label is moved to function_prologue, so that we can
2573 get the line number correctly emitted before the .ent directive,
2574 and after any .file directives. Define as empty so that the function
2575 is not declared before the .ent directive elsewhere. */
2576
2577 #undef ASM_DECLARE_FUNCTION_NAME
2578 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2579
2580 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2581 #define FUNCTION_NAME_ALREADY_DECLARED 0
2582 #endif
2583
2584 /* This is how to store into the string LABEL
2585 the symbol_ref name of an internal numbered label where
2586 PREFIX is the class of label and NUM is the number within the class.
2587 This is suitable for output with `assemble_name'. */
2588
2589 #undef ASM_GENERATE_INTERNAL_LABEL
2590 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2591 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2592
2593 /* This is how to output an element of a case-vector that is absolute. */
2594
2595 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2596 fprintf (STREAM, "\t%s\t%sL%d\n", \
2597 ptr_mode == DImode ? ".dword" : ".word", \
2598 LOCAL_LABEL_PREFIX, \
2599 VALUE)
2600
2601 /* This is how to output an element of a case-vector. We can make the
2602 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2603 is supported. */
2604
2605 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2606 do { \
2607 if (TARGET_MIPS16) \
2608 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2609 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2610 else if (TARGET_GPWORD) \
2611 fprintf (STREAM, "\t%s\t%sL%d\n", \
2612 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2613 LOCAL_LABEL_PREFIX, VALUE); \
2614 else if (TARGET_RTP_PIC) \
2615 { \
2616 /* Make the entry relative to the start of the function. */ \
2617 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2618 fprintf (STREAM, "\t%s\t%sL%d-", \
2619 Pmode == DImode ? ".dword" : ".word", \
2620 LOCAL_LABEL_PREFIX, VALUE); \
2621 assemble_name (STREAM, XSTR (fnsym, 0)); \
2622 fprintf (STREAM, "\n"); \
2623 } \
2624 else \
2625 fprintf (STREAM, "\t%s\t%sL%d\n", \
2626 ptr_mode == DImode ? ".dword" : ".word", \
2627 LOCAL_LABEL_PREFIX, VALUE); \
2628 } while (0)
2629
2630 /* When generating MIPS16 code, we want the jump table to be in the text
2631 section so that we can load its address using a PC-relative addition. */
2632 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2633
2634 /* This is how to output an assembler line
2635 that says to advance the location counter
2636 to a multiple of 2**LOG bytes. */
2637
2638 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2639 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2640
2641 /* This is how to output an assembler line to advance the location
2642 counter by SIZE bytes. */
2643
2644 #undef ASM_OUTPUT_SKIP
2645 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2646 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2647
2648 /* This is how to output a string. */
2649 #undef ASM_OUTPUT_ASCII
2650 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2651 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2652
2653 /* Output #ident as a in the read-only data section. */
2654 #undef ASM_OUTPUT_IDENT
2655 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2656 { \
2657 const char *p = STRING; \
2658 int size = strlen (p) + 1; \
2659 switch_to_section (readonly_data_section); \
2660 assemble_string (p, size); \
2661 }
2662 \f
2663 /* Default to -G 8 */
2664 #ifndef MIPS_DEFAULT_GVALUE
2665 #define MIPS_DEFAULT_GVALUE 8
2666 #endif
2667
2668 /* Define the strings to put out for each section in the object file. */
2669 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2670 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2671
2672 #undef READONLY_DATA_SECTION_ASM_OP
2673 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2674 \f
2675 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2676 do \
2677 { \
2678 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2679 TARGET_64BIT ? "dsubu" : "subu", \
2680 reg_names[STACK_POINTER_REGNUM], \
2681 reg_names[STACK_POINTER_REGNUM], \
2682 TARGET_64BIT ? "sd" : "sw", \
2683 reg_names[REGNO], \
2684 reg_names[STACK_POINTER_REGNUM]); \
2685 } \
2686 while (0)
2687
2688 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2689 do \
2690 { \
2691 if (! set_noreorder) \
2692 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2693 \
2694 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2695 TARGET_64BIT ? "ld" : "lw", \
2696 reg_names[REGNO], \
2697 reg_names[STACK_POINTER_REGNUM], \
2698 TARGET_64BIT ? "daddu" : "addu", \
2699 reg_names[STACK_POINTER_REGNUM], \
2700 reg_names[STACK_POINTER_REGNUM]); \
2701 \
2702 if (! set_noreorder) \
2703 fprintf (STREAM, "\t.set\treorder\n"); \
2704 } \
2705 while (0)
2706
2707 /* How to start an assembler comment.
2708 The leading space is important (the mips native assembler requires it). */
2709 #ifndef ASM_COMMENT_START
2710 #define ASM_COMMENT_START " #"
2711 #endif
2712 \f
2713 /* Default definitions for size_t and ptrdiff_t. We must override the
2714 definitions from ../svr4.h on mips-*-linux-gnu. */
2715
2716 #undef SIZE_TYPE
2717 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2718
2719 #undef PTRDIFF_TYPE
2720 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2721 \f
2722 #ifndef __mips16
2723 /* Since the bits of the _init and _fini function is spread across
2724 many object files, each potentially with its own GP, we must assume
2725 we need to load our GP. We don't preserve $gp or $ra, since each
2726 init/fini chunk is supposed to initialize $gp, and crti/crtn
2727 already take care of preserving $ra and, when appropriate, $gp. */
2728 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2729 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2730 asm (SECTION_OP "\n\
2731 .set noreorder\n\
2732 bal 1f\n\
2733 nop\n\
2734 1: .cpload $31\n\
2735 .set reorder\n\
2736 jal " USER_LABEL_PREFIX #FUNC "\n\
2737 " TEXT_SECTION_ASM_OP);
2738 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2739 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2740 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2741 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2742 asm (SECTION_OP "\n\
2743 .set noreorder\n\
2744 bal 1f\n\
2745 nop\n\
2746 1: .set reorder\n\
2747 .cpsetup $31, $2, 1b\n\
2748 jal " USER_LABEL_PREFIX #FUNC "\n\
2749 " TEXT_SECTION_ASM_OP);
2750 #endif
2751 #endif
2752
2753 #ifndef HAVE_AS_TLS
2754 #define HAVE_AS_TLS 0
2755 #endif
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