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mips.c (override_options): Use mips_costs to derive the default branch cost.
[official-gcc.git] / gcc / config / mips / mips.h
blob2496986c881216ea2927596d98458a12c2024cbd
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING. If not, write to
24 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
25 Boston, MA 02110-1301, USA. */
26
27
28 #include "config/vxworks-dummy.h"
29
30 /* MIPS external variables defined in mips.c. */
31
32 /* Which processor to schedule for. Since there is no difference between
33 a R2000 and R3000 in terms of the scheduler, we collapse them into
34 just an R3000. The elements of the enumeration must match exactly
35 the cpu attribute in the mips.md machine description. */
36
37 enum processor_type {
38 PROCESSOR_R3000,
39 PROCESSOR_4KC,
40 PROCESSOR_4KP,
41 PROCESSOR_5KC,
42 PROCESSOR_5KF,
43 PROCESSOR_20KC,
44 PROCESSOR_24KC,
45 PROCESSOR_24KF2_1,
46 PROCESSOR_24KF1_1,
47 PROCESSOR_74KC,
48 PROCESSOR_74KF2_1,
49 PROCESSOR_74KF1_1,
50 PROCESSOR_74KF3_2,
51 PROCESSOR_M4K,
52 PROCESSOR_R3900,
53 PROCESSOR_R6000,
54 PROCESSOR_R4000,
55 PROCESSOR_R4100,
56 PROCESSOR_R4111,
57 PROCESSOR_R4120,
58 PROCESSOR_R4130,
59 PROCESSOR_R4300,
60 PROCESSOR_R4600,
61 PROCESSOR_R4650,
62 PROCESSOR_R5000,
63 PROCESSOR_R5400,
64 PROCESSOR_R5500,
65 PROCESSOR_R7000,
66 PROCESSOR_R8000,
67 PROCESSOR_R9000,
68 PROCESSOR_SB1,
69 PROCESSOR_SB1A,
70 PROCESSOR_SR71000,
71 PROCESSOR_MAX
72 };
73
74 /* Costs of various operations on the different architectures. */
75
76 struct mips_rtx_cost_data
77 {
78 unsigned short fp_add;
79 unsigned short fp_mult_sf;
80 unsigned short fp_mult_df;
81 unsigned short fp_div_sf;
82 unsigned short fp_div_df;
83 unsigned short int_mult_si;
84 unsigned short int_mult_di;
85 unsigned short int_div_si;
86 unsigned short int_div_di;
87 unsigned short branch_cost;
88 unsigned short memory_latency;
89 };
90
91 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
92 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
93 to work on a 64-bit machine. */
94
95 #define ABI_32 0
96 #define ABI_N32 1
97 #define ABI_64 2
98 #define ABI_EABI 3
99 #define ABI_O64 4
100
101 /* Information about one recognized processor. Defined here for the
102 benefit of TARGET_CPU_CPP_BUILTINS. */
103 struct mips_cpu_info {
104 /* The 'canonical' name of the processor as far as GCC is concerned.
105 It's typically a manufacturer's prefix followed by a numerical
106 designation. It should be lowercase. */
107 const char *name;
108
109 /* The internal processor number that most closely matches this
110 entry. Several processors can have the same value, if there's no
111 difference between them from GCC's point of view. */
112 enum processor_type cpu;
113
114 /* The ISA level that the processor implements. */
115 int isa;
116 };
117
118 #ifndef USED_FOR_TARGET
119 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
120 extern const char *current_function_file; /* filename current function is in */
121 extern int num_source_filenames; /* current .file # */
122 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
123 extern int sym_lineno; /* sgi next label # for each stmt */
124 extern int set_noreorder; /* # of nested .set noreorder's */
125 extern int set_nomacro; /* # of nested .set nomacro's */
126 extern int set_noat; /* # of nested .set noat's */
127 extern int set_volatile; /* # of nested .set volatile's */
128 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
129 extern int mips_dbx_regno[];
130 extern int mips_dwarf_regno[];
131 extern bool mips_split_p[];
132 extern GTY(()) rtx cmp_operands[2];
133 extern enum processor_type mips_arch; /* which cpu to codegen for */
134 extern enum processor_type mips_tune; /* which cpu to schedule for */
135 extern int mips_isa; /* architectural level */
136 extern int mips_abi; /* which ABI to use */
137 extern int mips16_hard_float; /* mips16 without -msoft-float */
138 extern const struct mips_cpu_info mips_cpu_info_table[];
139 extern const struct mips_cpu_info *mips_arch_info;
140 extern const struct mips_cpu_info *mips_tune_info;
141 extern const struct mips_rtx_cost_data *mips_cost;
142 #endif
143
144 /* Macros to silence warnings about numbers being signed in traditional
145 C and unsigned in ISO C when compiled on 32-bit hosts. */
146
147 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
148 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
149 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
150
151 \f
152 /* Run-time compilation parameters selecting different hardware subsets. */
153
154 /* True if we are generating position-independent VxWorks RTP code. */
155 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
156
157 /* True if the call patterns should be split into a jalr followed by
158 an instruction to restore $gp. It is only safe to split the load
159 from the call when every use of $gp is explicit. */
160
161 #define TARGET_SPLIT_CALLS \
162 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
163
164 /* True if we're generating a form of -mabicalls in which we can use
165 operators like %hi and %lo to refer to locally-binding symbols.
166 We can only do this for -mno-shared, and only then if we can use
167 relocation operations instead of assembly macros. It isn't really
168 worth using absolute sequences for 64-bit symbols because GOT
169 accesses are so much shorter. */
170
171 #define TARGET_ABSOLUTE_ABICALLS \
172 (TARGET_ABICALLS \
173 && !TARGET_SHARED \
174 && TARGET_EXPLICIT_RELOCS \
175 && !ABI_HAS_64BIT_SYMBOLS)
176
177 /* True if we can optimize sibling calls. For simplicity, we only
178 handle cases in which call_insn_operand will reject invalid
179 sibcall addresses. There are two cases in which this isn't true:
180
181 - TARGET_MIPS16. call_insn_operand accepts constant addresses
182 but there is no direct jump instruction. It isn't worth
183 using sibling calls in this case anyway; they would usually
184 be longer than normal calls.
185
186 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
187 accepts global constants, but all sibcalls must be indirect. */
188 #define TARGET_SIBCALLS \
189 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
190
191 /* True if we need to use a global offset table to access some symbols. */
192 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
193
194 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
195 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
196
197 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
198 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
199
200 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
201 This is true for both the PIC and non-PIC VxWorks RTP modes. */
202 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
203
204 /* True if .gpword or .gpdword should be used for switch tables.
205
206 Although GAS does understand .gpdword, the SGI linker mishandles
207 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
208 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
209 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
210
211 /* Generate mips16 code */
212 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
213 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
214 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
215 /* Generate mips16e register save/restore sequences. */
216 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
217
218 /* Generic ISA defines. */
219 #define ISA_MIPS1 (mips_isa == 1)
220 #define ISA_MIPS2 (mips_isa == 2)
221 #define ISA_MIPS3 (mips_isa == 3)
222 #define ISA_MIPS4 (mips_isa == 4)
223 #define ISA_MIPS32 (mips_isa == 32)
224 #define ISA_MIPS32R2 (mips_isa == 33)
225 #define ISA_MIPS64 (mips_isa == 64)
226
227 /* Architecture target defines. */
228 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
229 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
230 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
231 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
232 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
233 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
234 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
235 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
236 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
237 || mips_arch == PROCESSOR_SB1A)
238 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
239
240 /* Scheduling target defines. */
241 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
242 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
243 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
244 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
245 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
246 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
247 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
248 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
249 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
250 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
251 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
252 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
253 || mips_tune == PROCESSOR_SB1A)
254 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
255 || mips_tune == PROCESSOR_24KF2_1 \
256 || mips_tune == PROCESSOR_24KF1_1)
257 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
258 || mips_tune == PROCESSOR_74KF2_1 \
259 || mips_tune == PROCESSOR_74KF1_1 \
260 || mips_tune == PROCESSOR_74KF3_2)
261 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
262
263 /* True if the pre-reload scheduler should try to create chains of
264 multiply-add or multiply-subtract instructions. For example,
265 suppose we have:
266
267 t1 = a * b
268 t2 = t1 + c * d
269 t3 = e * f
270 t4 = t3 - g * h
271
272 t1 will have a higher priority than t2 and t3 will have a higher
273 priority than t4. However, before reload, there is no dependence
274 between t1 and t3, and they can often have similar priorities.
275 The scheduler will then tend to prefer:
276
277 t1 = a * b
278 t3 = e * f
279 t2 = t1 + c * d
280 t4 = t3 - g * h
281
282 which stops us from making full use of macc/madd-style instructions.
283 This sort of situation occurs frequently in Fourier transforms and
284 in unrolled loops.
285
286 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
287 queue so that chained multiply-add and multiply-subtract instructions
288 appear ahead of any other instruction that is likely to clobber lo.
289 In the example above, if t2 and t3 become ready at the same time,
290 the code ensures that t2 is scheduled first.
291
292 Multiply-accumulate instructions are a bigger win for some targets
293 than others, so this macro is defined on an opt-in basis. */
294 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
295 || TUNE_MIPS4120 \
296 || TUNE_MIPS4130 \
297 || TUNE_24K)
298
299 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
300 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
301
302 /* Similar to TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT, but reflect the ABI
303 in use rather than whether the FPU is directly accessible. */
304 #define TARGET_HARD_FLOAT_ABI (TARGET_HARD_FLOAT || mips16_hard_float)
305 #define TARGET_SOFT_FLOAT_ABI (!TARGET_HARD_FLOAT_ABI)
306
307 /* IRIX specific stuff. */
308 #define TARGET_IRIX 0
309 #define TARGET_IRIX6 0
310
311 /* Define preprocessor macros for the -march and -mtune options.
312 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
313 processor. If INFO's canonical name is "foo", define PREFIX to
314 be "foo", and define an additional macro PREFIX_FOO. */
315 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
316 do \
317 { \
318 char *macro, *p; \
319 \
320 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
321 for (p = macro; *p != 0; p++) \
322 *p = TOUPPER (*p); \
323 \
324 builtin_define (macro); \
325 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
326 free (macro); \
327 } \
328 while (0)
329
330 /* Target CPU builtins. */
331 #define TARGET_CPU_CPP_BUILTINS() \
332 do \
333 { \
334 /* Everyone but IRIX defines this to mips. */ \
335 if (!TARGET_IRIX) \
336 builtin_assert ("machine=mips"); \
337 \
338 builtin_assert ("cpu=mips"); \
339 builtin_define ("__mips__"); \
340 builtin_define ("_mips"); \
341 \
342 /* We do this here because __mips is defined below \
343 and so we can't use builtin_define_std. */ \
344 if (!flag_iso) \
345 builtin_define ("mips"); \
346 \
347 if (TARGET_64BIT) \
348 builtin_define ("__mips64"); \
349 \
350 if (!TARGET_IRIX) \
351 { \
352 /* Treat _R3000 and _R4000 like register-size \
353 defines, which is how they've historically \
354 been used. */ \
355 if (TARGET_64BIT) \
356 { \
357 builtin_define_std ("R4000"); \
358 builtin_define ("_R4000"); \
359 } \
360 else \
361 { \
362 builtin_define_std ("R3000"); \
363 builtin_define ("_R3000"); \
364 } \
365 } \
366 if (TARGET_FLOAT64) \
367 builtin_define ("__mips_fpr=64"); \
368 else \
369 builtin_define ("__mips_fpr=32"); \
370 \
371 if (TARGET_MIPS16) \
372 builtin_define ("__mips16"); \
373 \
374 if (TARGET_MIPS3D) \
375 builtin_define ("__mips3d"); \
376 \
377 if (TARGET_SMARTMIPS) \
378 builtin_define ("__mips_smartmips"); \
379 \
380 if (TARGET_DSP) \
381 builtin_define ("__mips_dsp"); \
382 \
383 if (TARGET_DSPR2) \
384 builtin_define ("__mips_dspr2"); \
385 \
386 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
387 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
388 \
389 if (ISA_MIPS1) \
390 { \
391 builtin_define ("__mips=1"); \
392 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
393 } \
394 else if (ISA_MIPS2) \
395 { \
396 builtin_define ("__mips=2"); \
397 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
398 } \
399 else if (ISA_MIPS3) \
400 { \
401 builtin_define ("__mips=3"); \
402 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
403 } \
404 else if (ISA_MIPS4) \
405 { \
406 builtin_define ("__mips=4"); \
407 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
408 } \
409 else if (ISA_MIPS32) \
410 { \
411 builtin_define ("__mips=32"); \
412 builtin_define ("__mips_isa_rev=1"); \
413 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
414 } \
415 else if (ISA_MIPS32R2) \
416 { \
417 builtin_define ("__mips=32"); \
418 builtin_define ("__mips_isa_rev=2"); \
419 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
420 } \
421 else if (ISA_MIPS64) \
422 { \
423 builtin_define ("__mips=64"); \
424 builtin_define ("__mips_isa_rev=1"); \
425 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
426 } \
427 \
428 /* These defines reflect the ABI in use, not whether the \
429 FPU is directly accessible. */ \
430 if (TARGET_HARD_FLOAT_ABI) \
431 builtin_define ("__mips_hard_float"); \
432 else \
433 builtin_define ("__mips_soft_float"); \
434 \
435 if (TARGET_SINGLE_FLOAT) \
436 builtin_define ("__mips_single_float"); \
437 \
438 if (TARGET_PAIRED_SINGLE_FLOAT) \
439 builtin_define ("__mips_paired_single_float"); \
440 \
441 if (TARGET_BIG_ENDIAN) \
442 { \
443 builtin_define_std ("MIPSEB"); \
444 builtin_define ("_MIPSEB"); \
445 } \
446 else \
447 { \
448 builtin_define_std ("MIPSEL"); \
449 builtin_define ("_MIPSEL"); \
450 } \
451 \
452 /* Macros dependent on the C dialect. */ \
453 if (preprocessing_asm_p ()) \
454 { \
455 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
456 builtin_define ("_LANGUAGE_ASSEMBLY"); \
457 } \
458 else if (c_dialect_cxx ()) \
459 { \
460 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
461 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
462 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
463 } \
464 else \
465 { \
466 builtin_define_std ("LANGUAGE_C"); \
467 builtin_define ("_LANGUAGE_C"); \
468 } \
469 if (c_dialect_objc ()) \
470 { \
471 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
472 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
473 /* Bizarre, but needed at least for Irix. */ \
474 builtin_define_std ("LANGUAGE_C"); \
475 builtin_define ("_LANGUAGE_C"); \
476 } \
477 \
478 if (mips_abi == ABI_EABI) \
479 builtin_define ("__mips_eabi"); \
480 \
481 } while (0)
482
483 /* Default target_flags if no switches are specified */
484
485 #ifndef TARGET_DEFAULT
486 #define TARGET_DEFAULT 0
487 #endif
488
489 #ifndef TARGET_CPU_DEFAULT
490 #define TARGET_CPU_DEFAULT 0
491 #endif
492
493 #ifndef TARGET_ENDIAN_DEFAULT
494 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
495 #endif
496
497 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
498 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
499 #endif
500
501 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
502 #ifndef MIPS_ISA_DEFAULT
503 #ifndef MIPS_CPU_STRING_DEFAULT
504 #define MIPS_CPU_STRING_DEFAULT "from-abi"
505 #endif
506 #endif
507
508 #ifdef IN_LIBGCC2
509 #undef TARGET_64BIT
510 /* Make this compile time constant for libgcc2 */
511 #ifdef __mips64
512 #define TARGET_64BIT 1
513 #else
514 #define TARGET_64BIT 0
515 #endif
516 #endif /* IN_LIBGCC2 */
517
518 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
519
520 #ifndef MULTILIB_ENDIAN_DEFAULT
521 #if TARGET_ENDIAN_DEFAULT == 0
522 #define MULTILIB_ENDIAN_DEFAULT "EL"
523 #else
524 #define MULTILIB_ENDIAN_DEFAULT "EB"
525 #endif
526 #endif
527
528 #ifndef MULTILIB_ISA_DEFAULT
529 # if MIPS_ISA_DEFAULT == 1
530 # define MULTILIB_ISA_DEFAULT "mips1"
531 # else
532 # if MIPS_ISA_DEFAULT == 2
533 # define MULTILIB_ISA_DEFAULT "mips2"
534 # else
535 # if MIPS_ISA_DEFAULT == 3
536 # define MULTILIB_ISA_DEFAULT "mips3"
537 # else
538 # if MIPS_ISA_DEFAULT == 4
539 # define MULTILIB_ISA_DEFAULT "mips4"
540 # else
541 # if MIPS_ISA_DEFAULT == 32
542 # define MULTILIB_ISA_DEFAULT "mips32"
543 # else
544 # if MIPS_ISA_DEFAULT == 33
545 # define MULTILIB_ISA_DEFAULT "mips32r2"
546 # else
547 # if MIPS_ISA_DEFAULT == 64
548 # define MULTILIB_ISA_DEFAULT "mips64"
549 # else
550 # define MULTILIB_ISA_DEFAULT "mips1"
551 # endif
552 # endif
553 # endif
554 # endif
555 # endif
556 # endif
557 # endif
558 #endif
559
560 #ifndef MULTILIB_DEFAULTS
561 #define MULTILIB_DEFAULTS \
562 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
563 #endif
564
565 /* We must pass -EL to the linker by default for little endian embedded
566 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
567 linker will default to using big-endian output files. The OUTPUT_FORMAT
568 line must be in the linker script, otherwise -EB/-EL will not work. */
569
570 #ifndef ENDIAN_SPEC
571 #if TARGET_ENDIAN_DEFAULT == 0
572 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
573 #else
574 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
575 #endif
576 #endif
577
578 /* A spec condition that matches all non-mips16 -mips arguments. */
579
580 #define MIPS_ISA_LEVEL_OPTION_SPEC \
581 "mips1|mips2|mips3|mips4|mips32*|mips64*"
582
583 /* A spec condition that matches all non-mips16 architecture arguments. */
584
585 #define MIPS_ARCH_OPTION_SPEC \
586 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
587
588 /* A spec that infers a -mips argument from an -march argument. */
589
590 #define MIPS_ISA_LEVEL_SPEC \
591 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
592 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
593 %{march=mips2|march=r6000:-mips2} \
594 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
595 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
596 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
597 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
598 |march=34k*|march=74k*: -mips32r2} \
599 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64}}"
600
601 /* Support for a compile-time default CPU, et cetera. The rules are:
602 --with-arch is ignored if -march is specified or a -mips is specified
603 (other than -mips16).
604 --with-tune is ignored if -mtune is specified.
605 --with-abi is ignored if -mabi is specified.
606 --with-float is ignored if -mhard-float or -msoft-float are
607 specified.
608 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
609 specified. */
610 #define OPTION_DEFAULT_SPECS \
611 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
612 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
613 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
614 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
615 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
616
617
618 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
619 && ISA_HAS_COND_TRAP)
620
621 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
622 && !TARGET_SR71K \
623 && !TARGET_MIPS16)
624
625 /* True if the ABI can only work with 64-bit integer registers. We
626 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
627 otherwise floating-point registers must also be 64-bit. */
628 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
629
630 /* Likewise for 32-bit regs. */
631 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
632
633 /* True if symbols are 64 bits wide. At present, n64 is the only
634 ABI for which this is true. */
635 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
636
637 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
638 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
639 || ISA_MIPS4 \
640 || ISA_MIPS64)
641
642 /* ISA has branch likely instructions (e.g. mips2). */
643 /* Disable branchlikely for tx39 until compare rewrite. They haven't
644 been generated up to this point. */
645 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
646
647 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
648 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
649 || TARGET_MIPS5400 \
650 || TARGET_MIPS5500 \
651 || TARGET_MIPS7000 \
652 || TARGET_MIPS9000 \
653 || TARGET_MAD \
654 || ISA_MIPS32 \
655 || ISA_MIPS32R2 \
656 || ISA_MIPS64) \
657 && !TARGET_MIPS16)
658
659 /* ISA has the conditional move instructions introduced in mips4. */
660 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
661 || ISA_MIPS32 \
662 || ISA_MIPS32R2 \
663 || ISA_MIPS64) \
664 && !TARGET_MIPS5500 \
665 && !TARGET_MIPS16)
666
667 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
668 branch on CC, and move (both FP and non-FP) on CC. */
669 #define ISA_HAS_8CC (ISA_MIPS4 \
670 || ISA_MIPS32 \
671 || ISA_MIPS32R2 \
672 || ISA_MIPS64)
673
674 /* This is a catch all for other mips4 instructions: indexed load, the
675 FP madd and msub instructions, and the FP recip and recip sqrt
676 instructions. */
677 #define ISA_HAS_FP4 ((ISA_MIPS4 \
678 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
679 || ISA_MIPS64) \
680 && !TARGET_MIPS16)
681
682 /* ISA has conditional trap instructions. */
683 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
684 && !TARGET_MIPS16)
685
686 /* ISA has integer multiply-accumulate instructions, madd and msub. */
687 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
688 || ISA_MIPS32R2 \
689 || ISA_MIPS64) \
690 && !TARGET_MIPS16)
691
692 /* Integer multiply-accumulate instructions should be generated. */
693 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
694
695 /* ISA has floating-point nmadd and nmsub instructions. */
696 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
697 || ISA_MIPS64) \
698 && (!TARGET_MIPS5400 || TARGET_MAD) \
699 && !TARGET_MIPS16)
700
701 /* ISA has count leading zeroes/ones instruction (not implemented). */
702 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
703 || ISA_MIPS32R2 \
704 || ISA_MIPS64) \
705 && !TARGET_MIPS16)
706
707 /* ISA has three operand multiply instructions that put
708 the high part in an accumulator: mulhi or mulhiu. */
709 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
710 || TARGET_MIPS5500 \
711 || TARGET_SR71K) \
712 && !TARGET_MIPS16)
713
714 /* ISA has three operand multiply instructions that
715 negates the result and puts the result in an accumulator. */
716 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
717 || TARGET_MIPS5500 \
718 || TARGET_SR71K) \
719 && !TARGET_MIPS16)
720
721 /* ISA has three operand multiply instructions that subtracts the
722 result from a 4th operand and puts the result in an accumulator. */
723 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
724 || TARGET_MIPS5500 \
725 || TARGET_SR71K) \
726 && !TARGET_MIPS16)
727
728 /* ISA has three operand multiply instructions that the result
729 from a 4th operand and puts the result in an accumulator. */
730 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
731 || TARGET_MIPS4130 \
732 || TARGET_MIPS5400 \
733 || TARGET_MIPS5500 \
734 || TARGET_SR71K) \
735 && !TARGET_MIPS16)
736
737 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
738 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
739 || TARGET_MIPS4130) \
740 && !TARGET_MIPS16)
741
742 /* ISA has the "ror" (rotate right) instructions. */
743 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
744 || TARGET_MIPS5400 \
745 || TARGET_MIPS5500 \
746 || TARGET_SR71K \
747 || TARGET_SMARTMIPS) \
748 && !TARGET_MIPS16)
749
750 /* ISA has data prefetch instructions. This controls use of 'pref'. */
751 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
752 || ISA_MIPS32 \
753 || ISA_MIPS32R2 \
754 || ISA_MIPS64) \
755 && !TARGET_MIPS16)
756
757 /* ISA has data indexed prefetch instructions. This controls use of
758 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
759 (prefx is a cop1x instruction, so can only be used if FP is
760 enabled.) */
761 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
762 || ISA_MIPS32R2 \
763 || ISA_MIPS64) \
764 && !TARGET_MIPS16)
765
766 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
767 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
768 also requires TARGET_DOUBLE_FLOAT. */
769 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
770
771 /* ISA includes the MIPS32r2 seb and seh instructions. */
772 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
773 && !TARGET_MIPS16)
774
775 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
776 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
777 && !TARGET_MIPS16)
778
779 /* ISA has instructions for accessing top part of 64-bit fp regs. */
780 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
781
782 /* ISA has lwxs instruction (load w/scaled index address. */
783 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
784
785 /* True if the result of a load is not available to the next instruction.
786 A nop will then be needed between instructions like "lw $4,..."
787 and "addiu $4,$4,1". */
788 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
789 && !TARGET_MIPS3900 \
790 && !TARGET_MIPS16)
791
792 /* Likewise mtc1 and mfc1. */
793 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
794
795 /* Likewise floating-point comparisons. */
796 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
797
798 /* True if mflo and mfhi can be immediately followed by instructions
799 which write to the HI and LO registers.
800
801 According to MIPS specifications, MIPS ISAs I, II, and III need
802 (at least) two instructions between the reads of HI/LO and
803 instructions which write them, and later ISAs do not. Contradicting
804 the MIPS specifications, some MIPS IV processor user manuals (e.g.
805 the UM for the NEC Vr5000) document needing the instructions between
806 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
807 MIPS64 and later ISAs to have the interlocks, plus any specific
808 earlier-ISA CPUs for which CPU documentation declares that the
809 instructions are really interlocked. */
810 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
811 || ISA_MIPS32R2 \
812 || ISA_MIPS64 \
813 || TARGET_MIPS5500)
814
815 /* ISA includes synci, jr.hb and jalr.hb. */
816 #define ISA_HAS_SYNCI ISA_MIPS32R2
817
818 \f
819 /* Add -G xx support. */
820
821 #undef SWITCH_TAKES_ARG
822 #define SWITCH_TAKES_ARG(CHAR) \
823 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
824
825 #define OVERRIDE_OPTIONS override_options ()
826
827 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
828
829 /* Show we can debug even without a frame pointer. */
830 #define CAN_DEBUG_WITHOUT_FP
831 \f
832 /* Tell collect what flags to pass to nm. */
833 #ifndef NM_FLAGS
834 #define NM_FLAGS "-Bn"
835 #endif
836
837 \f
838 #ifndef MIPS_ABI_DEFAULT
839 #define MIPS_ABI_DEFAULT ABI_32
840 #endif
841
842 /* Use the most portable ABI flag for the ASM specs. */
843
844 #if MIPS_ABI_DEFAULT == ABI_32
845 #define MULTILIB_ABI_DEFAULT "mabi=32"
846 #endif
847
848 #if MIPS_ABI_DEFAULT == ABI_O64
849 #define MULTILIB_ABI_DEFAULT "mabi=o64"
850 #endif
851
852 #if MIPS_ABI_DEFAULT == ABI_N32
853 #define MULTILIB_ABI_DEFAULT "mabi=n32"
854 #endif
855
856 #if MIPS_ABI_DEFAULT == ABI_64
857 #define MULTILIB_ABI_DEFAULT "mabi=64"
858 #endif
859
860 #if MIPS_ABI_DEFAULT == ABI_EABI
861 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
862 #endif
863
864 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
865 to the assembler. It may be overridden by subtargets. */
866 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
867 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
868 %{noasmopt:-O0} \
869 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
870 #endif
871
872 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
873 the assembler. It may be overridden by subtargets.
874
875 Beginning with gas 2.13, -mdebug must be passed to correctly handle
876 COFF debugging info. */
877
878 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
879 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
880 %{g} %{g0} %{g1} %{g2} %{g3} \
881 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
882 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
883 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
884 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
885 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
886 #endif
887
888 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
889 overridden by subtargets. */
890
891 #ifndef SUBTARGET_ASM_SPEC
892 #define SUBTARGET_ASM_SPEC ""
893 #endif
894
895 #undef ASM_SPEC
896 #define ASM_SPEC "\
897 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
898 %{mips32} %{mips32r2} %{mips64} \
899 %{mips16} %{mno-mips16:-no-mips16} \
900 %{mips3d} %{mno-mips3d:-no-mips3d} \
901 %{mdmx} %{mno-mdmx:-no-mdmx} \
902 %{mdsp} %{mno-dsp} \
903 %{mdspr2} %{mno-dspr2} \
904 %{msmartmips} %{mno-smartmips} \
905 %{mmt} %{mno-mt} \
906 %{mfix-vr4120} %{mfix-vr4130} \
907 %(subtarget_asm_optimizing_spec) \
908 %(subtarget_asm_debugging_spec) \
909 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
910 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
911 %{mfp32} %{mfp64} \
912 %{mshared} %{mno-shared} \
913 %{msym32} %{mno-sym32} \
914 %{mtune=*} %{v} \
915 %(subtarget_asm_spec)"
916
917 /* Extra switches sometimes passed to the linker. */
918 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
919 will interpret it as a -b option. */
920
921 #ifndef LINK_SPEC
922 #define LINK_SPEC "\
923 %(endian_spec) \
924 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
925 %{bestGnum} %{shared} %{non_shared}"
926 #endif /* LINK_SPEC defined */
927
928
929 /* Specs for the compiler proper */
930
931 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
932 overridden by subtargets. */
933 #ifndef SUBTARGET_CC1_SPEC
934 #define SUBTARGET_CC1_SPEC ""
935 #endif
936
937 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
938
939 #undef CC1_SPEC
940 #define CC1_SPEC "\
941 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
942 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
943 %{save-temps: } \
944 %(subtarget_cc1_spec)"
945
946 /* Preprocessor specs. */
947
948 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
949 overridden by subtargets. */
950 #ifndef SUBTARGET_CPP_SPEC
951 #define SUBTARGET_CPP_SPEC ""
952 #endif
953
954 #define CPP_SPEC "%(subtarget_cpp_spec)"
955
956 /* This macro defines names of additional specifications to put in the specs
957 that can be used in various specifications like CC1_SPEC. Its definition
958 is an initializer with a subgrouping for each command option.
959
960 Each subgrouping contains a string constant, that defines the
961 specification name, and a string constant that used by the GCC driver
962 program.
963
964 Do not define this macro if it does not need to do anything. */
965
966 #define EXTRA_SPECS \
967 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
968 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
969 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
970 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
971 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
972 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
973 { "endian_spec", ENDIAN_SPEC }, \
974 SUBTARGET_EXTRA_SPECS
975
976 #ifndef SUBTARGET_EXTRA_SPECS
977 #define SUBTARGET_EXTRA_SPECS
978 #endif
979 \f
980 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
981 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
982 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
983
984 #ifndef PREFERRED_DEBUGGING_TYPE
985 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
986 #endif
987
988 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
989
990 /* By default, turn on GDB extensions. */
991 #define DEFAULT_GDB_EXTENSIONS 1
992
993 /* Local compiler-generated symbols must have a prefix that the assembler
994 understands. By default, this is $, although some targets (e.g.,
995 NetBSD-ELF) need to override this. */
996
997 #ifndef LOCAL_LABEL_PREFIX
998 #define LOCAL_LABEL_PREFIX "$"
999 #endif
1000
1001 /* By default on the mips, external symbols do not have an underscore
1002 prepended, but some targets (e.g., NetBSD) require this. */
1003
1004 #ifndef USER_LABEL_PREFIX
1005 #define USER_LABEL_PREFIX ""
1006 #endif
1007
1008 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1009 since the length can run past this up to a continuation point. */
1010 #undef DBX_CONTIN_LENGTH
1011 #define DBX_CONTIN_LENGTH 1500
1012
1013 /* How to renumber registers for dbx and gdb. */
1014 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1015
1016 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1017 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1018
1019 /* The DWARF 2 CFA column which tracks the return address. */
1020 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1021
1022 /* Before the prologue, RA lives in r31. */
1023 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1024
1025 /* Describe how we implement __builtin_eh_return. */
1026 #define EH_RETURN_DATA_REGNO(N) \
1027 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1028
1029 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1030
1031 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1032 The default for this in 64-bit mode is 8, which causes problems with
1033 SFmode register saves. */
1034 #define DWARF_CIE_DATA_ALIGNMENT -4
1035
1036 /* Correct the offset of automatic variables and arguments. Note that
1037 the MIPS debug format wants all automatic variables and arguments
1038 to be in terms of the virtual frame pointer (stack pointer before
1039 any adjustment in the function), while the MIPS 3.0 linker wants
1040 the frame pointer to be the stack pointer after the initial
1041 adjustment. */
1042
1043 #define DEBUGGER_AUTO_OFFSET(X) \
1044 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1045 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1046 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1047 \f
1048 /* Target machine storage layout */
1049
1050 #define BITS_BIG_ENDIAN 0
1051 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1052 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1053
1054 /* Define this to set the endianness to use in libgcc2.c, which can
1055 not depend on target_flags. */
1056 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1057 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1058 #else
1059 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1060 #endif
1061
1062 #define MAX_BITS_PER_WORD 64
1063
1064 /* Width of a word, in units (bytes). */
1065 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1066 #ifndef IN_LIBGCC2
1067 #define MIN_UNITS_PER_WORD 4
1068 #endif
1069
1070 /* For MIPS, width of a floating point register. */
1071 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1072
1073 /* The number of consecutive floating-point registers needed to store the
1074 largest format supported by the FPU. */
1075 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1076
1077 /* The number of consecutive floating-point registers needed to store the
1078 smallest format supported by the FPU. */
1079 #define MIN_FPRS_PER_FMT \
1080 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1081
1082 /* The largest size of value that can be held in floating-point
1083 registers and moved with a single instruction. */
1084 #define UNITS_PER_HWFPVALUE \
1085 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1086
1087 /* The largest size of value that can be held in floating-point
1088 registers. */
1089 #define UNITS_PER_FPVALUE \
1090 (TARGET_SOFT_FLOAT_ABI ? 0 \
1091 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1092 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1093
1094 /* The number of bytes in a double. */
1095 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1096
1097 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1098
1099 /* Set the sizes of the core types. */
1100 #define SHORT_TYPE_SIZE 16
1101 #define INT_TYPE_SIZE 32
1102 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1103 #define LONG_LONG_TYPE_SIZE 64
1104
1105 #define FLOAT_TYPE_SIZE 32
1106 #define DOUBLE_TYPE_SIZE 64
1107 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1108
1109 /* long double is not a fixed mode, but the idea is that, if we
1110 support long double, we also want a 128-bit integer type. */
1111 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1112
1113 #ifdef IN_LIBGCC2
1114 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1115 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1116 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1117 # else
1118 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1119 # endif
1120 #endif
1121
1122 /* Width in bits of a pointer. */
1123 #ifndef POINTER_SIZE
1124 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1125 #endif
1126
1127 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1128 #define PARM_BOUNDARY BITS_PER_WORD
1129
1130 /* Allocation boundary (in *bits*) for the code of a function. */
1131 #define FUNCTION_BOUNDARY 32
1132
1133 /* Alignment of field after `int : 0' in a structure. */
1134 #define EMPTY_FIELD_BOUNDARY 32
1135
1136 /* Every structure's size must be a multiple of this. */
1137 /* 8 is observed right on a DECstation and on riscos 4.02. */
1138 #define STRUCTURE_SIZE_BOUNDARY 8
1139
1140 /* There is no point aligning anything to a rounder boundary than this. */
1141 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1142
1143 /* All accesses must be aligned. */
1144 #define STRICT_ALIGNMENT 1
1145
1146 /* Define this if you wish to imitate the way many other C compilers
1147 handle alignment of bitfields and the structures that contain
1148 them.
1149
1150 The behavior is that the type written for a bit-field (`int',
1151 `short', or other integer type) imposes an alignment for the
1152 entire structure, as if the structure really did contain an
1153 ordinary field of that type. In addition, the bit-field is placed
1154 within the structure so that it would fit within such a field,
1155 not crossing a boundary for it.
1156
1157 Thus, on most machines, a bit-field whose type is written as `int'
1158 would not cross a four-byte boundary, and would force four-byte
1159 alignment for the whole structure. (The alignment used may not
1160 be four bytes; it is controlled by the other alignment
1161 parameters.)
1162
1163 If the macro is defined, its definition should be a C expression;
1164 a nonzero value for the expression enables this behavior. */
1165
1166 #define PCC_BITFIELD_TYPE_MATTERS 1
1167
1168 /* If defined, a C expression to compute the alignment given to a
1169 constant that is being placed in memory. CONSTANT is the constant
1170 and ALIGN is the alignment that the object would ordinarily have.
1171 The value of this macro is used instead of that alignment to align
1172 the object.
1173
1174 If this macro is not defined, then ALIGN is used.
1175
1176 The typical use of this macro is to increase alignment for string
1177 constants to be word aligned so that `strcpy' calls that copy
1178 constants can be done inline. */
1179
1180 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1181 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1182 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1183
1184 /* If defined, a C expression to compute the alignment for a static
1185 variable. TYPE is the data type, and ALIGN is the alignment that
1186 the object would ordinarily have. The value of this macro is used
1187 instead of that alignment to align the object.
1188
1189 If this macro is not defined, then ALIGN is used.
1190
1191 One use of this macro is to increase alignment of medium-size
1192 data to make it all fit in fewer cache lines. Another is to
1193 cause character arrays to be word-aligned so that `strcpy' calls
1194 that copy constants to character arrays can be done inline. */
1195
1196 #undef DATA_ALIGNMENT
1197 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1198 ((((ALIGN) < BITS_PER_WORD) \
1199 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1200 || TREE_CODE (TYPE) == UNION_TYPE \
1201 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1202
1203
1204 #define PAD_VARARGS_DOWN \
1205 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1206
1207 /* Define if operations between registers always perform the operation
1208 on the full register even if a narrower mode is specified. */
1209 #define WORD_REGISTER_OPERATIONS
1210
1211 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1212 moves. All other references are zero extended. */
1213 #define LOAD_EXTEND_OP(MODE) \
1214 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1215 ? SIGN_EXTEND : ZERO_EXTEND)
1216
1217 /* Define this macro if it is advisable to hold scalars in registers
1218 in a wider mode than that declared by the program. In such cases,
1219 the value is constrained to be within the bounds of the declared
1220 type, but kept valid in the wider mode. The signedness of the
1221 extension may differ from that of the type. */
1222
1223 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1224 if (GET_MODE_CLASS (MODE) == MODE_INT \
1225 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1226 { \
1227 if ((MODE) == SImode) \
1228 (UNSIGNEDP) = 0; \
1229 (MODE) = Pmode; \
1230 }
1231
1232 /* Define if loading short immediate values into registers sign extends. */
1233 #define SHORT_IMMEDIATES_SIGN_EXTEND
1234
1235 /* The [d]clz instructions have the natural values at 0. */
1236
1237 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1238 ((VALUE) = GET_MODE_BITSIZE (MODE), true)
1239 \f
1240 /* Standard register usage. */
1241
1242 /* Number of hardware registers. We have:
1243
1244 - 32 integer registers
1245 - 32 floating point registers
1246 - 8 condition code registers
1247 - 2 accumulator registers (hi and lo)
1248 - 32 registers each for coprocessors 0, 2 and 3
1249 - 3 fake registers:
1250 - ARG_POINTER_REGNUM
1251 - FRAME_POINTER_REGNUM
1252 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1253 - 3 dummy entries that were used at various times in the past.
1254 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1255 - 6 DSP control registers */
1256
1257 #define FIRST_PSEUDO_REGISTER 188
1258
1259 /* By default, fix the kernel registers ($26 and $27), the global
1260 pointer ($28) and the stack pointer ($29). This can change
1261 depending on the command-line options.
1262
1263 Regarding coprocessor registers: without evidence to the contrary,
1264 it's best to assume that each coprocessor register has a unique
1265 use. This can be overridden, in, e.g., override_options() or
1266 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1267 for a particular target. */
1268
1269 #define FIXED_REGISTERS \
1270 { \
1271 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1272 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1273 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1274 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1275 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1276 /* COP0 registers */ \
1277 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1278 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1279 /* COP2 registers */ \
1280 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1281 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1282 /* COP3 registers */ \
1283 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1284 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1285 /* 6 DSP accumulator registers & 6 control registers */ \
1286 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1287 }
1288
1289
1290 /* Set up this array for o32 by default.
1291
1292 Note that we don't mark $31 as a call-clobbered register. The idea is
1293 that it's really the call instructions themselves which clobber $31.
1294 We don't care what the called function does with it afterwards.
1295
1296 This approach makes it easier to implement sibcalls. Unlike normal
1297 calls, sibcalls don't clobber $31, so the register reaches the
1298 called function in tact. EPILOGUE_USES says that $31 is useful
1299 to the called function. */
1300
1301 #define CALL_USED_REGISTERS \
1302 { \
1303 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1304 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1305 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1306 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1307 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1308 /* COP0 registers */ \
1309 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1310 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1311 /* COP2 registers */ \
1312 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1313 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1314 /* COP3 registers */ \
1315 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1316 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1317 /* 6 DSP accumulator registers & 6 control registers */ \
1318 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1319 }
1320
1321
1322 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1323
1324 #define CALL_REALLY_USED_REGISTERS \
1325 { /* General registers. */ \
1326 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1327 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1328 /* Floating-point registers. */ \
1329 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1330 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1331 /* Others. */ \
1332 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1333 /* COP0 registers */ \
1334 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1335 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1336 /* COP2 registers */ \
1337 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1338 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1339 /* COP3 registers */ \
1340 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1341 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1342 /* 6 DSP accumulator registers & 6 control registers */ \
1343 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1344 }
1345
1346 /* Internal macros to classify a register number as to whether it's a
1347 general purpose register, a floating point register, a
1348 multiply/divide register, or a status register. */
1349
1350 #define GP_REG_FIRST 0
1351 #define GP_REG_LAST 31
1352 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1353 #define GP_DBX_FIRST 0
1354
1355 #define FP_REG_FIRST 32
1356 #define FP_REG_LAST 63
1357 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1358 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1359
1360 #define MD_REG_FIRST 64
1361 #define MD_REG_LAST 65
1362 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1363 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1364
1365 /* The DWARF 2 CFA column which tracks the return address from a
1366 signal handler context. This means that to maintain backwards
1367 compatibility, no hard register can be assigned this column if it
1368 would need to be handled by the DWARF unwinder. */
1369 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1370
1371 #define ST_REG_FIRST 67
1372 #define ST_REG_LAST 74
1373 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1374
1375
1376 /* FIXME: renumber. */
1377 #define COP0_REG_FIRST 80
1378 #define COP0_REG_LAST 111
1379 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1380
1381 #define COP2_REG_FIRST 112
1382 #define COP2_REG_LAST 143
1383 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1384
1385 #define COP3_REG_FIRST 144
1386 #define COP3_REG_LAST 175
1387 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1388 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1389 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1390
1391 #define DSP_ACC_REG_FIRST 176
1392 #define DSP_ACC_REG_LAST 181
1393 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1394
1395 #define AT_REGNUM (GP_REG_FIRST + 1)
1396 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1397 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1398
1399 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1400 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1401 should be used instead. */
1402 #define FPSW_REGNUM ST_REG_FIRST
1403
1404 #define GP_REG_P(REGNO) \
1405 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1406 #define M16_REG_P(REGNO) \
1407 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1408 #define FP_REG_P(REGNO) \
1409 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1410 #define MD_REG_P(REGNO) \
1411 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1412 #define ST_REG_P(REGNO) \
1413 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1414 #define COP0_REG_P(REGNO) \
1415 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1416 #define COP2_REG_P(REGNO) \
1417 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1418 #define COP3_REG_P(REGNO) \
1419 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1420 #define ALL_COP_REG_P(REGNO) \
1421 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1422 /* Test if REGNO is one of the 6 new DSP accumulators. */
1423 #define DSP_ACC_REG_P(REGNO) \
1424 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1425 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1426 #define ACC_REG_P(REGNO) \
1427 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1428
1429 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1430
1431 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1432 to initialize the mips16 gp pseudo register. */
1433 #define CONST_GP_P(X) \
1434 (GET_CODE (X) == CONST \
1435 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1436 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1437
1438 /* Return coprocessor number from register number. */
1439
1440 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1441 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1442 : COP3_REG_P (REGNO) ? '3' : '?')
1443
1444
1445 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1446
1447 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1448 array built in override_options. Because machmodes.h is not yet
1449 included before this file is processed, the MODE bound can't be
1450 expressed here. */
1451
1452 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1453
1454 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1455 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1456
1457 /* Value is 1 if it is a good idea to tie two pseudo registers
1458 when one has mode MODE1 and one has mode MODE2.
1459 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1460 for any hard reg, then this must be 0 for correct output. */
1461 #define MODES_TIEABLE_P(MODE1, MODE2) \
1462 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1463 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1464 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1465 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1466
1467 /* Register to use for pushing function arguments. */
1468 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1469
1470 /* These two registers don't really exist: they get eliminated to either
1471 the stack or hard frame pointer. */
1472 #define ARG_POINTER_REGNUM 77
1473 #define FRAME_POINTER_REGNUM 78
1474
1475 /* $30 is not available on the mips16, so we use $17 as the frame
1476 pointer. */
1477 #define HARD_FRAME_POINTER_REGNUM \
1478 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1479
1480 /* Value should be nonzero if functions must have frame pointers.
1481 Zero means the frame pointer need not be set up (and parms
1482 may be accessed via the stack pointer) in functions that seem suitable.
1483 This is computed in `reload', in reload1.c. */
1484 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1485
1486 /* Register in which static-chain is passed to a function. */
1487 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1488
1489 /* Registers used as temporaries in prologue/epilogue code. If we're
1490 generating mips16 code, these registers must come from the core set
1491 of 8. The prologue register mustn't conflict with any incoming
1492 arguments, the static chain pointer, or the frame pointer. The
1493 epilogue temporary mustn't conflict with the return registers, the
1494 frame pointer, the EH stack adjustment, or the EH data registers. */
1495
1496 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1497 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1498
1499 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1500 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1501
1502 /* Define this macro if it is as good or better to call a constant
1503 function address than to call an address kept in a register. */
1504 #define NO_FUNCTION_CSE 1
1505
1506 /* The ABI-defined global pointer. Sometimes we use a different
1507 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1508 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1509
1510 /* We normally use $28 as the global pointer. However, when generating
1511 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1512 register instead. They can then avoid saving and restoring $28
1513 and perhaps avoid using a frame at all.
1514
1515 When a leaf function uses something other than $28, mips_expand_prologue
1516 will modify pic_offset_table_rtx in place. Take the register number
1517 from there after reload. */
1518 #define PIC_OFFSET_TABLE_REGNUM \
1519 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1520
1521 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1522 \f
1523 /* Define the classes of registers for register constraints in the
1524 machine description. Also define ranges of constants.
1525
1526 One of the classes must always be named ALL_REGS and include all hard regs.
1527 If there is more than one class, another class must be named NO_REGS
1528 and contain no registers.
1529
1530 The name GENERAL_REGS must be the name of a class (or an alias for
1531 another name such as ALL_REGS). This is the class of registers
1532 that is allowed by "g" or "r" in a register constraint.
1533 Also, registers outside this class are allocated only when
1534 instructions express preferences for them.
1535
1536 The classes must be numbered in nondecreasing order; that is,
1537 a larger-numbered class must never be contained completely
1538 in a smaller-numbered class.
1539
1540 For any two classes, it is very desirable that there be another
1541 class that represents their union. */
1542
1543 enum reg_class
1544 {
1545 NO_REGS, /* no registers in set */
1546 M16_NA_REGS, /* mips16 regs not used to pass args */
1547 M16_REGS, /* mips16 directly accessible registers */
1548 T_REG, /* mips16 T register ($24) */
1549 M16_T_REGS, /* mips16 registers plus T register */
1550 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1551 V1_REG, /* Register $v1 ($3) used for TLS access. */
1552 LEA_REGS, /* Every GPR except $25 */
1553 GR_REGS, /* integer registers */
1554 FP_REGS, /* floating point registers */
1555 MD0_REG, /* first multiply/divide register */
1556 MD1_REG, /* second multiply/divide register */
1557 MD_REGS, /* multiply/divide registers (hi/lo) */
1558 COP0_REGS, /* generic coprocessor classes */
1559 COP2_REGS,
1560 COP3_REGS,
1561 HI_AND_GR_REGS, /* union classes */
1562 LO_AND_GR_REGS,
1563 HI_AND_FP_REGS,
1564 COP0_AND_GR_REGS,
1565 COP2_AND_GR_REGS,
1566 COP3_AND_GR_REGS,
1567 ALL_COP_REGS,
1568 ALL_COP_AND_GR_REGS,
1569 ST_REGS, /* status registers (fp status) */
1570 DSP_ACC_REGS, /* DSP accumulator registers */
1571 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1572 ALL_REGS, /* all registers */
1573 LIM_REG_CLASSES /* max value + 1 */
1574 };
1575
1576 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1577
1578 #define GENERAL_REGS GR_REGS
1579
1580 /* An initializer containing the names of the register classes as C
1581 string constants. These names are used in writing some of the
1582 debugging dumps. */
1583
1584 #define REG_CLASS_NAMES \
1585 { \
1586 "NO_REGS", \
1587 "M16_NA_REGS", \
1588 "M16_REGS", \
1589 "T_REG", \
1590 "M16_T_REGS", \
1591 "PIC_FN_ADDR_REG", \
1592 "V1_REG", \
1593 "LEA_REGS", \
1594 "GR_REGS", \
1595 "FP_REGS", \
1596 "MD0_REG", \
1597 "MD1_REG", \
1598 "MD_REGS", \
1599 /* coprocessor registers */ \
1600 "COP0_REGS", \
1601 "COP2_REGS", \
1602 "COP3_REGS", \
1603 "HI_AND_GR_REGS", \
1604 "LO_AND_GR_REGS", \
1605 "HI_AND_FP_REGS", \
1606 "COP0_AND_GR_REGS", \
1607 "COP2_AND_GR_REGS", \
1608 "COP3_AND_GR_REGS", \
1609 "ALL_COP_REGS", \
1610 "ALL_COP_AND_GR_REGS", \
1611 "ST_REGS", \
1612 "DSP_ACC_REGS", \
1613 "ACC_REGS", \
1614 "ALL_REGS" \
1615 }
1616
1617 /* An initializer containing the contents of the register classes,
1618 as integers which are bit masks. The Nth integer specifies the
1619 contents of class N. The way the integer MASK is interpreted is
1620 that register R is in the class if `MASK & (1 << R)' is 1.
1621
1622 When the machine has more than 32 registers, an integer does not
1623 suffice. Then the integers are replaced by sub-initializers,
1624 braced groupings containing several integers. Each
1625 sub-initializer must be suitable as an initializer for the type
1626 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1627
1628 #define REG_CLASS_CONTENTS \
1629 { \
1630 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1631 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1632 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1633 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1634 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1635 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1636 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1637 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1638 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1639 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1640 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1641 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1642 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1643 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1644 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1645 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1646 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1647 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1648 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1649 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1650 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1651 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1652 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1653 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1654 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1655 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1656 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1657 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1658 }
1659
1660
1661 /* A C expression whose value is a register class containing hard
1662 register REGNO. In general there is more that one such class;
1663 choose a class which is "minimal", meaning that no smaller class
1664 also contains the register. */
1665
1666 extern const enum reg_class mips_regno_to_class[];
1667
1668 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1669
1670 /* A macro whose definition is the name of the class to which a
1671 valid base register must belong. A base register is one used in
1672 an address which is the register value plus a displacement. */
1673
1674 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1675
1676 /* A macro whose definition is the name of the class to which a
1677 valid index register must belong. An index register is one used
1678 in an address where its value is either multiplied by a scale
1679 factor or added to another register (as well as added to a
1680 displacement). */
1681
1682 #define INDEX_REG_CLASS NO_REGS
1683
1684 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1685 registers explicitly used in the rtl to be used as spill registers
1686 but prevents the compiler from extending the lifetime of these
1687 registers. */
1688
1689 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1690
1691 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1692 is the default value (allocate the registers in numeric order). We
1693 define it just so that we can override it for the mips16 target in
1694 ORDER_REGS_FOR_LOCAL_ALLOC. */
1695
1696 #define REG_ALLOC_ORDER \
1697 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1698 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1699 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1700 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1701 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1702 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1703 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1704 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1705 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1706 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1707 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1708 176,177,178,179,180,181,182,183,184,185,186,187 \
1709 }
1710
1711 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1712 to be rearranged based on a particular function. On the mips16, we
1713 want to allocate $24 (T_REG) before other registers for
1714 instructions for which it is possible. */
1715
1716 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1717
1718 /* True if VALUE is an unsigned 6-bit number. */
1719
1720 #define UIMM6_OPERAND(VALUE) \
1721 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1722
1723 /* True if VALUE is a signed 10-bit number. */
1724
1725 #define IMM10_OPERAND(VALUE) \
1726 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1727
1728 /* True if VALUE is a signed 16-bit number. */
1729
1730 #define SMALL_OPERAND(VALUE) \
1731 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1732
1733 /* True if VALUE is an unsigned 16-bit number. */
1734
1735 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1736 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1737
1738 /* True if VALUE can be loaded into a register using LUI. */
1739
1740 #define LUI_OPERAND(VALUE) \
1741 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1742 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1743
1744 /* Return a value X with the low 16 bits clear, and such that
1745 VALUE - X is a signed 16-bit value. */
1746
1747 #define CONST_HIGH_PART(VALUE) \
1748 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1749
1750 #define CONST_LOW_PART(VALUE) \
1751 ((VALUE) - CONST_HIGH_PART (VALUE))
1752
1753 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1754 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1755 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1756
1757 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1758 mips_preferred_reload_class (X, CLASS)
1759
1760 /* The HI and LO registers can only be reloaded via the general
1761 registers. Condition code registers can only be loaded to the
1762 general registers, and from the floating point registers. */
1763
1764 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1765 mips_secondary_reload_class (CLASS, MODE, X, 1)
1766 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1767 mips_secondary_reload_class (CLASS, MODE, X, 0)
1768
1769 /* Return the maximum number of consecutive registers
1770 needed to represent mode MODE in a register of class CLASS. */
1771
1772 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1773
1774 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1775 mips_cannot_change_mode_class (FROM, TO, CLASS)
1776 \f
1777 /* Stack layout; function entry, exit and calling. */
1778
1779 #define STACK_GROWS_DOWNWARD
1780
1781 /* The offset of the first local variable from the beginning of the frame.
1782 See compute_frame_size for details about the frame layout.
1783
1784 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1785 we assume that we will need 16 bytes of argument space. This is because
1786 the value profiling code may emit calls to cmpdi2 in leaf functions.
1787 Without this hack, the local variables will start at sp+8 and the gp save
1788 area will be at sp+16, and thus they will overlap. compute_frame_size is
1789 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1790 will end up as 24 instead of 8. This won't be needed if profiling code is
1791 inserted before virtual register instantiation. */
1792
1793 #define STARTING_FRAME_OFFSET \
1794 ((flag_profile_values && ! TARGET_64BIT \
1795 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1796 : current_function_outgoing_args_size) \
1797 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1798
1799 #define RETURN_ADDR_RTX mips_return_addr
1800
1801 /* Since the mips16 ISA mode is encoded in the least-significant bit
1802 of the address, mask it off return addresses for purposes of
1803 finding exception handling regions. */
1804
1805 #define MASK_RETURN_ADDR GEN_INT (-2)
1806
1807
1808 /* Similarly, don't use the least-significant bit to tell pointers to
1809 code from vtable index. */
1810
1811 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1812
1813 /* The eliminations to $17 are only used for mips16 code. See the
1814 definition of HARD_FRAME_POINTER_REGNUM. */
1815
1816 #define ELIMINABLE_REGS \
1817 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1818 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1819 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1820 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1821 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1822 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1823
1824 /* We can always eliminate to the hard frame pointer. We can eliminate
1825 to the stack pointer unless a frame pointer is needed.
1826
1827 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1828 reload may be unable to compute the address of a local variable,
1829 since there is no way to add a large constant to the stack pointer
1830 without using a temporary register. */
1831 #define CAN_ELIMINATE(FROM, TO) \
1832 ((TO) == HARD_FRAME_POINTER_REGNUM \
1833 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1834 && (!TARGET_MIPS16 \
1835 || compute_frame_size (get_frame_size ()) < 32768)))
1836
1837 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1838 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1839
1840 /* Allocate stack space for arguments at the beginning of each function. */
1841 #define ACCUMULATE_OUTGOING_ARGS 1
1842
1843 /* The argument pointer always points to the first argument. */
1844 #define FIRST_PARM_OFFSET(FNDECL) 0
1845
1846 /* o32 and o64 reserve stack space for all argument registers. */
1847 #define REG_PARM_STACK_SPACE(FNDECL) \
1848 (TARGET_OLDABI \
1849 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1850 : 0)
1851
1852 /* Define this if it is the responsibility of the caller to
1853 allocate the area reserved for arguments passed in registers.
1854 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1855 of this macro is to determine whether the space is included in
1856 `current_function_outgoing_args_size'. */
1857 #define OUTGOING_REG_PARM_STACK_SPACE 1
1858
1859 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1860 \f
1861 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1862
1863 /* Symbolic macros for the registers used to return integer and floating
1864 point values. */
1865
1866 #define GP_RETURN (GP_REG_FIRST + 2)
1867 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1868
1869 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1870
1871 /* Symbolic macros for the first/last argument registers. */
1872
1873 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1874 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1875 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1876 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1877
1878 #define LIBCALL_VALUE(MODE) \
1879 mips_function_value (NULL_TREE, NULL, (MODE))
1880
1881 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1882 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1883
1884 /* 1 if N is a possible register number for a function value.
1885 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1886 Currently, R2 and F0 are only implemented here (C has no complex type) */
1887
1888 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1889 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1890 && (N) == FP_RETURN + 2))
1891
1892 /* 1 if N is a possible register number for function argument passing.
1893 We have no FP argument registers when soft-float. When FP registers
1894 are 32 bits, we can't directly reference the odd numbered ones. */
1895
1896 #define FUNCTION_ARG_REGNO_P(N) \
1897 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1898 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1899 && !fixed_regs[N])
1900 \f
1901 /* This structure has to cope with two different argument allocation
1902 schemes. Most MIPS ABIs view the arguments as a structure, of which
1903 the first N words go in registers and the rest go on the stack. If I
1904 < N, the Ith word might go in Ith integer argument register or in a
1905 floating-point register. For these ABIs, we only need to remember
1906 the offset of the current argument into the structure.
1907
1908 The EABI instead allocates the integer and floating-point arguments
1909 separately. The first N words of FP arguments go in FP registers,
1910 the rest go on the stack. Likewise, the first N words of the other
1911 arguments go in integer registers, and the rest go on the stack. We
1912 need to maintain three counts: the number of integer registers used,
1913 the number of floating-point registers used, and the number of words
1914 passed on the stack.
1915
1916 We could keep separate information for the two ABIs (a word count for
1917 the standard ABIs, and three separate counts for the EABI). But it
1918 seems simpler to view the standard ABIs as forms of EABI that do not
1919 allocate floating-point registers.
1920
1921 So for the standard ABIs, the first N words are allocated to integer
1922 registers, and function_arg decides on an argument-by-argument basis
1923 whether that argument should really go in an integer register, or in
1924 a floating-point one. */
1925
1926 typedef struct mips_args {
1927 /* Always true for varargs functions. Otherwise true if at least
1928 one argument has been passed in an integer register. */
1929 int gp_reg_found;
1930
1931 /* The number of arguments seen so far. */
1932 unsigned int arg_number;
1933
1934 /* The number of integer registers used so far. For all ABIs except
1935 EABI, this is the number of words that have been added to the
1936 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
1937 unsigned int num_gprs;
1938
1939 /* For EABI, the number of floating-point registers used so far. */
1940 unsigned int num_fprs;
1941
1942 /* The number of words passed on the stack. */
1943 unsigned int stack_words;
1944
1945 /* On the mips16, we need to keep track of which floating point
1946 arguments were passed in general registers, but would have been
1947 passed in the FP regs if this were a 32-bit function, so that we
1948 can move them to the FP regs if we wind up calling a 32-bit
1949 function. We record this information in fp_code, encoded in base
1950 four. A zero digit means no floating point argument, a one digit
1951 means an SFmode argument, and a two digit means a DFmode argument,
1952 and a three digit is not used. The low order digit is the first
1953 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
1954 an SFmode argument. ??? A more sophisticated approach will be
1955 needed if MIPS_ABI != ABI_32. */
1956 int fp_code;
1957
1958 /* True if the function has a prototype. */
1959 int prototype;
1960 } CUMULATIVE_ARGS;
1961
1962 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1963 for a call to a function whose data type is FNTYPE.
1964 For a library call, FNTYPE is 0. */
1965
1966 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1967 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1968
1969 /* Update the data in CUM to advance over an argument
1970 of mode MODE and data type TYPE.
1971 (TYPE is null for libcalls where that information may not be available.) */
1972
1973 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1974 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1975
1976 /* Determine where to put an argument to a function.
1977 Value is zero to push the argument on the stack,
1978 or a hard register in which to store the argument.
1979
1980 MODE is the argument's machine mode.
1981 TYPE is the data type of the argument (as a tree).
1982 This is null for libcalls where that information may
1983 not be available.
1984 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1985 the preceding args and about the function being called.
1986 NAMED is nonzero if this argument is a named parameter
1987 (otherwise it is an extra parameter matching an ellipsis). */
1988
1989 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1990 function_arg( &CUM, MODE, TYPE, NAMED)
1991
1992 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
1993
1994 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1995 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
1996
1997 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
1998 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
1999
2000 /* True if using EABI and varargs can be passed in floating-point
2001 registers. Under these conditions, we need a more complex form
2002 of va_list, which tracks GPR, FPR and stack arguments separately. */
2003 #define EABI_FLOAT_VARARGS_P \
2004 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2005
2006 \f
2007 /* Say that the epilogue uses the return address register. Note that
2008 in the case of sibcalls, the values "used by the epilogue" are
2009 considered live at the start of the called function. */
2010 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2011
2012 /* Treat LOC as a byte offset from the stack pointer and round it up
2013 to the next fully-aligned offset. */
2014 #define MIPS_STACK_ALIGN(LOC) \
2015 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2016
2017 \f
2018 /* Implement `va_start' for varargs and stdarg. */
2019 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2020 mips_va_start (valist, nextarg)
2021 \f
2022 /* Output assembler code to FILE to increment profiler label # LABELNO
2023 for profiling a function entry. */
2024
2025 #define FUNCTION_PROFILER(FILE, LABELNO) \
2026 { \
2027 if (TARGET_MIPS16) \
2028 sorry ("mips16 function profiling"); \
2029 fprintf (FILE, "\t.set\tnoat\n"); \
2030 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2031 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2032 if (!TARGET_NEWABI) \
2033 { \
2034 fprintf (FILE, \
2035 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2036 TARGET_64BIT ? "dsubu" : "subu", \
2037 reg_names[STACK_POINTER_REGNUM], \
2038 reg_names[STACK_POINTER_REGNUM], \
2039 Pmode == DImode ? 16 : 8); \
2040 } \
2041 fprintf (FILE, "\tjal\t_mcount\n"); \
2042 fprintf (FILE, "\t.set\tat\n"); \
2043 }
2044
2045 /* No mips port has ever used the profiler counter word, so don't emit it
2046 or the label for it. */
2047
2048 #define NO_PROFILE_COUNTERS 1
2049
2050 /* Define this macro if the code for function profiling should come
2051 before the function prologue. Normally, the profiling code comes
2052 after. */
2053
2054 /* #define PROFILE_BEFORE_PROLOGUE */
2055
2056 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2057 the stack pointer does not matter. The value is tested only in
2058 functions that have frame pointers.
2059 No definition is equivalent to always zero. */
2060
2061 #define EXIT_IGNORE_STACK 1
2062
2063 \f
2064 /* A C statement to output, on the stream FILE, assembler code for a
2065 block of data that contains the constant parts of a trampoline.
2066 This code should not include a label--the label is taken care of
2067 automatically. */
2068
2069 #define TRAMPOLINE_TEMPLATE(STREAM) \
2070 { \
2071 if (ptr_mode == DImode) \
2072 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2073 else \
2074 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2075 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2076 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2077 if (ptr_mode == DImode) \
2078 { \
2079 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2080 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2081 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2082 } \
2083 else \
2084 { \
2085 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2086 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2087 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2088 } \
2089 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2090 if (ptr_mode == DImode) \
2091 { \
2092 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2093 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2094 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2095 } \
2096 else \
2097 { \
2098 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2099 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2100 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2101 } \
2102 }
2103
2104 /* A C expression for the size in bytes of the trampoline, as an
2105 integer. */
2106
2107 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2108
2109 /* Alignment required for trampolines, in bits. */
2110
2111 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2112
2113 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2114 program and data caches. */
2115
2116 #ifndef CACHE_FLUSH_FUNC
2117 #define CACHE_FLUSH_FUNC "_flush_cache"
2118 #endif
2119
2120 /* A C statement to initialize the variable parts of a trampoline.
2121 ADDR is an RTX for the address of the trampoline; FNADDR is an
2122 RTX for the address of the nested function; STATIC_CHAIN is an
2123 RTX for the static chain value that should be passed to the
2124 function when it is called. */
2125
2126 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2127 { \
2128 rtx func_addr, chain_addr, end_addr; \
2129 \
2130 func_addr = plus_constant (ADDR, 32); \
2131 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2132 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2133 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2134 end_addr = gen_reg_rtx (Pmode); \
2135 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2136 GEN_INT (TRAMPOLINE_SIZE))); \
2137 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2138 }
2139 \f
2140 /* Addressing modes, and classification of registers for them. */
2141
2142 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2143 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2144 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2145
2146 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2147 and check its validity for a certain class.
2148 We have two alternate definitions for each of them.
2149 The usual definition accepts all pseudo regs; the other rejects them all.
2150 The symbol REG_OK_STRICT causes the latter definition to be used.
2151
2152 Most source files want to accept pseudo regs in the hope that
2153 they will get allocated to the class that the insn wants them to be in.
2154 Some source files that are used after register allocation
2155 need to be strict. */
2156
2157 #ifndef REG_OK_STRICT
2158 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2159 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2160 #else
2161 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2162 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2163 #endif
2164
2165 #define REG_OK_FOR_INDEX_P(X) 0
2166
2167 \f
2168 /* Maximum number of registers that can appear in a valid memory address. */
2169
2170 #define MAX_REGS_PER_ADDRESS 1
2171
2172 #ifdef REG_OK_STRICT
2173 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2174 { \
2175 if (mips_legitimate_address_p (MODE, X, 1)) \
2176 goto ADDR; \
2177 }
2178 #else
2179 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2180 { \
2181 if (mips_legitimate_address_p (MODE, X, 0)) \
2182 goto ADDR; \
2183 }
2184 #endif
2185
2186 /* Check for constness inline but use mips_legitimate_address_p
2187 to check whether a constant really is an address. */
2188
2189 #define CONSTANT_ADDRESS_P(X) \
2190 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2191
2192 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2193
2194 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2195 do { \
2196 if (mips_legitimize_address (&(X), MODE)) \
2197 goto WIN; \
2198 } while (0)
2199
2200
2201 /* A C statement or compound statement with a conditional `goto
2202 LABEL;' executed if memory address X (an RTX) can have different
2203 meanings depending on the machine mode of the memory reference it
2204 is used for.
2205
2206 Autoincrement and autodecrement addresses typically have
2207 mode-dependent effects because the amount of the increment or
2208 decrement is the size of the operand being addressed. Some
2209 machines have other mode-dependent addresses. Many RISC machines
2210 have no mode-dependent addresses.
2211
2212 You may assume that ADDR is a valid address for the machine. */
2213
2214 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2215
2216 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2217 'the start of the function that this code is output in'. */
2218
2219 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2220 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2221 asm_fprintf ((FILE), "%U%s", \
2222 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2223 else \
2224 asm_fprintf ((FILE), "%U%s", (NAME))
2225 \f
2226 /* Flag to mark a function decl symbol that requires a long call. */
2227 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2228 #define SYMBOL_REF_LONG_CALL_P(X) \
2229 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2230
2231 /* Specify the machine mode that this machine uses
2232 for the index in the tablejump instruction.
2233 ??? Using HImode in mips16 mode can cause overflow. */
2234 #define CASE_VECTOR_MODE \
2235 (TARGET_MIPS16 ? HImode : ptr_mode)
2236
2237 /* Define as C expression which evaluates to nonzero if the tablejump
2238 instruction expects the table to contain offsets from the address of the
2239 table.
2240 Do not define this if the table should contain absolute addresses. */
2241 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2242
2243 /* Define this as 1 if `char' should by default be signed; else as 0. */
2244 #ifndef DEFAULT_SIGNED_CHAR
2245 #define DEFAULT_SIGNED_CHAR 1
2246 #endif
2247
2248 /* Max number of bytes we can move from memory to memory
2249 in one reasonably fast instruction. */
2250 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2251 #define MAX_MOVE_MAX 8
2252
2253 /* Define this macro as a C expression which is nonzero if
2254 accessing less than a word of memory (i.e. a `char' or a
2255 `short') is no faster than accessing a word of memory, i.e., if
2256 such access require more than one instruction or if there is no
2257 difference in cost between byte and (aligned) word loads.
2258
2259 On RISC machines, it tends to generate better code to define
2260 this as 1, since it avoids making a QI or HI mode register.
2261
2262 But, generating word accesses for -mips16 is generally bad as shifts
2263 (often extended) would be needed for byte accesses. */
2264 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2265
2266 /* Define this to be nonzero if shift instructions ignore all but the low-order
2267 few bits. */
2268 #define SHIFT_COUNT_TRUNCATED 1
2269
2270 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2271 is done just by pretending it is already truncated. */
2272 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2273 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2274
2275
2276 /* Specify the machine mode that pointers have.
2277 After generation of rtl, the compiler makes no further distinction
2278 between pointers and any other objects of this machine mode. */
2279
2280 #ifndef Pmode
2281 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2282 #endif
2283
2284 /* Give call MEMs SImode since it is the "most permissive" mode
2285 for both 32-bit and 64-bit targets. */
2286
2287 #define FUNCTION_MODE SImode
2288
2289 \f
2290 /* The cost of loading values from the constant pool. It should be
2291 larger than the cost of any constant we want to synthesize in-line. */
2292
2293 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2294
2295 /* A C expression for the cost of moving data from a register in
2296 class FROM to one in class TO. The classes are expressed using
2297 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2298 the default; other values are interpreted relative to that.
2299
2300 It is not required that the cost always equal 2 when FROM is the
2301 same as TO; on some machines it is expensive to move between
2302 registers if they are not general registers.
2303
2304 If reload sees an insn consisting of a single `set' between two
2305 hard registers, and if `REGISTER_MOVE_COST' applied to their
2306 classes returns a value of 2, reload does not check to ensure
2307 that the constraints of the insn are met. Setting a cost of
2308 other than 2 will allow reload to verify that the constraints are
2309 met. You should do this if the `movM' pattern's constraints do
2310 not allow such copying. */
2311
2312 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2313 mips_register_move_cost (MODE, FROM, TO)
2314
2315 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2316 (mips_cost->memory_latency \
2317 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2318
2319 /* Define if copies to/from condition code registers should be avoided.
2320
2321 This is needed for the MIPS because reload_outcc is not complete;
2322 it needs to handle cases where the source is a general or another
2323 condition code register. */
2324 #define AVOID_CCMODE_COPIES
2325
2326 /* A C expression for the cost of a branch instruction. A value of
2327 1 is the default; other values are interpreted relative to that. */
2328
2329 #define BRANCH_COST mips_branch_cost
2330 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2331
2332 /* If defined, modifies the length assigned to instruction INSN as a
2333 function of the context in which it is used. LENGTH is an lvalue
2334 that contains the initially computed length of the insn and should
2335 be updated with the correct length of the insn. */
2336 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2337 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2338
2339 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2340 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2341 its operands. */
2342 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2343 "%*" OPCODE "%?\t" OPERANDS "%/"
2344
2345 /* Return the asm template for a call. INSN is the instruction's mnemonic
2346 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2347 of the target.
2348
2349 When generating GOT code without explicit relocation operators,
2350 all calls should use assembly macros. Otherwise, all indirect
2351 calls should use "jr" or "jalr"; we will arrange to restore $gp
2352 afterwards if necessary. Finally, we can only generate direct
2353 calls for -mabicalls by temporarily switching to non-PIC mode. */
2354 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2355 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2356 ? "%*" INSN "\t%" #OPNO "%/" \
2357 : REG_P (OPERANDS[OPNO]) \
2358 ? "%*" INSN "r\t%" #OPNO "%/" \
2359 : TARGET_ABICALLS \
2360 ? (".option\tpic0\n\t" \
2361 "%*" INSN "\t%" #OPNO "%/\n\t" \
2362 ".option\tpic2") \
2363 : "%*" INSN "\t%" #OPNO "%/")
2364 \f
2365 /* Control the assembler format that we output. */
2366
2367 /* Output to assembler file text saying following lines
2368 may contain character constants, extra white space, comments, etc. */
2369
2370 #ifndef ASM_APP_ON
2371 #define ASM_APP_ON " #APP\n"
2372 #endif
2373
2374 /* Output to assembler file text saying following lines
2375 no longer contain unusual constructs. */
2376
2377 #ifndef ASM_APP_OFF
2378 #define ASM_APP_OFF " #NO_APP\n"
2379 #endif
2380
2381 #define REGISTER_NAMES \
2382 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2383 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2384 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2385 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2386 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2387 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2388 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2389 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2390 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2391 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2392 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2393 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2394 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2395 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2396 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2397 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2398 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2399 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2400 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2401 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2402 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2403 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2404 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2405 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2406
2407 /* List the "software" names for each register. Also list the numerical
2408 names for $fp and $sp. */
2409
2410 #define ADDITIONAL_REGISTER_NAMES \
2411 { \
2412 { "$29", 29 + GP_REG_FIRST }, \
2413 { "$30", 30 + GP_REG_FIRST }, \
2414 { "at", 1 + GP_REG_FIRST }, \
2415 { "v0", 2 + GP_REG_FIRST }, \
2416 { "v1", 3 + GP_REG_FIRST }, \
2417 { "a0", 4 + GP_REG_FIRST }, \
2418 { "a1", 5 + GP_REG_FIRST }, \
2419 { "a2", 6 + GP_REG_FIRST }, \
2420 { "a3", 7 + GP_REG_FIRST }, \
2421 { "t0", 8 + GP_REG_FIRST }, \
2422 { "t1", 9 + GP_REG_FIRST }, \
2423 { "t2", 10 + GP_REG_FIRST }, \
2424 { "t3", 11 + GP_REG_FIRST }, \
2425 { "t4", 12 + GP_REG_FIRST }, \
2426 { "t5", 13 + GP_REG_FIRST }, \
2427 { "t6", 14 + GP_REG_FIRST }, \
2428 { "t7", 15 + GP_REG_FIRST }, \
2429 { "s0", 16 + GP_REG_FIRST }, \
2430 { "s1", 17 + GP_REG_FIRST }, \
2431 { "s2", 18 + GP_REG_FIRST }, \
2432 { "s3", 19 + GP_REG_FIRST }, \
2433 { "s4", 20 + GP_REG_FIRST }, \
2434 { "s5", 21 + GP_REG_FIRST }, \
2435 { "s6", 22 + GP_REG_FIRST }, \
2436 { "s7", 23 + GP_REG_FIRST }, \
2437 { "t8", 24 + GP_REG_FIRST }, \
2438 { "t9", 25 + GP_REG_FIRST }, \
2439 { "k0", 26 + GP_REG_FIRST }, \
2440 { "k1", 27 + GP_REG_FIRST }, \
2441 { "gp", 28 + GP_REG_FIRST }, \
2442 { "sp", 29 + GP_REG_FIRST }, \
2443 { "fp", 30 + GP_REG_FIRST }, \
2444 { "ra", 31 + GP_REG_FIRST }, \
2445 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2446 }
2447
2448 /* This is meant to be redefined in the host dependent files. It is a
2449 set of alternative names and regnums for mips coprocessors. */
2450
2451 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2452
2453 /* A C compound statement to output to stdio stream STREAM the
2454 assembler syntax for an instruction operand X. X is an RTL
2455 expression.
2456
2457 CODE is a value that can be used to specify one of several ways
2458 of printing the operand. It is used when identical operands
2459 must be printed differently depending on the context. CODE
2460 comes from the `%' specification that was used to request
2461 printing of the operand. If the specification was just `%DIGIT'
2462 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2463 is the ASCII code for LTR.
2464
2465 If X is a register, this macro should print the register's name.
2466 The names can be found in an array `reg_names' whose type is
2467 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2468
2469 When the machine description has a specification `%PUNCT' (a `%'
2470 followed by a punctuation character), this macro is called with
2471 a null pointer for X and the punctuation character for CODE.
2472
2473 See mips.c for the MIPS specific codes. */
2474
2475 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2476
2477 /* A C expression which evaluates to true if CODE is a valid
2478 punctuation character for use in the `PRINT_OPERAND' macro. If
2479 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2480 punctuation characters (except for the standard one, `%') are
2481 used in this way. */
2482
2483 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2484
2485 /* A C compound statement to output to stdio stream STREAM the
2486 assembler syntax for an instruction operand that is a memory
2487 reference whose address is ADDR. ADDR is an RTL expression. */
2488
2489 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2490
2491
2492 /* A C statement, to be executed after all slot-filler instructions
2493 have been output. If necessary, call `dbr_sequence_length' to
2494 determine the number of slots filled in a sequence (zero if not
2495 currently outputting a sequence), to decide how many no-ops to
2496 output, or whatever.
2497
2498 Don't define this macro if it has nothing to do, but it is
2499 helpful in reading assembly output if the extent of the delay
2500 sequence is made explicit (e.g. with white space).
2501
2502 Note that output routines for instructions with delay slots must
2503 be prepared to deal with not being output as part of a sequence
2504 (i.e. when the scheduling pass is not run, or when no slot
2505 fillers could be found.) The variable `final_sequence' is null
2506 when not processing a sequence, otherwise it contains the
2507 `sequence' rtx being output. */
2508
2509 #define DBR_OUTPUT_SEQEND(STREAM) \
2510 do \
2511 { \
2512 if (set_nomacro > 0 && --set_nomacro == 0) \
2513 fputs ("\t.set\tmacro\n", STREAM); \
2514 \
2515 if (set_noreorder > 0 && --set_noreorder == 0) \
2516 fputs ("\t.set\treorder\n", STREAM); \
2517 \
2518 fputs ("\n", STREAM); \
2519 } \
2520 while (0)
2521
2522
2523 /* How to tell the debugger about changes of source files. */
2524 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2525 mips_output_filename (STREAM, NAME)
2526
2527 /* mips-tfile does not understand .stabd directives. */
2528 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2529 dbxout_begin_stabn_sline (LINE); \
2530 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2531 } while (0)
2532
2533 /* Use .loc directives for SDB line numbers. */
2534 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2535 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2536
2537 /* The MIPS implementation uses some labels for its own purpose. The
2538 following lists what labels are created, and are all formed by the
2539 pattern $L[a-z].*. The machine independent portion of GCC creates
2540 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2541
2542 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2543 $Lb[0-9]+ Begin blocks for MIPS debug support
2544 $Lc[0-9]+ Label for use in s<xx> operation.
2545 $Le[0-9]+ End blocks for MIPS debug support */
2546
2547 #undef ASM_DECLARE_OBJECT_NAME
2548 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2549 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2550
2551 /* Globalizing directive for a label. */
2552 #define GLOBAL_ASM_OP "\t.globl\t"
2553
2554 /* This says how to define a global common symbol. */
2555
2556 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2557
2558 /* This says how to define a local common symbol (i.e., not visible to
2559 linker). */
2560
2561 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2562 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2563 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2564 #endif
2565
2566 /* This says how to output an external. It would be possible not to
2567 output anything and let undefined symbol become external. However
2568 the assembler uses length information on externals to allocate in
2569 data/sdata bss/sbss, thereby saving exec time. */
2570
2571 #undef ASM_OUTPUT_EXTERNAL
2572 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2573 mips_output_external(STREAM,DECL,NAME)
2574
2575 /* This is how to declare a function name. The actual work of
2576 emitting the label is moved to function_prologue, so that we can
2577 get the line number correctly emitted before the .ent directive,
2578 and after any .file directives. Define as empty so that the function
2579 is not declared before the .ent directive elsewhere. */
2580
2581 #undef ASM_DECLARE_FUNCTION_NAME
2582 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2583
2584 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2585 #define FUNCTION_NAME_ALREADY_DECLARED 0
2586 #endif
2587
2588 /* This is how to store into the string LABEL
2589 the symbol_ref name of an internal numbered label where
2590 PREFIX is the class of label and NUM is the number within the class.
2591 This is suitable for output with `assemble_name'. */
2592
2593 #undef ASM_GENERATE_INTERNAL_LABEL
2594 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2595 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2596
2597 /* This is how to output an element of a case-vector that is absolute. */
2598
2599 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2600 fprintf (STREAM, "\t%s\t%sL%d\n", \
2601 ptr_mode == DImode ? ".dword" : ".word", \
2602 LOCAL_LABEL_PREFIX, \
2603 VALUE)
2604
2605 /* This is how to output an element of a case-vector. We can make the
2606 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2607 is supported. */
2608
2609 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2610 do { \
2611 if (TARGET_MIPS16) \
2612 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2613 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2614 else if (TARGET_GPWORD) \
2615 fprintf (STREAM, "\t%s\t%sL%d\n", \
2616 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2617 LOCAL_LABEL_PREFIX, VALUE); \
2618 else if (TARGET_RTP_PIC) \
2619 { \
2620 /* Make the entry relative to the start of the function. */ \
2621 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2622 fprintf (STREAM, "\t%s\t%sL%d-", \
2623 Pmode == DImode ? ".dword" : ".word", \
2624 LOCAL_LABEL_PREFIX, VALUE); \
2625 assemble_name (STREAM, XSTR (fnsym, 0)); \
2626 fprintf (STREAM, "\n"); \
2627 } \
2628 else \
2629 fprintf (STREAM, "\t%s\t%sL%d\n", \
2630 ptr_mode == DImode ? ".dword" : ".word", \
2631 LOCAL_LABEL_PREFIX, VALUE); \
2632 } while (0)
2633
2634 /* When generating MIPS16 code, we want the jump table to be in the text
2635 section so that we can load its address using a PC-relative addition. */
2636 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16
2637
2638 /* This is how to output an assembler line
2639 that says to advance the location counter
2640 to a multiple of 2**LOG bytes. */
2641
2642 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2643 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2644
2645 /* This is how to output an assembler line to advance the location
2646 counter by SIZE bytes. */
2647
2648 #undef ASM_OUTPUT_SKIP
2649 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2650 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2651
2652 /* This is how to output a string. */
2653 #undef ASM_OUTPUT_ASCII
2654 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2655 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2656
2657 /* Output #ident as a in the read-only data section. */
2658 #undef ASM_OUTPUT_IDENT
2659 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2660 { \
2661 const char *p = STRING; \
2662 int size = strlen (p) + 1; \
2663 switch_to_section (readonly_data_section); \
2664 assemble_string (p, size); \
2665 }
2666 \f
2667 /* Default to -G 8 */
2668 #ifndef MIPS_DEFAULT_GVALUE
2669 #define MIPS_DEFAULT_GVALUE 8
2670 #endif
2671
2672 /* Define the strings to put out for each section in the object file. */
2673 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2674 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2675
2676 #undef READONLY_DATA_SECTION_ASM_OP
2677 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2678 \f
2679 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2680 do \
2681 { \
2682 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2683 TARGET_64BIT ? "dsubu" : "subu", \
2684 reg_names[STACK_POINTER_REGNUM], \
2685 reg_names[STACK_POINTER_REGNUM], \
2686 TARGET_64BIT ? "sd" : "sw", \
2687 reg_names[REGNO], \
2688 reg_names[STACK_POINTER_REGNUM]); \
2689 } \
2690 while (0)
2691
2692 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2693 do \
2694 { \
2695 if (! set_noreorder) \
2696 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2697 \
2698 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2699 TARGET_64BIT ? "ld" : "lw", \
2700 reg_names[REGNO], \
2701 reg_names[STACK_POINTER_REGNUM], \
2702 TARGET_64BIT ? "daddu" : "addu", \
2703 reg_names[STACK_POINTER_REGNUM], \
2704 reg_names[STACK_POINTER_REGNUM]); \
2705 \
2706 if (! set_noreorder) \
2707 fprintf (STREAM, "\t.set\treorder\n"); \
2708 } \
2709 while (0)
2710
2711 /* How to start an assembler comment.
2712 The leading space is important (the mips native assembler requires it). */
2713 #ifndef ASM_COMMENT_START
2714 #define ASM_COMMENT_START " #"
2715 #endif
2716 \f
2717 /* Default definitions for size_t and ptrdiff_t. We must override the
2718 definitions from ../svr4.h on mips-*-linux-gnu. */
2719
2720 #undef SIZE_TYPE
2721 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2722
2723 #undef PTRDIFF_TYPE
2724 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2725 \f
2726 #ifndef __mips16
2727 /* Since the bits of the _init and _fini function is spread across
2728 many object files, each potentially with its own GP, we must assume
2729 we need to load our GP. We don't preserve $gp or $ra, since each
2730 init/fini chunk is supposed to initialize $gp, and crti/crtn
2731 already take care of preserving $ra and, when appropriate, $gp. */
2732 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2733 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2734 asm (SECTION_OP "\n\
2735 .set noreorder\n\
2736 bal 1f\n\
2737 nop\n\
2738 1: .cpload $31\n\
2739 .set reorder\n\
2740 jal " USER_LABEL_PREFIX #FUNC "\n\
2741 " TEXT_SECTION_ASM_OP);
2742 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2743 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2744 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2745 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2746 asm (SECTION_OP "\n\
2747 .set noreorder\n\
2748 bal 1f\n\
2749 nop\n\
2750 1: .set reorder\n\
2751 .cpsetup $31, $2, 1b\n\
2752 jal " USER_LABEL_PREFIX #FUNC "\n\
2753 " TEXT_SECTION_ASM_OP);
2754 #endif
2755 #endif
2756
2757 #ifndef HAVE_AS_TLS
2758 #define HAVE_AS_TLS 0
2759 #endif
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