| blob | 95317738b0cd9be21753269f50b833455a283543 |
1 /* Definitions of target machine for GNU compiler for Hitachi Super-H.
2 Copyright (C) 1993-1998, 1999 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 #define TARGET_VERSION \
27 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
28 include it here, because hconfig.h is also included by gencodes.c . */
31 /* Generate SDB debugging information. */
33 #define SDB_DEBUGGING_INFO
35 /* Output DBX (stabs) debugging information if doing -gstabs. */
42 %{m1:-D__sh1__} \
43 %{m2:-D__sh2__} \
44 %{m3:-D__sh3__} \
45 %{m3e:-D__SH3E__} \
46 %{m4-single-only:-D__SH4_SINGLE_ONLY__} \
47 %{m4-single:-D__SH4_SINGLE__} \
48 %{m4:-D__SH4__} \
49 %{!m1:%{!m2:%{!m3:%{!m3e:%{!m4:%{!m4-single:%{!m4-single-only:-D__sh1__}}}}}}} \
50 %{mhitachi:-D__HITACHI__}"
58 /* We can not debug without a frame pointer. */
59 /* #define CAN_DEBUG_WITHOUT_FP */
61 #define CONDITIONAL_REGISTER_USAGE \
62 if (! TARGET_SH4 || ! TARGET_FMOVD) \
63 { \
64 int regno; \
65 for (regno = FIRST_XD_REG; regno <= LAST_XD_REG; regno++) \
66 fixed_regs[regno] = call_used_regs[regno] = 1; \
67 if (! TARGET_SH4) \
68 { \
69 if (! TARGET_SH3E) \
70 { \
71 int regno; \
72 for (regno = FIRST_FP_REG; regno <= LAST_FP_REG; regno++) \
73 fixed_regs[regno] = call_used_regs[regno] = 1; \
74 fixed_regs[FPUL_REG] = call_used_regs[FPUL_REG] = 1; \
75 } \
76 } \
77 } \
79 if (TARGET_HITACHI) \
80 { \
81 call_used_regs[MACH_REG] = 0; \
82 call_used_regs[MACL_REG] = 0; \
83 }
84 \f
85 /* ??? Need to write documentation for all SH options and add it to the
86 invoke.texi file. */
88 /* Run-time compilation parameters selecting different hardware subsets. */
91 #define ISIZE_BIT (1<<1)
92 #define DALIGN_BIT (1<<6)
93 #define SH1_BIT (1<<8)
94 #define SH2_BIT (1<<9)
95 #define SH3_BIT (1<<10)
96 #define SH3E_BIT (1<<11)
97 #define HARD_SH4_BIT (1<<5)
98 #define FPU_SINGLE_BIT (1<<7)
99 #define SH4_BIT (1<<12)
100 #define FMOVD_BIT (1<<4)
101 #define SPACE_BIT (1<<13)
102 #define BIGTABLE_BIT (1<<14)
103 #define RELAX_BIT (1<<15)
104 #define HITACHI_BIT (1<<22)
105 #define PADSTRUCT_BIT (1<<28)
106 #define LITTLE_ENDIAN_BIT (1<<29)
107 #define IEEE_BIT (1<<30)
109 /* Nonzero if we should dump out instruction size info. */
110 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
112 /* Nonzero to align doubles on 64 bit boundaries. */
113 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
115 /* Nonzero if we should generate code using type 1 insns. */
116 #define TARGET_SH1 (target_flags & SH1_BIT)
118 /* Nonzero if we should generate code using type 2 insns. */
119 #define TARGET_SH2 (target_flags & SH2_BIT)
121 /* Nonzero if we should generate code using type 3 insns. */
122 #define TARGET_SH3 (target_flags & SH3_BIT)
124 /* Nonzero if we should generate code using type 3E insns. */
125 #define TARGET_SH3E (target_flags & SH3E_BIT)
127 /* Nonzero if the cache line size is 32. */
128 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT)
130 /* Nonzero if we schedule for a superscalar implementation. */
131 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
133 /* Nonzero if the target has separate instruction and data caches. */
134 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
136 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
137 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
139 /* Nonzero if the default precision of th FPU is single */
140 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
142 /* Nonzero if we should generate code using type 4 insns. */
143 #define TARGET_SH4 (target_flags & SH4_BIT)
145 /* Nonzero if we should generate fmovd. */
146 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
148 /* Nonzero if we respect NANs. */
149 #define TARGET_IEEE (target_flags & IEEE_BIT)
151 /* Nonzero if we should generate smaller code rather than faster code. */
152 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
154 /* Nonzero to use long jump tables. */
155 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
157 /* Nonzero to generate pseudo-ops needed by the assembler and linker
158 to do function call relaxing. */
159 #define TARGET_RELAX (target_flags & RELAX_BIT)
161 /* Nonzero if using Hitachi's calling convention. */
162 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
164 /* Nonzero if padding structures to a multiple of 4 bytes. This is
165 incompatible with Hitachi's compiler, and gives unusual structure layouts
166 which confuse programmers.
167 ??? This option is not useful, but is retained in case there are people
168 who are still relying on it. It may be deleted in the future. */
169 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
171 /* Nonzero if generating code for a little endian SH. */
172 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
174 #define TARGET_SWITCHES \
194 SUBTARGET_SWITCHES \
196 }
198 /* This are meant to be redefined in the host dependent files */
199 #define SUBTARGET_SWITCHES
201 #define TARGET_DEFAULT (0)
203 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
204 do { \
205 if (LEVEL) \
206 flag_omit_frame_pointer = -1; \
207 if (LEVEL) \
208 sh_flag_remove_dead_before_cse = 1; \
209 if (SIZE) \
210 target_flags |= SPACE_BIT; \
211 } while (0)
213 #define ASSEMBLER_DIALECT assembler_dialect
217 #define OVERRIDE_OPTIONS \
218 do { \
219 sh_cpu = CPU_SH1; \
220 assembler_dialect = 0; \
221 if (TARGET_SH2) \
222 sh_cpu = CPU_SH2; \
223 if (TARGET_SH3) \
224 sh_cpu = CPU_SH3; \
225 if (TARGET_SH3E) \
226 sh_cpu = CPU_SH3E; \
227 if (TARGET_SH4) \
228 { \
229 assembler_dialect = 1; \
230 sh_cpu = CPU_SH4; \
231 } \
232 if (! TARGET_SH4 || ! TARGET_FMOVD) \
233 { \
234 /* Prevent usage of explicit register names for variables \
235 for registers not present / not addressable in the \
237 int regno; \
238 for (regno = (TARGET_SH3E) ? 17 : 0; \
239 regno <= 24; regno++) \
240 fp_reg_names[regno][0] = 0; \
241 } \
242 if (flag_omit_frame_pointer < 0) \
243 /* The debugging information is sufficient, \
245 if (0) \
246 flag_omit_frame_pointer \
247 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
248 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
249 else \
250 flag_omit_frame_pointer = 0; \
251 \
252 /* Never run scheduling before reload, since that can \
253 break global alloc, and generates slower code anyway due \
255 flag_schedule_insns = 0; \
256 sh_addr_diff_vec_mode = TARGET_BIGTABLE ? SImode : HImode; \
257 } while (0)
258 \f
259 /* Target machine storage layout. */
261 /* Define to use software floating point emulator for REAL_ARITHMETIC and
262 decimal <-> binary conversion. */
263 #define REAL_ARITHMETIC
265 /* Define this if most significant bit is lowest numbered
266 in instructions that operate on numbered bit-fields. */
268 #define BITS_BIG_ENDIAN 0
270 /* Define this if most significant byte of a word is the lowest numbered. */
271 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
273 /* Define this if most significant word of a multiword number is the lowest
274 numbered. */
275 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
277 /* Define this to set the endianness to use in libgcc2.c, which can
278 not depend on target_flags. */
279 #if defined(__LITTLE_ENDIAN__)
280 #define LIBGCC2_WORDS_BIG_ENDIAN 0
281 #else
282 #define LIBGCC2_WORDS_BIG_ENDIAN 1
283 #endif
285 /* Number of bits in an addressable storage unit. */
286 #define BITS_PER_UNIT 8
288 /* Width in bits of a "word", which is the contents of a machine register.
289 Note that this is not necessarily the width of data type `int';
290 if using 16-bit ints on a 68000, this would still be 32.
291 But on a machine with 16-bit registers, this would be 16. */
292 #define BITS_PER_WORD 32
293 #define MAX_BITS_PER_WORD 32
295 /* Width of a word, in units (bytes). */
296 #define UNITS_PER_WORD 4
298 /* Width in bits of a pointer.
299 See also the macro `Pmode' defined below. */
300 #define POINTER_SIZE 32
302 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
303 #define PARM_BOUNDARY 32
305 /* Boundary (in *bits*) on which stack pointer should be aligned. */
306 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
308 /* The log (base 2) of the cache line size, in bytes. Processors prior to
309 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
310 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
311 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
313 /* Allocation boundary (in *bits*) for the code of a function.
314 32 bit alignment is faster, because instructions are always fetched as a
315 pair from a longword boundary. */
316 #define FUNCTION_BOUNDARY (TARGET_SMALLCODE ? 16 : (1 << CACHE_LOG) * 8)
318 /* Alignment of field after `int : 0' in a structure. */
319 #define EMPTY_FIELD_BOUNDARY 32
321 /* No data type wants to be aligned rounder than this. */
322 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
324 /* The best alignment to use in cases where we have a choice. */
325 #define FASTEST_ALIGNMENT 32
327 /* Make strings word-aligned so strcpy from constants will be faster. */
328 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
329 ((TREE_CODE (EXP) == STRING_CST \
330 && (ALIGN) < FASTEST_ALIGNMENT) \
331 ? FASTEST_ALIGNMENT : (ALIGN))
333 #ifndef MAX_OFILE_ALIGNMENT
334 #define MAX_OFILE_ALIGNMENT 128
335 #endif
337 /* Make arrays of chars word-aligned for the same reasons. */
338 #define DATA_ALIGNMENT(TYPE, ALIGN) \
339 (TREE_CODE (TYPE) == ARRAY_TYPE \
340 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
341 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
343 /* Number of bits which any structure or union's size must be a
344 multiple of. Each structure or union's size is rounded up to a
345 multiple of this. */
346 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
348 /* Set this nonzero if move instructions will actually fail to work
349 when given unaligned data. */
350 #define STRICT_ALIGNMENT 1
352 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
353 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
354 barrier_align (LABEL_AFTER_BARRIER)
356 #define LOOP_ALIGN(A_LABEL) \
357 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) ? 0 : 2)
359 #define LABEL_ALIGN(A_LABEL) \
360 ( \
361 (PREV_INSN (A_LABEL) \
362 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
363 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
364 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == 1) \
366 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
367 : 0)
369 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
370 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
372 /* The base two logarithm of the known minimum alignment of an insn length. */
373 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
374 (GET_CODE (A_INSN) == INSN \
375 ? 1 \
376 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
377 ? 1 \
378 : CACHE_LOG)
379 \f
380 /* Standard register usage. */
382 /* Register allocation for the Hitachi calling convention:
384 r0 arg return
385 r1..r3 scratch
386 r4..r7 args in
387 r8..r13 call saved
388 r14 frame pointer/call saved
389 r15 stack pointer
390 ap arg pointer (doesn't really exist, always eliminated)
391 pr subroutine return address
392 t t bit
393 mach multiply/accumulate result, high part
394 macl multiply/accumulate result, low part.
395 fpul fp/int communication register
396 rap return address pointer register
397 fr0 fp arg return
398 fr1..fr3 scratch floating point registers
399 fr4..fr11 fp args in
400 fr12..fr15 call saved floating point registers */
402 /* Number of actual hardware registers.
403 The hardware registers are assigned numbers for the compiler
404 from 0 to just below FIRST_PSEUDO_REGISTER.
405 All registers that the compiler knows about must be given numbers,
406 even those that are not normally considered general registers. */
408 #define AP_REG 16
409 #define PR_REG 17
410 #define T_REG 18
411 #define GBR_REG 19
412 #define MACH_REG 20
413 #define MACL_REG 21
414 #define SPECIAL_REG(REGNO) ((REGNO) >= 18 && (REGNO) <= 21)
415 #define FPUL_REG 22
416 #define RAP_REG 23
417 #define FIRST_FP_REG 24
418 #define LAST_FP_REG 39
419 #define FIRST_XD_REG 40
420 #define LAST_XD_REG 47
421 #define FPSCR_REG 48
423 #define FIRST_PSEUDO_REGISTER 49
425 /* 1 for registers that have pervasive standard uses
426 and are not available for the register allocator.
428 Mach register is fixed 'cause it's only 10 bits wide for SH1.
429 It is 32 bits wide for SH2. */
431 #define FIXED_REGISTERS \
432 { 0, 0, 0, 0, \
433 0, 0, 0, 0, \
434 0, 0, 0, 0, \
435 0, 0, 0, 1, \
436 1, 1, 1, 1, \
437 1, 1, 0, 1, \
438 0, 0, 0, 0, \
439 0, 0, 0, 0, \
440 0, 0, 0, 0, \
441 0, 0, 0, 0, \
442 0, 0, 0, 0, \
443 0, 0, 0, 0, \
444 1, \
445 }
447 /* 1 for registers not available across function calls.
448 These must include the FIXED_REGISTERS and also any
449 registers that can be used without being saved.
450 The latter must include the registers where values are returned
451 and the register where structure-value addresses are passed.
452 Aside from that, you can include as many other registers as you like. */
454 #define CALL_USED_REGISTERS \
455 { 1, 1, 1, 1, \
456 1, 1, 1, 1, \
457 0, 0, 0, 0, \
458 0, 0, 0, 1, \
459 1, 0, 1, 1, \
460 1, 1, 1, 1, \
461 1, 1, 1, 1, \
462 1, 1, 1, 1, \
463 1, 1, 1, 1, \
464 0, 0, 0, 0, \
465 1, 1, 1, 1, \
466 1, 1, 0, 0, \
467 1, \
468 }
470 /* Return number of consecutive hard regs needed starting at reg REGNO
471 to hold something of mode MODE.
472 This is ordinarily the length in words of a value of mode MODE
473 but can be less for certain modes in special long registers.
475 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
477 #define HARD_REGNO_NREGS(REGNO, MODE) \
478 ((REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \
479 ? (GET_MODE_SIZE (MODE) / (2 * UNITS_PER_WORD)) \
480 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
482 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
483 We can allow any mode in any general register. The special registers
484 only allow SImode. Don't allow any mode in the PR. */
486 /* We cannot hold DCmode values in the XD registers because alter_reg
487 handles subregs of them incorrectly. We could work around this by
488 spacing the XD registers like the DR registers, but this would require
489 additional memory in every compilation to hold larger register vectors.
490 We could hold SFmode / SCmode values in XD registers, but that
491 would require a tertiary reload when reloading from / to memory,
492 and a secondary reload to reload from / to general regs; that
493 seems to be a loosing proposition. */
494 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
495 (SPECIAL_REG (REGNO) ? (MODE) == SImode \
496 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
497 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG && (MODE) == SFmode \
498 ? 1 \
499 : (REGNO) >= FIRST_FP_REG && (REGNO) <= LAST_FP_REG \
500 ? ((MODE) == SFmode \
501 || (TARGET_SH3E && (MODE) == SCmode) \
502 || (((TARGET_SH4 && (MODE) == DFmode) || (MODE) == DCmode) \
503 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
504 : (REGNO) >= FIRST_XD_REG && (REGNO) <= LAST_XD_REG \
505 ? (MODE) == DFmode \
506 : (REGNO) == PR_REG ? 0 \
507 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
508 : 1)
510 /* Value is 1 if it is a good idea to tie two pseudo registers
511 when one has mode MODE1 and one has mode MODE2.
512 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
513 for any hard reg, then this must be 0 for correct output. */
515 #define MODES_TIEABLE_P(MODE1, MODE2) \
516 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
518 /* Specify the registers used for certain standard purposes.
519 The values of these macros are register numbers. */
521 /* Define this if the program counter is overloaded on a register. */
522 /* #define PC_REGNUM 15*/
524 /* Register to use for pushing function arguments. */
525 #define STACK_POINTER_REGNUM 15
527 /* Base register for access to local variables of the function. */
528 #define FRAME_POINTER_REGNUM 14
530 /* Fake register that holds the address on the stack of the
531 current function's return address. */
532 #define RETURN_ADDRESS_POINTER_REGNUM 23
534 /* Value should be nonzero if functions must have frame pointers.
535 Zero means the frame pointer need not be set up (and parms may be accessed
536 via the stack pointer) in functions that seem suitable. */
538 #define FRAME_POINTER_REQUIRED 0
540 /* Definitions for register eliminations.
542 We have three registers that can be eliminated on the SH. First, the
543 frame pointer register can often be eliminated in favor of the stack
544 pointer register. Secondly, the argument pointer register can always be
545 eliminated; it is replaced with either the stack or frame pointer.
546 Third, there is the return address pointer, which can also be replaced
547 with either the stack or the frame pointer. */
549 /* This is an array of structures. Each structure initializes one pair
550 of eliminable registers. The "from" register number is given first,
551 followed by "to". Eliminations of the same "from" register are listed
552 in order of preference. */
554 /* If you add any registers here that are not actually hard registers,
555 and that have any alternative of elimination that doesn't always
556 apply, you need to amend calc_live_regs to exclude it, because
557 reload spills all eliminable registers where it sees an
558 can_eliminate == 0 entry, thus making them 'live' .
559 If you add any hard registers that can be eliminated in different
560 ways, you have to patch reload to spill them only when all alternatives
561 of elimination fail. */
563 #define ELIMINABLE_REGS \
564 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
565 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
566 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
567 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
568 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
570 /* Given FROM and TO register numbers, say whether this elimination
571 is allowed. */
572 #define CAN_ELIMINATE(FROM, TO) \
573 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
575 /* Define the offset between two registers, one to be eliminated, and the other
576 its replacement, at the start of a routine. */
578 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
579 OFFSET = initial_elimination_offset ((FROM), (TO))
581 /* Base register for access to arguments of the function. */
582 #define ARG_POINTER_REGNUM 16
584 /* Register in which the static-chain is passed to a function. */
585 #define STATIC_CHAIN_REGNUM 13
587 /* The register in which a struct value address is passed. */
589 #define STRUCT_VALUE_REGNUM 2
591 /* If the structure value address is not passed in a register, define
592 `STRUCT_VALUE' as an expression returning an RTX for the place
593 where the address is passed. If it returns 0, the address is
594 passed as an "invisible" first argument. */
596 /*#define STRUCT_VALUE ((rtx)0)*/
598 /* Don't default to pcc-struct-return, because we have already specified
599 exactly how to return structures in the RETURN_IN_MEMORY macro. */
601 #define DEFAULT_PCC_STRUCT_RETURN 0
602 \f
603 /* Define the classes of registers for register constraints in the
604 machine description. Also define ranges of constants.
606 One of the classes must always be named ALL_REGS and include all hard regs.
607 If there is more than one class, another class must be named NO_REGS
608 and contain no registers.
610 The name GENERAL_REGS must be the name of a class (or an alias for
611 another name such as ALL_REGS). This is the class of registers
612 that is allowed by "g" or "r" in a register constraint.
613 Also, registers outside this class are allocated only when
614 instructions express preferences for them.
616 The classes must be numbered in nondecreasing order; that is,
617 a larger-numbered class must never be contained completely
618 in a smaller-numbered class.
620 For any two classes, it is very desirable that there be another
621 class that represents their union. */
623 /* The SH has two sorts of general registers, R0 and the rest. R0 can
624 be used as the destination of some of the arithmetic ops. There are
625 also some special purpose registers; the T bit register, the
626 Procedure Return Register and the Multiply Accumulate Registers. */
627 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
628 reg_class_subunion. We don't want to have an actual union class
629 of these, because it would only be used when both classes are calculated
630 to give the same cost, but there is only one FPUL register.
631 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
632 applying to the actual instruction alternative considered. E.g., the
633 y/r alternative of movsi_ie is considered to have no more cost that
634 the r/r alternative, which is patently untrue. */
636 enum reg_class
637 {
638 NO_REGS,
639 R0_REGS,
640 PR_REGS,
641 T_REGS,
642 MAC_REGS,
643 FPUL_REGS,
644 GENERAL_REGS,
645 FP0_REGS,
646 FP_REGS,
647 DF_REGS,
648 FPSCR_REGS,
649 GENERAL_FP_REGS,
650 ALL_REGS,
651 LIM_REG_CLASSES
652 };
654 #define N_REG_CLASSES (int) LIM_REG_CLASSES
656 /* Give names of register classes as strings for dump file. */
657 #define REG_CLASS_NAMES \
658 { \
672 }
674 /* Define which registers fit in which classes.
675 This is an initializer for a vector of HARD_REG_SET
676 of length N_REG_CLASSES. */
678 #define REG_CLASS_CONTENTS \
679 { \
693 }
695 /* The same information, inverted:
696 Return the class number of the smallest class containing
697 reg number REGNO. This could be a conditional expression
698 or could index an array. */
701 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
703 /* When defined, the compiler allows registers explicitly used in the
704 rtl to be used as spill registers but prevents the compiler from
705 extending the lifetime of these registers. */
707 #define SMALL_REGISTER_CLASSES 1
709 /* The order in which register should be allocated. */
710 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
711 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
712 spilled or used otherwise, we better have the FP_REGS allocated first. */
713 #define REG_ALLOC_ORDER \
714 { 25,26,27,28,29,30,31,24,32,33,34,35,36,37,38,39, \
715 40,41,42,43,44,45,46,47,48, \
716 1,2,3,7,6,5,4,0,8,9,10,11,12,13,14, \
717 22,15,16,17,18,19,20,21,23 }
719 /* The class value for index registers, and the one for base regs. */
720 #define INDEX_REG_CLASS R0_REGS
721 #define BASE_REG_CLASS GENERAL_REGS
723 /* Get reg_class from a letter such as appears in the machine
724 description. */
727 #define REG_CLASS_FROM_LETTER(C) \
729 \f
730 /* The letters I, J, K, L and M in a register constraint string
731 can be used to stand for particular ranges of immediate operands.
732 This macro defines what the ranges are.
733 C is the letter, and VALUE is a constant value.
734 Return 1 if VALUE is in the range specified by C.
735 I: arithmetic operand -127..128, as used in add, sub, etc
736 K: shift operand 1,2,8 or 16
737 L: logical operand 0..255, as used in and, or, etc.
738 M: constant 1
739 N: constant 0 */
741 #define CONST_OK_FOR_I(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
742 && ((HOST_WIDE_INT)(VALUE)) <= 127)
743 #define CONST_OK_FOR_K(VALUE) ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
744 #define CONST_OK_FOR_L(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
745 && ((HOST_WIDE_INT)(VALUE)) <= 255)
746 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
747 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
748 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
754 : 0)
756 /* Similar, but for floating constants, and defining letters G and H.
757 Here VALUE is the CONST_DOUBLE rtx itself. */
759 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
764 /* Given an rtx X being reloaded into a reg required to be
765 in class CLASS, return the class of reg to actually use.
766 In general this is just CLASS; but on some machines
767 in some cases it is preferable to use a more restrictive class. */
769 #define PREFERRED_RELOAD_CLASS(X, CLASS) (CLASS)
771 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
772 ((((((CLASS) == FP_REGS || (CLASS) == FP0_REGS \
773 || (CLASS) == DF_REGS) \
774 && (GET_CODE (X) == REG && REGNO (X) <= AP_REG)) \
775 || (((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS) \
776 && GET_CODE (X) == REG \
777 && REGNO (X) >= FIRST_FP_REG && REGNO (X) <= LAST_FP_REG)) \
778 && MODE == SFmode) \
779 ? FPUL_REGS \
780 : ((CLASS) == FPUL_REGS \
781 && (GET_CODE (X) == MEM \
782 || (GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER)))\
783 ? GENERAL_REGS \
784 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
785 && GET_CODE (X) == REG && REGNO (X) > 15 \
786 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
787 ? GENERAL_REGS : NO_REGS)
789 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
790 ((((CLASS) == FP_REGS || (CLASS) == FP0_REGS || (CLASS) == DF_REGS) \
791 && immediate_operand ((X), (MODE)) \
792 && ! ((fp_zero_operand (X) || fp_one_operand (X)) && (MODE) == SFmode))\
793 ? R0_REGS \
794 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
795 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I (INTVAL (X)) \
796 ? GENERAL_REGS \
797 : R0_REGS) \
798 : (CLASS == FPSCR_REGS \
799 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
800 || GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)) \
801 ? GENERAL_REGS \
802 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
804 /* Return the maximum number of consecutive registers
805 needed to represent mode MODE in a register of class CLASS.
807 On SH this is the size of MODE in words. */
808 #define CLASS_MAX_NREGS(CLASS, MODE) \
809 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
811 /* If defined, gives a class of registers that cannot be used as the
812 operand of a SUBREG that changes the size of the object. */
814 #define CLASS_CANNOT_CHANGE_SIZE DF_REGS
815 \f
816 /* Stack layout; function entry, exit and calling. */
818 /* Define the number of registers that can hold parameters.
819 These macros are used only in other macro definitions below. */
821 #define NPARM_REGS(MODE) \
822 (TARGET_SH3E && (MODE) == SFmode \
823 ? 8 \
824 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
825 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
826 ? 8 \
827 : 4)
829 #define FIRST_PARM_REG 4
830 #define FIRST_RET_REG 0
832 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4)
833 #define FIRST_FP_RET_REG FIRST_FP_REG
835 /* Define this if pushing a word on the stack
836 makes the stack pointer a smaller address. */
837 #define STACK_GROWS_DOWNWARD
839 /* Define this macro if the addresses of local variable slots are at
840 negative offsets from the frame pointer.
842 The SH only has positive indexes, so grow the frame up. */
843 /* #define FRAME_GROWS_DOWNWARD */
845 /* Offset from the frame pointer to the first local variable slot to
846 be allocated. */
847 #define STARTING_FRAME_OFFSET 0
849 /* If we generate an insn to push BYTES bytes,
850 this says how many the stack pointer really advances by. */
851 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
852 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
853 do correct alignment. */
854 #if 0
855 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
856 #endif
858 /* Offset of first parameter from the argument pointer register value. */
859 #define FIRST_PARM_OFFSET(FNDECL) 0
861 /* Value is the number of byte of arguments automatically
862 popped when returning from a subroutine call.
863 FUNDECL is the declaration node of the function (as a tree),
864 FUNTYPE is the data type of the function (as a tree),
865 or for a library call it is an identifier node for the subroutine name.
866 SIZE is the number of bytes of arguments passed on the stack.
868 On the SH, the caller does not pop any of its arguments that were passed
869 on the stack. */
870 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
872 /* Nonzero if we do not know how to pass TYPE solely in registers.
873 Values that come in registers with inconvenient padding are stored
874 to memory at the function start. */
876 #define MUST_PASS_IN_STACK(MODE,TYPE) \
877 ((TYPE) != 0 \
878 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
879 || TREE_ADDRESSABLE (TYPE)))
880 /* Some subroutine macros specific to this machine. */
882 #define BASE_RETURN_VALUE_REG(MODE) \
883 ((TARGET_SH3E && ((MODE) == SFmode)) \
884 ? FIRST_FP_RET_REG \
885 : TARGET_SH3E && (MODE) == SCmode \
886 ? FIRST_FP_RET_REG \
887 : (TARGET_SH4 \
888 && ((MODE) == DFmode || (MODE) == SFmode \
889 || (MODE) == DCmode || (MODE) == SCmode )) \
890 ? FIRST_FP_RET_REG \
891 : FIRST_RET_REG)
893 #define BASE_ARG_REG(MODE) \
894 ((TARGET_SH3E && ((MODE) == SFmode)) \
895 ? FIRST_FP_PARM_REG \
896 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
897 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
898 ? FIRST_FP_PARM_REG \
899 : FIRST_PARM_REG)
901 /* Define how to find the value returned by a function.
902 VALTYPE is the data type of the value (as a tree).
903 If the precise function being called is known, FUNC is its FUNCTION_DECL;
904 otherwise, FUNC is 0.
905 For the SH, this is like LIBCALL_VALUE, except that we must change the
906 mode like PROMOTE_MODE does.
907 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
908 tested here has to be kept in sync with the one in explow.c:promote_mode. */
910 #define FUNCTION_VALUE(VALTYPE, FUNC) \
911 gen_rtx (REG, \
912 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
913 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
914 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
915 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
916 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
917 || TREE_CODE (VALTYPE) == CHAR_TYPE \
918 || TREE_CODE (VALTYPE) == REAL_TYPE \
919 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
920 ? SImode : TYPE_MODE (VALTYPE)), \
921 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
923 /* Define how to find the value returned by a library function
924 assuming the value has mode MODE. */
925 #define LIBCALL_VALUE(MODE) \
926 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
928 /* 1 if N is a possible register number for a function value. */
929 #define FUNCTION_VALUE_REGNO_P(REGNO) \
930 ((REGNO) == FIRST_RET_REG || (TARGET_SH3E && (REGNO) == FIRST_FP_RET_REG))
932 /* 1 if N is a possible register number for function argument passing. */
933 #define FUNCTION_ARG_REGNO_P(REGNO) \
934 (((REGNO) >= FIRST_PARM_REG && (REGNO) < (FIRST_PARM_REG + 4)) \
935 || (TARGET_SH3E \
936 && (REGNO) >= FIRST_FP_PARM_REG && (REGNO) < (FIRST_FP_PARM_REG + 8)))
937 \f
938 /* Define a data type for recording info about an argument list
939 during the scan of that argument list. This data type should
940 hold all necessary information about the function itself
941 and about the args processed so far, enough to enable macros
942 such as FUNCTION_ARG to determine where the next arg should go.
944 On SH, this is a single integer, which is a number of words
945 of arguments scanned so far (including the invisible argument,
946 if any, which holds the structure-value-address).
947 Thus NARGREGS or more means all following args should go on the stack. */
952 };
954 #define CUMULATIVE_ARGS struct sh_args
956 #define GET_SH_ARG_CLASS(MODE) \
957 ((TARGET_SH3E && (MODE) == SFmode) \
958 ? SH_ARG_FLOAT \
959 : TARGET_SH4 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
960 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
961 ? SH_ARG_FLOAT : SH_ARG_INT)
963 #define ROUND_ADVANCE(SIZE) \
964 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
966 /* Round a register number up to a proper boundary for an arg of mode
967 MODE.
969 The SH doesn't care about double alignment, so we only
970 round doubles to even regs when asked to explicitly. */
972 #define ROUND_REG(CUM, MODE) \
973 (((TARGET_ALIGN_DOUBLE \
974 || (TARGET_SH4 && ((MODE) == DFmode || (MODE) == DCmode) \
975 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
976 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
977 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
978 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
979 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
981 /* Initialize a variable CUM of type CUMULATIVE_ARGS
982 for a call to a function whose data type is FNTYPE.
983 For a library call, FNTYPE is 0.
985 On SH, the offset always starts at 0: the first parm reg is always
986 the same reg for a given argument class. */
988 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
989 do { \
990 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
991 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
992 } while (0)
994 /* Update the data in CUM to advance over an argument
995 of mode MODE and data type TYPE.
996 (TYPE is null for libcalls where that information may not be
997 available.) */
999 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1000 if (! TARGET_SH4 || PASS_IN_REG_P ((CUM), (MODE), (TYPE))) \
1001 ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1002 = (ROUND_REG ((CUM), (MODE)) \
1003 + ((MODE) == BLKmode \
1004 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1005 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))))
1007 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1008 This macro is only used in this file. */
1010 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1011 (((TYPE) == 0 \
1012 || (! TREE_ADDRESSABLE ((tree)(TYPE))) \
1013 && (! TARGET_HITACHI || ! AGGREGATE_TYPE_P (TYPE))) \
1014 && (TARGET_SH3E \
1015 ? ((MODE) == BLKmode \
1016 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1017 + int_size_in_bytes (TYPE)) \
1018 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1019 : ((ROUND_REG((CUM), (MODE)) \
1020 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1021 <= NPARM_REGS (MODE))) \
1022 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1024 /* Define where to put the arguments to a function.
1025 Value is zero to push the argument on the stack,
1026 or a hard register in which to store the argument.
1028 MODE is the argument's machine mode.
1029 TYPE is the data type of the argument (as a tree).
1030 This is null for libcalls where that information may
1031 not be available.
1032 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1033 the preceding args and about the function being called.
1034 NAMED is nonzero if this argument is a named parameter
1035 (otherwise it is an extra parameter matching an ellipsis).
1037 On SH the first args are normally in registers
1038 and the rest are pushed. Any arg that starts within the first
1039 NPARM_REGS words is at least partially passed in a register unless
1040 its data type forbids. */
1042 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1043 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1044 && ((NAMED) \
1045 || (! TARGET_HITACHI && (TARGET_SH3E || ! current_function_varargs)))) \
1046 ? gen_rtx_REG ((MODE), \
1047 ((BASE_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))) \
1048 ^ ((MODE) == SFmode && TARGET_SH4 \
1049 && TARGET_LITTLE_ENDIAN != 0))) \
1050 : 0)
1052 #define PRETEND_OUTGOING_VARARGS_NAMED (! TARGET_HITACHI)
1054 /* For an arg passed partly in registers and partly in memory,
1055 this is the number of registers used.
1056 For args passed entirely in registers or entirely in memory, zero.
1058 We sometimes split args. */
1060 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1061 ((PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1062 && ! TARGET_SH4 \
1063 && (ROUND_REG ((CUM), (MODE)) \
1064 + ((MODE) != BLKmode \
1065 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1066 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
1067 - NPARM_REGS (MODE) > 0)) \
1068 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
1069 : 0)
1073 /* Perform any needed actions needed for a function that is receiving a
1074 variable number of arguments. */
1076 #define SETUP_INCOMING_VARARGS(ASF, MODE, TYPE, PAS, ST) \
1077 current_function_anonymous_args = 1;
1079 /* Define the `__builtin_va_list' type for the ABI. */
1080 #define BUILD_VA_LIST_TYPE(VALIST) \
1081 (VALIST) = sh_build_va_list ()
1083 /* Implement `va_start' for varargs and stdarg. */
1084 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1085 sh_va_start (stdarg, valist, nextarg)
1087 /* Implement `va_arg'. */
1088 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1089 sh_va_arg (valist, type)
1091 /* Call the function profiler with a given profile label.
1092 We use two .aligns, so as to make sure that both the .long is aligned
1093 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1094 from the trapa instruction. */
1096 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1097 { \
1102 }
1104 /* Define this macro if the code for function profiling should come
1105 before the function prologue. Normally, the profiling code comes
1106 after. */
1108 #define PROFILE_BEFORE_PROLOGUE
1110 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1111 the stack pointer does not matter. The value is tested only in
1112 functions that have frame pointers.
1113 No definition is equivalent to always zero. */
1115 #define EXIT_IGNORE_STACK 1
1117 /* Generate the assembly code for function exit
1118 Just dump out any accumulated constant table. */
1120 #define FUNCTION_EPILOGUE(STREAM, SIZE) function_epilogue ((STREAM), (SIZE))
1122 /*
1123 On the SH, the trampoline looks like
1124 2 0002 DD02 mov.l l2,r13
1125 1 0000 D301 mov.l l1,r3
1126 3 0004 4D2B jmp @r13
1127 4 0006 0009 nop
1128 5 0008 00000000 l1: .long function
1129 6 000c 00000000 l2: .long area */
1131 /* Length in units of the trampoline for entering a nested function. */
1132 #define TRAMPOLINE_SIZE 16
1134 /* Alignment required for a trampoline in bits . */
1135 #define TRAMPOLINE_ALIGNMENT \
1136 ((CACHE_LOG < 3 || TARGET_SMALLCODE && ! TARGET_HARVARD) ? 32 : 64)
1138 /* Emit RTL insns to initialize the variable parts of a trampoline.
1139 FNADDR is an RTX for the address of the function's pure code.
1140 CXT is an RTX for the static chain value for the function. */
1142 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1143 { \
1144 emit_move_insn (gen_rtx_MEM (SImode, (TRAMP)), \
1145 GEN_INT (TARGET_LITTLE_ENDIAN ? 0xd301dd02 : 0xdd02d301));\
1146 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 4)), \
1147 GEN_INT (TARGET_LITTLE_ENDIAN ? 0x00094d2b : 0x4d2b0009));\
1148 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 8)), \
1149 (CXT)); \
1150 emit_move_insn (gen_rtx_MEM (SImode, plus_constant ((TRAMP), 12)), \
1151 (FNADDR)); \
1152 if (TARGET_HARVARD) \
1153 emit_insn (gen_ic_invalidate_line (TRAMP)); \
1154 }
1156 /* A C expression whose value is RTL representing the value of the return
1157 address for the frame COUNT steps up from the current frame.
1158 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1159 can ignore COUNT. */
1161 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1162 (((COUNT) == 0) \
1163 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)) \
1164 : (rtx) 0)
1165 \f
1166 /* Generate necessary RTL for __builtin_saveregs(). */
1168 #define EXPAND_BUILTIN_SAVEREGS() sh_builtin_saveregs ()
1169 \f
1170 /* Addressing modes, and classification of registers for them. */
1171 #define HAVE_POST_INCREMENT 1
1172 /*#define HAVE_PRE_INCREMENT 1*/
1173 /*#define HAVE_POST_DECREMENT 1*/
1174 #define HAVE_PRE_DECREMENT 1
1176 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1177 ? 0 : 1)
1178 #define USE_LOAD_PRE_DECREMENT(mode) 0
1179 #define USE_STORE_POST_INCREMENT(mode) 0
1180 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1181 ? 0 : 1)
1183 #define MOVE_BY_PIECES_P(SIZE, ALIGN) (move_by_pieces_ninsns (SIZE, ALIGN) \
1184 < (TARGET_SMALLCODE ? 2 : \
1185 ((ALIGN >= 4) ? 16 : 2)))
1187 /* Macros to check register numbers against specific register classes. */
1189 /* These assume that REGNO is a hard or pseudo reg number.
1190 They give nonzero only if REGNO is a hard reg of the suitable class
1191 or a pseudo reg currently allocated to a suitable hard reg.
1192 Since they use reg_renumber, they are safe only once reg_renumber
1193 has been allocated, which happens in local-alloc.c. */
1195 #define REGNO_OK_FOR_BASE_P(REGNO) \
1196 ((REGNO) < PR_REG || (unsigned) reg_renumber[(REGNO)] < PR_REG)
1197 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1198 ((REGNO) == 0 || (unsigned) reg_renumber[(REGNO)] == 0)
1200 /* Maximum number of registers that can appear in a valid memory
1201 address. */
1203 #define MAX_REGS_PER_ADDRESS 2
1205 /* Recognize any constant value that is a valid address. */
1207 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1209 /* Nonzero if the constant value X is a legitimate general operand. */
1211 #define LEGITIMATE_CONSTANT_P(X) \
1212 (GET_CODE (X) != CONST_DOUBLE \
1213 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
1214 || (TARGET_SH3E && (fp_zero_operand (X) || fp_one_operand (X))))
1216 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1217 and check its validity for a certain class.
1218 We have two alternate definitions for each of them.
1219 The usual definition accepts all pseudo regs; the other rejects
1220 them unless they have been allocated suitable hard regs.
1221 The symbol REG_OK_STRICT causes the latter definition to be used. */
1223 #ifndef REG_OK_STRICT
1225 /* Nonzero if X is a hard reg that can be used as a base reg
1226 or if it is a pseudo reg. */
1227 #define REG_OK_FOR_BASE_P(X) \
1228 (REGNO (X) <= 16 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1230 /* Nonzero if X is a hard reg that can be used as an index
1231 or if it is a pseudo reg. */
1232 #define REG_OK_FOR_INDEX_P(X) \
1233 (REGNO (X) == 0 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1235 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
1236 or if X is a pseudo reg. */
1237 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1238 ((REGNO (X) == 0 && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1240 #else
1242 /* Nonzero if X is a hard reg that can be used as a base reg. */
1243 #define REG_OK_FOR_BASE_P(X) \
1244 REGNO_OK_FOR_BASE_P (REGNO (X))
1246 /* Nonzero if X is a hard reg that can be used as an index. */
1247 #define REG_OK_FOR_INDEX_P(X) \
1248 REGNO_OK_FOR_INDEX_P (REGNO (X))
1250 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
1251 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
1252 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
1254 #endif
1256 /* The 'Q' constraint is a pc relative load operand. */
1257 #define EXTRA_CONSTRAINT_Q(OP) \
1258 (GET_CODE (OP) == MEM && \
1259 ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
1260 || (GET_CODE (XEXP ((OP), 0)) == CONST \
1261 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
1262 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
1263 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
1265 #define EXTRA_CONSTRAINT(OP, C) \
1267 : 0)
1268 \f
1269 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1270 that is a valid memory address for an instruction.
1271 The MODE argument is the machine mode for the MEM expression
1272 that wants to use this address.
1274 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1276 #define MODE_DISP_OK_4(X,MODE) \
1277 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
1278 && ! (INTVAL (X) & 3) && ! (TARGET_SH3E && (MODE) == SFmode))
1280 #define MODE_DISP_OK_8(X,MODE) \
1281 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
1282 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
1284 #define BASE_REGISTER_RTX_P(X) \
1285 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1286 || (GET_CODE (X) == SUBREG \
1287 && GET_CODE (SUBREG_REG (X)) == REG \
1288 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1290 /* Since this must be r0, which is a single register class, we must check
1291 SUBREGs more carefully, to be sure that we don't accept one that extends
1292 outside the class. */
1293 #define INDEX_REGISTER_RTX_P(X) \
1294 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1295 || (GET_CODE (X) == SUBREG \
1296 && GET_CODE (SUBREG_REG (X)) == REG \
1297 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_WORD (X))))
1299 /* Jump to LABEL if X is a valid address RTX. This must also take
1300 REG_OK_STRICT into account when deciding about valid registers, but it uses
1301 the above macros so we are in luck.
1303 Allow REG
1304 REG+disp
1305 REG+r0
1306 REG++
1307 --REG */
1309 /* ??? The SH3e does not have the REG+disp addressing mode when loading values
1310 into the FRx registers. We implement this by setting the maximum offset
1311 to zero when the value is SFmode. This also restricts loading of SFmode
1312 values into the integer registers, but that can't be helped. */
1314 /* The SH allows a displacement in a QI or HI amode, but only when the
1315 other operand is R0. GCC doesn't handle this very well, so we forgo
1316 all of that.
1318 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
1319 DI can be any number 0..60. */
1321 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
1322 do { \
1323 if (GET_CODE (OP) == CONST_INT) \
1324 { \
1325 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
1326 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
1327 } \
1328 } while(0)
1330 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
1331 { \
1332 if (BASE_REGISTER_RTX_P (X)) \
1333 goto LABEL; \
1334 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
1335 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
1336 goto LABEL; \
1337 else if (GET_CODE (X) == PLUS \
1338 && ((MODE) != PSImode || reload_completed)) \
1339 { \
1340 rtx xop0 = XEXP ((X), 0); \
1341 rtx xop1 = XEXP ((X), 1); \
1342 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
1343 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
1344 if (GET_MODE_SIZE (MODE) <= 4 \
1345 || TARGET_SH4 && TARGET_FMOVD && MODE == DFmode) \
1346 { \
1347 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
1348 goto LABEL; \
1349 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
1350 goto LABEL; \
1351 } \
1352 } \
1353 }
1354 \f
1355 /* Try machine-dependent ways of modifying an illegitimate address
1356 to be legitimate. If we find one, return the new, valid address.
1357 This macro is used in only one place: `memory_address' in explow.c.
1359 OLDX is the address as it was before break_out_memory_refs was called.
1360 In some cases it is useful to look at this to decide what needs to be done.
1362 MODE and WIN are passed so that this macro can use
1363 GO_IF_LEGITIMATE_ADDRESS.
1365 It is always safe for this macro to do nothing. It exists to recognize
1366 opportunities to optimize the output.
1368 For the SH, if X is almost suitable for indexing, but the offset is
1369 out of range, convert it into a normal form so that cse has a chance
1370 of reducing the number of address registers used. */
1372 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1373 { \
1374 if (GET_CODE (X) == PLUS \
1375 && (GET_MODE_SIZE (MODE) == 4 \
1376 || GET_MODE_SIZE (MODE) == 8) \
1377 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
1378 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
1379 && ! (TARGET_SH4 && (MODE) == DFmode) \
1380 && ! (TARGET_SH3E && (MODE) == SFmode)) \
1381 { \
1382 rtx index_rtx = XEXP ((X), 1); \
1383 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1384 rtx sum; \
1385 \
1386 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
1387 /* On rare occasions, we might get an unaligned pointer \
1388 that is indexed in a way to give an aligned address. \
1390 /* Instead of offset_base 128..131 use 124..127, so that \
1392 if (offset > 127) \
1393 { \
1394 offset_base = ((offset + 4) & ~60) - 4; \
1395 } \
1396 else \
1397 offset_base = offset & ~60; \
1398 /* Sometimes the normal form does not suit DImode. We \
1399 could avoid that by using smaller ranges, but that \
1400 would give less optimized code when SImode is \
1402 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1403 { \
1404 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
1405 GEN_INT (offset_base), NULL_RTX, 0, \
1406 OPTAB_LIB_WIDEN); \
1407 \
1408 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
1409 goto WIN; \
1410 } \
1411 } \
1412 }
1414 /* A C compound statement that attempts to replace X, which is an address
1415 that needs reloading, with a valid memory address for an operand of
1416 mode MODE. WIN is a C statement label elsewhere in the code.
1418 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
1419 of the address. That will allow inheritance of the address reloads. */
1421 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1422 { \
1423 if (GET_CODE (X) == PLUS \
1424 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1425 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1426 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
1427 && ! (TARGET_SH4 && (MODE) == DFmode) \
1428 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
1429 { \
1430 rtx index_rtx = XEXP (X, 1); \
1431 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
1432 rtx sum; \
1433 \
1434 if (TARGET_SH3E && MODE == SFmode) \
1435 { \
1436 X = copy_rtx (X); \
1437 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL_PTR, \
1438 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1439 (TYPE)); \
1440 goto WIN; \
1441 } \
1442 /* Instead of offset_base 128..131 use 124..127, so that \
1444 if (offset > 127) \
1445 { \
1446 offset_base = ((offset + 4) & ~60) - 4; \
1447 } \
1448 else \
1449 offset_base = offset & ~60; \
1450 /* Sometimes the normal form does not suit DImode. We \
1451 could avoid that by using smaller ranges, but that \
1452 would give less optimized code when SImode is \
1454 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
1455 { \
1456 sum = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1457 GEN_INT (offset_base)); \
1458 X = gen_rtx (PLUS, Pmode, sum, GEN_INT (offset - offset_base));\
1459 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL_PTR, \
1460 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
1461 (TYPE)); \
1462 goto WIN; \
1463 } \
1464 } \
1466 else if (GET_CODE (X) == PLUS \
1467 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
1468 && GET_CODE (XEXP (X, 0)) == PLUS \
1469 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
1470 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
1471 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1472 && ! (TARGET_SH3E && MODE == SFmode)) \
1473 { \
1474 /* Because this address is so complex, we know it must have \
1475 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
1477 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL_PTR, \
1478 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
1479 goto WIN; \
1480 } \
1481 }
1483 /* Go to LABEL if ADDR (a legitimate address expression)
1484 has an effect that depends on the machine mode it is used for.
1486 ??? Strictly speaking, we should also include all indexed addressing,
1487 because the index scale factor is the length of the operand.
1488 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
1489 high if we did that. So we rely on reload to fix things up. */
1491 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1492 { \
1493 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
1494 goto LABEL; \
1495 }
1496 \f
1497 /* Specify the machine mode that this machine uses
1498 for the index in the tablejump instruction. */
1499 #define CASE_VECTOR_MODE (TARGET_BIGTABLE ? SImode : HImode)
1501 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1502 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1503 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1504 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1505 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1506 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1507 : SImode)
1509 /* Define as C expression which evaluates to nonzero if the tablejump
1510 instruction expects the table to contain offsets from the address of the
1511 table.
1512 Do not define this if the table should contain absolute addresses. */
1513 #define CASE_VECTOR_PC_RELATIVE 1
1515 /* Specify the tree operation to be used to convert reals to integers. */
1516 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1518 /* This is the kind of divide that is easiest to do in the general case. */
1519 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1521 /* Since the SH3e has only `float' support, it is desirable to make all
1522 floating point types equivalent to `float'. */
1523 #define DOUBLE_TYPE_SIZE ((TARGET_SH3E && ! TARGET_SH4) ? 32 : 64)
1525 /* 'char' is signed by default. */
1526 #define DEFAULT_SIGNED_CHAR 1
1528 /* The type of size_t unsigned int. */
1532 #define WCHAR_TYPE_SIZE 16
1534 /* Don't cse the address of the function being compiled. */
1535 /*#define NO_RECURSIVE_FUNCTION_CSE 1*/
1537 /* Max number of bytes we can move from memory to memory
1538 in one reasonably fast instruction. */
1539 #define MOVE_MAX 4
1541 /* Max number of bytes we want move_by_pieces to be able to copy
1542 efficiently. */
1543 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4)
1545 /* Define if operations between registers always perform the operation
1546 on the full register even if a narrower mode is specified. */
1547 #define WORD_REGISTER_OPERATIONS
1549 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1550 will either zero-extend or sign-extend. The value of this macro should
1551 be the code that says which one of the two operations is implicitly
1552 done, NIL if none. */
1553 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
1555 /* Define if loading short immediate values into registers sign extends. */
1556 #define SHORT_IMMEDIATES_SIGN_EXTEND
1558 /* Define this if zero-extension is slow (more than one real instruction).
1559 On the SH, it's only one instruction. */
1560 /* #define SLOW_ZERO_EXTEND */
1562 /* Nonzero if access to memory by bytes is no faster than for words. */
1563 #define SLOW_BYTE_ACCESS 1
1565 /* Force sizeof(bool) == 1 to maintain binary compatibility; otherwise, the
1566 change in SLOW_BYTE_ACCESS would have changed it to 4. */
1568 #define BOOL_TYPE_SIZE (flag_new_abi ? INT_TYPE_SIZE : CHAR_TYPE_SIZE)
1570 /* We assume that the store-condition-codes instructions store 0 for false
1571 and some other value for true. This is the value stored for true. */
1573 #define STORE_FLAG_VALUE 1
1575 /* Immediate shift counts are truncated by the output routines (or was it
1576 the assembler?). Shift counts in a register are truncated by SH. Note
1577 that the native compiler puts too large (> 32) immediate shift counts
1578 into a register and shifts by the register, letting the SH decide what
1579 to do instead of doing that itself. */
1580 /* ??? The library routines in lib1funcs.asm truncate the shift count.
1581 However, the SH3 has hardware shifts that do not truncate exactly as gcc
1582 expects - the sign bit is significant - so it appears that we need to
1583 leave this zero for correct SH3 code. */
1584 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3)
1586 /* All integers have the same format so truncation is easy. */
1587 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
1589 /* Define this if addresses of constant functions
1590 shouldn't be put through pseudo regs where they can be cse'd.
1591 Desirable on machines where ordinary constants are expensive
1592 but a CALL with constant address is cheap. */
1593 /*#define NO_FUNCTION_CSE 1*/
1595 /* Chars and shorts should be passed as ints. */
1596 #define PROMOTE_PROTOTYPES 1
1598 /* The machine modes of pointers and functions. */
1599 #define Pmode SImode
1600 #define FUNCTION_MODE Pmode
1602 /* The relative costs of various types of constants. Note that cse.c defines
1603 REG = 1, SUBREG = 2, any node = (2 + sum of subnodes). */
1605 #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1606 case CONST_INT: \
1607 if (INTVAL (RTX) == 0) \
1608 return 0; \
1609 else if (CONST_OK_FOR_I (INTVAL (RTX))) \
1610 return 1; \
1611 else if (((OUTER_CODE) == AND || (OUTER_CODE) == IOR || (OUTER_CODE) == XOR) \
1612 && CONST_OK_FOR_L (INTVAL (RTX))) \
1613 return 1; \
1614 else \
1615 return 8; \
1616 case CONST: \
1617 case LABEL_REF: \
1618 case SYMBOL_REF: \
1619 return 5; \
1620 case CONST_DOUBLE: \
1621 return 10;
1623 #define RTX_COSTS(X, CODE, OUTER_CODE) \
1624 case PLUS: \
1625 return (COSTS_N_INSNS (1) \
1626 + rtx_cost (XEXP ((X), 0), PLUS) \
1627 + (rtx_equal_p (XEXP ((X), 0), XEXP ((X), 1))\
1628 ? 0 : rtx_cost (XEXP ((X), 1), PLUS)));\
1629 case AND: \
1630 return COSTS_N_INSNS (andcosts (X)); \
1631 case MULT: \
1632 return COSTS_N_INSNS (multcosts (X)); \
1633 case ASHIFT: \
1634 case ASHIFTRT: \
1635 case LSHIFTRT: \
1636 /* Add one extra unit for the matching constraint. \
1637 Otherwise loop strength reduction would think that\
1638 a shift with different sourc and destination is \
1640 return (COSTS_N_INSNS (shiftcosts (X)) \
1641 + rtx_cost (XEXP ((X), 0), (CODE)) \
1642 + 1); \
1643 case DIV: \
1644 case UDIV: \
1645 case MOD: \
1646 case UMOD: \
1647 return COSTS_N_INSNS (20); \
1648 case FLOAT: \
1649 case FIX: \
1650 return 100;
1652 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1653 are actually function calls with some special constraints on arguments
1654 and register usage.
1656 These macros tell reorg that the references to arguments and
1657 register clobbers for insns of type sfunc do not appear to happen
1658 until after the millicode call. This allows reorg to put insns
1659 which set the argument registers into the delay slot of the millicode
1660 call -- thus they act more like traditional CALL_INSNs.
1662 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1663 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1664 in particular. */
1666 #define INSN_SETS_ARE_DELAYED(X) \
1667 ((GET_CODE (X) == INSN \
1668 && GET_CODE (PATTERN (X)) != SEQUENCE \
1669 && GET_CODE (PATTERN (X)) != USE \
1670 && GET_CODE (PATTERN (X)) != CLOBBER \
1671 && get_attr_is_sfunc (X)))
1673 #define INSN_REFERENCES_ARE_DELAYED(X) \
1674 ((GET_CODE (X) == INSN \
1675 && GET_CODE (PATTERN (X)) != SEQUENCE \
1676 && GET_CODE (PATTERN (X)) != USE \
1677 && GET_CODE (PATTERN (X)) != CLOBBER \
1678 && get_attr_is_sfunc (X)))
1680 /* Compute the cost of an address. For the SH, all valid addresses are
1681 the same cost. */
1682 /* ??? Perhaps we should make reg+reg addresses have higher cost because
1683 they add to register pressure on r0. */
1685 #define ADDRESS_COST(RTX) 1
1687 /* Compute extra cost of moving data between one register class
1688 and another. */
1690 /* Regclass always uses 2 for moves in the same register class;
1691 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair,
1692 it uses this information. Hence, the general register <-> floating point
1693 register information here is not used for SFmode. */
1694 #define REGISTER_MOVE_COST(SRCCLASS, DSTCLASS) \
1695 ((((DSTCLASS) == T_REGS) || ((DSTCLASS) == PR_REGS)) ? 10 \
1696 : ((((DSTCLASS) == FP0_REGS || (DSTCLASS) == FP_REGS || (DSTCLASS) == DF_REGS) \
1697 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1698 || (((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS) \
1699 && ((SRCCLASS) == FP0_REGS || (SRCCLASS) == FP_REGS \
1700 || (SRCCLASS) == DF_REGS))) \
1701 ? TARGET_FMOVD ? 8 : 12 \
1702 : (((DSTCLASS) == FPUL_REGS \
1703 && ((SRCCLASS) == GENERAL_REGS || (SRCCLASS) == R0_REGS)) \
1704 || (SRCCLASS == FPUL_REGS \
1705 && ((DSTCLASS) == GENERAL_REGS || (DSTCLASS) == R0_REGS))) \
1706 ? 5 \
1707 : (((DSTCLASS) == FPUL_REGS \
1708 && ((SRCCLASS) == PR_REGS || (SRCCLASS) == MAC_REGS \
1709 || (SRCCLASS) == T_REGS)) \
1710 || ((SRCCLASS) == FPUL_REGS \
1711 && ((DSTCLASS) == PR_REGS || (DSTCLASS) == MAC_REGS))) \
1712 ? 7 \
1713 : 2)
1715 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1716 would be so that people with slow memory systems could generate
1717 different code that does fewer memory accesses. */
1719 /* A C expression for the cost of a branch instruction. A value of 1
1720 is the default; other values are interpreted relative to that.
1721 The SH1 does not have delay slots, hence we get a pipeline stall
1722 at every branch. The SH4 is superscalar, so the single delay slot
1723 is not sufficient to keep both pipelines filled. */
1724 #define BRANCH_COST (! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
1725 \f
1726 /* Assembler output control. */
1728 /* A C string constant describing how to begin a comment in the target
1729 assembler language. The compiler assumes that the comment will end at
1730 the end of the line. */
1733 /* The text to go at the start of the assembler file. */
1734 #define ASM_FILE_START(STREAM) \
1735 output_file_start (STREAM)
1737 #define ASM_FILE_END(STREAM)
1745 /* How to change between sections. */
1751 #define EXTRA_SECTIONS in_ctors, in_dtors
1752 #define EXTRA_SECTION_FUNCTIONS \
1753 void \
1754 ctors_section() \
1755 { \
1756 if (in_section != in_ctors) \
1757 { \
1759 in_section = in_ctors; \
1760 } \
1761 } \
1762 void \
1763 dtors_section() \
1764 { \
1765 if (in_section != in_dtors) \
1766 { \
1768 in_section = in_dtors; \
1769 } \
1770 }
1772 /* If defined, a C expression whose value is a string containing the
1773 assembler operation to identify the following data as
1774 uninitialized global data. If not defined, and neither
1775 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
1776 uninitialized global data will be output in the data section if
1777 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
1778 used. */
1779 #ifndef BSS_SECTION_ASM_OP
1781 #endif
1783 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
1784 separate, explicit argument. If you define this macro, it is used
1785 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
1786 handling the required alignment of the variable. The alignment is
1787 specified as the number of bits.
1789 Try to use function `asm_output_aligned_bss' defined in file
1790 `varasm.c' when defining this macro. */
1791 #ifndef ASM_OUTPUT_ALIGNED_BSS
1792 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1793 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1794 #endif
1796 /* Define this so that jump tables go in same section as the current function,
1797 which could be text or it could be a user defined section. */
1798 #define JUMP_TABLES_IN_TEXT_SECTION 1
1800 /* A C statement to output something to the assembler file to switch to section
1801 NAME for object DECL which is either a FUNCTION_DECL, a VAR_DECL or
1802 NULL_TREE. Some target formats do not support arbitrary sections. Do not
1803 define this macro in such cases. */
1805 #define ASM_OUTPUT_SECTION_NAME(FILE, DECL, NAME, RELOC) \
1808 #define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \
1811 #define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \
1814 #undef DO_GLOBAL_CTORS_BODY
1816 #define DO_GLOBAL_CTORS_BODY \
1817 { \
1818 typedef (*pfunc)(); \
1819 extern pfunc __ctors[]; \
1820 extern pfunc __ctors_end[]; \
1821 pfunc *p; \
1822 for (p = __ctors_end; p > __ctors; ) \
1823 { \
1824 (*--p)(); \
1825 } \
1826 }
1828 #undef DO_GLOBAL_DTORS_BODY
1829 #define DO_GLOBAL_DTORS_BODY \
1830 { \
1831 typedef (*pfunc)(); \
1832 extern pfunc __dtors[]; \
1833 extern pfunc __dtors_end[]; \
1834 pfunc *p; \
1835 for (p = __dtors; p < __dtors_end; p++) \
1836 { \
1837 (*p)(); \
1838 } \
1839 }
1841 #define ASM_OUTPUT_REG_PUSH(file, v) \
1844 #define ASM_OUTPUT_REG_POP(file, v) \
1847 /* The assembler's names for the registers. RFP need not always be used as
1848 the Real framepointer; it can also be used as a normal general register.
1849 Note that the name `fp' is horribly misleading since `fp' is in fact only
1850 the argument-and-return-context pointer. */
1854 #define REGISTER_NAMES \
1855 { \
1859 fp_reg_names[0], fp_reg_names[1] , fp_reg_names[2], fp_reg_names[3], \
1860 fp_reg_names[4], fp_reg_names[5], fp_reg_names[6], fp_reg_names[7], \
1861 fp_reg_names[8], fp_reg_names[9], fp_reg_names[10], fp_reg_names[11], \
1862 fp_reg_names[12], fp_reg_names[13], fp_reg_names[14], fp_reg_names[15], \
1863 fp_reg_names[17], fp_reg_names[18], fp_reg_names[19], fp_reg_names[20], \
1864 fp_reg_names[21], fp_reg_names[22], fp_reg_names[23], fp_reg_names[24], \
1866 }
1868 #define DEBUG_REGISTER_NAMES \
1869 { \
1877 }
1879 /* DBX register number for a given compiler register number. */
1880 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
1881 to match gdb. */
1882 #define DBX_REGISTER_NUMBER(REGNO) \
1883 (((REGNO) >= 22 && (REGNO) <= 39) ? ((REGNO) + 1) : (REGNO))
1885 /* Output a label definition. */
1886 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1889 /* This is how to output an assembler line
1890 that says to advance the location counter
1891 to a multiple of 2**LOG bytes. */
1893 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1894 if ((LOG) != 0) \
1897 /* Output a function label definition. */
1898 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
1899 ASM_OUTPUT_LABEL((STREAM), (NAME))
1901 /* Output a globalising directive for a label. */
1902 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
1904 assemble_name ((STREAM), (NAME)), \
1907 /* The prefix to add to user-visible assembler symbols. */
1911 /* The prefix to add to an internally generated label. */
1915 /* Make an internal label into a string. */
1916 #define ASM_GENERATE_INTERNAL_LABEL(STRING, PREFIX, NUM) \
1919 /* Output an internal label definition. */
1920 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1923 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
1925 /* Construct a private name. */
1926 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \
1927 ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \
1930 /* Output a relative address table. */
1932 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
1933 switch (GET_MODE (BODY)) \
1934 { \
1935 case SImode: \
1937 break; \
1938 case HImode: \
1940 break; \
1941 case QImode: \
1943 break; \
1944 }
1946 /* Output an absolute table element. */
1948 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
1949 if (TARGET_BIGTABLE) \
1951 else \
1954 /* Output various types of constants. */
1956 /* This is how to output an assembler line defining a `double'. */
1958 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1959 do { char dstr[30]; \
1962 } while (0)
1964 /* This is how to output an assembler line defining a `float' constant. */
1965 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1966 do { char dstr[30]; \
1969 } while (0)
1971 #define ASM_OUTPUT_INT(STREAM, EXP) \
1973 output_addr_const ((STREAM), (EXP)), \
1976 #define ASM_OUTPUT_SHORT(STREAM, EXP) \
1978 output_addr_const ((STREAM), (EXP)), \
1981 #define ASM_OUTPUT_CHAR(STREAM, EXP) \
1983 output_addr_const ((STREAM), (EXP)), \
1986 #define ASM_OUTPUT_BYTE(STREAM, VALUE) \
1989 /* The next two are used for debug info when compiling with -gdwarf. */
1993 /* Loop alignment is now done in machine_dependent_reorg, so that
1994 branch shortening can know about it. */
1996 /* This is how to output an assembler line
1997 that says to advance the location counter by SIZE bytes. */
1999 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2002 /* This says how to output an assembler line
2003 to define a global common symbol. */
2005 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2007 assemble_name ((FILE), (NAME)), \
2010 /* This says how to output an assembler line
2011 to define a local common symbol. */
2013 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
2015 assemble_name ((FILE), (NAME)), \
2018 /* The assembler's parentheses characters. */
2022 /* Target characters. */
2023 #define TARGET_BELL 007
2024 #define TARGET_BS 010
2025 #define TARGET_TAB 011
2026 #define TARGET_NEWLINE 012
2027 #define TARGET_VT 013
2028 #define TARGET_FF 014
2029 #define TARGET_CR 015
2030 \f
2031 /* A C statement to be executed just prior to the output of
2032 assembler code for INSN, to modify the extracted operands so
2033 they will be output differently.
2035 Here the argument OPVEC is the vector containing the operands
2036 extracted from INSN, and NOPERANDS is the number of elements of
2037 the vector which contain meaningful data for this insn.
2038 The contents of this vector are what will be used to convert the insn
2039 template into assembler code, so you can change the assembler output
2040 by changing the contents of the vector. */
2042 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2043 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2045 /* Print operand X (an rtx) in assembler syntax to file FILE.
2046 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2047 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2049 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
2051 /* Print a memory address as an operand to reference that memory location. */
2053 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
2055 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2058 \f
2063 /* Which processor to schedule for. The elements of the enumeration must
2064 match exactly the cpu attribute in the sh.md file. */
2067 PROCESSOR_SH1,
2068 PROCESSOR_SH2,
2069 PROCESSOR_SH3,
2070 PROCESSOR_SH3E,
2071 PROCESSOR_SH4
2072 };
2074 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2081 /* Declare functions defined in sh.c and used in templates. */
2092 enum mdep_reorg_phase_e
2093 {
2094 SH_BEFORE_MDEP_REORG,
2095 SH_INSERT_USES_LABELS,
2096 SH_SHORTEN_BRANCHES0,
2097 SH_FIXUP_PCLOAD,
2098 SH_SHORTEN_BRANCHES1,
2099 SH_AFTER_MDEP_REORG
2100 };
2108 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg(X)
2110 /* Generate calls to memcpy, memcmp and memset. */
2112 #define TARGET_MEM_FUNCTIONS
2114 /* Define this macro if you want to implement any pragmas. If defined, it
2115 is a C expression whose value is 1 if the pragma was handled by the
2116 macro, zero otherwise. */
2117 #define HANDLE_PRAGMA(GETC, UNGETC, NODE) sh_handle_pragma (GETC, UNGETC, NODE)
2120 /* Set when processing a function with pragma interrupt turned on. */
2124 /* Set to an RTX containing the address of the stack to switch to
2125 for interrupt functions. */
2128 /* A C expression whose value is nonzero if IDENTIFIER with arguments ARGS
2129 is a valid machine specific attribute for DECL.
2130 The attributes in ATTRIBUTES have previously been assigned to DECL. */
2132 #define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, IDENTIFIER, ARGS) \
2133 sh_valid_machine_decl_attribute (DECL, ATTRIBUTES, IDENTIFIER, ARGS)
2136 #define PRAGMA_INSERT_ATTRIBUTES(node, pattr, prefix_attr) \
2137 sh_pragma_insert_attributes (node, pattr, prefix_attr)
2144 \f
2145 /* Instructions with unfilled delay slots take up an extra two bytes for
2146 the nop in the delay slot. */
2148 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2149 if (((GET_CODE (X) == INSN \
2150 && GET_CODE (PATTERN (X)) != USE \
2151 && GET_CODE (PATTERN (X)) != CLOBBER) \
2152 || GET_CODE (X) == CALL_INSN \
2153 || (GET_CODE (X) == JUMP_INSN \
2154 && GET_CODE (PATTERN (X)) != ADDR_DIFF_VEC \
2155 && GET_CODE (PATTERN (X)) != ADDR_VEC)) \
2156 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (X)))) != SEQUENCE \
2157 && get_attr_needs_delay_slot (X) == NEEDS_DELAY_SLOT_YES) \
2158 (LENGTH) += 2;
2159 \f
2160 /* Define the codes that are matched by predicates in sh.c. */
2161 #define PREDICATE_CODES \
2176 /* Define this macro if it is advisable to hold scalars in registers
2177 in a wider mode than that declared by the program. In such cases,
2178 the value is constrained to be within the bounds of the declared
2179 type, but kept valid in the wider mode. The signedness of the
2180 extension may differ from that of the type.
2182 Leaving the unsignedp unchanged gives better code than always setting it
2183 to 0. This is despite the fact that we have only signed char and short
2184 load instructions. */
2185 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2186 if (GET_MODE_CLASS (MODE) == MODE_INT \
2187 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
2188 (MODE) = SImode;
2190 /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign
2191 extensions applied to char/short functions arguments. Defining
2192 PROMOTE_FUNCTION_RETURN does the same for function returns. */
2194 #define PROMOTE_FUNCTION_ARGS
2195 #define PROMOTE_FUNCTION_RETURN
2197 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
2198 and poping arguments. However, we do have push/pop instructions, and
2199 rather limited offsets (4 bits) in load/store instructions, so it isn't
2200 clear if this would give better code. If implemented, should check for
2201 compatibility problems. */
2203 /* A C statement (sans semicolon) to update the integer variable COST
2204 based on the relationship between INSN that is dependent on
2205 DEP_INSN through the dependence LINK. The default is to make no
2206 adjustment to COST. This can be used for example to specify to
2207 the scheduler that an output- or anti-dependence does not incur
2208 the same cost as a data-dependence. */
2210 #define ADJUST_COST(insn,link,dep_insn,cost) \
2211 do { \
2212 rtx reg; \
2213 \
2214 if (GET_CODE(insn) == CALL_INSN) \
2215 { \
2216 /* The only input for a call that is timing-critical is the \
2218 rtx call = PATTERN (insn); \
2219 \
2220 if (GET_CODE (call) == PARALLEL) \
2221 call = XVECEXP (call, 0 ,0); \
2222 if (GET_CODE (call) == SET) \
2223 call = SET_SRC (call); \
2224 if (GET_CODE (call) == CALL && GET_CODE (XEXP (call, 0)) == MEM \
2225 && ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)) \
2226 (cost) = 0; \
2227 } \
2228 /* All sfunc calls are parallels with at least four components. \
2230 else if (GET_CODE (PATTERN (insn)) == PARALLEL \
2231 && XVECLEN (PATTERN (insn), 0) >= 4 \
2232 && (reg = sfunc_uses_reg (insn))) \
2233 { \
2234 /* Likewise, the most timing critical input for an sfuncs call \
2235 is the function address. However, sfuncs typically start \
2236 using their arguments pretty quickly. \
2238 if (! reg_set_p (reg, dep_insn)) \
2239 cost -= TARGET_SUPERSCALAR ? 40 : 4; \
2240 } \
2241 /* Adjust load_si / pcload_si type insns latency. Use the known \
2243 else if (cost == 3 \
2244 && GET_CODE (PATTERN (dep_insn)) == SET \
2245 /* Latency for dmpy type insns is also 3, so check the that \
2247 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn)), SImode))\
2248 cost = 2; \
2249 else if (cost == 30 \
2250 && GET_CODE (PATTERN (dep_insn)) == SET \
2251 && GET_MODE (SET_SRC (PATTERN (dep_insn))) == SImode) \
2252 cost = 20; \
2253 } while (0) \
2255 #define SH_DYNAMIC_SHIFT_COST \
2256 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)