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2004-08-23 Eric Christopher <echristo@redhat.com>
[official-gcc.git] / gcc / config / sh / sh.h
blobc249661452983c2286e0472fd0d2197a36d2e1f5
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
57 break; \
58 case PROCESSOR_SH3: \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
63 break; \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
66 break; \
67 case PROCESSOR_SH4: \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
69 break; \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
75 : "__SH4_NOFPU__"); \
76 break; \
77 case PROCESSOR_SH5: \
78 { \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
85 } \
86 } \
87 if (TARGET_HITACHI) \
88 builtin_define ("__HITACHI__"); \
89 builtin_define (TARGET_LITTLE_ENDIAN \
90 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
91 if (flag_pic) \
92 { \
93 builtin_define ("__pic__"); \
94 builtin_define ("__PIC__"); \
95 } \
96 } while (0)
97
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
100
101 #define CONDITIONAL_REGISTER_USAGE do \
102 { \
103 int regno; \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
108 if (TARGET_SH5) \
109 { \
110 call_used_regs[FIRST_GENERAL_REG + 8] \
111 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
112 call_really_used_regs[FIRST_GENERAL_REG + 8] \
113 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
114 } \
115 if (TARGET_SHMEDIA) \
116 { \
117 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
118 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
119 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
120 } \
121 if (flag_pic) \
122 { \
123 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
125 } \
126 /* Renesas saves and restores mac registers on call. */ \
127 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
128 { \
129 call_really_used_regs[MACH_REG] = 0; \
130 call_really_used_regs[MACL_REG] = 0; \
131 } \
132 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
133 regno <= LAST_FP_REG; regno += 2) \
134 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
135 if (TARGET_SHMEDIA) \
136 { \
137 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
138 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
139 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
140 } \
141 else \
142 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
143 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
144 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
145 } while (0)
146 \f
147 /* ??? Need to write documentation for all SH options and add it to the
148 invoke.texi file. */
149
150 /* Run-time compilation parameters selecting different hardware subsets. */
151
152 extern int target_flags;
153 #define ISIZE_BIT (1<<1)
154 #define DALIGN_BIT (1<<6)
155 #define SH1_BIT (1<<8)
156 #define SH2_BIT (1<<9)
157 #define SH3_BIT (1<<10)
158 #define SH_E_BIT (1<<11)
159 #define HARD_SH4_BIT (1<<5)
160 #define FPU_SINGLE_BIT (1<<7)
161 #define SH4_BIT (1<<12)
162 #define SH4A_BIT (1<<3)
163 #define FMOVD_BIT (1<<4)
164 #define SH5_BIT (1<<0)
165 #define SPACE_BIT (1<<13)
166 #define BIGTABLE_BIT (1<<14)
167 #define RELAX_BIT (1<<15)
168 #define USERMODE_BIT (1<<16)
169 #define HITACHI_BIT (1<<22)
170 #define NOMACSAVE_BIT (1<<23)
171 #define PREFERGOT_BIT (1<<24)
172 #define PADSTRUCT_BIT (1<<28)
173 #define LITTLE_ENDIAN_BIT (1<<29)
174 #define IEEE_BIT (1<<30)
175 #define SAVE_ALL_TR_BIT (1<<2)
176 #define HARD_SH2A_BIT (1<<17)
177 #define HARD_SH2A_DOUBLE_BIT (1<<18)
178
179 /* Nonzero if this is an ELF target - compile time only */
180 #define TARGET_ELF 0
181
182 /* Nonzero if we should dump out instruction size info. */
183 #define TARGET_DUMPISIZE (target_flags & ISIZE_BIT)
184
185 /* Nonzero to align doubles on 64 bit boundaries. */
186 #define TARGET_ALIGN_DOUBLE (target_flags & DALIGN_BIT)
187
188 /* Nonzero if we should generate code using type 1 insns. */
189 #define TARGET_SH1 (target_flags & SH1_BIT)
190
191 /* Nonzero if we should generate code using type 2 insns. */
192 #define TARGET_SH2 (target_flags & SH2_BIT)
193
194 /* Nonzero if we should generate code using type 2E insns. */
195 #define TARGET_SH2E ((target_flags & SH_E_BIT) && TARGET_SH2)
196
197 /* Nonzero if we should generate code using type 2A insns. */
198 #define TARGET_SH2A (target_flags & HARD_SH2A_BIT)
199 /* Nonzero if we should generate code using type 2A SF insns. */
200 #define TARGET_SH2A_SINGLE ((target_flags & HARD_SH2A_BIT) && TARGET_SH2E)
201 /* Nonzero if we should generate code using type 2A DF insns. */
202 #define TARGET_SH2A_DOUBLE ((target_flags & HARD_SH2A_DOUBLE_BIT) && TARGET_SH2A)
203
204 /* Nonzero if we should generate code using type 3 insns. */
205 #define TARGET_SH3 (target_flags & SH3_BIT)
206
207 /* Nonzero if we should generate code using type 3E insns. */
208 #define TARGET_SH3E ((target_flags & SH_E_BIT) && TARGET_SH3)
209
210 /* Nonzero if the cache line size is 32. */
211 #define TARGET_CACHE32 (target_flags & HARD_SH4_BIT || TARGET_SH5)
212
213 /* Nonzero if we schedule for a superscalar implementation. */
214 #define TARGET_SUPERSCALAR (target_flags & HARD_SH4_BIT)
215
216 /* Nonzero if the target has separate instruction and data caches. */
217 #define TARGET_HARVARD (target_flags & HARD_SH4_BIT)
218
219 /* Nonzero if compiling for SH4 hardware (to be used for insn costs etc.) */
220 #define TARGET_HARD_SH4 (target_flags & HARD_SH4_BIT)
221
222 /* Nonzero if the default precision of th FPU is single */
223 #define TARGET_FPU_SINGLE (target_flags & FPU_SINGLE_BIT)
224
225 /* Nonzero if a double-precision FPU is available. */
226 #define TARGET_FPU_DOUBLE ((target_flags & SH4_BIT) || TARGET_SH2A_DOUBLE)
227
228 /* Nonzero if an FPU is available. */
229 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
230
231 /* Nonzero if we should generate code using type 4 insns. */
232 #define TARGET_SH4 ((target_flags & SH4_BIT) && (target_flags & SH1_BIT))
233
234 /* Nonzero if we're generating code for the common subset of
235 instructions present on both SH4a and SH4al-dsp. */
236 #define TARGET_SH4A_ARCH (target_flags & SH4A_BIT)
237
238 /* Nonzero if we're generating code for SH4a, unless the use of the
239 FPU is disabled (which makes it compatible with SH4al-dsp). */
240 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
241
242 /* Nonzero if we should generate code for a SH5 CPU (either ISA). */
243 #define TARGET_SH5 (target_flags & SH5_BIT)
244
245 /* Nonzero if we should generate code using the SHcompact instruction
246 set and 32-bit ABI. */
247 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
248
249 /* Nonzero if we should generate code using the SHmedia instruction
250 set and ABI. */
251 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
252
253 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
254 ABI. */
255 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 \
256 && (target_flags & SH_E_BIT))
257
258 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
259 ABI. */
260 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 \
261 && ! (target_flags & SH_E_BIT))
262
263 /* Nonzero if we should generate code using SHmedia FPU instructions. */
264 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
265 /* Nonzero if we should generate fmovd. */
266 #define TARGET_FMOVD (target_flags & FMOVD_BIT)
267
268 /* Nonzero if we respect NANs. */
269 #define TARGET_IEEE (target_flags & IEEE_BIT)
270
271 /* Nonzero if we should generate smaller code rather than faster code. */
272 #define TARGET_SMALLCODE (target_flags & SPACE_BIT)
273
274 /* Nonzero to use long jump tables. */
275 #define TARGET_BIGTABLE (target_flags & BIGTABLE_BIT)
276
277 /* Nonzero to generate pseudo-ops needed by the assembler and linker
278 to do function call relaxing. */
279 #define TARGET_RELAX (target_flags & RELAX_BIT)
280
281 /* Nonzero if using Renesas's calling convention. */
282 #define TARGET_HITACHI (target_flags & HITACHI_BIT)
283
284 /* Nonzero if not saving macl/mach when using -mhitachi */
285 #define TARGET_NOMACSAVE (target_flags & NOMACSAVE_BIT)
286
287 /* Nonzero if padding structures to a multiple of 4 bytes. This is
288 incompatible with Renesas's compiler, and gives unusual structure layouts
289 which confuse programmers.
290 ??? This option is not useful, but is retained in case there are people
291 who are still relying on it. It may be deleted in the future. */
292 #define TARGET_PADSTRUCT (target_flags & PADSTRUCT_BIT)
293
294 /* Nonzero if generating code for a little endian SH. */
295 #define TARGET_LITTLE_ENDIAN (target_flags & LITTLE_ENDIAN_BIT)
296
297 /* Nonzero if we should do everything in userland. */
298 #define TARGET_USERMODE (target_flags & USERMODE_BIT)
299
300 /* Nonzero if we should prefer @GOT calls when generating PIC. */
301 #define TARGET_PREFERGOT (target_flags & PREFERGOT_BIT)
302
303 #define TARGET_SAVE_ALL_TARGET_REGS (target_flags & SAVE_ALL_TR_BIT)
304
305 /* This is not used by the SH2E calling convention */
306 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
307 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
308 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
309
310 #ifndef TARGET_CPU_DEFAULT
311 #define TARGET_CPU_DEFAULT SELECT_SH1
312 #define SUPPORT_SH1
313 #define SUPPORT_SH2E
314 #define SUPPORT_SH4
315 #define SUPPORT_SH4_SINGLE
316 #define SUPPORT_SH2A
317 #define SUPPORT_SH2A_SINGLE
318 #endif
319
320 #define SELECT_SH1 (SH1_BIT)
321 #define SELECT_SH2 (SH2_BIT | SELECT_SH1)
322 #define SELECT_SH2E (SH_E_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
323 #define SELECT_SH2A (SH_E_BIT | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
324 #define SELECT_SH2A_NOFPU (HARD_SH2A_BIT | SH2_BIT | SH1_BIT)
325 #define SELECT_SH2A_SINGLE_ONLY (SH_E_BIT | HARD_SH2A_BIT | SH2_BIT | SH1_BIT | FPU_SINGLE_BIT)
326 #define SELECT_SH2A_SINGLE (SH_E_BIT | HARD_SH2A_BIT | FPU_SINGLE_BIT \
327 | HARD_SH2A_DOUBLE_BIT | SH2_BIT | SH1_BIT)
328 #define SELECT_SH3 (SH3_BIT | SELECT_SH2)
329 #define SELECT_SH3E (SH_E_BIT | FPU_SINGLE_BIT | SELECT_SH3)
330 #define SELECT_SH4_NOFPU (HARD_SH4_BIT | SELECT_SH3)
331 #define SELECT_SH4_SINGLE_ONLY (HARD_SH4_BIT | SELECT_SH3E)
332 #define SELECT_SH4 (SH4_BIT | SH_E_BIT | HARD_SH4_BIT | SELECT_SH3)
333 #define SELECT_SH4_SINGLE (FPU_SINGLE_BIT | SELECT_SH4)
334 #define SELECT_SH4A_NOFPU (SH4A_BIT | SELECT_SH4_NOFPU)
335 #define SELECT_SH4A_SINGLE_ONLY (SH4A_BIT | SELECT_SH4_SINGLE_ONLY)
336 #define SELECT_SH4A (SH4A_BIT | SELECT_SH4)
337 #define SELECT_SH4A_SINGLE (SH4A_BIT | SELECT_SH4_SINGLE)
338 #define SELECT_SH5_64MEDIA (SH5_BIT | SH4_BIT)
339 #define SELECT_SH5_64MEDIA_NOFPU (SH5_BIT)
340 #define SELECT_SH5_32MEDIA (SH5_BIT | SH4_BIT | SH_E_BIT)
341 #define SELECT_SH5_32MEDIA_NOFPU (SH5_BIT | SH_E_BIT)
342 #define SELECT_SH5_COMPACT (SH5_BIT | SH4_BIT | SELECT_SH3E)
343 #define SELECT_SH5_COMPACT_NOFPU (SH5_BIT | SELECT_SH3)
344
345 /* Disable processor switches for which we have no suitable multilibs. */
346 #ifndef SUPPORT_SH1
347 #define TARGET_SWITCH_SH1
348 #ifndef SUPPORT_SH2
349 #define TARGET_SWITCH_SH2
350 #ifndef SUPPORT_SH3
351 #define TARGET_SWITCH_SH3
352 #ifndef SUPPORT_SH4_NOFPU
353 #define TARGET_SWITCH_SH4_NOFPU
354 #endif
355 #ifndef SUPPORT_SH4A_NOFPU
356 #define TARGET_SWITCH_SH4A_NOFPU
357 #endif
358 #ifndef SUPPORT_SH4AL
359 #define TARGET_SWITCH_SH4AL
360 #endif
361 #ifndef SUPPORT_SH2A_NOFPU
362 #define TARGET_SWITCH_SH2A_NOFPU
363 #endif
364 #endif
365 #endif
366 #endif
367
368 #ifndef SUPPORT_SH2E
369 #define TARGET_SWITCH_SH2E
370 #ifndef SUPPORT_SH3E
371 #define TARGET_SWITCH_SH3E
372 #ifndef SUPPORT_SH4_SINGLE_ONLY
373 #define TARGET_SWITCH_SH4_SINGLE_ONLY
374 #endif
375 #ifndef SUPPORT_SH4A_SINGLE_ONLY
376 #define TARGET_SWITCH_SH4A_SINGLE_ONLY
377 #endif
378 #ifndef SUPPORT_SH2A_SINGLE_ONLY
379 #define TARGET_SWITCH_SH2A_SINGLE_ONLY
380 #endif
381 #endif
382 #endif
383
384 #ifndef SUPPORT_SH4
385 #define TARGET_SWITCH_SH4
386 #ifndef SUPPORT_SH4A
387 #define TARGET_SWITCH_SH4A
388 #endif
389 #endif
390
391 #ifndef SUPPORT_SH4_SINGLE
392 #define TARGET_SWITCH_SH4_SINGLE
393 #ifndef SUPPORT_SH4A_SINGLE
394 #define TARGET_SWITCH_SH4A_SINGLE
395 #endif
396 #endif
397
398 #ifndef SUPPORT_SH2A
399 #define TARGET_SWITCH_SH2A
400 #endif
401
402 #ifndef SUPPORT_SH2A_SINGLE
403 #define TARGET_SWITCH_SH2A_SINGLE
404 #endif
405
406 #ifndef SUPPORT_SH5_64MEDIA
407 #define TARGET_SWITCH_SH5_64MEDIA
408 #endif
409
410 #ifndef SUPPORT_SH5_64MEDIA_NOFPU
411 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU
412 #endif
413
414 #if !defined(SUPPORT_SH5_32MEDIA) && !defined (SUPPORT_SH5_COMPACT)
415 #define TARGET_SWITCHES_SH5_32MEDIA
416 #endif
417
418 #if !defined(SUPPORT_SH5_32MEDIA_NOFPU) && !defined (SUPPORT_SH5_COMPACT_NOFPU)
419 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU
420 #endif
421
422 /* Reset all target-selection flags. */
423 #define TARGET_NONE -(SH1_BIT | SH2_BIT | SH3_BIT | SH_E_BIT | SH4_BIT \
424 | HARD_SH2A_BIT | HARD_SH2A_DOUBLE_BIT \
425 | SH4A_BIT | HARD_SH4_BIT | FPU_SINGLE_BIT | SH5_BIT)
426
427 #ifndef TARGET_SWITCH_SH1
428 #define TARGET_SWITCH_SH1 \
429 {"1", TARGET_NONE, "" }, \
430 {"1", SELECT_SH1, "Generate SH1 code" },
431 #endif
432 #ifndef TARGET_SWITCH_SH2
433 #define TARGET_SWITCH_SH2 \
434 {"2", TARGET_NONE, "" }, \
435 {"2", SELECT_SH2, "Generate SH2 code" },
436 #endif
437 #ifndef TARGET_SWITCH_SH2E
438 #define TARGET_SWITCH_SH2E \
439 {"2e", TARGET_NONE, "" }, \
440 {"2e", SELECT_SH2E, "Generate SH2e code" },
441 #endif
442 #ifndef TARGET_SWITCH_SH2A
443 #define TARGET_SWITCH_SH2A \
444 {"2a", TARGET_NONE, "" }, \
445 {"2a", SELECT_SH2A, "Generate SH2a code" },
446 #endif
447 #ifndef TARGET_SWITCH_SH2A_SINGLE_ONLY
448 #define TARGET_SWITCH_SH2A_SINGLE_ONLY \
449 {"2a-single-only", TARGET_NONE, "" }, \
450 {"2a-single-only", SELECT_SH2A_SINGLE_ONLY, "Generate only single-precision SH2a code" },
451 #endif
452 #ifndef TARGET_SWITCH_SH2A_SINGLE
453 #define TARGET_SWITCH_SH2A_SINGLE \
454 {"2a-single", TARGET_NONE, "" }, \
455 {"2a-single", SELECT_SH2A_SINGLE, "Generate default single-precision SH2a code" },
456 #endif
457 #ifndef TARGET_SWITCH_SH2A_NOFPU
458 #define TARGET_SWITCH_SH2A_NOFPU \
459 {"2a-nofpu", TARGET_NONE, "" }, \
460 {"2a-nofpu", SELECT_SH2A_NOFPU, "Generate SH2a FPU-less code" },
461 #endif
462 #ifndef TARGET_SWITCH_SH3
463 #define TARGET_SWITCH_SH3 \
464 {"3", TARGET_NONE, "" }, \
465 {"3", SELECT_SH3, "Generate SH3 code" },
466 #endif
467 #ifndef TARGET_SWITCH_SH3E
468 #define TARGET_SWITCH_SH3E \
469 {"3e", TARGET_NONE, "" }, \
470 {"3e", SELECT_SH3E, "Generate SH3e code" },
471 #endif
472 #ifndef TARGET_SWITCH_SH4_SINGLE_ONLY
473 #define TARGET_SWITCH_SH4_SINGLE_ONLY \
474 {"4-single-only", TARGET_NONE, "" }, \
475 {"4-single-only", SELECT_SH4_SINGLE_ONLY, "Generate only single-precision SH4 code" },
476 #endif
477 #ifndef TARGET_SWITCH_SH4_SINGLE
478 #define TARGET_SWITCH_SH4_SINGLE \
479 {"4-single", TARGET_NONE, "" }, \
480 {"4-single", SELECT_SH4_SINGLE, "Generate default single-precision SH4 code" },
481 #endif
482 #ifndef TARGET_SWITCH_SH4_NOFPU
483 #define TARGET_SWITCH_SH4_NOFPU \
484 {"4-nofpu", TARGET_NONE, "" }, \
485 {"4-nofpu", SELECT_SH4_NOFPU, "Generate SH4 FPU-less code" },
486 #endif
487 #ifndef TARGET_SWITCH_SH4
488 #define TARGET_SWITCH_SH4 \
489 {"4", TARGET_NONE, "" }, \
490 {"4", SELECT_SH4, "Generate SH4 code" },
491 #endif
492 #ifndef TARGET_SWITCH_SH4A
493 #define TARGET_SWITCH_SH4A \
494 {"4a", TARGET_NONE, "" }, \
495 {"4a", SELECT_SH4A, "Generate SH4a code" },
496 #endif
497 #ifndef TARGET_SWITCH_SH4A_SINGLE_ONLY
498 #define TARGET_SWITCH_SH4A_SINGLE_ONLY \
499 {"4a-single-only", TARGET_NONE, "" }, \
500 {"4a-single-only", SELECT_SH4A_SINGLE_ONLY, "Generate only single-precision SH4a code" },
501 #endif
502 #ifndef TARGET_SWITCH_SH4A_SINGLE
503 #define TARGET_SWITCH_SH4A_SINGLE \
504 {"4a-single", TARGET_NONE, "" },\
505 {"4a-single", SELECT_SH4A_SINGLE, "Generate default single-precision SH4a code" },
506 #endif
507 #ifndef TARGET_SWITCH_SH4A_NOFPU
508 #define TARGET_SWITCH_SH4A_NOFPU \
509 {"4a-nofpu", TARGET_NONE, "" },\
510 {"4a-nofpu", SELECT_SH4A_NOFPU, "Generate SH4a FPU-less code" },
511 #endif
512 #ifndef TARGET_SWITCH_SH4AL
513 #define TARGET_SWITCH_SH4AL \
514 {"4al", TARGET_NONE, "" },\
515 {"4al", SELECT_SH4A_NOFPU, "Generate SH4al-dsp code" },
516 #endif
517 #ifndef TARGET_SWITCH_SH5_64MEDIA
518 #define TARGET_SWITCH_SH5_64MEDIA \
519 {"5-64media", TARGET_NONE, "" }, \
520 {"5-64media", SELECT_SH5_64MEDIA, "Generate 64-bit SHmedia code" },
521 #endif
522 #ifndef TARGET_SWITCH_SH5_64MEDIA_NOFPU
523 #define TARGET_SWITCH_SH5_64MEDIA_NOFPU \
524 {"5-64media-nofpu", TARGET_NONE, "" }, \
525 {"5-64media-nofpu", SELECT_SH5_64MEDIA_NOFPU, "Generate 64-bit FPU-less SHmedia code" },
526 #endif
527 #ifndef TARGET_SWITCHES_SH5_32MEDIA
528 #define TARGET_SWITCHES_SH5_32MEDIA \
529 {"5-32media", TARGET_NONE, "" }, \
530 {"5-32media", SELECT_SH5_32MEDIA, "Generate 32-bit SHmedia code" }, \
531 {"5-compact", TARGET_NONE, "" }, \
532 {"5-compact", SELECT_SH5_COMPACT, "Generate SHcompact code" },
533 #endif
534 #ifndef TARGET_SWITCHES_SH5_32MEDIA_NOFPU
535 #define TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
536 {"5-32media-nofpu", TARGET_NONE, "" }, \
537 {"5-32media-nofpu", SELECT_SH5_32MEDIA_NOFPU, "Generate 32-bit FPU-less SHmedia code" }, \
538 {"5-compact-nofpu", TARGET_NONE, "" }, \
539 {"5-compact-nofpu", SELECT_SH5_COMPACT_NOFPU, "Generate FPU-less SHcompact code" },
540 #endif
541
542 #define TARGET_SWITCHES \
543 { TARGET_SWITCH_SH1 \
544 TARGET_SWITCH_SH2 \
545 TARGET_SWITCH_SH2A_SINGLE_ONLY \
546 TARGET_SWITCH_SH2A_SINGLE \
547 TARGET_SWITCH_SH2A_NOFPU \
548 TARGET_SWITCH_SH2A \
549 TARGET_SWITCH_SH2E \
550 TARGET_SWITCH_SH3 \
551 TARGET_SWITCH_SH3E \
552 TARGET_SWITCH_SH4_SINGLE_ONLY \
553 TARGET_SWITCH_SH4_SINGLE \
554 TARGET_SWITCH_SH4_NOFPU \
555 TARGET_SWITCH_SH4 \
556 TARGET_SWITCH_SH4A_SINGLE_ONLY \
557 TARGET_SWITCH_SH4A_SINGLE \
558 TARGET_SWITCH_SH4A_NOFPU \
559 TARGET_SWITCH_SH4A \
560 TARGET_SWITCH_SH4AL \
561 TARGET_SWITCH_SH5_64MEDIA \
562 TARGET_SWITCH_SH5_64MEDIA_NOFPU \
563 TARGET_SWITCHES_SH5_32MEDIA \
564 TARGET_SWITCHES_SH5_32MEDIA_NOFPU \
565 {"b", -LITTLE_ENDIAN_BIT, "Generate code in big endian mode" }, \
566 {"bigtable", BIGTABLE_BIT, "Generate 32-bit offsets in switch tables" }, \
567 {"dalign", DALIGN_BIT, "Aligns doubles at 64-bit boundaries" }, \
568 {"fmovd", FMOVD_BIT, "" }, \
569 {"hitachi", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
570 {"renesas", HITACHI_BIT, "Follow Renesas (formerly Hitachi) / SuperH calling conventions" }, \
571 {"no-renesas",-HITACHI_BIT,"Follow the GCC calling conventions" }, \
572 {"nomacsave", NOMACSAVE_BIT, "Mark MAC register as call-clobbered" }, \
573 {"ieee", IEEE_BIT, "Increase the IEEE compliance for floating-point code" }, \
574 {"isize", ISIZE_BIT, "" }, \
575 {"l", LITTLE_ENDIAN_BIT, "Generate code in little endian mode" }, \
576 {"no-ieee", -IEEE_BIT, "" }, \
577 {"padstruct", PADSTRUCT_BIT, "" }, \
578 {"prefergot", PREFERGOT_BIT, "Emit function-calls using global offset table when generating PIC" }, \
579 {"relax", RELAX_BIT, "Shorten address references during linking" }, \
580 {"space", SPACE_BIT, "Deprecated. Use -Os instead" }, \
581 {"usermode", USERMODE_BIT, "Generate library function call to invalidate instruction cache entries after fixing trampoline" }, \
582 SUBTARGET_SWITCHES \
583 {"", TARGET_DEFAULT, "" } \
584 }
585
586 /* This are meant to be redefined in the host dependent files */
587 #define SUBTARGET_SWITCHES
588
589 /* This defaults us to big-endian. */
590 #ifndef TARGET_ENDIAN_DEFAULT
591 #define TARGET_ENDIAN_DEFAULT 0
592 #endif
593
594 #define TARGET_DEFAULT (TARGET_CPU_DEFAULT|TARGET_ENDIAN_DEFAULT)
595
596 #ifndef SH_MULTILIB_CPU_DEFAULT
597 #define SH_MULTILIB_CPU_DEFAULT "m1"
598 #endif
599
600 #if TARGET_ENDIAN_DEFAULT
601 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
602 #else
603 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
604 #endif
605
606 #define CPP_SPEC " %(subtarget_cpp_spec) "
607
608 #ifndef SUBTARGET_CPP_SPEC
609 #define SUBTARGET_CPP_SPEC ""
610 #endif
611
612 #ifndef SUBTARGET_EXTRA_SPECS
613 #define SUBTARGET_EXTRA_SPECS
614 #endif
615
616 #define EXTRA_SPECS \
617 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
618 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
619 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
620 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
621 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
622 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
623 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
624 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
625 SUBTARGET_EXTRA_SPECS
626
627 #if TARGET_CPU_DEFAULT & HARD_SH4_BIT
628 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
629 #else
630 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
631 #endif
632
633 #define SH_ASM_SPEC \
634 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
635 %(subtarget_asm_isa_spec) %{m4al:-dsp}"
636
637 #define ASM_SPEC SH_ASM_SPEC
638
639 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
640 #if TARGET_ENDIAN_DEFAULT == LITTLE_ENDIAN_BIT
641 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
642 #else
643 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
644 #endif
645 #endif
646
647 #define SUBTARGET_ASM_ISA_SPEC ""
648
649 #define LINK_EMUL_PREFIX "sh%{ml:l}"
650
651 #if TARGET_CPU_DEFAULT & SH5_BIT
652 #if TARGET_CPU_DEFAULT & SH_E_BIT
653 #define LINK_DEFAULT_CPU_EMUL "32"
654 #if TARGET_CPU_DEFAULT & SH1_BIT
655 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
656 #else
657 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
658 #endif /* SH1_BIT */
659 #else /* !SH_E_BIT */
660 #define LINK_DEFAULT_CPU_EMUL "64"
661 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
662 #endif /* SH_E_BIT */
663 #define ASM_ISA_DEFAULT_SPEC \
664 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
665 #else /* !SH5_BIT */
666 #define LINK_DEFAULT_CPU_EMUL ""
667 #define ASM_ISA_DEFAULT_SPEC ""
668 #endif /* SH5_BIT */
669
670 #define SUBTARGET_LINK_EMUL_SUFFIX ""
671 #define SUBTARGET_LINK_SPEC ""
672
673 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
674 so that we can undo the damage without code replication. */
675 #define LINK_SPEC SH_LINK_SPEC
676
677 #define SH_LINK_SPEC "\
678 -m %(link_emul_prefix)\
679 %{m5-compact*|m5-32media*:32}\
680 %{m5-64media*:64}\
681 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
682 %(subtarget_link_emul_suffix) \
683 %{mrelax:-relax} %(subtarget_link_spec)"
684
685 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
686 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
687 do { \
688 if (LEVEL) \
689 flag_omit_frame_pointer = -1; \
690 if (SIZE) \
691 target_flags |= SPACE_BIT; \
692 if (TARGET_SHMEDIA && LEVEL > 1) \
693 { \
694 flag_branch_target_load_optimize = 1; \
695 if (! (SIZE)) \
696 target_flags |= SAVE_ALL_TR_BIT; \
697 } \
698 } while (0)
699
700 #define ASSEMBLER_DIALECT assembler_dialect
701
702 extern int assembler_dialect;
703
704 #define OVERRIDE_OPTIONS \
705 do { \
706 int regno; \
707 \
708 sh_cpu = CPU_SH1; \
709 assembler_dialect = 0; \
710 if (TARGET_SH2) \
711 sh_cpu = CPU_SH2; \
712 if (TARGET_SH2E) \
713 sh_cpu = CPU_SH2E; \
714 if (TARGET_SH2A) \
715 { \
716 sh_cpu = CPU_SH2A; \
717 if (TARGET_SH2A_DOUBLE) \
718 target_flags |= FMOVD_BIT; \
719 } \
720 if (TARGET_SH3) \
721 sh_cpu = CPU_SH3; \
722 if (TARGET_SH3E) \
723 sh_cpu = CPU_SH3E; \
724 if (TARGET_SH4) \
725 { \
726 assembler_dialect = 1; \
727 sh_cpu = CPU_SH4; \
728 } \
729 if (TARGET_SH4A_ARCH) \
730 { \
731 assembler_dialect = 1; \
732 sh_cpu = CPU_SH4A; \
733 } \
734 if (TARGET_SH5) \
735 { \
736 sh_cpu = CPU_SH5; \
737 target_flags |= DALIGN_BIT; \
738 if (TARGET_FPU_ANY \
739 && ! (TARGET_SHCOMPACT && TARGET_LITTLE_ENDIAN)) \
740 target_flags |= FMOVD_BIT; \
741 if (TARGET_SHMEDIA) \
742 { \
743 /* There are no delay slots on SHmedia. */ \
744 flag_delayed_branch = 0; \
745 /* Relaxation isn't yet supported for SHmedia */ \
746 target_flags &= ~RELAX_BIT; \
747 } \
748 /* -fprofile-arcs needs a working libgcov . In unified tree \
749 configurations with newlib, this requires to configure with \
750 --with-newlib --with-headers. But there is no way to check \
751 here we have a working libgcov, so just assume that we have. */\
752 if (profile_flag) \
753 { \
754 warning ("Profiling is not supported on this target."); \
755 profile_flag = profile_arc_flag = 0; \
756 } \
757 } \
758 else \
759 { \
760 /* Only the sh64-elf assembler fully supports .quad properly. */\
761 targetm.asm_out.aligned_op.di = NULL; \
762 targetm.asm_out.unaligned_op.di = NULL; \
763 } \
764 if (TARGET_FMOVD) \
765 reg_class_from_letter['e' - 'a'] = NO_REGS; \
766 \
767 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
768 if (! VALID_REGISTER_P (regno)) \
769 sh_register_names[regno][0] = '\0'; \
770 \
771 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
772 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
773 sh_additional_register_names[regno][0] = '\0'; \
774 \
775 if (flag_omit_frame_pointer < 0) \
776 { \
777 /* The debugging information is sufficient, \
778 but gdb doesn't implement this yet */ \
779 if (0) \
780 flag_omit_frame_pointer \
781 = (PREFERRED_DEBUGGING_TYPE == DWARF_DEBUG \
782 || PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
783 else \
784 flag_omit_frame_pointer = 0; \
785 } \
786 \
787 if (flag_pic && ! TARGET_PREFERGOT) \
788 flag_no_function_cse = 1; \
789 \
790 if (SMALL_REGISTER_CLASSES) \
791 { \
792 /* Never run scheduling before reload, since that can \
793 break global alloc, and generates slower code anyway due \
794 to the pressure on R0. */ \
795 /* Enable sched1 for SH4; ready queue will be reordered by \
796 the target hooks when pressure is high. We can not do this for \
797 SH3 and lower as they give spill failures for R0. */ \
798 if (!TARGET_HARD_SH4) \
799 flag_schedule_insns = 0; \
800 } \
801 \
802 if (align_loops == 0) \
803 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
804 if (align_jumps == 0) \
805 align_jumps = 1 << CACHE_LOG; \
806 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
807 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
808 \
809 /* Allocation boundary (in *bytes*) for the code of a function. \
810 SH1: 32 bit alignment is faster, because instructions are always \
811 fetched as a pair from a longword boundary. \
812 SH2 .. SH5 : align to cache line start. */ \
813 if (align_functions == 0) \
814 align_functions \
815 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
816 /* The linker relaxation code breaks when a function contains \
817 alignments that are larger than that at the start of a \
818 compilation unit. */ \
819 if (TARGET_RELAX) \
820 { \
821 int min_align \
822 = align_loops > align_jumps ? align_loops : align_jumps; \
823 \
824 /* Also take possible .long constants / mova tables int account. */\
825 if (min_align < 4) \
826 min_align = 4; \
827 if (align_functions < min_align) \
828 align_functions = min_align; \
829 } \
830 } while (0)
831 \f
832 /* Target machine storage layout. */
833
834 /* Define this if most significant bit is lowest numbered
835 in instructions that operate on numbered bit-fields. */
836
837 #define BITS_BIG_ENDIAN 0
838
839 /* Define this if most significant byte of a word is the lowest numbered. */
840 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
841
842 /* Define this if most significant word of a multiword number is the lowest
843 numbered. */
844 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
845
846 /* Define this to set the endianness to use in libgcc2.c, which can
847 not depend on target_flags. */
848 #if defined(__LITTLE_ENDIAN__)
849 #define LIBGCC2_WORDS_BIG_ENDIAN 0
850 #else
851 #define LIBGCC2_WORDS_BIG_ENDIAN 1
852 #endif
853
854 #define MAX_BITS_PER_WORD 64
855
856 /* Width in bits of an `int'. We want just 32-bits, even if words are
857 longer. */
858 #define INT_TYPE_SIZE 32
859
860 /* Width in bits of a `long'. */
861 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
862
863 /* Width in bits of a `long long'. */
864 #define LONG_LONG_TYPE_SIZE 64
865
866 /* Width in bits of a `long double'. */
867 #define LONG_DOUBLE_TYPE_SIZE 64
868
869 /* Width of a word, in units (bytes). */
870 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
871 #define MIN_UNITS_PER_WORD 4
872
873 /* Scaling factor for Dwarf data offsets for CFI information.
874 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
875 SHmedia; however, since we do partial register saves for the registers
876 visible to SHcompact, and for target registers for SHMEDIA32, we have
877 to allow saves that are only 4-byte aligned. */
878 #define DWARF_CIE_DATA_ALIGNMENT -4
879
880 /* Width in bits of a pointer.
881 See also the macro `Pmode' defined below. */
882 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
883
884 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
885 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
886
887 /* Boundary (in *bits*) on which stack pointer should be aligned. */
888 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
889
890 /* The log (base 2) of the cache line size, in bytes. Processors prior to
891 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
892 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
893 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
894
895 /* ABI given & required minimum allocation boundary (in *bits*) for the
896 code of a function. */
897 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
898
899 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
900 the vbit must go into the delta field of
901 pointers-to-member-functions. */
902 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
903 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
904
905 /* Alignment of field after `int : 0' in a structure. */
906 #define EMPTY_FIELD_BOUNDARY 32
907
908 /* No data type wants to be aligned rounder than this. */
909 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
910
911 /* The best alignment to use in cases where we have a choice. */
912 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
913
914 /* Make strings word-aligned so strcpy from constants will be faster. */
915 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
916 ((TREE_CODE (EXP) == STRING_CST \
917 && (ALIGN) < FASTEST_ALIGNMENT) \
918 ? FASTEST_ALIGNMENT : (ALIGN))
919
920 /* get_mode_alignment assumes complex values are always held in multiple
921 registers, but that is not the case on the SH; CQImode and CHImode are
922 held in a single integer register. SH5 also holds CSImode and SCmode
923 values in integer registers. This is relevant for argument passing on
924 SHcompact as we use a stack temp in order to pass CSImode by reference. */
925 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
926 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
927 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
928 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
929 : (unsigned) ALIGN)
930
931 /* Make arrays of chars word-aligned for the same reasons. */
932 #define DATA_ALIGNMENT(TYPE, ALIGN) \
933 (TREE_CODE (TYPE) == ARRAY_TYPE \
934 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
935 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
936
937 /* Number of bits which any structure or union's size must be a
938 multiple of. Each structure or union's size is rounded up to a
939 multiple of this. */
940 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
941
942 /* Set this nonzero if move instructions will actually fail to work
943 when given unaligned data. */
944 #define STRICT_ALIGNMENT 1
945
946 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
947 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
948 barrier_align (LABEL_AFTER_BARRIER)
949
950 #define LOOP_ALIGN(A_LABEL) \
951 ((! optimize || TARGET_HARVARD || TARGET_SMALLCODE) \
952 ? 0 : sh_loop_align (A_LABEL))
953
954 #define LABEL_ALIGN(A_LABEL) \
955 ( \
956 (PREV_INSN (A_LABEL) \
957 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
958 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
959 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
960 /* explicit alignment insn in constant tables. */ \
961 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
962 : 0)
963
964 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
965 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
966
967 /* The base two logarithm of the known minimum alignment of an insn length. */
968 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
969 (GET_CODE (A_INSN) == INSN \
970 ? 1 << TARGET_SHMEDIA \
971 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
972 ? 1 << TARGET_SHMEDIA \
973 : CACHE_LOG)
974 \f
975 /* Standard register usage. */
976
977 /* Register allocation for the Renesas calling convention:
978
979 r0 arg return
980 r1..r3 scratch
981 r4..r7 args in
982 r8..r13 call saved
983 r14 frame pointer/call saved
984 r15 stack pointer
985 ap arg pointer (doesn't really exist, always eliminated)
986 pr subroutine return address
987 t t bit
988 mach multiply/accumulate result, high part
989 macl multiply/accumulate result, low part.
990 fpul fp/int communication register
991 rap return address pointer register
992 fr0 fp arg return
993 fr1..fr3 scratch floating point registers
994 fr4..fr11 fp args in
995 fr12..fr15 call saved floating point registers */
996
997 #define MAX_REGISTER_NAME_LENGTH 5
998 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
999
1000 #define SH_REGISTER_NAMES_INITIALIZER \
1001 { \
1002 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1003 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1004 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
1005 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
1006 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
1007 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
1008 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
1009 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
1010 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
1011 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
1012 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
1013 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
1014 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
1015 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
1016 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
1017 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
1018 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
1019 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
1020 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
1021 "rap" \
1022 }
1023
1024 #define REGNAMES_ARR_INDEX_1(index) \
1025 (sh_register_names[index])
1026 #define REGNAMES_ARR_INDEX_2(index) \
1027 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
1028 #define REGNAMES_ARR_INDEX_4(index) \
1029 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
1030 #define REGNAMES_ARR_INDEX_8(index) \
1031 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
1032 #define REGNAMES_ARR_INDEX_16(index) \
1033 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
1034 #define REGNAMES_ARR_INDEX_32(index) \
1035 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
1036 #define REGNAMES_ARR_INDEX_64(index) \
1037 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
1038
1039 #define REGISTER_NAMES \
1040 { \
1041 REGNAMES_ARR_INDEX_64 (0), \
1042 REGNAMES_ARR_INDEX_64 (64), \
1043 REGNAMES_ARR_INDEX_8 (128), \
1044 REGNAMES_ARR_INDEX_8 (136), \
1045 REGNAMES_ARR_INDEX_8 (144), \
1046 REGNAMES_ARR_INDEX_1 (152) \
1047 }
1048
1049 #define ADDREGNAMES_SIZE 32
1050 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
1051 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
1052 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
1053
1054 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
1055 { \
1056 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
1057 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
1058 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
1059 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
1060 }
1061
1062 #define ADDREGNAMES_REGNO(index) \
1063 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
1064 : (-1))
1065
1066 #define ADDREGNAMES_ARR_INDEX_1(index) \
1067 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
1068 #define ADDREGNAMES_ARR_INDEX_2(index) \
1069 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
1070 #define ADDREGNAMES_ARR_INDEX_4(index) \
1071 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
1072 #define ADDREGNAMES_ARR_INDEX_8(index) \
1073 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1074 #define ADDREGNAMES_ARR_INDEX_16(index) \
1075 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1076 #define ADDREGNAMES_ARR_INDEX_32(index) \
1077 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1078
1079 #define ADDITIONAL_REGISTER_NAMES \
1080 { \
1081 ADDREGNAMES_ARR_INDEX_32 (0) \
1082 }
1083
1084 /* Number of actual hardware registers.
1085 The hardware registers are assigned numbers for the compiler
1086 from 0 to just below FIRST_PSEUDO_REGISTER.
1087 All registers that the compiler knows about must be given numbers,
1088 even those that are not normally considered general registers. */
1089
1090 /* There are many other relevant definitions in sh.md's md_constants. */
1091
1092 #define FIRST_GENERAL_REG R0_REG
1093 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1094 #define FIRST_FP_REG DR0_REG
1095 #define LAST_FP_REG (FIRST_FP_REG + \
1096 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1097 #define FIRST_XD_REG XD0_REG
1098 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1099 #define FIRST_TARGET_REG TR0_REG
1100 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1101
1102 #define GENERAL_REGISTER_P(REGNO) \
1103 IN_RANGE ((REGNO), \
1104 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1105 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1106
1107 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1108 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG))
1109
1110 #define FP_REGISTER_P(REGNO) \
1111 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1112
1113 #define XD_REGISTER_P(REGNO) \
1114 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1115
1116 #define FP_OR_XD_REGISTER_P(REGNO) \
1117 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1118
1119 #define FP_ANY_REGISTER_P(REGNO) \
1120 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1121
1122 #define SPECIAL_REGISTER_P(REGNO) \
1123 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1124 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1125
1126 #define TARGET_REGISTER_P(REGNO) \
1127 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1128
1129 #define SHMEDIA_REGISTER_P(REGNO) \
1130 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1131 || TARGET_REGISTER_P (REGNO))
1132
1133 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1134 that should be fixed. */
1135 #define VALID_REGISTER_P(REGNO) \
1136 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1137 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1138 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1139 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1140
1141 /* The mode that should be generally used to store a register by
1142 itself in the stack, or to load it back. */
1143 #define REGISTER_NATURAL_MODE(REGNO) \
1144 (FP_REGISTER_P (REGNO) ? SFmode \
1145 : XD_REGISTER_P (REGNO) ? DFmode \
1146 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1147 ? DImode \
1148 : SImode)
1149
1150 #define FIRST_PSEUDO_REGISTER 153
1151
1152 /* 1 for registers that have pervasive standard uses
1153 and are not available for the register allocator.
1154
1155 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1156 It is 32 bits wide for SH2. */
1157
1158 #define FIXED_REGISTERS \
1159 { \
1160 /* Regular registers. */ \
1161 0, 0, 0, 0, 0, 0, 0, 0, \
1162 0, 0, 0, 0, 0, 0, 0, 1, \
1163 /* r16 is reserved, r18 is the former pr. */ \
1164 1, 0, 0, 0, 0, 0, 0, 0, \
1165 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1166 /* r26 is a global variable data pointer; r27 is for constants. */ \
1167 1, 1, 1, 1, 0, 0, 0, 0, \
1168 0, 0, 0, 0, 0, 0, 0, 0, \
1169 0, 0, 0, 0, 0, 0, 0, 0, \
1170 0, 0, 0, 0, 0, 0, 0, 0, \
1171 0, 0, 0, 0, 0, 0, 0, 1, \
1172 /* FP registers. */ \
1173 0, 0, 0, 0, 0, 0, 0, 0, \
1174 0, 0, 0, 0, 0, 0, 0, 0, \
1175 0, 0, 0, 0, 0, 0, 0, 0, \
1176 0, 0, 0, 0, 0, 0, 0, 0, \
1177 0, 0, 0, 0, 0, 0, 0, 0, \
1178 0, 0, 0, 0, 0, 0, 0, 0, \
1179 0, 0, 0, 0, 0, 0, 0, 0, \
1180 0, 0, 0, 0, 0, 0, 0, 0, \
1181 /* Branch target registers. */ \
1182 0, 0, 0, 0, 0, 0, 0, 0, \
1183 /* XD registers. */ \
1184 0, 0, 0, 0, 0, 0, 0, 0, \
1185 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1186 1, 1, 1, 1, 1, 1, 0, 1, \
1187 /*"rap" */ \
1188 1, \
1189 }
1190
1191 /* 1 for registers not available across function calls.
1192 These must include the FIXED_REGISTERS and also any
1193 registers that can be used without being saved.
1194 The latter must include the registers where values are returned
1195 and the register where structure-value addresses are passed.
1196 Aside from that, you can include as many other registers as you like. */
1197
1198 #define CALL_USED_REGISTERS \
1199 { \
1200 /* Regular registers. */ \
1201 1, 1, 1, 1, 1, 1, 1, 1, \
1202 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1203 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1204 across SH5 function calls. */ \
1205 0, 0, 0, 0, 0, 0, 0, 1, \
1206 1, 1, 1, 1, 1, 1, 1, 1, \
1207 1, 1, 1, 1, 0, 0, 0, 0, \
1208 0, 0, 0, 0, 1, 1, 1, 1, \
1209 1, 1, 1, 1, 0, 0, 0, 0, \
1210 0, 0, 0, 0, 0, 0, 0, 0, \
1211 0, 0, 0, 0, 1, 1, 1, 1, \
1212 /* FP registers. */ \
1213 1, 1, 1, 1, 1, 1, 1, 1, \
1214 1, 1, 1, 1, 0, 0, 0, 0, \
1215 1, 1, 1, 1, 1, 1, 1, 1, \
1216 1, 1, 1, 1, 1, 1, 1, 1, \
1217 1, 1, 1, 1, 0, 0, 0, 0, \
1218 0, 0, 0, 0, 0, 0, 0, 0, \
1219 0, 0, 0, 0, 0, 0, 0, 0, \
1220 0, 0, 0, 0, 0, 0, 0, 0, \
1221 /* Branch target registers. */ \
1222 1, 1, 1, 1, 1, 0, 0, 0, \
1223 /* XD registers. */ \
1224 1, 1, 1, 1, 1, 1, 0, 0, \
1225 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1226 1, 1, 1, 1, 1, 1, 1, 1, \
1227 /*"rap" */ \
1228 1, \
1229 }
1230
1231 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1232 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1233 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1234
1235 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1236 across SHcompact function calls. We can't tell whether a called
1237 function is SHmedia or SHcompact, so we assume it may be when
1238 compiling SHmedia code with the 32-bit ABI, since that's the only
1239 ABI that can be linked with SHcompact code. */
1240 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1241 (TARGET_SHMEDIA32 \
1242 && GET_MODE_SIZE (MODE) > 4 \
1243 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1244 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1245 || TARGET_REGISTER_P (REGNO) \
1246 || (REGNO) == PR_MEDIA_REG))
1247
1248 /* Return number of consecutive hard regs needed starting at reg REGNO
1249 to hold something of mode MODE.
1250 This is ordinarily the length in words of a value of mode MODE
1251 but can be less for certain modes in special long registers.
1252
1253 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1254
1255 #define HARD_REGNO_NREGS(REGNO, MODE) \
1256 (XD_REGISTER_P (REGNO) \
1257 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1258 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1259 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1260 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1261
1262 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1263 We can allow any mode in any general register. The special registers
1264 only allow SImode. Don't allow any mode in the PR. */
1265
1266 /* We cannot hold DCmode values in the XD registers because alter_reg
1267 handles subregs of them incorrectly. We could work around this by
1268 spacing the XD registers like the DR registers, but this would require
1269 additional memory in every compilation to hold larger register vectors.
1270 We could hold SFmode / SCmode values in XD registers, but that
1271 would require a tertiary reload when reloading from / to memory,
1272 and a secondary reload to reload from / to general regs; that
1273 seems to be a loosing proposition. */
1274 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1275 it won't be ferried through GP registers first. */
1276 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1277 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1278 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1279 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1280 ? 1 \
1281 : (MODE) == V2SFmode \
1282 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1283 || GENERAL_REGISTER_P (REGNO)) \
1284 : (MODE) == V4SFmode \
1285 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1286 || (! TARGET_SHMEDIA && GENERAL_REGISTER_P (REGNO))) \
1287 : (MODE) == V16SFmode \
1288 ? (TARGET_SHMEDIA \
1289 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1290 : (REGNO) == FIRST_XD_REG) \
1291 : FP_REGISTER_P (REGNO) \
1292 ? ((MODE) == SFmode || (MODE) == SImode \
1293 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1294 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1295 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1296 || (MODE) == V2SFmode || (MODE) == TImode))) \
1297 && (((REGNO) - FIRST_FP_REG) & 1) == 0)) \
1298 : XD_REGISTER_P (REGNO) \
1299 ? (MODE) == DFmode \
1300 : TARGET_REGISTER_P (REGNO) \
1301 ? ((MODE) == DImode || (MODE) == SImode) \
1302 : (REGNO) == PR_REG ? (MODE) == SImode \
1303 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1304 : 1)
1305
1306 /* Value is 1 if it is a good idea to tie two pseudo registers
1307 when one has mode MODE1 and one has mode MODE2.
1308 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1309 for any hard reg, then this must be 0 for correct output.
1310 That's the case for xd registers: we don't hold SFmode values in
1311 them, so we can't tie an SFmode pseudos with one in another
1312 floating-point mode. */
1313
1314 #define MODES_TIEABLE_P(MODE1, MODE2) \
1315 ((MODE1) == (MODE2) \
1316 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1317 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1318 && (GET_MODE_SIZE (MODE2) <= 4)) \
1319 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1320
1321 /* A C expression that is nonzero if hard register NEW_REG can be
1322 considered for use as a rename register for OLD_REG register */
1323
1324 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1325 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1326
1327 /* Specify the registers used for certain standard purposes.
1328 The values of these macros are register numbers. */
1329
1330 /* Define this if the program counter is overloaded on a register. */
1331 /* #define PC_REGNUM 15*/
1332
1333 /* Register to use for pushing function arguments. */
1334 #define STACK_POINTER_REGNUM SP_REG
1335
1336 /* Base register for access to local variables of the function. */
1337 #define FRAME_POINTER_REGNUM FP_REG
1338
1339 /* Fake register that holds the address on the stack of the
1340 current function's return address. */
1341 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1342
1343 /* Register to hold the addressing base for position independent
1344 code access to data items. */
1345 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1346
1347 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1348
1349 /* Value should be nonzero if functions must have frame pointers.
1350 Zero means the frame pointer need not be set up (and parms may be accessed
1351 via the stack pointer) in functions that seem suitable. */
1352
1353 #define FRAME_POINTER_REQUIRED 0
1354
1355 /* Definitions for register eliminations.
1356
1357 We have three registers that can be eliminated on the SH. First, the
1358 frame pointer register can often be eliminated in favor of the stack
1359 pointer register. Secondly, the argument pointer register can always be
1360 eliminated; it is replaced with either the stack or frame pointer.
1361 Third, there is the return address pointer, which can also be replaced
1362 with either the stack or the frame pointer. */
1363
1364 /* This is an array of structures. Each structure initializes one pair
1365 of eliminable registers. The "from" register number is given first,
1366 followed by "to". Eliminations of the same "from" register are listed
1367 in order of preference. */
1368
1369 /* If you add any registers here that are not actually hard registers,
1370 and that have any alternative of elimination that doesn't always
1371 apply, you need to amend calc_live_regs to exclude it, because
1372 reload spills all eliminable registers where it sees an
1373 can_eliminate == 0 entry, thus making them 'live' .
1374 If you add any hard registers that can be eliminated in different
1375 ways, you have to patch reload to spill them only when all alternatives
1376 of elimination fail. */
1377
1378 #define ELIMINABLE_REGS \
1379 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1380 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1381 { RETURN_ADDRESS_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1382 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1383 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM},}
1384
1385 /* Given FROM and TO register numbers, say whether this elimination
1386 is allowed. */
1387 #define CAN_ELIMINATE(FROM, TO) \
1388 (!((FROM) == FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1389
1390 /* Define the offset between two registers, one to be eliminated, and the other
1391 its replacement, at the start of a routine. */
1392
1393 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1394 OFFSET = initial_elimination_offset ((FROM), (TO))
1395
1396 /* Base register for access to arguments of the function. */
1397 #define ARG_POINTER_REGNUM AP_REG
1398
1399 /* Register in which the static-chain is passed to a function. */
1400 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1401
1402 /* Don't default to pcc-struct-return, because we have already specified
1403 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1404 target hook. */
1405
1406 #define DEFAULT_PCC_STRUCT_RETURN 0
1407
1408 #define SHMEDIA_REGS_STACK_ADJUST() \
1409 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1410 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1411 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1412 : 0)
1413
1414 \f
1415 /* Define the classes of registers for register constraints in the
1416 machine description. Also define ranges of constants.
1417
1418 One of the classes must always be named ALL_REGS and include all hard regs.
1419 If there is more than one class, another class must be named NO_REGS
1420 and contain no registers.
1421
1422 The name GENERAL_REGS must be the name of a class (or an alias for
1423 another name such as ALL_REGS). This is the class of registers
1424 that is allowed by "g" or "r" in a register constraint.
1425 Also, registers outside this class are allocated only when
1426 instructions express preferences for them.
1427
1428 The classes must be numbered in nondecreasing order; that is,
1429 a larger-numbered class must never be contained completely
1430 in a smaller-numbered class.
1431
1432 For any two classes, it is very desirable that there be another
1433 class that represents their union. */
1434
1435 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1436 be used as the destination of some of the arithmetic ops. There are
1437 also some special purpose registers; the T bit register, the
1438 Procedure Return Register and the Multiply Accumulate Registers. */
1439 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1440 reg_class_subunion. We don't want to have an actual union class
1441 of these, because it would only be used when both classes are calculated
1442 to give the same cost, but there is only one FPUL register.
1443 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1444 applying to the actual instruction alternative considered. E.g., the
1445 y/r alternative of movsi_ie is considered to have no more cost that
1446 the r/r alternative, which is patently untrue. */
1447
1448 enum reg_class
1449 {
1450 NO_REGS,
1451 R0_REGS,
1452 PR_REGS,
1453 T_REGS,
1454 MAC_REGS,
1455 FPUL_REGS,
1456 SIBCALL_REGS,
1457 GENERAL_REGS,
1458 FP0_REGS,
1459 FP_REGS,
1460 DF_HI_REGS,
1461 DF_REGS,
1462 FPSCR_REGS,
1463 GENERAL_FP_REGS,
1464 TARGET_REGS,
1465 ALL_REGS,
1466 LIM_REG_CLASSES
1467 };
1468
1469 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1470
1471 /* Give names of register classes as strings for dump file. */
1472 #define REG_CLASS_NAMES \
1473 { \
1474 "NO_REGS", \
1475 "R0_REGS", \
1476 "PR_REGS", \
1477 "T_REGS", \
1478 "MAC_REGS", \
1479 "FPUL_REGS", \
1480 "SIBCALL_REGS", \
1481 "GENERAL_REGS", \
1482 "FP0_REGS", \
1483 "FP_REGS", \
1484 "DF_HI_REGS", \
1485 "DF_REGS", \
1486 "FPSCR_REGS", \
1487 "GENERAL_FP_REGS", \
1488 "TARGET_REGS", \
1489 "ALL_REGS", \
1490 }
1491
1492 /* Define which registers fit in which classes.
1493 This is an initializer for a vector of HARD_REG_SET
1494 of length N_REG_CLASSES. */
1495
1496 #define REG_CLASS_CONTENTS \
1497 { \
1498 /* NO_REGS: */ \
1499 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1500 /* R0_REGS: */ \
1501 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1502 /* PR_REGS: */ \
1503 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1504 /* T_REGS: */ \
1505 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1506 /* MAC_REGS: */ \
1507 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1508 /* FPUL_REGS: */ \
1509 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1510 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1511 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1512 /* GENERAL_REGS: */ \
1513 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x01020000 }, \
1514 /* FP0_REGS: */ \
1515 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1516 /* FP_REGS: */ \
1517 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1518 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1519 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1520 /* DF_REGS: */ \
1521 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1522 /* FPSCR_REGS: */ \
1523 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1524 /* GENERAL_FP_REGS: */ \
1525 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0102ff00 }, \
1526 /* TARGET_REGS: */ \
1527 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1528 /* ALL_REGS: */ \
1529 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x01ffffff }, \
1530 }
1531
1532 /* The same information, inverted:
1533 Return the class number of the smallest class containing
1534 reg number REGNO. This could be a conditional expression
1535 or could index an array. */
1536
1537 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1538 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1539
1540 /* When defined, the compiler allows registers explicitly used in the
1541 rtl to be used as spill registers but prevents the compiler from
1542 extending the lifetime of these registers. */
1543
1544 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1545
1546 /* The order in which register should be allocated. */
1547 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1548 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1549 spilled or used otherwise, we better have the FP_REGS allocated first. */
1550 #define REG_ALLOC_ORDER \
1551 {/* Caller-saved FPRs */ \
1552 65, 66, 67, 68, 69, 70, 71, 64, \
1553 72, 73, 74, 75, 80, 81, 82, 83, \
1554 84, 85, 86, 87, 88, 89, 90, 91, \
1555 92, 93, 94, 95, 96, 97, 98, 99, \
1556 /* Callee-saved FPRs */ \
1557 76, 77, 78, 79,100,101,102,103, \
1558 104,105,106,107,108,109,110,111, \
1559 112,113,114,115,116,117,118,119, \
1560 120,121,122,123,124,125,126,127, \
1561 136,137,138,139,140,141,142,143, \
1562 /* FPSCR */ 151, \
1563 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1564 1, 2, 3, 7, 6, 5, 4, 0, \
1565 8, 9, 17, 19, 20, 21, 22, 23, \
1566 36, 37, 38, 39, 40, 41, 42, 43, \
1567 60, 61, 62, \
1568 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1569 10, 11, 12, 13, 14, 18, \
1570 /* SH5 callee-saved GPRs */ \
1571 28, 29, 30, 31, 32, 33, 34, 35, \
1572 44, 45, 46, 47, 48, 49, 50, 51, \
1573 52, 53, 54, 55, 56, 57, 58, 59, \
1574 /* FPUL */ 150, \
1575 /* SH5 branch target registers */ \
1576 128,129,130,131,132,133,134,135, \
1577 /* Fixed registers */ \
1578 15, 16, 24, 25, 26, 27, 63,144, \
1579 145,146,147,148,149,152 }
1580
1581 /* The class value for index registers, and the one for base regs. */
1582 #define INDEX_REG_CLASS (TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1583 #define BASE_REG_CLASS GENERAL_REGS
1584
1585 /* Get reg_class from a letter such as appears in the machine
1586 description. */
1587 extern enum reg_class reg_class_from_letter[];
1588
1589 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1590 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1591 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1592 \f
1593 /* Overview of uppercase letter constraints:
1594 A: Addresses (constraint len == 3)
1595 Ac4: sh4 cache operations
1596 Ac5: sh5 cache operations
1597 Bxx: miscellaneous constraints
1598 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1599 fldi0 / fldi0 cases
1600 C: Constants other than only CONST_INT (constraint len == 3)
1601 C16: 16 bit constant, literal or symbolic
1602 Csy: label or symbol
1603 Cpg: non-explicit constants that can be directly loaded into a general
1604 purpose register in PIC code. like 's' except we don't allow
1605 PIC_DIRECT_ADDR_P
1606 IJKLMNOP: CONT_INT constants
1607 Ixx: signed xx bit
1608 J16: 0xffffffff00000000 | 0x00000000ffffffff
1609 Kxx: unsigned xx bit
1610 M: 1
1611 N: 0
1612 P27: 1 | 2 | 8 | 16
1613 Q: pc relative load operand
1614 Rxx: reserved for exotic register classes.
1615 S: extra memory (storage) constraints (constraint len == 3)
1616 Sua: unaligned memory operations
1617 W: vector
1618 Z: zero in any mode
1619
1620 unused CONST_INT constraint letters: LO
1621 unused EXTRA_CONSTRAINT letters: D T U Y */
1622
1623 #if 1 /* check that the transition went well. */
1624 #define CONSTRAINT_LEN(C,STR) \
1625 (((C) == 'L' || (C) == 'O' || (C) == 'D' || (C) == 'T' || (C) == 'U' \
1626 || (C) == 'Y' \
1627 || ((C) == 'I' \
1628 && (((STR)[1] != '0' && (STR)[1] != '1' && (STR)[1] != '2') \
1629 || (STR)[2] < '0' || (STR)[2] > '9')) \
1630 || ((C) == 'B' && ((STR)[1] != 's' || (STR)[2] != 'c')) \
1631 || ((C) == 'J' && ((STR)[1] != '1' || (STR)[2] != '6')) \
1632 || ((C) == 'K' && ((STR)[1] != '0' || (STR)[2] != '8')) \
1633 || ((C) == 'P' && ((STR)[1] != '2' || (STR)[2] != '7'))) \
1634 ? -1 \
1635 : ((C) == 'A' || (C) == 'B' || (C) == 'C' \
1636 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1637 || (C) == 'R' || (C) == 'S') \
1638 ? 3 \
1639 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1640 #else
1641 #define CONSTRAINT_LEN(C,STR) \
1642 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1643 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1644 || (C) == 'R' || (C) == 'S') \
1645 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1646 #endif
1647
1648 /* The letters I, J, K, L and M in a register constraint string
1649 can be used to stand for particular ranges of immediate operands.
1650 This macro defines what the ranges are.
1651 C is the letter, and VALUE is a constant value.
1652 Return 1 if VALUE is in the range specified by C.
1653 I08: arithmetic operand -127..128, as used in add, sub, etc
1654 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1655 P27: shift operand 1,2,8 or 16
1656 K08: logical operand 0..255, as used in and, or, etc.
1657 M: constant 1
1658 N: constant 0
1659 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1660 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1661 */
1662
1663 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1664 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1665 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1666 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1667 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1668 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1669 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1670 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1671 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1672 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1673 && TARGET_SH2A)
1674 #define CONST_OK_FOR_I(VALUE, STR) \
1675 ((STR)[1] == '0' && (STR)[2] == 6 ? CONST_OK_FOR_I06 (VALUE) \
1676 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1677 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1678 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1679 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1680 : 0)
1681
1682 #define CONST_OK_FOR_J16(VALUE) \
1683 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1684 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1685 #define CONST_OK_FOR_J(VALUE, STR) \
1686 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1687 : 0)
1688
1689 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1690 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1691 #define CONST_OK_FOR_K(VALUE, STR) \
1692 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1693 : 0)
1694 #define CONST_OK_FOR_P27(VALUE) \
1695 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1696 #define CONST_OK_FOR_P(VALUE, STR) \
1697 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1698 : 0)
1699 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1700 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1701 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1702 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1703 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1704 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1705 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1706 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1707 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1708 : 0)
1709
1710 /* Similar, but for floating constants, and defining letters G and H.
1711 Here VALUE is the CONST_DOUBLE rtx itself. */
1712
1713 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1714 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1715 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1716 : (C) == 'F')
1717
1718 /* Given an rtx X being reloaded into a reg required to be
1719 in class CLASS, return the class of reg to actually use.
1720 In general this is just CLASS; but on some machines
1721 in some cases it is preferable to use a more restrictive class. */
1722
1723 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1724 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1725 && (GET_CODE (X) == CONST_DOUBLE \
1726 || GET_CODE (X) == SYMBOL_REF) \
1727 ? GENERAL_REGS \
1728 : (CLASS)) \
1729
1730 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1731 ((((REGCLASS_HAS_FP_REG (CLASS) \
1732 && (GET_CODE (X) == REG \
1733 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1734 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1735 && TARGET_FMOVD)))) \
1736 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1737 && GET_CODE (X) == REG \
1738 && FP_REGISTER_P (REGNO (X)))) \
1739 && ! TARGET_SHMEDIA \
1740 && ((MODE) == SFmode || (MODE) == SImode)) \
1741 ? FPUL_REGS \
1742 : (((CLASS) == FPUL_REGS \
1743 || (REGCLASS_HAS_FP_REG (CLASS) \
1744 && ! TARGET_SHMEDIA && MODE == SImode)) \
1745 && (GET_CODE (X) == MEM \
1746 || (GET_CODE (X) == REG \
1747 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1748 || REGNO (X) == T_REG \
1749 || system_reg_operand (X, VOIDmode))))) \
1750 ? GENERAL_REGS \
1751 : ((CLASS) == TARGET_REGS \
1752 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1753 ? ((target_operand ((X), (MODE)) \
1754 && ! target_reg_operand ((X), (MODE))) \
1755 ? NO_REGS : GENERAL_REGS) \
1756 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1757 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1758 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1759 ? GENERAL_REGS \
1760 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1761 && TARGET_REGISTER_P (REGNO (X))) \
1762 ? GENERAL_REGS : NO_REGS)
1763
1764 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1765 ((REGCLASS_HAS_FP_REG (CLASS) \
1766 && ! TARGET_SHMEDIA \
1767 && immediate_operand ((X), (MODE)) \
1768 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1769 && (MODE) == SFmode && fldi_ok ())) \
1770 ? R0_REGS \
1771 : (CLASS == FPUL_REGS \
1772 && ((GET_CODE (X) == REG \
1773 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1774 || REGNO (X) == T_REG)) \
1775 || GET_CODE (X) == PLUS)) \
1776 ? GENERAL_REGS \
1777 : CLASS == FPUL_REGS && immediate_operand ((X), (MODE)) \
1778 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1779 ? GENERAL_REGS \
1780 : R0_REGS) \
1781 : (CLASS == FPSCR_REGS \
1782 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1783 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1784 ? GENERAL_REGS \
1785 : (REGCLASS_HAS_FP_REG (CLASS) \
1786 && TARGET_SHMEDIA \
1787 && immediate_operand ((X), (MODE)) \
1788 && (X) != CONST0_RTX (GET_MODE (X)) \
1789 && GET_MODE (X) != V4SFmode) \
1790 ? GENERAL_REGS \
1791 : SECONDARY_OUTPUT_RELOAD_CLASS((CLASS),(MODE),(X)))
1792
1793 /* Return the maximum number of consecutive registers
1794 needed to represent mode MODE in a register of class CLASS.
1795
1796 If TARGET_SHMEDIA, we need two FP registers per word.
1797 Otherwise we will need at most one register per word. */
1798 #define CLASS_MAX_NREGS(CLASS, MODE) \
1799 (TARGET_SHMEDIA \
1800 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1801 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1802 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1803
1804 /* If defined, gives a class of registers that cannot be used as the
1805 operand of a SUBREG that changes the mode of the object illegally. */
1806 /* ??? We need to renumber the internal numbers for the frnn registers
1807 when in little endian in order to allow mode size changes. */
1808
1809 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1810 sh_cannot_change_mode_class (FROM, TO, CLASS)
1811 \f
1812 /* Stack layout; function entry, exit and calling. */
1813
1814 /* Define the number of registers that can hold parameters.
1815 These macros are used only in other macro definitions below. */
1816
1817 #define NPARM_REGS(MODE) \
1818 (TARGET_FPU_ANY && (MODE) == SFmode \
1819 ? (TARGET_SH5 ? 12 : 8) \
1820 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1821 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1822 ? (TARGET_SH5 ? 12 : 8) \
1823 : (TARGET_SH5 ? 8 : 4))
1824
1825 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1826 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1827
1828 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1829 #define FIRST_FP_RET_REG FIRST_FP_REG
1830
1831 /* Define this if pushing a word on the stack
1832 makes the stack pointer a smaller address. */
1833 #define STACK_GROWS_DOWNWARD
1834
1835 /* Define this macro if the addresses of local variable slots are at
1836 negative offsets from the frame pointer.
1837
1838 The SH only has positive indexes, so grow the frame up. */
1839 /* #define FRAME_GROWS_DOWNWARD */
1840
1841 /* Offset from the frame pointer to the first local variable slot to
1842 be allocated. */
1843 #define STARTING_FRAME_OFFSET 0
1844
1845 /* If we generate an insn to push BYTES bytes,
1846 this says how many the stack pointer really advances by. */
1847 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1848 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1849 do correct alignment. */
1850 #if 0
1851 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1852 #endif
1853
1854 /* Offset of first parameter from the argument pointer register value. */
1855 #define FIRST_PARM_OFFSET(FNDECL) 0
1856
1857 /* Value is the number of byte of arguments automatically
1858 popped when returning from a subroutine call.
1859 FUNDECL is the declaration node of the function (as a tree),
1860 FUNTYPE is the data type of the function (as a tree),
1861 or for a library call it is an identifier node for the subroutine name.
1862 SIZE is the number of bytes of arguments passed on the stack.
1863
1864 On the SH, the caller does not pop any of its arguments that were passed
1865 on the stack. */
1866 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1867
1868 /* Value is the number of bytes of arguments automatically popped when
1869 calling a subroutine.
1870 CUM is the accumulated argument list.
1871
1872 On SHcompact, the call trampoline pops arguments off the stack. */
1873 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1874
1875 /* Some subroutine macros specific to this machine. */
1876
1877 #define BASE_RETURN_VALUE_REG(MODE) \
1878 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1879 ? FIRST_FP_RET_REG \
1880 : TARGET_FPU_ANY && (MODE) == SCmode \
1881 ? FIRST_FP_RET_REG \
1882 : (TARGET_FPU_DOUBLE \
1883 && ((MODE) == DFmode || (MODE) == SFmode \
1884 || (MODE) == DCmode || (MODE) == SCmode )) \
1885 ? FIRST_FP_RET_REG \
1886 : FIRST_RET_REG)
1887
1888 #define BASE_ARG_REG(MODE) \
1889 ((TARGET_SH2E && ((MODE) == SFmode)) \
1890 ? FIRST_FP_PARM_REG \
1891 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1892 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1893 ? FIRST_FP_PARM_REG \
1894 : FIRST_PARM_REG)
1895
1896 /* Define how to find the value returned by a function.
1897 VALTYPE is the data type of the value (as a tree).
1898 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1899 otherwise, FUNC is 0.
1900 For the SH, this is like LIBCALL_VALUE, except that we must change the
1901 mode like PROMOTE_MODE does.
1902 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1903 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1904
1905 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1906 gen_rtx_REG ( \
1907 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1908 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < UNITS_PER_WORD \
1909 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1910 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1911 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1912 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1913 || TREE_CODE (VALTYPE) == REAL_TYPE \
1914 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1915 && sh_promote_prototypes (VALTYPE) \
1916 ? (TARGET_SHMEDIA ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1917 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1918
1919 /* Define how to find the value returned by a library function
1920 assuming the value has mode MODE. */
1921 #define LIBCALL_VALUE(MODE) \
1922 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1923
1924 /* 1 if N is a possible register number for a function value. */
1925 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1926 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1927 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1928
1929 /* 1 if N is a possible register number for function argument passing. */
1930 /* ??? There are some callers that pass REGNO as int, and others that pass
1931 it as unsigned. We get warnings unless we do casts everywhere. */
1932 #define FUNCTION_ARG_REGNO_P(REGNO) \
1933 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1934 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1935 || (TARGET_FPU_ANY \
1936 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1937 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1938 + NPARM_REGS (SFmode))))
1939 \f
1940 /* Define a data type for recording info about an argument list
1941 during the scan of that argument list. This data type should
1942 hold all necessary information about the function itself
1943 and about the args processed so far, enough to enable macros
1944 such as FUNCTION_ARG to determine where the next arg should go.
1945
1946 On SH, this is a single integer, which is a number of words
1947 of arguments scanned so far (including the invisible argument,
1948 if any, which holds the structure-value-address).
1949 Thus NARGREGS or more means all following args should go on the stack. */
1950
1951 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1952 struct sh_args {
1953 int arg_count[2];
1954 int force_mem;
1955 /* Nonzero if a prototype is available for the function. */
1956 int prototype_p;
1957 /* The number of an odd floating-point register, that should be used
1958 for the next argument of type float. */
1959 int free_single_fp_reg;
1960 /* Whether we're processing an outgoing function call. */
1961 int outgoing;
1962 /* The number of general-purpose registers that should have been
1963 used to pass partial arguments, that are passed totally on the
1964 stack. On SHcompact, a call trampoline will pop them off the
1965 stack before calling the actual function, and, if the called
1966 function is implemented in SHcompact mode, the incoming arguments
1967 decoder will push such arguments back onto the stack. For
1968 incoming arguments, STACK_REGS also takes into account other
1969 arguments passed by reference, that the decoder will also push
1970 onto the stack. */
1971 int stack_regs;
1972 /* The number of general-purpose registers that should have been
1973 used to pass arguments, if the arguments didn't have to be passed
1974 by reference. */
1975 int byref_regs;
1976 /* Set as by shcompact_byref if the current argument is to be passed
1977 by reference. */
1978 int byref;
1979
1980 /* call_cookie is a bitmask used by call expanders, as well as
1981 function prologue and epilogues, to allow SHcompact to comply
1982 with the SH5 32-bit ABI, that requires 64-bit registers to be
1983 used even though only the lower 32-bit half is visible in
1984 SHcompact mode. The strategy is to call SHmedia trampolines.
1985
1986 The alternatives for each of the argument-passing registers are
1987 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1988 contents from the address in it; (d) add 8 to it, storing the
1989 result in the next register, then (c); (e) copy it from some
1990 floating-point register,
1991
1992 Regarding copies from floating-point registers, r2 may only be
1993 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1994 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1995 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1996 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1997 dr10.
1998
1999 The bit mask is structured as follows:
2000
2001 - 1 bit to tell whether to set up a return trampoline.
2002
2003 - 3 bits to count the number consecutive registers to pop off the
2004 stack.
2005
2006 - 4 bits for each of r9, r8, r7 and r6.
2007
2008 - 3 bits for each of r5, r4, r3 and r2.
2009
2010 - 3 bits set to 0 (the most significant ones)
2011
2012 3 2 1 0
2013 1098 7654 3210 9876 5432 1098 7654 3210
2014 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
2015 2223 3344 4555 6666 7777 8888 9999 SSS-
2016
2017 - If F is set, the register must be copied from an FP register,
2018 whose number is encoded in the remaining bits.
2019
2020 - Else, if L is set, the register must be loaded from the address
2021 contained in it. If the P bit is *not* set, the address of the
2022 following dword should be computed first, and stored in the
2023 following register.
2024
2025 - Else, if P is set, the register alone should be popped off the
2026 stack.
2027
2028 - After all this processing, the number of registers represented
2029 in SSS will be popped off the stack. This is an optimization
2030 for pushing/popping consecutive registers, typically used for
2031 varargs and large arguments partially passed in registers.
2032
2033 - If T is set, a return trampoline will be set up for 64-bit
2034 return values to be split into 2 32-bit registers. */
2035 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
2036 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
2037 #define CALL_COOKIE_STACKSEQ_SHIFT 1
2038 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
2039 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
2040 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
2041 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
2042 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
2043 #define CALL_COOKIE_INT_REG(REG, VAL) \
2044 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
2045 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
2046 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
2047 long call_cookie;
2048
2049 /* This is set to nonzero when the call in question must use the Renesas ABI,
2050 even without the -mrenesas option. */
2051 int renesas_abi;
2052 };
2053
2054 #define CUMULATIVE_ARGS struct sh_args
2055
2056 #define GET_SH_ARG_CLASS(MODE) \
2057 ((TARGET_FPU_ANY && (MODE) == SFmode) \
2058 ? SH_ARG_FLOAT \
2059 /* There's no mention of complex float types in the SH5 ABI, so we
2060 should presumably handle them as aggregate types. */ \
2061 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
2062 ? SH_ARG_INT \
2063 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2064 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
2065 ? SH_ARG_FLOAT : SH_ARG_INT)
2066
2067 #define ROUND_ADVANCE(SIZE) \
2068 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
2069
2070 /* Round a register number up to a proper boundary for an arg of mode
2071 MODE.
2072
2073 The SH doesn't care about double alignment, so we only
2074 round doubles to even regs when asked to explicitly. */
2075
2076 #define ROUND_REG(CUM, MODE) \
2077 (((TARGET_ALIGN_DOUBLE \
2078 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
2079 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
2080 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
2081 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
2082 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
2083 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
2084
2085 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2086 for a call to a function whose data type is FNTYPE.
2087 For a library call, FNTYPE is 0.
2088
2089 On SH, the offset always starts at 0: the first parm reg is always
2090 the same reg for a given argument class.
2091
2092 For TARGET_HITACHI, the structure value pointer is passed in memory. */
2093
2094 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
2095 do { \
2096 (CUM).arg_count[(int) SH_ARG_INT] = 0; \
2097 (CUM).arg_count[(int) SH_ARG_FLOAT] = 0; \
2098 (CUM).renesas_abi = sh_attr_renesas_p (FNTYPE) ? 1 : 0; \
2099 (CUM).force_mem \
2100 = ((TARGET_HITACHI || (CUM).renesas_abi) && (FNTYPE) \
2101 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
2102 (CUM).prototype_p = (FNTYPE) && TYPE_ARG_TYPES (FNTYPE); \
2103 (CUM).arg_count[(int) SH_ARG_INT] \
2104 = (TARGET_SH5 && (FNTYPE) \
2105 && aggregate_value_p (TREE_TYPE (FNTYPE), (FNDECL))); \
2106 (CUM).free_single_fp_reg = 0; \
2107 (CUM).outgoing = 1; \
2108 (CUM).stack_regs = 0; \
2109 (CUM).byref_regs = 0; \
2110 (CUM).byref = 0; \
2111 (CUM).call_cookie \
2112 = (CALL_COOKIE_RET_TRAMP \
2113 (TARGET_SHCOMPACT && (FNTYPE) \
2114 && (CUM).arg_count[(int) SH_ARG_INT] == 0 \
2115 && (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
2116 ? int_size_in_bytes (TREE_TYPE (FNTYPE)) \
2117 : GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (FNTYPE)))) > 4 \
2118 && (BASE_RETURN_VALUE_REG (TYPE_MODE (TREE_TYPE \
2119 (FNTYPE))) \
2120 == FIRST_RET_REG))); \
2121 } while (0)
2122
2123 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
2124 do { \
2125 INIT_CUMULATIVE_ARGS ((CUM), NULL_TREE, (LIBNAME), 0, 0); \
2126 (CUM).call_cookie \
2127 = (CALL_COOKIE_RET_TRAMP \
2128 (TARGET_SHCOMPACT && GET_MODE_SIZE (MODE) > 4 \
2129 && BASE_RETURN_VALUE_REG (MODE) == FIRST_RET_REG)); \
2130 } while (0)
2131
2132 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
2133 do { \
2134 INIT_CUMULATIVE_ARGS ((CUM), (FNTYPE), (LIBNAME), 0, 0); \
2135 (CUM).outgoing = 0; \
2136 } while (0)
2137
2138 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2139 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
2140 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2141 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
2142
2143 /* Return boolean indicating arg of mode MODE will be passed in a reg.
2144 This macro is only used in this file. */
2145
2146 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
2147 (((TYPE) == 0 \
2148 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
2149 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2150 || ! (AGGREGATE_TYPE_P (TYPE) \
2151 || (!TARGET_FPU_ANY \
2152 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2153 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2154 && ! (CUM).force_mem \
2155 && (TARGET_SH2E \
2156 ? ((MODE) == BLKmode \
2157 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2158 + int_size_in_bytes (TYPE)) \
2159 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2160 : ((ROUND_REG((CUM), (MODE)) \
2161 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2162 <= NPARM_REGS (MODE))) \
2163 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2164
2165 /* By accident we got stuck with passing SCmode on SH4 little endian
2166 in two registers that are nominally successive - which is different from
2167 two single SFmode values, where we take endianness translation into
2168 account. That does not work at all if an odd number of registers is
2169 already in use, so that got fixed, but library functions are still more
2170 likely to use complex numbers without mixing them with SFmode arguments
2171 (which in C would have to be structures), so for the sake of ABI
2172 compatibility the way SCmode values are passed when an even number of
2173 FP registers is in use remains different from a pair of SFmode values for
2174 now.
2175 I.e.:
2176 foo (double); a: fr5,fr4
2177 foo (float a, float b); a: fr5 b: fr4
2178 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2179 this should be the other way round...
2180 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2181 #define FUNCTION_ARG_SCmode_WART 1
2182
2183 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2184 register in SHcompact mode, it must be padded in the most
2185 significant end. This means that passing it by reference wouldn't
2186 pad properly on a big-endian machine. In this particular case, we
2187 pass this argument on the stack, in a way that the call trampoline
2188 will load its value into the appropriate register. */
2189 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2190 ((MODE) == BLKmode \
2191 && TARGET_SHCOMPACT \
2192 && ! TARGET_LITTLE_ENDIAN \
2193 && int_size_in_bytes (TYPE) > 4 \
2194 && int_size_in_bytes (TYPE) < 8)
2195
2196 /* Minimum alignment for an argument to be passed by callee-copy
2197 reference. We need such arguments to be aligned to 8 byte
2198 boundaries, because they'll be loaded using quad loads. */
2199 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2200
2201 #define FUNCTION_ARG_CALLEE_COPIES(CUM,MODE,TYPE,NAMED) \
2202 ((CUM).outgoing \
2203 && (((MODE) == BLKmode ? TYPE_ALIGN (TYPE) \
2204 : GET_MODE_ALIGNMENT (MODE)) \
2205 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0))
2206
2207 /* The SH5 ABI requires floating-point arguments to be passed to
2208 functions without a prototype in both an FP register and a regular
2209 register or the stack. When passing the argument in both FP and
2210 general-purpose registers, list the FP register first. */
2211 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2212 (gen_rtx_PARALLEL \
2213 ((MODE), \
2214 gen_rtvec (2, \
2215 gen_rtx_EXPR_LIST \
2216 (VOIDmode, \
2217 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2218 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2219 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2220 : NULL_RTX), \
2221 const0_rtx), \
2222 gen_rtx_EXPR_LIST \
2223 (VOIDmode, \
2224 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2225 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2226 + (CUM).arg_count[(int) SH_ARG_INT]) \
2227 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2228 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2229 const0_rtx))))
2230
2231 /* The SH5 ABI requires regular registers or stack slots to be
2232 reserved for floating-point arguments. Registers are taken care of
2233 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2234 Unfortunately, there's no way to just reserve a stack slot, so
2235 we'll end up needlessly storing a copy of the argument in the
2236 stack. For incoming arguments, however, the PARALLEL will be
2237 optimized to the register-only form, and the value in the stack
2238 slot won't be used at all. */
2239 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2240 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2241 ? gen_rtx_REG ((MODE), (REG)) \
2242 : gen_rtx_PARALLEL ((MODE), \
2243 gen_rtvec (2, \
2244 gen_rtx_EXPR_LIST \
2245 (VOIDmode, NULL_RTX, \
2246 const0_rtx), \
2247 gen_rtx_EXPR_LIST \
2248 (VOIDmode, gen_rtx_REG ((MODE), \
2249 (REG)), \
2250 const0_rtx))))
2251
2252 /* For an arg passed partly in registers and partly in memory,
2253 this is the number of registers used.
2254 For args passed entirely in registers or entirely in memory, zero.
2255
2256 We sometimes split args. */
2257
2258 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2259 ((! TARGET_SH5 \
2260 && PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
2261 && ! (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2262 && (ROUND_REG ((CUM), (MODE)) \
2263 + ((MODE) != BLKmode \
2264 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
2265 : ROUND_ADVANCE (int_size_in_bytes (TYPE))) \
2266 > NPARM_REGS (MODE))) \
2267 ? NPARM_REGS (MODE) - ROUND_REG ((CUM), (MODE)) \
2268 : (SH5_WOULD_BE_PARTIAL_NREGS ((CUM), (MODE), (TYPE), (NAMED)) \
2269 && ! TARGET_SHCOMPACT) \
2270 ? NPARM_REGS (SImode) - (CUM).arg_count[(int) SH_ARG_INT] \
2271 : 0)
2272
2273 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2274 (TARGET_SH5 \
2275 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2276 || (MODE) == DCmode) \
2277 && ((CUM).arg_count[(int) SH_ARG_INT] \
2278 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2279
2280 /* Perform any needed actions needed for a function that is receiving a
2281 variable number of arguments. */
2282
2283 /* Implement `va_start' for varargs and stdarg. */
2284 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2285 sh_va_start (valist, nextarg)
2286
2287 /* Call the function profiler with a given profile label.
2288 We use two .aligns, so as to make sure that both the .long is aligned
2289 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2290 from the trapa instruction. */
2291
2292 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2293 { \
2294 fprintf((STREAM), "\t.align\t2\n"); \
2295 fprintf((STREAM), "\ttrapa\t#33\n"); \
2296 fprintf((STREAM), "\t.align\t2\n"); \
2297 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2298 }
2299
2300 /* Define this macro if the code for function profiling should come
2301 before the function prologue. Normally, the profiling code comes
2302 after. */
2303
2304 #define PROFILE_BEFORE_PROLOGUE
2305
2306 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2307 the stack pointer does not matter. The value is tested only in
2308 functions that have frame pointers.
2309 No definition is equivalent to always zero. */
2310
2311 #define EXIT_IGNORE_STACK 1
2312
2313 /*
2314 On the SH, the trampoline looks like
2315 2 0002 D202 mov.l l2,r2
2316 1 0000 D301 mov.l l1,r3
2317 3 0004 422B jmp @r2
2318 4 0006 0009 nop
2319 5 0008 00000000 l1: .long area
2320 6 000c 00000000 l2: .long function */
2321
2322 /* Length in units of the trampoline for entering a nested function. */
2323 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2324
2325 /* Alignment required for a trampoline in bits . */
2326 #define TRAMPOLINE_ALIGNMENT \
2327 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2328 : TARGET_SHMEDIA ? 256 : 64)
2329
2330 /* Emit RTL insns to initialize the variable parts of a trampoline.
2331 FNADDR is an RTX for the address of the function's pure code.
2332 CXT is an RTX for the static chain value for the function. */
2333
2334 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2335 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2336
2337 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2338
2339 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2340 { \
2341 if (TARGET_SHMEDIA) \
2342 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2343 gen_reg_rtx (Pmode), 0, \
2344 OPTAB_LIB_WIDEN); \
2345 } while (0)
2346
2347 /* A C expression whose value is RTL representing the value of the return
2348 address for the frame COUNT steps up from the current frame.
2349 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2350 can ignore COUNT. */
2351
2352 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2353 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2354
2355 /* A C expression whose value is RTL representing the location of the
2356 incoming return address at the beginning of any function, before the
2357 prologue. This RTL is either a REG, indicating that the return
2358 value is saved in REG, or a MEM representing a location in
2359 the stack. */
2360 #define INCOMING_RETURN_ADDR_RTX \
2361 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2362 \f
2363 /* Addressing modes, and classification of registers for them. */
2364 #define HAVE_POST_INCREMENT TARGET_SH1
2365 #define HAVE_PRE_DECREMENT TARGET_SH1
2366
2367 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2368 ? 0 : TARGET_SH1)
2369 #define USE_LOAD_PRE_DECREMENT(mode) 0
2370 #define USE_STORE_POST_INCREMENT(mode) 0
2371 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2372 ? 0 : TARGET_SH1)
2373
2374 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2375 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2376 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2377
2378 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2379 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2380 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2381
2382 /* Macros to check register numbers against specific register classes. */
2383
2384 /* These assume that REGNO is a hard or pseudo reg number.
2385 They give nonzero only if REGNO is a hard reg of the suitable class
2386 or a pseudo reg currently allocated to a suitable hard reg.
2387 Since they use reg_renumber, they are safe only once reg_renumber
2388 has been allocated, which happens in local-alloc.c. */
2389
2390 #define REGNO_OK_FOR_BASE_P(REGNO) \
2391 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2392 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2393 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2394 (TARGET_SHMEDIA \
2395 ? (GENERAL_REGISTER_P (REGNO) \
2396 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2397 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2398
2399 /* Maximum number of registers that can appear in a valid memory
2400 address. */
2401
2402 #define MAX_REGS_PER_ADDRESS 2
2403
2404 /* Recognize any constant value that is a valid address. */
2405
2406 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2407
2408 /* Nonzero if the constant value X is a legitimate general operand. */
2409
2410 #define LEGITIMATE_CONSTANT_P(X) \
2411 (TARGET_SHMEDIA \
2412 ? ((GET_MODE (X) != DFmode \
2413 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2414 || (X) == CONST0_RTX (GET_MODE (X)) \
2415 || ! TARGET_SHMEDIA_FPU \
2416 || TARGET_SHMEDIA64) \
2417 : (GET_CODE (X) != CONST_DOUBLE \
2418 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2419 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2420
2421 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2422 and check its validity for a certain class.
2423 We have two alternate definitions for each of them.
2424 The usual definition accepts all pseudo regs; the other rejects
2425 them unless they have been allocated suitable hard regs.
2426 The symbol REG_OK_STRICT causes the latter definition to be used. */
2427
2428 #ifndef REG_OK_STRICT
2429
2430 /* Nonzero if X is a hard reg that can be used as a base reg
2431 or if it is a pseudo reg. */
2432 #define REG_OK_FOR_BASE_P(X) \
2433 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2434
2435 /* Nonzero if X is a hard reg that can be used as an index
2436 or if it is a pseudo reg. */
2437 #define REG_OK_FOR_INDEX_P(X) \
2438 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2439 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2440
2441 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2442 or if X is a pseudo reg. */
2443 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2444 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2445 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2446
2447 #else
2448
2449 /* Nonzero if X is a hard reg that can be used as a base reg. */
2450 #define REG_OK_FOR_BASE_P(X) \
2451 REGNO_OK_FOR_BASE_P (REGNO (X))
2452
2453 /* Nonzero if X is a hard reg that can be used as an index. */
2454 #define REG_OK_FOR_INDEX_P(X) \
2455 REGNO_OK_FOR_INDEX_P (REGNO (X))
2456
2457 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2458 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2459 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2460
2461 #endif
2462
2463 /* The 'Q' constraint is a pc relative load operand. */
2464 #define EXTRA_CONSTRAINT_Q(OP) \
2465 (GET_CODE (OP) == MEM \
2466 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2467 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2468 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2469 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2470 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2471
2472 /* Extra address constraints. */
2473 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2474
2475 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2476 operand is not SCRATCH (i.e. REG) then R0 is probably being
2477 used, hence mova is being used, hence do not select this pattern */
2478 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2479 #define EXTRA_CONSTRAINT_B(OP, STR) \
2480 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2481 : 0)
2482
2483 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2484 #define EXTRA_CONSTRAINT_C16(OP) \
2485 (GET_CODE (OP) == CONST \
2486 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2487 && GET_MODE (XEXP ((OP), 0)) == DImode \
2488 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2489 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2490 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2491 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2492 && (MOVI_SHORI_BASE_OPERAND_P \
2493 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2494 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2495 1)) == CONST_INT)))
2496
2497 /* Check whether OP is a datalabel unspec. */
2498 #define DATALABEL_REF_NO_CONST_P(OP) \
2499 (GET_CODE (OP) == UNSPEC \
2500 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2501 && XVECLEN ((OP), 0) == 1 \
2502 && (GET_CODE (XVECEXP ((OP), 0, 0)) == SYMBOL_REF \
2503 || GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF))
2504
2505 /* Check whether OP is a datalabel unspec, possibly enclosed within a
2506 CONST. */
2507 #define DATALABEL_REF_P(OP) \
2508 ((GET_CODE (OP) == CONST && DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0))) \
2509 || DATALABEL_REF_NO_CONST_P (OP))
2510
2511 #define GOT_ENTRY_P(OP) \
2512 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2513 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2514
2515 #define GOTPLT_ENTRY_P(OP) \
2516 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2517 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2518
2519 #define UNSPEC_GOTOFF_P(OP) \
2520 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2521
2522 #define GOTOFF_P(OP) \
2523 (GET_CODE (OP) == CONST \
2524 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2525 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2526 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2527 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2528
2529 #define PIC_ADDR_P(OP) \
2530 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2531 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2532
2533 #define PIC_OFFSET_P(OP) \
2534 (PIC_ADDR_P (OP) \
2535 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2536 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2537
2538 #define PIC_DIRECT_ADDR_P(OP) \
2539 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2540
2541 #define NON_PIC_REFERENCE_P(OP) \
2542 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2543 || DATALABEL_REF_P (OP) \
2544 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2545 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2546 || DATALABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
2547 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2548
2549 #define PIC_REFERENCE_P(OP) \
2550 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2551 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2552
2553 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2554 (flag_pic \
2555 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2556 || PIC_OFFSET_P (OP)) \
2557 : NON_PIC_REFERENCE_P (OP))
2558
2559 /* The `Csy' constraint is a label or a symbol. */
2560 #define EXTRA_CONSTRAINT_Csy(OP) \
2561 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2562
2563 /* A zero in any shape or form. */
2564 #define EXTRA_CONSTRAINT_Z(OP) \
2565 ((OP) == CONST0_RTX (GET_MODE (OP)))
2566
2567 /* Any vector constant we can handle. */
2568 #define EXTRA_CONSTRAINT_W(OP) \
2569 (GET_CODE (OP) == CONST_VECTOR \
2570 && (sh_rep_vec ((OP), VOIDmode) \
2571 || (HOST_BITS_PER_WIDE_INT >= 64 \
2572 ? sh_const_vec ((OP), VOIDmode) \
2573 : sh_1el_vec ((OP), VOIDmode))))
2574
2575 /* A non-explicit constant that can be loaded directly into a general purpose
2576 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2577 #define EXTRA_CONSTRAINT_Cpg(OP) \
2578 (CONSTANT_P (OP) \
2579 && GET_CODE (OP) != CONST_INT \
2580 && GET_CODE (OP) != CONST_DOUBLE \
2581 && (!flag_pic \
2582 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2583 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2584 && GET_CODE (OP) != LABEL_REF)))
2585 #define EXTRA_CONSTRAINT_C(OP, STR) \
2586 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2587 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2588 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2589 : 0)
2590
2591 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2592 #define EXTRA_CONSTRAINT_Sr0(OP) \
2593 (memory_operand((OP), GET_MODE (OP)) \
2594 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2595 #define EXTRA_CONSTRAINT_Sua(OP) \
2596 (memory_operand((OP), GET_MODE (OP)) \
2597 && GET_CODE (XEXP (OP, 0)) != PLUS)
2598 #define EXTRA_CONSTRAINT_S(OP, STR) \
2599 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2600 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2601 : 0)
2602
2603 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2604 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2605 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2606 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2607 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2608 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2609 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2610 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2611 : 0)
2612 \f
2613 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2614 that is a valid memory address for an instruction.
2615 The MODE argument is the machine mode for the MEM expression
2616 that wants to use this address. */
2617
2618 #define MODE_DISP_OK_4(X,MODE) \
2619 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2620 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2621
2622 #define MODE_DISP_OK_8(X,MODE) \
2623 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2624 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2625
2626 #undef MODE_DISP_OK_4
2627 #define MODE_DISP_OK_4(X,MODE) \
2628 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2629 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2630 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2631 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2632
2633 #undef MODE_DISP_OK_8
2634 #define MODE_DISP_OK_8(X,MODE) \
2635 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2636 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2637 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2638 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2639
2640 #define BASE_REGISTER_RTX_P(X) \
2641 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2642 || (GET_CODE (X) == SUBREG \
2643 && GET_CODE (SUBREG_REG (X)) == REG \
2644 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2645
2646 /* Since this must be r0, which is a single register class, we must check
2647 SUBREGs more carefully, to be sure that we don't accept one that extends
2648 outside the class. */
2649 #define INDEX_REGISTER_RTX_P(X) \
2650 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2651 || (GET_CODE (X) == SUBREG \
2652 && GET_CODE (SUBREG_REG (X)) == REG \
2653 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2654
2655 /* Jump to LABEL if X is a valid address RTX. This must also take
2656 REG_OK_STRICT into account when deciding about valid registers, but it uses
2657 the above macros so we are in luck.
2658
2659 Allow REG
2660 REG+disp
2661 REG+r0
2662 REG++
2663 --REG */
2664
2665 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2666 into the FRx registers. We implement this by setting the maximum offset
2667 to zero when the value is SFmode. This also restricts loading of SFmode
2668 values into the integer registers, but that can't be helped. */
2669
2670 /* The SH allows a displacement in a QI or HI amode, but only when the
2671 other operand is R0. GCC doesn't handle this very well, so we forgo
2672 all of that.
2673
2674 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2675 DI can be any number 0..60. */
2676
2677 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2678 do { \
2679 if (GET_CODE (OP) == CONST_INT) \
2680 { \
2681 if (TARGET_SHMEDIA) \
2682 { \
2683 int MODE_SIZE = GET_MODE_SIZE (MODE); \
2684 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2685 && INTVAL (OP) >= -512 * MODE_SIZE \
2686 && INTVAL (OP) < 512 * MODE_SIZE) \
2687 goto LABEL; \
2688 else \
2689 break; \
2690 } \
2691 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2692 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2693 } \
2694 } while(0)
2695
2696 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2697 { \
2698 if (BASE_REGISTER_RTX_P (X)) \
2699 goto LABEL; \
2700 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2701 && ! TARGET_SHMEDIA \
2702 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2703 goto LABEL; \
2704 else if (GET_CODE (X) == PLUS \
2705 && ((MODE) != PSImode || reload_completed)) \
2706 { \
2707 rtx xop0 = XEXP ((X), 0); \
2708 rtx xop1 = XEXP ((X), 1); \
2709 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2710 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2711 if (GET_MODE_SIZE (MODE) <= 4 \
2712 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2713 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && MODE == DFmode)) \
2714 { \
2715 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2716 goto LABEL; \
2717 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2718 goto LABEL; \
2719 } \
2720 } \
2721 }
2722 \f
2723 /* Try machine-dependent ways of modifying an illegitimate address
2724 to be legitimate. If we find one, return the new, valid address.
2725 This macro is used in only one place: `memory_address' in explow.c.
2726
2727 OLDX is the address as it was before break_out_memory_refs was called.
2728 In some cases it is useful to look at this to decide what needs to be done.
2729
2730 MODE and WIN are passed so that this macro can use
2731 GO_IF_LEGITIMATE_ADDRESS.
2732
2733 It is always safe for this macro to do nothing. It exists to recognize
2734 opportunities to optimize the output.
2735
2736 For the SH, if X is almost suitable for indexing, but the offset is
2737 out of range, convert it into a normal form so that cse has a chance
2738 of reducing the number of address registers used. */
2739
2740 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2741 { \
2742 if (flag_pic) \
2743 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2744 if (GET_CODE (X) == PLUS \
2745 && (GET_MODE_SIZE (MODE) == 4 \
2746 || GET_MODE_SIZE (MODE) == 8) \
2747 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2748 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2749 && ! TARGET_SHMEDIA \
2750 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2751 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2752 { \
2753 rtx index_rtx = XEXP ((X), 1); \
2754 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2755 rtx sum; \
2756 \
2757 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2758 /* On rare occasions, we might get an unaligned pointer \
2759 that is indexed in a way to give an aligned address. \
2760 Therefore, keep the lower two bits in offset_base. */ \
2761 /* Instead of offset_base 128..131 use 124..127, so that \
2762 simple add suffices. */ \
2763 if (offset > 127) \
2764 { \
2765 offset_base = ((offset + 4) & ~60) - 4; \
2766 } \
2767 else \
2768 offset_base = offset & ~60; \
2769 /* Sometimes the normal form does not suit DImode. We \
2770 could avoid that by using smaller ranges, but that \
2771 would give less optimized code when SImode is \
2772 prevalent. */ \
2773 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2774 { \
2775 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2776 GEN_INT (offset_base), NULL_RTX, 0, \
2777 OPTAB_LIB_WIDEN); \
2778 \
2779 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2780 goto WIN; \
2781 } \
2782 } \
2783 }
2784
2785 /* A C compound statement that attempts to replace X, which is an address
2786 that needs reloading, with a valid memory address for an operand of
2787 mode MODE. WIN is a C statement label elsewhere in the code.
2788
2789 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2790 of the address. That will allow inheritance of the address reloads. */
2791
2792 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2793 { \
2794 if (GET_CODE (X) == PLUS \
2795 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2796 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2797 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2798 && ! TARGET_SHMEDIA \
2799 && ! (TARGET_SH4 && (MODE) == DFmode) \
2800 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS)) \
2801 { \
2802 rtx index_rtx = XEXP (X, 1); \
2803 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2804 rtx sum; \
2805 \
2806 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2807 { \
2808 push_reload (X, NULL_RTX, &X, NULL, \
2809 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2810 (TYPE)); \
2811 goto WIN; \
2812 } \
2813 if (TARGET_SH2E && MODE == SFmode) \
2814 { \
2815 X = copy_rtx (X); \
2816 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2817 INDEX_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2818 (TYPE)); \
2819 goto WIN; \
2820 } \
2821 /* Instead of offset_base 128..131 use 124..127, so that \
2822 simple add suffices. */ \
2823 if (offset > 127) \
2824 { \
2825 offset_base = ((offset + 4) & ~60) - 4; \
2826 } \
2827 else \
2828 offset_base = offset & ~60; \
2829 /* Sometimes the normal form does not suit DImode. We \
2830 could avoid that by using smaller ranges, but that \
2831 would give less optimized code when SImode is \
2832 prevalent. */ \
2833 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2834 { \
2835 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2836 GEN_INT (offset_base)); \
2837 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2838 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2839 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2840 (TYPE)); \
2841 goto WIN; \
2842 } \
2843 } \
2844 /* We must re-recognize what we created before. */ \
2845 else if (GET_CODE (X) == PLUS \
2846 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2847 && GET_CODE (XEXP (X, 0)) == PLUS \
2848 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2849 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2850 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2851 && ! TARGET_SHMEDIA \
2852 && ! (TARGET_SH2E && MODE == SFmode)) \
2853 { \
2854 /* Because this address is so complex, we know it must have \
2855 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2856 it is already unshared, and needs no further unsharing. */ \
2857 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2858 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2859 goto WIN; \
2860 } \
2861 }
2862
2863 /* Go to LABEL if ADDR (a legitimate address expression)
2864 has an effect that depends on the machine mode it is used for.
2865
2866 ??? Strictly speaking, we should also include all indexed addressing,
2867 because the index scale factor is the length of the operand.
2868 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2869 high if we did that. So we rely on reload to fix things up. */
2870
2871 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2872 { \
2873 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2874 goto LABEL; \
2875 }
2876 \f
2877 /* Specify the machine mode that this machine uses
2878 for the index in the tablejump instruction. */
2879 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2880
2881 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2882 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2883 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2884 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2885 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2886 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2887 : SImode)
2888
2889 /* Define as C expression which evaluates to nonzero if the tablejump
2890 instruction expects the table to contain offsets from the address of the
2891 table.
2892 Do not define this if the table should contain absolute addresses. */
2893 #define CASE_VECTOR_PC_RELATIVE 1
2894
2895 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2896 #define FLOAT_TYPE_SIZE 32
2897
2898 /* Since the SH2e has only `float' support, it is desirable to make all
2899 floating point types equivalent to `float'. */
2900 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2901
2902 /* 'char' is signed by default. */
2903 #define DEFAULT_SIGNED_CHAR 1
2904
2905 /* The type of size_t unsigned int. */
2906 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2907
2908 #undef PTRDIFF_TYPE
2909 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2910
2911 #define WCHAR_TYPE "short unsigned int"
2912 #define WCHAR_TYPE_SIZE 16
2913
2914 #define SH_ELF_WCHAR_TYPE "long int"
2915
2916 /* Max number of bytes we can move from memory to memory
2917 in one reasonably fast instruction. */
2918 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2919
2920 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2921 MOVE_MAX is not a compile-time constant. */
2922 #define MAX_MOVE_MAX 8
2923
2924 /* Max number of bytes we want move_by_pieces to be able to copy
2925 efficiently. */
2926 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2927
2928 /* Define if operations between registers always perform the operation
2929 on the full register even if a narrower mode is specified. */
2930 #define WORD_REGISTER_OPERATIONS
2931
2932 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2933 will either zero-extend or sign-extend. The value of this macro should
2934 be the code that says which one of the two operations is implicitly
2935 done, UNKNOWN if none. */
2936 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2937 /* FP registers can load SImode values, but don't implicitly sign-extend
2938 them to DImode. */
2939 #define LOAD_EXTEND_OP(MODE) \
2940 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2941 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2942
2943 /* Define if loading short immediate values into registers sign extends. */
2944 #define SHORT_IMMEDIATES_SIGN_EXTEND
2945
2946 /* Nonzero if access to memory by bytes is no faster than for words. */
2947 #define SLOW_BYTE_ACCESS 1
2948
2949 /* Immediate shift counts are truncated by the output routines (or was it
2950 the assembler?). Shift counts in a register are truncated by SH. Note
2951 that the native compiler puts too large (> 32) immediate shift counts
2952 into a register and shifts by the register, letting the SH decide what
2953 to do instead of doing that itself. */
2954 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2955 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2956 expects - the sign bit is significant - so it appears that we need to
2957 leave this zero for correct SH3 code. */
2958 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2959
2960 /* All integers have the same format so truncation is easy. */
2961 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1
2962
2963 /* Define this if addresses of constant functions
2964 shouldn't be put through pseudo regs where they can be cse'd.
2965 Desirable on machines where ordinary constants are expensive
2966 but a CALL with constant address is cheap. */
2967 /*#define NO_FUNCTION_CSE 1*/
2968
2969 /* The machine modes of pointers and functions. */
2970 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2971 #define FUNCTION_MODE Pmode
2972
2973 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2974 are actually function calls with some special constraints on arguments
2975 and register usage.
2976
2977 These macros tell reorg that the references to arguments and
2978 register clobbers for insns of type sfunc do not appear to happen
2979 until after the millicode call. This allows reorg to put insns
2980 which set the argument registers into the delay slot of the millicode
2981 call -- thus they act more like traditional CALL_INSNs.
2982
2983 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2984 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2985 in particular. */
2986
2987 #define INSN_SETS_ARE_DELAYED(X) \
2988 ((GET_CODE (X) == INSN \
2989 && GET_CODE (PATTERN (X)) != SEQUENCE \
2990 && GET_CODE (PATTERN (X)) != USE \
2991 && GET_CODE (PATTERN (X)) != CLOBBER \
2992 && get_attr_is_sfunc (X)))
2993
2994 #define INSN_REFERENCES_ARE_DELAYED(X) \
2995 ((GET_CODE (X) == INSN \
2996 && GET_CODE (PATTERN (X)) != SEQUENCE \
2997 && GET_CODE (PATTERN (X)) != USE \
2998 && GET_CODE (PATTERN (X)) != CLOBBER \
2999 && get_attr_is_sfunc (X)))
3000
3001 \f
3002 /* Position Independent Code. */
3003
3004 /* We can't directly access anything that contains a symbol,
3005 nor can we indirect via the constant pool. */
3006 #define LEGITIMATE_PIC_OPERAND_P(X) \
3007 ((! nonpic_symbol_mentioned_p (X) \
3008 && (GET_CODE (X) != SYMBOL_REF \
3009 || ! CONSTANT_POOL_ADDRESS_P (X) \
3010 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
3011 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
3012
3013 #define SYMBOLIC_CONST_P(X) \
3014 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
3015 && nonpic_symbol_mentioned_p (X))
3016 \f
3017 /* Compute extra cost of moving data between one register class
3018 and another. */
3019
3020 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
3021 uses this information. Hence, the general register <-> floating point
3022 register information here is not used for SFmode. */
3023
3024 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
3025 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
3026 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
3027
3028 #define REGCLASS_HAS_FP_REG(CLASS) \
3029 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
3030 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
3031
3032 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
3033 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
3034
3035 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
3036 would be so that people with slow memory systems could generate
3037 different code that does fewer memory accesses. */
3038
3039 /* A C expression for the cost of a branch instruction. A value of 1
3040 is the default; other values are interpreted relative to that.
3041 The SH1 does not have delay slots, hence we get a pipeline stall
3042 at every branch. The SH4 is superscalar, so the single delay slot
3043 is not sufficient to keep both pipelines filled. */
3044 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
3045 \f
3046 /* Assembler output control. */
3047
3048 /* A C string constant describing how to begin a comment in the target
3049 assembler language. The compiler assumes that the comment will end at
3050 the end of the line. */
3051 #define ASM_COMMENT_START "!"
3052
3053 #define ASM_APP_ON ""
3054 #define ASM_APP_OFF ""
3055 #define FILE_ASM_OP "\t.file\n"
3056 #define SET_ASM_OP "\t.set\t"
3057
3058 /* How to change between sections. */
3059
3060 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
3061 #define DATA_SECTION_ASM_OP "\t.data"
3062
3063 #if defined CRT_BEGIN || defined CRT_END
3064 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
3065 # undef TEXT_SECTION_ASM_OP
3066 # if __SHMEDIA__ == 1 && __SH5__ == 32
3067 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
3068 # else
3069 # define TEXT_SECTION_ASM_OP "\t.text"
3070 # endif
3071 #endif
3072
3073
3074 /* If defined, a C expression whose value is a string containing the
3075 assembler operation to identify the following data as
3076 uninitialized global data. If not defined, and neither
3077 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
3078 uninitialized global data will be output in the data section if
3079 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
3080 used. */
3081 #ifndef BSS_SECTION_ASM_OP
3082 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
3083 #endif
3084
3085 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
3086 separate, explicit argument. If you define this macro, it is used
3087 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
3088 handling the required alignment of the variable. The alignment is
3089 specified as the number of bits.
3090
3091 Try to use function `asm_output_aligned_bss' defined in file
3092 `varasm.c' when defining this macro. */
3093 #ifndef ASM_OUTPUT_ALIGNED_BSS
3094 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
3095 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
3096 #endif
3097
3098 /* Define this so that jump tables go in same section as the current function,
3099 which could be text or it could be a user defined section. */
3100 #define JUMP_TABLES_IN_TEXT_SECTION 1
3101
3102 #undef DO_GLOBAL_CTORS_BODY
3103 #define DO_GLOBAL_CTORS_BODY \
3104 { \
3105 typedef (*pfunc)(); \
3106 extern pfunc __ctors[]; \
3107 extern pfunc __ctors_end[]; \
3108 pfunc *p; \
3109 for (p = __ctors_end; p > __ctors; ) \
3110 { \
3111 (*--p)(); \
3112 } \
3113 }
3114
3115 #undef DO_GLOBAL_DTORS_BODY
3116 #define DO_GLOBAL_DTORS_BODY \
3117 { \
3118 typedef (*pfunc)(); \
3119 extern pfunc __dtors[]; \
3120 extern pfunc __dtors_end[]; \
3121 pfunc *p; \
3122 for (p = __dtors; p < __dtors_end; p++) \
3123 { \
3124 (*p)(); \
3125 } \
3126 }
3127
3128 #define ASM_OUTPUT_REG_PUSH(file, v) \
3129 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v));
3130
3131 #define ASM_OUTPUT_REG_POP(file, v) \
3132 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v));
3133
3134 /* DBX register number for a given compiler register number. */
3135 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3136 to match gdb. */
3137 /* svr4.h undefines this macro, yet we really want to use the same numbers
3138 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3139 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3140 register exists, so we should return -1 for invalid register numbers. */
3141 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3142
3143 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3144 used to use the encodings 245..260, but that doesn't make sense:
3145 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3146 the FP registers stay the same when switching between compact and media
3147 mode. Hence, we also need to use the same dwarf frame columns.
3148 Likewise, we need to support unwind information for SHmedia registers
3149 even in compact code. */
3150 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3151 (IN_RANGE ((REGNO), \
3152 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3153 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3154 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3155 : ((int) (REGNO) >= FIRST_FP_REG \
3156 && ((int) (REGNO) \
3157 <= (FIRST_FP_REG + \
3158 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3159 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3160 + (TARGET_SH5 ? 77 : 25)) \
3161 : XD_REGISTER_P (REGNO) \
3162 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3163 : TARGET_REGISTER_P (REGNO) \
3164 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3165 : (REGNO) == PR_REG \
3166 ? (TARGET_SH5 ? 18 : 17) \
3167 : (REGNO) == PR_MEDIA_REG \
3168 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3169 : (REGNO) == T_REG \
3170 ? (TARGET_SH5 ? 242 : 18) \
3171 : (REGNO) == GBR_REG \
3172 ? (TARGET_SH5 ? 238 : 19) \
3173 : (REGNO) == MACH_REG \
3174 ? (TARGET_SH5 ? 239 : 20) \
3175 : (REGNO) == MACL_REG \
3176 ? (TARGET_SH5 ? 240 : 21) \
3177 : (REGNO) == FPUL_REG \
3178 ? (TARGET_SH5 ? 244 : 23) \
3179 : (unsigned) -1)
3180
3181 /* This is how to output a reference to a symbol_ref. On SH5,
3182 references to non-code symbols must be preceded by `datalabel'. */
3183 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3184 do \
3185 { \
3186 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3187 fputs ("datalabel ", (FILE)); \
3188 assemble_name ((FILE), XSTR ((SYM), 0)); \
3189 } \
3190 while (0)
3191
3192 /* This is how to output an assembler line
3193 that says to advance the location counter
3194 to a multiple of 2**LOG bytes. */
3195
3196 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3197 if ((LOG) != 0) \
3198 fprintf ((FILE), "\t.align %d\n", (LOG))
3199
3200 /* Globalizing directive for a label. */
3201 #define GLOBAL_ASM_OP "\t.global\t"
3202
3203 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3204
3205 /* Output a relative address table. */
3206
3207 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3208 switch (GET_MODE (BODY)) \
3209 { \
3210 case SImode: \
3211 if (TARGET_SH5) \
3212 { \
3213 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3214 (VALUE), (REL)); \
3215 break; \
3216 } \
3217 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3218 break; \
3219 case HImode: \
3220 if (TARGET_SH5) \
3221 { \
3222 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3223 (VALUE), (REL)); \
3224 break; \
3225 } \
3226 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3227 break; \
3228 case QImode: \
3229 if (TARGET_SH5) \
3230 { \
3231 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3232 (VALUE), (REL)); \
3233 break; \
3234 } \
3235 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3236 break; \
3237 default: \
3238 break; \
3239 }
3240
3241 /* Output an absolute table element. */
3242
3243 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3244 if (! optimize || TARGET_BIGTABLE) \
3245 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3246 else \
3247 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3248
3249 \f
3250 /* A C statement to be executed just prior to the output of
3251 assembler code for INSN, to modify the extracted operands so
3252 they will be output differently.
3253
3254 Here the argument OPVEC is the vector containing the operands
3255 extracted from INSN, and NOPERANDS is the number of elements of
3256 the vector which contain meaningful data for this insn.
3257 The contents of this vector are what will be used to convert the insn
3258 template into assembler code, so you can change the assembler output
3259 by changing the contents of the vector. */
3260
3261 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3262 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3263
3264 /* Print operand X (an rtx) in assembler syntax to file FILE.
3265 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3266 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3267
3268 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3269
3270 /* Print a memory address as an operand to reference that memory location. */
3271
3272 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3273
3274 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3275 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3276 || (CHAR) == '$'|| (CHAR) == '\'')
3277
3278 /* Recognize machine-specific patterns that may appear within
3279 constants. Used for PIC-specific UNSPECs. */
3280 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3281 do \
3282 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3283 { \
3284 switch (XINT ((X), 1)) \
3285 { \
3286 case UNSPEC_DATALABEL: \
3287 fputs ("datalabel ", (STREAM)); \
3288 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3289 break; \
3290 case UNSPEC_PIC: \
3291 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3292 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3293 break; \
3294 case UNSPEC_GOT: \
3295 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3296 fputs ("@GOT", (STREAM)); \
3297 break; \
3298 case UNSPEC_GOTOFF: \
3299 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3300 fputs ("@GOTOFF", (STREAM)); \
3301 break; \
3302 case UNSPEC_PLT: \
3303 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3304 fputs ("@PLT", (STREAM)); \
3305 break; \
3306 case UNSPEC_GOTPLT: \
3307 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3308 fputs ("@GOTPLT", (STREAM)); \
3309 break; \
3310 case UNSPEC_DTPOFF: \
3311 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3312 fputs ("@DTPOFF", (STREAM)); \
3313 break; \
3314 case UNSPEC_GOTTPOFF: \
3315 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3316 fputs ("@GOTTPOFF", (STREAM)); \
3317 break; \
3318 case UNSPEC_TPOFF: \
3319 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3320 fputs ("@TPOFF", (STREAM)); \
3321 break; \
3322 case UNSPEC_CALLER: \
3323 { \
3324 char name[32]; \
3325 /* LPCS stands for Label for PIC Call Site. */ \
3326 ASM_GENERATE_INTERNAL_LABEL \
3327 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3328 assemble_name ((STREAM), name); \
3329 } \
3330 break; \
3331 default: \
3332 goto FAIL; \
3333 } \
3334 break; \
3335 } \
3336 else \
3337 goto FAIL; \
3338 while (0)
3339
3340 \f
3341 extern struct rtx_def *sh_compare_op0;
3342 extern struct rtx_def *sh_compare_op1;
3343
3344 /* Which processor to schedule for. The elements of the enumeration must
3345 match exactly the cpu attribute in the sh.md file. */
3346
3347 enum processor_type {
3348 PROCESSOR_SH1,
3349 PROCESSOR_SH2,
3350 PROCESSOR_SH2E,
3351 PROCESSOR_SH2A,
3352 PROCESSOR_SH3,
3353 PROCESSOR_SH3E,
3354 PROCESSOR_SH4,
3355 PROCESSOR_SH4A,
3356 PROCESSOR_SH5
3357 };
3358
3359 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3360 extern enum processor_type sh_cpu;
3361
3362 extern int optimize; /* needed for gen_casesi. */
3363
3364 enum mdep_reorg_phase_e
3365 {
3366 SH_BEFORE_MDEP_REORG,
3367 SH_INSERT_USES_LABELS,
3368 SH_SHORTEN_BRANCHES0,
3369 SH_FIXUP_PCLOAD,
3370 SH_SHORTEN_BRANCHES1,
3371 SH_AFTER_MDEP_REORG
3372 };
3373
3374 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3375
3376 /* Handle Renesas compiler's pragmas. */
3377 #define REGISTER_TARGET_PRAGMAS() do { \
3378 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3379 c_register_pragma (0, "trapa", sh_pr_trapa); \
3380 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3381 } while (0)
3382
3383 /* Set when processing a function with pragma interrupt turned on. */
3384
3385 extern int pragma_interrupt;
3386
3387 /* Set when processing a function with interrupt attribute. */
3388
3389 extern int current_function_interrupt;
3390
3391 /* Set to an RTX containing the address of the stack to switch to
3392 for interrupt functions. */
3393 extern struct rtx_def *sp_switch;
3394
3395 extern int rtx_equal_function_value_matters;
3396
3397 \f
3398 /* Instructions with unfilled delay slots take up an
3399 extra two bytes for the nop in the delay slot.
3400 sh-dsp parallel processing insns are four bytes long. */
3401
3402 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3403 (LENGTH) += sh_insn_length_adjustment (X);
3404 \f
3405 /* Define the codes that are matched by predicates in sh.c. */
3406 #define PREDICATE_CODES \
3407 {"and_operand", {SUBREG, REG, CONST_INT}}, \
3408 {"any_register_operand", {SUBREG, REG}}, \
3409 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
3410 {"arith_reg_dest", {SUBREG, REG}}, \
3411 {"arith_reg_operand", {SUBREG, REG}}, \
3412 {"arith_reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_VECTOR}}, \
3413 {"binary_float_operator", {PLUS, MINUS, MULT, DIV}}, \
3414 {"binary_logical_operator", {AND, IOR, XOR}}, \
3415 {"cmpsi_operand", {SUBREG, REG, CONST_INT}}, \
3416 {"commutative_float_operator", {PLUS, MULT}}, \
3417 {"equality_comparison_operator", {EQ,NE}}, \
3418 {"extend_reg_operand", {SUBREG, REG, TRUNCATE}}, \
3419 {"extend_reg_or_0_operand", {SUBREG, REG, TRUNCATE, CONST_INT}}, \
3420 {"fp_arith_reg_operand", {SUBREG, REG}}, \
3421 {"fpscr_operand", {REG}}, \
3422 {"fpul_operand", {REG}}, \
3423 {"general_extend_operand", {SUBREG, REG, MEM, TRUNCATE}}, \
3424 {"general_movsrc_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
3425 {"general_movdst_operand", {SUBREG, REG, MEM}}, \
3426 {"unaligned_load_operand", {MEM}}, \
3427 {"greater_comparison_operator", {GT,GE,GTU,GEU}}, \
3428 {"int_gpr_dest", {SUBREG, REG}}, \
3429 {"inqhi_operand", {TRUNCATE}}, \
3430 {"less_comparison_operator", {LT,LE,LTU,LEU}}, \
3431 {"logical_operand", {SUBREG, REG, CONST_INT}}, \
3432 {"mextr_bit_offset", {CONST_INT}}, \
3433 {"noncommutative_float_operator", {MINUS, DIV}}, \
3434 {"shmedia_6bit_operand", {SUBREG, REG, CONST_INT}}, \
3435 {"sh_register_operand", {REG, SUBREG, CONST_INT}}, \
3436 {"target_reg_operand", {SUBREG, REG}}, \
3437 {"target_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST, UNSPEC}},\
3438 {"trunc_hi_operand", {SUBREG, REG, TRUNCATE}}, \
3439 {"sh_const_vec", {CONST_VECTOR}}, \
3440 {"sh_1el_vec", {CONST_VECTOR, PARALLEL}}, \
3441 {"sh_rep_vec", {CONST_VECTOR, PARALLEL}}, \
3442 {"symbol_ref_operand", {SYMBOL_REF}}, \
3443 {"unary_float_operator", {ABS, NEG, SQRT}}, \
3444
3445 #define SPECIAL_MODE_PREDICATES \
3446 "any_register_operand", \
3447 "int_gpr_dest", \
3448 "trunc_hi_operand", \
3449 /* This line intentionally left blank. */
3450
3451 #define any_register_operand register_operand
3452
3453 /* Define this macro if it is advisable to hold scalars in registers
3454 in a wider mode than that declared by the program. In such cases,
3455 the value is constrained to be within the bounds of the declared
3456 type, but kept valid in the wider mode. The signedness of the
3457 extension may differ from that of the type.
3458
3459 Leaving the unsignedp unchanged gives better code than always setting it
3460 to 0. This is despite the fact that we have only signed char and short
3461 load instructions. */
3462 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3463 if (GET_MODE_CLASS (MODE) == MODE_INT \
3464 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
3465 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3466 (MODE) = (TARGET_SH1 ? SImode : DImode);
3467
3468 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3469
3470 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3471 and popping arguments. However, we do have push/pop instructions, and
3472 rather limited offsets (4 bits) in load/store instructions, so it isn't
3473 clear if this would give better code. If implemented, should check for
3474 compatibility problems. */
3475
3476 #define SH_DYNAMIC_SHIFT_COST \
3477 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3478
3479
3480 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3481
3482 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3483
3484 #define ACTUAL_NORMAL_MODE(ENTITY) \
3485 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3486
3487 #define NORMAL_MODE(ENTITY) \
3488 (sh_cfun_interrupt_handler_p () \
3489 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3490 : ACTUAL_NORMAL_MODE (ENTITY))
3491
3492 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3493
3494 #define MODE_EXIT(ENTITY) \
3495 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3496
3497 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3498 && (REGNO) == FPSCR_REG)
3499
3500 #define MODE_NEEDED(ENTITY, INSN) \
3501 (recog_memoized (INSN) >= 0 \
3502 ? get_attr_fp_mode (INSN) \
3503 : FP_MODE_NONE)
3504
3505 #define MODE_AFTER(MODE, INSN) \
3506 (TARGET_HITACHI \
3507 && recog_memoized (INSN) >= 0 \
3508 && get_attr_fp_set (INSN) != FP_SET_NONE \
3509 ? (int) get_attr_fp_set (INSN) \
3510 : (MODE))
3511
3512 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3513 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3514
3515 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3516 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3517
3518 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3519 sh_can_redirect_branch ((INSN), (SEQ))
3520
3521 #define DWARF_FRAME_RETURN_COLUMN \
3522 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3523
3524 #define EH_RETURN_DATA_REGNO(N) \
3525 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3526
3527 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3528 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3529
3530 /* We have to distinguish between code and data, so that we apply
3531 datalabel where and only where appropriate. Use textrel for code. */
3532 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3533 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3534 | ((CODE) ? DW_EH_PE_textrel : flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))
3535
3536 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3537 indirect are handled automatically. */
3538 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3539 do { \
3540 if (((ENCODING) & 0x70) == DW_EH_PE_textrel) \
3541 { \
3542 encoding &= ~DW_EH_PE_textrel; \
3543 encoding |= flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr; \
3544 if (GET_CODE (ADDR) != SYMBOL_REF) \
3545 abort (); \
3546 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3547 if (0) goto DONE; \
3548 } \
3549 } while (0)
3550
3551 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3552 /* SH constant pool breaks the devices in crtstuff.c to control section
3553 in where code resides. We have to write it as asm code. */
3554 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3555 asm (SECTION_OP "\n\
3556 mov.l 1f,r1\n\
3557 mova 2f,r0\n\
3558 braf r1\n\
3559 lds r0,pr\n\
3560 0: .p2align 2\n\
3561 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3562 2:\n" TEXT_SECTION_ASM_OP);
3563 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3564
3565 #define ALLOCATE_INITIAL_VALUE(hard_reg) \
3566 (REGNO (hard_reg) == (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG) \
3567 ? (current_function_is_leaf \
3568 && ! sh_pr_n_sets () \
3569 && ! (TARGET_SHCOMPACT \
3570 && ((current_function_args_info.call_cookie \
3571 & ~ CALL_COOKIE_RET_TRAMP (1)) \
3572 || current_function_has_nonlocal_label)) \
3573 ? (hard_reg) \
3574 : gen_rtx_MEM (Pmode, return_address_pointer_rtx)) \
3575 : NULL_RTX)
3576
3577 #endif /* ! GCC_SH_H */
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