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PR target/16407
[official-gcc.git] / gcc / config / mips / mips.h
blob00ddbba1b65693fbcd2f85de6aa9bdfdb1669377
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* comparison type */
34 enum cmp_type {
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
40 };
41
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
46
47 enum processor_type {
48 PROCESSOR_DEFAULT,
49 PROCESSOR_4KC,
50 PROCESSOR_5KC,
51 PROCESSOR_20KC,
52 PROCESSOR_M4K,
53 PROCESSOR_R3000,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4130,
61 PROCESSOR_R4300,
62 PROCESSOR_R4600,
63 PROCESSOR_R4650,
64 PROCESSOR_R5000,
65 PROCESSOR_R5400,
66 PROCESSOR_R5500,
67 PROCESSOR_R7000,
68 PROCESSOR_R8000,
69 PROCESSOR_R9000,
70 PROCESSOR_SB1,
71 PROCESSOR_SR71000
72 };
73
74 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
75 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
76 to work on a 64 bit machine. */
77
78 #define ABI_32 0
79 #define ABI_N32 1
80 #define ABI_64 2
81 #define ABI_EABI 3
82 #define ABI_O64 4
83
84 /* Information about one recognized processor. Defined here for the
85 benefit of TARGET_CPU_CPP_BUILTINS. */
86 struct mips_cpu_info {
87 /* The 'canonical' name of the processor as far as GCC is concerned.
88 It's typically a manufacturer's prefix followed by a numerical
89 designation. It should be lower case. */
90 const char *name;
91
92 /* The internal processor number that most closely matches this
93 entry. Several processors can have the same value, if there's no
94 difference between them from GCC's point of view. */
95 enum processor_type cpu;
96
97 /* The ISA level that the processor implements. */
98 int isa;
99 };
100
101 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
102 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
103 extern const char *current_function_file; /* filename current function is in */
104 extern int num_source_filenames; /* current .file # */
105 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
106 extern int sym_lineno; /* sgi next label # for each stmt */
107 extern int set_noreorder; /* # of nested .set noreorder's */
108 extern int set_nomacro; /* # of nested .set nomacro's */
109 extern int set_noat; /* # of nested .set noat's */
110 extern int set_volatile; /* # of nested .set volatile's */
111 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
112 extern int mips_dbx_regno[]; /* Map register # to debug register # */
113 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
114 extern enum cmp_type branch_type; /* what type of branch to use */
115 extern enum processor_type mips_arch; /* which cpu to codegen for */
116 extern enum processor_type mips_tune; /* which cpu to schedule for */
117 extern int mips_isa; /* architectural level */
118 extern int mips_abi; /* which ABI to use */
119 extern int mips16_hard_float; /* mips16 without -msoft-float */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern const struct mips_cpu_info mips_cpu_info_table[];
126 extern const struct mips_cpu_info *mips_arch_info;
127 extern const struct mips_cpu_info *mips_tune_info;
128
129 /* Macros to silence warnings about numbers being signed in traditional
130 C and unsigned in ISO C when compiled on 32-bit hosts. */
131
132 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
133 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
134 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
135
136 \f
137 /* Run-time compilation parameters selecting different hardware subsets. */
138
139 /* Macros used in the machine description to test the flags. */
140
141 /* Bits for real switches */
142 #define MASK_INT64 0x00000001 /* ints are 64 bits */
143 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
144 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
145 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
146 multiply-add operations. */
147 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
148 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
149 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
150 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
151 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
152 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
153 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
154 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
155 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
156 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
157 #define MASK_EMBEDDED_DATA 0x00004000 /* Reduce RAM usage, not fast code */
158 #define MASK_BIG_ENDIAN 0x00008000 /* Generate big endian code */
159 #define MASK_SINGLE_FLOAT 0x00010000 /* Only single precision FPU. */
160 #define MASK_MAD 0x00020000 /* Generate mad/madu as on 4650. */
161 #define MASK_4300_MUL_FIX 0x00040000 /* Work-around early Vr4300 CPU bug */
162 #define MASK_MIPS16 0x00080000 /* Generate mips16 code */
163 #define MASK_NO_CHECK_ZERO_DIV \
164 0x00100000 /* divide by zero checking */
165 #define MASK_BRANCHLIKELY 0x00200000 /* Generate Branch Likely
166 instructions. */
167 #define MASK_UNINIT_CONST_IN_RODATA \
168 0x00400000 /* Store uninitialized
169 consts in rodata */
170 #define MASK_FIX_R4000 0x00800000 /* Work around R4000 errata. */
171 #define MASK_FIX_R4400 0x01000000 /* Work around R4400 errata. */
172 #define MASK_FIX_SB1 0x02000000 /* Work around SB-1 errata. */
173 #define MASK_FIX_VR4120 0x04000000 /* Work around VR4120 errata. */
174 #define MASK_VR4130_ALIGN 0x08000000 /* Perform VR4130 alignment opts. */
175 #define MASK_FP_EXCEPTIONS 0x10000000 /* FP exceptions are enabled. */
176
177 /* Debug switches, not documented */
178 #define MASK_DEBUG 0 /* unused */
179 #define MASK_DEBUG_D 0 /* don't do define_split's */
180
181 /* Dummy switches used only in specs */
182 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
183
184 /* r4000 64 bit sizes */
185 #define TARGET_INT64 (target_flags & MASK_INT64)
186 #define TARGET_LONG64 (target_flags & MASK_LONG64)
187 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
188 #define TARGET_64BIT (target_flags & MASK_64BIT)
189
190 /* Mips vs. GNU linker */
191 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
192
193 /* Mips vs. GNU assembler */
194 #define TARGET_GAS (target_flags & MASK_GAS)
195 #define TARGET_MIPS_AS (!TARGET_GAS)
196
197 /* Debug Modes */
198 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
199 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
200
201 /* Reg. Naming in .s ($21 vs. $a0) */
202 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
203
204 /* call memcpy instead of inline code */
205 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
206
207 /* .abicalls, etc from Pyramid V.4 */
208 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
209 #define TARGET_XGOT (target_flags & MASK_XGOT)
210
211 /* software floating point */
212 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
213 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
214
215 /* always call through a register */
216 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
217
218 /* for embedded systems, optimize for
219 reduced RAM space instead of for
220 fastest code. */
221 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
222
223 /* always store uninitialized const
224 variables in rodata, requires
225 TARGET_EMBEDDED_DATA. */
226 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
227
228 /* generate big endian code. */
229 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
230
231 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
232 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
233
234 #define TARGET_MAD (target_flags & MASK_MAD)
235
236 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
237
238 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
239
240 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
241
242 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
243
244 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
245
246 /* Work around R4000 errata. */
247 #define TARGET_FIX_R4000 (target_flags & MASK_FIX_R4000)
248
249 /* Work around R4400 errata. */
250 #define TARGET_FIX_R4400 (target_flags & MASK_FIX_R4400)
251 #define TARGET_FIX_VR4120 (target_flags & MASK_FIX_VR4120)
252 #define TARGET_VR4130_ALIGN (target_flags & MASK_VR4130_ALIGN)
253
254 #define TARGET_FP_EXCEPTIONS (target_flags & MASK_FP_EXCEPTIONS)
255
256 /* True if we should use NewABI-style relocation operators for
257 symbolic addresses. This is never true for mips16 code,
258 which has its own conventions. */
259
260 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
261
262
263 /* True if the call patterns should be split into a jalr followed by
264 an instruction to restore $gp. This is only ever true for SVR4 PIC,
265 in which $gp is call-clobbered. It is only safe to split the load
266 from the call when every use of $gp is explicit. */
267
268 #define TARGET_SPLIT_CALLS \
269 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
270
271 /* True if we can optimize sibling calls. For simplicity, we only
272 handle cases in which call_insn_operand will reject invalid
273 sibcall addresses. There are two cases in which this isn't true:
274
275 - TARGET_MIPS16. call_insn_operand accepts constant addresses
276 but there is no direct jump instruction. It isn't worth
277 using sibling calls in this case anyway; they would usually
278 be longer than normal calls.
279
280 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
281 accepts global constants, but "jr $25" is the only allowed
282 sibcall. */
283
284 #define TARGET_SIBCALLS \
285 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
286
287 /* True if .gpword or .gpdword should be used for switch tables.
288 There are some problems with using these directives with the
289 native IRIX tools:
290
291 - It has been reported that some versions of the native n32
292 assembler mishandle .gpword, complaining that symbols are
293 global when they are in fact local.
294
295 - The native assemblers don't understand .gpdword.
296
297 - Although GAS does understand .gpdword, the native linker
298 mishandles the relocations GAS generates (R_MIPS_GPREL32
299 followed by R_MIPS_64).
300
301 We therefore disable GP-relative switch tables for n32 and n64
302 on IRIX targets. */
303 #define TARGET_GPWORD (TARGET_ABICALLS && !(TARGET_NEWABI && TARGET_IRIX))
304
305 /* Generate mips16 code */
306 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
307
308 /* Generic ISA defines. */
309 #define ISA_MIPS1 (mips_isa == 1)
310 #define ISA_MIPS2 (mips_isa == 2)
311 #define ISA_MIPS3 (mips_isa == 3)
312 #define ISA_MIPS4 (mips_isa == 4)
313 #define ISA_MIPS32 (mips_isa == 32)
314 #define ISA_MIPS32R2 (mips_isa == 33)
315 #define ISA_MIPS64 (mips_isa == 64)
316
317 /* Architecture target defines. */
318 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
319 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
320 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
321 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
322 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
323 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
324 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
325 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
326 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
327
328 /* Scheduling target defines. */
329 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
330 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
331 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
332 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
333 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
334 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
335 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
336 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
337 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
338 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
339 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
340 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
341
342 /* True if the pre-reload scheduler should try to create chains of
343 multiply-add or multiply-subtract instructions. For example,
344 suppose we have:
345
346 t1 = a * b
347 t2 = t1 + c * d
348 t3 = e * f
349 t4 = t3 - g * h
350
351 t1 will have a higher priority than t2 and t3 will have a higher
352 priority than t4. However, before reload, there is no dependence
353 between t1 and t3, and they can often have similar priorities.
354 The scheduler will then tend to prefer:
355
356 t1 = a * b
357 t3 = e * f
358 t2 = t1 + c * d
359 t4 = t3 - g * h
360
361 which stops us from making full use of macc/madd-style instructions.
362 This sort of situation occurs frequently in Fourier transforms and
363 in unrolled loops.
364
365 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
366 queue so that chained multiply-add and multiply-subtract instructions
367 appear ahead of any other instruction that is likely to clobber lo.
368 In the example above, if t2 and t3 become ready at the same time,
369 the code ensures that t2 is scheduled first.
370
371 Multiply-accumulate instructions are a bigger win for some targets
372 than others, so this macro is defined on an opt-in basis. */
373 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
374 || TUNE_MIPS4120 \
375 || TUNE_MIPS4130)
376
377 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
378 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
379
380 /* IRIX specific stuff. */
381 #define TARGET_IRIX 0
382 #define TARGET_IRIX5 0
383 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
384
385 /* Define preprocessor macros for the -march and -mtune options.
386 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
387 processor. If INFO's canonical name is "foo", define PREFIX to
388 be "foo", and define an additional macro PREFIX_FOO. */
389 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
390 do \
391 { \
392 char *macro, *p; \
393 \
394 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
395 for (p = macro; *p != 0; p++) \
396 *p = TOUPPER (*p); \
397 \
398 builtin_define (macro); \
399 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
400 free (macro); \
401 } \
402 while (0)
403
404 /* Target CPU builtins. */
405 #define TARGET_CPU_CPP_BUILTINS() \
406 do \
407 { \
408 builtin_assert ("cpu=mips"); \
409 builtin_define ("__mips__"); \
410 builtin_define ("_mips"); \
411 \
412 /* We do this here because __mips is defined below \
413 and so we can't use builtin_define_std. */ \
414 if (!flag_iso) \
415 builtin_define ("mips"); \
416 \
417 /* Treat _R3000 and _R4000 like register-size defines, \
418 which is how they've historically been used. */ \
419 if (TARGET_64BIT) \
420 { \
421 builtin_define ("__mips64"); \
422 builtin_define_std ("R4000"); \
423 builtin_define ("_R4000"); \
424 } \
425 else \
426 { \
427 builtin_define_std ("R3000"); \
428 builtin_define ("_R3000"); \
429 } \
430 if (TARGET_FLOAT64) \
431 builtin_define ("__mips_fpr=64"); \
432 else \
433 builtin_define ("__mips_fpr=32"); \
434 \
435 if (TARGET_MIPS16) \
436 builtin_define ("__mips16"); \
437 \
438 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
439 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
440 \
441 if (ISA_MIPS1) \
442 { \
443 builtin_define ("__mips=1"); \
444 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
445 } \
446 else if (ISA_MIPS2) \
447 { \
448 builtin_define ("__mips=2"); \
449 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
450 } \
451 else if (ISA_MIPS3) \
452 { \
453 builtin_define ("__mips=3"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
455 } \
456 else if (ISA_MIPS4) \
457 { \
458 builtin_define ("__mips=4"); \
459 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
460 } \
461 else if (ISA_MIPS32) \
462 { \
463 builtin_define ("__mips=32"); \
464 builtin_define ("__mips_isa_rev=1"); \
465 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
466 } \
467 else if (ISA_MIPS32R2) \
468 { \
469 builtin_define ("__mips=32"); \
470 builtin_define ("__mips_isa_rev=2"); \
471 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
472 } \
473 else if (ISA_MIPS64) \
474 { \
475 builtin_define ("__mips=64"); \
476 builtin_define ("__mips_isa_rev=1"); \
477 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
478 } \
479 \
480 if (TARGET_HARD_FLOAT) \
481 builtin_define ("__mips_hard_float"); \
482 else if (TARGET_SOFT_FLOAT) \
483 builtin_define ("__mips_soft_float"); \
484 \
485 if (TARGET_SINGLE_FLOAT) \
486 builtin_define ("__mips_single_float"); \
487 \
488 if (TARGET_BIG_ENDIAN) \
489 { \
490 builtin_define_std ("MIPSEB"); \
491 builtin_define ("_MIPSEB"); \
492 } \
493 else \
494 { \
495 builtin_define_std ("MIPSEL"); \
496 builtin_define ("_MIPSEL"); \
497 } \
498 \
499 /* Macros dependent on the C dialect. */ \
500 if (preprocessing_asm_p ()) \
501 { \
502 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
503 builtin_define ("_LANGUAGE_ASSEMBLY"); \
504 } \
505 else if (c_dialect_cxx ()) \
506 { \
507 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
508 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
509 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
510 } \
511 else \
512 { \
513 builtin_define_std ("LANGUAGE_C"); \
514 builtin_define ("_LANGUAGE_C"); \
515 } \
516 if (c_dialect_objc ()) \
517 { \
518 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
519 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
520 /* Bizarre, but needed at least for Irix. */ \
521 builtin_define_std ("LANGUAGE_C"); \
522 builtin_define ("_LANGUAGE_C"); \
523 } \
524 \
525 if (mips_abi == ABI_EABI) \
526 builtin_define ("__mips_eabi"); \
527 \
528 } while (0)
529
530
531
532 /* Macro to define tables used to set the flags.
533 This is a list in braces of pairs in braces,
534 each pair being { "NAME", VALUE }
535 where VALUE is the bits to set or minus the bits to clear.
536 An empty string NAME is used to identify the default VALUE. */
537
538 #define TARGET_SWITCHES \
539 { \
540 SUBTARGET_TARGET_SWITCHES \
541 {"int64", MASK_INT64 | MASK_LONG64, \
542 N_("Use 64-bit int type")}, \
543 {"long64", MASK_LONG64, \
544 N_("Use 64-bit long type")}, \
545 {"long32", -(MASK_LONG64 | MASK_INT64), \
546 N_("Use 32-bit long type")}, \
547 {"split-addresses", MASK_SPLIT_ADDR, \
548 N_("Optimize lui/addiu address loads")}, \
549 {"no-split-addresses", -MASK_SPLIT_ADDR, \
550 N_("Don't optimize lui/addiu address loads")}, \
551 {"mips-as", -MASK_GAS, \
552 N_("Use MIPS as")}, \
553 {"gas", MASK_GAS, \
554 N_("Use GNU as")}, \
555 {"rnames", MASK_NAME_REGS, \
556 N_("Use symbolic register names")}, \
557 {"no-rnames", -MASK_NAME_REGS, \
558 N_("Don't use symbolic register names")}, \
559 {"gpOPT", 0, \
560 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
561 {"gpopt", 0, \
562 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
563 {"no-gpOPT", 0, \
564 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
565 {"no-gpopt", 0, \
566 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
567 {"stats", 0, \
568 N_("Output compiler statistics (now ignored)")}, \
569 {"no-stats", 0, \
570 N_("Don't output compiler statistics")}, \
571 {"memcpy", MASK_MEMCPY, \
572 N_("Don't optimize block moves")}, \
573 {"no-memcpy", -MASK_MEMCPY, \
574 N_("Optimize block moves")}, \
575 {"mips-tfile", MASK_MIPS_TFILE, \
576 N_("Use mips-tfile asm postpass")}, \
577 {"no-mips-tfile", -MASK_MIPS_TFILE, \
578 N_("Don't use mips-tfile asm postpass")}, \
579 {"soft-float", MASK_SOFT_FLOAT, \
580 N_("Use software floating point")}, \
581 {"hard-float", -MASK_SOFT_FLOAT, \
582 N_("Use hardware floating point")}, \
583 {"fp64", MASK_FLOAT64, \
584 N_("Use 64-bit FP registers")}, \
585 {"fp32", -MASK_FLOAT64, \
586 N_("Use 32-bit FP registers")}, \
587 {"gp64", MASK_64BIT, \
588 N_("Use 64-bit general registers")}, \
589 {"gp32", -MASK_64BIT, \
590 N_("Use 32-bit general registers")}, \
591 {"abicalls", MASK_ABICALLS, \
592 N_("Use Irix PIC")}, \
593 {"no-abicalls", -MASK_ABICALLS, \
594 N_("Don't use Irix PIC")}, \
595 {"long-calls", MASK_LONG_CALLS, \
596 N_("Use indirect calls")}, \
597 {"no-long-calls", -MASK_LONG_CALLS, \
598 N_("Don't use indirect calls")}, \
599 {"embedded-data", MASK_EMBEDDED_DATA, \
600 N_("Use ROM instead of RAM")}, \
601 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
602 N_("Don't use ROM instead of RAM")}, \
603 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
604 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
605 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
606 N_("Don't put uninitialized constants in ROM")}, \
607 {"eb", MASK_BIG_ENDIAN, \
608 N_("Use big-endian byte order")}, \
609 {"el", -MASK_BIG_ENDIAN, \
610 N_("Use little-endian byte order")}, \
611 {"single-float", MASK_SINGLE_FLOAT, \
612 N_("Use single (32-bit) FP only")}, \
613 {"double-float", -MASK_SINGLE_FLOAT, \
614 N_("Don't use single (32-bit) FP only")}, \
615 {"mad", MASK_MAD, \
616 N_("Use multiply accumulate")}, \
617 {"no-mad", -MASK_MAD, \
618 N_("Don't use multiply accumulate")}, \
619 {"no-fused-madd", MASK_NO_FUSED_MADD, \
620 N_("Don't generate fused multiply/add instructions")}, \
621 {"fused-madd", -MASK_NO_FUSED_MADD, \
622 N_("Generate fused multiply/add instructions")}, \
623 {"vr4130-align", MASK_VR4130_ALIGN, \
624 N_("Perform VR4130-specific alignment optimizations")}, \
625 {"no-vr4130-align", -MASK_VR4130_ALIGN, \
626 N_("Don't perform VR4130-specific alignment optimizations")}, \
627 {"fix4300", MASK_4300_MUL_FIX, \
628 N_("Work around early 4300 hardware bug")}, \
629 {"no-fix4300", -MASK_4300_MUL_FIX, \
630 N_("Don't work around early 4300 hardware bug")}, \
631 {"fix-sb1", MASK_FIX_SB1, \
632 N_("Work around errata for early SB-1 revision 2 cores")}, \
633 {"no-fix-sb1", -MASK_FIX_SB1, \
634 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
635 {"fix-r4000", MASK_FIX_R4000, \
636 N_("Work around R4000 errata")}, \
637 {"no-fix-r4000", -MASK_FIX_R4000, \
638 N_("Don't work around R4000 errata")}, \
639 {"fix-r4400", MASK_FIX_R4400, \
640 N_("Work around R4400 errata")}, \
641 {"no-fix-r4400", -MASK_FIX_R4400, \
642 N_("Don't work around R4400 errata")}, \
643 {"fix-vr4120", MASK_FIX_VR4120, \
644 N_("Work around certain VR4120 errata")}, \
645 {"no-fix-vr4120", -MASK_FIX_VR4120, \
646 N_("Don't work around certain VR4120 errata")}, \
647 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
648 N_("Trap on integer divide by zero")}, \
649 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
650 N_("Don't trap on integer divide by zero")}, \
651 { "branch-likely", MASK_BRANCHLIKELY, \
652 N_("Use Branch Likely instructions, overriding default for arch")}, \
653 { "no-branch-likely", -MASK_BRANCHLIKELY, \
654 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
655 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
656 N_("Use NewABI-style %reloc() assembly operators")}, \
657 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
658 N_("Use assembler macros instead of relocation operators")}, \
659 {"ips16", MASK_MIPS16, \
660 N_("Generate mips16 code") }, \
661 {"no-mips16", -MASK_MIPS16, \
662 N_("Generate normal-mode code") }, \
663 {"xgot", MASK_XGOT, \
664 N_("Lift restrictions on GOT size") }, \
665 {"no-xgot", -MASK_XGOT, \
666 N_("Do not lift restrictions on GOT size") }, \
667 {"fp-exceptions", MASK_FP_EXCEPTIONS, \
668 N_("FP exceptions are enabled") }, \
669 {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
670 N_("FP exceptions are not enabled") }, \
671 {"debug", MASK_DEBUG, \
672 NULL}, \
673 {"debugd", MASK_DEBUG_D, \
674 NULL}, \
675 {"", (TARGET_DEFAULT \
676 | TARGET_CPU_DEFAULT \
677 | TARGET_ENDIAN_DEFAULT \
678 | TARGET_FP_EXCEPTIONS_DEFAULT), \
679 NULL}, \
680 }
681
682 /* Default target_flags if no switches are specified */
683
684 #ifndef TARGET_DEFAULT
685 #define TARGET_DEFAULT 0
686 #endif
687
688 #ifndef TARGET_CPU_DEFAULT
689 #define TARGET_CPU_DEFAULT 0
690 #endif
691
692 #ifndef TARGET_ENDIAN_DEFAULT
693 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
694 #endif
695
696 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
697 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
698 #endif
699
700 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
701 #ifndef MIPS_ISA_DEFAULT
702 #ifndef MIPS_CPU_STRING_DEFAULT
703 #define MIPS_CPU_STRING_DEFAULT "from-abi"
704 #endif
705 #endif
706
707 #ifdef IN_LIBGCC2
708 #undef TARGET_64BIT
709 /* Make this compile time constant for libgcc2 */
710 #ifdef __mips64
711 #define TARGET_64BIT 1
712 #else
713 #define TARGET_64BIT 0
714 #endif
715 #endif /* IN_LIBGCC2 */
716
717 #ifndef MULTILIB_ENDIAN_DEFAULT
718 #if TARGET_ENDIAN_DEFAULT == 0
719 #define MULTILIB_ENDIAN_DEFAULT "EL"
720 #else
721 #define MULTILIB_ENDIAN_DEFAULT "EB"
722 #endif
723 #endif
724
725 #ifndef MULTILIB_ISA_DEFAULT
726 # if MIPS_ISA_DEFAULT == 1
727 # define MULTILIB_ISA_DEFAULT "mips1"
728 # else
729 # if MIPS_ISA_DEFAULT == 2
730 # define MULTILIB_ISA_DEFAULT "mips2"
731 # else
732 # if MIPS_ISA_DEFAULT == 3
733 # define MULTILIB_ISA_DEFAULT "mips3"
734 # else
735 # if MIPS_ISA_DEFAULT == 4
736 # define MULTILIB_ISA_DEFAULT "mips4"
737 # else
738 # if MIPS_ISA_DEFAULT == 32
739 # define MULTILIB_ISA_DEFAULT "mips32"
740 # else
741 # if MIPS_ISA_DEFAULT == 33
742 # define MULTILIB_ISA_DEFAULT "mips32r2"
743 # else
744 # if MIPS_ISA_DEFAULT == 64
745 # define MULTILIB_ISA_DEFAULT "mips64"
746 # else
747 # define MULTILIB_ISA_DEFAULT "mips1"
748 # endif
749 # endif
750 # endif
751 # endif
752 # endif
753 # endif
754 # endif
755 #endif
756
757 #ifndef MULTILIB_DEFAULTS
758 #define MULTILIB_DEFAULTS \
759 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
760 #endif
761
762 /* We must pass -EL to the linker by default for little endian embedded
763 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
764 linker will default to using big-endian output files. The OUTPUT_FORMAT
765 line must be in the linker script, otherwise -EB/-EL will not work. */
766
767 #ifndef ENDIAN_SPEC
768 #if TARGET_ENDIAN_DEFAULT == 0
769 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
770 #else
771 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
772 #endif
773 #endif
774
775 #define TARGET_OPTIONS \
776 { \
777 SUBTARGET_TARGET_OPTIONS \
778 { "tune=", &mips_tune_string, \
779 N_("Specify CPU for scheduling purposes"), 0}, \
780 { "arch=", &mips_arch_string, \
781 N_("Specify CPU for code generation purposes"), 0}, \
782 { "abi=", &mips_abi_string, \
783 N_("Specify an ABI"), 0}, \
784 { "ips", &mips_isa_string, \
785 N_("Specify a Standard MIPS ISA"), 0}, \
786 { "no-flush-func", &mips_cache_flush_func, \
787 N_("Don't call any cache flush functions"), 0}, \
788 { "flush-func=", &mips_cache_flush_func, \
789 N_("Specify cache flush function"), 0}, \
790 }
791
792 /* This is meant to be redefined in the host dependent files. */
793 #define SUBTARGET_TARGET_OPTIONS
794
795 /* Support for a compile-time default CPU, et cetera. The rules are:
796 --with-arch is ignored if -march is specified or a -mips is specified
797 (other than -mips16).
798 --with-tune is ignored if -mtune is specified.
799 --with-abi is ignored if -mabi is specified.
800 --with-float is ignored if -mhard-float or -msoft-float are
801 specified. */
802 #define OPTION_DEFAULT_SPECS \
803 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
804 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
805 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
806 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
807
808
809 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
810 && !TARGET_SR71K \
811 && !TARGET_MIPS16)
812
813 /* Generate three-operand multiply instructions for SImode. */
814 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
815 || TARGET_MIPS5400 \
816 || TARGET_MIPS5500 \
817 || TARGET_MIPS7000 \
818 || TARGET_MIPS9000 \
819 || ISA_MIPS32 \
820 || ISA_MIPS32R2 \
821 || ISA_MIPS64) \
822 && !TARGET_MIPS16)
823
824 /* Generate three-operand multiply instructions for DImode. */
825 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
826 && !TARGET_MIPS16)
827
828 /* Macros to decide whether certain features are available or not,
829 depending on the instruction set architecture level. */
830
831 #define HAVE_SQRT_P() (!ISA_MIPS1)
832
833 /* True if the ABI can only work with 64-bit integer registers. We
834 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
835 otherwise floating-point registers must also be 64-bit. */
836 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
837
838 /* Likewise for 32-bit regs. */
839 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
840
841 /* True if symbols are 64 bits wide. At present, n64 is the only
842 ABI for which this is true. */
843 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
844
845 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
846 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
847 || ISA_MIPS4 \
848 || ISA_MIPS64)
849
850 /* ISA has branch likely instructions (eg. mips2). */
851 /* Disable branchlikely for tx39 until compare rewrite. They haven't
852 been generated up to this point. */
853 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
854
855 /* ISA has the conditional move instructions introduced in mips4. */
856 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
857 || ISA_MIPS32 \
858 || ISA_MIPS32R2 \
859 || ISA_MIPS64) \
860 && !TARGET_MIPS5500 \
861 && !TARGET_MIPS16)
862
863 /* ISA has just the integer condition move instructions (movn,movz) */
864 #define ISA_HAS_INT_CONDMOVE 0
865
866 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
867 branch on CC, and move (both FP and non-FP) on CC. */
868 #define ISA_HAS_8CC (ISA_MIPS4 \
869 || ISA_MIPS32 \
870 || ISA_MIPS32R2 \
871 || ISA_MIPS64)
872
873 /* This is a catch all for other mips4 instructions: indexed load, the
874 FP madd and msub instructions, and the FP recip and recip sqrt
875 instructions. */
876 #define ISA_HAS_FP4 ((ISA_MIPS4 \
877 || ISA_MIPS64) \
878 && !TARGET_MIPS16)
879
880 /* ISA has conditional trap instructions. */
881 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
882 && !TARGET_MIPS16)
883
884 /* ISA has integer multiply-accumulate instructions, madd and msub. */
885 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
886 || ISA_MIPS32R2 \
887 || ISA_MIPS64 \
888 ) && !TARGET_MIPS16)
889
890 /* ISA has floating-point nmadd and nmsub instructions. */
891 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
892 || ISA_MIPS64) \
893 && (!TARGET_MIPS5400 || TARGET_MAD) \
894 && ! TARGET_MIPS16)
895
896 /* ISA has count leading zeroes/ones instruction (not implemented). */
897 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
898 || ISA_MIPS32R2 \
899 || ISA_MIPS64 \
900 ) && !TARGET_MIPS16)
901
902 /* ISA has double-word count leading zeroes/ones instruction (not
903 implemented). */
904 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
905 && !TARGET_MIPS16)
906
907 /* ISA has three operand multiply instructions that put
908 the high part in an accumulator: mulhi or mulhiu. */
909 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
910 || TARGET_MIPS5500 \
911 || TARGET_SR71K \
912 )
913
914 /* ISA has three operand multiply instructions that
915 negates the result and puts the result in an accumulator. */
916 #define ISA_HAS_MULS (TARGET_MIPS5400 \
917 || TARGET_MIPS5500 \
918 || TARGET_SR71K \
919 )
920
921 /* ISA has three operand multiply instructions that subtracts the
922 result from a 4th operand and puts the result in an accumulator. */
923 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
924 || TARGET_MIPS5500 \
925 || TARGET_SR71K \
926 )
927 /* ISA has three operand multiply instructions that the result
928 from a 4th operand and puts the result in an accumulator. */
929 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
930 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
931 || TARGET_MIPS5400 \
932 || TARGET_MIPS5500 \
933 || TARGET_SR71K \
934 )
935
936 /* ISA has 32-bit rotate right instruction. */
937 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
938 && (ISA_MIPS32R2 \
939 || TARGET_MIPS5400 \
940 || TARGET_MIPS5500 \
941 || TARGET_SR71K \
942 ))
943
944 /* ISA has 64-bit rotate right instruction. */
945 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
946 && !TARGET_MIPS16 \
947 && (TARGET_MIPS5400 \
948 || TARGET_MIPS5500 \
949 || TARGET_SR71K \
950 ))
951
952 /* ISA has data prefetch instructions. This controls use of 'pref'. */
953 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
954 || ISA_MIPS32 \
955 || ISA_MIPS32R2 \
956 || ISA_MIPS64) \
957 && !TARGET_MIPS16)
958
959 /* ISA has data indexed prefetch instructions. This controls use of
960 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
961 (prefx is a cop1x instruction, so can only be used if FP is
962 enabled.) */
963 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
964 || ISA_MIPS64) \
965 && !TARGET_MIPS16)
966
967 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
968 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
969 also requires TARGET_DOUBLE_FLOAT. */
970 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
971
972 /* ISA includes the MIPS32r2 seb and seh instructions. */
973 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
974 && (ISA_MIPS32R2 \
975 ))
976
977 /* True if the result of a load is not available to the next instruction.
978 A nop will then be needed between instructions like "lw $4,..."
979 and "addiu $4,$4,1". */
980 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
981 && !TARGET_MIPS3900 \
982 && !TARGET_MIPS16)
983
984 /* Likewise mtc1 and mfc1. */
985 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
986
987 /* Likewise floating-point comparisons. */
988 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
989
990 /* True if mflo and mfhi can be immediately followed by instructions
991 which write to the HI and LO registers.
992
993 According to MIPS specifications, MIPS ISAs I, II, and III need
994 (at least) two instructions between the reads of HI/LO and
995 instructions which write them, and later ISAs do not. Contradicting
996 the MIPS specifications, some MIPS IV processor user manuals (e.g.
997 the UM for the NEC Vr5000) document needing the instructions between
998 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
999 MIPS64 and later ISAs to have the interlocks, plus any specific
1000 earlier-ISA CPUs for which CPU documentation declares that the
1001 instructions are really interlocked. */
1002 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1003 || ISA_MIPS32R2 \
1004 || ISA_MIPS64 \
1005 || TARGET_MIPS5500)
1006 \f
1007 /* Add -G xx support. */
1008
1009 #undef SWITCH_TAKES_ARG
1010 #define SWITCH_TAKES_ARG(CHAR) \
1011 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1012
1013 #define OVERRIDE_OPTIONS override_options ()
1014
1015 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1016
1017 /* Show we can debug even without a frame pointer. */
1018 #define CAN_DEBUG_WITHOUT_FP
1019 \f
1020 /* Tell collect what flags to pass to nm. */
1021 #ifndef NM_FLAGS
1022 #define NM_FLAGS "-Bn"
1023 #endif
1024
1025 \f
1026 /* Assembler specs. */
1027
1028 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
1029 than gas. */
1030
1031 #define MIPS_AS_ASM_SPEC "\
1032 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
1033 %{pipe: %e-pipe is not supported} \
1034 %{K} %(subtarget_mips_as_asm_spec)"
1035
1036 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
1037 rather than gas. It may be overridden by subtargets. */
1038
1039 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
1040 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
1041 #endif
1042
1043 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
1044 assembler. */
1045
1046 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1047
1048 #define SUBTARGET_TARGET_SWITCHES
1049
1050 #ifndef MIPS_ABI_DEFAULT
1051 #define MIPS_ABI_DEFAULT ABI_32
1052 #endif
1053
1054 /* Use the most portable ABI flag for the ASM specs. */
1055
1056 #if MIPS_ABI_DEFAULT == ABI_32
1057 #define MULTILIB_ABI_DEFAULT "mabi=32"
1058 #define ASM_ABI_DEFAULT_SPEC "-32"
1059 #endif
1060
1061 #if MIPS_ABI_DEFAULT == ABI_O64
1062 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1063 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1064 #endif
1065
1066 #if MIPS_ABI_DEFAULT == ABI_N32
1067 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1068 #define ASM_ABI_DEFAULT_SPEC "-n32"
1069 #endif
1070
1071 #if MIPS_ABI_DEFAULT == ABI_64
1072 #define MULTILIB_ABI_DEFAULT "mabi=64"
1073 #define ASM_ABI_DEFAULT_SPEC "-64"
1074 #endif
1075
1076 #if MIPS_ABI_DEFAULT == ABI_EABI
1077 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1078 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1079 #endif
1080
1081 /* Only ELF targets can switch the ABI. */
1082 #ifndef OBJECT_FORMAT_ELF
1083 #undef ASM_ABI_DEFAULT_SPEC
1084 #define ASM_ABI_DEFAULT_SPEC ""
1085 #endif
1086
1087 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1088 GAS_ASM_SPEC as the default, depending upon the value of
1089 TARGET_DEFAULT. */
1090
1091 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1092 /* GAS */
1093
1094 #define TARGET_ASM_SPEC "\
1095 %{mmips-as: %(mips_as_asm_spec)} \
1096 %{!mmips-as: %(gas_asm_spec)}"
1097
1098 #else /* not GAS */
1099
1100 #define TARGET_ASM_SPEC "\
1101 %{!mgas: %(mips_as_asm_spec)} \
1102 %{mgas: %(gas_asm_spec)}"
1103
1104 #endif /* not GAS */
1105
1106 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1107 to the assembler. It may be overridden by subtargets. */
1108 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1109 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1110 %{noasmopt:-O0} \
1111 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1112 #endif
1113
1114 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1115 the assembler. It may be overridden by subtargets. */
1116 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1117 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1118 %{g} %{g0} %{g1} %{g2} %{g3} \
1119 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1120 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1121 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1122 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1123 %(mdebug_asm_spec)"
1124 #endif
1125
1126 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1127 debugging info. */
1128 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1129 /* GAS */
1130 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1131 %{!gcoff*:-no-mdebug}"
1132 #else /* not GAS */
1133 #define MDEBUG_ASM_SPEC ""
1134 #endif /* not GAS */
1135
1136 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1137 overridden by subtargets. */
1138
1139 #ifndef SUBTARGET_ASM_SPEC
1140 #define SUBTARGET_ASM_SPEC ""
1141 #endif
1142
1143 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1144 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1145 whether we're using GAS. These options can only be used properly
1146 with GAS, and it is better to get an error from a non-GAS assembler
1147 than to silently generate bad code. */
1148
1149 #undef ASM_SPEC
1150 #define ASM_SPEC "\
1151 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1152 %{mips32} %{mips32r2} %{mips64} \
1153 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1154 %{mfix-vr4120} \
1155 %(subtarget_asm_optimizing_spec) \
1156 %(subtarget_asm_debugging_spec) \
1157 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1158 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1159 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1160 %(target_asm_spec) \
1161 %(subtarget_asm_spec)"
1162
1163 /* Extra switches sometimes passed to the linker. */
1164 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1165 will interpret it as a -b option. */
1166
1167 #ifndef LINK_SPEC
1168 #define LINK_SPEC "\
1169 %(endian_spec) \
1170 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1171 %{bestGnum} %{shared} %{non_shared}"
1172 #endif /* LINK_SPEC defined */
1173
1174
1175 /* Specs for the compiler proper */
1176
1177 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1178 overridden by subtargets. */
1179 #ifndef SUBTARGET_CC1_SPEC
1180 #define SUBTARGET_CC1_SPEC ""
1181 #endif
1182
1183 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1184
1185 #ifndef CC1_SPEC
1186 #define CC1_SPEC "\
1187 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1188 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1189 %{save-temps: } \
1190 %(subtarget_cc1_spec)"
1191 #endif
1192
1193 /* Preprocessor specs. */
1194
1195 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1196 overridden by subtargets. */
1197 #ifndef SUBTARGET_CPP_SPEC
1198 #define SUBTARGET_CPP_SPEC ""
1199 #endif
1200
1201 #define CPP_SPEC "%(subtarget_cpp_spec)"
1202
1203 /* This macro defines names of additional specifications to put in the specs
1204 that can be used in various specifications like CC1_SPEC. Its definition
1205 is an initializer with a subgrouping for each command option.
1206
1207 Each subgrouping contains a string constant, that defines the
1208 specification name, and a string constant that used by the GCC driver
1209 program.
1210
1211 Do not define this macro if it does not need to do anything. */
1212
1213 #define EXTRA_SPECS \
1214 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1215 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1216 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1217 { "gas_asm_spec", GAS_ASM_SPEC }, \
1218 { "target_asm_spec", TARGET_ASM_SPEC }, \
1219 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1220 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1221 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1222 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1223 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1224 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1225 { "endian_spec", ENDIAN_SPEC }, \
1226 SUBTARGET_EXTRA_SPECS
1227
1228 #ifndef SUBTARGET_EXTRA_SPECS
1229 #define SUBTARGET_EXTRA_SPECS
1230 #endif
1231
1232 /* If defined, this macro is an additional prefix to try after
1233 `STANDARD_EXEC_PREFIX'. */
1234
1235 #ifndef MD_EXEC_PREFIX
1236 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1237 #endif
1238
1239 #ifndef MD_STARTFILE_PREFIX
1240 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1241 #endif
1242
1243 \f
1244 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1245 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1246 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1247
1248 #ifndef PREFERRED_DEBUGGING_TYPE
1249 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1250 #endif
1251
1252 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1253
1254 /* By default, turn on GDB extensions. */
1255 #define DEFAULT_GDB_EXTENSIONS 1
1256
1257 /* If we are passing smuggling stabs through the MIPS ECOFF object
1258 format, put a comment in front of the .stab<x> operation so
1259 that the MIPS assembler does not choke. The mips-tfile program
1260 will correctly put the stab into the object file. */
1261
1262 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1263 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1264 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1265
1266 /* Local compiler-generated symbols must have a prefix that the assembler
1267 understands. By default, this is $, although some targets (e.g.,
1268 NetBSD-ELF) need to override this. */
1269
1270 #ifndef LOCAL_LABEL_PREFIX
1271 #define LOCAL_LABEL_PREFIX "$"
1272 #endif
1273
1274 /* By default on the mips, external symbols do not have an underscore
1275 prepended, but some targets (e.g., NetBSD) require this. */
1276
1277 #ifndef USER_LABEL_PREFIX
1278 #define USER_LABEL_PREFIX ""
1279 #endif
1280
1281 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1282 since the length can run past this up to a continuation point. */
1283 #undef DBX_CONTIN_LENGTH
1284 #define DBX_CONTIN_LENGTH 1500
1285
1286 /* How to renumber registers for dbx and gdb. */
1287 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1288
1289 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1290 #define DWARF_FRAME_REGNUM(REG) (REG)
1291
1292 /* The DWARF 2 CFA column which tracks the return address. */
1293 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1294
1295 /* The DWARF 2 CFA column which tracks the return address from a
1296 signal handler context. */
1297 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1298
1299 /* Before the prologue, RA lives in r31. */
1300 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1301
1302 /* Describe how we implement __builtin_eh_return. */
1303 #define EH_RETURN_DATA_REGNO(N) \
1304 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1305
1306 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1307
1308 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1309 The default for this in 64-bit mode is 8, which causes problems with
1310 SFmode register saves. */
1311 #define DWARF_CIE_DATA_ALIGNMENT 4
1312
1313 /* Correct the offset of automatic variables and arguments. Note that
1314 the MIPS debug format wants all automatic variables and arguments
1315 to be in terms of the virtual frame pointer (stack pointer before
1316 any adjustment in the function), while the MIPS 3.0 linker wants
1317 the frame pointer to be the stack pointer after the initial
1318 adjustment. */
1319
1320 #define DEBUGGER_AUTO_OFFSET(X) \
1321 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1322 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1323 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1324 \f
1325 /* Target machine storage layout */
1326
1327 #define BITS_BIG_ENDIAN 0
1328 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1329 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1330
1331 /* Define this to set the endianness to use in libgcc2.c, which can
1332 not depend on target_flags. */
1333 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1334 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1335 #else
1336 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1337 #endif
1338
1339 #define MAX_BITS_PER_WORD 64
1340
1341 /* Width of a word, in units (bytes). */
1342 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1343 #define MIN_UNITS_PER_WORD 4
1344
1345 /* For MIPS, width of a floating point register. */
1346 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1347
1348 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1349 the next available register. */
1350 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1351
1352 /* The largest size of value that can be held in floating-point
1353 registers and moved with a single instruction. */
1354 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1355
1356 /* The largest size of value that can be held in floating-point
1357 registers. */
1358 #define UNITS_PER_FPVALUE \
1359 (TARGET_SOFT_FLOAT ? 0 \
1360 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1361 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1362
1363 /* The number of bytes in a double. */
1364 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1365
1366 /* Set the sizes of the core types. */
1367 #define SHORT_TYPE_SIZE 16
1368 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1369 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1370 #define LONG_LONG_TYPE_SIZE 64
1371
1372 #define FLOAT_TYPE_SIZE 32
1373 #define DOUBLE_TYPE_SIZE 64
1374 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1375
1376 /* long double is not a fixed mode, but the idea is that, if we
1377 support long double, we also want a 128-bit integer type. */
1378 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1379
1380 #ifdef IN_LIBGCC2
1381 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1382 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1383 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1384 # else
1385 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1386 # endif
1387 #endif
1388
1389 /* Width in bits of a pointer. */
1390 #ifndef POINTER_SIZE
1391 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1392 #endif
1393
1394 #define POINTERS_EXTEND_UNSIGNED 0
1395
1396 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1397 #define PARM_BOUNDARY ((mips_abi == ABI_O64 \
1398 || TARGET_NEWABI \
1399 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1400
1401
1402 /* Allocation boundary (in *bits*) for the code of a function. */
1403 #define FUNCTION_BOUNDARY 32
1404
1405 /* Alignment of field after `int : 0' in a structure. */
1406 #define EMPTY_FIELD_BOUNDARY 32
1407
1408 /* Every structure's size must be a multiple of this. */
1409 /* 8 is observed right on a DECstation and on riscos 4.02. */
1410 #define STRUCTURE_SIZE_BOUNDARY 8
1411
1412 /* There is no point aligning anything to a rounder boundary than this. */
1413 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1414
1415 /* All accesses must be aligned. */
1416 #define STRICT_ALIGNMENT 1
1417
1418 /* Define this if you wish to imitate the way many other C compilers
1419 handle alignment of bitfields and the structures that contain
1420 them.
1421
1422 The behavior is that the type written for a bit-field (`int',
1423 `short', or other integer type) imposes an alignment for the
1424 entire structure, as if the structure really did contain an
1425 ordinary field of that type. In addition, the bit-field is placed
1426 within the structure so that it would fit within such a field,
1427 not crossing a boundary for it.
1428
1429 Thus, on most machines, a bit-field whose type is written as `int'
1430 would not cross a four-byte boundary, and would force four-byte
1431 alignment for the whole structure. (The alignment used may not
1432 be four bytes; it is controlled by the other alignment
1433 parameters.)
1434
1435 If the macro is defined, its definition should be a C expression;
1436 a nonzero value for the expression enables this behavior. */
1437
1438 #define PCC_BITFIELD_TYPE_MATTERS 1
1439
1440 /* If defined, a C expression to compute the alignment given to a
1441 constant that is being placed in memory. CONSTANT is the constant
1442 and ALIGN is the alignment that the object would ordinarily have.
1443 The value of this macro is used instead of that alignment to align
1444 the object.
1445
1446 If this macro is not defined, then ALIGN is used.
1447
1448 The typical use of this macro is to increase alignment for string
1449 constants to be word aligned so that `strcpy' calls that copy
1450 constants can be done inline. */
1451
1452 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1453 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1454 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1455
1456 /* If defined, a C expression to compute the alignment for a static
1457 variable. TYPE is the data type, and ALIGN is the alignment that
1458 the object would ordinarily have. The value of this macro is used
1459 instead of that alignment to align the object.
1460
1461 If this macro is not defined, then ALIGN is used.
1462
1463 One use of this macro is to increase alignment of medium-size
1464 data to make it all fit in fewer cache lines. Another is to
1465 cause character arrays to be word-aligned so that `strcpy' calls
1466 that copy constants to character arrays can be done inline. */
1467
1468 #undef DATA_ALIGNMENT
1469 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1470 ((((ALIGN) < BITS_PER_WORD) \
1471 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1472 || TREE_CODE (TYPE) == UNION_TYPE \
1473 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1474
1475
1476 #define PAD_VARARGS_DOWN \
1477 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1478
1479 /* Define if operations between registers always perform the operation
1480 on the full register even if a narrower mode is specified. */
1481 #define WORD_REGISTER_OPERATIONS
1482
1483 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1484 moves. All other references are zero extended. */
1485 #define LOAD_EXTEND_OP(MODE) \
1486 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1487 ? SIGN_EXTEND : ZERO_EXTEND)
1488
1489 /* Define this macro if it is advisable to hold scalars in registers
1490 in a wider mode than that declared by the program. In such cases,
1491 the value is constrained to be within the bounds of the declared
1492 type, but kept valid in the wider mode. The signedness of the
1493 extension may differ from that of the type. */
1494
1495 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1496 if (GET_MODE_CLASS (MODE) == MODE_INT \
1497 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1498 { \
1499 if ((MODE) == SImode) \
1500 (UNSIGNEDP) = 0; \
1501 (MODE) = Pmode; \
1502 }
1503
1504 /* Define if loading short immediate values into registers sign extends. */
1505 #define SHORT_IMMEDIATES_SIGN_EXTEND
1506 \f
1507 /* Standard register usage. */
1508
1509 /* Number of hardware registers. We have:
1510
1511 - 32 integer registers
1512 - 32 floating point registers
1513 - 8 condition code registers
1514 - 2 accumulator registers (hi and lo)
1515 - 32 registers each for coprocessors 0, 2 and 3
1516 - 3 fake registers:
1517 - ARG_POINTER_REGNUM
1518 - FRAME_POINTER_REGNUM
1519 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1520 - 3 dummy entries that were used at various times in the past. */
1521
1522 #define FIRST_PSEUDO_REGISTER 176
1523
1524 /* By default, fix the kernel registers ($26 and $27), the global
1525 pointer ($28) and the stack pointer ($29). This can change
1526 depending on the command-line options.
1527
1528 Regarding coprocessor registers: without evidence to the contrary,
1529 it's best to assume that each coprocessor register has a unique
1530 use. This can be overridden, in, e.g., override_options() or
1531 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1532 for a particular target. */
1533
1534 #define FIXED_REGISTERS \
1535 { \
1536 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1537 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1538 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1539 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1540 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1541 /* COP0 registers */ \
1542 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1543 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1544 /* COP2 registers */ \
1545 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1547 /* COP3 registers */ \
1548 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1550 }
1551
1552
1553 /* Set up this array for o32 by default.
1554
1555 Note that we don't mark $31 as a call-clobbered register. The idea is
1556 that it's really the call instructions themselves which clobber $31.
1557 We don't care what the called function does with it afterwards.
1558
1559 This approach makes it easier to implement sibcalls. Unlike normal
1560 calls, sibcalls don't clobber $31, so the register reaches the
1561 called function in tact. EPILOGUE_USES says that $31 is useful
1562 to the called function. */
1563
1564 #define CALL_USED_REGISTERS \
1565 { \
1566 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1567 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1569 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1570 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1571 /* COP0 registers */ \
1572 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1573 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1574 /* COP2 registers */ \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1577 /* COP3 registers */ \
1578 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1580 }
1581
1582
1583 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1584
1585 #define CALL_REALLY_USED_REGISTERS \
1586 { /* General registers. */ \
1587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1588 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1589 /* Floating-point registers. */ \
1590 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1591 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1592 /* Others. */ \
1593 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1594 /* COP0 registers */ \
1595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1596 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1597 /* COP2 registers */ \
1598 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1600 /* COP3 registers */ \
1601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1602 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1603 }
1604
1605 /* Internal macros to classify a register number as to whether it's a
1606 general purpose register, a floating point register, a
1607 multiply/divide register, or a status register. */
1608
1609 #define GP_REG_FIRST 0
1610 #define GP_REG_LAST 31
1611 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1612 #define GP_DBX_FIRST 0
1613
1614 #define FP_REG_FIRST 32
1615 #define FP_REG_LAST 63
1616 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1617 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1618
1619 #define MD_REG_FIRST 64
1620 #define MD_REG_LAST 65
1621 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1622 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1623
1624 #define ST_REG_FIRST 67
1625 #define ST_REG_LAST 74
1626 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1627
1628
1629 /* FIXME: renumber. */
1630 #define COP0_REG_FIRST 80
1631 #define COP0_REG_LAST 111
1632 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1633
1634 #define COP2_REG_FIRST 112
1635 #define COP2_REG_LAST 143
1636 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1637
1638 #define COP3_REG_FIRST 144
1639 #define COP3_REG_LAST 175
1640 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1641 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1642 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1643
1644 #define AT_REGNUM (GP_REG_FIRST + 1)
1645 #define HI_REGNUM (MD_REG_FIRST + 0)
1646 #define LO_REGNUM (MD_REG_FIRST + 1)
1647
1648 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1649 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1650 should be used instead. */
1651 #define FPSW_REGNUM ST_REG_FIRST
1652
1653 #define GP_REG_P(REGNO) \
1654 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1655 #define M16_REG_P(REGNO) \
1656 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1657 #define FP_REG_P(REGNO) \
1658 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1659 #define MD_REG_P(REGNO) \
1660 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1661 #define ST_REG_P(REGNO) \
1662 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1663 #define COP0_REG_P(REGNO) \
1664 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1665 #define COP2_REG_P(REGNO) \
1666 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1667 #define COP3_REG_P(REGNO) \
1668 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1669 #define ALL_COP_REG_P(REGNO) \
1670 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1671
1672 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1673
1674 /* Return coprocessor number from register number. */
1675
1676 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1677 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1678 : COP3_REG_P (REGNO) ? '3' : '?')
1679
1680
1681 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1682
1683 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1684 array built in override_options. Because machmodes.h is not yet
1685 included before this file is processed, the MODE bound can't be
1686 expressed here. */
1687
1688 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1689
1690 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1691 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1692
1693 /* Value is 1 if it is a good idea to tie two pseudo registers
1694 when one has mode MODE1 and one has mode MODE2.
1695 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1696 for any hard reg, then this must be 0 for correct output. */
1697 #define MODES_TIEABLE_P(MODE1, MODE2) \
1698 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1699 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1700 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1701 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1702
1703 /* Register to use for pushing function arguments. */
1704 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1705
1706 /* These two registers don't really exist: they get eliminated to either
1707 the stack or hard frame pointer. */
1708 #define ARG_POINTER_REGNUM 77
1709 #define FRAME_POINTER_REGNUM 78
1710
1711 /* $30 is not available on the mips16, so we use $17 as the frame
1712 pointer. */
1713 #define HARD_FRAME_POINTER_REGNUM \
1714 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1715
1716 /* Value should be nonzero if functions must have frame pointers.
1717 Zero means the frame pointer need not be set up (and parms
1718 may be accessed via the stack pointer) in functions that seem suitable.
1719 This is computed in `reload', in reload1.c. */
1720 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1721
1722 /* Register in which static-chain is passed to a function. */
1723 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1724
1725 /* Registers used as temporaries in prologue/epilogue code. If we're
1726 generating mips16 code, these registers must come from the core set
1727 of 8. The prologue register mustn't conflict with any incoming
1728 arguments, the static chain pointer, or the frame pointer. The
1729 epilogue temporary mustn't conflict with the return registers, the
1730 frame pointer, the EH stack adjustment, or the EH data registers. */
1731
1732 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1733 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1734
1735 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1736 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1737
1738 /* Define this macro if it is as good or better to call a constant
1739 function address than to call an address kept in a register. */
1740 #define NO_FUNCTION_CSE 1
1741
1742 /* The ABI-defined global pointer. Sometimes we use a different
1743 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1744 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1745
1746 /* We normally use $28 as the global pointer. However, when generating
1747 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1748 register instead. They can then avoid saving and restoring $28
1749 and perhaps avoid using a frame at all.
1750
1751 When a leaf function uses something other than $28, mips_expand_prologue
1752 will modify pic_offset_table_rtx in place. Take the register number
1753 from there after reload. */
1754 #define PIC_OFFSET_TABLE_REGNUM \
1755 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1756
1757 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1758 \f
1759 /* Define the classes of registers for register constraints in the
1760 machine description. Also define ranges of constants.
1761
1762 One of the classes must always be named ALL_REGS and include all hard regs.
1763 If there is more than one class, another class must be named NO_REGS
1764 and contain no registers.
1765
1766 The name GENERAL_REGS must be the name of a class (or an alias for
1767 another name such as ALL_REGS). This is the class of registers
1768 that is allowed by "g" or "r" in a register constraint.
1769 Also, registers outside this class are allocated only when
1770 instructions express preferences for them.
1771
1772 The classes must be numbered in nondecreasing order; that is,
1773 a larger-numbered class must never be contained completely
1774 in a smaller-numbered class.
1775
1776 For any two classes, it is very desirable that there be another
1777 class that represents their union. */
1778
1779 enum reg_class
1780 {
1781 NO_REGS, /* no registers in set */
1782 M16_NA_REGS, /* mips16 regs not used to pass args */
1783 M16_REGS, /* mips16 directly accessible registers */
1784 T_REG, /* mips16 T register ($24) */
1785 M16_T_REGS, /* mips16 registers plus T register */
1786 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1787 LEA_REGS, /* Every GPR except $25 */
1788 GR_REGS, /* integer registers */
1789 FP_REGS, /* floating point registers */
1790 HI_REG, /* hi register */
1791 LO_REG, /* lo register */
1792 MD_REGS, /* multiply/divide registers (hi/lo) */
1793 COP0_REGS, /* generic coprocessor classes */
1794 COP2_REGS,
1795 COP3_REGS,
1796 HI_AND_GR_REGS, /* union classes */
1797 LO_AND_GR_REGS,
1798 HI_AND_FP_REGS,
1799 COP0_AND_GR_REGS,
1800 COP2_AND_GR_REGS,
1801 COP3_AND_GR_REGS,
1802 ALL_COP_REGS,
1803 ALL_COP_AND_GR_REGS,
1804 ST_REGS, /* status registers (fp status) */
1805 ALL_REGS, /* all registers */
1806 LIM_REG_CLASSES /* max value + 1 */
1807 };
1808
1809 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1810
1811 #define GENERAL_REGS GR_REGS
1812
1813 /* An initializer containing the names of the register classes as C
1814 string constants. These names are used in writing some of the
1815 debugging dumps. */
1816
1817 #define REG_CLASS_NAMES \
1818 { \
1819 "NO_REGS", \
1820 "M16_NA_REGS", \
1821 "M16_REGS", \
1822 "T_REG", \
1823 "M16_T_REGS", \
1824 "PIC_FN_ADDR_REG", \
1825 "LEA_REGS", \
1826 "GR_REGS", \
1827 "FP_REGS", \
1828 "HI_REG", \
1829 "LO_REG", \
1830 "MD_REGS", \
1831 /* coprocessor registers */ \
1832 "COP0_REGS", \
1833 "COP2_REGS", \
1834 "COP3_REGS", \
1835 "HI_AND_GR_REGS", \
1836 "LO_AND_GR_REGS", \
1837 "HI_AND_FP_REGS", \
1838 "COP0_AND_GR_REGS", \
1839 "COP2_AND_GR_REGS", \
1840 "COP3_AND_GR_REGS", \
1841 "ALL_COP_REGS", \
1842 "ALL_COP_AND_GR_REGS", \
1843 "ST_REGS", \
1844 "ALL_REGS" \
1845 }
1846
1847 /* An initializer containing the contents of the register classes,
1848 as integers which are bit masks. The Nth integer specifies the
1849 contents of class N. The way the integer MASK is interpreted is
1850 that register R is in the class if `MASK & (1 << R)' is 1.
1851
1852 When the machine has more than 32 registers, an integer does not
1853 suffice. Then the integers are replaced by sub-initializers,
1854 braced groupings containing several integers. Each
1855 sub-initializer must be suitable as an initializer for the type
1856 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1857
1858 #define REG_CLASS_CONTENTS \
1859 { \
1860 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1861 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1862 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1863 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1864 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1865 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1866 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1867 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1868 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1869 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1870 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1871 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1872 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1873 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1874 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1875 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1876 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1877 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1878 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1879 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1880 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1881 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1882 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1883 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1884 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1885 }
1886
1887
1888 /* A C expression whose value is a register class containing hard
1889 register REGNO. In general there is more that one such class;
1890 choose a class which is "minimal", meaning that no smaller class
1891 also contains the register. */
1892
1893 extern const enum reg_class mips_regno_to_class[];
1894
1895 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1896
1897 /* A macro whose definition is the name of the class to which a
1898 valid base register must belong. A base register is one used in
1899 an address which is the register value plus a displacement. */
1900
1901 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1902
1903 /* A macro whose definition is the name of the class to which a
1904 valid index register must belong. An index register is one used
1905 in an address where its value is either multiplied by a scale
1906 factor or added to another register (as well as added to a
1907 displacement). */
1908
1909 #define INDEX_REG_CLASS NO_REGS
1910
1911 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1912 registers explicitly used in the rtl to be used as spill registers
1913 but prevents the compiler from extending the lifetime of these
1914 registers. */
1915
1916 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1917
1918 /* This macro is used later on in the file. */
1919 #define GR_REG_CLASS_P(CLASS) \
1920 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1921 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1922 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1923
1924 /* This macro is also used later on in the file. */
1925 #define COP_REG_CLASS_P(CLASS) \
1926 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1927
1928 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1929 is the default value (allocate the registers in numeric order). We
1930 define it just so that we can override it for the mips16 target in
1931 ORDER_REGS_FOR_LOCAL_ALLOC. */
1932
1933 #define REG_ALLOC_ORDER \
1934 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1935 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1936 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1937 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1938 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1939 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1940 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1941 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1942 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1943 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1944 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1945 }
1946
1947 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1948 to be rearranged based on a particular function. On the mips16, we
1949 want to allocate $24 (T_REG) before other registers for
1950 instructions for which it is possible. */
1951
1952 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1953
1954 /* REGISTER AND CONSTANT CLASSES */
1955
1956 /* Get reg_class from a letter such as appears in the machine
1957 description.
1958
1959 DEFINED REGISTER CLASSES:
1960
1961 'd' General (aka integer) registers
1962 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1963 'y' General registers (in both mips16 and non mips16 mode)
1964 'e' Effective address registers (general registers except $25)
1965 't' mips16 temporary register ($24)
1966 'f' Floating point registers
1967 'h' Hi register
1968 'l' Lo register
1969 'x' Multiply/divide registers
1970 'z' FP Status register
1971 'B' Cop0 register
1972 'C' Cop2 register
1973 'D' Cop3 register
1974 'b' All registers */
1975
1976 extern enum reg_class mips_char_to_class[256];
1977
1978 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1979
1980 /* True if VALUE is a signed 16-bit number. */
1981
1982 #define SMALL_OPERAND(VALUE) \
1983 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1984
1985 /* True if VALUE is an unsigned 16-bit number. */
1986
1987 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1988 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1989
1990 /* True if VALUE can be loaded into a register using LUI. */
1991
1992 #define LUI_OPERAND(VALUE) \
1993 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1994 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1995
1996 /* Return a value X with the low 16 bits clear, and such that
1997 VALUE - X is a signed 16-bit value. */
1998
1999 #define CONST_HIGH_PART(VALUE) \
2000 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2001
2002 #define CONST_LOW_PART(VALUE) \
2003 ((VALUE) - CONST_HIGH_PART (VALUE))
2004
2005 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2006 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2007 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2008
2009 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2010 string can be used to stand for particular ranges of immediate
2011 operands. This macro defines what the ranges are. C is the
2012 letter, and VALUE is a constant value. Return 1 if VALUE is
2013 in the range specified by C. */
2014
2015 /* For MIPS:
2016
2017 `I' is used for the range of constants an arithmetic insn can
2018 actually contain (16 bits signed integers).
2019
2020 `J' is used for the range which is just zero (ie, $r0).
2021
2022 `K' is used for the range of constants a logical insn can actually
2023 contain (16 bit zero-extended integers).
2024
2025 `L' is used for the range of constants that be loaded with lui
2026 (ie, the bottom 16 bits are zero).
2027
2028 `M' is used for the range of constants that take two words to load
2029 (ie, not matched by `I', `K', and `L').
2030
2031 `N' is used for negative 16 bit constants other than -65536.
2032
2033 `O' is a 15 bit signed integer.
2034
2035 `P' is used for positive 16 bit constants. */
2036
2037 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2038 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
2039 : (C) == 'J' ? ((VALUE) == 0) \
2040 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
2041 : (C) == 'L' ? LUI_OPERAND (VALUE) \
2042 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
2043 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2044 && !LUI_OPERAND (VALUE)) \
2045 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2046 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2047 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2048 : 0)
2049
2050 /* Similar, but for floating constants, and defining letters G and H.
2051 Here VALUE is the CONST_DOUBLE rtx itself. */
2052
2053 /* For Mips
2054
2055 'G' : Floating point 0 */
2056
2057 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2058 ((C) == 'G' \
2059 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2060
2061 /* Letters in the range `Q' through `U' may be defined in a
2062 machine-dependent fashion to stand for arbitrary operand types.
2063 The machine description macro `EXTRA_CONSTRAINT' is passed the
2064 operand as its first argument and the constraint letter as its
2065 second operand.
2066
2067 `Q' is for signed 16-bit constants.
2068 `R' is for single-instruction memory references. Note that this
2069 constraint has often been used in linux and glibc code.
2070 `S' is for legitimate constant call addresses.
2071 `T' is for constant move_operands that cannot be safely loaded into $25.
2072 `U' is for constant move_operands that can be safely loaded into $25.
2073 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2074 This is true for all non-mips16 references (although it can sometimes
2075 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2076 stack and constant-pool references. */
2077
2078 #define EXTRA_CONSTRAINT(OP,CODE) \
2079 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2080 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2081 && mips_fetch_insns (OP) == 1) \
2082 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2083 && call_insn_operand (OP, VOIDmode)) \
2084 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2085 && move_operand (OP, VOIDmode) \
2086 && mips_dangerous_for_la25_p (OP)) \
2087 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2088 && move_operand (OP, VOIDmode) \
2089 && !mips_dangerous_for_la25_p (OP)) \
2090 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2091 && memory_operand (OP, VOIDmode) \
2092 && (!TARGET_MIPS16 \
2093 || (!stack_operand (OP, VOIDmode) \
2094 && !CONSTANT_P (XEXP (OP, 0))))) \
2095 : FALSE)
2096
2097 /* Say which of the above are memory constraints. */
2098 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2099
2100 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2101 mips_preferred_reload_class (X, CLASS)
2102
2103 /* Certain machines have the property that some registers cannot be
2104 copied to some other registers without using memory. Define this
2105 macro on those machines to be a C expression that is nonzero if
2106 objects of mode MODE in registers of CLASS1 can only be copied to
2107 registers of class CLASS2 by storing a register of CLASS1 into
2108 memory and loading that memory location into a register of CLASS2.
2109
2110 Do not define this macro if its value would always be zero. */
2111 #if 0
2112 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2113 ((!TARGET_DEBUG_H_MODE \
2114 && GET_MODE_CLASS (MODE) == MODE_INT \
2115 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2116 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2117 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2118 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2119 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2120 #endif
2121 /* The HI and LO registers can only be reloaded via the general
2122 registers. Condition code registers can only be loaded to the
2123 general registers, and from the floating point registers. */
2124
2125 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2126 mips_secondary_reload_class (CLASS, MODE, X, 1)
2127 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2128 mips_secondary_reload_class (CLASS, MODE, X, 0)
2129
2130 /* Return the maximum number of consecutive registers
2131 needed to represent mode MODE in a register of class CLASS. */
2132
2133 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2134
2135 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2136 mips_cannot_change_mode_class (FROM, TO, CLASS)
2137 \f
2138 /* Stack layout; function entry, exit and calling. */
2139
2140 #define STACK_GROWS_DOWNWARD
2141
2142 /* The offset of the first local variable from the beginning of the frame.
2143 See compute_frame_size for details about the frame layout. */
2144 #define STARTING_FRAME_OFFSET \
2145 (current_function_outgoing_args_size \
2146 + (TARGET_ABICALLS && !TARGET_NEWABI \
2147 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2148
2149 #define RETURN_ADDR_RTX mips_return_addr
2150
2151 /* Since the mips16 ISA mode is encoded in the least-significant bit
2152 of the address, mask it off return addresses for purposes of
2153 finding exception handling regions. */
2154
2155 #define MASK_RETURN_ADDR GEN_INT (-2)
2156
2157
2158 /* Similarly, don't use the least-significant bit to tell pointers to
2159 code from vtable index. */
2160
2161 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2162
2163 /* The eliminations to $17 are only used for mips16 code. See the
2164 definition of HARD_FRAME_POINTER_REGNUM. */
2165
2166 #define ELIMINABLE_REGS \
2167 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2168 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2169 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2170 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2171 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2172 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2173
2174 /* We can always eliminate to the hard frame pointer. We can eliminate
2175 to the stack pointer unless a frame pointer is needed.
2176
2177 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2178 reload may be unable to compute the address of a local variable,
2179 since there is no way to add a large constant to the stack pointer
2180 without using a temporary register. */
2181 #define CAN_ELIMINATE(FROM, TO) \
2182 ((TO) == HARD_FRAME_POINTER_REGNUM \
2183 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2184 && (!TARGET_MIPS16 \
2185 || compute_frame_size (get_frame_size ()) < 32768)))
2186
2187 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2188 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2189
2190 /* Allocate stack space for arguments at the beginning of each function. */
2191 #define ACCUMULATE_OUTGOING_ARGS 1
2192
2193 /* The argument pointer always points to the first argument. */
2194 #define FIRST_PARM_OFFSET(FNDECL) 0
2195
2196 /* o32 and o64 reserve stack space for all argument registers. */
2197 #define REG_PARM_STACK_SPACE(FNDECL) \
2198 (TARGET_OLDABI \
2199 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2200 : 0)
2201
2202 /* Define this if it is the responsibility of the caller to
2203 allocate the area reserved for arguments passed in registers.
2204 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2205 of this macro is to determine whether the space is included in
2206 `current_function_outgoing_args_size'. */
2207 #define OUTGOING_REG_PARM_STACK_SPACE
2208
2209 #define STACK_BOUNDARY ((TARGET_OLDABI || mips_abi == ABI_EABI) ? 64 : 128)
2210 \f
2211 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2212
2213 /* Symbolic macros for the registers used to return integer and floating
2214 point values. */
2215
2216 #define GP_RETURN (GP_REG_FIRST + 2)
2217 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2218
2219 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2220
2221 /* Symbolic macros for the first/last argument registers. */
2222
2223 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2224 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2225 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2226 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2227
2228 #define LIBCALL_VALUE(MODE) \
2229 mips_function_value (NULL_TREE, NULL, (MODE))
2230
2231 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2232 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2233
2234 /* 1 if N is a possible register number for a function value.
2235 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2236 Currently, R2 and F0 are only implemented here (C has no complex type) */
2237
2238 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2239 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2240 && (N) == FP_RETURN + 2))
2241
2242 /* 1 if N is a possible register number for function argument passing.
2243 We have no FP argument registers when soft-float. When FP registers
2244 are 32 bits, we can't directly reference the odd numbered ones. */
2245
2246 #define FUNCTION_ARG_REGNO_P(N) \
2247 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2248 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2249 && !fixed_regs[N])
2250 \f
2251 /* This structure has to cope with two different argument allocation
2252 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2253 first N words go in registers and the rest go on the stack. If I < N,
2254 the Ith word might go in Ith integer argument register or the
2255 Ith floating-point one. For these ABIs, we only need to remember
2256 the number of words passed so far.
2257
2258 The EABI instead allocates the integer and floating-point arguments
2259 separately. The first N words of FP arguments go in FP registers,
2260 the rest go on the stack. Likewise, the first N words of the other
2261 arguments go in integer registers, and the rest go on the stack. We
2262 need to maintain three counts: the number of integer registers used,
2263 the number of floating-point registers used, and the number of words
2264 passed on the stack.
2265
2266 We could keep separate information for the two ABIs (a word count for
2267 the standard ABIs, and three separate counts for the EABI). But it
2268 seems simpler to view the standard ABIs as forms of EABI that do not
2269 allocate floating-point registers.
2270
2271 So for the standard ABIs, the first N words are allocated to integer
2272 registers, and function_arg decides on an argument-by-argument basis
2273 whether that argument should really go in an integer register, or in
2274 a floating-point one. */
2275
2276 typedef struct mips_args {
2277 /* Always true for varargs functions. Otherwise true if at least
2278 one argument has been passed in an integer register. */
2279 int gp_reg_found;
2280
2281 /* The number of arguments seen so far. */
2282 unsigned int arg_number;
2283
2284 /* For EABI, the number of integer registers used so far. For other
2285 ABIs, the number of words passed in registers (whether integer
2286 or floating-point). */
2287 unsigned int num_gprs;
2288
2289 /* For EABI, the number of floating-point registers used so far. */
2290 unsigned int num_fprs;
2291
2292 /* The number of words passed on the stack. */
2293 unsigned int stack_words;
2294
2295 /* On the mips16, we need to keep track of which floating point
2296 arguments were passed in general registers, but would have been
2297 passed in the FP regs if this were a 32 bit function, so that we
2298 can move them to the FP regs if we wind up calling a 32 bit
2299 function. We record this information in fp_code, encoded in base
2300 four. A zero digit means no floating point argument, a one digit
2301 means an SFmode argument, and a two digit means a DFmode argument,
2302 and a three digit is not used. The low order digit is the first
2303 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2304 an SFmode argument. ??? A more sophisticated approach will be
2305 needed if MIPS_ABI != ABI_32. */
2306 int fp_code;
2307
2308 /* True if the function has a prototype. */
2309 int prototype;
2310 } CUMULATIVE_ARGS;
2311
2312 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2313 for a call to a function whose data type is FNTYPE.
2314 For a library call, FNTYPE is 0. */
2315
2316 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2317 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2318
2319 /* Update the data in CUM to advance over an argument
2320 of mode MODE and data type TYPE.
2321 (TYPE is null for libcalls where that information may not be available.) */
2322
2323 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2324 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2325
2326 /* Determine where to put an argument to a function.
2327 Value is zero to push the argument on the stack,
2328 or a hard register in which to store the argument.
2329
2330 MODE is the argument's machine mode.
2331 TYPE is the data type of the argument (as a tree).
2332 This is null for libcalls where that information may
2333 not be available.
2334 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2335 the preceding args and about the function being called.
2336 NAMED is nonzero if this argument is a named parameter
2337 (otherwise it is an extra parameter matching an ellipsis). */
2338
2339 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2340 function_arg( &CUM, MODE, TYPE, NAMED)
2341
2342 /* For an arg passed partly in registers and partly in memory,
2343 this is the number of registers used.
2344 For args passed entirely in registers or entirely in memory, zero. */
2345
2346 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2347 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2348
2349 /* If defined, a C expression that gives the alignment boundary, in
2350 bits, of an argument with the specified mode and type. If it is
2351 not defined, `PARM_BOUNDARY' is used for all arguments. */
2352
2353 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2354 (((TYPE) != 0) \
2355 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2356 ? PARM_BOUNDARY \
2357 : TYPE_ALIGN(TYPE)) \
2358 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2359 ? PARM_BOUNDARY \
2360 : GET_MODE_ALIGNMENT(MODE)))
2361
2362 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2363 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2364
2365 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2366 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2367
2368 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2369 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2370
2371 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2372 (mips_abi == ABI_EABI && (NAMED) \
2373 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2374
2375 /* Modified version of the macro in expr.h. Only return true if
2376 the type has a variable size or if the front end requires it
2377 to be passed by reference. */
2378 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2379 ((TYPE) != 0 \
2380 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2381 || TREE_ADDRESSABLE (TYPE)))
2382
2383 /* True if using EABI and varargs can be passed in floating-point
2384 registers. Under these conditions, we need a more complex form
2385 of va_list, which tracks GPR, FPR and stack arguments separately. */
2386 #define EABI_FLOAT_VARARGS_P \
2387 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2388
2389 \f
2390 /* Say that the epilogue uses the return address register. Note that
2391 in the case of sibcalls, the values "used by the epilogue" are
2392 considered live at the start of the called function. */
2393 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2394
2395 /* Treat LOC as a byte offset from the stack pointer and round it up
2396 to the next fully-aligned offset. */
2397 #define MIPS_STACK_ALIGN(LOC) \
2398 ((TARGET_OLDABI || mips_abi == ABI_EABI) \
2399 ? ((LOC) + 7) & ~7 \
2400 : ((LOC) + 15) & ~15)
2401
2402 \f
2403 /* Implement `va_start' for varargs and stdarg. */
2404 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2405 mips_va_start (valist, nextarg)
2406
2407 /* Implement `va_arg'. */
2408 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2409 mips_va_arg (valist, type)
2410 \f
2411 /* Output assembler code to FILE to increment profiler label # LABELNO
2412 for profiling a function entry. */
2413
2414 #define FUNCTION_PROFILER(FILE, LABELNO) \
2415 { \
2416 if (TARGET_MIPS16) \
2417 sorry ("mips16 function profiling"); \
2418 fprintf (FILE, "\t.set\tnoat\n"); \
2419 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2420 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2421 if (!TARGET_NEWABI) \
2422 { \
2423 fprintf (FILE, \
2424 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2425 TARGET_64BIT ? "dsubu" : "subu", \
2426 reg_names[STACK_POINTER_REGNUM], \
2427 reg_names[STACK_POINTER_REGNUM], \
2428 Pmode == DImode ? 16 : 8); \
2429 } \
2430 fprintf (FILE, "\tjal\t_mcount\n"); \
2431 fprintf (FILE, "\t.set\tat\n"); \
2432 }
2433
2434 /* Define this macro if the code for function profiling should come
2435 before the function prologue. Normally, the profiling code comes
2436 after. */
2437
2438 /* #define PROFILE_BEFORE_PROLOGUE */
2439
2440 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2441 the stack pointer does not matter. The value is tested only in
2442 functions that have frame pointers.
2443 No definition is equivalent to always zero. */
2444
2445 #define EXIT_IGNORE_STACK 1
2446
2447 \f
2448 /* A C statement to output, on the stream FILE, assembler code for a
2449 block of data that contains the constant parts of a trampoline.
2450 This code should not include a label--the label is taken care of
2451 automatically. */
2452
2453 #define TRAMPOLINE_TEMPLATE(STREAM) \
2454 { \
2455 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2456 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2457 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2458 if (ptr_mode == DImode) \
2459 { \
2460 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2461 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2462 } \
2463 else \
2464 { \
2465 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2466 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2467 } \
2468 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2469 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2470 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2471 if (ptr_mode == DImode) \
2472 { \
2473 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2474 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2475 } \
2476 else \
2477 { \
2478 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2479 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2480 } \
2481 }
2482
2483 /* A C expression for the size in bytes of the trampoline, as an
2484 integer. */
2485
2486 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2487
2488 /* Alignment required for trampolines, in bits. */
2489
2490 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2491
2492 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2493 program and data caches. */
2494
2495 #ifndef CACHE_FLUSH_FUNC
2496 #define CACHE_FLUSH_FUNC "_flush_cache"
2497 #endif
2498
2499 /* A C statement to initialize the variable parts of a trampoline.
2500 ADDR is an RTX for the address of the trampoline; FNADDR is an
2501 RTX for the address of the nested function; STATIC_CHAIN is an
2502 RTX for the static chain value that should be passed to the
2503 function when it is called. */
2504
2505 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2506 { \
2507 rtx func_addr, chain_addr; \
2508 \
2509 func_addr = plus_constant (ADDR, 32); \
2510 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2511 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2512 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2513 \
2514 /* Flush both caches. We need to flush the data cache in case \
2515 the system has a write-back cache. */ \
2516 /* ??? Should check the return value for errors. */ \
2517 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2518 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2519 0, VOIDmode, 3, ADDR, Pmode, \
2520 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2521 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2522 }
2523 \f
2524 /* Addressing modes, and classification of registers for them. */
2525
2526 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2527 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2528 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2529
2530 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2531 and check its validity for a certain class.
2532 We have two alternate definitions for each of them.
2533 The usual definition accepts all pseudo regs; the other rejects them all.
2534 The symbol REG_OK_STRICT causes the latter definition to be used.
2535
2536 Most source files want to accept pseudo regs in the hope that
2537 they will get allocated to the class that the insn wants them to be in.
2538 Some source files that are used after register allocation
2539 need to be strict. */
2540
2541 #ifndef REG_OK_STRICT
2542 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2543 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2544 #else
2545 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2546 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2547 #endif
2548
2549 #define REG_OK_FOR_INDEX_P(X) 0
2550
2551 \f
2552 /* Maximum number of registers that can appear in a valid memory address. */
2553
2554 #define MAX_REGS_PER_ADDRESS 1
2555
2556 #ifdef REG_OK_STRICT
2557 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2558 { \
2559 if (mips_legitimate_address_p (MODE, X, 1)) \
2560 goto ADDR; \
2561 }
2562 #else
2563 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2564 { \
2565 if (mips_legitimate_address_p (MODE, X, 0)) \
2566 goto ADDR; \
2567 }
2568 #endif
2569
2570 /* Check for constness inline but use mips_legitimate_address_p
2571 to check whether a constant really is an address. */
2572
2573 #define CONSTANT_ADDRESS_P(X) \
2574 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2575
2576 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2577
2578 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2579 do { \
2580 if (mips_legitimize_address (&(X), MODE)) \
2581 goto WIN; \
2582 } while (0)
2583
2584
2585 /* A C statement or compound statement with a conditional `goto
2586 LABEL;' executed if memory address X (an RTX) can have different
2587 meanings depending on the machine mode of the memory reference it
2588 is used for.
2589
2590 Autoincrement and autodecrement addresses typically have
2591 mode-dependent effects because the amount of the increment or
2592 decrement is the size of the operand being addressed. Some
2593 machines have other mode-dependent addresses. Many RISC machines
2594 have no mode-dependent addresses.
2595
2596 You may assume that ADDR is a valid address for the machine. */
2597
2598 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2599
2600 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2601 'the start of the function that this code is output in'. */
2602
2603 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2604 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2605 asm_fprintf ((FILE), "%U%s", \
2606 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2607 else \
2608 asm_fprintf ((FILE), "%U%s", (NAME))
2609 \f
2610 /* Specify the machine mode that this machine uses
2611 for the index in the tablejump instruction.
2612 ??? Using HImode in mips16 mode can cause overflow. */
2613 #define CASE_VECTOR_MODE \
2614 (TARGET_MIPS16 ? HImode : ptr_mode)
2615
2616 /* Define as C expression which evaluates to nonzero if the tablejump
2617 instruction expects the table to contain offsets from the address of the
2618 table.
2619 Do not define this if the table should contain absolute addresses. */
2620 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2621
2622 /* Define this as 1 if `char' should by default be signed; else as 0. */
2623 #ifndef DEFAULT_SIGNED_CHAR
2624 #define DEFAULT_SIGNED_CHAR 1
2625 #endif
2626
2627 /* Max number of bytes we can move from memory to memory
2628 in one reasonably fast instruction. */
2629 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2630 #define MAX_MOVE_MAX 8
2631
2632 /* Define this macro as a C expression which is nonzero if
2633 accessing less than a word of memory (i.e. a `char' or a
2634 `short') is no faster than accessing a word of memory, i.e., if
2635 such access require more than one instruction or if there is no
2636 difference in cost between byte and (aligned) word loads.
2637
2638 On RISC machines, it tends to generate better code to define
2639 this as 1, since it avoids making a QI or HI mode register. */
2640 #define SLOW_BYTE_ACCESS 1
2641
2642 /* Define this to be nonzero if shift instructions ignore all but the low-order
2643 few bits. */
2644 #define SHIFT_COUNT_TRUNCATED 1
2645
2646 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2647 is done just by pretending it is already truncated. */
2648 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2649 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2650
2651
2652 /* Specify the machine mode that pointers have.
2653 After generation of rtl, the compiler makes no further distinction
2654 between pointers and any other objects of this machine mode. */
2655
2656 #ifndef Pmode
2657 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2658 #endif
2659
2660 /* Give call MEMs SImode since it is the "most permissive" mode
2661 for both 32-bit and 64-bit targets. */
2662
2663 #define FUNCTION_MODE SImode
2664
2665 \f
2666 /* The cost of loading values from the constant pool. It should be
2667 larger than the cost of any constant we want to synthesize in-line. */
2668
2669 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2670
2671 /* A C expression for the cost of moving data from a register in
2672 class FROM to one in class TO. The classes are expressed using
2673 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2674 the default; other values are interpreted relative to that.
2675
2676 It is not required that the cost always equal 2 when FROM is the
2677 same as TO; on some machines it is expensive to move between
2678 registers if they are not general registers.
2679
2680 If reload sees an insn consisting of a single `set' between two
2681 hard registers, and if `REGISTER_MOVE_COST' applied to their
2682 classes returns a value of 2, reload does not check to ensure
2683 that the constraints of the insn are met. Setting a cost of
2684 other than 2 will allow reload to verify that the constraints are
2685 met. You should do this if the `movM' pattern's constraints do
2686 not allow such copying. */
2687
2688 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2689 mips_register_move_cost (MODE, FROM, TO)
2690
2691 /* ??? Fix this to be right for the R8000. */
2692 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2693 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2694 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2695
2696 /* Define if copies to/from condition code registers should be avoided.
2697
2698 This is needed for the MIPS because reload_outcc is not complete;
2699 it needs to handle cases where the source is a general or another
2700 condition code register. */
2701 #define AVOID_CCMODE_COPIES
2702
2703 /* A C expression for the cost of a branch instruction. A value of
2704 1 is the default; other values are interpreted relative to that. */
2705
2706 /* ??? Fix this to be right for the R8000. */
2707 #define BRANCH_COST \
2708 ((! TARGET_MIPS16 \
2709 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2710 ? 2 : 1)
2711
2712 /* If defined, modifies the length assigned to instruction INSN as a
2713 function of the context in which it is used. LENGTH is an lvalue
2714 that contains the initially computed length of the insn and should
2715 be updated with the correct length of the insn. */
2716 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2717 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2718
2719 \f
2720 /* Optionally define this if you have added predicates to
2721 `MACHINE.c'. This macro is called within an initializer of an
2722 array of structures. The first field in the structure is the
2723 name of a predicate and the second field is an array of rtl
2724 codes. For each predicate, list all rtl codes that can be in
2725 expressions matched by the predicate. The list should have a
2726 trailing comma. Here is an example of two entries in the list
2727 for a typical RISC machine:
2728
2729 #define PREDICATE_CODES \
2730 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2731 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2732
2733 Defining this macro does not affect the generated code (however,
2734 incorrect definitions that omit an rtl code that may be matched
2735 by the predicate can cause the compiler to malfunction).
2736 Instead, it allows the table built by `genrecog' to be more
2737 compact and efficient, thus speeding up the compiler. The most
2738 important predicates to include in the list specified by this
2739 macro are thoses used in the most insn patterns. */
2740
2741 #define PREDICATE_CODES \
2742 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
2743 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2744 {"general_symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2745 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2746 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2747 {"const_arith_operand", { CONST_INT }}, \
2748 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2749 UNSPEC_VOLATILE }}, \
2750 {"arith_operand", { REG, CONST_INT, CONST, SUBREG }}, \
2751 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
2752 {"small_int", { CONST_INT }}, \
2753 {"const_float_1_operand", { CONST_DOUBLE }}, \
2754 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2755 {"equality_op", { EQ, NE }}, \
2756 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2757 LTU, LEU }}, \
2758 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2759 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2760 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2761 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2762 SYMBOL_REF, LABEL_REF, SUBREG, \
2763 REG, MEM}}, \
2764 {"stack_operand", { MEM }}, \
2765 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2766 CONST_DOUBLE, CONST }}, \
2767 {"fcc_register_operand", { REG, SUBREG }}, \
2768 {"hilo_operand", { REG }}, \
2769 {"macc_msac_operand", { PLUS, MINUS }}, \
2770 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2771
2772 /* A list of predicates that do special things with modes, and so
2773 should not elicit warnings for VOIDmode match_operand. */
2774
2775 #define SPECIAL_MODE_PREDICATES \
2776 "pc_or_label_operand",
2777 \f
2778 /* Control the assembler format that we output. */
2779
2780 /* Output to assembler file text saying following lines
2781 may contain character constants, extra white space, comments, etc. */
2782
2783 #ifndef ASM_APP_ON
2784 #define ASM_APP_ON " #APP\n"
2785 #endif
2786
2787 /* Output to assembler file text saying following lines
2788 no longer contain unusual constructs. */
2789
2790 #ifndef ASM_APP_OFF
2791 #define ASM_APP_OFF " #NO_APP\n"
2792 #endif
2793
2794 /* How to refer to registers in assembler output.
2795 This sequence is indexed by compiler's hard-register-number (see above).
2796
2797 In order to support the two different conventions for register names,
2798 we use the name of a table set up in mips.c, which is overwritten
2799 if -mrnames is used. */
2800
2801 #define REGISTER_NAMES \
2802 { \
2803 &mips_reg_names[ 0][0], \
2804 &mips_reg_names[ 1][0], \
2805 &mips_reg_names[ 2][0], \
2806 &mips_reg_names[ 3][0], \
2807 &mips_reg_names[ 4][0], \
2808 &mips_reg_names[ 5][0], \
2809 &mips_reg_names[ 6][0], \
2810 &mips_reg_names[ 7][0], \
2811 &mips_reg_names[ 8][0], \
2812 &mips_reg_names[ 9][0], \
2813 &mips_reg_names[10][0], \
2814 &mips_reg_names[11][0], \
2815 &mips_reg_names[12][0], \
2816 &mips_reg_names[13][0], \
2817 &mips_reg_names[14][0], \
2818 &mips_reg_names[15][0], \
2819 &mips_reg_names[16][0], \
2820 &mips_reg_names[17][0], \
2821 &mips_reg_names[18][0], \
2822 &mips_reg_names[19][0], \
2823 &mips_reg_names[20][0], \
2824 &mips_reg_names[21][0], \
2825 &mips_reg_names[22][0], \
2826 &mips_reg_names[23][0], \
2827 &mips_reg_names[24][0], \
2828 &mips_reg_names[25][0], \
2829 &mips_reg_names[26][0], \
2830 &mips_reg_names[27][0], \
2831 &mips_reg_names[28][0], \
2832 &mips_reg_names[29][0], \
2833 &mips_reg_names[30][0], \
2834 &mips_reg_names[31][0], \
2835 &mips_reg_names[32][0], \
2836 &mips_reg_names[33][0], \
2837 &mips_reg_names[34][0], \
2838 &mips_reg_names[35][0], \
2839 &mips_reg_names[36][0], \
2840 &mips_reg_names[37][0], \
2841 &mips_reg_names[38][0], \
2842 &mips_reg_names[39][0], \
2843 &mips_reg_names[40][0], \
2844 &mips_reg_names[41][0], \
2845 &mips_reg_names[42][0], \
2846 &mips_reg_names[43][0], \
2847 &mips_reg_names[44][0], \
2848 &mips_reg_names[45][0], \
2849 &mips_reg_names[46][0], \
2850 &mips_reg_names[47][0], \
2851 &mips_reg_names[48][0], \
2852 &mips_reg_names[49][0], \
2853 &mips_reg_names[50][0], \
2854 &mips_reg_names[51][0], \
2855 &mips_reg_names[52][0], \
2856 &mips_reg_names[53][0], \
2857 &mips_reg_names[54][0], \
2858 &mips_reg_names[55][0], \
2859 &mips_reg_names[56][0], \
2860 &mips_reg_names[57][0], \
2861 &mips_reg_names[58][0], \
2862 &mips_reg_names[59][0], \
2863 &mips_reg_names[60][0], \
2864 &mips_reg_names[61][0], \
2865 &mips_reg_names[62][0], \
2866 &mips_reg_names[63][0], \
2867 &mips_reg_names[64][0], \
2868 &mips_reg_names[65][0], \
2869 &mips_reg_names[66][0], \
2870 &mips_reg_names[67][0], \
2871 &mips_reg_names[68][0], \
2872 &mips_reg_names[69][0], \
2873 &mips_reg_names[70][0], \
2874 &mips_reg_names[71][0], \
2875 &mips_reg_names[72][0], \
2876 &mips_reg_names[73][0], \
2877 &mips_reg_names[74][0], \
2878 &mips_reg_names[75][0], \
2879 &mips_reg_names[76][0], \
2880 &mips_reg_names[77][0], \
2881 &mips_reg_names[78][0], \
2882 &mips_reg_names[79][0], \
2883 &mips_reg_names[80][0], \
2884 &mips_reg_names[81][0], \
2885 &mips_reg_names[82][0], \
2886 &mips_reg_names[83][0], \
2887 &mips_reg_names[84][0], \
2888 &mips_reg_names[85][0], \
2889 &mips_reg_names[86][0], \
2890 &mips_reg_names[87][0], \
2891 &mips_reg_names[88][0], \
2892 &mips_reg_names[89][0], \
2893 &mips_reg_names[90][0], \
2894 &mips_reg_names[91][0], \
2895 &mips_reg_names[92][0], \
2896 &mips_reg_names[93][0], \
2897 &mips_reg_names[94][0], \
2898 &mips_reg_names[95][0], \
2899 &mips_reg_names[96][0], \
2900 &mips_reg_names[97][0], \
2901 &mips_reg_names[98][0], \
2902 &mips_reg_names[99][0], \
2903 &mips_reg_names[100][0], \
2904 &mips_reg_names[101][0], \
2905 &mips_reg_names[102][0], \
2906 &mips_reg_names[103][0], \
2907 &mips_reg_names[104][0], \
2908 &mips_reg_names[105][0], \
2909 &mips_reg_names[106][0], \
2910 &mips_reg_names[107][0], \
2911 &mips_reg_names[108][0], \
2912 &mips_reg_names[109][0], \
2913 &mips_reg_names[110][0], \
2914 &mips_reg_names[111][0], \
2915 &mips_reg_names[112][0], \
2916 &mips_reg_names[113][0], \
2917 &mips_reg_names[114][0], \
2918 &mips_reg_names[115][0], \
2919 &mips_reg_names[116][0], \
2920 &mips_reg_names[117][0], \
2921 &mips_reg_names[118][0], \
2922 &mips_reg_names[119][0], \
2923 &mips_reg_names[120][0], \
2924 &mips_reg_names[121][0], \
2925 &mips_reg_names[122][0], \
2926 &mips_reg_names[123][0], \
2927 &mips_reg_names[124][0], \
2928 &mips_reg_names[125][0], \
2929 &mips_reg_names[126][0], \
2930 &mips_reg_names[127][0], \
2931 &mips_reg_names[128][0], \
2932 &mips_reg_names[129][0], \
2933 &mips_reg_names[130][0], \
2934 &mips_reg_names[131][0], \
2935 &mips_reg_names[132][0], \
2936 &mips_reg_names[133][0], \
2937 &mips_reg_names[134][0], \
2938 &mips_reg_names[135][0], \
2939 &mips_reg_names[136][0], \
2940 &mips_reg_names[137][0], \
2941 &mips_reg_names[138][0], \
2942 &mips_reg_names[139][0], \
2943 &mips_reg_names[140][0], \
2944 &mips_reg_names[141][0], \
2945 &mips_reg_names[142][0], \
2946 &mips_reg_names[143][0], \
2947 &mips_reg_names[144][0], \
2948 &mips_reg_names[145][0], \
2949 &mips_reg_names[146][0], \
2950 &mips_reg_names[147][0], \
2951 &mips_reg_names[148][0], \
2952 &mips_reg_names[149][0], \
2953 &mips_reg_names[150][0], \
2954 &mips_reg_names[151][0], \
2955 &mips_reg_names[152][0], \
2956 &mips_reg_names[153][0], \
2957 &mips_reg_names[154][0], \
2958 &mips_reg_names[155][0], \
2959 &mips_reg_names[156][0], \
2960 &mips_reg_names[157][0], \
2961 &mips_reg_names[158][0], \
2962 &mips_reg_names[159][0], \
2963 &mips_reg_names[160][0], \
2964 &mips_reg_names[161][0], \
2965 &mips_reg_names[162][0], \
2966 &mips_reg_names[163][0], \
2967 &mips_reg_names[164][0], \
2968 &mips_reg_names[165][0], \
2969 &mips_reg_names[166][0], \
2970 &mips_reg_names[167][0], \
2971 &mips_reg_names[168][0], \
2972 &mips_reg_names[169][0], \
2973 &mips_reg_names[170][0], \
2974 &mips_reg_names[171][0], \
2975 &mips_reg_names[172][0], \
2976 &mips_reg_names[173][0], \
2977 &mips_reg_names[174][0], \
2978 &mips_reg_names[175][0] \
2979 }
2980
2981 /* If defined, a C initializer for an array of structures
2982 containing a name and a register number. This macro defines
2983 additional names for hard registers, thus allowing the `asm'
2984 option in declarations to refer to registers using alternate
2985 names.
2986
2987 We define both names for the integer registers here. */
2988
2989 #define ADDITIONAL_REGISTER_NAMES \
2990 { \
2991 { "$0", 0 + GP_REG_FIRST }, \
2992 { "$1", 1 + GP_REG_FIRST }, \
2993 { "$2", 2 + GP_REG_FIRST }, \
2994 { "$3", 3 + GP_REG_FIRST }, \
2995 { "$4", 4 + GP_REG_FIRST }, \
2996 { "$5", 5 + GP_REG_FIRST }, \
2997 { "$6", 6 + GP_REG_FIRST }, \
2998 { "$7", 7 + GP_REG_FIRST }, \
2999 { "$8", 8 + GP_REG_FIRST }, \
3000 { "$9", 9 + GP_REG_FIRST }, \
3001 { "$10", 10 + GP_REG_FIRST }, \
3002 { "$11", 11 + GP_REG_FIRST }, \
3003 { "$12", 12 + GP_REG_FIRST }, \
3004 { "$13", 13 + GP_REG_FIRST }, \
3005 { "$14", 14 + GP_REG_FIRST }, \
3006 { "$15", 15 + GP_REG_FIRST }, \
3007 { "$16", 16 + GP_REG_FIRST }, \
3008 { "$17", 17 + GP_REG_FIRST }, \
3009 { "$18", 18 + GP_REG_FIRST }, \
3010 { "$19", 19 + GP_REG_FIRST }, \
3011 { "$20", 20 + GP_REG_FIRST }, \
3012 { "$21", 21 + GP_REG_FIRST }, \
3013 { "$22", 22 + GP_REG_FIRST }, \
3014 { "$23", 23 + GP_REG_FIRST }, \
3015 { "$24", 24 + GP_REG_FIRST }, \
3016 { "$25", 25 + GP_REG_FIRST }, \
3017 { "$26", 26 + GP_REG_FIRST }, \
3018 { "$27", 27 + GP_REG_FIRST }, \
3019 { "$28", 28 + GP_REG_FIRST }, \
3020 { "$29", 29 + GP_REG_FIRST }, \
3021 { "$30", 30 + GP_REG_FIRST }, \
3022 { "$31", 31 + GP_REG_FIRST }, \
3023 { "$sp", 29 + GP_REG_FIRST }, \
3024 { "$fp", 30 + GP_REG_FIRST }, \
3025 { "at", 1 + GP_REG_FIRST }, \
3026 { "v0", 2 + GP_REG_FIRST }, \
3027 { "v1", 3 + GP_REG_FIRST }, \
3028 { "a0", 4 + GP_REG_FIRST }, \
3029 { "a1", 5 + GP_REG_FIRST }, \
3030 { "a2", 6 + GP_REG_FIRST }, \
3031 { "a3", 7 + GP_REG_FIRST }, \
3032 { "t0", 8 + GP_REG_FIRST }, \
3033 { "t1", 9 + GP_REG_FIRST }, \
3034 { "t2", 10 + GP_REG_FIRST }, \
3035 { "t3", 11 + GP_REG_FIRST }, \
3036 { "t4", 12 + GP_REG_FIRST }, \
3037 { "t5", 13 + GP_REG_FIRST }, \
3038 { "t6", 14 + GP_REG_FIRST }, \
3039 { "t7", 15 + GP_REG_FIRST }, \
3040 { "s0", 16 + GP_REG_FIRST }, \
3041 { "s1", 17 + GP_REG_FIRST }, \
3042 { "s2", 18 + GP_REG_FIRST }, \
3043 { "s3", 19 + GP_REG_FIRST }, \
3044 { "s4", 20 + GP_REG_FIRST }, \
3045 { "s5", 21 + GP_REG_FIRST }, \
3046 { "s6", 22 + GP_REG_FIRST }, \
3047 { "s7", 23 + GP_REG_FIRST }, \
3048 { "t8", 24 + GP_REG_FIRST }, \
3049 { "t9", 25 + GP_REG_FIRST }, \
3050 { "k0", 26 + GP_REG_FIRST }, \
3051 { "k1", 27 + GP_REG_FIRST }, \
3052 { "gp", 28 + GP_REG_FIRST }, \
3053 { "sp", 29 + GP_REG_FIRST }, \
3054 { "fp", 30 + GP_REG_FIRST }, \
3055 { "ra", 31 + GP_REG_FIRST }, \
3056 { "$sp", 29 + GP_REG_FIRST }, \
3057 { "$fp", 30 + GP_REG_FIRST } \
3058 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3059 }
3060
3061 /* This is meant to be redefined in the host dependent files. It is a
3062 set of alternative names and regnums for mips coprocessors. */
3063
3064 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3065
3066 /* A C compound statement to output to stdio stream STREAM the
3067 assembler syntax for an instruction operand X. X is an RTL
3068 expression.
3069
3070 CODE is a value that can be used to specify one of several ways
3071 of printing the operand. It is used when identical operands
3072 must be printed differently depending on the context. CODE
3073 comes from the `%' specification that was used to request
3074 printing of the operand. If the specification was just `%DIGIT'
3075 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3076 is the ASCII code for LTR.
3077
3078 If X is a register, this macro should print the register's name.
3079 The names can be found in an array `reg_names' whose type is
3080 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3081
3082 When the machine description has a specification `%PUNCT' (a `%'
3083 followed by a punctuation character), this macro is called with
3084 a null pointer for X and the punctuation character for CODE.
3085
3086 See mips.c for the MIPS specific codes. */
3087
3088 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3089
3090 /* A C expression which evaluates to true if CODE is a valid
3091 punctuation character for use in the `PRINT_OPERAND' macro. If
3092 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3093 punctuation characters (except for the standard one, `%') are
3094 used in this way. */
3095
3096 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3097
3098 /* A C compound statement to output to stdio stream STREAM the
3099 assembler syntax for an instruction operand that is a memory
3100 reference whose address is ADDR. ADDR is an RTL expression. */
3101
3102 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3103
3104
3105 /* A C statement, to be executed after all slot-filler instructions
3106 have been output. If necessary, call `dbr_sequence_length' to
3107 determine the number of slots filled in a sequence (zero if not
3108 currently outputting a sequence), to decide how many no-ops to
3109 output, or whatever.
3110
3111 Don't define this macro if it has nothing to do, but it is
3112 helpful in reading assembly output if the extent of the delay
3113 sequence is made explicit (e.g. with white space).
3114
3115 Note that output routines for instructions with delay slots must
3116 be prepared to deal with not being output as part of a sequence
3117 (i.e. when the scheduling pass is not run, or when no slot
3118 fillers could be found.) The variable `final_sequence' is null
3119 when not processing a sequence, otherwise it contains the
3120 `sequence' rtx being output. */
3121
3122 #define DBR_OUTPUT_SEQEND(STREAM) \
3123 do \
3124 { \
3125 if (set_nomacro > 0 && --set_nomacro == 0) \
3126 fputs ("\t.set\tmacro\n", STREAM); \
3127 \
3128 if (set_noreorder > 0 && --set_noreorder == 0) \
3129 fputs ("\t.set\treorder\n", STREAM); \
3130 \
3131 fputs ("\n", STREAM); \
3132 } \
3133 while (0)
3134
3135
3136 /* How to tell the debugger about changes of source files. */
3137
3138 #ifndef SET_FILE_NUMBER
3139 #define SET_FILE_NUMBER() ++num_source_filenames
3140 #endif
3141
3142 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3143 mips_output_filename (STREAM, NAME)
3144
3145 /* This is defined so that it can be overridden in iris6.h. */
3146 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3147 do \
3148 { \
3149 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3150 output_quoted_string (STREAM, NAME); \
3151 fputs ("\n", STREAM); \
3152 } \
3153 while (0)
3154
3155 /* This is how to output a note the debugger telling it the line number
3156 to which the following sequence of instructions corresponds.
3157 Silicon graphics puts a label after each .loc. */
3158
3159 #ifndef LABEL_AFTER_LOC
3160 #define LABEL_AFTER_LOC(STREAM)
3161 #endif
3162
3163 #ifndef ASM_OUTPUT_SOURCE_LINE
3164 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3165 mips_output_lineno (STREAM, LINE)
3166 #endif
3167
3168 /* The MIPS implementation uses some labels for its own purpose. The
3169 following lists what labels are created, and are all formed by the
3170 pattern $L[a-z].*. The machine independent portion of GCC creates
3171 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3172
3173 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3174 $Lb[0-9]+ Begin blocks for MIPS debug support
3175 $Lc[0-9]+ Label for use in s<xx> operation.
3176 $Le[0-9]+ End blocks for MIPS debug support */
3177
3178 #undef ASM_DECLARE_OBJECT_NAME
3179 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3180 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3181
3182 /* Globalizing directive for a label. */
3183 #define GLOBAL_ASM_OP "\t.globl\t"
3184
3185 /* This says how to define a global common symbol. */
3186
3187 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
3188
3189 /* This says how to define a local common symbol (ie, not visible to
3190 linker). */
3191
3192 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
3193 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
3194 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
3195 #endif
3196
3197 /* This says how to output an external. It would be possible not to
3198 output anything and let undefined symbol become external. However
3199 the assembler uses length information on externals to allocate in
3200 data/sdata bss/sbss, thereby saving exec time. */
3201
3202 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3203 mips_output_external(STREAM,DECL,NAME)
3204
3205 /* This is how to declare a function name. The actual work of
3206 emitting the label is moved to function_prologue, so that we can
3207 get the line number correctly emitted before the .ent directive,
3208 and after any .file directives. Define as empty so that the function
3209 is not declared before the .ent directive elsewhere. */
3210
3211 #undef ASM_DECLARE_FUNCTION_NAME
3212 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3213
3214 #ifndef FUNCTION_NAME_ALREADY_DECLARED
3215 #define FUNCTION_NAME_ALREADY_DECLARED 0
3216 #endif
3217
3218 /* This is how to store into the string LABEL
3219 the symbol_ref name of an internal numbered label where
3220 PREFIX is the class of label and NUM is the number within the class.
3221 This is suitable for output with `assemble_name'. */
3222
3223 #undef ASM_GENERATE_INTERNAL_LABEL
3224 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3225 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3226
3227 /* This is how to output an element of a case-vector that is absolute. */
3228
3229 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3230 fprintf (STREAM, "\t%s\t%sL%d\n", \
3231 ptr_mode == DImode ? ".dword" : ".word", \
3232 LOCAL_LABEL_PREFIX, \
3233 VALUE)
3234
3235 /* This is how to output an element of a case-vector. We can make the
3236 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
3237 is supported. */
3238
3239 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3240 do { \
3241 if (TARGET_MIPS16) \
3242 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3243 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3244 else if (TARGET_GPWORD) \
3245 fprintf (STREAM, "\t%s\t%sL%d\n", \
3246 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3247 LOCAL_LABEL_PREFIX, VALUE); \
3248 else \
3249 fprintf (STREAM, "\t%s\t%sL%d\n", \
3250 ptr_mode == DImode ? ".dword" : ".word", \
3251 LOCAL_LABEL_PREFIX, VALUE); \
3252 } while (0)
3253
3254 /* When generating mips16 code we want to put the jump table in the .text
3255 section. In all other cases, we want to put the jump table in the .rdata
3256 section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
3257 it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
3258 to the .text section if appropriate. */
3259 #undef ASM_OUTPUT_CASE_LABEL
3260 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3261 do { \
3262 if (TARGET_MIPS16) \
3263 function_section (current_function_decl); \
3264 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3265 } while (0)
3266
3267 /* This is how to output an assembler line
3268 that says to advance the location counter
3269 to a multiple of 2**LOG bytes. */
3270
3271 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3272 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3273
3274 /* This is how to output an assembler line to advance the location
3275 counter by SIZE bytes. */
3276
3277 #undef ASM_OUTPUT_SKIP
3278 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3279 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3280
3281 /* This is how to output a string. */
3282 #undef ASM_OUTPUT_ASCII
3283 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3284 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3285
3286 /* Output #ident as a in the read-only data section. */
3287 #undef ASM_OUTPUT_IDENT
3288 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3289 { \
3290 const char *p = STRING; \
3291 int size = strlen (p) + 1; \
3292 readonly_data_section (); \
3293 assemble_string (p, size); \
3294 }
3295 \f
3296 /* Default to -G 8 */
3297 #ifndef MIPS_DEFAULT_GVALUE
3298 #define MIPS_DEFAULT_GVALUE 8
3299 #endif
3300
3301 /* Define the strings to put out for each section in the object file. */
3302 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3303 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3304 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3305
3306 #undef READONLY_DATA_SECTION_ASM_OP
3307 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3308
3309 /* Given a decl node or constant node, choose the section to output it in
3310 and select that section. */
3311
3312 #undef TARGET_ASM_SELECT_SECTION
3313 #define TARGET_ASM_SELECT_SECTION mips_select_section
3314 \f
3315 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3316 do \
3317 { \
3318 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3319 TARGET_64BIT ? "dsubu" : "subu", \
3320 reg_names[STACK_POINTER_REGNUM], \
3321 reg_names[STACK_POINTER_REGNUM], \
3322 TARGET_64BIT ? "sd" : "sw", \
3323 reg_names[REGNO], \
3324 reg_names[STACK_POINTER_REGNUM]); \
3325 } \
3326 while (0)
3327
3328 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3329 do \
3330 { \
3331 if (! set_noreorder) \
3332 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3333 \
3334 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3335 TARGET_64BIT ? "ld" : "lw", \
3336 reg_names[REGNO], \
3337 reg_names[STACK_POINTER_REGNUM], \
3338 TARGET_64BIT ? "daddu" : "addu", \
3339 reg_names[STACK_POINTER_REGNUM], \
3340 reg_names[STACK_POINTER_REGNUM]); \
3341 \
3342 if (! set_noreorder) \
3343 fprintf (STREAM, "\t.set\treorder\n"); \
3344 } \
3345 while (0)
3346
3347 /* How to start an assembler comment.
3348 The leading space is important (the mips native assembler requires it). */
3349 #ifndef ASM_COMMENT_START
3350 #define ASM_COMMENT_START " #"
3351 #endif
3352 \f
3353 /* Default definitions for size_t and ptrdiff_t. We must override the
3354 definitions from ../svr4.h on mips-*-linux-gnu. */
3355
3356 #undef SIZE_TYPE
3357 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3358
3359 #undef PTRDIFF_TYPE
3360 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3361
3362 /* See mips_expand_prologue's use of loadgp for when this should be
3363 true. */
3364
3365 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
3366 \f
3367 #ifndef __mips16
3368 /* Since the bits of the _init and _fini function is spread across
3369 many object files, each potentially with its own GP, we must assume
3370 we need to load our GP. We don't preserve $gp or $ra, since each
3371 init/fini chunk is supposed to initialize $gp, and crti/crtn
3372 already take care of preserving $ra and, when appropriate, $gp. */
3373 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3374 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3375 asm (SECTION_OP "\n\
3376 .set noreorder\n\
3377 bal 1f\n\
3378 nop\n\
3379 1: .cpload $31\n\
3380 .set reorder\n\
3381 jal " USER_LABEL_PREFIX #FUNC "\n\
3382 " TEXT_SECTION_ASM_OP);
3383 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3384 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3385 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3386 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3387 asm (SECTION_OP "\n\
3388 .set noreorder\n\
3389 bal 1f\n\
3390 nop\n\
3391 1: .set reorder\n\
3392 .cpsetup $31, $2, 1b\n\
3393 jal " USER_LABEL_PREFIX #FUNC "\n\
3394 " TEXT_SECTION_ASM_OP);
3395 #endif
3396 #endif
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