| blob | 1062d26ab4cbf46764e80135461b1a8ee1f784a0 |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(FIRST_GPR_REGNO 0)
29 (STACK_POINTER_REGNUM 1)
30 (TOC_REGNUM 2)
31 (STATIC_CHAIN_REGNUM 11)
32 (HARD_FRAME_POINTER_REGNUM 31)
33 (LAST_GPR_REGNO 31)
34 (FIRST_FPR_REGNO 32)
35 (LAST_FPR_REGNO 63)
36 (LR_REGNO 65)
37 (CTR_REGNO 66)
38 (ARG_POINTER_REGNUM 67)
39 (CR0_REGNO 68)
40 (CR1_REGNO 69)
41 (CR2_REGNO 70)
42 (CR3_REGNO 71)
43 (CR4_REGNO 72)
44 (CR5_REGNO 73)
45 (CR6_REGNO 74)
46 (CR7_REGNO 75)
47 (MAX_CR_REGNO 75)
48 (CA_REGNO 76)
49 (FIRST_ALTIVEC_REGNO 77)
50 (LAST_ALTIVEC_REGNO 108)
51 (VRSAVE_REGNO 109)
52 (VSCR_REGNO 110)
53 (SPE_ACC_REGNO 111)
54 (SPEFSCR_REGNO 112)
55 (FRAME_POINTER_REGNUM 113)
56 (TFHAR_REGNO 114)
57 (TFIAR_REGNO 115)
58 (TEXASR_REGNO 116)
59 ])
61 ;;
62 ;; UNSPEC usage
63 ;;
65 (define_c_enum "unspec"
66 [UNSPEC_FRSP ; frsp for POWER machines
67 UNSPEC_PROBE_STACK ; probe stack memory reference
68 UNSPEC_TOCPTR ; address of a word pointing to the TOC
69 UNSPEC_TOC ; address of the TOC (more-or-less)
70 UNSPEC_MOVSI_GOT
71 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
72 UNSPEC_FCTIWZ
73 UNSPEC_FRIM
74 UNSPEC_FRIN
75 UNSPEC_FRIP
76 UNSPEC_FRIZ
77 UNSPEC_LD_MPIC ; load_macho_picbase
78 UNSPEC_RELD_MPIC ; re-load_macho_picbase
79 UNSPEC_MPIC_CORRECT ; macho_correct_pic
80 UNSPEC_TLSGD
81 UNSPEC_TLSLD
82 UNSPEC_MOVESI_FROM_CR
83 UNSPEC_MOVESI_TO_CR
84 UNSPEC_TLSDTPREL
85 UNSPEC_TLSDTPRELHA
86 UNSPEC_TLSDTPRELLO
87 UNSPEC_TLSGOTDTPREL
88 UNSPEC_TLSTPREL
89 UNSPEC_TLSTPRELHA
90 UNSPEC_TLSTPRELLO
91 UNSPEC_TLSGOTTPREL
92 UNSPEC_TLSTLS
93 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
94 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
95 UNSPEC_STFIWX
96 UNSPEC_POPCNTB
97 UNSPEC_FRES
98 UNSPEC_SP_SET
99 UNSPEC_SP_TEST
100 UNSPEC_SYNC
101 UNSPEC_LWSYNC
102 UNSPEC_SYNC_OP
103 UNSPEC_ATOMIC
104 UNSPEC_CMPXCHG
105 UNSPEC_XCHG
106 UNSPEC_AND
107 UNSPEC_DLMZB
108 UNSPEC_DLMZB_CR
109 UNSPEC_DLMZB_STRLEN
110 UNSPEC_RSQRT
111 UNSPEC_TOCREL
112 UNSPEC_MACHOPIC_OFFSET
113 UNSPEC_BPERM
114 UNSPEC_COPYSIGN
115 UNSPEC_PARITY
116 UNSPEC_FCTIW
117 UNSPEC_FCTID
118 UNSPEC_LFIWAX
119 UNSPEC_LFIWZX
120 UNSPEC_FCTIWUZ
121 UNSPEC_GRP_END_NOP
122 UNSPEC_P8V_FMRGOW
123 UNSPEC_P8V_MTVSRWZ
124 UNSPEC_P8V_RELOAD_FROM_GPR
125 UNSPEC_P8V_MTVSRD
126 UNSPEC_P8V_XXPERMDI
127 UNSPEC_P8V_RELOAD_FROM_VSX
128 ])
130 ;;
131 ;; UNSPEC_VOLATILE usage
132 ;;
134 (define_c_enum "unspecv"
135 [UNSPECV_BLOCK
136 UNSPECV_LL ; load-locked
137 UNSPECV_SC ; store-conditional
138 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
139 UNSPECV_EH_RR ; eh_reg_restore
140 UNSPECV_ISYNC ; isync instruction
141 UNSPECV_MFTB ; move from time base
142 UNSPECV_NLGR ; non-local goto receiver
143 UNSPECV_MFFS ; Move from FPSCR
144 UNSPECV_MTFSF ; Move to FPSCR Fields
145 ])
147 \f
148 ;; Define an insn type attribute. This is used in function unit delay
149 ;; computations.
150 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm"
151 (const_string "integer"))
153 ;; Define floating point instruction sub-types for use with Xfpu.md
154 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
156 ;; Length (in bytes).
157 ; '(pc)' in the following doesn't include the instruction itself; it is
158 ; calculated as if the instruction had zero size.
159 (define_attr "length" ""
160 (if_then_else (eq_attr "type" "branch")
161 (if_then_else (and (ge (minus (match_dup 0) (pc))
162 (const_int -32768))
163 (lt (minus (match_dup 0) (pc))
164 (const_int 32764)))
165 (const_int 4)
166 (const_int 8))
167 (const_int 4)))
169 ;; Processor type -- this attribute must exactly match the processor_type
170 ;; enumeration in rs6000-opts.h.
171 (define_attr "cpu"
172 "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,
173 ppc750,ppc7400,ppc7450,
174 ppc403,ppc405,ppc440,ppc476,
175 ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
176 power4,power5,power6,power7,power8,
177 rs64a,mpccore,cell,ppca2,titan"
178 (const (symbol_ref "rs6000_cpu_attr")))
181 ;; If this instruction is microcoded on the CELL processor
182 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
183 (define_attr "cell_micro" "not,conditional,always"
184 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
185 (const_string "always")
186 (const_string "not")))
188 (automata_option "ndfa")
190 (include "rs64.md")
191 (include "mpc.md")
192 (include "40x.md")
193 (include "440.md")
194 (include "476.md")
195 (include "601.md")
196 (include "603.md")
197 (include "6xx.md")
198 (include "7xx.md")
199 (include "7450.md")
200 (include "8540.md")
201 (include "e300c2c3.md")
202 (include "e500mc.md")
203 (include "e500mc64.md")
204 (include "e5500.md")
205 (include "e6500.md")
206 (include "power4.md")
207 (include "power5.md")
208 (include "power6.md")
209 (include "power7.md")
210 (include "power8.md")
211 (include "cell.md")
212 (include "xfpu.md")
213 (include "a2.md")
214 (include "titan.md")
216 (include "predicates.md")
217 (include "constraints.md")
219 (include "darwin.md")
221 \f
222 ;; Mode iterators
224 ; This mode iterator allows :GPR to be used to indicate the allowable size
225 ; of whole values in GPRs.
226 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
228 ; Any supported integer mode.
229 (define_mode_iterator INT [QI HI SI DI TI PTI])
231 ; Any supported integer mode that fits in one register.
232 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
234 ; extend modes for DImode
235 (define_mode_iterator QHSI [QI HI SI])
237 ; QImode or HImode for small atomic ops
238 (define_mode_iterator QHI [QI HI])
240 ; HImode or SImode for sign extended fusion ops
241 (define_mode_iterator HSI [HI SI])
243 ; SImode or DImode, even if DImode doesn't fit in GPRs.
244 (define_mode_iterator SDI [SI DI])
246 ; The size of a pointer. Also, the size of the value that a record-condition
247 ; (one with a '.') will compare; and the size used for arithmetic carries.
248 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
250 ; Iterator to add PTImode along with TImode (TImode can go in VSX registers,
251 ; PTImode is GPR only)
252 (define_mode_iterator TI2 [TI PTI])
254 ; Any hardware-supported floating-point mode
255 (define_mode_iterator FP [
256 (SF "TARGET_HARD_FLOAT
257 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
258 (DF "TARGET_HARD_FLOAT
259 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
260 (TF "!TARGET_IEEEQUAD
261 && TARGET_HARD_FLOAT
262 && (TARGET_FPRS || TARGET_E500_DOUBLE)
263 && TARGET_LONG_DOUBLE_128")
264 (DD "TARGET_DFP")
265 (TD "TARGET_DFP")])
267 ; Any fma capable floating-point mode.
268 (define_mode_iterator FMA_F [
269 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
270 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
271 || VECTOR_UNIT_VSX_P (DFmode)")
272 (V2SF "TARGET_PAIRED_FLOAT")
273 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
274 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
275 ])
277 ; Floating point move iterators to combine binary and decimal moves
278 (define_mode_iterator FMOVE32 [SF SD])
279 (define_mode_iterator FMOVE64 [DF DD])
280 (define_mode_iterator FMOVE64X [DI DF DD])
281 (define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128")
282 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")])
284 ; Iterators for 128 bit types for direct move
285 (define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE")
286 (V16QI "")
287 (V8HI "")
288 (V4SI "")
289 (V4SF "")
290 (V2DI "")
291 (V2DF "")])
293 ; Whether a floating point move is ok, don't allow SD without hardware FP
294 (define_mode_attr fmove_ok [(SF "")
295 (DF "")
296 (SD "TARGET_HARD_FLOAT && TARGET_FPRS")
297 (DD "")])
299 ; Convert REAL_VALUE to the appropriate bits
300 (define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE")
301 (DF "REAL_VALUE_TO_TARGET_DOUBLE")
302 (SD "REAL_VALUE_TO_TARGET_DECIMAL32")
303 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")])
305 ; Definitions for load to 32-bit fpr register
306 (define_mode_attr f32_lr [(SF "f") (SD "wz")])
307 (define_mode_attr f32_lm [(SF "m") (SD "Z")])
308 (define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")])
309 (define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")])
311 ; Definitions for store from 32-bit fpr register
312 (define_mode_attr f32_sr [(SF "f") (SD "wx")])
313 (define_mode_attr f32_sm [(SF "m") (SD "Z")])
314 (define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")])
315 (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")])
317 ; Definitions for 32-bit fpr direct move
318 (define_mode_attr f32_dm [(SF "wn") (SD "wm")])
320 ; These modes do not fit in integer registers in 32-bit mode.
321 ; but on e500v2, the gpr are 64 bit registers
322 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
324 ; Iterator for reciprocal estimate instructions
325 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
327 ; Iterator for just SF/DF
328 (define_mode_iterator SFDF [SF DF])
330 ; SF/DF suffix for traditional floating instructions
331 (define_mode_attr Ftrad [(SF "s") (DF "")])
333 ; SF/DF suffix for VSX instructions
334 (define_mode_attr Fvsx [(SF "sp") (DF "dp")])
336 ; SF/DF constraint for arithmetic on traditional floating point registers
337 (define_mode_attr Ff [(SF "f") (DF "d")])
339 ; SF/DF constraint for arithmetic on VSX registers
340 (define_mode_attr Fv [(SF "wy") (DF "ws")])
342 ; s/d suffix for things like fp_addsub_s/fp_addsub_d
343 (define_mode_attr Fs [(SF "s") (DF "d")])
345 ; FRE/FRES support
346 (define_mode_attr Ffre [(SF "fres") (DF "fre")])
347 (define_mode_attr FFRE [(SF "FRES") (DF "FRE")])
349 ; Conditional returns.
350 (define_code_iterator any_return [return simple_return])
351 (define_code_attr return_pred [(return "direct_return ()")
352 (simple_return "1")])
353 (define_code_attr return_str [(return "") (simple_return "simple_")])
355 ; Various instructions that come in SI and DI forms.
356 ; A generic w/d attribute, for things like cmpw/cmpd.
357 (define_mode_attr wd [(QI "b")
358 (HI "h")
359 (SI "w")
360 (DI "d")
361 (V16QI "b")
362 (V8HI "h")
363 (V4SI "w")
364 (V2DI "d")])
366 ; DImode bits
367 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
369 ;; ISEL/ISEL64 target selection
370 (define_mode_attr sel [(SI "") (DI "64")])
372 ;; Suffix for reload patterns
373 (define_mode_attr ptrsize [(SI "32bit")
374 (DI "64bit")])
376 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
377 (DI "TARGET_64BIT")])
379 (define_mode_attr mptrsize [(SI "si")
380 (DI "di")])
382 (define_mode_attr ptrload [(SI "lwz")
383 (DI "ld")])
385 (define_mode_attr ptrm [(SI "m")
386 (DI "Y")])
388 (define_mode_attr rreg [(SF "f")
389 (DF "ws")
390 (TF "f")
391 (TD "f")
392 (V4SF "wf")
393 (V2DF "wd")])
395 (define_mode_attr rreg2 [(SF "f")
396 (DF "d")])
398 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
399 (DF "TARGET_FCFID")])
401 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
402 (DF "TARGET_E500_DOUBLE")])
404 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
405 (DF "TARGET_DOUBLE_FLOAT")])
407 ;; Mode iterator for logical operations on 128-bit types
408 (define_mode_iterator BOOL_128 [TI
409 PTI
410 (V16QI "TARGET_ALTIVEC")
411 (V8HI "TARGET_ALTIVEC")
412 (V4SI "TARGET_ALTIVEC")
413 (V4SF "TARGET_ALTIVEC")
414 (V2DI "TARGET_ALTIVEC")
415 (V2DF "TARGET_ALTIVEC")])
417 ;; For the GPRs we use 3 constraints for register outputs, two that are the
418 ;; same as the output register, and a third where the output register is an
419 ;; early clobber, so we don't have to deal with register overlaps. For the
420 ;; vector types, we prefer to use the vector registers. For TI mode, allow
421 ;; either.
423 ;; Mode attribute for boolean operation register constraints for output
424 (define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v")
425 (PTI "&r,r,r")
426 (V16QI "wa,v,&?r,?r,?r")
427 (V8HI "wa,v,&?r,?r,?r")
428 (V4SI "wa,v,&?r,?r,?r")
429 (V4SF "wa,v,&?r,?r,?r")
430 (V2DI "wa,v,&?r,?r,?r")
431 (V2DF "wa,v,&?r,?r,?r")])
433 ;; Mode attribute for boolean operation register constraints for operand1
434 (define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v")
435 (PTI "r,0,r")
436 (V16QI "wa,v,r,0,r")
437 (V8HI "wa,v,r,0,r")
438 (V4SI "wa,v,r,0,r")
439 (V4SF "wa,v,r,0,r")
440 (V2DI "wa,v,r,0,r")
441 (V2DF "wa,v,r,0,r")])
443 ;; Mode attribute for boolean operation register constraints for operand2
444 (define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v")
445 (PTI "r,r,0")
446 (V16QI "wa,v,r,r,0")
447 (V8HI "wa,v,r,r,0")
448 (V4SI "wa,v,r,r,0")
449 (V4SF "wa,v,r,r,0")
450 (V2DI "wa,v,r,r,0")
451 (V2DF "wa,v,r,r,0")])
453 ;; Mode attribute for boolean operation register constraints for operand1
454 ;; for one_cmpl. To simplify things, we repeat the constraint where 0
455 ;; is used for operand1 or operand2
456 (define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v")
457 (PTI "r,0,0")
458 (V16QI "wa,v,r,0,0")
459 (V8HI "wa,v,r,0,0")
460 (V4SI "wa,v,r,0,0")
461 (V4SF "wa,v,r,0,0")
462 (V2DI "wa,v,r,0,0")
463 (V2DF "wa,v,r,0,0")])
465 ;; Mode attribute for the clobber of CC0 for AND expansion.
466 ;; For the 128-bit types, we never do AND immediate, but we need to
467 ;; get the correct number of X's for the number of operands.
468 (define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X")
469 (PTI "X,X,X")
470 (V16QI "X,X,X,X,X")
471 (V8HI "X,X,X,X,X")
472 (V4SI "X,X,X,X,X")
473 (V4SF "X,X,X,X,X")
474 (V2DI "X,X,X,X,X")
475 (V2DF "X,X,X,X,X")])
477 \f
478 ;; Start with fixed-point load and store insns. Here we put only the more
479 ;; complex forms. Basic data transfer is done later.
481 (define_expand "zero_extend<mode>di2"
482 [(set (match_operand:DI 0 "gpc_reg_operand" "")
483 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
484 "TARGET_POWERPC64"
485 "")
487 (define_insn "*zero_extend<mode>di2_internal1"
488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
489 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
490 "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)"
491 "@
492 l<wd>z%U1%X1 %0,%1
493 rldicl %0,%1,0,<dbits>"
494 [(set_attr_alternative "type"
495 [(if_then_else
496 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
497 (const_string "load_ux")
498 (if_then_else
499 (match_test "update_address_mem (operands[1], VOIDmode)")
500 (const_string "load_u")
501 (const_string "load")))
502 (const_string "*")])])
504 (define_insn "*zero_extend<mode>di2_internal2"
505 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
506 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
507 (const_int 0)))
508 (clobber (match_scratch:DI 2 "=r,r"))]
509 "TARGET_64BIT"
510 "@
511 rldicl. %2,%1,0,<dbits>
512 #"
513 [(set_attr "type" "compare")
514 (set_attr "length" "4,8")])
516 (define_split
517 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
518 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
519 (const_int 0)))
520 (clobber (match_scratch:DI 2 ""))]
521 "TARGET_POWERPC64 && reload_completed"
522 [(set (match_dup 2)
523 (zero_extend:DI (match_dup 1)))
524 (set (match_dup 0)
525 (compare:CC (match_dup 2)
526 (const_int 0)))]
527 "")
529 (define_insn "*zero_extend<mode>di2_internal3"
530 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
531 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
532 (const_int 0)))
533 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
534 (zero_extend:DI (match_dup 1)))]
535 "TARGET_64BIT"
536 "@
537 rldicl. %0,%1,0,<dbits>
538 #"
539 [(set_attr "type" "compare")
540 (set_attr "length" "4,8")])
542 (define_split
543 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
544 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
545 (const_int 0)))
546 (set (match_operand:DI 0 "gpc_reg_operand" "")
547 (zero_extend:DI (match_dup 1)))]
548 "TARGET_POWERPC64 && reload_completed"
549 [(set (match_dup 0)
550 (zero_extend:DI (match_dup 1)))
551 (set (match_dup 2)
552 (compare:CC (match_dup 0)
553 (const_int 0)))]
554 "")
556 (define_insn "*zero_extendsidi2_lfiwzx"
557 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu")
558 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))]
559 "TARGET_POWERPC64 && TARGET_LFIWZX"
560 "@
561 lwz%U1%X1 %0,%1
562 rldicl %0,%1,0,32
563 mtvsrwz %x0,%1
564 lfiwzx %0,%y1
565 lxsiwzx %x0,%y1"
566 [(set_attr_alternative "type"
567 [(if_then_else
568 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
569 (const_string "load_ux")
570 (if_then_else
571 (match_test "update_address_mem (operands[1], VOIDmode)")
572 (const_string "load_u")
573 (const_string "load")))
574 (const_string "*")
575 (const_string "mffgpr")
576 (const_string "fpload")
577 (const_string "fpload")])])
579 (define_insn "extendqidi2"
580 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
581 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
582 "TARGET_POWERPC64"
583 "extsb %0,%1"
584 [(set_attr "type" "exts")])
586 (define_insn ""
587 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
588 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
589 (const_int 0)))
590 (clobber (match_scratch:DI 2 "=r,r"))]
591 "TARGET_64BIT"
592 "@
593 extsb. %2,%1
594 #"
595 [(set_attr "type" "compare")
596 (set_attr "length" "4,8")])
598 (define_split
599 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
600 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
601 (const_int 0)))
602 (clobber (match_scratch:DI 2 ""))]
603 "TARGET_POWERPC64 && reload_completed"
604 [(set (match_dup 2)
605 (sign_extend:DI (match_dup 1)))
606 (set (match_dup 0)
607 (compare:CC (match_dup 2)
608 (const_int 0)))]
609 "")
611 (define_insn ""
612 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
613 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
614 (const_int 0)))
615 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
616 (sign_extend:DI (match_dup 1)))]
617 "TARGET_64BIT"
618 "@
619 extsb. %0,%1
620 #"
621 [(set_attr "type" "compare")
622 (set_attr "length" "4,8")])
624 (define_split
625 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
626 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
627 (const_int 0)))
628 (set (match_operand:DI 0 "gpc_reg_operand" "")
629 (sign_extend:DI (match_dup 1)))]
630 "TARGET_POWERPC64 && reload_completed"
631 [(set (match_dup 0)
632 (sign_extend:DI (match_dup 1)))
633 (set (match_dup 2)
634 (compare:CC (match_dup 0)
635 (const_int 0)))]
636 "")
638 (define_expand "extendhidi2"
639 [(set (match_operand:DI 0 "gpc_reg_operand" "")
640 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
641 "TARGET_POWERPC64"
642 "")
644 (define_insn ""
645 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
646 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
647 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
648 "@
649 lha%U1%X1 %0,%1
650 extsh %0,%1"
651 [(set_attr_alternative "type"
652 [(if_then_else
653 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
654 (const_string "load_ext_ux")
655 (if_then_else
656 (match_test "update_address_mem (operands[1], VOIDmode)")
657 (const_string "load_ext_u")
658 (const_string "load_ext")))
659 (const_string "exts")])])
661 (define_insn ""
662 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
663 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
664 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
665 "extsh %0,%1"
666 [(set_attr "type" "exts")])
668 (define_insn ""
669 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
670 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
671 (const_int 0)))
672 (clobber (match_scratch:DI 2 "=r,r"))]
673 "TARGET_64BIT"
674 "@
675 extsh. %2,%1
676 #"
677 [(set_attr "type" "compare")
678 (set_attr "length" "4,8")])
680 (define_split
681 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
682 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
683 (const_int 0)))
684 (clobber (match_scratch:DI 2 ""))]
685 "TARGET_POWERPC64 && reload_completed"
686 [(set (match_dup 2)
687 (sign_extend:DI (match_dup 1)))
688 (set (match_dup 0)
689 (compare:CC (match_dup 2)
690 (const_int 0)))]
691 "")
693 (define_insn ""
694 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
695 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
696 (const_int 0)))
697 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
698 (sign_extend:DI (match_dup 1)))]
699 "TARGET_64BIT"
700 "@
701 extsh. %0,%1
702 #"
703 [(set_attr "type" "compare")
704 (set_attr "length" "4,8")])
706 (define_split
707 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
708 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
709 (const_int 0)))
710 (set (match_operand:DI 0 "gpc_reg_operand" "")
711 (sign_extend:DI (match_dup 1)))]
712 "TARGET_POWERPC64 && reload_completed"
713 [(set (match_dup 0)
714 (sign_extend:DI (match_dup 1)))
715 (set (match_dup 2)
716 (compare:CC (match_dup 0)
717 (const_int 0)))]
718 "")
720 (define_expand "extendsidi2"
721 [(set (match_operand:DI 0 "gpc_reg_operand" "")
722 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
723 "TARGET_POWERPC64"
724 "")
726 (define_insn "*extendsidi2_lfiwax"
727 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu")
728 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))]
729 "TARGET_POWERPC64 && TARGET_LFIWAX"
730 "@
731 lwa%U1%X1 %0,%1
732 extsw %0,%1
733 mtvsrwa %x0,%1
734 lfiwax %0,%y1
735 lxsiwax %x0,%y1"
736 [(set_attr_alternative "type"
737 [(if_then_else
738 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
739 (const_string "load_ext_ux")
740 (if_then_else
741 (match_test "update_address_mem (operands[1], VOIDmode)")
742 (const_string "load_ext_u")
743 (const_string "load_ext")))
744 (const_string "exts")
745 (const_string "mffgpr")
746 (const_string "fpload")
747 (const_string "fpload")])])
749 (define_insn "*extendsidi2_nocell"
750 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
751 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
752 "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX"
753 "@
754 lwa%U1%X1 %0,%1
755 extsw %0,%1"
756 [(set_attr_alternative "type"
757 [(if_then_else
758 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
759 (const_string "load_ext_ux")
760 (if_then_else
761 (match_test "update_address_mem (operands[1], VOIDmode)")
762 (const_string "load_ext_u")
763 (const_string "load_ext")))
764 (const_string "exts")])])
766 (define_insn "*extendsidi2_nocell"
767 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
768 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
769 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
770 "extsw %0,%1"
771 [(set_attr "type" "exts")])
773 (define_insn ""
774 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
775 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
776 (const_int 0)))
777 (clobber (match_scratch:DI 2 "=r,r"))]
778 "TARGET_64BIT"
779 "@
780 extsw. %2,%1
781 #"
782 [(set_attr "type" "compare")
783 (set_attr "length" "4,8")])
785 (define_split
786 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
787 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
788 (const_int 0)))
789 (clobber (match_scratch:DI 2 ""))]
790 "TARGET_POWERPC64 && reload_completed"
791 [(set (match_dup 2)
792 (sign_extend:DI (match_dup 1)))
793 (set (match_dup 0)
794 (compare:CC (match_dup 2)
795 (const_int 0)))]
796 "")
798 (define_insn ""
799 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
800 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
801 (const_int 0)))
802 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
803 (sign_extend:DI (match_dup 1)))]
804 "TARGET_64BIT"
805 "@
806 extsw. %0,%1
807 #"
808 [(set_attr "type" "compare")
809 (set_attr "length" "4,8")])
811 (define_split
812 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
813 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
814 (const_int 0)))
815 (set (match_operand:DI 0 "gpc_reg_operand" "")
816 (sign_extend:DI (match_dup 1)))]
817 "TARGET_POWERPC64 && reload_completed"
818 [(set (match_dup 0)
819 (sign_extend:DI (match_dup 1)))
820 (set (match_dup 2)
821 (compare:CC (match_dup 0)
822 (const_int 0)))]
823 "")
825 (define_expand "zero_extendqisi2"
826 [(set (match_operand:SI 0 "gpc_reg_operand" "")
827 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
828 ""
829 "")
831 (define_insn ""
832 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
833 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
834 ""
835 "@
836 lbz%U1%X1 %0,%1
837 rlwinm %0,%1,0,0xff"
838 [(set_attr_alternative "type"
839 [(if_then_else
840 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
841 (const_string "load_ux")
842 (if_then_else
843 (match_test "update_address_mem (operands[1], VOIDmode)")
844 (const_string "load_u")
845 (const_string "load")))
846 (const_string "*")])])
848 (define_insn ""
849 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
850 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
851 (const_int 0)))
852 (clobber (match_scratch:SI 2 "=r,r"))]
853 ""
854 "@
855 andi. %2,%1,0xff
856 #"
857 [(set_attr "type" "fast_compare,compare")
858 (set_attr "length" "4,8")])
860 (define_split
861 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
862 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
863 (const_int 0)))
864 (clobber (match_scratch:SI 2 ""))]
865 "reload_completed"
866 [(set (match_dup 2)
867 (zero_extend:SI (match_dup 1)))
868 (set (match_dup 0)
869 (compare:CC (match_dup 2)
870 (const_int 0)))]
871 "")
873 (define_insn ""
874 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
875 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
876 (const_int 0)))
877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
878 (zero_extend:SI (match_dup 1)))]
879 ""
880 "@
881 andi. %0,%1,0xff
882 #"
883 [(set_attr "type" "fast_compare,compare")
884 (set_attr "length" "4,8")])
886 (define_split
887 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
888 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
889 (const_int 0)))
890 (set (match_operand:SI 0 "gpc_reg_operand" "")
891 (zero_extend:SI (match_dup 1)))]
892 "reload_completed"
893 [(set (match_dup 0)
894 (zero_extend:SI (match_dup 1)))
895 (set (match_dup 2)
896 (compare:CC (match_dup 0)
897 (const_int 0)))]
898 "")
900 (define_insn "extendqisi2"
901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
902 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
903 ""
904 "extsb %0,%1"
905 [(set_attr "type" "exts")])
907 (define_insn ""
908 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
909 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
910 (const_int 0)))
911 (clobber (match_scratch:SI 2 "=r,r"))]
912 ""
913 "@
914 extsb. %2,%1
915 #"
916 [(set_attr "type" "compare")
917 (set_attr "length" "4,8")])
919 (define_split
920 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
921 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
922 (const_int 0)))
923 (clobber (match_scratch:SI 2 ""))]
924 "reload_completed"
925 [(set (match_dup 2)
926 (sign_extend:SI (match_dup 1)))
927 (set (match_dup 0)
928 (compare:CC (match_dup 2)
929 (const_int 0)))]
930 "")
932 (define_insn ""
933 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
934 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
935 (const_int 0)))
936 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
937 (sign_extend:SI (match_dup 1)))]
938 ""
939 "@
940 extsb. %0,%1
941 #"
942 [(set_attr "type" "compare")
943 (set_attr "length" "4,8")])
945 (define_split
946 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
947 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
948 (const_int 0)))
949 (set (match_operand:SI 0 "gpc_reg_operand" "")
950 (sign_extend:SI (match_dup 1)))]
951 "reload_completed"
952 [(set (match_dup 0)
953 (sign_extend:SI (match_dup 1)))
954 (set (match_dup 2)
955 (compare:CC (match_dup 0)
956 (const_int 0)))]
957 "")
959 (define_insn ""
960 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
961 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
962 ""
963 "@
964 lbz%U1%X1 %0,%1
965 rlwinm %0,%1,0,0xff"
966 [(set_attr_alternative "type"
967 [(if_then_else
968 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
969 (const_string "load_ux")
970 (if_then_else
971 (match_test "update_address_mem (operands[1], VOIDmode)")
972 (const_string "load_u")
973 (const_string "load")))
974 (const_string "*")])])
976 (define_insn ""
977 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
978 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
979 (const_int 0)))
980 (clobber (match_scratch:HI 2 "=r,r"))]
981 ""
982 "@
983 andi. %2,%1,0xff
984 #"
985 [(set_attr "type" "fast_compare,compare")
986 (set_attr "length" "4,8")])
988 (define_split
989 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
990 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
991 (const_int 0)))
992 (clobber (match_scratch:HI 2 ""))]
993 "reload_completed"
994 [(set (match_dup 2)
995 (zero_extend:HI (match_dup 1)))
996 (set (match_dup 0)
997 (compare:CC (match_dup 2)
998 (const_int 0)))]
999 "")
1001 (define_insn ""
1002 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1003 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1004 (const_int 0)))
1005 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1006 (zero_extend:HI (match_dup 1)))]
1007 ""
1008 "@
1009 andi. %0,%1,0xff
1010 #"
1011 [(set_attr "type" "fast_compare,compare")
1012 (set_attr "length" "4,8")])
1014 (define_split
1015 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1016 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1017 (const_int 0)))
1018 (set (match_operand:HI 0 "gpc_reg_operand" "")
1019 (zero_extend:HI (match_dup 1)))]
1020 "reload_completed"
1021 [(set (match_dup 0)
1022 (zero_extend:HI (match_dup 1)))
1023 (set (match_dup 2)
1024 (compare:CC (match_dup 0)
1025 (const_int 0)))]
1026 "")
1028 (define_insn "extendqihi2"
1029 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1030 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1031 ""
1032 "extsb %0,%1"
1033 [(set_attr "type" "exts")])
1035 (define_insn ""
1036 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1037 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1038 (const_int 0)))
1039 (clobber (match_scratch:HI 2 "=r,r"))]
1040 ""
1041 "@
1042 extsb. %2,%1
1043 #"
1044 [(set_attr "type" "compare")
1045 (set_attr "length" "4,8")])
1047 (define_split
1048 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1049 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1050 (const_int 0)))
1051 (clobber (match_scratch:HI 2 ""))]
1052 "reload_completed"
1053 [(set (match_dup 2)
1054 (sign_extend:HI (match_dup 1)))
1055 (set (match_dup 0)
1056 (compare:CC (match_dup 2)
1057 (const_int 0)))]
1058 "")
1060 (define_insn ""
1061 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1062 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1063 (const_int 0)))
1064 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1065 (sign_extend:HI (match_dup 1)))]
1066 ""
1067 "@
1068 extsb. %0,%1
1069 #"
1070 [(set_attr "type" "compare")
1071 (set_attr "length" "4,8")])
1073 (define_split
1074 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1075 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1076 (const_int 0)))
1077 (set (match_operand:HI 0 "gpc_reg_operand" "")
1078 (sign_extend:HI (match_dup 1)))]
1079 "reload_completed"
1080 [(set (match_dup 0)
1081 (sign_extend:HI (match_dup 1)))
1082 (set (match_dup 2)
1083 (compare:CC (match_dup 0)
1084 (const_int 0)))]
1085 "")
1087 (define_expand "zero_extendhisi2"
1088 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1089 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1090 ""
1091 "")
1093 (define_insn ""
1094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1095 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1096 ""
1097 "@
1098 lhz%U1%X1 %0,%1
1099 rlwinm %0,%1,0,0xffff"
1100 [(set_attr_alternative "type"
1101 [(if_then_else
1102 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1103 (const_string "load_ux")
1104 (if_then_else
1105 (match_test "update_address_mem (operands[1], VOIDmode)")
1106 (const_string "load_u")
1107 (const_string "load")))
1108 (const_string "*")])])
1110 (define_insn ""
1111 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1112 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1113 (const_int 0)))
1114 (clobber (match_scratch:SI 2 "=r,r"))]
1115 ""
1116 "@
1117 andi. %2,%1,0xffff
1118 #"
1119 [(set_attr "type" "fast_compare,compare")
1120 (set_attr "length" "4,8")])
1122 (define_split
1123 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1124 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1125 (const_int 0)))
1126 (clobber (match_scratch:SI 2 ""))]
1127 "reload_completed"
1128 [(set (match_dup 2)
1129 (zero_extend:SI (match_dup 1)))
1130 (set (match_dup 0)
1131 (compare:CC (match_dup 2)
1132 (const_int 0)))]
1133 "")
1135 (define_insn ""
1136 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1137 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1138 (const_int 0)))
1139 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1140 (zero_extend:SI (match_dup 1)))]
1141 ""
1142 "@
1143 andi. %0,%1,0xffff
1144 #"
1145 [(set_attr "type" "fast_compare,compare")
1146 (set_attr "length" "4,8")])
1148 (define_split
1149 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1150 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1151 (const_int 0)))
1152 (set (match_operand:SI 0 "gpc_reg_operand" "")
1153 (zero_extend:SI (match_dup 1)))]
1154 "reload_completed"
1155 [(set (match_dup 0)
1156 (zero_extend:SI (match_dup 1)))
1157 (set (match_dup 2)
1158 (compare:CC (match_dup 0)
1159 (const_int 0)))]
1160 "")
1162 (define_expand "extendhisi2"
1163 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1164 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1165 ""
1166 "")
1168 (define_insn ""
1169 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1170 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1171 "rs6000_gen_cell_microcode"
1172 "@
1173 lha%U1%X1 %0,%1
1174 extsh %0,%1"
1175 [(set_attr_alternative "type"
1176 [(if_then_else
1177 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
1178 (const_string "load_ext_ux")
1179 (if_then_else
1180 (match_test "update_address_mem (operands[1], VOIDmode)")
1181 (const_string "load_ext_u")
1182 (const_string "load_ext")))
1183 (const_string "exts")])])
1185 (define_insn ""
1186 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1187 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
1188 "!rs6000_gen_cell_microcode"
1189 "extsh %0,%1"
1190 [(set_attr "type" "exts")])
1192 (define_insn ""
1193 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1194 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1195 (const_int 0)))
1196 (clobber (match_scratch:SI 2 "=r,r"))]
1197 ""
1198 "@
1199 extsh. %2,%1
1200 #"
1201 [(set_attr "type" "compare")
1202 (set_attr "length" "4,8")])
1204 (define_split
1205 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1206 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1207 (const_int 0)))
1208 (clobber (match_scratch:SI 2 ""))]
1209 "reload_completed"
1210 [(set (match_dup 2)
1211 (sign_extend:SI (match_dup 1)))
1212 (set (match_dup 0)
1213 (compare:CC (match_dup 2)
1214 (const_int 0)))]
1215 "")
1217 (define_insn ""
1218 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1219 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1220 (const_int 0)))
1221 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1222 (sign_extend:SI (match_dup 1)))]
1223 ""
1224 "@
1225 extsh. %0,%1
1226 #"
1227 [(set_attr "type" "compare")
1228 (set_attr "length" "4,8")])
1230 (define_split
1231 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1232 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1233 (const_int 0)))
1234 (set (match_operand:SI 0 "gpc_reg_operand" "")
1235 (sign_extend:SI (match_dup 1)))]
1236 "reload_completed"
1237 [(set (match_dup 0)
1238 (sign_extend:SI (match_dup 1)))
1239 (set (match_dup 2)
1240 (compare:CC (match_dup 0)
1241 (const_int 0)))]
1242 "")
1243 \f
1244 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1246 (define_insn "*macchwc"
1247 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1248 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1249 (match_operand:SI 2 "gpc_reg_operand" "r")
1250 (const_int 16))
1251 (sign_extend:SI
1252 (match_operand:HI 1 "gpc_reg_operand" "r")))
1253 (match_operand:SI 4 "gpc_reg_operand" "0"))
1254 (const_int 0)))
1255 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (plus:SI (mult:SI (ashiftrt:SI
1257 (match_dup 2)
1258 (const_int 16))
1259 (sign_extend:SI
1260 (match_dup 1)))
1261 (match_dup 4)))]
1262 "TARGET_MULHW"
1263 "macchw. %0,%1,%2"
1264 [(set_attr "type" "imul3")])
1266 (define_insn "*macchw"
1267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1268 (plus:SI (mult:SI (ashiftrt:SI
1269 (match_operand:SI 2 "gpc_reg_operand" "r")
1270 (const_int 16))
1271 (sign_extend:SI
1272 (match_operand:HI 1 "gpc_reg_operand" "r")))
1273 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1274 "TARGET_MULHW"
1275 "macchw %0,%1,%2"
1276 [(set_attr "type" "imul3")])
1278 (define_insn "*macchwuc"
1279 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1280 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1281 (match_operand:SI 2 "gpc_reg_operand" "r")
1282 (const_int 16))
1283 (zero_extend:SI
1284 (match_operand:HI 1 "gpc_reg_operand" "r")))
1285 (match_operand:SI 4 "gpc_reg_operand" "0"))
1286 (const_int 0)))
1287 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1288 (plus:SI (mult:SI (lshiftrt:SI
1289 (match_dup 2)
1290 (const_int 16))
1291 (zero_extend:SI
1292 (match_dup 1)))
1293 (match_dup 4)))]
1294 "TARGET_MULHW"
1295 "macchwu. %0,%1,%2"
1296 [(set_attr "type" "imul3")])
1298 (define_insn "*macchwu"
1299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1300 (plus:SI (mult:SI (lshiftrt:SI
1301 (match_operand:SI 2 "gpc_reg_operand" "r")
1302 (const_int 16))
1303 (zero_extend:SI
1304 (match_operand:HI 1 "gpc_reg_operand" "r")))
1305 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1306 "TARGET_MULHW"
1307 "macchwu %0,%1,%2"
1308 [(set_attr "type" "imul3")])
1310 (define_insn "*machhwc"
1311 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1312 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1313 (match_operand:SI 1 "gpc_reg_operand" "%r")
1314 (const_int 16))
1315 (ashiftrt:SI
1316 (match_operand:SI 2 "gpc_reg_operand" "r")
1317 (const_int 16)))
1318 (match_operand:SI 4 "gpc_reg_operand" "0"))
1319 (const_int 0)))
1320 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1321 (plus:SI (mult:SI (ashiftrt:SI
1322 (match_dup 1)
1323 (const_int 16))
1324 (ashiftrt:SI
1325 (match_dup 2)
1326 (const_int 16)))
1327 (match_dup 4)))]
1328 "TARGET_MULHW"
1329 "machhw. %0,%1,%2"
1330 [(set_attr "type" "imul3")])
1332 (define_insn "*machhw"
1333 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1334 (plus:SI (mult:SI (ashiftrt:SI
1335 (match_operand:SI 1 "gpc_reg_operand" "%r")
1336 (const_int 16))
1337 (ashiftrt:SI
1338 (match_operand:SI 2 "gpc_reg_operand" "r")
1339 (const_int 16)))
1340 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1341 "TARGET_MULHW"
1342 "machhw %0,%1,%2"
1343 [(set_attr "type" "imul3")])
1345 (define_insn "*machhwuc"
1346 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1347 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1348 (match_operand:SI 1 "gpc_reg_operand" "%r")
1349 (const_int 16))
1350 (lshiftrt:SI
1351 (match_operand:SI 2 "gpc_reg_operand" "r")
1352 (const_int 16)))
1353 (match_operand:SI 4 "gpc_reg_operand" "0"))
1354 (const_int 0)))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (plus:SI (mult:SI (lshiftrt:SI
1357 (match_dup 1)
1358 (const_int 16))
1359 (lshiftrt:SI
1360 (match_dup 2)
1361 (const_int 16)))
1362 (match_dup 4)))]
1363 "TARGET_MULHW"
1364 "machhwu. %0,%1,%2"
1365 [(set_attr "type" "imul3")])
1367 (define_insn "*machhwu"
1368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1369 (plus:SI (mult:SI (lshiftrt:SI
1370 (match_operand:SI 1 "gpc_reg_operand" "%r")
1371 (const_int 16))
1372 (lshiftrt:SI
1373 (match_operand:SI 2 "gpc_reg_operand" "r")
1374 (const_int 16)))
1375 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1376 "TARGET_MULHW"
1377 "machhwu %0,%1,%2"
1378 [(set_attr "type" "imul3")])
1380 (define_insn "*maclhwc"
1381 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1382 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1383 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1384 (sign_extend:SI
1385 (match_operand:HI 2 "gpc_reg_operand" "r")))
1386 (match_operand:SI 4 "gpc_reg_operand" "0"))
1387 (const_int 0)))
1388 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1389 (plus:SI (mult:SI (sign_extend:SI
1390 (match_dup 1))
1391 (sign_extend:SI
1392 (match_dup 2)))
1393 (match_dup 4)))]
1394 "TARGET_MULHW"
1395 "maclhw. %0,%1,%2"
1396 [(set_attr "type" "imul3")])
1398 (define_insn "*maclhw"
1399 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1400 (plus:SI (mult:SI (sign_extend:SI
1401 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1402 (sign_extend:SI
1403 (match_operand:HI 2 "gpc_reg_operand" "r")))
1404 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1405 "TARGET_MULHW"
1406 "maclhw %0,%1,%2"
1407 [(set_attr "type" "imul3")])
1409 (define_insn "*maclhwuc"
1410 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1411 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1412 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1413 (zero_extend:SI
1414 (match_operand:HI 2 "gpc_reg_operand" "r")))
1415 (match_operand:SI 4 "gpc_reg_operand" "0"))
1416 (const_int 0)))
1417 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1418 (plus:SI (mult:SI (zero_extend:SI
1419 (match_dup 1))
1420 (zero_extend:SI
1421 (match_dup 2)))
1422 (match_dup 4)))]
1423 "TARGET_MULHW"
1424 "maclhwu. %0,%1,%2"
1425 [(set_attr "type" "imul3")])
1427 (define_insn "*maclhwu"
1428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1429 (plus:SI (mult:SI (zero_extend:SI
1430 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1431 (zero_extend:SI
1432 (match_operand:HI 2 "gpc_reg_operand" "r")))
1433 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1434 "TARGET_MULHW"
1435 "maclhwu %0,%1,%2"
1436 [(set_attr "type" "imul3")])
1438 (define_insn "*nmacchwc"
1439 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1440 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1441 (mult:SI (ashiftrt:SI
1442 (match_operand:SI 2 "gpc_reg_operand" "r")
1443 (const_int 16))
1444 (sign_extend:SI
1445 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1446 (const_int 0)))
1447 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1448 (minus:SI (match_dup 4)
1449 (mult:SI (ashiftrt:SI
1450 (match_dup 2)
1451 (const_int 16))
1452 (sign_extend:SI
1453 (match_dup 1)))))]
1454 "TARGET_MULHW"
1455 "nmacchw. %0,%1,%2"
1456 [(set_attr "type" "imul3")])
1458 (define_insn "*nmacchw"
1459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1460 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1461 (mult:SI (ashiftrt:SI
1462 (match_operand:SI 2 "gpc_reg_operand" "r")
1463 (const_int 16))
1464 (sign_extend:SI
1465 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1466 "TARGET_MULHW"
1467 "nmacchw %0,%1,%2"
1468 [(set_attr "type" "imul3")])
1470 (define_insn "*nmachhwc"
1471 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1472 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1473 (mult:SI (ashiftrt:SI
1474 (match_operand:SI 1 "gpc_reg_operand" "%r")
1475 (const_int 16))
1476 (ashiftrt:SI
1477 (match_operand:SI 2 "gpc_reg_operand" "r")
1478 (const_int 16))))
1479 (const_int 0)))
1480 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1481 (minus:SI (match_dup 4)
1482 (mult:SI (ashiftrt:SI
1483 (match_dup 1)
1484 (const_int 16))
1485 (ashiftrt:SI
1486 (match_dup 2)
1487 (const_int 16)))))]
1488 "TARGET_MULHW"
1489 "nmachhw. %0,%1,%2"
1490 [(set_attr "type" "imul3")])
1492 (define_insn "*nmachhw"
1493 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1494 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1495 (mult:SI (ashiftrt:SI
1496 (match_operand:SI 1 "gpc_reg_operand" "%r")
1497 (const_int 16))
1498 (ashiftrt:SI
1499 (match_operand:SI 2 "gpc_reg_operand" "r")
1500 (const_int 16)))))]
1501 "TARGET_MULHW"
1502 "nmachhw %0,%1,%2"
1503 [(set_attr "type" "imul3")])
1505 (define_insn "*nmaclhwc"
1506 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1507 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1508 (mult:SI (sign_extend:SI
1509 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1510 (sign_extend:SI
1511 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1512 (const_int 0)))
1513 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1514 (minus:SI (match_dup 4)
1515 (mult:SI (sign_extend:SI
1516 (match_dup 1))
1517 (sign_extend:SI
1518 (match_dup 2)))))]
1519 "TARGET_MULHW"
1520 "nmaclhw. %0,%1,%2"
1521 [(set_attr "type" "imul3")])
1523 (define_insn "*nmaclhw"
1524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1525 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1526 (mult:SI (sign_extend:SI
1527 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1528 (sign_extend:SI
1529 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1530 "TARGET_MULHW"
1531 "nmaclhw %0,%1,%2"
1532 [(set_attr "type" "imul3")])
1534 (define_insn "*mulchwc"
1535 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1536 (compare:CC (mult:SI (ashiftrt:SI
1537 (match_operand:SI 2 "gpc_reg_operand" "r")
1538 (const_int 16))
1539 (sign_extend:SI
1540 (match_operand:HI 1 "gpc_reg_operand" "r")))
1541 (const_int 0)))
1542 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1543 (mult:SI (ashiftrt:SI
1544 (match_dup 2)
1545 (const_int 16))
1546 (sign_extend:SI
1547 (match_dup 1))))]
1548 "TARGET_MULHW"
1549 "mulchw. %0,%1,%2"
1550 [(set_attr "type" "imul3")])
1552 (define_insn "*mulchw"
1553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1554 (mult:SI (ashiftrt:SI
1555 (match_operand:SI 2 "gpc_reg_operand" "r")
1556 (const_int 16))
1557 (sign_extend:SI
1558 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1559 "TARGET_MULHW"
1560 "mulchw %0,%1,%2"
1561 [(set_attr "type" "imul3")])
1563 (define_insn "*mulchwuc"
1564 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1565 (compare:CC (mult:SI (lshiftrt:SI
1566 (match_operand:SI 2 "gpc_reg_operand" "r")
1567 (const_int 16))
1568 (zero_extend:SI
1569 (match_operand:HI 1 "gpc_reg_operand" "r")))
1570 (const_int 0)))
1571 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1572 (mult:SI (lshiftrt:SI
1573 (match_dup 2)
1574 (const_int 16))
1575 (zero_extend:SI
1576 (match_dup 1))))]
1577 "TARGET_MULHW"
1578 "mulchwu. %0,%1,%2"
1579 [(set_attr "type" "imul3")])
1581 (define_insn "*mulchwu"
1582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1583 (mult:SI (lshiftrt:SI
1584 (match_operand:SI 2 "gpc_reg_operand" "r")
1585 (const_int 16))
1586 (zero_extend:SI
1587 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1588 "TARGET_MULHW"
1589 "mulchwu %0,%1,%2"
1590 [(set_attr "type" "imul3")])
1592 (define_insn "*mulhhwc"
1593 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1594 (compare:CC (mult:SI (ashiftrt:SI
1595 (match_operand:SI 1 "gpc_reg_operand" "%r")
1596 (const_int 16))
1597 (ashiftrt:SI
1598 (match_operand:SI 2 "gpc_reg_operand" "r")
1599 (const_int 16)))
1600 (const_int 0)))
1601 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1602 (mult:SI (ashiftrt:SI
1603 (match_dup 1)
1604 (const_int 16))
1605 (ashiftrt:SI
1606 (match_dup 2)
1607 (const_int 16))))]
1608 "TARGET_MULHW"
1609 "mulhhw. %0,%1,%2"
1610 [(set_attr "type" "imul3")])
1612 (define_insn "*mulhhw"
1613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1614 (mult:SI (ashiftrt:SI
1615 (match_operand:SI 1 "gpc_reg_operand" "%r")
1616 (const_int 16))
1617 (ashiftrt:SI
1618 (match_operand:SI 2 "gpc_reg_operand" "r")
1619 (const_int 16))))]
1620 "TARGET_MULHW"
1621 "mulhhw %0,%1,%2"
1622 [(set_attr "type" "imul3")])
1624 (define_insn "*mulhhwuc"
1625 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1626 (compare:CC (mult:SI (lshiftrt:SI
1627 (match_operand:SI 1 "gpc_reg_operand" "%r")
1628 (const_int 16))
1629 (lshiftrt:SI
1630 (match_operand:SI 2 "gpc_reg_operand" "r")
1631 (const_int 16)))
1632 (const_int 0)))
1633 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1634 (mult:SI (lshiftrt:SI
1635 (match_dup 1)
1636 (const_int 16))
1637 (lshiftrt:SI
1638 (match_dup 2)
1639 (const_int 16))))]
1640 "TARGET_MULHW"
1641 "mulhhwu. %0,%1,%2"
1642 [(set_attr "type" "imul3")])
1644 (define_insn "*mulhhwu"
1645 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1646 (mult:SI (lshiftrt:SI
1647 (match_operand:SI 1 "gpc_reg_operand" "%r")
1648 (const_int 16))
1649 (lshiftrt:SI
1650 (match_operand:SI 2 "gpc_reg_operand" "r")
1651 (const_int 16))))]
1652 "TARGET_MULHW"
1653 "mulhhwu %0,%1,%2"
1654 [(set_attr "type" "imul3")])
1656 (define_insn "*mullhwc"
1657 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1658 (compare:CC (mult:SI (sign_extend:SI
1659 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1660 (sign_extend:SI
1661 (match_operand:HI 2 "gpc_reg_operand" "r")))
1662 (const_int 0)))
1663 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1664 (mult:SI (sign_extend:SI
1665 (match_dup 1))
1666 (sign_extend:SI
1667 (match_dup 2))))]
1668 "TARGET_MULHW"
1669 "mullhw. %0,%1,%2"
1670 [(set_attr "type" "imul3")])
1672 (define_insn "*mullhw"
1673 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1674 (mult:SI (sign_extend:SI
1675 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1676 (sign_extend:SI
1677 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1678 "TARGET_MULHW"
1679 "mullhw %0,%1,%2"
1680 [(set_attr "type" "imul3")])
1682 (define_insn "*mullhwuc"
1683 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1684 (compare:CC (mult:SI (zero_extend:SI
1685 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1686 (zero_extend:SI
1687 (match_operand:HI 2 "gpc_reg_operand" "r")))
1688 (const_int 0)))
1689 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1690 (mult:SI (zero_extend:SI
1691 (match_dup 1))
1692 (zero_extend:SI
1693 (match_dup 2))))]
1694 "TARGET_MULHW"
1695 "mullhwu. %0,%1,%2"
1696 [(set_attr "type" "imul3")])
1698 (define_insn "*mullhwu"
1699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1700 (mult:SI (zero_extend:SI
1701 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1702 (zero_extend:SI
1703 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1704 "TARGET_MULHW"
1705 "mullhwu %0,%1,%2"
1706 [(set_attr "type" "imul3")])
1707 \f
1708 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1709 (define_insn "dlmzb"
1710 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1711 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1712 (match_operand:SI 2 "gpc_reg_operand" "r")]
1713 UNSPEC_DLMZB_CR))
1714 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1715 (unspec:SI [(match_dup 1)
1716 (match_dup 2)]
1717 UNSPEC_DLMZB))]
1718 "TARGET_DLMZB"
1719 "dlmzb. %0,%1,%2")
1721 (define_expand "strlensi"
1722 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1723 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1724 (match_operand:QI 2 "const_int_operand" "")
1725 (match_operand 3 "const_int_operand" "")]
1726 UNSPEC_DLMZB_STRLEN))
1727 (clobber (match_scratch:CC 4 "=x"))]
1728 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1729 {
1730 rtx result = operands[0];
1731 rtx src = operands[1];
1732 rtx search_char = operands[2];
1733 rtx align = operands[3];
1734 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1735 rtx loop_label, end_label, mem, cr0, cond;
1736 if (search_char != const0_rtx
1737 || GET_CODE (align) != CONST_INT
1738 || INTVAL (align) < 8)
1739 FAIL;
1740 word1 = gen_reg_rtx (SImode);
1741 word2 = gen_reg_rtx (SImode);
1742 scratch_dlmzb = gen_reg_rtx (SImode);
1743 scratch_string = gen_reg_rtx (Pmode);
1744 loop_label = gen_label_rtx ();
1745 end_label = gen_label_rtx ();
1746 addr = force_reg (Pmode, XEXP (src, 0));
1747 emit_move_insn (scratch_string, addr);
1748 emit_label (loop_label);
1749 mem = change_address (src, SImode, scratch_string);
1750 emit_move_insn (word1, mem);
1751 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1752 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1753 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1754 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1755 emit_jump_insn (gen_rtx_SET (VOIDmode,
1756 pc_rtx,
1757 gen_rtx_IF_THEN_ELSE (VOIDmode,
1758 cond,
1759 gen_rtx_LABEL_REF
1760 (VOIDmode,
1761 end_label),
1762 pc_rtx)));
1763 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1764 emit_jump_insn (gen_rtx_SET (VOIDmode,
1765 pc_rtx,
1766 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1767 emit_barrier ();
1768 emit_label (end_label);
1769 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1770 emit_insn (gen_subsi3 (result, scratch_string, addr));
1771 emit_insn (gen_subsi3 (result, result, const1_rtx));
1772 DONE;
1773 })
1774 \f
1775 ;; Fixed-point arithmetic insns.
1777 (define_expand "add<mode>3"
1778 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1779 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1780 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1781 ""
1782 {
1783 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1784 {
1785 if (non_short_cint_operand (operands[2], DImode))
1786 FAIL;
1787 }
1788 else if (GET_CODE (operands[2]) == CONST_INT
1789 && ! add_operand (operands[2], <MODE>mode))
1790 {
1791 rtx tmp = ((!can_create_pseudo_p ()
1792 || rtx_equal_p (operands[0], operands[1]))
1793 ? operands[0] : gen_reg_rtx (<MODE>mode));
1795 HOST_WIDE_INT val = INTVAL (operands[2]);
1796 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1797 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1799 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1800 FAIL;
1802 /* The ordering here is important for the prolog expander.
1803 When space is allocated from the stack, adding 'low' first may
1804 produce a temporary deallocation (which would be bad). */
1805 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1806 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1807 DONE;
1808 }
1809 })
1811 ;; Discourage ai/addic because of carry but provide it in an alternative
1812 ;; allowing register zero as source.
1813 (define_insn "*add<mode>3_internal1"
1814 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1815 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1816 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1817 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1818 "@
1819 add %0,%1,%2
1820 addi %0,%1,%2
1821 addic %0,%1,%2
1822 addis %0,%1,%v2"
1823 [(set_attr "length" "4,4,4,4")])
1825 (define_insn "addsi3_high"
1826 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1827 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1828 (high:SI (match_operand 2 "" ""))))]
1829 "TARGET_MACHO && !TARGET_64BIT"
1830 "addis %0,%1,ha16(%2)"
1831 [(set_attr "length" "4")])
1833 (define_insn "*add<mode>3_internal2"
1834 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1835 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1836 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1837 (const_int 0)))
1838 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1839 ""
1840 "@
1841 add. %3,%1,%2
1842 addic. %3,%1,%2
1843 #
1844 #"
1845 [(set_attr "type" "fast_compare,compare,compare,compare")
1846 (set_attr "length" "4,4,8,8")])
1848 (define_split
1849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1850 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1851 (match_operand:GPR 2 "reg_or_short_operand" ""))
1852 (const_int 0)))
1853 (clobber (match_scratch:GPR 3 ""))]
1854 "reload_completed"
1855 [(set (match_dup 3)
1856 (plus:GPR (match_dup 1)
1857 (match_dup 2)))
1858 (set (match_dup 0)
1859 (compare:CC (match_dup 3)
1860 (const_int 0)))]
1861 "")
1863 (define_insn "*add<mode>3_internal3"
1864 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1865 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1866 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1867 (const_int 0)))
1868 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1869 (plus:P (match_dup 1)
1870 (match_dup 2)))]
1871 ""
1872 "@
1873 add. %0,%1,%2
1874 addic. %0,%1,%2
1875 #
1876 #"
1877 [(set_attr "type" "fast_compare,compare,compare,compare")
1878 (set_attr "length" "4,4,8,8")])
1880 (define_split
1881 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1882 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1883 (match_operand:P 2 "reg_or_short_operand" ""))
1884 (const_int 0)))
1885 (set (match_operand:P 0 "gpc_reg_operand" "")
1886 (plus:P (match_dup 1) (match_dup 2)))]
1887 "reload_completed"
1888 [(set (match_dup 0)
1889 (plus:P (match_dup 1)
1890 (match_dup 2)))
1891 (set (match_dup 3)
1892 (compare:CC (match_dup 0)
1893 (const_int 0)))]
1894 "")
1896 ;; Split an add that we can't do in one insn into two insns, each of which
1897 ;; does one 16-bit part. This is used by combine. Note that the low-order
1898 ;; add should be last in case the result gets used in an address.
1900 (define_split
1901 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1902 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1903 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1904 ""
1905 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1906 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1907 {
1908 HOST_WIDE_INT val = INTVAL (operands[2]);
1909 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1910 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1912 operands[4] = GEN_INT (low);
1913 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1914 operands[3] = GEN_INT (rest);
1915 else if (can_create_pseudo_p ())
1916 {
1917 operands[3] = gen_reg_rtx (DImode);
1918 emit_move_insn (operands[3], operands[2]);
1919 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1920 DONE;
1921 }
1922 else
1923 FAIL;
1924 })
1926 (define_expand "one_cmpl<mode>2"
1927 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1928 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
1929 ""
1930 {
1931 if (<MODE>mode == DImode && !TARGET_POWERPC64)
1932 {
1933 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
1934 DONE;
1935 }
1936 })
1938 (define_insn "*one_cmpl<mode>2"
1939 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1940 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1941 ""
1942 "nor %0,%1,%1")
1944 (define_insn ""
1945 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1946 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1947 (const_int 0)))
1948 (clobber (match_scratch:P 2 "=r,r"))]
1949 ""
1950 "@
1951 nor. %2,%1,%1
1952 #"
1953 [(set_attr "type" "fast_compare,compare")
1954 (set_attr "length" "4,8")])
1956 (define_split
1957 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1958 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1959 (const_int 0)))
1960 (clobber (match_scratch:P 2 ""))]
1961 "reload_completed"
1962 [(set (match_dup 2)
1963 (not:P (match_dup 1)))
1964 (set (match_dup 0)
1965 (compare:CC (match_dup 2)
1966 (const_int 0)))]
1967 "")
1969 (define_insn ""
1970 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1971 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1972 (const_int 0)))
1973 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1974 (not:P (match_dup 1)))]
1975 ""
1976 "@
1977 nor. %0,%1,%1
1978 #"
1979 [(set_attr "type" "fast_compare,compare")
1980 (set_attr "length" "4,8")])
1982 (define_split
1983 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1984 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1985 (const_int 0)))
1986 (set (match_operand:P 0 "gpc_reg_operand" "")
1987 (not:P (match_dup 1)))]
1988 "reload_completed"
1989 [(set (match_dup 0)
1990 (not:P (match_dup 1)))
1991 (set (match_dup 2)
1992 (compare:CC (match_dup 0)
1993 (const_int 0)))]
1994 "")
1996 (define_insn ""
1997 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1998 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1999 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
2000 ""
2001 "@
2002 subf %0,%2,%1
2003 subfic %0,%2,%1")
2005 (define_insn ""
2006 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2007 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2008 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2009 (const_int 0)))
2010 (clobber (match_scratch:P 3 "=r,r"))]
2011 ""
2012 "@
2013 subf. %3,%2,%1
2014 #"
2015 [(set_attr "type" "fast_compare")
2016 (set_attr "length" "4,8")])
2018 (define_split
2019 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2020 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2021 (match_operand:P 2 "gpc_reg_operand" ""))
2022 (const_int 0)))
2023 (clobber (match_scratch:P 3 ""))]
2024 "reload_completed"
2025 [(set (match_dup 3)
2026 (minus:P (match_dup 1)
2027 (match_dup 2)))
2028 (set (match_dup 0)
2029 (compare:CC (match_dup 3)
2030 (const_int 0)))]
2031 "")
2033 (define_insn ""
2034 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2035 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2036 (match_operand:P 2 "gpc_reg_operand" "r,r"))
2037 (const_int 0)))
2038 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2039 (minus:P (match_dup 1)
2040 (match_dup 2)))]
2041 ""
2042 "@
2043 subf. %0,%2,%1
2044 #"
2045 [(set_attr "type" "fast_compare")
2046 (set_attr "length" "4,8")])
2048 (define_split
2049 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2050 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
2051 (match_operand:P 2 "gpc_reg_operand" ""))
2052 (const_int 0)))
2053 (set (match_operand:P 0 "gpc_reg_operand" "")
2054 (minus:P (match_dup 1)
2055 (match_dup 2)))]
2056 "reload_completed"
2057 [(set (match_dup 0)
2058 (minus:P (match_dup 1)
2059 (match_dup 2)))
2060 (set (match_dup 3)
2061 (compare:CC (match_dup 0)
2062 (const_int 0)))]
2063 "")
2065 (define_expand "sub<mode>3"
2066 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2067 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
2068 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
2069 ""
2070 "
2071 {
2072 if (GET_CODE (operands[2]) == CONST_INT)
2073 {
2074 emit_insn (gen_add<mode>3 (operands[0], operands[1],
2075 negate_rtx (<MODE>mode, operands[2])));
2076 DONE;
2077 }
2078 }")
2080 (define_expand "neg<mode>2"
2081 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2082 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2083 ""
2084 "")
2086 (define_insn "*neg<mode>2_internal"
2087 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2088 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2089 ""
2090 "neg %0,%1")
2092 (define_insn ""
2093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2094 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2095 (const_int 0)))
2096 (clobber (match_scratch:P 2 "=r,r"))]
2097 ""
2098 "@
2099 neg. %2,%1
2100 #"
2101 [(set_attr "type" "fast_compare")
2102 (set_attr "length" "4,8")])
2104 (define_split
2105 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2106 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2107 (const_int 0)))
2108 (clobber (match_scratch:P 2 ""))]
2109 "reload_completed"
2110 [(set (match_dup 2)
2111 (neg:P (match_dup 1)))
2112 (set (match_dup 0)
2113 (compare:CC (match_dup 2)
2114 (const_int 0)))]
2115 "")
2117 (define_insn ""
2118 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2119 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2120 (const_int 0)))
2121 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2122 (neg:P (match_dup 1)))]
2123 ""
2124 "@
2125 neg. %0,%1
2126 #"
2127 [(set_attr "type" "fast_compare")
2128 (set_attr "length" "4,8")])
2130 (define_split
2131 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2132 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2133 (const_int 0)))
2134 (set (match_operand:P 0 "gpc_reg_operand" "")
2135 (neg:P (match_dup 1)))]
2136 "reload_completed"
2137 [(set (match_dup 0)
2138 (neg:P (match_dup 1)))
2139 (set (match_dup 2)
2140 (compare:CC (match_dup 0)
2141 (const_int 0)))]
2142 "")
2144 (define_insn "clz<mode>2"
2145 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2146 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2147 ""
2148 "cntlz<wd> %0,%1"
2149 [(set_attr "type" "cntlz")])
2151 (define_expand "ctz<mode>2"
2152 [(set (match_dup 2)
2153 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2154 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2155 (match_dup 2)))
2156 (clobber (scratch:CC))])
2157 (set (match_dup 4) (clz:GPR (match_dup 3)))
2158 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2159 (minus:GPR (match_dup 5) (match_dup 4)))]
2160 ""
2161 {
2162 operands[2] = gen_reg_rtx (<MODE>mode);
2163 operands[3] = gen_reg_rtx (<MODE>mode);
2164 operands[4] = gen_reg_rtx (<MODE>mode);
2165 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2166 })
2168 (define_expand "ffs<mode>2"
2169 [(set (match_dup 2)
2170 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2171 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2172 (match_dup 2)))
2173 (clobber (scratch:CC))])
2174 (set (match_dup 4) (clz:GPR (match_dup 3)))
2175 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2176 (minus:GPR (match_dup 5) (match_dup 4)))]
2177 ""
2178 {
2179 operands[2] = gen_reg_rtx (<MODE>mode);
2180 operands[3] = gen_reg_rtx (<MODE>mode);
2181 operands[4] = gen_reg_rtx (<MODE>mode);
2182 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2183 })
2185 (define_insn "popcntb<mode>2"
2186 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2187 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2188 UNSPEC_POPCNTB))]
2189 "TARGET_POPCNTB"
2190 "popcntb %0,%1"
2191 [(set_attr "length" "4")
2192 (set_attr "type" "popcnt")])
2194 (define_insn "popcntd<mode>2"
2195 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2196 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2197 "TARGET_POPCNTD"
2198 "popcnt<wd> %0,%1"
2199 [(set_attr "length" "4")
2200 (set_attr "type" "popcnt")])
2202 (define_expand "popcount<mode>2"
2203 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2204 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2205 "TARGET_POPCNTB || TARGET_POPCNTD"
2206 {
2207 rs6000_emit_popcount (operands[0], operands[1]);
2208 DONE;
2209 })
2211 (define_insn "parity<mode>2_cmpb"
2212 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2213 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2214 "TARGET_CMPB && TARGET_POPCNTB"
2215 "prty<wd> %0,%1"
2216 [(set_attr "length" "4")
2217 (set_attr "type" "popcnt")])
2219 (define_expand "parity<mode>2"
2220 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2221 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2222 "TARGET_POPCNTB"
2223 {
2224 rs6000_emit_parity (operands[0], operands[1]);
2225 DONE;
2226 })
2228 ;; Since the hardware zeros the upper part of the register, save generating the
2229 ;; AND immediate if we are converting to unsigned
2230 (define_insn "*bswaphi2_extenddi"
2231 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2232 (zero_extend:DI
2233 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2234 "TARGET_POWERPC64"
2235 "lhbrx %0,%y1"
2236 [(set_attr "length" "4")
2237 (set_attr "type" "load")])
2239 (define_insn "*bswaphi2_extendsi"
2240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2241 (zero_extend:SI
2242 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2243 ""
2244 "lhbrx %0,%y1"
2245 [(set_attr "length" "4")
2246 (set_attr "type" "load")])
2248 (define_expand "bswaphi2"
2249 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2250 (bswap:HI
2251 (match_operand:HI 1 "reg_or_mem_operand" "")))
2252 (clobber (match_scratch:SI 2 ""))])]
2253 ""
2254 {
2255 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2256 operands[1] = force_reg (HImode, operands[1]);
2257 })
2259 (define_insn "bswaphi2_internal"
2260 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2261 (bswap:HI
2262 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2263 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2264 ""
2265 "@
2266 lhbrx %0,%y1
2267 sthbrx %1,%y0
2268 #"
2269 [(set_attr "length" "4,4,12")
2270 (set_attr "type" "load,store,*")])
2272 ;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is
2273 ;; correct for -mlittle as well as -mbig.
2274 (define_split
2275 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2276 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2277 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2278 "reload_completed"
2279 [(set (match_dup 3)
2280 (zero_extract:SI (match_dup 4)
2281 (const_int 8)
2282 (const_int 16)))
2283 (set (match_dup 2)
2284 (and:SI (ashift:SI (match_dup 4)
2285 (const_int 8))
2286 (const_int 65280))) ;; 0xff00
2287 (set (match_dup 3)
2288 (ior:SI (match_dup 3)
2289 (match_dup 2)))]
2290 "
2291 {
2292 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2293 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2294 }")
2296 (define_insn "*bswapsi2_extenddi"
2297 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2298 (zero_extend:DI
2299 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2300 "TARGET_POWERPC64"
2301 "lwbrx %0,%y1"
2302 [(set_attr "length" "4")
2303 (set_attr "type" "load")])
2305 (define_expand "bswapsi2"
2306 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2307 (bswap:SI
2308 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2309 ""
2310 {
2311 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2312 operands[1] = force_reg (SImode, operands[1]);
2313 })
2315 (define_insn "*bswapsi2_internal"
2316 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2317 (bswap:SI
2318 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2319 ""
2320 "@
2321 lwbrx %0,%y1
2322 stwbrx %1,%y0
2323 #"
2324 [(set_attr "length" "4,4,12")
2325 (set_attr "type" "load,store,*")])
2327 ;; We are always BITS_BIG_ENDIAN, so the bit positions below in
2328 ;; zero_extract insns do not change for -mlittle.
2329 (define_split
2330 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2331 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2332 "reload_completed"
2333 [(set (match_dup 0)
2334 (rotate:SI (match_dup 1) (const_int 8)))
2335 (set (zero_extract:SI (match_dup 0)
2336 (const_int 8)
2337 (const_int 0))
2338 (match_dup 1))
2339 (set (zero_extract:SI (match_dup 0)
2340 (const_int 8)
2341 (const_int 16))
2342 (rotate:SI (match_dup 1)
2343 (const_int 16)))]
2344 "")
2346 (define_expand "bswapdi2"
2347 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2348 (bswap:DI
2349 (match_operand:DI 1 "reg_or_mem_operand" "")))
2350 (clobber (match_scratch:DI 2 ""))
2351 (clobber (match_scratch:DI 3 ""))
2352 (clobber (match_scratch:DI 4 ""))])]
2353 ""
2354 {
2355 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2356 operands[1] = force_reg (DImode, operands[1]);
2358 if (!TARGET_POWERPC64)
2359 {
2360 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2361 that uses 64-bit registers needs the same scratch registers as 64-bit
2362 mode. */
2363 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2364 DONE;
2365 }
2366 })
2368 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2369 (define_insn "*bswapdi2_ldbrx"
2370 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2371 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2372 (clobber (match_scratch:DI 2 "=X,X,&r"))
2373 (clobber (match_scratch:DI 3 "=X,X,&r"))
2374 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2375 "TARGET_POWERPC64 && TARGET_LDBRX
2376 && (REG_P (operands[0]) || REG_P (operands[1]))"
2377 "@
2378 ldbrx %0,%y1
2379 stdbrx %1,%y0
2380 #"
2381 [(set_attr "length" "4,4,36")
2382 (set_attr "type" "load,store,*")])
2384 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2385 (define_insn "*bswapdi2_64bit"
2386 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2387 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2388 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2389 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2390 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2391 "TARGET_POWERPC64 && !TARGET_LDBRX
2392 && (REG_P (operands[0]) || REG_P (operands[1]))
2393 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))
2394 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
2395 "#"
2396 [(set_attr "length" "16,12,36")])
2398 (define_split
2399 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2400 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2401 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2402 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2403 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2404 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2405 [(const_int 0)]
2406 "
2407 {
2408 rtx dest = operands[0];
2409 rtx src = operands[1];
2410 rtx op2 = operands[2];
2411 rtx op3 = operands[3];
2412 rtx op4 = operands[4];
2413 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode,
2414 BYTES_BIG_ENDIAN ? 4 : 0);
2415 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode,
2416 BYTES_BIG_ENDIAN ? 4 : 0);
2417 rtx addr1;
2418 rtx addr2;
2419 rtx word_high;
2420 rtx word_low;
2422 addr1 = XEXP (src, 0);
2423 if (GET_CODE (addr1) == PLUS)
2424 {
2425 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2426 if (TARGET_AVOID_XFORM)
2427 {
2428 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2429 addr2 = op2;
2430 }
2431 else
2432 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2433 }
2434 else if (TARGET_AVOID_XFORM)
2435 {
2436 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2437 addr2 = op2;
2438 }
2439 else
2440 {
2441 emit_move_insn (op2, GEN_INT (4));
2442 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2443 }
2445 if (BYTES_BIG_ENDIAN)
2446 {
2447 word_high = change_address (src, SImode, addr1);
2448 word_low = change_address (src, SImode, addr2);
2449 }
2450 else
2451 {
2452 word_high = change_address (src, SImode, addr2);
2453 word_low = change_address (src, SImode, addr1);
2454 }
2456 emit_insn (gen_bswapsi2 (op3_32, word_low));
2457 emit_insn (gen_bswapsi2 (op4_32, word_high));
2458 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2459 emit_insn (gen_iordi3 (dest, dest, op4));
2460 }")
2462 (define_split
2463 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2464 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2465 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2466 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2467 (clobber (match_operand:DI 4 "" ""))]
2468 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2469 [(const_int 0)]
2470 "
2471 {
2472 rtx dest = operands[0];
2473 rtx src = operands[1];
2474 rtx op2 = operands[2];
2475 rtx op3 = operands[3];
2476 rtx src_si = simplify_gen_subreg (SImode, src, DImode,
2477 BYTES_BIG_ENDIAN ? 4 : 0);
2478 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode,
2479 BYTES_BIG_ENDIAN ? 4 : 0);
2480 rtx addr1;
2481 rtx addr2;
2482 rtx word_high;
2483 rtx word_low;
2485 addr1 = XEXP (dest, 0);
2486 if (GET_CODE (addr1) == PLUS)
2487 {
2488 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2489 if (TARGET_AVOID_XFORM)
2490 {
2491 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2492 addr2 = op2;
2493 }
2494 else
2495 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2496 }
2497 else if (TARGET_AVOID_XFORM)
2498 {
2499 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2500 addr2 = op2;
2501 }
2502 else
2503 {
2504 emit_move_insn (op2, GEN_INT (4));
2505 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2506 }
2508 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2509 if (BYTES_BIG_ENDIAN)
2510 {
2511 word_high = change_address (dest, SImode, addr1);
2512 word_low = change_address (dest, SImode, addr2);
2513 }
2514 else
2515 {
2516 word_high = change_address (dest, SImode, addr2);
2517 word_low = change_address (dest, SImode, addr1);
2518 }
2519 emit_insn (gen_bswapsi2 (word_high, src_si));
2520 emit_insn (gen_bswapsi2 (word_low, op3_si));
2521 }")
2523 (define_split
2524 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2525 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2526 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2527 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2528 (clobber (match_operand:DI 4 "" ""))]
2529 "TARGET_POWERPC64 && reload_completed"
2530 [(const_int 0)]
2531 "
2532 {
2533 rtx dest = operands[0];
2534 rtx src = operands[1];
2535 rtx op2 = operands[2];
2536 rtx op3 = operands[3];
2537 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0;
2538 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off);
2539 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off);
2540 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off);
2541 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off);
2543 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2544 emit_insn (gen_bswapsi2 (dest_si, src_si));
2545 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2546 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2547 emit_insn (gen_iordi3 (dest, dest, op3));
2548 }")
2550 (define_insn "bswapdi2_32bit"
2551 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,&r")
2552 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2553 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2554 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2555 "#"
2556 [(set_attr "length" "16,12,36")])
2558 (define_split
2559 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2560 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2561 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2562 "!TARGET_POWERPC64 && reload_completed"
2563 [(const_int 0)]
2564 "
2565 {
2566 rtx dest = operands[0];
2567 rtx src = operands[1];
2568 rtx op2 = operands[2];
2569 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2570 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2571 rtx addr1;
2572 rtx addr2;
2573 rtx word1;
2574 rtx word2;
2576 addr1 = XEXP (src, 0);
2577 if (GET_CODE (addr1) == PLUS)
2578 {
2579 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2580 if (TARGET_AVOID_XFORM)
2581 {
2582 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2583 addr2 = op2;
2584 }
2585 else
2586 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2587 }
2588 else if (TARGET_AVOID_XFORM)
2589 {
2590 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2591 addr2 = op2;
2592 }
2593 else
2594 {
2595 emit_move_insn (op2, GEN_INT (4));
2596 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2597 }
2599 word1 = change_address (src, SImode, addr1);
2600 word2 = change_address (src, SImode, addr2);
2602 emit_insn (gen_bswapsi2 (dest2, word1));
2603 emit_insn (gen_bswapsi2 (dest1, word2));
2604 }")
2606 (define_split
2607 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2608 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2609 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2610 "!TARGET_POWERPC64 && reload_completed"
2611 [(const_int 0)]
2612 "
2613 {
2614 rtx dest = operands[0];
2615 rtx src = operands[1];
2616 rtx op2 = operands[2];
2617 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2618 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2619 rtx addr1;
2620 rtx addr2;
2621 rtx word1;
2622 rtx word2;
2624 addr1 = XEXP (dest, 0);
2625 if (GET_CODE (addr1) == PLUS)
2626 {
2627 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2628 if (TARGET_AVOID_XFORM)
2629 {
2630 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2631 addr2 = op2;
2632 }
2633 else
2634 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2635 }
2636 else if (TARGET_AVOID_XFORM)
2637 {
2638 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2639 addr2 = op2;
2640 }
2641 else
2642 {
2643 emit_move_insn (op2, GEN_INT (4));
2644 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2645 }
2647 word1 = change_address (dest, SImode, addr1);
2648 word2 = change_address (dest, SImode, addr2);
2650 emit_insn (gen_bswapsi2 (word2, src1));
2651 emit_insn (gen_bswapsi2 (word1, src2));
2652 }")
2654 (define_split
2655 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2656 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2657 (clobber (match_operand:SI 2 "" ""))]
2658 "!TARGET_POWERPC64 && reload_completed"
2659 [(const_int 0)]
2660 "
2661 {
2662 rtx dest = operands[0];
2663 rtx src = operands[1];
2664 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0);
2665 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4);
2666 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0);
2667 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4);
2669 emit_insn (gen_bswapsi2 (dest1, src2));
2670 emit_insn (gen_bswapsi2 (dest2, src1));
2671 }")
2673 (define_insn "mulsi3"
2674 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2675 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2676 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2677 ""
2678 "@
2679 mullw %0,%1,%2
2680 mulli %0,%1,%2"
2681 [(set (attr "type")
2682 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2683 (const_string "imul3")
2684 (match_operand:SI 2 "short_cint_operand" "")
2685 (const_string "imul2")]
2686 (const_string "imul")))])
2688 (define_insn "*mulsi3_internal1"
2689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2690 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2691 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2692 (const_int 0)))
2693 (clobber (match_scratch:SI 3 "=r,r"))]
2694 "TARGET_32BIT"
2695 "@
2696 mullw. %3,%1,%2
2697 #"
2698 [(set_attr "type" "imul_compare")
2699 (set_attr "length" "4,8")])
2701 (define_split
2702 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2703 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2704 (match_operand:SI 2 "gpc_reg_operand" ""))
2705 (const_int 0)))
2706 (clobber (match_scratch:SI 3 ""))]
2707 "TARGET_32BIT && reload_completed"
2708 [(set (match_dup 3)
2709 (mult:SI (match_dup 1) (match_dup 2)))
2710 (set (match_dup 0)
2711 (compare:CC (match_dup 3)
2712 (const_int 0)))]
2713 "")
2715 (define_insn "*mulsi3_internal2"
2716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2717 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2718 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2719 (const_int 0)))
2720 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2721 (mult:SI (match_dup 1) (match_dup 2)))]
2722 "TARGET_32BIT"
2723 "@
2724 mullw. %0,%1,%2
2725 #"
2726 [(set_attr "type" "imul_compare")
2727 (set_attr "length" "4,8")])
2729 (define_split
2730 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2731 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2732 (match_operand:SI 2 "gpc_reg_operand" ""))
2733 (const_int 0)))
2734 (set (match_operand:SI 0 "gpc_reg_operand" "")
2735 (mult:SI (match_dup 1) (match_dup 2)))]
2736 "TARGET_32BIT && reload_completed"
2737 [(set (match_dup 0)
2738 (mult:SI (match_dup 1) (match_dup 2)))
2739 (set (match_dup 3)
2740 (compare:CC (match_dup 0)
2741 (const_int 0)))]
2742 "")
2745 (define_insn "udiv<mode>3"
2746 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2747 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2748 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2749 ""
2750 "div<wd>u %0,%1,%2"
2751 [(set (attr "type")
2752 (cond [(match_operand:SI 0 "" "")
2753 (const_string "idiv")]
2754 (const_string "ldiv")))])
2757 ;; For powers of two we can do srai/aze for divide and then adjust for
2758 ;; modulus. If it isn't a power of two, force operands into register and do
2759 ;; a normal divide.
2760 (define_expand "div<mode>3"
2761 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2762 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2763 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2764 ""
2765 {
2766 if (GET_CODE (operands[2]) != CONST_INT
2767 || INTVAL (operands[2]) <= 0
2768 || exact_log2 (INTVAL (operands[2])) < 0)
2769 operands[2] = force_reg (<MODE>mode, operands[2]);
2770 })
2772 (define_insn "*div<mode>3"
2773 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2774 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2775 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2776 ""
2777 "div<wd> %0,%1,%2"
2778 [(set (attr "type")
2779 (cond [(match_operand:SI 0 "" "")
2780 (const_string "idiv")]
2781 (const_string "ldiv")))])
2783 (define_expand "mod<mode>3"
2784 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2785 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2786 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2787 ""
2788 "
2789 {
2790 int i;
2791 rtx temp1;
2792 rtx temp2;
2794 if (GET_CODE (operands[2]) != CONST_INT
2795 || INTVAL (operands[2]) <= 0
2796 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2797 FAIL;
2799 temp1 = gen_reg_rtx (<MODE>mode);
2800 temp2 = gen_reg_rtx (<MODE>mode);
2802 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2803 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2804 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2805 DONE;
2806 }")
2808 (define_insn ""
2809 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2810 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2811 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2812 ""
2813 "sra<wd>i %0,%1,%p2\;addze %0,%0"
2814 [(set_attr "type" "two")
2815 (set_attr "length" "8")])
2817 (define_insn ""
2818 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2819 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2820 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2821 (const_int 0)))
2822 (clobber (match_scratch:P 3 "=r,r"))]
2823 ""
2824 "@
2825 sra<wd>i %3,%1,%p2\;addze. %3,%3
2826 #"
2827 [(set_attr "type" "compare")
2828 (set_attr "length" "8,12")
2829 (set_attr "cell_micro" "not")])
2831 (define_split
2832 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2833 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2834 (match_operand:GPR 2 "exact_log2_cint_operand"
2835 ""))
2836 (const_int 0)))
2837 (clobber (match_scratch:GPR 3 ""))]
2838 "reload_completed"
2839 [(set (match_dup 3)
2840 (div:<MODE> (match_dup 1) (match_dup 2)))
2841 (set (match_dup 0)
2842 (compare:CC (match_dup 3)
2843 (const_int 0)))]
2844 "")
2846 (define_insn ""
2847 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2848 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2849 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2850 (const_int 0)))
2851 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2852 (div:P (match_dup 1) (match_dup 2)))]
2853 ""
2854 "@
2855 sra<wd>i %0,%1,%p2\;addze. %0,%0
2856 #"
2857 [(set_attr "type" "compare")
2858 (set_attr "length" "8,12")
2859 (set_attr "cell_micro" "not")])
2861 (define_split
2862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2863 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2864 (match_operand:GPR 2 "exact_log2_cint_operand"
2865 ""))
2866 (const_int 0)))
2867 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2868 (div:GPR (match_dup 1) (match_dup 2)))]
2869 "reload_completed"
2870 [(set (match_dup 0)
2871 (div:<MODE> (match_dup 1) (match_dup 2)))
2872 (set (match_dup 3)
2873 (compare:CC (match_dup 0)
2874 (const_int 0)))]
2875 "")
2876 \f
2877 ;; Logical instructions
2878 ;; The logical instructions are mostly combined by using match_operator,
2879 ;; but the plain AND insns are somewhat different because there is no
2880 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2881 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2883 (define_expand "andsi3"
2884 [(parallel
2885 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2886 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2887 (match_operand:SI 2 "and_operand" "")))
2888 (clobber (match_scratch:CC 3 ""))])]
2889 ""
2890 "")
2892 (define_insn "andsi3_mc"
2893 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2894 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2895 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2896 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2897 "rs6000_gen_cell_microcode"
2898 "@
2899 and %0,%1,%2
2900 rlwinm %0,%1,0,%m2,%M2
2901 andi. %0,%1,%b2
2902 andis. %0,%1,%u2"
2903 [(set_attr "type" "*,*,fast_compare,fast_compare")])
2905 (define_insn "andsi3_nomc"
2906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2907 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2908 (match_operand:SI 2 "and_operand" "?r,T")))
2909 (clobber (match_scratch:CC 3 "=X,X"))]
2910 "!rs6000_gen_cell_microcode"
2911 "@
2912 and %0,%1,%2
2913 rlwinm %0,%1,0,%m2,%M2")
2915 (define_insn "andsi3_internal0_nomc"
2916 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2917 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2918 (match_operand:SI 2 "and_operand" "?r,T")))]
2919 "!rs6000_gen_cell_microcode"
2920 "@
2921 and %0,%1,%2
2922 rlwinm %0,%1,0,%m2,%M2")
2925 ;; Note to set cr's other than cr0 we do the and immediate and then
2926 ;; the test again -- this avoids a mfcr which on the higher end
2927 ;; machines causes an execution serialization
2929 (define_insn "*andsi3_internal2_mc"
2930 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2931 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2932 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2933 (const_int 0)))
2934 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2935 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2936 "TARGET_32BIT && rs6000_gen_cell_microcode"
2937 "@
2938 and. %3,%1,%2
2939 andi. %3,%1,%b2
2940 andis. %3,%1,%u2
2941 rlwinm. %3,%1,0,%m2,%M2
2942 #
2943 #
2944 #
2945 #"
2946 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2947 compare,compare,compare,compare")
2948 (set_attr "length" "4,4,4,4,8,8,8,8")])
2950 (define_insn "*andsi3_internal3_mc"
2951 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2952 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2953 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2954 (const_int 0)))
2955 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2956 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2957 "TARGET_64BIT && rs6000_gen_cell_microcode"
2958 "@
2959 #
2960 andi. %3,%1,%b2
2961 andis. %3,%1,%u2
2962 rlwinm. %3,%1,0,%m2,%M2
2963 #
2964 #
2965 #
2966 #"
2967 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2968 compare,compare,compare")
2969 (set_attr "length" "8,4,4,4,8,8,8,8")])
2971 (define_split
2972 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2973 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2974 (match_operand:GPR 2 "and_operand" ""))
2975 (const_int 0)))
2976 (clobber (match_scratch:GPR 3 ""))
2977 (clobber (match_scratch:CC 4 ""))]
2978 "reload_completed"
2979 [(parallel [(set (match_dup 3)
2980 (and:<MODE> (match_dup 1)
2981 (match_dup 2)))
2982 (clobber (match_dup 4))])
2983 (set (match_dup 0)
2984 (compare:CC (match_dup 3)
2985 (const_int 0)))]
2986 "")
2988 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2989 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2991 (define_split
2992 [(set (match_operand:CC 0 "cc_reg_operand" "")
2993 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2994 (match_operand:SI 2 "gpc_reg_operand" ""))
2995 (const_int 0)))
2996 (clobber (match_scratch:SI 3 ""))
2997 (clobber (match_scratch:CC 4 ""))]
2998 "TARGET_POWERPC64 && reload_completed"
2999 [(parallel [(set (match_dup 3)
3000 (and:SI (match_dup 1)
3001 (match_dup 2)))
3002 (clobber (match_dup 4))])
3003 (set (match_dup 0)
3004 (compare:CC (match_dup 3)
3005 (const_int 0)))]
3006 "")
3008 (define_insn "*andsi3_internal4"
3009 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3010 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3011 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3012 (const_int 0)))
3013 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3014 (and:SI (match_dup 1)
3015 (match_dup 2)))
3016 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3017 "TARGET_32BIT && rs6000_gen_cell_microcode"
3018 "@
3019 and. %0,%1,%2
3020 andi. %0,%1,%b2
3021 andis. %0,%1,%u2
3022 rlwinm. %0,%1,0,%m2,%M2
3023 #
3024 #
3025 #
3026 #"
3027 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3028 compare,compare,compare,compare")
3029 (set_attr "length" "4,4,4,4,8,8,8,8")])
3031 (define_insn "*andsi3_internal5_mc"
3032 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3033 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3034 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3035 (const_int 0)))
3036 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3037 (and:SI (match_dup 1)
3038 (match_dup 2)))
3039 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3040 "TARGET_64BIT && rs6000_gen_cell_microcode"
3041 "@
3042 #
3043 andi. %0,%1,%b2
3044 andis. %0,%1,%u2
3045 rlwinm. %0,%1,0,%m2,%M2
3046 #
3047 #
3048 #
3049 #"
3050 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3051 compare,compare,compare")
3052 (set_attr "length" "8,4,4,4,8,8,8,8")])
3054 (define_split
3055 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3056 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3057 (match_operand:SI 2 "and_operand" ""))
3058 (const_int 0)))
3059 (set (match_operand:SI 0 "gpc_reg_operand" "")
3060 (and:SI (match_dup 1)
3061 (match_dup 2)))
3062 (clobber (match_scratch:CC 4 ""))]
3063 "reload_completed"
3064 [(parallel [(set (match_dup 0)
3065 (and:SI (match_dup 1)
3066 (match_dup 2)))
3067 (clobber (match_dup 4))])
3068 (set (match_dup 3)
3069 (compare:CC (match_dup 0)
3070 (const_int 0)))]
3071 "")
3073 (define_split
3074 [(set (match_operand:CC 3 "cc_reg_operand" "")
3075 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3076 (match_operand:SI 2 "gpc_reg_operand" ""))
3077 (const_int 0)))
3078 (set (match_operand:SI 0 "gpc_reg_operand" "")
3079 (and:SI (match_dup 1)
3080 (match_dup 2)))
3081 (clobber (match_scratch:CC 4 ""))]
3082 "TARGET_POWERPC64 && reload_completed"
3083 [(parallel [(set (match_dup 0)
3084 (and:SI (match_dup 1)
3085 (match_dup 2)))
3086 (clobber (match_dup 4))])
3087 (set (match_dup 3)
3088 (compare:CC (match_dup 0)
3089 (const_int 0)))]
3090 "")
3092 ;; Handle the PowerPC64 rlwinm corner case
3094 (define_insn_and_split "*andsi3_internal6"
3095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3096 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3097 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3098 "TARGET_POWERPC64"
3099 "#"
3100 "TARGET_POWERPC64"
3101 [(set (match_dup 0)
3102 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3103 (match_dup 4)))
3104 (set (match_dup 0)
3105 (rotate:SI (match_dup 0) (match_dup 5)))]
3106 "
3107 {
3108 int mb = extract_MB (operands[2]);
3109 int me = extract_ME (operands[2]);
3110 operands[3] = GEN_INT (me + 1);
3111 operands[5] = GEN_INT (32 - (me + 1));
3112 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3113 }"
3114 [(set_attr "length" "8")])
3116 (define_expand "iorsi3"
3117 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3118 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3119 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3120 ""
3121 "
3122 {
3123 if (GET_CODE (operands[2]) == CONST_INT
3124 && ! logical_operand (operands[2], SImode))
3125 {
3126 HOST_WIDE_INT value = INTVAL (operands[2]);
3127 rtx tmp = ((!can_create_pseudo_p ()
3128 || rtx_equal_p (operands[0], operands[1]))
3129 ? operands[0] : gen_reg_rtx (SImode));
3131 emit_insn (gen_iorsi3 (tmp, operands[1],
3132 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3133 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3134 DONE;
3135 }
3136 }")
3138 (define_expand "xorsi3"
3139 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3140 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3141 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3142 ""
3143 "
3144 {
3145 if (GET_CODE (operands[2]) == CONST_INT
3146 && ! logical_operand (operands[2], SImode))
3147 {
3148 HOST_WIDE_INT value = INTVAL (operands[2]);
3149 rtx tmp = ((!can_create_pseudo_p ()
3150 || rtx_equal_p (operands[0], operands[1]))
3151 ? operands[0] : gen_reg_rtx (SImode));
3153 emit_insn (gen_xorsi3 (tmp, operands[1],
3154 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3155 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3156 DONE;
3157 }
3158 }")
3160 (define_insn "*boolsi3_internal1"
3161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3162 (match_operator:SI 3 "boolean_or_operator"
3163 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3164 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3165 ""
3166 "@
3167 %q3 %0,%1,%2
3168 %q3i %0,%1,%b2
3169 %q3is %0,%1,%u2")
3171 (define_insn "*boolsi3_internal2"
3172 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3173 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3174 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3175 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3176 (const_int 0)))
3177 (clobber (match_scratch:SI 3 "=r,r"))]
3178 "TARGET_32BIT"
3179 "@
3180 %q4. %3,%1,%2
3181 #"
3182 [(set_attr "type" "fast_compare,compare")
3183 (set_attr "length" "4,8")])
3185 (define_split
3186 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3187 (compare:CC (match_operator:SI 4 "boolean_operator"
3188 [(match_operand:SI 1 "gpc_reg_operand" "")
3189 (match_operand:SI 2 "gpc_reg_operand" "")])
3190 (const_int 0)))
3191 (clobber (match_scratch:SI 3 ""))]
3192 "TARGET_32BIT && reload_completed"
3193 [(set (match_dup 3) (match_dup 4))
3194 (set (match_dup 0)
3195 (compare:CC (match_dup 3)
3196 (const_int 0)))]
3197 "")
3199 (define_insn "*boolsi3_internal3"
3200 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3201 (compare:CC (match_operator:SI 4 "boolean_operator"
3202 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3203 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3204 (const_int 0)))
3205 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3206 (match_dup 4))]
3207 "TARGET_32BIT"
3208 "@
3209 %q4. %0,%1,%2
3210 #"
3211 [(set_attr "type" "fast_compare,compare")
3212 (set_attr "length" "4,8")])
3214 (define_split
3215 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3216 (compare:CC (match_operator:SI 4 "boolean_operator"
3217 [(match_operand:SI 1 "gpc_reg_operand" "")
3218 (match_operand:SI 2 "gpc_reg_operand" "")])
3219 (const_int 0)))
3220 (set (match_operand:SI 0 "gpc_reg_operand" "")
3221 (match_dup 4))]
3222 "TARGET_32BIT && reload_completed"
3223 [(set (match_dup 0) (match_dup 4))
3224 (set (match_dup 3)
3225 (compare:CC (match_dup 0)
3226 (const_int 0)))]
3227 "")
3229 ;; Split a logical operation that we can't do in one insn into two insns,
3230 ;; each of which does one 16-bit part. This is used by combine.
3232 (define_split
3233 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3234 (match_operator:SI 3 "boolean_or_operator"
3235 [(match_operand:SI 1 "gpc_reg_operand" "")
3236 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3237 ""
3238 [(set (match_dup 0) (match_dup 4))
3239 (set (match_dup 0) (match_dup 5))]
3240 "
3241 {
3242 rtx i;
3243 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3244 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3245 operands[1], i);
3246 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3247 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3248 operands[0], i);
3249 }")
3251 (define_insn "*boolcsi3_internal1"
3252 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3253 (match_operator:SI 3 "boolean_operator"
3254 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3255 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3256 ""
3257 "%q3 %0,%2,%1")
3259 (define_insn "*boolcsi3_internal2"
3260 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3261 (compare:CC (match_operator:SI 4 "boolean_operator"
3262 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3263 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3264 (const_int 0)))
3265 (clobber (match_scratch:SI 3 "=r,r"))]
3266 "TARGET_32BIT"
3267 "@
3268 %q4. %3,%2,%1
3269 #"
3270 [(set_attr "type" "compare")
3271 (set_attr "length" "4,8")])
3273 (define_split
3274 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3275 (compare:CC (match_operator:SI 4 "boolean_operator"
3276 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3277 (match_operand:SI 2 "gpc_reg_operand" "")])
3278 (const_int 0)))
3279 (clobber (match_scratch:SI 3 ""))]
3280 "TARGET_32BIT && reload_completed"
3281 [(set (match_dup 3) (match_dup 4))
3282 (set (match_dup 0)
3283 (compare:CC (match_dup 3)
3284 (const_int 0)))]
3285 "")
3287 (define_insn "*boolcsi3_internal3"
3288 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3289 (compare:CC (match_operator:SI 4 "boolean_operator"
3290 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3291 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3292 (const_int 0)))
3293 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3294 (match_dup 4))]
3295 "TARGET_32BIT"
3296 "@
3297 %q4. %0,%2,%1
3298 #"
3299 [(set_attr "type" "compare")
3300 (set_attr "length" "4,8")])
3302 (define_split
3303 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3304 (compare:CC (match_operator:SI 4 "boolean_operator"
3305 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3306 (match_operand:SI 2 "gpc_reg_operand" "")])
3307 (const_int 0)))
3308 (set (match_operand:SI 0 "gpc_reg_operand" "")
3309 (match_dup 4))]
3310 "TARGET_32BIT && reload_completed"
3311 [(set (match_dup 0) (match_dup 4))
3312 (set (match_dup 3)
3313 (compare:CC (match_dup 0)
3314 (const_int 0)))]
3315 "")
3317 (define_insn "*boolccsi3_internal1"
3318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3319 (match_operator:SI 3 "boolean_operator"
3320 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3321 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3322 ""
3323 "%q3 %0,%1,%2")
3325 (define_insn "*boolccsi3_internal2"
3326 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3327 (compare:CC (match_operator:SI 4 "boolean_operator"
3328 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3329 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3330 (const_int 0)))
3331 (clobber (match_scratch:SI 3 "=r,r"))]
3332 "TARGET_32BIT"
3333 "@
3334 %q4. %3,%1,%2
3335 #"
3336 [(set_attr "type" "fast_compare,compare")
3337 (set_attr "length" "4,8")])
3339 (define_split
3340 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3341 (compare:CC (match_operator:SI 4 "boolean_operator"
3342 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3343 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3344 (const_int 0)))
3345 (clobber (match_scratch:SI 3 ""))]
3346 "TARGET_32BIT && reload_completed"
3347 [(set (match_dup 3) (match_dup 4))
3348 (set (match_dup 0)
3349 (compare:CC (match_dup 3)
3350 (const_int 0)))]
3351 "")
3353 (define_insn "*boolccsi3_internal3"
3354 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3355 (compare:CC (match_operator:SI 4 "boolean_operator"
3356 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3357 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3358 (const_int 0)))
3359 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3360 (match_dup 4))]
3361 "TARGET_32BIT"
3362 "@
3363 %q4. %0,%1,%2
3364 #"
3365 [(set_attr "type" "fast_compare,compare")
3366 (set_attr "length" "4,8")])
3368 (define_split
3369 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3370 (compare:CC (match_operator:SI 4 "boolean_operator"
3371 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3372 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3373 (const_int 0)))
3374 (set (match_operand:SI 0 "gpc_reg_operand" "")
3375 (match_dup 4))]
3376 "TARGET_32BIT && reload_completed"
3377 [(set (match_dup 0) (match_dup 4))
3378 (set (match_dup 3)
3379 (compare:CC (match_dup 0)
3380 (const_int 0)))]
3381 "")
3382 \f
3383 ;; Rotate and shift insns, in all their variants. These support shifts,
3384 ;; field inserts and extracts, and various combinations thereof.
3385 (define_expand "insv"
3386 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3387 (match_operand:SI 1 "const_int_operand" "")
3388 (match_operand:SI 2 "const_int_operand" ""))
3389 (match_operand 3 "gpc_reg_operand" ""))]
3390 ""
3391 "
3392 {
3393 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3394 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3395 compiler if the address of the structure is taken later. Likewise, do
3396 not handle invalid E500 subregs. */
3397 if (GET_CODE (operands[0]) == SUBREG
3398 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3399 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3400 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3401 FAIL;
3403 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3404 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2],
3405 operands[3]));
3406 else
3407 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2],
3408 operands[3]));
3409 DONE;
3410 }")
3412 (define_insn "insvsi_internal"
3413 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3414 (match_operand:SI 1 "const_int_operand" "i")
3415 (match_operand:SI 2 "const_int_operand" "i"))
3416 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3417 ""
3418 "*
3419 {
3420 int start = INTVAL (operands[2]) & 31;
3421 int size = INTVAL (operands[1]) & 31;
3423 operands[4] = GEN_INT (32 - start - size);
3424 operands[1] = GEN_INT (start + size - 1);
3425 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3426 }"
3427 [(set_attr "type" "insert_word")])
3429 (define_insn "*insvsi_internal1"
3430 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3431 (match_operand:SI 1 "const_int_operand" "i")
3432 (match_operand:SI 2 "const_int_operand" "i"))
3433 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3434 (match_operand:SI 4 "const_int_operand" "i")))]
3435 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3436 "*
3437 {
3438 int shift = INTVAL (operands[4]) & 31;
3439 int start = INTVAL (operands[2]) & 31;
3440 int size = INTVAL (operands[1]) & 31;
3442 operands[4] = GEN_INT (shift - start - size);
3443 operands[1] = GEN_INT (start + size - 1);
3444 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3445 }"
3446 [(set_attr "type" "insert_word")])
3448 (define_insn "*insvsi_internal2"
3449 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3450 (match_operand:SI 1 "const_int_operand" "i")
3451 (match_operand:SI 2 "const_int_operand" "i"))
3452 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3453 (match_operand:SI 4 "const_int_operand" "i")))]
3454 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3455 "*
3456 {
3457 int shift = INTVAL (operands[4]) & 31;
3458 int start = INTVAL (operands[2]) & 31;
3459 int size = INTVAL (operands[1]) & 31;
3461 operands[4] = GEN_INT (32 - shift - start - size);
3462 operands[1] = GEN_INT (start + size - 1);
3463 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3464 }"
3465 [(set_attr "type" "insert_word")])
3467 (define_insn "*insvsi_internal3"
3468 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3469 (match_operand:SI 1 "const_int_operand" "i")
3470 (match_operand:SI 2 "const_int_operand" "i"))
3471 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3472 (match_operand:SI 4 "const_int_operand" "i")))]
3473 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3474 "*
3475 {
3476 int shift = INTVAL (operands[4]) & 31;
3477 int start = INTVAL (operands[2]) & 31;
3478 int size = INTVAL (operands[1]) & 31;
3480 operands[4] = GEN_INT (32 - shift - start - size);
3481 operands[1] = GEN_INT (start + size - 1);
3482 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3483 }"
3484 [(set_attr "type" "insert_word")])
3486 (define_insn "*insvsi_internal4"
3487 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3488 (match_operand:SI 1 "const_int_operand" "i")
3489 (match_operand:SI 2 "const_int_operand" "i"))
3490 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3491 (match_operand:SI 4 "const_int_operand" "i")
3492 (match_operand:SI 5 "const_int_operand" "i")))]
3493 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3494 "*
3495 {
3496 int extract_start = INTVAL (operands[5]) & 31;
3497 int extract_size = INTVAL (operands[4]) & 31;
3498 int insert_start = INTVAL (operands[2]) & 31;
3499 int insert_size = INTVAL (operands[1]) & 31;
3501 /* Align extract field with insert field */
3502 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3503 operands[1] = GEN_INT (insert_start + insert_size - 1);
3504 return \"rlwimi %0,%3,%h5,%h2,%h1\";
3505 }"
3506 [(set_attr "type" "insert_word")])
3508 ;; combine patterns for rlwimi
3509 (define_insn "*insvsi_internal5"
3510 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3511 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3512 (match_operand:SI 1 "mask_operand" "i"))
3513 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3514 (match_operand:SI 2 "const_int_operand" "i"))
3515 (match_operand:SI 5 "mask_operand" "i"))))]
3516 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3517 "*
3518 {
3519 int me = extract_ME(operands[5]);
3520 int mb = extract_MB(operands[5]);
3521 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3522 operands[2] = GEN_INT(mb);
3523 operands[1] = GEN_INT(me);
3524 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3525 }"
3526 [(set_attr "type" "insert_word")])
3528 (define_insn "*insvsi_internal6"
3529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3530 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3531 (match_operand:SI 2 "const_int_operand" "i"))
3532 (match_operand:SI 5 "mask_operand" "i"))
3533 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3534 (match_operand:SI 1 "mask_operand" "i"))))]
3535 "INTVAL(operands[1]) == ~INTVAL(operands[5])"
3536 "*
3537 {
3538 int me = extract_ME(operands[5]);
3539 int mb = extract_MB(operands[5]);
3540 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3541 operands[2] = GEN_INT(mb);
3542 operands[1] = GEN_INT(me);
3543 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3544 }"
3545 [(set_attr "type" "insert_word")])
3547 (define_insn "insvdi_internal"
3548 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3549 (match_operand:SI 1 "const_int_operand" "i")
3550 (match_operand:SI 2 "const_int_operand" "i"))
3551 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3552 "TARGET_POWERPC64"
3553 "*
3554 {
3555 int start = INTVAL (operands[2]) & 63;
3556 int size = INTVAL (operands[1]) & 63;
3558 operands[1] = GEN_INT (64 - start - size);
3559 return \"rldimi %0,%3,%H1,%H2\";
3560 }"
3561 [(set_attr "type" "insert_dword")])
3563 (define_insn "*insvdi_internal2"
3564 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3565 (match_operand:SI 1 "const_int_operand" "i")
3566 (match_operand:SI 2 "const_int_operand" "i"))
3567 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3568 (match_operand:SI 4 "const_int_operand" "i")))]
3569 "TARGET_POWERPC64
3570 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3571 "*
3572 {
3573 int shift = INTVAL (operands[4]) & 63;
3574 int start = (INTVAL (operands[2]) & 63) - 32;
3575 int size = INTVAL (operands[1]) & 63;
3577 operands[4] = GEN_INT (64 - shift - start - size);
3578 operands[2] = GEN_INT (start);
3579 operands[1] = GEN_INT (start + size - 1);
3580 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3581 }")
3583 (define_insn "*insvdi_internal3"
3584 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3585 (match_operand:SI 1 "const_int_operand" "i")
3586 (match_operand:SI 2 "const_int_operand" "i"))
3587 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3588 (match_operand:SI 4 "const_int_operand" "i")))]
3589 "TARGET_POWERPC64
3590 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3591 "*
3592 {
3593 int shift = INTVAL (operands[4]) & 63;
3594 int start = (INTVAL (operands[2]) & 63) - 32;
3595 int size = INTVAL (operands[1]) & 63;
3597 operands[4] = GEN_INT (64 - shift - start - size);
3598 operands[2] = GEN_INT (start);
3599 operands[1] = GEN_INT (start + size - 1);
3600 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3601 }")
3603 (define_expand "extzv"
3604 [(set (match_operand 0 "gpc_reg_operand" "")
3605 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3606 (match_operand:SI 2 "const_int_operand" "")
3607 (match_operand:SI 3 "const_int_operand" "")))]
3608 ""
3609 "
3610 {
3611 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3612 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3613 compiler if the address of the structure is taken later. */
3614 if (GET_CODE (operands[0]) == SUBREG
3615 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3616 FAIL;
3618 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3619 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2],
3620 operands[3]));
3621 else
3622 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2],
3623 operands[3]));
3624 DONE;
3625 }")
3627 (define_insn "extzvsi_internal"
3628 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3629 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3630 (match_operand:SI 2 "const_int_operand" "i")
3631 (match_operand:SI 3 "const_int_operand" "i")))]
3632 ""
3633 "*
3634 {
3635 int start = INTVAL (operands[3]) & 31;
3636 int size = INTVAL (operands[2]) & 31;
3638 if (start + size >= 32)
3639 operands[3] = const0_rtx;
3640 else
3641 operands[3] = GEN_INT (start + size);
3642 return \"rlwinm %0,%1,%3,%s2,31\";
3643 }")
3645 (define_insn "*extzvsi_internal1"
3646 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3647 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3648 (match_operand:SI 2 "const_int_operand" "i,i")
3649 (match_operand:SI 3 "const_int_operand" "i,i"))
3650 (const_int 0)))
3651 (clobber (match_scratch:SI 4 "=r,r"))]
3652 ""
3653 "*
3654 {
3655 int start = INTVAL (operands[3]) & 31;
3656 int size = INTVAL (operands[2]) & 31;
3658 /* Force split for non-cc0 compare. */
3659 if (which_alternative == 1)
3660 return \"#\";
3662 /* If the bit-field being tested fits in the upper or lower half of a
3663 word, it is possible to use andiu. or andil. to test it. This is
3664 useful because the condition register set-use delay is smaller for
3665 andi[ul]. than for rlinm. This doesn't work when the starting bit
3666 position is 0 because the LT and GT bits may be set wrong. */
3668 if ((start > 0 && start + size <= 16) || start >= 16)
3669 {
3670 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3671 - (1 << (16 - (start & 15) - size))));
3672 if (start < 16)
3673 return \"andis. %4,%1,%3\";
3674 else
3675 return \"andi. %4,%1,%3\";
3676 }
3678 if (start + size >= 32)
3679 operands[3] = const0_rtx;
3680 else
3681 operands[3] = GEN_INT (start + size);
3682 return \"rlwinm. %4,%1,%3,%s2,31\";
3683 }"
3684 [(set_attr "type" "delayed_compare")
3685 (set_attr "length" "4,8")])
3687 (define_split
3688 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3689 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3690 (match_operand:SI 2 "const_int_operand" "")
3691 (match_operand:SI 3 "const_int_operand" ""))
3692 (const_int 0)))
3693 (clobber (match_scratch:SI 4 ""))]
3694 "reload_completed"
3695 [(set (match_dup 4)
3696 (zero_extract:SI (match_dup 1) (match_dup 2)
3697 (match_dup 3)))
3698 (set (match_dup 0)
3699 (compare:CC (match_dup 4)
3700 (const_int 0)))]
3701 "")
3703 (define_insn "*extzvsi_internal2"
3704 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3705 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3706 (match_operand:SI 2 "const_int_operand" "i,i")
3707 (match_operand:SI 3 "const_int_operand" "i,i"))
3708 (const_int 0)))
3709 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3710 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3711 ""
3712 "*
3713 {
3714 int start = INTVAL (operands[3]) & 31;
3715 int size = INTVAL (operands[2]) & 31;
3717 /* Force split for non-cc0 compare. */
3718 if (which_alternative == 1)
3719 return \"#\";
3721 /* Since we are using the output value, we can't ignore any need for
3722 a shift. The bit-field must end at the LSB. */
3723 if (start >= 16 && start + size == 32)
3724 {
3725 operands[3] = GEN_INT ((1 << size) - 1);
3726 return \"andi. %0,%1,%3\";
3727 }
3729 if (start + size >= 32)
3730 operands[3] = const0_rtx;
3731 else
3732 operands[3] = GEN_INT (start + size);
3733 return \"rlwinm. %0,%1,%3,%s2,31\";
3734 }"
3735 [(set_attr "type" "delayed_compare")
3736 (set_attr "length" "4,8")])
3738 (define_split
3739 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3740 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3741 (match_operand:SI 2 "const_int_operand" "")
3742 (match_operand:SI 3 "const_int_operand" ""))
3743 (const_int 0)))
3744 (set (match_operand:SI 0 "gpc_reg_operand" "")
3745 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3746 "reload_completed"
3747 [(set (match_dup 0)
3748 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3749 (set (match_dup 4)
3750 (compare:CC (match_dup 0)
3751 (const_int 0)))]
3752 "")
3754 (define_insn "extzvdi_internal"
3755 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3756 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3757 (match_operand:SI 2 "const_int_operand" "i")
3758 (match_operand:SI 3 "const_int_operand" "i")))]
3759 "TARGET_POWERPC64"
3760 "*
3761 {
3762 int start = INTVAL (operands[3]) & 63;
3763 int size = INTVAL (operands[2]) & 63;
3765 if (start + size >= 64)
3766 operands[3] = const0_rtx;
3767 else
3768 operands[3] = GEN_INT (start + size);
3769 operands[2] = GEN_INT (64 - size);
3770 return \"rldicl %0,%1,%3,%2\";
3771 }")
3773 (define_insn "*extzvdi_internal1"
3774 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3775 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3776 (match_operand:SI 2 "const_int_operand" "i")
3777 (match_operand:SI 3 "const_int_operand" "i"))
3778 (const_int 0)))
3779 (clobber (match_scratch:DI 4 "=r"))]
3780 "TARGET_64BIT && rs6000_gen_cell_microcode"
3781 "*
3782 {
3783 int start = INTVAL (operands[3]) & 63;
3784 int size = INTVAL (operands[2]) & 63;
3786 if (start + size >= 64)
3787 operands[3] = const0_rtx;
3788 else
3789 operands[3] = GEN_INT (start + size);
3790 operands[2] = GEN_INT (64 - size);
3791 return \"rldicl. %4,%1,%3,%2\";
3792 }"
3793 [(set_attr "type" "compare")])
3795 (define_insn "*extzvdi_internal2"
3796 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3797 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3798 (match_operand:SI 2 "const_int_operand" "i")
3799 (match_operand:SI 3 "const_int_operand" "i"))
3800 (const_int 0)))
3801 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3802 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3803 "TARGET_64BIT && rs6000_gen_cell_microcode"
3804 "*
3805 {
3806 int start = INTVAL (operands[3]) & 63;
3807 int size = INTVAL (operands[2]) & 63;
3809 if (start + size >= 64)
3810 operands[3] = const0_rtx;
3811 else
3812 operands[3] = GEN_INT (start + size);
3813 operands[2] = GEN_INT (64 - size);
3814 return \"rldicl. %0,%1,%3,%2\";
3815 }"
3816 [(set_attr "type" "compare")])
3818 (define_insn "rotlsi3"
3819 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3820 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3821 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3822 ""
3823 "@
3824 rlwnm %0,%1,%2,0xffffffff
3825 rlwinm %0,%1,%h2,0xffffffff"
3826 [(set_attr "type" "var_shift_rotate,integer")])
3828 (define_insn "*rotlsi3_64"
3829 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3830 (zero_extend:DI
3831 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3832 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3833 "TARGET_64BIT"
3834 "@
3835 rlwnm %0,%1,%2,0xffffffff
3836 rlwinm %0,%1,%h2,0xffffffff"
3837 [(set_attr "type" "var_shift_rotate,integer")])
3839 (define_insn "*rotlsi3_internal2"
3840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3841 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3842 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3843 (const_int 0)))
3844 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3845 ""
3846 "@
3847 rlwnm. %3,%1,%2,0xffffffff
3848 rlwinm. %3,%1,%h2,0xffffffff
3849 #
3850 #"
3851 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3852 (set_attr "length" "4,4,8,8")])
3854 (define_split
3855 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3856 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3857 (match_operand:SI 2 "reg_or_cint_operand" ""))
3858 (const_int 0)))
3859 (clobber (match_scratch:SI 3 ""))]
3860 "reload_completed"
3861 [(set (match_dup 3)
3862 (rotate:SI (match_dup 1) (match_dup 2)))
3863 (set (match_dup 0)
3864 (compare:CC (match_dup 3)
3865 (const_int 0)))]
3866 "")
3868 (define_insn "*rotlsi3_internal3"
3869 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3870 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3871 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3872 (const_int 0)))
3873 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3874 (rotate:SI (match_dup 1) (match_dup 2)))]
3875 ""
3876 "@
3877 rlwnm. %0,%1,%2,0xffffffff
3878 rlwinm. %0,%1,%h2,0xffffffff
3879 #
3880 #"
3881 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3882 (set_attr "length" "4,4,8,8")])
3884 (define_split
3885 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3886 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3887 (match_operand:SI 2 "reg_or_cint_operand" ""))
3888 (const_int 0)))
3889 (set (match_operand:SI 0 "gpc_reg_operand" "")
3890 (rotate:SI (match_dup 1) (match_dup 2)))]
3891 "reload_completed"
3892 [(set (match_dup 0)
3893 (rotate:SI (match_dup 1) (match_dup 2)))
3894 (set (match_dup 3)
3895 (compare:CC (match_dup 0)
3896 (const_int 0)))]
3897 "")
3899 (define_insn "*rotlsi3_internal4"
3900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3901 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3902 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3903 (match_operand:SI 3 "mask_operand" "n,n")))]
3904 ""
3905 "@
3906 rlwnm %0,%1,%2,%m3,%M3
3907 rlwinm %0,%1,%h2,%m3,%M3"
3908 [(set_attr "type" "var_shift_rotate,integer")])
3910 (define_insn "*rotlsi3_internal5"
3911 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3912 (compare:CC (and:SI
3913 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3914 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3915 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3916 (const_int 0)))
3917 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
3918 ""
3919 "@
3920 rlwnm. %4,%1,%2,%m3,%M3
3921 rlwinm. %4,%1,%h2,%m3,%M3
3922 #
3923 #"
3924 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3925 (set_attr "length" "4,4,8,8")])
3927 (define_split
3928 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3929 (compare:CC (and:SI
3930 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3931 (match_operand:SI 2 "reg_or_cint_operand" ""))
3932 (match_operand:SI 3 "mask_operand" ""))
3933 (const_int 0)))
3934 (clobber (match_scratch:SI 4 ""))]
3935 "reload_completed"
3936 [(set (match_dup 4)
3937 (and:SI (rotate:SI (match_dup 1)
3938 (match_dup 2))
3939 (match_dup 3)))
3940 (set (match_dup 0)
3941 (compare:CC (match_dup 4)
3942 (const_int 0)))]
3943 "")
3945 (define_insn "*rotlsi3_internal6"
3946 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
3947 (compare:CC (and:SI
3948 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3949 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3950 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
3951 (const_int 0)))
3952 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3953 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3954 ""
3955 "@
3956 rlwnm. %0,%1,%2,%m3,%M3
3957 rlwinm. %0,%1,%h2,%m3,%M3
3958 #
3959 #"
3960 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3961 (set_attr "length" "4,4,8,8")])
3963 (define_split
3964 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3965 (compare:CC (and:SI
3966 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3967 (match_operand:SI 2 "reg_or_cint_operand" ""))
3968 (match_operand:SI 3 "mask_operand" ""))
3969 (const_int 0)))
3970 (set (match_operand:SI 0 "gpc_reg_operand" "")
3971 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3972 "reload_completed"
3973 [(set (match_dup 0)
3974 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3975 (set (match_dup 4)
3976 (compare:CC (match_dup 0)
3977 (const_int 0)))]
3978 "")
3980 (define_insn "*rotlsi3_internal7le"
3981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3982 (zero_extend:SI
3983 (subreg:QI
3984 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3985 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3986 "!BYTES_BIG_ENDIAN"
3987 "rlw%I2nm %0,%1,%h2,0xff"
3988 [(set (attr "cell_micro")
3989 (if_then_else (match_operand:SI 2 "const_int_operand" "")
3990 (const_string "not")
3991 (const_string "always")))])
3993 (define_insn "*rotlsi3_internal7be"
3994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3995 (zero_extend:SI
3996 (subreg:QI
3997 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3998 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))]
3999 "BYTES_BIG_ENDIAN"
4000 "rlw%I2nm %0,%1,%h2,0xff"
4001 [(set (attr "cell_micro")
4002 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4003 (const_string "not")
4004 (const_string "always")))])
4006 (define_insn "*rotlsi3_internal8le"
4007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4008 (compare:CC (zero_extend:SI
4009 (subreg:QI
4010 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4011 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4012 (const_int 0)))
4013 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4014 "!BYTES_BIG_ENDIAN"
4015 "@
4016 rlwnm. %3,%1,%2,0xff
4017 rlwinm. %3,%1,%h2,0xff
4018 #
4019 #"
4020 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4021 (set_attr "length" "4,4,8,8")])
4023 (define_insn "*rotlsi3_internal8be"
4024 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4025 (compare:CC (zero_extend:SI
4026 (subreg:QI
4027 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4028 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
4029 (const_int 0)))
4030 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4031 "BYTES_BIG_ENDIAN"
4032 "@
4033 rlwnm. %3,%1,%2,0xff
4034 rlwinm. %3,%1,%h2,0xff
4035 #
4036 #"
4037 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4038 (set_attr "length" "4,4,8,8")])
4040 (define_split
4041 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4042 (compare:CC (zero_extend:SI
4043 (subreg:QI
4044 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4045 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4046 (const_int 0)))
4047 (clobber (match_scratch:SI 3 ""))]
4048 "!BYTES_BIG_ENDIAN && reload_completed"
4049 [(set (match_dup 3)
4050 (zero_extend:SI (subreg:QI
4051 (rotate:SI (match_dup 1)
4052 (match_dup 2)) 0)))
4053 (set (match_dup 0)
4054 (compare:CC (match_dup 3)
4055 (const_int 0)))]
4056 "")
4058 (define_split
4059 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4060 (compare:CC (zero_extend:SI
4061 (subreg:QI
4062 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4063 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4064 (const_int 0)))
4065 (clobber (match_scratch:SI 3 ""))]
4066 "BYTES_BIG_ENDIAN && reload_completed"
4067 [(set (match_dup 3)
4068 (zero_extend:SI (subreg:QI
4069 (rotate:SI (match_dup 1)
4070 (match_dup 2)) 3)))
4071 (set (match_dup 0)
4072 (compare:CC (match_dup 3)
4073 (const_int 0)))]
4074 "")
4076 (define_insn "*rotlsi3_internal9le"
4077 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4078 (compare:CC (zero_extend:SI
4079 (subreg:QI
4080 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4081 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4082 (const_int 0)))
4083 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4084 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4085 "!BYTES_BIG_ENDIAN"
4086 "@
4087 rlwnm. %0,%1,%2,0xff
4088 rlwinm. %0,%1,%h2,0xff
4089 #
4090 #"
4091 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4092 (set_attr "length" "4,4,8,8")])
4094 (define_insn "*rotlsi3_internal9be"
4095 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4096 (compare:CC (zero_extend:SI
4097 (subreg:QI
4098 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4099 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3))
4100 (const_int 0)))
4101 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4102 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4103 "BYTES_BIG_ENDIAN"
4104 "@
4105 rlwnm. %0,%1,%2,0xff
4106 rlwinm. %0,%1,%h2,0xff
4107 #
4108 #"
4109 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4110 (set_attr "length" "4,4,8,8")])
4112 (define_split
4113 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4114 (compare:CC (zero_extend:SI
4115 (subreg:QI
4116 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4117 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4118 (const_int 0)))
4119 (set (match_operand:SI 0 "gpc_reg_operand" "")
4120 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4121 "!BYTES_BIG_ENDIAN && reload_completed"
4122 [(set (match_dup 0)
4123 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4124 (set (match_dup 3)
4125 (compare:CC (match_dup 0)
4126 (const_int 0)))]
4127 "")
4129 (define_split
4130 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4131 (compare:CC (zero_extend:SI
4132 (subreg:QI
4133 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4134 (match_operand:SI 2 "reg_or_cint_operand" "")) 3))
4135 (const_int 0)))
4136 (set (match_operand:SI 0 "gpc_reg_operand" "")
4137 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))]
4138 "BYTES_BIG_ENDIAN && reload_completed"
4139 [(set (match_dup 0)
4140 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))
4141 (set (match_dup 3)
4142 (compare:CC (match_dup 0)
4143 (const_int 0)))]
4144 "")
4146 (define_insn "*rotlsi3_internal10le"
4147 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4148 (zero_extend:SI
4149 (subreg:HI
4150 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4151 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4152 "!BYTES_BIG_ENDIAN"
4153 "@
4154 rlwnm %0,%1,%2,0xffff
4155 rlwinm %0,%1,%h2,0xffff"
4156 [(set_attr "type" "var_shift_rotate,integer")])
4158 (define_insn "*rotlsi3_internal10be"
4159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4160 (zero_extend:SI
4161 (subreg:HI
4162 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4163 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))]
4164 "BYTES_BIG_ENDIAN"
4165 "@
4166 rlwnm %0,%1,%2,0xffff
4167 rlwinm %0,%1,%h2,0xffff"
4168 [(set_attr "type" "var_shift_rotate,integer")])
4170 (define_insn "*rotlsi3_internal11le"
4171 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4172 (compare:CC (zero_extend:SI
4173 (subreg:HI
4174 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4175 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4176 (const_int 0)))
4177 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4178 "!BYTES_BIG_ENDIAN"
4179 "@
4180 rlwnm. %3,%1,%2,0xffff
4181 rlwinm. %3,%1,%h2,0xffff
4182 #
4183 #"
4184 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4185 (set_attr "length" "4,4,8,8")])
4187 (define_insn "*rotlsi3_internal11be"
4188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4189 (compare:CC (zero_extend:SI
4190 (subreg:HI
4191 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4192 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4193 (const_int 0)))
4194 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4195 "BYTES_BIG_ENDIAN"
4196 "@
4197 rlwnm. %3,%1,%2,0xffff
4198 rlwinm. %3,%1,%h2,0xffff
4199 #
4200 #"
4201 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4202 (set_attr "length" "4,4,8,8")])
4204 (define_split
4205 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4206 (compare:CC (zero_extend:SI
4207 (subreg:HI
4208 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4209 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4210 (const_int 0)))
4211 (clobber (match_scratch:SI 3 ""))]
4212 "!BYTES_BIG_ENDIAN && reload_completed"
4213 [(set (match_dup 3)
4214 (zero_extend:SI (subreg:HI
4215 (rotate:SI (match_dup 1)
4216 (match_dup 2)) 0)))
4217 (set (match_dup 0)
4218 (compare:CC (match_dup 3)
4219 (const_int 0)))]
4220 "")
4222 (define_split
4223 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4224 (compare:CC (zero_extend:SI
4225 (subreg:HI
4226 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4227 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4228 (const_int 0)))
4229 (clobber (match_scratch:SI 3 ""))]
4230 "BYTES_BIG_ENDIAN && reload_completed"
4231 [(set (match_dup 3)
4232 (zero_extend:SI (subreg:HI
4233 (rotate:SI (match_dup 1)
4234 (match_dup 2)) 2)))
4235 (set (match_dup 0)
4236 (compare:CC (match_dup 3)
4237 (const_int 0)))]
4238 "")
4240 (define_insn "*rotlsi3_internal12le"
4241 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4242 (compare:CC (zero_extend:SI
4243 (subreg:HI
4244 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4245 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4246 (const_int 0)))
4247 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4248 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4249 "!BYTES_BIG_ENDIAN"
4250 "@
4251 rlwnm. %0,%1,%2,0xffff
4252 rlwinm. %0,%1,%h2,0xffff
4253 #
4254 #"
4255 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4256 (set_attr "length" "4,4,8,8")])
4258 (define_insn "*rotlsi3_internal12be"
4259 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4260 (compare:CC (zero_extend:SI
4261 (subreg:HI
4262 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4263 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2))
4264 (const_int 0)))
4265 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4266 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4267 "BYTES_BIG_ENDIAN"
4268 "@
4269 rlwnm. %0,%1,%2,0xffff
4270 rlwinm. %0,%1,%h2,0xffff
4271 #
4272 #"
4273 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4274 (set_attr "length" "4,4,8,8")])
4276 (define_split
4277 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4278 (compare:CC (zero_extend:SI
4279 (subreg:HI
4280 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4281 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4282 (const_int 0)))
4283 (set (match_operand:SI 0 "gpc_reg_operand" "")
4284 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4285 "!BYTES_BIG_ENDIAN && reload_completed"
4286 [(set (match_dup 0)
4287 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4288 (set (match_dup 3)
4289 (compare:CC (match_dup 0)
4290 (const_int 0)))]
4291 "")
4293 (define_split
4294 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4295 (compare:CC (zero_extend:SI
4296 (subreg:HI
4297 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4298 (match_operand:SI 2 "reg_or_cint_operand" "")) 2))
4299 (const_int 0)))
4300 (set (match_operand:SI 0 "gpc_reg_operand" "")
4301 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))]
4302 "BYTES_BIG_ENDIAN && reload_completed"
4303 [(set (match_dup 0)
4304 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))
4305 (set (match_dup 3)
4306 (compare:CC (match_dup 0)
4307 (const_int 0)))]
4308 "")
4310 (define_insn "ashlsi3"
4311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4312 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4313 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4314 ""
4315 "@
4316 slw %0,%1,%2
4317 slwi %0,%1,%h2"
4318 [(set_attr "type" "var_shift_rotate,shift")])
4320 (define_insn "*ashlsi3_64"
4321 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4322 (zero_extend:DI
4323 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4324 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4325 "TARGET_POWERPC64"
4326 "@
4327 slw %0,%1,%2
4328 slwi %0,%1,%h2"
4329 [(set_attr "type" "var_shift_rotate,shift")])
4331 (define_insn ""
4332 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4333 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4334 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4335 (const_int 0)))
4336 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4337 "TARGET_32BIT"
4338 "@
4339 slw. %3,%1,%2
4340 slwi. %3,%1,%h2
4341 #
4342 #"
4343 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4344 (set_attr "length" "4,4,8,8")])
4346 (define_split
4347 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4348 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4349 (match_operand:SI 2 "reg_or_cint_operand" ""))
4350 (const_int 0)))
4351 (clobber (match_scratch:SI 3 ""))]
4352 "TARGET_32BIT && reload_completed"
4353 [(set (match_dup 3)
4354 (ashift:SI (match_dup 1) (match_dup 2)))
4355 (set (match_dup 0)
4356 (compare:CC (match_dup 3)
4357 (const_int 0)))]
4358 "")
4360 (define_insn ""
4361 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4362 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4363 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4364 (const_int 0)))
4365 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4366 (ashift:SI (match_dup 1) (match_dup 2)))]
4367 "TARGET_32BIT"
4368 "@
4369 slw. %0,%1,%2
4370 slwi. %0,%1,%h2
4371 #
4372 #"
4373 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4374 (set_attr "length" "4,4,8,8")])
4376 (define_split
4377 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4378 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4379 (match_operand:SI 2 "reg_or_cint_operand" ""))
4380 (const_int 0)))
4381 (set (match_operand:SI 0 "gpc_reg_operand" "")
4382 (ashift:SI (match_dup 1) (match_dup 2)))]
4383 "TARGET_32BIT && reload_completed"
4384 [(set (match_dup 0)
4385 (ashift:SI (match_dup 1) (match_dup 2)))
4386 (set (match_dup 3)
4387 (compare:CC (match_dup 0)
4388 (const_int 0)))]
4389 "")
4391 (define_insn "rlwinm"
4392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4393 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4394 (match_operand:SI 2 "const_int_operand" "i"))
4395 (match_operand:SI 3 "mask_operand" "n")))]
4396 "includes_lshift_p (operands[2], operands[3])"
4397 "rlwinm %0,%1,%h2,%m3,%M3")
4399 (define_insn ""
4400 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4401 (compare:CC
4402 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4403 (match_operand:SI 2 "const_int_operand" "i,i"))
4404 (match_operand:SI 3 "mask_operand" "n,n"))
4405 (const_int 0)))
4406 (clobber (match_scratch:SI 4 "=r,r"))]
4407 "includes_lshift_p (operands[2], operands[3])"
4408 "@
4409 rlwinm. %4,%1,%h2,%m3,%M3
4410 #"
4411 [(set_attr "type" "delayed_compare")
4412 (set_attr "length" "4,8")])
4414 (define_split
4415 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4416 (compare:CC
4417 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4418 (match_operand:SI 2 "const_int_operand" ""))
4419 (match_operand:SI 3 "mask_operand" ""))
4420 (const_int 0)))
4421 (clobber (match_scratch:SI 4 ""))]
4422 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4423 [(set (match_dup 4)
4424 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4425 (match_dup 3)))
4426 (set (match_dup 0)
4427 (compare:CC (match_dup 4)
4428 (const_int 0)))]
4429 "")
4431 (define_insn ""
4432 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4433 (compare:CC
4434 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4435 (match_operand:SI 2 "const_int_operand" "i,i"))
4436 (match_operand:SI 3 "mask_operand" "n,n"))
4437 (const_int 0)))
4438 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4439 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4440 "includes_lshift_p (operands[2], operands[3])"
4441 "@
4442 rlwinm. %0,%1,%h2,%m3,%M3
4443 #"
4444 [(set_attr "type" "delayed_compare")
4445 (set_attr "length" "4,8")])
4447 (define_split
4448 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4449 (compare:CC
4450 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4451 (match_operand:SI 2 "const_int_operand" ""))
4452 (match_operand:SI 3 "mask_operand" ""))
4453 (const_int 0)))
4454 (set (match_operand:SI 0 "gpc_reg_operand" "")
4455 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4456 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4457 [(set (match_dup 0)
4458 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4459 (set (match_dup 4)
4460 (compare:CC (match_dup 0)
4461 (const_int 0)))]
4462 "")
4464 (define_insn "lshrsi3"
4465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4466 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4467 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4468 ""
4469 "@
4470 mr %0,%1
4471 srw %0,%1,%2
4472 srwi %0,%1,%h2"
4473 [(set_attr "type" "integer,var_shift_rotate,shift")])
4475 (define_insn "*lshrsi3_64"
4476 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4477 (zero_extend:DI
4478 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4479 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4480 "TARGET_POWERPC64"
4481 "@
4482 srw %0,%1,%2
4483 srwi %0,%1,%h2"
4484 [(set_attr "type" "var_shift_rotate,shift")])
4486 (define_insn ""
4487 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4488 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4489 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4490 (const_int 0)))
4491 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4492 "TARGET_32BIT"
4493 "@
4494 mr. %1,%1
4495 srw. %3,%1,%2
4496 srwi. %3,%1,%h2
4497 #
4498 #
4499 #"
4500 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4501 (set_attr "length" "4,4,4,8,8,8")])
4503 (define_split
4504 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4505 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4506 (match_operand:SI 2 "reg_or_cint_operand" ""))
4507 (const_int 0)))
4508 (clobber (match_scratch:SI 3 ""))]
4509 "TARGET_32BIT && reload_completed"
4510 [(set (match_dup 3)
4511 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4512 (set (match_dup 0)
4513 (compare:CC (match_dup 3)
4514 (const_int 0)))]
4515 "")
4517 (define_insn ""
4518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4519 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4520 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4521 (const_int 0)))
4522 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4523 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4524 "TARGET_32BIT"
4525 "@
4526 mr. %0,%1
4527 srw. %0,%1,%2
4528 srwi. %0,%1,%h2
4529 #
4530 #
4531 #"
4532 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4533 (set_attr "length" "4,4,4,8,8,8")])
4535 (define_split
4536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4537 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4538 (match_operand:SI 2 "reg_or_cint_operand" ""))
4539 (const_int 0)))
4540 (set (match_operand:SI 0 "gpc_reg_operand" "")
4541 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4542 "TARGET_32BIT && reload_completed"
4543 [(set (match_dup 0)
4544 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4545 (set (match_dup 3)
4546 (compare:CC (match_dup 0)
4547 (const_int 0)))]
4548 "")
4550 (define_insn ""
4551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4552 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4553 (match_operand:SI 2 "const_int_operand" "i"))
4554 (match_operand:SI 3 "mask_operand" "n")))]
4555 "includes_rshift_p (operands[2], operands[3])"
4556 "rlwinm %0,%1,%s2,%m3,%M3")
4558 (define_insn ""
4559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4560 (compare:CC
4561 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4562 (match_operand:SI 2 "const_int_operand" "i,i"))
4563 (match_operand:SI 3 "mask_operand" "n,n"))
4564 (const_int 0)))
4565 (clobber (match_scratch:SI 4 "=r,r"))]
4566 "includes_rshift_p (operands[2], operands[3])"
4567 "@
4568 rlwinm. %4,%1,%s2,%m3,%M3
4569 #"
4570 [(set_attr "type" "delayed_compare")
4571 (set_attr "length" "4,8")])
4573 (define_split
4574 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4575 (compare:CC
4576 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4577 (match_operand:SI 2 "const_int_operand" ""))
4578 (match_operand:SI 3 "mask_operand" ""))
4579 (const_int 0)))
4580 (clobber (match_scratch:SI 4 ""))]
4581 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4582 [(set (match_dup 4)
4583 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4584 (match_dup 3)))
4585 (set (match_dup 0)
4586 (compare:CC (match_dup 4)
4587 (const_int 0)))]
4588 "")
4590 (define_insn ""
4591 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4592 (compare:CC
4593 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4594 (match_operand:SI 2 "const_int_operand" "i,i"))
4595 (match_operand:SI 3 "mask_operand" "n,n"))
4596 (const_int 0)))
4597 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4598 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4599 "includes_rshift_p (operands[2], operands[3])"
4600 "@
4601 rlwinm. %0,%1,%s2,%m3,%M3
4602 #"
4603 [(set_attr "type" "delayed_compare")
4604 (set_attr "length" "4,8")])
4606 (define_split
4607 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4608 (compare:CC
4609 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4610 (match_operand:SI 2 "const_int_operand" ""))
4611 (match_operand:SI 3 "mask_operand" ""))
4612 (const_int 0)))
4613 (set (match_operand:SI 0 "gpc_reg_operand" "")
4614 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4615 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4616 [(set (match_dup 0)
4617 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4618 (set (match_dup 4)
4619 (compare:CC (match_dup 0)
4620 (const_int 0)))]
4621 "")
4623 (define_insn "*lshiftrt_internal1le"
4624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4625 (zero_extend:SI
4626 (subreg:QI
4627 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4628 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4629 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4630 "rlwinm %0,%1,%s2,0xff")
4632 (define_insn "*lshiftrt_internal1be"
4633 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4634 (zero_extend:SI
4635 (subreg:QI
4636 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4637 (match_operand:SI 2 "const_int_operand" "i")) 3)))]
4638 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4639 "rlwinm %0,%1,%s2,0xff")
4641 (define_insn "*lshiftrt_internal2le"
4642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4643 (compare:CC
4644 (zero_extend:SI
4645 (subreg:QI
4646 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4647 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4648 (const_int 0)))
4649 (clobber (match_scratch:SI 3 "=r,r"))]
4650 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4651 "@
4652 rlwinm. %3,%1,%s2,0xff
4653 #"
4654 [(set_attr "type" "delayed_compare")
4655 (set_attr "length" "4,8")])
4657 (define_insn "*lshiftrt_internal2be"
4658 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4659 (compare:CC
4660 (zero_extend:SI
4661 (subreg:QI
4662 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4663 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4664 (const_int 0)))
4665 (clobber (match_scratch:SI 3 "=r,r"))]
4666 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4667 "@
4668 rlwinm. %3,%1,%s2,0xff
4669 #"
4670 [(set_attr "type" "delayed_compare")
4671 (set_attr "length" "4,8")])
4673 (define_split
4674 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4675 (compare:CC
4676 (zero_extend:SI
4677 (subreg:QI
4678 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4679 (match_operand:SI 2 "const_int_operand" "")) 0))
4680 (const_int 0)))
4681 (clobber (match_scratch:SI 3 ""))]
4682 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4683 [(set (match_dup 3)
4684 (zero_extend:SI (subreg:QI
4685 (lshiftrt:SI (match_dup 1)
4686 (match_dup 2)) 0)))
4687 (set (match_dup 0)
4688 (compare:CC (match_dup 3)
4689 (const_int 0)))]
4690 "")
4692 (define_split
4693 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4694 (compare:CC
4695 (zero_extend:SI
4696 (subreg:QI
4697 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4698 (match_operand:SI 2 "const_int_operand" "")) 3))
4699 (const_int 0)))
4700 (clobber (match_scratch:SI 3 ""))]
4701 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4702 [(set (match_dup 3)
4703 (zero_extend:SI (subreg:QI
4704 (lshiftrt:SI (match_dup 1)
4705 (match_dup 2)) 3)))
4706 (set (match_dup 0)
4707 (compare:CC (match_dup 3)
4708 (const_int 0)))]
4709 "")
4711 (define_insn "*lshiftrt_internal3le"
4712 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4713 (compare:CC
4714 (zero_extend:SI
4715 (subreg:QI
4716 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4717 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4718 (const_int 0)))
4719 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4720 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4721 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4722 "@
4723 rlwinm. %0,%1,%s2,0xff
4724 #"
4725 [(set_attr "type" "delayed_compare")
4726 (set_attr "length" "4,8")])
4728 (define_insn "*lshiftrt_internal3be"
4729 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4730 (compare:CC
4731 (zero_extend:SI
4732 (subreg:QI
4733 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4734 (match_operand:SI 2 "const_int_operand" "i,i")) 3))
4735 (const_int 0)))
4736 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4737 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4738 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))"
4739 "@
4740 rlwinm. %0,%1,%s2,0xff
4741 #"
4742 [(set_attr "type" "delayed_compare")
4743 (set_attr "length" "4,8")])
4745 (define_split
4746 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4747 (compare:CC
4748 (zero_extend:SI
4749 (subreg:QI
4750 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4751 (match_operand:SI 2 "const_int_operand" "")) 0))
4752 (const_int 0)))
4753 (set (match_operand:SI 0 "gpc_reg_operand" "")
4754 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4755 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4756 [(set (match_dup 0)
4757 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4758 (set (match_dup 3)
4759 (compare:CC (match_dup 0)
4760 (const_int 0)))]
4761 "")
4763 (define_split
4764 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4765 (compare:CC
4766 (zero_extend:SI
4767 (subreg:QI
4768 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4769 (match_operand:SI 2 "const_int_operand" "")) 3))
4770 (const_int 0)))
4771 (set (match_operand:SI 0 "gpc_reg_operand" "")
4772 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))]
4773 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4774 [(set (match_dup 0)
4775 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))
4776 (set (match_dup 3)
4777 (compare:CC (match_dup 0)
4778 (const_int 0)))]
4779 "")
4781 (define_insn "*lshiftrt_internal4le"
4782 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4783 (zero_extend:SI
4784 (subreg:HI
4785 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4786 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4787 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4788 "rlwinm %0,%1,%s2,0xffff")
4790 (define_insn "*lshiftrt_internal4be"
4791 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4792 (zero_extend:SI
4793 (subreg:HI
4794 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4795 (match_operand:SI 2 "const_int_operand" "i")) 2)))]
4796 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4797 "rlwinm %0,%1,%s2,0xffff")
4799 (define_insn "*lshiftrt_internal5le"
4800 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4801 (compare:CC
4802 (zero_extend:SI
4803 (subreg:HI
4804 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4805 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4806 (const_int 0)))
4807 (clobber (match_scratch:SI 3 "=r,r"))]
4808 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4809 "@
4810 rlwinm. %3,%1,%s2,0xffff
4811 #"
4812 [(set_attr "type" "delayed_compare")
4813 (set_attr "length" "4,8")])
4815 (define_insn "*lshiftrt_internal5be"
4816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4817 (compare:CC
4818 (zero_extend:SI
4819 (subreg:HI
4820 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4821 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4822 (const_int 0)))
4823 (clobber (match_scratch:SI 3 "=r,r"))]
4824 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4825 "@
4826 rlwinm. %3,%1,%s2,0xffff
4827 #"
4828 [(set_attr "type" "delayed_compare")
4829 (set_attr "length" "4,8")])
4831 (define_split
4832 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4833 (compare:CC
4834 (zero_extend:SI
4835 (subreg:HI
4836 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4837 (match_operand:SI 2 "const_int_operand" "")) 0))
4838 (const_int 0)))
4839 (clobber (match_scratch:SI 3 ""))]
4840 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4841 [(set (match_dup 3)
4842 (zero_extend:SI (subreg:HI
4843 (lshiftrt:SI (match_dup 1)
4844 (match_dup 2)) 0)))
4845 (set (match_dup 0)
4846 (compare:CC (match_dup 3)
4847 (const_int 0)))]
4848 "")
4850 (define_split
4851 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4852 (compare:CC
4853 (zero_extend:SI
4854 (subreg:HI
4855 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4856 (match_operand:SI 2 "const_int_operand" "")) 2))
4857 (const_int 0)))
4858 (clobber (match_scratch:SI 3 ""))]
4859 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4860 [(set (match_dup 3)
4861 (zero_extend:SI (subreg:HI
4862 (lshiftrt:SI (match_dup 1)
4863 (match_dup 2)) 2)))
4864 (set (match_dup 0)
4865 (compare:CC (match_dup 3)
4866 (const_int 0)))]
4867 "")
4869 (define_insn "*lshiftrt_internal5le"
4870 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4871 (compare:CC
4872 (zero_extend:SI
4873 (subreg:HI
4874 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4875 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4876 (const_int 0)))
4877 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4878 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4879 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4880 "@
4881 rlwinm. %0,%1,%s2,0xffff
4882 #"
4883 [(set_attr "type" "delayed_compare")
4884 (set_attr "length" "4,8")])
4886 (define_insn "*lshiftrt_internal5be"
4887 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4888 (compare:CC
4889 (zero_extend:SI
4890 (subreg:HI
4891 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4892 (match_operand:SI 2 "const_int_operand" "i,i")) 2))
4893 (const_int 0)))
4894 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4895 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4896 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))"
4897 "@
4898 rlwinm. %0,%1,%s2,0xffff
4899 #"
4900 [(set_attr "type" "delayed_compare")
4901 (set_attr "length" "4,8")])
4903 (define_split
4904 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4905 (compare:CC
4906 (zero_extend:SI
4907 (subreg:HI
4908 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4909 (match_operand:SI 2 "const_int_operand" "")) 0))
4910 (const_int 0)))
4911 (set (match_operand:SI 0 "gpc_reg_operand" "")
4912 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4913 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4914 [(set (match_dup 0)
4915 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4916 (set (match_dup 3)
4917 (compare:CC (match_dup 0)
4918 (const_int 0)))]
4919 "")
4921 (define_split
4922 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4923 (compare:CC
4924 (zero_extend:SI
4925 (subreg:HI
4926 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4927 (match_operand:SI 2 "const_int_operand" "")) 2))
4928 (const_int 0)))
4929 (set (match_operand:SI 0 "gpc_reg_operand" "")
4930 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))]
4931 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4932 [(set (match_dup 0)
4933 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))
4934 (set (match_dup 3)
4935 (compare:CC (match_dup 0)
4936 (const_int 0)))]
4937 "")
4939 (define_insn "ashrsi3"
4940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4941 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4942 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4943 ""
4944 "@
4945 sraw %0,%1,%2
4946 srawi %0,%1,%h2"
4947 [(set_attr "type" "var_shift_rotate,shift")])
4949 (define_insn "*ashrsi3_64"
4950 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4951 (sign_extend:DI
4952 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4953 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4954 "TARGET_POWERPC64"
4955 "@
4956 sraw %0,%1,%2
4957 srawi %0,%1,%h2"
4958 [(set_attr "type" "var_shift_rotate,shift")])
4960 (define_insn ""
4961 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4962 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4963 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4964 (const_int 0)))
4965 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4966 ""
4967 "@
4968 sraw. %3,%1,%2
4969 srawi. %3,%1,%h2
4970 #
4971 #"
4972 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4973 (set_attr "length" "4,4,8,8")])
4975 (define_split
4976 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4977 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4978 (match_operand:SI 2 "reg_or_cint_operand" ""))
4979 (const_int 0)))
4980 (clobber (match_scratch:SI 3 ""))]
4981 "reload_completed"
4982 [(set (match_dup 3)
4983 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4984 (set (match_dup 0)
4985 (compare:CC (match_dup 3)
4986 (const_int 0)))]
4987 "")
4989 (define_insn ""
4990 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4991 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4992 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4993 (const_int 0)))
4994 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4995 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4996 ""
4997 "@
4998 sraw. %0,%1,%2
4999 srawi. %0,%1,%h2
5000 #
5001 #"
5002 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5003 (set_attr "length" "4,4,8,8")])
5004 \f
5005 ;; Builtins to replace a division to generate FRE reciprocal estimate
5006 ;; instructions and the necessary fixup instructions
5007 (define_expand "recip<mode>3"
5008 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5009 (match_operand:RECIPF 1 "gpc_reg_operand" "")
5010 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
5011 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
5012 {
5013 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
5014 DONE;
5015 })
5017 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
5018 ;; hardware division. This is only done before register allocation and with
5019 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
5020 (define_split
5021 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
5022 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
5023 (match_operand 2 "gpc_reg_operand" "")))]
5024 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
5025 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
5026 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
5027 [(const_int 0)]
5028 {
5029 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
5030 DONE;
5031 })
5033 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
5034 ;; appropriate fixup.
5035 (define_expand "rsqrt<mode>2"
5036 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
5037 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
5038 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5039 {
5040 rs6000_emit_swrsqrt (operands[0], operands[1]);
5041 DONE;
5042 })
5043 \f
5044 (define_split
5045 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5046 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5047 (match_operand:SI 2 "reg_or_cint_operand" ""))
5048 (const_int 0)))
5049 (set (match_operand:SI 0 "gpc_reg_operand" "")
5050 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5051 "reload_completed"
5052 [(set (match_dup 0)
5053 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5054 (set (match_dup 3)
5055 (compare:CC (match_dup 0)
5056 (const_int 0)))]
5057 "")
5059 \f
5060 ;; Floating-point insns, excluding normal data motion. We combine the SF/DF
5061 ;; modes here, and also add in conditional vsx/power8-vector support to access
5062 ;; values in the traditional Altivec registers if the appropriate
5063 ;; -mupper-regs-{df,sf} option is enabled.
5065 (define_expand "abs<mode>2"
5066 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5067 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5068 "TARGET_<MODE>_INSN"
5069 "")
5071 (define_insn "*abs<mode>2_fpr"
5072 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5073 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5074 "TARGET_<MODE>_FPR"
5075 "@
5076 fabs %0,%1
5077 xsabsdp %x0,%x1"
5078 [(set_attr "type" "fp")
5079 (set_attr "fp_type" "fp_addsub_<Fs>")])
5081 (define_insn "*nabs<mode>2_fpr"
5082 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5083 (neg:SFDF
5084 (abs:SFDF
5085 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
5086 "TARGET_<MODE>_FPR"
5087 "@
5088 fnabs %0,%1
5089 xsnabsdp %x0,%x1"
5090 [(set_attr "type" "fp")
5091 (set_attr "fp_type" "fp_addsub_<Fs>")])
5093 (define_expand "neg<mode>2"
5094 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5095 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5096 "TARGET_<MODE>_INSN"
5097 "")
5099 (define_insn "*neg<mode>2_fpr"
5100 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5101 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5102 "TARGET_<MODE>_FPR"
5103 "@
5104 fneg %0,%1
5105 xsnegdp %x0,%x1"
5106 [(set_attr "type" "fp")
5107 (set_attr "fp_type" "fp_addsub_<Fs>")])
5109 (define_expand "add<mode>3"
5110 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5111 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5112 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5113 "TARGET_<MODE>_INSN"
5114 "")
5116 (define_insn "*add<mode>3_fpr"
5117 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5118 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5119 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5120 "TARGET_<MODE>_FPR"
5121 "@
5122 fadd<Ftrad> %0,%1,%2
5123 xsadd<Fvsx> %x0,%x1,%x2"
5124 [(set_attr "type" "fp")
5125 (set_attr "fp_type" "fp_addsub_<Fs>")])
5127 (define_expand "sub<mode>3"
5128 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5129 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5130 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5131 "TARGET_<MODE>_INSN"
5132 "")
5134 (define_insn "*sub<mode>3_fpr"
5135 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5136 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5137 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5138 "TARGET_<MODE>_FPR"
5139 "@
5140 fsub<Ftrad> %0,%1,%2
5141 xssub<Fvsx> %x0,%x1,%x2"
5142 [(set_attr "type" "fp")
5143 (set_attr "fp_type" "fp_addsub_<Fs>")])
5145 (define_expand "mul<mode>3"
5146 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5147 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5148 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5149 "TARGET_<MODE>_INSN"
5150 "")
5152 (define_insn "*mul<mode>3_fpr"
5153 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5154 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5155 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5156 "TARGET_<MODE>_FPR"
5157 "@
5158 fmul<Ftrad> %0,%1,%2
5159 xsmul<Fvsx> %x0,%x1,%x2"
5160 [(set_attr "type" "dmul")
5161 (set_attr "fp_type" "fp_mul_<Fs>")])
5163 (define_expand "div<mode>3"
5164 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5165 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")
5166 (match_operand:SFDF 2 "gpc_reg_operand" "")))]
5167 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU"
5168 "")
5170 (define_insn "*div<mode>3_fpr"
5171 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5172 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5173 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5174 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
5175 "@
5176 fdiv<Ftrad> %0,%1,%2
5177 xsdiv<Fvsx> %x0,%x1,%x2"
5178 [(set_attr "type" "<Fs>div")
5179 (set_attr "fp_type" "fp_div_<Fs>")])
5181 (define_insn "sqrt<mode>2"
5182 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5183 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
5184 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
5185 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
5186 "@
5187 fsqrt<Ftrad> %0,%1
5188 xssqrt<Fvsx> %x0,%x1"
5189 [(set_attr "type" "<Fs>sqrt")
5190 (set_attr "fp_type" "fp_sqrt_<Fs>")])
5192 ;; Floating point reciprocal approximation
5193 (define_insn "fre<Fs>"
5194 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5195 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5196 UNSPEC_FRES))]
5197 "TARGET_<FFRE>"
5198 "@
5199 fre<Ftrad> %0,%1
5200 xsre<Fvsx> %x0,%x1"
5201 [(set_attr "type" "fp")])
5203 (define_insn "*rsqrt<mode>2"
5204 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5205 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
5206 UNSPEC_RSQRT))]
5207 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
5208 "@
5209 frsqrte<Ftrad> %0,%1
5210 xsrsqrte<Fvsx> %x0,%x1"
5211 [(set_attr "type" "fp")])
5213 ;; Floating point comparisons
5214 (define_insn "*cmp<mode>_fpr"
5215 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
5216 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5217 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5218 "TARGET_<MODE>_FPR"
5219 "@
5220 fcmpu %0,%1,%2
5221 xscmpudp %0,%x1,%x2"
5222 [(set_attr "type" "fpcompare")])
5224 ;; Floating point conversions
5225 (define_expand "extendsfdf2"
5226 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5227 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5228 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5229 "")
5231 (define_insn_and_split "*extendsfdf2_fpr"
5232 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv")
5233 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))]
5234 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5235 "@
5236 #
5237 fmr %0,%1
5238 lfs%U1%X1 %0,%1
5239 #
5240 xxlor %x0,%x1,%x1
5241 lxsspx %x0,%y1"
5242 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5243 [(const_int 0)]
5244 {
5245 emit_note (NOTE_INSN_DELETED);
5246 DONE;
5247 }
5248 [(set_attr_alternative "type"
5249 [(const_string "fp")
5250 (const_string "fp")
5251 (if_then_else
5252 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
5253 (const_string "fpload_ux")
5254 (if_then_else
5255 (match_test "update_address_mem (operands[1], VOIDmode)")
5256 (const_string "fpload_u")
5257 (const_string "fpload")))
5258 (const_string "fp")
5259 (const_string "vecsimple")
5260 (if_then_else
5261 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
5262 (const_string "fpload_ux")
5263 (if_then_else
5264 (match_test "update_address_mem (operands[1], VOIDmode)")
5265 (const_string "fpload_u")
5266 (const_string "fpload")))])])
5268 (define_expand "truncdfsf2"
5269 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5270 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5271 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5272 "")
5274 (define_insn "*truncdfsf2_fpr"
5275 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5276 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5277 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5278 "frsp %0,%1"
5279 [(set_attr "type" "fp")])
5281 ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
5282 ;; builtins.c and optabs.c that are not correct for IBM long double
5283 ;; when little-endian.
5284 (define_expand "signbittf2"
5285 [(set (match_dup 2)
5286 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))
5287 (set (match_dup 3)
5288 (subreg:DI (match_dup 2) 0))
5289 (set (match_dup 4)
5290 (match_dup 5))
5291 (set (match_operand:SI 0 "gpc_reg_operand" "")
5292 (match_dup 6))]
5293 "!TARGET_IEEEQUAD
5294 && TARGET_HARD_FLOAT
5295 && (TARGET_FPRS || TARGET_E500_DOUBLE)
5296 && TARGET_LONG_DOUBLE_128"
5297 {
5298 operands[2] = gen_reg_rtx (DFmode);
5299 operands[3] = gen_reg_rtx (DImode);
5300 if (TARGET_POWERPC64)
5301 {
5302 operands[4] = gen_reg_rtx (DImode);
5303 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63));
5304 operands[6] = gen_rtx_SUBREG (SImode, operands[4],
5305 WORDS_BIG_ENDIAN ? 4 : 0);
5306 }
5307 else
5308 {
5309 operands[4] = gen_reg_rtx (SImode);
5310 operands[5] = gen_rtx_SUBREG (SImode, operands[3],
5311 WORDS_BIG_ENDIAN ? 0 : 4);
5312 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31));
5313 }
5314 })
5316 (define_expand "copysign<mode>3"
5317 [(set (match_dup 3)
5318 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5319 (set (match_dup 4)
5320 (neg:SFDF (abs:SFDF (match_dup 1))))
5321 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5322 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5323 (match_dup 5))
5324 (match_dup 3)
5325 (match_dup 4)))]
5326 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5327 && ((TARGET_PPC_GFXOPT
5328 && !HONOR_NANS (<MODE>mode)
5329 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5330 || TARGET_CMPB
5331 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5332 {
5333 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5334 {
5335 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5336 operands[2]));
5337 DONE;
5338 }
5340 operands[3] = gen_reg_rtx (<MODE>mode);
5341 operands[4] = gen_reg_rtx (<MODE>mode);
5342 operands[5] = CONST0_RTX (<MODE>mode);
5343 })
5345 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5346 ;; compiler from optimizing -0.0
5347 (define_insn "copysign<mode>3_fcpsgn"
5348 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5349 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
5350 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
5351 UNSPEC_COPYSIGN))]
5352 "TARGET_<MODE>_FPR && TARGET_CMPB"
5353 "@
5354 fcpsgn %0,%2,%1
5355 xscpsgn<Fvsx> %x0,%x2,%x1"
5356 [(set_attr "type" "fp")])
5358 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5359 ;; fsel instruction and some auxiliary computations. Then we just have a
5360 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5361 ;; combine.
5362 ;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we
5363 ;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary
5364 ;; computations. Then we just have a single DEFINE_INSN for fsel and the
5365 ;; define_splits to make them if made by combine. On VSX machines we have the
5366 ;; min/max instructions.
5367 ;;
5368 ;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector
5369 ;; to allow either DF/SF to use only traditional registers.
5371 (define_expand "smax<mode>3"
5372 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5373 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5374 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5375 (match_dup 1)
5376 (match_dup 2)))]
5377 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5378 {
5379 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
5380 DONE;
5381 })
5383 (define_insn "*smax<mode>3_vsx"
5384 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5385 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5386 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5387 "TARGET_<MODE>_FPR && TARGET_VSX"
5388 "xsmaxdp %x0,%x1,%x2"
5389 [(set_attr "type" "fp")])
5391 (define_expand "smin<mode>3"
5392 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5393 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "")
5394 (match_operand:SFDF 2 "gpc_reg_operand" ""))
5395 (match_dup 2)
5396 (match_dup 1)))]
5397 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math"
5398 {
5399 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
5400 DONE;
5401 })
5403 (define_insn "*smin<mode>3_vsx"
5404 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
5405 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
5406 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
5407 "TARGET_<MODE>_FPR && TARGET_VSX"
5408 "xsmindp %x0,%x1,%x2"
5409 [(set_attr "type" "fp")])
5411 (define_split
5412 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
5413 (match_operator:SFDF 3 "min_max_operator"
5414 [(match_operand:SFDF 1 "gpc_reg_operand" "")
5415 (match_operand:SFDF 2 "gpc_reg_operand" "")]))]
5416 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math
5417 && !TARGET_VSX"
5418 [(const_int 0)]
5419 {
5420 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1],
5421 operands[2]);
5422 DONE;
5423 })
5425 (define_split
5426 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5427 (match_operator:SF 3 "min_max_operator"
5428 [(match_operand:SF 1 "gpc_reg_operand" "")
5429 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5430 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5431 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5432 [(const_int 0)]
5433 "
5434 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5435 operands[1], operands[2]);
5436 DONE;
5437 }")
5439 (define_expand "mov<mode>cc"
5440 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5441 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5442 (match_operand:GPR 2 "gpc_reg_operand" "")
5443 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5444 "TARGET_ISEL<sel>"
5445 "
5446 {
5447 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5448 DONE;
5449 else
5450 FAIL;
5451 }")
5453 ;; We use the BASE_REGS for the isel input operands because, if rA is
5454 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5455 ;; because we may switch the operands and rB may end up being rA.
5456 ;;
5457 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5458 ;; leave out the mode in operand 4 and use one pattern, but reload can
5459 ;; change the mode underneath our feet and then gets confused trying
5460 ;; to reload the value.
5461 (define_insn "isel_signed_<mode>"
5462 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5463 (if_then_else:GPR
5464 (match_operator 1 "scc_comparison_operator"
5465 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5466 (const_int 0)])
5467 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5468 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5469 "TARGET_ISEL<sel>"
5470 "*
5471 { return output_isel (operands); }"
5472 [(set_attr "type" "isel")
5473 (set_attr "length" "4")])
5475 (define_insn "isel_unsigned_<mode>"
5476 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5477 (if_then_else:GPR
5478 (match_operator 1 "scc_comparison_operator"
5479 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5480 (const_int 0)])
5481 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5482 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5483 "TARGET_ISEL<sel>"
5484 "*
5485 { return output_isel (operands); }"
5486 [(set_attr "type" "isel")
5487 (set_attr "length" "4")])
5489 ;; These patterns can be useful for combine; they let combine know that
5490 ;; isel can handle reversed comparisons so long as the operands are
5491 ;; registers.
5493 (define_insn "*isel_reversed_signed_<mode>"
5494 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5495 (if_then_else:GPR
5496 (match_operator 1 "scc_rev_comparison_operator"
5497 [(match_operand:CC 4 "cc_reg_operand" "y")
5498 (const_int 0)])
5499 (match_operand:GPR 2 "gpc_reg_operand" "b")
5500 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5501 "TARGET_ISEL<sel>"
5502 "*
5503 { return output_isel (operands); }"
5504 [(set_attr "type" "isel")
5505 (set_attr "length" "4")])
5507 (define_insn "*isel_reversed_unsigned_<mode>"
5508 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5509 (if_then_else:GPR
5510 (match_operator 1 "scc_rev_comparison_operator"
5511 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5512 (const_int 0)])
5513 (match_operand:GPR 2 "gpc_reg_operand" "b")
5514 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5515 "TARGET_ISEL<sel>"
5516 "*
5517 { return output_isel (operands); }"
5518 [(set_attr "type" "isel")
5519 (set_attr "length" "4")])
5521 (define_expand "movsfcc"
5522 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5523 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5524 (match_operand:SF 2 "gpc_reg_operand" "")
5525 (match_operand:SF 3 "gpc_reg_operand" "")))]
5526 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5527 "
5528 {
5529 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5530 DONE;
5531 else
5532 FAIL;
5533 }")
5535 (define_insn "*fselsfsf4"
5536 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5537 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5538 (match_operand:SF 4 "zero_fp_constant" "F"))
5539 (match_operand:SF 2 "gpc_reg_operand" "f")
5540 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5541 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5542 "fsel %0,%1,%2,%3"
5543 [(set_attr "type" "fp")])
5545 (define_insn "*fseldfsf4"
5546 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5547 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5548 (match_operand:DF 4 "zero_fp_constant" "F"))
5549 (match_operand:SF 2 "gpc_reg_operand" "f")
5550 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5551 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5552 "fsel %0,%1,%2,%3"
5553 [(set_attr "type" "fp")])
5555 ;; The conditional move instructions allow us to perform max and min
5556 ;; operations even when
5558 (define_split
5559 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5560 (match_operator:DF 3 "min_max_operator"
5561 [(match_operand:DF 1 "gpc_reg_operand" "")
5562 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5563 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5564 && !flag_trapping_math"
5565 [(const_int 0)]
5566 "
5567 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5568 operands[1], operands[2]);
5569 DONE;
5570 }")
5572 (define_expand "movdfcc"
5573 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5574 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5575 (match_operand:DF 2 "gpc_reg_operand" "")
5576 (match_operand:DF 3 "gpc_reg_operand" "")))]
5577 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5578 "
5579 {
5580 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5581 DONE;
5582 else
5583 FAIL;
5584 }")
5586 (define_insn "*fseldfdf4"
5587 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5588 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5589 (match_operand:DF 4 "zero_fp_constant" "F"))
5590 (match_operand:DF 2 "gpc_reg_operand" "d")
5591 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5592 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5593 "fsel %0,%1,%2,%3"
5594 [(set_attr "type" "fp")])
5596 (define_insn "*fselsfdf4"
5597 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5598 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5599 (match_operand:SF 4 "zero_fp_constant" "F"))
5600 (match_operand:DF 2 "gpc_reg_operand" "d")
5601 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5602 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5603 "fsel %0,%1,%2,%3"
5604 [(set_attr "type" "fp")])
5605 \f
5606 ;; Conversions to and from floating-point.
5608 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5609 ; don't want to support putting SImode in FPR registers.
5610 (define_insn "lfiwax"
5611 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5612 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5613 UNSPEC_LFIWAX))]
5614 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5615 "@
5616 lfiwax %0,%y1
5617 lxsiwax %x0,%y1
5618 mtvsrwa %x0,%1"
5619 [(set_attr "type" "fpload,fpload,mffgpr")])
5621 ; This split must be run before register allocation because it allocates the
5622 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5623 ; it earlier to allow for the combiner to merge insns together where it might
5624 ; not be needed and also in case the insns are deleted as dead code.
5626 (define_insn_and_split "floatsi<mode>2_lfiwax"
5627 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5628 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5629 (clobber (match_scratch:DI 2 "=d"))]
5630 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5631 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5632 "#"
5633 ""
5634 [(pc)]
5635 "
5636 {
5637 rtx dest = operands[0];
5638 rtx src = operands[1];
5639 rtx tmp;
5641 if (!MEM_P (src) && TARGET_POWERPC64
5642 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5643 tmp = convert_to_mode (DImode, src, false);
5644 else
5645 {
5646 tmp = operands[2];
5647 if (GET_CODE (tmp) == SCRATCH)
5648 tmp = gen_reg_rtx (DImode);
5649 if (MEM_P (src))
5650 {
5651 src = rs6000_address_for_fpconvert (src);
5652 emit_insn (gen_lfiwax (tmp, src));
5653 }
5654 else
5655 {
5656 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5657 emit_move_insn (stack, src);
5658 emit_insn (gen_lfiwax (tmp, stack));
5659 }
5660 }
5661 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5662 DONE;
5663 }"
5664 [(set_attr "length" "12")
5665 (set_attr "type" "fpload")])
5667 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5668 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5669 (float:SFDF
5670 (sign_extend:DI
5671 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5672 (clobber (match_scratch:DI 2 "=0,d"))]
5673 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5674 && <SI_CONVERT_FP>"
5675 "#"
5676 ""
5677 [(pc)]
5678 "
5679 {
5680 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5681 if (GET_CODE (operands[2]) == SCRATCH)
5682 operands[2] = gen_reg_rtx (DImode);
5683 emit_insn (gen_lfiwax (operands[2], operands[1]));
5684 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5685 DONE;
5686 }"
5687 [(set_attr "length" "8")
5688 (set_attr "type" "fpload")])
5690 (define_insn "lfiwzx"
5691 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm")
5692 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")]
5693 UNSPEC_LFIWZX))]
5694 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5695 "@
5696 lfiwzx %0,%y1
5697 lxsiwzx %x0,%y1
5698 mtvsrwz %x0,%1"
5699 [(set_attr "type" "fpload,fpload,mftgpr")])
5701 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5702 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5703 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5704 (clobber (match_scratch:DI 2 "=d"))]
5705 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5706 && <SI_CONVERT_FP>"
5707 "#"
5708 ""
5709 [(pc)]
5710 "
5711 {
5712 rtx dest = operands[0];
5713 rtx src = operands[1];
5714 rtx tmp;
5716 if (!MEM_P (src) && TARGET_POWERPC64
5717 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
5718 tmp = convert_to_mode (DImode, src, true);
5719 else
5720 {
5721 tmp = operands[2];
5722 if (GET_CODE (tmp) == SCRATCH)
5723 tmp = gen_reg_rtx (DImode);
5724 if (MEM_P (src))
5725 {
5726 src = rs6000_address_for_fpconvert (src);
5727 emit_insn (gen_lfiwzx (tmp, src));
5728 }
5729 else
5730 {
5731 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5732 emit_move_insn (stack, src);
5733 emit_insn (gen_lfiwzx (tmp, stack));
5734 }
5735 }
5736 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5737 DONE;
5738 }"
5739 [(set_attr "length" "12")
5740 (set_attr "type" "fpload")])
5742 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5743 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5744 (unsigned_float:SFDF
5745 (zero_extend:DI
5746 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5747 (clobber (match_scratch:DI 2 "=0,d"))]
5748 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5749 && <SI_CONVERT_FP>"
5750 "#"
5751 ""
5752 [(pc)]
5753 "
5754 {
5755 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5756 if (GET_CODE (operands[2]) == SCRATCH)
5757 operands[2] = gen_reg_rtx (DImode);
5758 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5759 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5760 DONE;
5761 }"
5762 [(set_attr "length" "8")
5763 (set_attr "type" "fpload")])
5765 ; For each of these conversions, there is a define_expand, a define_insn
5766 ; with a '#' template, and a define_split (with C code). The idea is
5767 ; to allow constant folding with the template of the define_insn,
5768 ; then to have the insns split later (between sched1 and final).
5770 (define_expand "floatsidf2"
5771 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5772 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5773 (use (match_dup 2))
5774 (use (match_dup 3))
5775 (clobber (match_dup 4))
5776 (clobber (match_dup 5))
5777 (clobber (match_dup 6))])]
5778 "TARGET_HARD_FLOAT
5779 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5780 "
5781 {
5782 if (TARGET_E500_DOUBLE)
5783 {
5784 if (!REG_P (operands[1]))
5785 operands[1] = force_reg (SImode, operands[1]);
5786 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5787 DONE;
5788 }
5789 else if (TARGET_LFIWAX && TARGET_FCFID)
5790 {
5791 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5792 DONE;
5793 }
5794 else if (TARGET_FCFID)
5795 {
5796 rtx dreg = operands[1];
5797 if (!REG_P (dreg))
5798 dreg = force_reg (SImode, dreg);
5799 dreg = convert_to_mode (DImode, dreg, false);
5800 emit_insn (gen_floatdidf2 (operands[0], dreg));
5801 DONE;
5802 }
5804 if (!REG_P (operands[1]))
5805 operands[1] = force_reg (SImode, operands[1]);
5806 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5807 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5808 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5809 operands[5] = gen_reg_rtx (DFmode);
5810 operands[6] = gen_reg_rtx (SImode);
5811 }")
5813 (define_insn_and_split "*floatsidf2_internal"
5814 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5815 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5816 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5817 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5818 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5819 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5820 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5821 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5822 "#"
5823 ""
5824 [(pc)]
5825 "
5826 {
5827 rtx lowword, highword;
5828 gcc_assert (MEM_P (operands[4]));
5829 highword = adjust_address (operands[4], SImode, 0);
5830 lowword = adjust_address (operands[4], SImode, 4);
5831 if (! WORDS_BIG_ENDIAN)
5832 {
5833 rtx tmp;
5834 tmp = highword; highword = lowword; lowword = tmp;
5835 }
5837 emit_insn (gen_xorsi3 (operands[6], operands[1],
5838 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5839 emit_move_insn (lowword, operands[6]);
5840 emit_move_insn (highword, operands[2]);
5841 emit_move_insn (operands[5], operands[4]);
5842 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5843 DONE;
5844 }"
5845 [(set_attr "length" "24")
5846 (set_attr "type" "fp")])
5848 ;; If we don't have a direct conversion to single precision, don't enable this
5849 ;; conversion for 32-bit without fast math, because we don't have the insn to
5850 ;; generate the fixup swizzle to avoid double rounding problems.
5851 (define_expand "floatunssisf2"
5852 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5853 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5854 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5855 && (!TARGET_FPRS
5856 || (TARGET_FPRS
5857 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5858 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5859 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5860 "
5861 {
5862 if (!TARGET_FPRS)
5863 {
5864 if (!REG_P (operands[1]))
5865 operands[1] = force_reg (SImode, operands[1]);
5866 }
5867 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5868 {
5869 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5870 DONE;
5871 }
5872 else
5873 {
5874 rtx dreg = operands[1];
5875 if (!REG_P (dreg))
5876 dreg = force_reg (SImode, dreg);
5877 dreg = convert_to_mode (DImode, dreg, true);
5878 emit_insn (gen_floatdisf2 (operands[0], dreg));
5879 DONE;
5880 }
5881 }")
5883 (define_expand "floatunssidf2"
5884 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5885 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5886 (use (match_dup 2))
5887 (use (match_dup 3))
5888 (clobber (match_dup 4))
5889 (clobber (match_dup 5))])]
5890 "TARGET_HARD_FLOAT
5891 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5892 "
5893 {
5894 if (TARGET_E500_DOUBLE)
5895 {
5896 if (!REG_P (operands[1]))
5897 operands[1] = force_reg (SImode, operands[1]);
5898 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5899 DONE;
5900 }
5901 else if (TARGET_LFIWZX && TARGET_FCFID)
5902 {
5903 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5904 DONE;
5905 }
5906 else if (TARGET_FCFID)
5907 {
5908 rtx dreg = operands[1];
5909 if (!REG_P (dreg))
5910 dreg = force_reg (SImode, dreg);
5911 dreg = convert_to_mode (DImode, dreg, true);
5912 emit_insn (gen_floatdidf2 (operands[0], dreg));
5913 DONE;
5914 }
5916 if (!REG_P (operands[1]))
5917 operands[1] = force_reg (SImode, operands[1]);
5918 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5919 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5920 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5921 operands[5] = gen_reg_rtx (DFmode);
5922 }")
5924 (define_insn_and_split "*floatunssidf2_internal"
5925 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5926 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5927 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5928 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5929 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5930 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5931 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5932 && !(TARGET_FCFID && TARGET_POWERPC64)"
5933 "#"
5934 ""
5935 [(pc)]
5936 "
5937 {
5938 rtx lowword, highword;
5939 gcc_assert (MEM_P (operands[4]));
5940 highword = adjust_address (operands[4], SImode, 0);
5941 lowword = adjust_address (operands[4], SImode, 4);
5942 if (! WORDS_BIG_ENDIAN)
5943 {
5944 rtx tmp;
5945 tmp = highword; highword = lowword; lowword = tmp;
5946 }
5948 emit_move_insn (lowword, operands[1]);
5949 emit_move_insn (highword, operands[2]);
5950 emit_move_insn (operands[5], operands[4]);
5951 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5952 DONE;
5953 }"
5954 [(set_attr "length" "20")
5955 (set_attr "type" "fp")])
5957 (define_expand "fix_trunc<mode>si2"
5958 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5959 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5960 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5961 "
5962 {
5963 if (!<E500_CONVERT>)
5964 {
5965 rtx tmp, stack;
5967 if (TARGET_STFIWX)
5968 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5969 else
5970 {
5971 tmp = gen_reg_rtx (DImode);
5972 stack = rs6000_allocate_stack_temp (DImode, true, false);
5973 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5974 tmp, stack));
5975 }
5976 DONE;
5977 }
5978 }")
5980 ; Like the convert to float patterns, this insn must be split before
5981 ; register allocation so that it can allocate the memory slot if it
5982 ; needed
5983 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5984 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5985 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5986 (clobber (match_scratch:DI 2 "=d"))]
5987 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5988 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5989 && TARGET_STFIWX && can_create_pseudo_p ()"
5990 "#"
5991 ""
5992 [(pc)]
5993 {
5994 rtx dest = operands[0];
5995 rtx src = operands[1];
5996 rtx tmp = operands[2];
5998 if (GET_CODE (tmp) == SCRATCH)
5999 tmp = gen_reg_rtx (DImode);
6001 emit_insn (gen_fctiwz_<mode> (tmp, src));
6002 if (MEM_P (dest))
6003 {
6004 dest = rs6000_address_for_fpconvert (dest);
6005 emit_insn (gen_stfiwx (dest, tmp));
6006 DONE;
6007 }
6008 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6009 {
6010 dest = gen_lowpart (DImode, dest);
6011 emit_move_insn (dest, tmp);
6012 DONE;
6013 }
6014 else
6015 {
6016 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6017 emit_insn (gen_stfiwx (stack, tmp));
6018 emit_move_insn (dest, stack);
6019 DONE;
6020 }
6021 }
6022 [(set_attr "length" "12")
6023 (set_attr "type" "fp")])
6025 (define_insn_and_split "fix_trunc<mode>si2_internal"
6026 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
6027 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
6028 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
6029 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
6030 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6031 "#"
6032 ""
6033 [(pc)]
6034 "
6035 {
6036 rtx lowword;
6037 gcc_assert (MEM_P (operands[3]));
6038 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6040 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
6041 emit_move_insn (operands[3], operands[2]);
6042 emit_move_insn (operands[0], lowword);
6043 DONE;
6044 }"
6045 [(set_attr "length" "16")
6046 (set_attr "type" "fp")])
6048 (define_expand "fix_trunc<mode>di2"
6049 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6050 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6051 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6052 && TARGET_FCFID"
6053 "")
6055 (define_insn "*fix_trunc<mode>di2_fctidz"
6056 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6057 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6058 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6059 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6060 "fctidz %0,%1"
6061 [(set_attr "type" "fp")])
6063 (define_expand "fixuns_trunc<mode>si2"
6064 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6065 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6066 "TARGET_HARD_FLOAT
6067 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6068 || <E500_CONVERT>)"
6069 "
6070 {
6071 if (!<E500_CONVERT>)
6072 {
6073 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6074 DONE;
6075 }
6076 }")
6078 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6079 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6080 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6081 (clobber (match_scratch:DI 2 "=d"))]
6082 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6083 && TARGET_STFIWX && can_create_pseudo_p ()"
6084 "#"
6085 ""
6086 [(pc)]
6087 {
6088 rtx dest = operands[0];
6089 rtx src = operands[1];
6090 rtx tmp = operands[2];
6092 if (GET_CODE (tmp) == SCRATCH)
6093 tmp = gen_reg_rtx (DImode);
6095 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6096 if (MEM_P (dest))
6097 {
6098 dest = rs6000_address_for_fpconvert (dest);
6099 emit_insn (gen_stfiwx (dest, tmp));
6100 DONE;
6101 }
6102 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE))
6103 {
6104 dest = gen_lowpart (DImode, dest);
6105 emit_move_insn (dest, tmp);
6106 DONE;
6107 }
6108 else
6109 {
6110 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6111 emit_insn (gen_stfiwx (stack, tmp));
6112 emit_move_insn (dest, stack);
6113 DONE;
6114 }
6115 }
6116 [(set_attr "length" "12")
6117 (set_attr "type" "fp")])
6119 (define_expand "fixuns_trunc<mode>di2"
6120 [(set (match_operand:DI 0 "register_operand" "")
6121 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6122 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6123 "")
6125 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6126 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6127 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6128 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6129 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6130 "fctiduz %0,%1"
6131 [(set_attr "type" "fp")])
6133 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6134 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6135 ; because the first makes it clear that operand 0 is not live
6136 ; before the instruction.
6137 (define_insn "fctiwz_<mode>"
6138 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6139 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6140 UNSPEC_FCTIWZ))]
6141 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6142 "fctiwz %0,%1"
6143 [(set_attr "type" "fp")])
6145 (define_insn "fctiwuz_<mode>"
6146 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6147 (unspec:DI [(unsigned_fix:SI
6148 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6149 UNSPEC_FCTIWUZ))]
6150 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6151 "fctiwuz %0,%1"
6152 [(set_attr "type" "fp")])
6154 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6155 ;; since the friz instruction does not truncate the value if the floating
6156 ;; point value is < LONG_MIN or > LONG_MAX.
6157 (define_insn "*friz"
6158 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6159 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6160 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6161 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6162 && !flag_trapping_math && TARGET_FRIZ"
6163 "friz %0,%1"
6164 [(set_attr "type" "fp")])
6166 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6167 ;; load to properly sign extend the value, but at least doing a store, load
6168 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6169 ;; if we have 32-bit memory ops
6170 (define_insn_and_split "*round32<mode>2_fprs"
6171 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6172 (float:SFDF
6173 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6174 (clobber (match_scratch:DI 2 "=d"))
6175 (clobber (match_scratch:DI 3 "=d"))]
6176 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6177 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6178 && can_create_pseudo_p ()"
6179 "#"
6180 ""
6181 [(pc)]
6182 {
6183 rtx dest = operands[0];
6184 rtx src = operands[1];
6185 rtx tmp1 = operands[2];
6186 rtx tmp2 = operands[3];
6187 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6189 if (GET_CODE (tmp1) == SCRATCH)
6190 tmp1 = gen_reg_rtx (DImode);
6191 if (GET_CODE (tmp2) == SCRATCH)
6192 tmp2 = gen_reg_rtx (DImode);
6194 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6195 emit_insn (gen_stfiwx (stack, tmp1));
6196 emit_insn (gen_lfiwax (tmp2, stack));
6197 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6198 DONE;
6199 }
6200 [(set_attr "type" "fpload")
6201 (set_attr "length" "16")])
6203 (define_insn_and_split "*roundu32<mode>2_fprs"
6204 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6205 (unsigned_float:SFDF
6206 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6207 (clobber (match_scratch:DI 2 "=d"))
6208 (clobber (match_scratch:DI 3 "=d"))]
6209 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6210 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6211 && can_create_pseudo_p ()"
6212 "#"
6213 ""
6214 [(pc)]
6215 {
6216 rtx dest = operands[0];
6217 rtx src = operands[1];
6218 rtx tmp1 = operands[2];
6219 rtx tmp2 = operands[3];
6220 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6222 if (GET_CODE (tmp1) == SCRATCH)
6223 tmp1 = gen_reg_rtx (DImode);
6224 if (GET_CODE (tmp2) == SCRATCH)
6225 tmp2 = gen_reg_rtx (DImode);
6227 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6228 emit_insn (gen_stfiwx (stack, tmp1));
6229 emit_insn (gen_lfiwzx (tmp2, stack));
6230 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6231 DONE;
6232 }
6233 [(set_attr "type" "fpload")
6234 (set_attr "length" "16")])
6236 ;; No VSX equivalent to fctid
6237 (define_insn "lrint<mode>di2"
6238 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6239 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6240 UNSPEC_FCTID))]
6241 "TARGET_<MODE>_FPR && TARGET_FPRND"
6242 "fctid %0,%1"
6243 [(set_attr "type" "fp")])
6245 (define_insn "btrunc<mode>2"
6246 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6247 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6248 UNSPEC_FRIZ))]
6249 "TARGET_<MODE>_FPR && TARGET_FPRND"
6250 "@
6251 friz %0,%1
6252 xsrdpiz %x0,%x1"
6253 [(set_attr "type" "fp")
6254 (set_attr "fp_type" "fp_addsub_<Fs>")])
6256 (define_insn "ceil<mode>2"
6257 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6258 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6259 UNSPEC_FRIP))]
6260 "TARGET_<MODE>_FPR && TARGET_FPRND"
6261 "@
6262 frip %0,%1
6263 xsrdpip %x0,%x1"
6264 [(set_attr "type" "fp")
6265 (set_attr "fp_type" "fp_addsub_<Fs>")])
6267 (define_insn "floor<mode>2"
6268 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
6269 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
6270 UNSPEC_FRIM))]
6271 "TARGET_<MODE>_FPR && TARGET_FPRND"
6272 "@
6273 frim %0,%1
6274 xsrdpim %x0,%x1"
6275 [(set_attr "type" "fp")
6276 (set_attr "fp_type" "fp_addsub_<Fs>")])
6278 ;; No VSX equivalent to frin
6279 (define_insn "round<mode>2"
6280 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6281 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6282 UNSPEC_FRIN))]
6283 "TARGET_<MODE>_FPR && TARGET_FPRND"
6284 "frin %0,%1"
6285 [(set_attr "type" "fp")
6286 (set_attr "fp_type" "fp_addsub_<Fs>")])
6288 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6289 (define_insn "stfiwx"
6290 [(set (match_operand:SI 0 "memory_operand" "=Z")
6291 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6292 UNSPEC_STFIWX))]
6293 "TARGET_PPC_GFXOPT"
6294 "stfiwx %1,%y0"
6295 [(set_attr "type" "fpstore")])
6297 ;; If we don't have a direct conversion to single precision, don't enable this
6298 ;; conversion for 32-bit without fast math, because we don't have the insn to
6299 ;; generate the fixup swizzle to avoid double rounding problems.
6300 (define_expand "floatsisf2"
6301 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6302 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6303 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6304 && (!TARGET_FPRS
6305 || (TARGET_FPRS
6306 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6307 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6308 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6309 "
6310 {
6311 if (!TARGET_FPRS)
6312 {
6313 if (!REG_P (operands[1]))
6314 operands[1] = force_reg (SImode, operands[1]);
6315 }
6316 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6317 {
6318 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6319 DONE;
6320 }
6321 else if (TARGET_FCFID && TARGET_LFIWAX)
6322 {
6323 rtx dfreg = gen_reg_rtx (DFmode);
6324 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6325 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6326 DONE;
6327 }
6328 else
6329 {
6330 rtx dreg = operands[1];
6331 if (!REG_P (dreg))
6332 dreg = force_reg (SImode, dreg);
6333 dreg = convert_to_mode (DImode, dreg, false);
6334 emit_insn (gen_floatdisf2 (operands[0], dreg));
6335 DONE;
6336 }
6337 }")
6339 (define_expand "floatdidf2"
6340 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6341 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6342 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6343 "")
6345 (define_insn "*floatdidf2_fpr"
6346 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6347 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6348 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6349 && !VECTOR_UNIT_VSX_P (DFmode)"
6350 "fcfid %0,%1"
6351 [(set_attr "type" "fp")])
6353 ; Allow the combiner to merge source memory operands to the conversion so that
6354 ; the optimizer/register allocator doesn't try to load the value too early in a
6355 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6356 ; hit. We will split after reload to avoid the trip through the GPRs
6358 (define_insn_and_split "*floatdidf2_mem"
6359 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6360 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6361 (clobber (match_scratch:DI 2 "=d"))]
6362 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6363 "#"
6364 "&& reload_completed"
6365 [(set (match_dup 2) (match_dup 1))
6366 (set (match_dup 0) (float:DF (match_dup 2)))]
6367 ""
6368 [(set_attr "length" "8")
6369 (set_attr "type" "fpload")])
6371 (define_expand "floatunsdidf2"
6372 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6373 (unsigned_float:DF
6374 (match_operand:DI 1 "gpc_reg_operand" "")))]
6375 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6376 "")
6378 (define_insn "*floatunsdidf2_fcfidu"
6379 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6380 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6381 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6382 "fcfidu %0,%1"
6383 [(set_attr "type" "fp")
6384 (set_attr "length" "4")])
6386 (define_insn_and_split "*floatunsdidf2_mem"
6387 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6388 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6389 (clobber (match_scratch:DI 2 "=d"))]
6390 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6391 "#"
6392 "&& reload_completed"
6393 [(set (match_dup 2) (match_dup 1))
6394 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6395 ""
6396 [(set_attr "length" "8")
6397 (set_attr "type" "fpload")])
6399 (define_expand "floatdisf2"
6400 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6401 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6402 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6403 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6404 "
6405 {
6406 if (!TARGET_FCFIDS)
6407 {
6408 rtx val = operands[1];
6409 if (!flag_unsafe_math_optimizations)
6410 {
6411 rtx label = gen_label_rtx ();
6412 val = gen_reg_rtx (DImode);
6413 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6414 emit_label (label);
6415 }
6416 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6417 DONE;
6418 }
6419 }")
6421 (define_insn "floatdisf2_fcfids"
6422 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6423 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6424 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6425 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6426 "fcfids %0,%1"
6427 [(set_attr "type" "fp")])
6429 (define_insn_and_split "*floatdisf2_mem"
6430 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6431 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6432 (clobber (match_scratch:DI 2 "=f"))]
6433 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6434 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6435 "#"
6436 "&& reload_completed"
6437 [(pc)]
6438 "
6439 {
6440 emit_move_insn (operands[2], operands[1]);
6441 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6442 DONE;
6443 }"
6444 [(set_attr "length" "8")])
6446 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6447 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6448 ;; from double rounding.
6449 ;; Instead of creating a new cpu type for two FP operations, just use fp
6450 (define_insn_and_split "floatdisf2_internal1"
6451 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6452 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6453 (clobber (match_scratch:DF 2 "=d"))]
6454 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6455 "#"
6456 "&& reload_completed"
6457 [(set (match_dup 2)
6458 (float:DF (match_dup 1)))
6459 (set (match_dup 0)
6460 (float_truncate:SF (match_dup 2)))]
6461 ""
6462 [(set_attr "length" "8")
6463 (set_attr "type" "fp")])
6465 ;; Twiddles bits to avoid double rounding.
6466 ;; Bits that might be truncated when converting to DFmode are replaced
6467 ;; by a bit that won't be lost at that stage, but is below the SFmode
6468 ;; rounding position.
6469 (define_expand "floatdisf2_internal2"
6470 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6471 (const_int 53)))
6472 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6473 (const_int 2047)))
6474 (clobber (scratch:CC))])
6475 (set (match_dup 3) (plus:DI (match_dup 3)
6476 (const_int 1)))
6477 (set (match_dup 0) (plus:DI (match_dup 0)
6478 (const_int 2047)))
6479 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6480 (const_int 2)))
6481 (set (match_dup 0) (ior:DI (match_dup 0)
6482 (match_dup 1)))
6483 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6484 (const_int -2048)))
6485 (clobber (scratch:CC))])
6486 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6487 (label_ref (match_operand:DI 2 "" ""))
6488 (pc)))
6489 (set (match_dup 0) (match_dup 1))]
6490 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6491 "
6492 {
6493 operands[3] = gen_reg_rtx (DImode);
6494 operands[4] = gen_reg_rtx (CCUNSmode);
6495 }")
6497 (define_expand "floatunsdisf2"
6498 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6499 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6500 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6501 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6502 "")
6504 (define_insn "floatunsdisf2_fcfidus"
6505 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6506 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6507 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6508 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6509 "fcfidus %0,%1"
6510 [(set_attr "type" "fp")])
6512 (define_insn_and_split "*floatunsdisf2_mem"
6513 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6514 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6515 (clobber (match_scratch:DI 2 "=f"))]
6516 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6517 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6518 "#"
6519 "&& reload_completed"
6520 [(pc)]
6521 "
6522 {
6523 emit_move_insn (operands[2], operands[1]);
6524 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6525 DONE;
6526 }"
6527 [(set_attr "length" "8")
6528 (set_attr "type" "fpload")])
6529 \f
6530 ;; Define the DImode operations that can be done in a small number
6531 ;; of instructions. The & constraints are to prevent the register
6532 ;; allocator from allocating registers that overlap with the inputs
6533 ;; (for example, having an input in 7,8 and an output in 6,7). We
6534 ;; also allow for the output being the same as one of the inputs.
6536 (define_insn "*adddi3_noppc64"
6537 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6538 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6539 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6540 "! TARGET_POWERPC64"
6541 "*
6542 {
6543 if (WORDS_BIG_ENDIAN)
6544 return (GET_CODE (operands[2])) != CONST_INT
6545 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\"
6546 : \"addic %L0,%L1,%2\;add%G2e %0,%1\";
6547 else
6548 return (GET_CODE (operands[2])) != CONST_INT
6549 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\"
6550 : \"addic %0,%1,%2\;add%G2e %L0,%L1\";
6551 }"
6552 [(set_attr "type" "two")
6553 (set_attr "length" "8")])
6555 (define_insn "*subdi3_noppc64"
6556 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6557 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6558 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6559 "! TARGET_POWERPC64"
6560 "*
6561 {
6562 if (WORDS_BIG_ENDIAN)
6563 return (GET_CODE (operands[1]) != CONST_INT)
6564 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\"
6565 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\";
6566 else
6567 return (GET_CODE (operands[1]) != CONST_INT)
6568 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\"
6569 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\";
6570 }"
6571 [(set_attr "type" "two")
6572 (set_attr "length" "8")])
6574 (define_insn "*negdi2_noppc64"
6575 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6576 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6577 "! TARGET_POWERPC64"
6578 "*
6579 {
6580 return (WORDS_BIG_ENDIAN)
6581 ? \"subfic %L0,%L1,0\;subfze %0,%1\"
6582 : \"subfic %0,%1,0\;subfze %L0,%L1\";
6583 }"
6584 [(set_attr "type" "two")
6585 (set_attr "length" "8")])
6587 (define_insn "mulsidi3"
6588 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6589 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6590 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6591 "! TARGET_POWERPC64"
6592 {
6593 return (WORDS_BIG_ENDIAN)
6594 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6595 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6596 }
6597 [(set_attr "type" "imul")
6598 (set_attr "length" "8")])
6600 (define_split
6601 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6602 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6603 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6604 "! TARGET_POWERPC64 && reload_completed"
6605 [(set (match_dup 3)
6606 (truncate:SI
6607 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6608 (sign_extend:DI (match_dup 2)))
6609 (const_int 32))))
6610 (set (match_dup 4)
6611 (mult:SI (match_dup 1)
6612 (match_dup 2)))]
6613 "
6614 {
6615 int endian = (WORDS_BIG_ENDIAN == 0);
6616 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6617 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6618 }")
6620 (define_insn "umulsidi3"
6621 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6622 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6623 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6624 "! TARGET_POWERPC64"
6625 "*
6626 {
6627 return (WORDS_BIG_ENDIAN)
6628 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6629 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6630 }"
6631 [(set_attr "type" "imul")
6632 (set_attr "length" "8")])
6634 (define_split
6635 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6636 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6637 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6638 "! TARGET_POWERPC64 && reload_completed"
6639 [(set (match_dup 3)
6640 (truncate:SI
6641 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6642 (zero_extend:DI (match_dup 2)))
6643 (const_int 32))))
6644 (set (match_dup 4)
6645 (mult:SI (match_dup 1)
6646 (match_dup 2)))]
6647 "
6648 {
6649 int endian = (WORDS_BIG_ENDIAN == 0);
6650 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6651 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6652 }")
6654 (define_insn "smulsi3_highpart"
6655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6656 (truncate:SI
6657 (lshiftrt:DI (mult:DI (sign_extend:DI
6658 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6659 (sign_extend:DI
6660 (match_operand:SI 2 "gpc_reg_operand" "r")))
6661 (const_int 32))))]
6662 ""
6663 "mulhw %0,%1,%2"
6664 [(set_attr "type" "imul")])
6666 (define_insn "umulsi3_highpart"
6667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6668 (truncate:SI
6669 (lshiftrt:DI (mult:DI (zero_extend:DI
6670 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6671 (zero_extend:DI
6672 (match_operand:SI 2 "gpc_reg_operand" "r")))
6673 (const_int 32))))]
6674 ""
6675 "mulhwu %0,%1,%2"
6676 [(set_attr "type" "imul")])
6678 ;; Shift by a variable amount is too complex to be worth open-coding. We
6679 ;; just handle shifts by constants.
6680 (define_insn "ashrdi3_no_power"
6681 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6682 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6683 (match_operand:SI 2 "const_int_operand" "M,i")))]
6684 "!TARGET_POWERPC64"
6685 "*
6686 {
6687 switch (which_alternative)
6688 {
6689 default:
6690 gcc_unreachable ();
6691 case 0:
6692 if (WORDS_BIG_ENDIAN)
6693 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\";
6694 else
6695 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\";
6696 case 1:
6697 if (WORDS_BIG_ENDIAN)
6698 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\";
6699 else
6700 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\";
6701 }
6702 }"
6703 [(set_attr "type" "two,three")
6704 (set_attr "length" "8,12")])
6706 (define_insn "*ashrdisi3_noppc64be"
6707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6708 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6709 (const_int 32)) 4))]
6710 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6711 "*
6712 {
6713 if (REGNO (operands[0]) == REGNO (operands[1]))
6714 return \"\";
6715 else
6716 return \"mr %0,%1\";
6717 }"
6718 [(set_attr "length" "4")])
6720 \f
6721 ;; PowerPC64 DImode operations.
6723 (define_insn "muldi3"
6724 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6725 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6726 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6727 "TARGET_POWERPC64"
6728 "@
6729 mulld %0,%1,%2
6730 mulli %0,%1,%2"
6731 [(set (attr "type")
6732 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6733 (const_string "imul3")
6734 (match_operand:SI 2 "short_cint_operand" "")
6735 (const_string "imul2")]
6736 (const_string "lmul")))])
6738 (define_insn "*muldi3_internal1"
6739 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6740 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6741 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6742 (const_int 0)))
6743 (clobber (match_scratch:DI 3 "=r,r"))]
6744 "TARGET_POWERPC64"
6745 "@
6746 mulld. %3,%1,%2
6747 #"
6748 [(set_attr "type" "lmul_compare")
6749 (set_attr "length" "4,8")])
6751 (define_split
6752 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6753 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6754 (match_operand:DI 2 "gpc_reg_operand" ""))
6755 (const_int 0)))
6756 (clobber (match_scratch:DI 3 ""))]
6757 "TARGET_POWERPC64 && reload_completed"
6758 [(set (match_dup 3)
6759 (mult:DI (match_dup 1) (match_dup 2)))
6760 (set (match_dup 0)
6761 (compare:CC (match_dup 3)
6762 (const_int 0)))]
6763 "")
6765 (define_insn "*muldi3_internal2"
6766 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6767 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6768 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6769 (const_int 0)))
6770 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6771 (mult:DI (match_dup 1) (match_dup 2)))]
6772 "TARGET_POWERPC64"
6773 "@
6774 mulld. %0,%1,%2
6775 #"
6776 [(set_attr "type" "lmul_compare")
6777 (set_attr "length" "4,8")])
6779 (define_split
6780 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6781 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6782 (match_operand:DI 2 "gpc_reg_operand" ""))
6783 (const_int 0)))
6784 (set (match_operand:DI 0 "gpc_reg_operand" "")
6785 (mult:DI (match_dup 1) (match_dup 2)))]
6786 "TARGET_POWERPC64 && reload_completed"
6787 [(set (match_dup 0)
6788 (mult:DI (match_dup 1) (match_dup 2)))
6789 (set (match_dup 3)
6790 (compare:CC (match_dup 0)
6791 (const_int 0)))]
6792 "")
6794 (define_insn "smuldi3_highpart"
6795 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6796 (truncate:DI
6797 (lshiftrt:TI (mult:TI (sign_extend:TI
6798 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6799 (sign_extend:TI
6800 (match_operand:DI 2 "gpc_reg_operand" "r")))
6801 (const_int 64))))]
6802 "TARGET_POWERPC64"
6803 "mulhd %0,%1,%2"
6804 [(set_attr "type" "lmul")])
6806 (define_insn "umuldi3_highpart"
6807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6808 (truncate:DI
6809 (lshiftrt:TI (mult:TI (zero_extend:TI
6810 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6811 (zero_extend:TI
6812 (match_operand:DI 2 "gpc_reg_operand" "r")))
6813 (const_int 64))))]
6814 "TARGET_POWERPC64"
6815 "mulhdu %0,%1,%2"
6816 [(set_attr "type" "lmul")])
6818 (define_expand "mulditi3"
6819 [(set (match_operand:TI 0 "gpc_reg_operand")
6820 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6821 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6822 "TARGET_POWERPC64"
6823 {
6824 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6825 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6826 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2]));
6827 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6828 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6829 DONE;
6830 })
6832 (define_expand "umulditi3"
6833 [(set (match_operand:TI 0 "gpc_reg_operand")
6834 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand"))
6835 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))]
6836 "TARGET_POWERPC64"
6837 {
6838 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode);
6839 emit_insn (gen_muldi3 (l, operands[1], operands[2]));
6840 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2]));
6841 emit_move_insn (gen_lowpart (DImode, operands[0]), l);
6842 emit_move_insn (gen_highpart (DImode, operands[0]), h);
6843 DONE;
6844 })
6846 (define_insn "rotldi3"
6847 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6848 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6849 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6850 "TARGET_POWERPC64"
6851 "@
6852 rldcl %0,%1,%2,0
6853 rldicl %0,%1,%H2,0"
6854 [(set_attr "type" "var_shift_rotate,integer")])
6856 (define_insn "*rotldi3_internal2"
6857 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6858 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6859 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6860 (const_int 0)))
6861 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6862 "TARGET_64BIT"
6863 "@
6864 rldcl. %3,%1,%2,0
6865 rldicl. %3,%1,%H2,0
6866 #
6867 #"
6868 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6869 (set_attr "length" "4,4,8,8")])
6871 (define_split
6872 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6873 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6874 (match_operand:DI 2 "reg_or_cint_operand" ""))
6875 (const_int 0)))
6876 (clobber (match_scratch:DI 3 ""))]
6877 "TARGET_POWERPC64 && reload_completed"
6878 [(set (match_dup 3)
6879 (rotate:DI (match_dup 1) (match_dup 2)))
6880 (set (match_dup 0)
6881 (compare:CC (match_dup 3)
6882 (const_int 0)))]
6883 "")
6885 (define_insn "*rotldi3_internal3"
6886 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6887 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6888 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6889 (const_int 0)))
6890 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6891 (rotate:DI (match_dup 1) (match_dup 2)))]
6892 "TARGET_64BIT"
6893 "@
6894 rldcl. %0,%1,%2,0
6895 rldicl. %0,%1,%H2,0
6896 #
6897 #"
6898 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6899 (set_attr "length" "4,4,8,8")])
6901 (define_split
6902 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6903 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6904 (match_operand:DI 2 "reg_or_cint_operand" ""))
6905 (const_int 0)))
6906 (set (match_operand:DI 0 "gpc_reg_operand" "")
6907 (rotate:DI (match_dup 1) (match_dup 2)))]
6908 "TARGET_POWERPC64 && reload_completed"
6909 [(set (match_dup 0)
6910 (rotate:DI (match_dup 1) (match_dup 2)))
6911 (set (match_dup 3)
6912 (compare:CC (match_dup 0)
6913 (const_int 0)))]
6914 "")
6916 (define_insn "*rotldi3_internal4"
6917 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6918 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6919 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6920 (match_operand:DI 3 "mask64_operand" "n,n")))]
6921 "TARGET_POWERPC64"
6922 "@
6923 rldc%B3 %0,%1,%2,%S3
6924 rldic%B3 %0,%1,%H2,%S3"
6925 [(set_attr "type" "var_shift_rotate,integer")])
6927 (define_insn "*rotldi3_internal5"
6928 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6929 (compare:CC (and:DI
6930 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6931 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6932 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6933 (const_int 0)))
6934 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6935 "TARGET_64BIT"
6936 "@
6937 rldc%B3. %4,%1,%2,%S3
6938 rldic%B3. %4,%1,%H2,%S3
6939 #
6940 #"
6941 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6942 (set_attr "length" "4,4,8,8")])
6944 (define_split
6945 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6946 (compare:CC (and:DI
6947 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6948 (match_operand:DI 2 "reg_or_cint_operand" ""))
6949 (match_operand:DI 3 "mask64_operand" ""))
6950 (const_int 0)))
6951 (clobber (match_scratch:DI 4 ""))]
6952 "TARGET_POWERPC64 && reload_completed"
6953 [(set (match_dup 4)
6954 (and:DI (rotate:DI (match_dup 1)
6955 (match_dup 2))
6956 (match_dup 3)))
6957 (set (match_dup 0)
6958 (compare:CC (match_dup 4)
6959 (const_int 0)))]
6960 "")
6962 (define_insn "*rotldi3_internal6"
6963 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6964 (compare:CC (and:DI
6965 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6966 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6967 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6968 (const_int 0)))
6969 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6970 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6971 "TARGET_64BIT"
6972 "@
6973 rldc%B3. %0,%1,%2,%S3
6974 rldic%B3. %0,%1,%H2,%S3
6975 #
6976 #"
6977 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6978 (set_attr "length" "4,4,8,8")])
6980 (define_split
6981 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6982 (compare:CC (and:DI
6983 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6984 (match_operand:DI 2 "reg_or_cint_operand" ""))
6985 (match_operand:DI 3 "mask64_operand" ""))
6986 (const_int 0)))
6987 (set (match_operand:DI 0 "gpc_reg_operand" "")
6988 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6989 "TARGET_POWERPC64 && reload_completed"
6990 [(set (match_dup 0)
6991 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6992 (set (match_dup 4)
6993 (compare:CC (match_dup 0)
6994 (const_int 0)))]
6995 "")
6997 (define_insn "*rotldi3_internal7le"
6998 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6999 (zero_extend:DI
7000 (subreg:QI
7001 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7002 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7003 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7004 "@
7005 rldcl %0,%1,%2,56
7006 rldicl %0,%1,%H2,56"
7007 [(set_attr "type" "var_shift_rotate,integer")])
7009 (define_insn "*rotldi3_internal7be"
7010 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7011 (zero_extend:DI
7012 (subreg:QI
7013 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7014 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))]
7015 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7016 "@
7017 rldcl %0,%1,%2,56
7018 rldicl %0,%1,%H2,56"
7019 [(set_attr "type" "var_shift_rotate,integer")])
7021 (define_insn "*rotldi3_internal8le"
7022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7023 (compare:CC (zero_extend:DI
7024 (subreg:QI
7025 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7026 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7027 (const_int 0)))
7028 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7029 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7030 "@
7031 rldcl. %3,%1,%2,56
7032 rldicl. %3,%1,%H2,56
7033 #
7034 #"
7035 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7036 (set_attr "length" "4,4,8,8")])
7038 (define_insn "*rotldi3_internal8be"
7039 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7040 (compare:CC (zero_extend:DI
7041 (subreg:QI
7042 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7043 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7044 (const_int 0)))
7045 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7046 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7047 "@
7048 rldcl. %3,%1,%2,56
7049 rldicl. %3,%1,%H2,56
7050 #
7051 #"
7052 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7053 (set_attr "length" "4,4,8,8")])
7055 (define_split
7056 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7057 (compare:CC (zero_extend:DI
7058 (subreg:QI
7059 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7060 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7061 (const_int 0)))
7062 (clobber (match_scratch:DI 3 ""))]
7063 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7064 [(set (match_dup 3)
7065 (zero_extend:DI (subreg:QI
7066 (rotate:DI (match_dup 1)
7067 (match_dup 2)) 0)))
7068 (set (match_dup 0)
7069 (compare:CC (match_dup 3)
7070 (const_int 0)))]
7071 "")
7073 (define_split
7074 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7075 (compare:CC (zero_extend:DI
7076 (subreg:QI
7077 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7078 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7079 (const_int 0)))
7080 (clobber (match_scratch:DI 3 ""))]
7081 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7082 [(set (match_dup 3)
7083 (zero_extend:DI (subreg:QI
7084 (rotate:DI (match_dup 1)
7085 (match_dup 2)) 7)))
7086 (set (match_dup 0)
7087 (compare:CC (match_dup 3)
7088 (const_int 0)))]
7089 "")
7091 (define_insn "*rotldi3_internal9le"
7092 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7093 (compare:CC (zero_extend:DI
7094 (subreg:QI
7095 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7096 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7097 (const_int 0)))
7098 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7099 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7100 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7101 "@
7102 rldcl. %0,%1,%2,56
7103 rldicl. %0,%1,%H2,56
7104 #
7105 #"
7106 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7107 (set_attr "length" "4,4,8,8")])
7109 (define_insn "*rotldi3_internal9be"
7110 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7111 (compare:CC (zero_extend:DI
7112 (subreg:QI
7113 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7114 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7))
7115 (const_int 0)))
7116 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7117 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7118 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7119 "@
7120 rldcl. %0,%1,%2,56
7121 rldicl. %0,%1,%H2,56
7122 #
7123 #"
7124 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7125 (set_attr "length" "4,4,8,8")])
7127 (define_split
7128 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7129 (compare:CC (zero_extend:DI
7130 (subreg:QI
7131 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7132 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7133 (const_int 0)))
7134 (set (match_operand:DI 0 "gpc_reg_operand" "")
7135 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7136 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7137 [(set (match_dup 0)
7138 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7139 (set (match_dup 3)
7140 (compare:CC (match_dup 0)
7141 (const_int 0)))]
7142 "")
7144 (define_split
7145 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7146 (compare:CC (zero_extend:DI
7147 (subreg:QI
7148 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7149 (match_operand:DI 2 "reg_or_cint_operand" "")) 7))
7150 (const_int 0)))
7151 (set (match_operand:DI 0 "gpc_reg_operand" "")
7152 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))]
7153 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7154 [(set (match_dup 0)
7155 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))
7156 (set (match_dup 3)
7157 (compare:CC (match_dup 0)
7158 (const_int 0)))]
7159 "")
7161 (define_insn "*rotldi3_internal10le"
7162 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7163 (zero_extend:DI
7164 (subreg:HI
7165 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7166 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7167 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7168 "@
7169 rldcl %0,%1,%2,48
7170 rldicl %0,%1,%H2,48"
7171 [(set_attr "type" "var_shift_rotate,integer")])
7173 (define_insn "*rotldi3_internal10be"
7174 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7175 (zero_extend:DI
7176 (subreg:HI
7177 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7178 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))]
7179 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7180 "@
7181 rldcl %0,%1,%2,48
7182 rldicl %0,%1,%H2,48"
7183 [(set_attr "type" "var_shift_rotate,integer")])
7185 (define_insn "*rotldi3_internal11le"
7186 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7187 (compare:CC (zero_extend:DI
7188 (subreg:HI
7189 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7190 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7191 (const_int 0)))
7192 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7193 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7194 "@
7195 rldcl. %3,%1,%2,48
7196 rldicl. %3,%1,%H2,48
7197 #
7198 #"
7199 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7200 (set_attr "length" "4,4,8,8")])
7202 (define_insn "*rotldi3_internal11be"
7203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7204 (compare:CC (zero_extend:DI
7205 (subreg:HI
7206 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7207 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7208 (const_int 0)))
7209 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7210 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7211 "@
7212 rldcl. %3,%1,%2,48
7213 rldicl. %3,%1,%H2,48
7214 #
7215 #"
7216 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7217 (set_attr "length" "4,4,8,8")])
7219 (define_split
7220 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7221 (compare:CC (zero_extend:DI
7222 (subreg:HI
7223 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7224 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7225 (const_int 0)))
7226 (clobber (match_scratch:DI 3 ""))]
7227 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7228 [(set (match_dup 3)
7229 (zero_extend:DI (subreg:HI
7230 (rotate:DI (match_dup 1)
7231 (match_dup 2)) 0)))
7232 (set (match_dup 0)
7233 (compare:CC (match_dup 3)
7234 (const_int 0)))]
7235 "")
7237 (define_split
7238 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7239 (compare:CC (zero_extend:DI
7240 (subreg:HI
7241 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7242 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7243 (const_int 0)))
7244 (clobber (match_scratch:DI 3 ""))]
7245 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7246 [(set (match_dup 3)
7247 (zero_extend:DI (subreg:HI
7248 (rotate:DI (match_dup 1)
7249 (match_dup 2)) 6)))
7250 (set (match_dup 0)
7251 (compare:CC (match_dup 3)
7252 (const_int 0)))]
7253 "")
7255 (define_insn "*rotldi3_internal12le"
7256 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7257 (compare:CC (zero_extend:DI
7258 (subreg:HI
7259 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7260 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7261 (const_int 0)))
7262 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7263 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7264 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7265 "@
7266 rldcl. %0,%1,%2,48
7267 rldicl. %0,%1,%H2,48
7268 #
7269 #"
7270 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7271 (set_attr "length" "4,4,8,8")])
7273 (define_insn "*rotldi3_internal12be"
7274 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7275 (compare:CC (zero_extend:DI
7276 (subreg:HI
7277 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7278 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6))
7279 (const_int 0)))
7280 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7281 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7282 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7283 "@
7284 rldcl. %0,%1,%2,48
7285 rldicl. %0,%1,%H2,48
7286 #
7287 #"
7288 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7289 (set_attr "length" "4,4,8,8")])
7291 (define_split
7292 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7293 (compare:CC (zero_extend:DI
7294 (subreg:HI
7295 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7296 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7297 (const_int 0)))
7298 (set (match_operand:DI 0 "gpc_reg_operand" "")
7299 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7300 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7301 [(set (match_dup 0)
7302 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7303 (set (match_dup 3)
7304 (compare:CC (match_dup 0)
7305 (const_int 0)))]
7306 "")
7308 (define_split
7309 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7310 (compare:CC (zero_extend:DI
7311 (subreg:HI
7312 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7313 (match_operand:DI 2 "reg_or_cint_operand" "")) 6))
7314 (const_int 0)))
7315 (set (match_operand:DI 0 "gpc_reg_operand" "")
7316 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))]
7317 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7318 [(set (match_dup 0)
7319 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))
7320 (set (match_dup 3)
7321 (compare:CC (match_dup 0)
7322 (const_int 0)))]
7323 "")
7325 (define_insn "*rotldi3_internal13le"
7326 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7327 (zero_extend:DI
7328 (subreg:SI
7329 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7330 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7331 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN"
7332 "@
7333 rldcl %0,%1,%2,32
7334 rldicl %0,%1,%H2,32"
7335 [(set_attr "type" "var_shift_rotate,integer")])
7337 (define_insn "*rotldi3_internal13be"
7338 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7339 (zero_extend:DI
7340 (subreg:SI
7341 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7342 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))]
7343 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN"
7344 "@
7345 rldcl %0,%1,%2,32
7346 rldicl %0,%1,%H2,32"
7347 [(set_attr "type" "var_shift_rotate,integer")])
7349 (define_insn "*rotldi3_internal14le"
7350 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7351 (compare:CC (zero_extend:DI
7352 (subreg:SI
7353 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7354 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7355 (const_int 0)))
7356 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7357 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7358 "@
7359 rldcl. %3,%1,%2,32
7360 rldicl. %3,%1,%H2,32
7361 #
7362 #"
7363 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7364 (set_attr "length" "4,4,8,8")])
7366 (define_insn "*rotldi3_internal14be"
7367 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7368 (compare:CC (zero_extend:DI
7369 (subreg:SI
7370 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7371 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7372 (const_int 0)))
7373 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7374 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7375 "@
7376 rldcl. %3,%1,%2,32
7377 rldicl. %3,%1,%H2,32
7378 #
7379 #"
7380 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7381 (set_attr "length" "4,4,8,8")])
7383 (define_split
7384 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7385 (compare:CC (zero_extend:DI
7386 (subreg:SI
7387 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7388 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7389 (const_int 0)))
7390 (clobber (match_scratch:DI 3 ""))]
7391 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7392 [(set (match_dup 3)
7393 (zero_extend:DI (subreg:SI
7394 (rotate:DI (match_dup 1)
7395 (match_dup 2)) 0)))
7396 (set (match_dup 0)
7397 (compare:CC (match_dup 3)
7398 (const_int 0)))]
7399 "")
7401 (define_split
7402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7403 (compare:CC (zero_extend:DI
7404 (subreg:SI
7405 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7406 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7407 (const_int 0)))
7408 (clobber (match_scratch:DI 3 ""))]
7409 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7410 [(set (match_dup 3)
7411 (zero_extend:DI (subreg:SI
7412 (rotate:DI (match_dup 1)
7413 (match_dup 2)) 4)))
7414 (set (match_dup 0)
7415 (compare:CC (match_dup 3)
7416 (const_int 0)))]
7417 "")
7419 (define_insn "*rotldi3_internal15le"
7420 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7421 (compare:CC (zero_extend:DI
7422 (subreg:SI
7423 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7424 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7425 (const_int 0)))
7426 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7427 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7428 "TARGET_64BIT && !BYTES_BIG_ENDIAN"
7429 "@
7430 rldcl. %0,%1,%2,32
7431 rldicl. %0,%1,%H2,32
7432 #
7433 #"
7434 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7435 (set_attr "length" "4,4,8,8")])
7437 (define_insn "*rotldi3_internal15be"
7438 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7439 (compare:CC (zero_extend:DI
7440 (subreg:SI
7441 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7442 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4))
7443 (const_int 0)))
7444 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7445 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7446 "TARGET_64BIT && BYTES_BIG_ENDIAN"
7447 "@
7448 rldcl. %0,%1,%2,32
7449 rldicl. %0,%1,%H2,32
7450 #
7451 #"
7452 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7453 (set_attr "length" "4,4,8,8")])
7455 (define_split
7456 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7457 (compare:CC (zero_extend:DI
7458 (subreg:SI
7459 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7460 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7461 (const_int 0)))
7462 (set (match_operand:DI 0 "gpc_reg_operand" "")
7463 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7464 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed"
7465 [(set (match_dup 0)
7466 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7467 (set (match_dup 3)
7468 (compare:CC (match_dup 0)
7469 (const_int 0)))]
7470 "")
7472 (define_split
7473 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7474 (compare:CC (zero_extend:DI
7475 (subreg:SI
7476 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7477 (match_operand:DI 2 "reg_or_cint_operand" "")) 4))
7478 (const_int 0)))
7479 (set (match_operand:DI 0 "gpc_reg_operand" "")
7480 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))]
7481 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed"
7482 [(set (match_dup 0)
7483 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))
7484 (set (match_dup 3)
7485 (compare:CC (match_dup 0)
7486 (const_int 0)))]
7487 "")
7489 (define_expand "ashldi3"
7490 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7491 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7492 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7493 "TARGET_POWERPC64"
7494 "")
7496 (define_insn "*ashldi3_internal1"
7497 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7498 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7499 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7500 "TARGET_POWERPC64"
7501 "@
7502 sld %0,%1,%2
7503 sldi %0,%1,%H2"
7504 [(set_attr "type" "var_shift_rotate,shift")])
7506 (define_insn "*ashldi3_internal2"
7507 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7508 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7509 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7510 (const_int 0)))
7511 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7512 "TARGET_64BIT"
7513 "@
7514 sld. %3,%1,%2
7515 sldi. %3,%1,%H2
7516 #
7517 #"
7518 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7519 (set_attr "length" "4,4,8,8")])
7521 (define_split
7522 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7523 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7524 (match_operand:SI 2 "reg_or_cint_operand" ""))
7525 (const_int 0)))
7526 (clobber (match_scratch:DI 3 ""))]
7527 "TARGET_POWERPC64 && reload_completed"
7528 [(set (match_dup 3)
7529 (ashift:DI (match_dup 1) (match_dup 2)))
7530 (set (match_dup 0)
7531 (compare:CC (match_dup 3)
7532 (const_int 0)))]
7533 "")
7535 (define_insn "*ashldi3_internal3"
7536 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7537 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7538 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7539 (const_int 0)))
7540 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7541 (ashift:DI (match_dup 1) (match_dup 2)))]
7542 "TARGET_64BIT"
7543 "@
7544 sld. %0,%1,%2
7545 sldi. %0,%1,%H2
7546 #
7547 #"
7548 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7549 (set_attr "length" "4,4,8,8")])
7551 (define_split
7552 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7553 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7554 (match_operand:SI 2 "reg_or_cint_operand" ""))
7555 (const_int 0)))
7556 (set (match_operand:DI 0 "gpc_reg_operand" "")
7557 (ashift:DI (match_dup 1) (match_dup 2)))]
7558 "TARGET_POWERPC64 && reload_completed"
7559 [(set (match_dup 0)
7560 (ashift:DI (match_dup 1) (match_dup 2)))
7561 (set (match_dup 3)
7562 (compare:CC (match_dup 0)
7563 (const_int 0)))]
7564 "")
7566 (define_insn "*ashldi3_internal4"
7567 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7568 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7569 (match_operand:SI 2 "const_int_operand" "i"))
7570 (match_operand:DI 3 "const_int_operand" "n")))]
7571 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7572 "rldic %0,%1,%H2,%W3")
7574 (define_insn "ashldi3_internal5"
7575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7576 (compare:CC
7577 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7578 (match_operand:SI 2 "const_int_operand" "i,i"))
7579 (match_operand:DI 3 "const_int_operand" "n,n"))
7580 (const_int 0)))
7581 (clobber (match_scratch:DI 4 "=r,r"))]
7582 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7583 "@
7584 rldic. %4,%1,%H2,%W3
7585 #"
7586 [(set_attr "type" "compare")
7587 (set_attr "length" "4,8")])
7589 (define_split
7590 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7591 (compare:CC
7592 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7593 (match_operand:SI 2 "const_int_operand" ""))
7594 (match_operand:DI 3 "const_int_operand" ""))
7595 (const_int 0)))
7596 (clobber (match_scratch:DI 4 ""))]
7597 "TARGET_POWERPC64 && reload_completed
7598 && includes_rldic_lshift_p (operands[2], operands[3])"
7599 [(set (match_dup 4)
7600 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7601 (match_dup 3)))
7602 (set (match_dup 0)
7603 (compare:CC (match_dup 4)
7604 (const_int 0)))]
7605 "")
7607 (define_insn "*ashldi3_internal6"
7608 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7609 (compare:CC
7610 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7611 (match_operand:SI 2 "const_int_operand" "i,i"))
7612 (match_operand:DI 3 "const_int_operand" "n,n"))
7613 (const_int 0)))
7614 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7615 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7616 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7617 "@
7618 rldic. %0,%1,%H2,%W3
7619 #"
7620 [(set_attr "type" "compare")
7621 (set_attr "length" "4,8")])
7623 (define_split
7624 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7625 (compare:CC
7626 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7627 (match_operand:SI 2 "const_int_operand" ""))
7628 (match_operand:DI 3 "const_int_operand" ""))
7629 (const_int 0)))
7630 (set (match_operand:DI 0 "gpc_reg_operand" "")
7631 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7632 "TARGET_POWERPC64 && reload_completed
7633 && includes_rldic_lshift_p (operands[2], operands[3])"
7634 [(set (match_dup 0)
7635 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7636 (match_dup 3)))
7637 (set (match_dup 4)
7638 (compare:CC (match_dup 0)
7639 (const_int 0)))]
7640 "")
7642 (define_insn "*ashldi3_internal7"
7643 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7644 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7645 (match_operand:SI 2 "const_int_operand" "i"))
7646 (match_operand:DI 3 "mask64_operand" "n")))]
7647 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7648 "rldicr %0,%1,%H2,%S3")
7650 (define_insn "ashldi3_internal8"
7651 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7652 (compare:CC
7653 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7654 (match_operand:SI 2 "const_int_operand" "i,i"))
7655 (match_operand:DI 3 "mask64_operand" "n,n"))
7656 (const_int 0)))
7657 (clobber (match_scratch:DI 4 "=r,r"))]
7658 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7659 "@
7660 rldicr. %4,%1,%H2,%S3
7661 #"
7662 [(set_attr "type" "compare")
7663 (set_attr "length" "4,8")])
7665 (define_split
7666 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7667 (compare:CC
7668 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7669 (match_operand:SI 2 "const_int_operand" ""))
7670 (match_operand:DI 3 "mask64_operand" ""))
7671 (const_int 0)))
7672 (clobber (match_scratch:DI 4 ""))]
7673 "TARGET_POWERPC64 && reload_completed
7674 && includes_rldicr_lshift_p (operands[2], operands[3])"
7675 [(set (match_dup 4)
7676 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7677 (match_dup 3)))
7678 (set (match_dup 0)
7679 (compare:CC (match_dup 4)
7680 (const_int 0)))]
7681 "")
7683 (define_insn "*ashldi3_internal9"
7684 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7685 (compare:CC
7686 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7687 (match_operand:SI 2 "const_int_operand" "i,i"))
7688 (match_operand:DI 3 "mask64_operand" "n,n"))
7689 (const_int 0)))
7690 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7691 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7692 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7693 "@
7694 rldicr. %0,%1,%H2,%S3
7695 #"
7696 [(set_attr "type" "compare")
7697 (set_attr "length" "4,8")])
7699 (define_split
7700 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7701 (compare:CC
7702 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7703 (match_operand:SI 2 "const_int_operand" ""))
7704 (match_operand:DI 3 "mask64_operand" ""))
7705 (const_int 0)))
7706 (set (match_operand:DI 0 "gpc_reg_operand" "")
7707 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7708 "TARGET_POWERPC64 && reload_completed
7709 && includes_rldicr_lshift_p (operands[2], operands[3])"
7710 [(set (match_dup 0)
7711 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7712 (match_dup 3)))
7713 (set (match_dup 4)
7714 (compare:CC (match_dup 0)
7715 (const_int 0)))]
7716 "")
7718 (define_expand "lshrdi3"
7719 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7720 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7721 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7722 "TARGET_POWERPC64"
7723 "")
7725 (define_insn "*lshrdi3_internal1"
7726 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7727 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7728 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7729 "TARGET_POWERPC64"
7730 "@
7731 srd %0,%1,%2
7732 srdi %0,%1,%H2"
7733 [(set_attr "type" "var_shift_rotate,shift")])
7735 (define_insn "*lshrdi3_internal2"
7736 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7737 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7738 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7739 (const_int 0)))
7740 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7741 "TARGET_64BIT "
7742 "@
7743 srd. %3,%1,%2
7744 srdi. %3,%1,%H2
7745 #
7746 #"
7747 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7748 (set_attr "length" "4,4,8,8")])
7750 (define_split
7751 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7752 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7753 (match_operand:SI 2 "reg_or_cint_operand" ""))
7754 (const_int 0)))
7755 (clobber (match_scratch:DI 3 ""))]
7756 "TARGET_POWERPC64 && reload_completed"
7757 [(set (match_dup 3)
7758 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7759 (set (match_dup 0)
7760 (compare:CC (match_dup 3)
7761 (const_int 0)))]
7762 "")
7764 (define_insn "*lshrdi3_internal3"
7765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7766 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7767 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7768 (const_int 0)))
7769 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7770 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7771 "TARGET_64BIT"
7772 "@
7773 srd. %0,%1,%2
7774 srdi. %0,%1,%H2
7775 #
7776 #"
7777 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7778 (set_attr "length" "4,4,8,8")])
7780 (define_split
7781 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7782 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7783 (match_operand:SI 2 "reg_or_cint_operand" ""))
7784 (const_int 0)))
7785 (set (match_operand:DI 0 "gpc_reg_operand" "")
7786 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7787 "TARGET_POWERPC64 && reload_completed"
7788 [(set (match_dup 0)
7789 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7790 (set (match_dup 3)
7791 (compare:CC (match_dup 0)
7792 (const_int 0)))]
7793 "")
7795 (define_expand "ashrdi3"
7796 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7797 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7798 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7799 ""
7800 "
7801 {
7802 if (TARGET_POWERPC64)
7803 ;
7804 else if (GET_CODE (operands[2]) == CONST_INT)
7805 {
7806 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7807 DONE;
7808 }
7809 else
7810 FAIL;
7811 }")
7813 (define_insn "*ashrdi3_internal1"
7814 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7815 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7816 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7817 "TARGET_POWERPC64"
7818 "@
7819 srad %0,%1,%2
7820 sradi %0,%1,%H2"
7821 [(set_attr "type" "var_shift_rotate,shift")])
7823 (define_insn "*ashrdi3_internal2"
7824 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7825 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7826 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7827 (const_int 0)))
7828 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7829 "TARGET_64BIT"
7830 "@
7831 srad. %3,%1,%2
7832 sradi. %3,%1,%H2
7833 #
7834 #"
7835 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7836 (set_attr "length" "4,4,8,8")])
7838 (define_split
7839 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7840 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7841 (match_operand:SI 2 "reg_or_cint_operand" ""))
7842 (const_int 0)))
7843 (clobber (match_scratch:DI 3 ""))]
7844 "TARGET_POWERPC64 && reload_completed"
7845 [(set (match_dup 3)
7846 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7847 (set (match_dup 0)
7848 (compare:CC (match_dup 3)
7849 (const_int 0)))]
7850 "")
7852 (define_insn "*ashrdi3_internal3"
7853 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7854 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7855 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7856 (const_int 0)))
7857 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7858 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7859 "TARGET_64BIT"
7860 "@
7861 srad. %0,%1,%2
7862 sradi. %0,%1,%H2
7863 #
7864 #"
7865 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7866 (set_attr "length" "4,4,8,8")])
7868 (define_split
7869 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7870 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7871 (match_operand:SI 2 "reg_or_cint_operand" ""))
7872 (const_int 0)))
7873 (set (match_operand:DI 0 "gpc_reg_operand" "")
7874 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7875 "TARGET_POWERPC64 && reload_completed"
7876 [(set (match_dup 0)
7877 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7878 (set (match_dup 3)
7879 (compare:CC (match_dup 0)
7880 (const_int 0)))]
7881 "")
7883 (define_expand "anddi3"
7884 [(parallel
7885 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7886 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7887 (match_operand:DI 2 "reg_or_cint_operand" "")))
7888 (clobber (match_scratch:CC 3 ""))])]
7889 ""
7890 {
7891 if (!TARGET_POWERPC64)
7892 {
7893 rtx cc = gen_rtx_SCRATCH (CCmode);
7894 rs6000_split_logical (operands, AND, false, false, false, cc);
7895 DONE;
7896 }
7897 else if (!and64_2_operand (operands[2], DImode))
7898 operands[2] = force_reg (DImode, operands[2]);
7899 })
7901 (define_insn "anddi3_mc"
7902 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7903 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7904 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7905 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7906 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7907 "@
7908 and %0,%1,%2
7909 rldic%B2 %0,%1,0,%S2
7910 rlwinm %0,%1,0,%m2,%M2
7911 andi. %0,%1,%b2
7912 andis. %0,%1,%u2
7913 #"
7914 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7915 (set_attr "length" "4,4,4,4,4,8")])
7917 (define_insn "anddi3_nomc"
7918 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7919 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7920 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7921 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7922 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7923 "@
7924 and %0,%1,%2
7925 rldic%B2 %0,%1,0,%S2
7926 rlwinm %0,%1,0,%m2,%M2
7927 #"
7928 [(set_attr "length" "4,4,4,8")])
7930 (define_split
7931 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7932 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7933 (match_operand:DI 2 "mask64_2_operand" "")))
7934 (clobber (match_scratch:CC 3 ""))]
7935 "TARGET_POWERPC64
7936 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7937 && !mask_operand (operands[2], DImode)
7938 && !mask64_operand (operands[2], DImode)"
7939 [(set (match_dup 0)
7940 (and:DI (rotate:DI (match_dup 1)
7941 (match_dup 4))
7942 (match_dup 5)))
7943 (set (match_dup 0)
7944 (and:DI (rotate:DI (match_dup 0)
7945 (match_dup 6))
7946 (match_dup 7)))]
7947 {
7948 build_mask64_2_operands (operands[2], &operands[4]);
7949 })
7951 (define_insn "*anddi3_internal2_mc"
7952 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7953 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7954 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7955 (const_int 0)))
7956 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7957 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7958 "TARGET_64BIT && rs6000_gen_cell_microcode"
7959 "@
7960 and. %3,%1,%2
7961 rldic%B2. %3,%1,0,%S2
7962 rlwinm. %3,%1,0,%m2,%M2
7963 andi. %3,%1,%b2
7964 andis. %3,%1,%u2
7965 #
7966 #
7967 #
7968 #
7969 #
7970 #
7971 #"
7972 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7973 fast_compare,compare,compare,compare,compare,compare,\
7974 compare,compare")
7975 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7977 (define_split
7978 [(set (match_operand:CC 0 "cc_reg_operand" "")
7979 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7980 (match_operand:DI 2 "mask64_2_operand" ""))
7981 (const_int 0)))
7982 (clobber (match_scratch:DI 3 ""))
7983 (clobber (match_scratch:CC 4 ""))]
7984 "TARGET_64BIT && reload_completed
7985 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7986 && !mask_operand (operands[2], DImode)
7987 && !mask64_operand (operands[2], DImode)"
7988 [(set (match_dup 3)
7989 (and:DI (rotate:DI (match_dup 1)
7990 (match_dup 5))
7991 (match_dup 6)))
7992 (parallel [(set (match_dup 0)
7993 (compare:CC (and:DI (rotate:DI (match_dup 3)
7994 (match_dup 7))
7995 (match_dup 8))
7996 (const_int 0)))
7997 (clobber (match_dup 3))])]
7998 "
7999 {
8000 build_mask64_2_operands (operands[2], &operands[5]);
8001 }")
8003 (define_insn "*anddi3_internal3_mc"
8004 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8005 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8006 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8007 (const_int 0)))
8008 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8009 (and:DI (match_dup 1) (match_dup 2)))
8010 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8011 "TARGET_64BIT && rs6000_gen_cell_microcode"
8012 "@
8013 and. %0,%1,%2
8014 rldic%B2. %0,%1,0,%S2
8015 rlwinm. %0,%1,0,%m2,%M2
8016 andi. %0,%1,%b2
8017 andis. %0,%1,%u2
8018 #
8019 #
8020 #
8021 #
8022 #
8023 #
8024 #"
8025 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8026 fast_compare,compare,compare,compare,compare,compare,\
8027 compare,compare")
8028 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8030 (define_split
8031 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8032 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8033 (match_operand:DI 2 "and64_2_operand" ""))
8034 (const_int 0)))
8035 (set (match_operand:DI 0 "gpc_reg_operand" "")
8036 (and:DI (match_dup 1) (match_dup 2)))
8037 (clobber (match_scratch:CC 4 ""))]
8038 "TARGET_64BIT && reload_completed"
8039 [(parallel [(set (match_dup 0)
8040 (and:DI (match_dup 1) (match_dup 2)))
8041 (clobber (match_dup 4))])
8042 (set (match_dup 3)
8043 (compare:CC (match_dup 0)
8044 (const_int 0)))]
8045 "")
8047 (define_split
8048 [(set (match_operand:CC 3 "cc_reg_operand" "")
8049 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8050 (match_operand:DI 2 "mask64_2_operand" ""))
8051 (const_int 0)))
8052 (set (match_operand:DI 0 "gpc_reg_operand" "")
8053 (and:DI (match_dup 1) (match_dup 2)))
8054 (clobber (match_scratch:CC 4 ""))]
8055 "TARGET_64BIT && reload_completed
8056 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8057 && !mask_operand (operands[2], DImode)
8058 && !mask64_operand (operands[2], DImode)"
8059 [(set (match_dup 0)
8060 (and:DI (rotate:DI (match_dup 1)
8061 (match_dup 5))
8062 (match_dup 6)))
8063 (parallel [(set (match_dup 3)
8064 (compare:CC (and:DI (rotate:DI (match_dup 0)
8065 (match_dup 7))
8066 (match_dup 8))
8067 (const_int 0)))
8068 (set (match_dup 0)
8069 (and:DI (rotate:DI (match_dup 0)
8070 (match_dup 7))
8071 (match_dup 8)))])]
8072 "
8073 {
8074 build_mask64_2_operands (operands[2], &operands[5]);
8075 }")
8077 (define_expand "iordi3"
8078 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8079 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8080 (match_operand:DI 2 "reg_or_cint_operand" "")))]
8081 ""
8082 {
8083 if (!TARGET_POWERPC64)
8084 {
8085 rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX);
8086 DONE;
8087 }
8088 else if (!reg_or_logical_cint_operand (operands[2], DImode))
8089 operands[2] = force_reg (DImode, operands[2]);
8090 else if (non_logical_cint_operand (operands[2], DImode))
8091 {
8092 HOST_WIDE_INT value;
8093 rtx tmp = ((!can_create_pseudo_p ()
8094 || rtx_equal_p (operands[0], operands[1]))
8095 ? operands[0] : gen_reg_rtx (DImode));
8097 value = INTVAL (operands[2]);
8098 emit_insn (gen_iordi3 (tmp, operands[1],
8099 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8101 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8102 DONE;
8103 }
8104 })
8106 (define_expand "xordi3"
8107 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8108 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8109 (match_operand:DI 2 "reg_or_cint_operand" "")))]
8110 ""
8111 {
8112 if (!TARGET_POWERPC64)
8113 {
8114 rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX);
8115 DONE;
8116 }
8117 else if (!reg_or_logical_cint_operand (operands[2], DImode))
8118 operands[2] = force_reg (DImode, operands[2]);
8119 if (non_logical_cint_operand (operands[2], DImode))
8120 {
8121 HOST_WIDE_INT value;
8122 rtx tmp = ((!can_create_pseudo_p ()
8123 || rtx_equal_p (operands[0], operands[1]))
8124 ? operands[0] : gen_reg_rtx (DImode));
8126 value = INTVAL (operands[2]);
8127 emit_insn (gen_xordi3 (tmp, operands[1],
8128 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8130 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8131 DONE;
8132 }
8133 })
8135 (define_insn "*booldi3_internal1"
8136 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8137 (match_operator:DI 3 "boolean_or_operator"
8138 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8139 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8140 "TARGET_POWERPC64"
8141 "@
8142 %q3 %0,%1,%2
8143 %q3i %0,%1,%b2
8144 %q3is %0,%1,%u2")
8146 (define_insn "*booldi3_internal2"
8147 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8148 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8149 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8150 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8151 (const_int 0)))
8152 (clobber (match_scratch:DI 3 "=r,r"))]
8153 "TARGET_64BIT"
8154 "@
8155 %q4. %3,%1,%2
8156 #"
8157 [(set_attr "type" "fast_compare,compare")
8158 (set_attr "length" "4,8")])
8160 (define_split
8161 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8162 (compare:CC (match_operator:DI 4 "boolean_operator"
8163 [(match_operand:DI 1 "gpc_reg_operand" "")
8164 (match_operand:DI 2 "gpc_reg_operand" "")])
8165 (const_int 0)))
8166 (clobber (match_scratch:DI 3 ""))]
8167 "TARGET_POWERPC64 && reload_completed"
8168 [(set (match_dup 3) (match_dup 4))
8169 (set (match_dup 0)
8170 (compare:CC (match_dup 3)
8171 (const_int 0)))]
8172 "")
8174 (define_insn "*booldi3_internal3"
8175 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8176 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8177 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8178 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8179 (const_int 0)))
8180 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8181 (match_dup 4))]
8182 "TARGET_64BIT"
8183 "@
8184 %q4. %0,%1,%2
8185 #"
8186 [(set_attr "type" "fast_compare,compare")
8187 (set_attr "length" "4,8")])
8189 (define_split
8190 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8191 (compare:CC (match_operator:DI 4 "boolean_operator"
8192 [(match_operand:DI 1 "gpc_reg_operand" "")
8193 (match_operand:DI 2 "gpc_reg_operand" "")])
8194 (const_int 0)))
8195 (set (match_operand:DI 0 "gpc_reg_operand" "")
8196 (match_dup 4))]
8197 "TARGET_POWERPC64 && reload_completed"
8198 [(set (match_dup 0) (match_dup 4))
8199 (set (match_dup 3)
8200 (compare:CC (match_dup 0)
8201 (const_int 0)))]
8202 "")
8204 ;; Split a logical operation that we can't do in one insn into two insns,
8205 ;; each of which does one 16-bit part. This is used by combine.
8207 (define_split
8208 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8209 (match_operator:DI 3 "boolean_or_operator"
8210 [(match_operand:DI 1 "gpc_reg_operand" "")
8211 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8212 "TARGET_POWERPC64"
8213 [(set (match_dup 0) (match_dup 4))
8214 (set (match_dup 0) (match_dup 5))]
8215 "
8216 {
8217 rtx i3,i4;
8219 i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
8220 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8221 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8222 operands[1], i3);
8223 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8224 operands[0], i4);
8225 }")
8227 (define_insn "*boolcdi3_internal1"
8228 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8229 (match_operator:DI 3 "boolean_operator"
8230 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8231 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8232 "TARGET_POWERPC64"
8233 "%q3 %0,%2,%1")
8235 (define_insn "*boolcdi3_internal2"
8236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8237 (compare:CC (match_operator:DI 4 "boolean_operator"
8238 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8239 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8240 (const_int 0)))
8241 (clobber (match_scratch:DI 3 "=r,r"))]
8242 "TARGET_64BIT"
8243 "@
8244 %q4. %3,%2,%1
8245 #"
8246 [(set_attr "type" "fast_compare,compare")
8247 (set_attr "length" "4,8")])
8249 (define_split
8250 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8251 (compare:CC (match_operator:DI 4 "boolean_operator"
8252 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8253 (match_operand:DI 2 "gpc_reg_operand" "")])
8254 (const_int 0)))
8255 (clobber (match_scratch:DI 3 ""))]
8256 "TARGET_POWERPC64 && reload_completed"
8257 [(set (match_dup 3) (match_dup 4))
8258 (set (match_dup 0)
8259 (compare:CC (match_dup 3)
8260 (const_int 0)))]
8261 "")
8263 (define_insn "*boolcdi3_internal3"
8264 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8265 (compare:CC (match_operator:DI 4 "boolean_operator"
8266 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8267 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8268 (const_int 0)))
8269 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8270 (match_dup 4))]
8271 "TARGET_64BIT"
8272 "@
8273 %q4. %0,%2,%1
8274 #"
8275 [(set_attr "type" "fast_compare,compare")
8276 (set_attr "length" "4,8")])
8278 (define_split
8279 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8280 (compare:CC (match_operator:DI 4 "boolean_operator"
8281 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8282 (match_operand:DI 2 "gpc_reg_operand" "")])
8283 (const_int 0)))
8284 (set (match_operand:DI 0 "gpc_reg_operand" "")
8285 (match_dup 4))]
8286 "TARGET_POWERPC64 && reload_completed"
8287 [(set (match_dup 0) (match_dup 4))
8288 (set (match_dup 3)
8289 (compare:CC (match_dup 0)
8290 (const_int 0)))]
8291 "")
8293 (define_insn "*boolccdi3_internal1"
8294 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8295 (match_operator:DI 3 "boolean_operator"
8296 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8297 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8298 "TARGET_POWERPC64"
8299 "%q3 %0,%1,%2")
8301 (define_insn "*boolccdi3_internal2"
8302 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8303 (compare:CC (match_operator:DI 4 "boolean_operator"
8304 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8305 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8306 (const_int 0)))
8307 (clobber (match_scratch:DI 3 "=r,r"))]
8308 "TARGET_64BIT"
8309 "@
8310 %q4. %3,%1,%2
8311 #"
8312 [(set_attr "type" "fast_compare,compare")
8313 (set_attr "length" "4,8")])
8315 (define_split
8316 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8317 (compare:CC (match_operator:DI 4 "boolean_operator"
8318 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8319 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8320 (const_int 0)))
8321 (clobber (match_scratch:DI 3 ""))]
8322 "TARGET_POWERPC64 && reload_completed"
8323 [(set (match_dup 3) (match_dup 4))
8324 (set (match_dup 0)
8325 (compare:CC (match_dup 3)
8326 (const_int 0)))]
8327 "")
8329 (define_insn "*boolccdi3_internal3"
8330 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8331 (compare:CC (match_operator:DI 4 "boolean_operator"
8332 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8333 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8334 (const_int 0)))
8335 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8336 (match_dup 4))]
8337 "TARGET_64BIT"
8338 "@
8339 %q4. %0,%1,%2
8340 #"
8341 [(set_attr "type" "fast_compare,compare")
8342 (set_attr "length" "4,8")])
8344 (define_split
8345 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8346 (compare:CC (match_operator:DI 4 "boolean_operator"
8347 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8348 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8349 (const_int 0)))
8350 (set (match_operand:DI 0 "gpc_reg_operand" "")
8351 (match_dup 4))]
8352 "TARGET_POWERPC64 && reload_completed"
8353 [(set (match_dup 0) (match_dup 4))
8354 (set (match_dup 3)
8355 (compare:CC (match_dup 0)
8356 (const_int 0)))]
8357 "")
8359 ;; Eqv operation.
8360 (define_insn "*eqv<mode>3"
8361 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
8362 (not:GPR
8363 (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
8364 (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
8365 ""
8366 "eqv %0,%1,%2"
8367 [(set_attr "type" "integer")
8368 (set_attr "length" "4")])
8370 \f
8371 ;; 128-bit logical operations expanders
8373 (define_expand "and<mode>3"
8374 [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8375 (and:BOOL_128
8376 (match_operand:BOOL_128 1 "vlogical_operand" "")
8377 (match_operand:BOOL_128 2 "vlogical_operand" "")))
8378 (clobber (match_scratch:CC 3 ""))])]
8379 ""
8380 "")
8382 (define_expand "ior<mode>3"
8383 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8384 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8385 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8386 ""
8387 "")
8389 (define_expand "xor<mode>3"
8390 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8391 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8392 (match_operand:BOOL_128 2 "vlogical_operand" "")))]
8393 ""
8394 "")
8396 (define_expand "one_cmpl<mode>2"
8397 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8398 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8399 ""
8400 "")
8402 (define_expand "nor<mode>3"
8403 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8404 (and:BOOL_128
8405 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8406 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8407 ""
8408 "")
8410 (define_expand "andc<mode>3"
8411 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8412 (and:BOOL_128
8413 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8414 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8415 ""
8416 "")
8418 ;; Power8 vector logical instructions.
8419 (define_expand "eqv<mode>3"
8420 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8421 (not:BOOL_128
8422 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")
8423 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8424 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8425 "")
8427 ;; Rewrite nand into canonical form
8428 (define_expand "nand<mode>3"
8429 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8430 (ior:BOOL_128
8431 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" ""))
8432 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))]
8433 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8434 "")
8436 ;; The canonical form is to have the negated element first, so we need to
8437 ;; reverse arguments.
8438 (define_expand "orc<mode>3"
8439 [(set (match_operand:BOOL_128 0 "vlogical_operand" "")
8440 (ior:BOOL_128
8441 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))
8442 (match_operand:BOOL_128 1 "vlogical_operand" "")))]
8443 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR"
8444 "")
8446 ;; 128-bit logical operations insns and split operations
8447 (define_insn_and_split "*and<mode>3_internal"
8448 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8449 (and:BOOL_128
8450 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8451 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")))
8452 (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))]
8453 ""
8454 {
8455 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8456 return "xxland %x0,%x1,%x2";
8458 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8459 return "vand %0,%1,%2";
8461 return "#";
8462 }
8463 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8464 [(const_int 0)]
8465 {
8466 rs6000_split_logical (operands, AND, false, false, false, operands[3]);
8467 DONE;
8468 }
8469 [(set (attr "type")
8470 (if_then_else
8471 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8472 (const_string "vecsimple")
8473 (const_string "integer")))
8474 (set (attr "length")
8475 (if_then_else
8476 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8477 (const_string "4")
8478 (if_then_else
8479 (match_test "TARGET_POWERPC64")
8480 (const_string "8")
8481 (const_string "16"))))])
8483 ;; 128-bit IOR/XOR
8484 (define_insn_and_split "*bool<mode>3_internal"
8485 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8486 (match_operator:BOOL_128 3 "boolean_or_operator"
8487 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>")
8488 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8489 ""
8490 {
8491 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8492 return "xxl%q3 %x0,%x1,%x2";
8494 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8495 return "v%q3 %0,%1,%2";
8497 return "#";
8498 }
8499 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8500 [(const_int 0)]
8501 {
8502 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false,
8503 NULL_RTX);
8504 DONE;
8505 }
8506 [(set (attr "type")
8507 (if_then_else
8508 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8509 (const_string "vecsimple")
8510 (const_string "integer")))
8511 (set (attr "length")
8512 (if_then_else
8513 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8514 (const_string "4")
8515 (if_then_else
8516 (match_test "TARGET_POWERPC64")
8517 (const_string "8")
8518 (const_string "16"))))])
8520 ;; 128-bit ANDC/ORC
8521 (define_insn_and_split "*boolc<mode>3_internal1"
8522 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8523 (match_operator:BOOL_128 3 "boolean_operator"
8524 [(not:BOOL_128
8525 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP1>"))
8526 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP2>")]))]
8527 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8528 {
8529 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8530 return "xxl%q3 %x0,%x1,%x2";
8532 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8533 return "v%q3 %0,%1,%2";
8535 return "#";
8536 }
8537 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8538 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8539 [(const_int 0)]
8540 {
8541 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8542 NULL_RTX);
8543 DONE;
8544 }
8545 [(set (attr "type")
8546 (if_then_else
8547 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8548 (const_string "vecsimple")
8549 (const_string "integer")))
8550 (set (attr "length")
8551 (if_then_else
8552 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8553 (const_string "4")
8554 (if_then_else
8555 (match_test "TARGET_POWERPC64")
8556 (const_string "8")
8557 (const_string "16"))))])
8559 (define_insn_and_split "*boolc<mode>3_internal2"
8560 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8561 (match_operator:TI2 3 "boolean_operator"
8562 [(not:TI2
8563 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8564 (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))]
8565 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8566 "#"
8567 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8568 [(const_int 0)]
8569 {
8570 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false,
8571 NULL_RTX);
8572 DONE;
8573 }
8574 [(set_attr "type" "integer")
8575 (set (attr "length")
8576 (if_then_else
8577 (match_test "TARGET_POWERPC64")
8578 (const_string "8")
8579 (const_string "16")))])
8581 ;; 128-bit NAND/NOR
8582 (define_insn_and_split "*boolcc<mode>3_internal1"
8583 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8584 (match_operator:BOOL_128 3 "boolean_operator"
8585 [(not:BOOL_128
8586 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>"))
8587 (not:BOOL_128
8588 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))]
8589 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)"
8590 {
8591 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8592 return "xxl%q3 %x0,%x1,%x2";
8594 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8595 return "v%q3 %0,%1,%2";
8597 return "#";
8598 }
8599 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND))
8600 && reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8601 [(const_int 0)]
8602 {
8603 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8604 NULL_RTX);
8605 DONE;
8606 }
8607 [(set (attr "type")
8608 (if_then_else
8609 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8610 (const_string "vecsimple")
8611 (const_string "integer")))
8612 (set (attr "length")
8613 (if_then_else
8614 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8615 (const_string "4")
8616 (if_then_else
8617 (match_test "TARGET_POWERPC64")
8618 (const_string "8")
8619 (const_string "16"))))])
8621 (define_insn_and_split "*boolcc<mode>3_internal2"
8622 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8623 (match_operator:TI2 3 "boolean_operator"
8624 [(not:TI2
8625 (match_operand:TI2 1 "int_reg_operand" "r,0,r"))
8626 (not:TI2
8627 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))]
8628 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8629 "#"
8630 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)"
8631 [(const_int 0)]
8632 {
8633 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true,
8634 NULL_RTX);
8635 DONE;
8636 }
8637 [(set_attr "type" "integer")
8638 (set (attr "length")
8639 (if_then_else
8640 (match_test "TARGET_POWERPC64")
8641 (const_string "8")
8642 (const_string "16")))])
8645 ;; 128-bit EQV
8646 (define_insn_and_split "*eqv<mode>3_internal1"
8647 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8648 (not:BOOL_128
8649 (xor:BOOL_128
8650 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")
8651 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))]
8652 "TARGET_P8_VECTOR"
8653 {
8654 if (vsx_register_operand (operands[0], <MODE>mode))
8655 return "xxleqv %x0,%x1,%x2";
8657 return "#";
8658 }
8659 "TARGET_P8_VECTOR && reload_completed
8660 && int_reg_operand (operands[0], <MODE>mode)"
8661 [(const_int 0)]
8662 {
8663 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8664 DONE;
8665 }
8666 [(set (attr "type")
8667 (if_then_else
8668 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8669 (const_string "vecsimple")
8670 (const_string "integer")))
8671 (set (attr "length")
8672 (if_then_else
8673 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8674 (const_string "4")
8675 (if_then_else
8676 (match_test "TARGET_POWERPC64")
8677 (const_string "8")
8678 (const_string "16"))))])
8680 (define_insn_and_split "*eqv<mode>3_internal2"
8681 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r")
8682 (not:TI2
8683 (xor:TI2
8684 (match_operand:TI2 1 "int_reg_operand" "r,0,r")
8685 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))]
8686 "!TARGET_P8_VECTOR"
8687 "#"
8688 "reload_completed && !TARGET_P8_VECTOR"
8689 [(const_int 0)]
8690 {
8691 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX);
8692 DONE;
8693 }
8694 [(set_attr "type" "integer")
8695 (set (attr "length")
8696 (if_then_else
8697 (match_test "TARGET_POWERPC64")
8698 (const_string "8")
8699 (const_string "16")))])
8701 ;; 128-bit one's complement
8702 (define_insn_and_split "*one_cmpl<mode>3_internal"
8703 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>")
8704 (not:BOOL_128
8705 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))]
8706 ""
8707 {
8708 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode))
8709 return "xxlnor %x0,%x1,%x1";
8711 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode))
8712 return "vnor %0,%1,%1";
8714 return "#";
8715 }
8716 "reload_completed && int_reg_operand (operands[0], <MODE>mode)"
8717 [(const_int 0)]
8718 {
8719 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX);
8720 DONE;
8721 }
8722 [(set (attr "type")
8723 (if_then_else
8724 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8725 (const_string "vecsimple")
8726 (const_string "integer")))
8727 (set (attr "length")
8728 (if_then_else
8729 (match_test "vsx_register_operand (operands[0], <MODE>mode)")
8730 (const_string "4")
8731 (if_then_else
8732 (match_test "TARGET_POWERPC64")
8733 (const_string "8")
8734 (const_string "16"))))])
8736 \f
8737 ;; Now define ways of moving data around.
8739 ;; Set up a register with a value from the GOT table
8741 (define_expand "movsi_got"
8742 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8743 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8744 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8745 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8746 "
8747 {
8748 if (GET_CODE (operands[1]) == CONST)
8749 {
8750 rtx offset = const0_rtx;
8751 HOST_WIDE_INT value;
8753 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8754 value = INTVAL (offset);
8755 if (value != 0)
8756 {
8757 rtx tmp = (!can_create_pseudo_p ()
8758 ? operands[0]
8759 : gen_reg_rtx (Pmode));
8760 emit_insn (gen_movsi_got (tmp, operands[1]));
8761 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8762 DONE;
8763 }
8764 }
8766 operands[2] = rs6000_got_register (operands[1]);
8767 }")
8769 (define_insn "*movsi_got_internal"
8770 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8771 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8772 (match_operand:SI 2 "gpc_reg_operand" "b")]
8773 UNSPEC_MOVSI_GOT))]
8774 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8775 "lwz %0,%a1@got(%2)"
8776 [(set_attr "type" "load")])
8778 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8779 ;; didn't get allocated to a hard register.
8780 (define_split
8781 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8782 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8783 (match_operand:SI 2 "memory_operand" "")]
8784 UNSPEC_MOVSI_GOT))]
8785 "DEFAULT_ABI == ABI_V4
8786 && flag_pic == 1
8787 && (reload_in_progress || reload_completed)"
8788 [(set (match_dup 0) (match_dup 2))
8789 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8790 UNSPEC_MOVSI_GOT))]
8791 "")
8793 ;; For SI, we special-case integers that can't be loaded in one insn. We
8794 ;; do the load 16-bits at a time. We could do this by loading from memory,
8795 ;; and this is even supposed to be faster, but it is simpler not to get
8796 ;; integers in the TOC.
8797 (define_insn "movsi_low"
8798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8799 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8800 (match_operand 2 "" ""))))]
8801 "TARGET_MACHO && ! TARGET_64BIT"
8802 "lwz %0,lo16(%2)(%1)"
8803 [(set_attr "type" "load")
8804 (set_attr "length" "4")])
8806 (define_insn "*movsi_internal1"
8807 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h")
8808 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))]
8809 "!TARGET_SINGLE_FPU &&
8810 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8811 "@
8812 mr %0,%1
8813 la %0,%a1
8814 lwz%U1%X1 %0,%1
8815 stw%U0%X0 %1,%0
8816 li %0,%1
8817 lis %0,%v1
8818 #
8819 mf%1 %0
8820 mt%0 %1
8821 mt%0 %1
8822 nop"
8823 [(set_attr_alternative "type"
8824 [(const_string "*")
8825 (const_string "*")
8826 (if_then_else
8827 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8828 (const_string "load_ux")
8829 (if_then_else
8830 (match_test "update_address_mem (operands[1], VOIDmode)")
8831 (const_string "load_u")
8832 (const_string "load")))
8833 (if_then_else
8834 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8835 (const_string "store_ux")
8836 (if_then_else
8837 (match_test "update_address_mem (operands[0], VOIDmode)")
8838 (const_string "store_u")
8839 (const_string "store")))
8840 (const_string "*")
8841 (const_string "*")
8842 (const_string "*")
8843 (const_string "mfjmpr")
8844 (const_string "mtjmpr")
8845 (const_string "*")
8846 (const_string "*")])
8848 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")])
8850 (define_insn "*movsi_internal1_single"
8851 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f")
8852 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))]
8853 "TARGET_SINGLE_FPU &&
8854 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8855 "@
8856 mr %0,%1
8857 la %0,%a1
8858 lwz%U1%X1 %0,%1
8859 stw%U0%X0 %1,%0
8860 li %0,%1
8861 lis %0,%v1
8862 #
8863 mf%1 %0
8864 mt%0 %1
8865 mt%0 %1
8866 nop
8867 stfs%U0%X0 %1,%0
8868 lfs%U1%X1 %0,%1"
8869 [(set_attr_alternative "type"
8870 [(const_string "*")
8871 (const_string "*")
8872 (if_then_else
8873 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8874 (const_string "load_ux")
8875 (if_then_else
8876 (match_test "update_address_mem (operands[1], VOIDmode)")
8877 (const_string "load_u")
8878 (const_string "load")))
8879 (if_then_else
8880 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8881 (const_string "store_ux")
8882 (if_then_else
8883 (match_test "update_address_mem (operands[0], VOIDmode)")
8884 (const_string "store_u")
8885 (const_string "store")))
8886 (const_string "*")
8887 (const_string "*")
8888 (const_string "*")
8889 (const_string "mfjmpr")
8890 (const_string "mtjmpr")
8891 (const_string "*")
8892 (const_string "*")
8893 (if_then_else
8894 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8895 (const_string "fpstore_ux")
8896 (if_then_else
8897 (match_test "update_address_mem (operands[0], VOIDmode)")
8898 (const_string "fpstore_u")
8899 (const_string "fpstore")))
8900 (if_then_else
8901 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8902 (const_string "fpload_ux")
8903 (if_then_else
8904 (match_test "update_address_mem (operands[1], VOIDmode)")
8905 (const_string "fpload_u")
8906 (const_string "fpload")))])
8907 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8909 ;; Split a load of a large constant into the appropriate two-insn
8910 ;; sequence.
8912 (define_split
8913 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8914 (match_operand:SI 1 "const_int_operand" ""))]
8915 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8916 && (INTVAL (operands[1]) & 0xffff) != 0"
8917 [(set (match_dup 0)
8918 (match_dup 2))
8919 (set (match_dup 0)
8920 (ior:SI (match_dup 0)
8921 (match_dup 3)))]
8922 "
8923 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8925 if (tem == operands[0])
8926 DONE;
8927 else
8928 FAIL;
8929 }")
8931 (define_insn "*mov<mode>_internal2"
8932 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8933 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8934 (const_int 0)))
8935 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8936 ""
8937 "@
8938 cmp<wd>i %2,%0,0
8939 mr. %0,%1
8940 #"
8941 [(set_attr "type" "cmp,fast_compare,cmp")
8942 (set_attr "length" "4,4,8")])
8944 (define_split
8945 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8946 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8947 (const_int 0)))
8948 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8949 "reload_completed"
8950 [(set (match_dup 0) (match_dup 1))
8951 (set (match_dup 2)
8952 (compare:CC (match_dup 0)
8953 (const_int 0)))]
8954 "")
8955 \f
8956 (define_insn "*movhi_internal"
8957 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8958 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8959 "gpc_reg_operand (operands[0], HImode)
8960 || gpc_reg_operand (operands[1], HImode)"
8961 "@
8962 mr %0,%1
8963 lhz%U1%X1 %0,%1
8964 sth%U0%X0 %1,%0
8965 li %0,%w1
8966 mf%1 %0
8967 mt%0 %1
8968 nop"
8969 [(set_attr_alternative "type"
8970 [(const_string "*")
8971 (if_then_else
8972 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
8973 (const_string "load_ux")
8974 (if_then_else
8975 (match_test "update_address_mem (operands[1], VOIDmode)")
8976 (const_string "load_u")
8977 (const_string "load")))
8978 (if_then_else
8979 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
8980 (const_string "store_ux")
8981 (if_then_else
8982 (match_test "update_address_mem (operands[0], VOIDmode)")
8983 (const_string "store_u")
8984 (const_string "store")))
8985 (const_string "*")
8986 (const_string "mfjmpr")
8987 (const_string "mtjmpr")
8988 (const_string "*")])])
8990 (define_expand "mov<mode>"
8991 [(set (match_operand:INT 0 "general_operand" "")
8992 (match_operand:INT 1 "any_operand" ""))]
8993 ""
8994 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8996 (define_insn "*movqi_internal"
8997 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h")
8998 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))]
8999 "gpc_reg_operand (operands[0], QImode)
9000 || gpc_reg_operand (operands[1], QImode)"
9001 "@
9002 mr %0,%1
9003 lbz%U1%X1 %0,%1
9004 stb%U0%X0 %1,%0
9005 li %0,%1
9006 mf%1 %0
9007 mt%0 %1
9008 nop"
9009 [(set_attr_alternative "type"
9010 [(const_string "*")
9011 (if_then_else
9012 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9013 (const_string "load_ux")
9014 (if_then_else
9015 (match_test "update_address_mem (operands[1], VOIDmode)")
9016 (const_string "load_u")
9017 (const_string "load")))
9018 (if_then_else
9019 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9020 (const_string "store_ux")
9021 (if_then_else
9022 (match_test "update_address_mem (operands[0], VOIDmode)")
9023 (const_string "store_u")
9024 (const_string "store")))
9025 (const_string "*")
9026 (const_string "mfjmpr")
9027 (const_string "mtjmpr")
9028 (const_string "*")])])
9029 \f
9030 ;; Here is how to move condition codes around. When we store CC data in
9031 ;; an integer register or memory, we store just the high-order 4 bits.
9032 ;; This lets us not shift in the most common case of CR0.
9033 (define_expand "movcc"
9034 [(set (match_operand:CC 0 "nonimmediate_operand" "")
9035 (match_operand:CC 1 "nonimmediate_operand" ""))]
9036 ""
9037 "")
9039 (define_insn "*movcc_internal1"
9040 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m")
9041 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))]
9042 "register_operand (operands[0], CCmode)
9043 || register_operand (operands[1], CCmode)"
9044 "@
9045 mcrf %0,%1
9046 mtcrf 128,%1
9047 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff
9048 crxor %0,%0,%0
9049 mfcr %0%Q1
9050 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000
9051 mr %0,%1
9052 li %0,%1
9053 mf%1 %0
9054 mt%0 %1
9055 lwz%U1%X1 %0,%1
9056 stw%U0%X0 %1,%0"
9057 [(set (attr "type")
9058 (cond [(eq_attr "alternative" "0,3")
9059 (const_string "cr_logical")
9060 (eq_attr "alternative" "1,2")
9061 (const_string "mtcr")
9062 (eq_attr "alternative" "6,7")
9063 (const_string "integer")
9064 (eq_attr "alternative" "8")
9065 (const_string "mfjmpr")
9066 (eq_attr "alternative" "9")
9067 (const_string "mtjmpr")
9068 (eq_attr "alternative" "10")
9069 (if_then_else
9070 (match_test "update_indexed_address_mem (operands[1],
9071 VOIDmode)")
9072 (const_string "load_ux")
9073 (if_then_else
9074 (match_test "update_address_mem (operands[1], VOIDmode)")
9075 (const_string "load_u")
9076 (const_string "load")))
9077 (eq_attr "alternative" "11")
9078 (if_then_else
9079 (match_test "update_indexed_address_mem (operands[0],
9080 VOIDmode)")
9081 (const_string "store_ux")
9082 (if_then_else
9083 (match_test "update_address_mem (operands[0], VOIDmode)")
9084 (const_string "store_u")
9085 (const_string "store")))
9086 (match_test "TARGET_MFCRF")
9087 (const_string "mfcrf")
9088 ]
9089 (const_string "mfcr")))
9090 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")])
9091 \f
9092 ;; For floating-point, we normally deal with the floating-point registers
9093 ;; unless -msoft-float is used. The sole exception is that parameter passing
9094 ;; can produce floating-point values in fixed-point registers. Unless the
9095 ;; value is a simple constant or already in memory, we deal with this by
9096 ;; allocating memory and copying the value explicitly via that memory location.
9098 ;; Move 32-bit binary/decimal floating point
9099 (define_expand "mov<mode>"
9100 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "")
9101 (match_operand:FMOVE32 1 "any_operand" ""))]
9102 "<fmove_ok>"
9103 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9105 (define_split
9106 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "")
9107 (match_operand:FMOVE32 1 "const_double_operand" ""))]
9108 "reload_completed
9109 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9110 || (GET_CODE (operands[0]) == SUBREG
9111 && GET_CODE (SUBREG_REG (operands[0])) == REG
9112 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9113 [(set (match_dup 2) (match_dup 3))]
9114 "
9115 {
9116 long l;
9117 REAL_VALUE_TYPE rv;
9119 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9120 <real_value_to_target> (rv, l);
9122 if (! TARGET_POWERPC64)
9123 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode);
9124 else
9125 operands[2] = gen_lowpart (SImode, operands[0]);
9127 operands[3] = gen_int_mode (l, SImode);
9128 }")
9130 (define_insn "mov<mode>_hardfloat"
9131 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,<f32_lr>,<f32_sm>,wu,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r")
9132 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,<f32_lm>,<f32_sr>,Z,wu,r,<f32_dm>,r,h,0,G,Fn"))]
9133 "(gpc_reg_operand (operands[0], <MODE>mode)
9134 || gpc_reg_operand (operands[1], <MODE>mode))
9135 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9136 "@
9137 mr %0,%1
9138 lwz%U1%X1 %0,%1
9139 stw%U0%X0 %1,%0
9140 fmr %0,%1
9141 xxlor %x0,%x1,%x1
9142 xxlxor %x0,%x0,%x0
9143 <f32_li>
9144 <f32_si>
9145 <f32_lv>
9146 <f32_sv>
9147 mtvsrwz %x0,%1
9148 mfvsrwz %0,%x1
9149 mt%0 %1
9150 mf%1 %0
9151 nop
9152 #
9153 #"
9154 [(set_attr_alternative "type"
9155 [(const_string "*")
9156 (if_then_else
9157 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9158 (const_string "load_ux")
9159 (if_then_else
9160 (match_test "update_address_mem (operands[1], VOIDmode)")
9161 (const_string "load_u")
9162 (const_string "load")))
9163 (if_then_else
9164 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9165 (const_string "store_ux")
9166 (if_then_else
9167 (match_test "update_address_mem (operands[0], VOIDmode)")
9168 (const_string "store_u")
9169 (const_string "store")))
9170 (const_string "fp")
9171 (const_string "vecsimple")
9172 (const_string "vecsimple")
9173 (if_then_else
9174 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9175 (const_string "fpload_ux")
9176 (if_then_else
9177 (match_test "update_address_mem (operands[1], VOIDmode)")
9178 (const_string "fpload_u")
9179 (const_string "fpload")))
9180 (if_then_else
9181 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9182 (const_string "fpstore_ux")
9183 (if_then_else
9184 (match_test "update_address_mem (operands[0], VOIDmode)")
9185 (const_string "fpstore_u")
9186 (const_string "fpstore")))
9187 (const_string "fpload")
9188 (const_string "fpstore")
9189 (const_string "mftgpr")
9190 (const_string "mffgpr")
9191 (const_string "mtjmpr")
9192 (const_string "mfjmpr")
9193 (const_string "*")
9194 (const_string "*")
9195 (const_string "*")])
9196 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")])
9198 (define_insn "*mov<mode>_softfloat"
9199 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
9200 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
9201 "(gpc_reg_operand (operands[0], <MODE>mode)
9202 || gpc_reg_operand (operands[1], <MODE>mode))
9203 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9204 "@
9205 mr %0,%1
9206 mt%0 %1
9207 mf%1 %0
9208 lwz%U1%X1 %0,%1
9209 stw%U0%X0 %1,%0
9210 li %0,%1
9211 lis %0,%v1
9212 #
9213 #
9214 nop"
9215 [(set_attr_alternative "type"
9216 [(const_string "*")
9217 (const_string "mtjmpr")
9218 (const_string "mfjmpr")
9219 (if_then_else
9220 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9221 (const_string "load_ux")
9222 (if_then_else
9223 (match_test "update_address_mem (operands[1], VOIDmode)")
9224 (const_string "load_u")
9225 (const_string "load")))
9226 (if_then_else
9227 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9228 (const_string "store_ux")
9229 (if_then_else
9230 (match_test "update_address_mem (operands[0], VOIDmode)")
9231 (const_string "store_u")
9232 (const_string "store")))
9233 (const_string "*")
9234 (const_string "*")
9235 (const_string "*")
9236 (const_string "*")
9237 (const_string "*")])
9238 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
9240 \f
9241 ;; Move 64-bit binary/decimal floating point
9242 (define_expand "mov<mode>"
9243 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "")
9244 (match_operand:FMOVE64 1 "any_operand" ""))]
9245 ""
9246 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9248 (define_split
9249 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9250 (match_operand:FMOVE64 1 "const_int_operand" ""))]
9251 "! TARGET_POWERPC64 && reload_completed
9252 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9253 || (GET_CODE (operands[0]) == SUBREG
9254 && GET_CODE (SUBREG_REG (operands[0])) == REG
9255 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9256 [(set (match_dup 2) (match_dup 4))
9257 (set (match_dup 3) (match_dup 1))]
9258 "
9259 {
9260 int endian = (WORDS_BIG_ENDIAN == 0);
9261 HOST_WIDE_INT value = INTVAL (operands[1]);
9263 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
9264 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
9265 operands[4] = GEN_INT (value >> 32);
9266 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9267 }")
9269 (define_split
9270 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9271 (match_operand:FMOVE64 1 "const_double_operand" ""))]
9272 "! TARGET_POWERPC64 && reload_completed
9273 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9274 || (GET_CODE (operands[0]) == SUBREG
9275 && GET_CODE (SUBREG_REG (operands[0])) == REG
9276 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9277 [(set (match_dup 2) (match_dup 4))
9278 (set (match_dup 3) (match_dup 5))]
9279 "
9280 {
9281 int endian = (WORDS_BIG_ENDIAN == 0);
9282 long l[2];
9283 REAL_VALUE_TYPE rv;
9285 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9286 <real_value_to_target> (rv, l);
9288 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
9289 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
9290 operands[4] = gen_int_mode (l[endian], SImode);
9291 operands[5] = gen_int_mode (l[1 - endian], SImode);
9292 }")
9294 (define_split
9295 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "")
9296 (match_operand:FMOVE64 1 "const_double_operand" ""))]
9297 "TARGET_POWERPC64 && reload_completed
9298 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9299 || (GET_CODE (operands[0]) == SUBREG
9300 && GET_CODE (SUBREG_REG (operands[0])) == REG
9301 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9302 [(set (match_dup 2) (match_dup 3))]
9303 "
9304 {
9305 int endian = (WORDS_BIG_ENDIAN == 0);
9306 long l[2];
9307 REAL_VALUE_TYPE rv;
9308 HOST_WIDE_INT val;
9310 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9311 <real_value_to_target> (rv, l);
9313 operands[2] = gen_lowpart (DImode, operands[0]);
9314 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9315 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9316 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9318 operands[3] = gen_int_mode (val, DImode);
9319 }")
9321 ;; Don't have reload use general registers to load a constant. It is
9322 ;; less efficient than loading the constant into an FP register, since
9323 ;; it will probably be used there.
9325 ;; The move constraints are ordered to prefer floating point registers before
9326 ;; general purpose registers to avoid doing a store and a load to get the value
9327 ;; into a floating point register when it is needed for a floating point
9328 ;; operation. Prefer traditional floating point registers over VSX registers,
9329 ;; since the D-form version of the memory instructions does not need a GPR for
9330 ;; reloading.
9332 (define_insn "*mov<mode>_hardfloat32"
9333 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r")
9334 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))]
9335 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9336 && (gpc_reg_operand (operands[0], <MODE>mode)
9337 || gpc_reg_operand (operands[1], <MODE>mode))"
9338 "@
9339 stfd%U0%X0 %1,%0
9340 lfd%U1%X1 %0,%1
9341 fmr %0,%1
9342 lxsd%U1x %x0,%y1
9343 stxsd%U0x %x1,%y0
9344 xxlor %x0,%x1,%x1
9345 xxlxor %x0,%x0,%x0
9346 #
9347 #
9348 #
9349 #
9350 #
9351 #"
9352 [(set_attr_alternative "type"
9353 [(if_then_else
9354 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9355 (const_string "fpstore_ux")
9356 (if_then_else
9357 (match_test "update_address_mem (operands[0], VOIDmode)")
9358 (const_string "fpstore_u")
9359 (const_string "fpstore")))
9360 (if_then_else
9361 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9362 (const_string "fpload_ux")
9363 (if_then_else
9364 (match_test "update_address_mem (operands[1], VOIDmode)")
9365 (const_string "fpload_u")
9366 (const_string "fpload")))
9367 (const_string "fp")
9368 (if_then_else
9369 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9370 (const_string "fpload_ux")
9371 (const_string "fpload"))
9372 (if_then_else
9373 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9374 (const_string "fpstore_ux")
9375 (const_string "fpstore"))
9376 (const_string "vecsimple")
9377 (const_string "vecsimple")
9378 (const_string "store")
9379 (const_string "load")
9380 (const_string "two")
9381 (const_string "fp")
9382 (const_string "fp")
9383 (const_string "*")])
9384 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")])
9386 (define_insn "*mov<mode>_softfloat32"
9387 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
9388 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
9389 "! TARGET_POWERPC64
9390 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9391 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9392 && (gpc_reg_operand (operands[0], <MODE>mode)
9393 || gpc_reg_operand (operands[1], <MODE>mode))"
9394 "#"
9395 [(set_attr "type" "store,load,two,*,*,*")
9396 (set_attr "length" "8,8,8,8,12,16")])
9398 ; ld/std require word-aligned displacements -> 'Y' constraint.
9399 ; List Y->r and r->Y before r->r for reload.
9400 (define_insn "*mov<mode>_hardfloat64"
9401 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm")
9402 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))]
9403 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9404 && (gpc_reg_operand (operands[0], <MODE>mode)
9405 || gpc_reg_operand (operands[1], <MODE>mode))"
9406 "@
9407 stfd%U0%X0 %1,%0
9408 lfd%U1%X1 %0,%1
9409 fmr %0,%1
9410 lxsd%U1x %x0,%y1
9411 stxsd%U0x %x1,%y0
9412 xxlor %x0,%x1,%x1
9413 xxlxor %x0,%x0,%x0
9414 std%U0%X0 %1,%0
9415 ld%U1%X1 %0,%1
9416 mr %0,%1
9417 mt%0 %1
9418 mf%1 %0
9419 nop
9420 #
9421 #
9422 #
9423 mftgpr %0,%1
9424 mffgpr %0,%1
9425 mfvsrd %0,%x1
9426 mtvsrd %x0,%1"
9427 [(set_attr_alternative "type"
9428 [(if_then_else
9429 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9430 (const_string "fpstore_ux")
9431 (if_then_else
9432 (match_test "update_address_mem (operands[0], VOIDmode)")
9433 (const_string "fpstore_u")
9434 (const_string "fpstore")))
9435 (if_then_else
9436 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9437 (const_string "fpload_ux")
9438 (if_then_else
9439 (match_test "update_address_mem (operands[1], VOIDmode)")
9440 (const_string "fpload_u")
9441 (const_string "fpload")))
9442 (const_string "fp")
9443 (if_then_else
9444 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9445 (const_string "fpload_ux")
9446 (const_string "fpload"))
9447 (if_then_else
9448 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9449 (const_string "fpstore_ux")
9450 (const_string "fpstore"))
9451 (const_string "vecsimple")
9452 (const_string "vecsimple")
9453 (if_then_else
9454 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9455 (const_string "store_ux")
9456 (if_then_else
9457 (match_test "update_address_mem (operands[0], VOIDmode)")
9458 (const_string "store_u")
9459 (const_string "store")))
9460 (if_then_else
9461 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9462 (const_string "load_ux")
9463 (if_then_else
9464 (match_test "update_address_mem (operands[1], VOIDmode)")
9465 (const_string "load_u")
9466 (const_string "load")))
9467 (const_string "*")
9468 (const_string "mtjmpr")
9469 (const_string "mfjmpr")
9470 (const_string "*")
9471 (const_string "*")
9472 (const_string "*")
9473 (const_string "*")
9474 (const_string "mftgpr")
9475 (const_string "mffgpr")
9476 (const_string "mftgpr")
9477 (const_string "mffgpr")])
9478 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")])
9480 (define_insn "*mov<mode>_softfloat64"
9481 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
9482 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
9483 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9484 && (gpc_reg_operand (operands[0], <MODE>mode)
9485 || gpc_reg_operand (operands[1], <MODE>mode))"
9486 "@
9487 std%U0%X0 %1,%0
9488 ld%U1%X1 %0,%1
9489 mr %0,%1
9490 mt%0 %1
9491 mf%1 %0
9492 #
9493 #
9494 #
9495 nop"
9496 [(set_attr_alternative "type"
9497 [(if_then_else
9498 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
9499 (const_string "store_ux")
9500 (if_then_else
9501 (match_test "update_address_mem (operands[0], VOIDmode)")
9502 (const_string "store_u")
9503 (const_string "store")))
9504 (if_then_else
9505 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
9506 (const_string "load_ux")
9507 (if_then_else
9508 (match_test "update_address_mem (operands[1], VOIDmode)")
9509 (const_string "load_u")
9510 (const_string "load")))
9511 (const_string "*")
9512 (const_string "mtjmpr")
9513 (const_string "mfjmpr")
9514 (const_string "*")
9515 (const_string "*")
9516 (const_string "*")
9517 (const_string "*")])
9518 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9519 \f
9520 (define_expand "mov<mode>"
9521 [(set (match_operand:FMOVE128 0 "general_operand" "")
9522 (match_operand:FMOVE128 1 "any_operand" ""))]
9523 ""
9524 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
9526 ;; It's important to list Y->r and r->Y before r->r because otherwise
9527 ;; reload, given m->r, will try to pick r->r and reload it, which
9528 ;; doesn't make progress.
9529 (define_insn_and_split "*mov<mode>_64bit"
9530 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm")
9531 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))]
9532 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
9533 && (gpc_reg_operand (operands[0], <MODE>mode)
9534 || gpc_reg_operand (operands[1], <MODE>mode))"
9535 "#"
9536 "&& reload_completed"
9537 [(pc)]
9538 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9539 [(set_attr "length" "8,8,8,12,12,8,8,8")])
9541 (define_insn_and_split "*mov<mode>_32bit"
9542 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
9543 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))]
9544 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64
9545 && (gpc_reg_operand (operands[0], <MODE>mode)
9546 || gpc_reg_operand (operands[1], <MODE>mode))"
9547 "#"
9548 "&& reload_completed"
9549 [(pc)]
9550 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9551 [(set_attr "length" "8,8,8,20,20,16")])
9553 (define_insn_and_split "*mov<mode>_softfloat"
9554 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r")
9555 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))]
9556 "(TARGET_SOFT_FLOAT || !TARGET_FPRS)
9557 && (gpc_reg_operand (operands[0], <MODE>mode)
9558 || gpc_reg_operand (operands[1], <MODE>mode))"
9559 "#"
9560 "&& reload_completed"
9561 [(pc)]
9562 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9563 [(set_attr "length" "20,20,16")])
9565 (define_expand "extenddftf2"
9566 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9567 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9568 "!TARGET_IEEEQUAD
9569 && TARGET_HARD_FLOAT
9570 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9571 && TARGET_LONG_DOUBLE_128"
9572 {
9573 if (TARGET_E500_DOUBLE)
9574 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9575 else
9576 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9577 DONE;
9578 })
9580 (define_expand "extenddftf2_fprs"
9581 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9582 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9583 (use (match_dup 2))])]
9584 "!TARGET_IEEEQUAD
9585 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9586 && TARGET_LONG_DOUBLE_128"
9587 {
9588 operands[2] = CONST0_RTX (DFmode);
9589 /* Generate GOT reference early for SVR4 PIC. */
9590 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9591 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9592 })
9594 (define_insn_and_split "*extenddftf2_internal"
9595 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
9596 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
9597 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
9598 "!TARGET_IEEEQUAD
9599 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9600 && TARGET_LONG_DOUBLE_128"
9601 "#"
9602 "&& reload_completed"
9603 [(pc)]
9604 {
9605 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9606 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9607 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9608 operands[1]);
9609 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9610 operands[2]);
9611 DONE;
9612 })
9614 (define_expand "extendsftf2"
9615 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9616 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9617 "!TARGET_IEEEQUAD
9618 && TARGET_HARD_FLOAT
9619 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9620 && TARGET_LONG_DOUBLE_128"
9621 {
9622 rtx tmp = gen_reg_rtx (DFmode);
9623 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9624 emit_insn (gen_extenddftf2 (operands[0], tmp));
9625 DONE;
9626 })
9628 (define_expand "trunctfdf2"
9629 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9630 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9631 "!TARGET_IEEEQUAD
9632 && TARGET_HARD_FLOAT
9633 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9634 && TARGET_LONG_DOUBLE_128"
9635 "")
9637 (define_insn_and_split "trunctfdf2_internal1"
9638 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9639 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9640 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9641 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9642 "@
9643 #
9644 fmr %0,%1"
9645 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9646 [(const_int 0)]
9647 {
9648 emit_note (NOTE_INSN_DELETED);
9649 DONE;
9650 }
9651 [(set_attr "type" "fp")])
9653 (define_insn "trunctfdf2_internal2"
9654 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9655 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9656 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9657 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9658 && TARGET_LONG_DOUBLE_128"
9659 "fadd %0,%1,%L1"
9660 [(set_attr "type" "fp")
9661 (set_attr "fp_type" "fp_addsub_d")])
9663 (define_expand "trunctfsf2"
9664 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9665 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9666 "!TARGET_IEEEQUAD
9667 && TARGET_HARD_FLOAT
9668 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9669 && TARGET_LONG_DOUBLE_128"
9670 {
9671 if (TARGET_E500_DOUBLE)
9672 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9673 else
9674 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9675 DONE;
9676 })
9678 (define_insn_and_split "trunctfsf2_fprs"
9679 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9680 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9681 (clobber (match_scratch:DF 2 "=d"))]
9682 "!TARGET_IEEEQUAD
9683 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9684 && TARGET_LONG_DOUBLE_128"
9685 "#"
9686 "&& reload_completed"
9687 [(set (match_dup 2)
9688 (float_truncate:DF (match_dup 1)))
9689 (set (match_dup 0)
9690 (float_truncate:SF (match_dup 2)))]
9691 "")
9693 (define_expand "floatsitf2"
9694 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9695 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9696 "!TARGET_IEEEQUAD
9697 && TARGET_HARD_FLOAT
9698 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9699 && TARGET_LONG_DOUBLE_128"
9700 {
9701 rtx tmp = gen_reg_rtx (DFmode);
9702 expand_float (tmp, operands[1], false);
9703 emit_insn (gen_extenddftf2 (operands[0], tmp));
9704 DONE;
9705 })
9707 ; fadd, but rounding towards zero.
9708 ; This is probably not the optimal code sequence.
9709 (define_insn "fix_trunc_helper"
9710 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9711 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9712 UNSPEC_FIX_TRUNC_TF))
9713 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9714 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9715 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9716 [(set_attr "type" "fp")
9717 (set_attr "length" "20")])
9719 (define_expand "fix_trunctfsi2"
9720 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9721 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9722 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT
9723 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
9724 {
9725 if (TARGET_E500_DOUBLE)
9726 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9727 else
9728 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9729 DONE;
9730 })
9732 (define_expand "fix_trunctfsi2_fprs"
9733 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9734 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9735 (clobber (match_dup 2))
9736 (clobber (match_dup 3))
9737 (clobber (match_dup 4))
9738 (clobber (match_dup 5))])]
9739 "!TARGET_IEEEQUAD
9740 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9741 {
9742 operands[2] = gen_reg_rtx (DFmode);
9743 operands[3] = gen_reg_rtx (DFmode);
9744 operands[4] = gen_reg_rtx (DImode);
9745 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
9746 })
9748 (define_insn_and_split "*fix_trunctfsi2_internal"
9749 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9750 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9751 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9752 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9753 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9754 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9755 "!TARGET_IEEEQUAD
9756 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9757 "#"
9758 ""
9759 [(pc)]
9760 {
9761 rtx lowword;
9762 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9764 gcc_assert (MEM_P (operands[5]));
9765 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9767 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9768 emit_move_insn (operands[5], operands[4]);
9769 emit_move_insn (operands[0], lowword);
9770 DONE;
9771 })
9773 (define_expand "negtf2"
9774 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9775 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9776 "!TARGET_IEEEQUAD
9777 && TARGET_HARD_FLOAT
9778 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9779 && TARGET_LONG_DOUBLE_128"
9780 "")
9782 (define_insn "negtf2_internal"
9783 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9784 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9785 "!TARGET_IEEEQUAD
9786 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9787 "*
9788 {
9789 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9790 return \"fneg %L0,%L1\;fneg %0,%1\";
9791 else
9792 return \"fneg %0,%1\;fneg %L0,%L1\";
9793 }"
9794 [(set_attr "type" "fp")
9795 (set_attr "length" "8")])
9797 (define_expand "abstf2"
9798 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9799 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9800 "!TARGET_IEEEQUAD
9801 && TARGET_HARD_FLOAT
9802 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9803 && TARGET_LONG_DOUBLE_128"
9804 "
9805 {
9806 rtx label = gen_label_rtx ();
9807 if (TARGET_E500_DOUBLE)
9808 {
9809 if (flag_finite_math_only && !flag_trapping_math)
9810 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9811 else
9812 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9813 }
9814 else
9815 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9816 emit_label (label);
9817 DONE;
9818 }")
9820 (define_expand "abstf2_internal"
9821 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9822 (match_operand:TF 1 "gpc_reg_operand" ""))
9823 (set (match_dup 3) (match_dup 5))
9824 (set (match_dup 5) (abs:DF (match_dup 5)))
9825 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9826 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9827 (label_ref (match_operand 2 "" ""))
9828 (pc)))
9829 (set (match_dup 6) (neg:DF (match_dup 6)))]
9830 "!TARGET_IEEEQUAD
9831 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9832 && TARGET_LONG_DOUBLE_128"
9833 "
9834 {
9835 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
9836 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
9837 operands[3] = gen_reg_rtx (DFmode);
9838 operands[4] = gen_reg_rtx (CCFPmode);
9839 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9840 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9841 }")
9842 \f
9843 ;; Reload helper functions used by rs6000_secondary_reload. The patterns all
9844 ;; must have 3 arguments, and scratch register constraint must be a single
9845 ;; constraint.
9847 ;; Reload patterns to support gpr load/store with misaligned mem.
9848 ;; and multiple gpr load/store at offset >= 0xfffc
9849 (define_expand "reload_<mode>_store"
9850 [(parallel [(match_operand 0 "memory_operand" "=m")
9851 (match_operand 1 "gpc_reg_operand" "r")
9852 (match_operand:GPR 2 "register_operand" "=&b")])]
9853 ""
9854 {
9855 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
9856 DONE;
9857 })
9859 (define_expand "reload_<mode>_load"
9860 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
9861 (match_operand 1 "memory_operand" "m")
9862 (match_operand:GPR 2 "register_operand" "=b")])]
9863 ""
9864 {
9865 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
9866 DONE;
9867 })
9869 \f
9870 ;; Power8 merge instructions to allow direct move to/from floating point
9871 ;; registers in 32-bit mode. We use TF mode to get two registers to move the
9872 ;; individual 32-bit parts across. Subreg doesn't work too well on the TF
9873 ;; value, since it is allocated in reload and not all of the flow information
9874 ;; is setup for it. We have two patterns to do the two moves between gprs and
9875 ;; fprs. There isn't a dependancy between the two, but we could potentially
9876 ;; schedule other instructions between the two instructions. TFmode is
9877 ;; currently limited to traditional FPR registers. If/when this is changed, we
9878 ;; will need to revist %L to make sure it works with VSX registers, or add an
9879 ;; %x version of %L.
9881 (define_insn "p8_fmrgow_<mode>"
9882 [(set (match_operand:FMOVE64X 0 "register_operand" "=d")
9883 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")]
9884 UNSPEC_P8V_FMRGOW))]
9885 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9886 "fmrgow %0,%1,%L1"
9887 [(set_attr "type" "vecperm")])
9889 (define_insn "p8_mtvsrwz_1"
9890 [(set (match_operand:TF 0 "register_operand" "=d")
9891 (unspec:TF [(match_operand:SI 1 "register_operand" "r")]
9892 UNSPEC_P8V_MTVSRWZ))]
9893 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9894 "mtvsrwz %x0,%1"
9895 [(set_attr "type" "mftgpr")])
9897 (define_insn "p8_mtvsrwz_2"
9898 [(set (match_operand:TF 0 "register_operand" "+d")
9899 (unspec:TF [(match_dup 0)
9900 (match_operand:SI 1 "register_operand" "r")]
9901 UNSPEC_P8V_MTVSRWZ))]
9902 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9903 "mtvsrwz %L0,%1"
9904 [(set_attr "type" "mftgpr")])
9906 (define_insn_and_split "reload_fpr_from_gpr<mode>"
9907 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws")
9908 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")]
9909 UNSPEC_P8V_RELOAD_FROM_GPR))
9910 (clobber (match_operand:TF 2 "register_operand" "=d"))]
9911 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9912 "#"
9913 "&& reload_completed"
9914 [(const_int 0)]
9915 {
9916 rtx dest = operands[0];
9917 rtx src = operands[1];
9918 rtx tmp = operands[2];
9919 rtx gpr_hi_reg = gen_highpart (SImode, src);
9920 rtx gpr_lo_reg = gen_lowpart (SImode, src);
9922 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg));
9923 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg));
9924 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp));
9925 DONE;
9926 }
9927 [(set_attr "length" "12")
9928 (set_attr "type" "three")])
9930 ;; Move 128 bit values from GPRs to VSX registers in 64-bit mode
9931 (define_insn "p8_mtvsrd_1"
9932 [(set (match_operand:TF 0 "register_operand" "=ws")
9933 (unspec:TF [(match_operand:DI 1 "register_operand" "r")]
9934 UNSPEC_P8V_MTVSRD))]
9935 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9936 "mtvsrd %0,%1"
9937 [(set_attr "type" "mftgpr")])
9939 (define_insn "p8_mtvsrd_2"
9940 [(set (match_operand:TF 0 "register_operand" "+ws")
9941 (unspec:TF [(match_dup 0)
9942 (match_operand:DI 1 "register_operand" "r")]
9943 UNSPEC_P8V_MTVSRD))]
9944 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9945 "mtvsrd %L0,%1"
9946 [(set_attr "type" "mftgpr")])
9948 (define_insn "p8_xxpermdi_<mode>"
9949 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9950 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")]
9951 UNSPEC_P8V_XXPERMDI))]
9952 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9953 "xxpermdi %x0,%1,%L1,0"
9954 [(set_attr "type" "vecperm")])
9956 (define_insn_and_split "reload_vsx_from_gpr<mode>"
9957 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa")
9958 (unspec:FMOVE128_GPR
9959 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")]
9960 UNSPEC_P8V_RELOAD_FROM_GPR))
9961 (clobber (match_operand:TF 2 "register_operand" "=ws"))]
9962 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9963 "#"
9964 "&& reload_completed"
9965 [(const_int 0)]
9966 {
9967 rtx dest = operands[0];
9968 rtx src = operands[1];
9969 rtx tmp = operands[2];
9970 rtx gpr_hi_reg = gen_highpart (DImode, src);
9971 rtx gpr_lo_reg = gen_lowpart (DImode, src);
9973 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg));
9974 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg));
9975 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp));
9976 }
9977 [(set_attr "length" "12")
9978 (set_attr "type" "three")])
9980 (define_split
9981 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "")
9982 (match_operand:FMOVE128_GPR 1 "input_operand" ""))]
9983 "reload_completed
9984 && (int_reg_operand (operands[0], <MODE>mode)
9985 || int_reg_operand (operands[1], <MODE>mode))"
9986 [(pc)]
9987 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9989 ;; Move SFmode to a VSX from a GPR register. Because scalar floating point
9990 ;; type is stored internally as double precision in the VSX registers, we have
9991 ;; to convert it from the vector format.
9993 (define_insn_and_split "reload_vsx_from_gprsf"
9994 [(set (match_operand:SF 0 "register_operand" "=wa")
9995 (unspec:SF [(match_operand:SF 1 "register_operand" "r")]
9996 UNSPEC_P8V_RELOAD_FROM_GPR))
9997 (clobber (match_operand:DI 2 "register_operand" "=r"))]
9998 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
9999 "#"
10000 "&& reload_completed"
10001 [(const_int 0)]
10002 {
10003 rtx op0 = operands[0];
10004 rtx op1 = operands[1];
10005 rtx op2 = operands[2];
10006 rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0);
10007 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0);
10009 /* Move SF value to upper 32-bits for xscvspdpn. */
10010 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32)));
10011 emit_move_insn (op0_di, op2);
10012 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0));
10013 DONE;
10014 }
10015 [(set_attr "length" "8")
10016 (set_attr "type" "two")])
10018 ;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a
10019 ;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value,
10020 ;; and then doing a move of that.
10021 (define_insn "p8_mfvsrd_3_<mode>"
10022 [(set (match_operand:DF 0 "register_operand" "=r")
10023 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
10024 UNSPEC_P8V_RELOAD_FROM_VSX))]
10025 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10026 "mfvsrd %0,%x1"
10027 [(set_attr "type" "mftgpr")])
10029 (define_insn_and_split "reload_gpr_from_vsx<mode>"
10030 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r")
10031 (unspec:FMOVE128_GPR
10032 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")]
10033 UNSPEC_P8V_RELOAD_FROM_VSX))
10034 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))]
10035 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10036 "#"
10037 "&& reload_completed"
10038 [(const_int 0)]
10039 {
10040 rtx dest = operands[0];
10041 rtx src = operands[1];
10042 rtx tmp = operands[2];
10043 rtx gpr_hi_reg = gen_highpart (DFmode, dest);
10044 rtx gpr_lo_reg = gen_lowpart (DFmode, dest);
10046 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src));
10047 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3)));
10048 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp));
10049 }
10050 [(set_attr "length" "12")
10051 (set_attr "type" "three")])
10053 ;; Move SFmode to a GPR from a VSX register. Because scalar floating point
10054 ;; type is stored internally as double precision, we have to convert it to the
10055 ;; vector format.
10057 (define_insn_and_split "reload_gpr_from_vsxsf"
10058 [(set (match_operand:SF 0 "register_operand" "=r")
10059 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")]
10060 UNSPEC_P8V_RELOAD_FROM_VSX))
10061 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))]
10062 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10063 "#"
10064 "&& reload_completed"
10065 [(const_int 0)]
10066 {
10067 rtx op0 = operands[0];
10068 rtx op1 = operands[1];
10069 rtx op2 = operands[2];
10070 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0);
10072 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1));
10073 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2));
10074 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32)));
10075 DONE;
10076 }
10077 [(set_attr "length" "12")
10078 (set_attr "type" "three")])
10080 (define_insn "p8_mfvsrd_4_disf"
10081 [(set (match_operand:DI 0 "register_operand" "=r")
10082 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")]
10083 UNSPEC_P8V_RELOAD_FROM_VSX))]
10084 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
10085 "mfvsrd %0,%x1"
10086 [(set_attr "type" "mftgpr")])
10088 \f
10089 ;; Next come the multi-word integer load and store and the load and store
10090 ;; multiple insns.
10092 ;; List r->r after r->Y, otherwise reload will try to reload a
10093 ;; non-offsettable address by using r->r which won't make progress.
10094 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
10095 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
10096 (define_insn "*movdi_internal32"
10097 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r")
10098 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))]
10099 "! TARGET_POWERPC64
10100 && (gpc_reg_operand (operands[0], DImode)
10101 || gpc_reg_operand (operands[1], DImode))"
10102 "@
10103 #
10104 #
10105 #
10106 stfd%U0%X0 %1,%0
10107 lfd%U1%X1 %0,%1
10108 fmr %0,%1
10109 #"
10110 [(set_attr_alternative "type"
10111 [(const_string "store")
10112 (const_string "load")
10113 (const_string "*")
10114 (if_then_else
10115 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10116 (const_string "fpstore_ux")
10117 (if_then_else
10118 (match_test "update_address_mem (operands[0], VOIDmode)")
10119 (const_string "fpstore_u")
10120 (const_string "fpstore")))
10121 (if_then_else
10122 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10123 (const_string "fpload_ux")
10124 (if_then_else
10125 (match_test "update_address_mem (operands[1], VOIDmode)")
10126 (const_string "fpload_u")
10127 (const_string "fpload")))
10128 (const_string "fp")
10129 (const_string "*")])])
10131 (define_split
10132 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10133 (match_operand:DI 1 "const_int_operand" ""))]
10134 "! TARGET_POWERPC64 && reload_completed
10135 && gpr_or_gpr_p (operands[0], operands[1])
10136 && !direct_move_p (operands[0], operands[1])"
10137 [(set (match_dup 2) (match_dup 4))
10138 (set (match_dup 3) (match_dup 1))]
10139 "
10140 {
10141 HOST_WIDE_INT value = INTVAL (operands[1]);
10142 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10143 DImode);
10144 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10145 DImode);
10146 operands[4] = GEN_INT (value >> 32);
10147 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
10148 }")
10150 (define_split
10151 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
10152 (match_operand:DIFD 1 "input_operand" ""))]
10153 "reload_completed && !TARGET_POWERPC64
10154 && gpr_or_gpr_p (operands[0], operands[1])
10155 && !direct_move_p (operands[0], operands[1])"
10156 [(pc)]
10157 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10159 (define_insn "*movdi_internal64"
10160 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm")
10161 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))]
10162 "TARGET_POWERPC64
10163 && (gpc_reg_operand (operands[0], DImode)
10164 || gpc_reg_operand (operands[1], DImode))"
10165 "@
10166 std%U0%X0 %1,%0
10167 ld%U1%X1 %0,%1
10168 mr %0,%1
10169 li %0,%1
10170 lis %0,%v1
10171 #
10172 stfd%U0%X0 %1,%0
10173 lfd%U1%X1 %0,%1
10174 fmr %0,%1
10175 mf%1 %0
10176 mt%0 %1
10177 nop
10178 mftgpr %0,%1
10179 mffgpr %0,%1
10180 mfvsrd %0,%x1
10181 mtvsrd %x0,%1"
10182 [(set_attr_alternative "type"
10183 [(if_then_else
10184 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10185 (const_string "store_ux")
10186 (if_then_else
10187 (match_test "update_address_mem (operands[0], VOIDmode)")
10188 (const_string "store_u")
10189 (const_string "store")))
10190 (if_then_else
10191 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10192 (const_string "load_ux")
10193 (if_then_else
10194 (match_test "update_address_mem (operands[1], VOIDmode)")
10195 (const_string "load_u")
10196 (const_string "load")))
10197 (const_string "*")
10198 (const_string "*")
10199 (const_string "*")
10200 (const_string "*")
10201 (if_then_else
10202 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
10203 (const_string "fpstore_ux")
10204 (if_then_else
10205 (match_test "update_address_mem (operands[0], VOIDmode)")
10206 (const_string "fpstore_u")
10207 (const_string "fpstore")))
10208 (if_then_else
10209 (match_test "update_indexed_address_mem (operands[1], VOIDmode)")
10210 (const_string "fpload_ux")
10211 (if_then_else
10212 (match_test "update_address_mem (operands[1], VOIDmode)")
10213 (const_string "fpload_u")
10214 (const_string "fpload")))
10215 (const_string "fp")
10216 (const_string "mfjmpr")
10217 (const_string "mtjmpr")
10218 (const_string "*")
10219 (const_string "mftgpr")
10220 (const_string "mffgpr")
10221 (const_string "mftgpr")
10222 (const_string "mffgpr")])
10223 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")])
10225 ;; Generate all one-bits and clear left or right.
10226 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
10227 (define_split
10228 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10229 (match_operand:DI 1 "mask64_operand" ""))]
10230 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10231 [(set (match_dup 0) (const_int -1))
10232 (set (match_dup 0)
10233 (and:DI (rotate:DI (match_dup 0)
10234 (const_int 0))
10235 (match_dup 1)))]
10236 "")
10238 ;; Split a load of a large constant into the appropriate five-instruction
10239 ;; sequence. Handle anything in a constant number of insns.
10240 ;; When non-easy constants can go in the TOC, this should use
10241 ;; easy_fp_constant predicate.
10242 (define_split
10243 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10244 (match_operand:DI 1 "const_int_operand" ""))]
10245 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10246 [(set (match_dup 0) (match_dup 2))
10247 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10248 "
10249 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10251 if (tem == operands[0])
10252 DONE;
10253 else
10254 FAIL;
10255 }")
10257 (define_split
10258 [(set (match_operand:DI 0 "gpc_reg_operand" "")
10259 (match_operand:DI 1 "const_double_operand" ""))]
10260 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
10261 [(set (match_dup 0) (match_dup 2))
10262 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
10263 "
10264 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
10266 if (tem == operands[0])
10267 DONE;
10268 else
10269 FAIL;
10270 }")
10271 \f
10272 ;; TImode/PTImode is similar, except that we usually want to compute the
10273 ;; address into a register and use lsi/stsi (the exception is during reload).
10275 (define_insn "*mov<mode>_string"
10276 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
10277 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))]
10278 "! TARGET_POWERPC64
10279 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode))
10280 && (gpc_reg_operand (operands[0], <MODE>mode)
10281 || gpc_reg_operand (operands[1], <MODE>mode))"
10282 "*
10283 {
10284 switch (which_alternative)
10285 {
10286 default:
10287 gcc_unreachable ();
10288 case 0:
10289 if (TARGET_STRING)
10290 return \"stswi %1,%P0,16\";
10291 case 1:
10292 return \"#\";
10293 case 2:
10294 /* If the address is not used in the output, we can use lsi. Otherwise,
10295 fall through to generating four loads. */
10296 if (TARGET_STRING
10297 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
10298 return \"lswi %0,%P1,16\";
10299 /* ... fall through ... */
10300 case 3:
10301 case 4:
10302 case 5:
10303 return \"#\";
10304 }
10305 }"
10306 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
10307 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
10308 (const_string "always")
10309 (const_string "conditional")))])
10311 (define_insn "*mov<mode>_ppc64"
10312 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r")
10313 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))]
10314 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode)
10315 && (gpc_reg_operand (operands[0], <MODE>mode)
10316 || gpc_reg_operand (operands[1], <MODE>mode)))"
10317 {
10318 return rs6000_output_move_128bit (operands);
10319 }
10320 [(set_attr "type" "store,store,load,load,*,*")
10321 (set_attr "length" "8")])
10323 (define_split
10324 [(set (match_operand:TI2 0 "int_reg_operand" "")
10325 (match_operand:TI2 1 "const_double_operand" ""))]
10326 "TARGET_POWERPC64
10327 && (VECTOR_MEM_NONE_P (<MODE>mode)
10328 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))"
10329 [(set (match_dup 2) (match_dup 4))
10330 (set (match_dup 3) (match_dup 5))]
10331 "
10332 {
10333 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
10334 <MODE>mode);
10335 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
10336 <MODE>mode);
10337 if (GET_CODE (operands[1]) == CONST_DOUBLE)
10338 {
10339 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
10340 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
10341 }
10342 else if (GET_CODE (operands[1]) == CONST_INT)
10343 {
10344 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
10345 operands[5] = operands[1];
10346 }
10347 else
10348 FAIL;
10349 }")
10351 (define_split
10352 [(set (match_operand:TI2 0 "nonimmediate_operand" "")
10353 (match_operand:TI2 1 "input_operand" ""))]
10354 "reload_completed
10355 && gpr_or_gpr_p (operands[0], operands[1])
10356 && !direct_move_p (operands[0], operands[1])
10357 && !quad_load_store_p (operands[0], operands[1])"
10358 [(pc)]
10359 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
10360 \f
10361 (define_expand "load_multiple"
10362 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10363 (match_operand:SI 1 "" ""))
10364 (use (match_operand:SI 2 "" ""))])]
10365 "TARGET_STRING && !TARGET_POWERPC64"
10366 "
10367 {
10368 int regno;
10369 int count;
10370 rtx op1;
10371 int i;
10373 /* Support only loading a constant number of fixed-point registers from
10374 memory and only bother with this if more than two; the machine
10375 doesn't support more than eight. */
10376 if (GET_CODE (operands[2]) != CONST_INT
10377 || INTVAL (operands[2]) <= 2
10378 || INTVAL (operands[2]) > 8
10379 || GET_CODE (operands[1]) != MEM
10380 || GET_CODE (operands[0]) != REG
10381 || REGNO (operands[0]) >= 32)
10382 FAIL;
10384 count = INTVAL (operands[2]);
10385 regno = REGNO (operands[0]);
10387 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
10388 op1 = replace_equiv_address (operands[1],
10389 force_reg (SImode, XEXP (operands[1], 0)));
10391 for (i = 0; i < count; i++)
10392 XVECEXP (operands[3], 0, i)
10393 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
10394 adjust_address_nv (op1, SImode, i * 4));
10395 }")
10397 (define_insn "*ldmsi8"
10398 [(match_parallel 0 "load_multiple_operation"
10399 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10400 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10401 (set (match_operand:SI 3 "gpc_reg_operand" "")
10402 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10403 (set (match_operand:SI 4 "gpc_reg_operand" "")
10404 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10405 (set (match_operand:SI 5 "gpc_reg_operand" "")
10406 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10407 (set (match_operand:SI 6 "gpc_reg_operand" "")
10408 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10409 (set (match_operand:SI 7 "gpc_reg_operand" "")
10410 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10411 (set (match_operand:SI 8 "gpc_reg_operand" "")
10412 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
10413 (set (match_operand:SI 9 "gpc_reg_operand" "")
10414 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
10415 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10416 "*
10417 { return rs6000_output_load_multiple (operands); }"
10418 [(set_attr "type" "load_ux")
10419 (set_attr "length" "32")])
10421 (define_insn "*ldmsi7"
10422 [(match_parallel 0 "load_multiple_operation"
10423 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10424 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10425 (set (match_operand:SI 3 "gpc_reg_operand" "")
10426 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10427 (set (match_operand:SI 4 "gpc_reg_operand" "")
10428 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10429 (set (match_operand:SI 5 "gpc_reg_operand" "")
10430 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10431 (set (match_operand:SI 6 "gpc_reg_operand" "")
10432 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10433 (set (match_operand:SI 7 "gpc_reg_operand" "")
10434 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
10435 (set (match_operand:SI 8 "gpc_reg_operand" "")
10436 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
10437 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10438 "*
10439 { return rs6000_output_load_multiple (operands); }"
10440 [(set_attr "type" "load_ux")
10441 (set_attr "length" "32")])
10443 (define_insn "*ldmsi6"
10444 [(match_parallel 0 "load_multiple_operation"
10445 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10446 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10447 (set (match_operand:SI 3 "gpc_reg_operand" "")
10448 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10449 (set (match_operand:SI 4 "gpc_reg_operand" "")
10450 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10451 (set (match_operand:SI 5 "gpc_reg_operand" "")
10452 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10453 (set (match_operand:SI 6 "gpc_reg_operand" "")
10454 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
10455 (set (match_operand:SI 7 "gpc_reg_operand" "")
10456 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
10457 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10458 "*
10459 { return rs6000_output_load_multiple (operands); }"
10460 [(set_attr "type" "load_ux")
10461 (set_attr "length" "32")])
10463 (define_insn "*ldmsi5"
10464 [(match_parallel 0 "load_multiple_operation"
10465 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10466 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10467 (set (match_operand:SI 3 "gpc_reg_operand" "")
10468 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10469 (set (match_operand:SI 4 "gpc_reg_operand" "")
10470 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10471 (set (match_operand:SI 5 "gpc_reg_operand" "")
10472 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
10473 (set (match_operand:SI 6 "gpc_reg_operand" "")
10474 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
10475 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10476 "*
10477 { return rs6000_output_load_multiple (operands); }"
10478 [(set_attr "type" "load_ux")
10479 (set_attr "length" "32")])
10481 (define_insn "*ldmsi4"
10482 [(match_parallel 0 "load_multiple_operation"
10483 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10484 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10485 (set (match_operand:SI 3 "gpc_reg_operand" "")
10486 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10487 (set (match_operand:SI 4 "gpc_reg_operand" "")
10488 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10489 (set (match_operand:SI 5 "gpc_reg_operand" "")
10490 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10491 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10492 "*
10493 { return rs6000_output_load_multiple (operands); }"
10494 [(set_attr "type" "load_ux")
10495 (set_attr "length" "32")])
10497 (define_insn "*ldmsi3"
10498 [(match_parallel 0 "load_multiple_operation"
10499 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10500 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10501 (set (match_operand:SI 3 "gpc_reg_operand" "")
10502 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10503 (set (match_operand:SI 4 "gpc_reg_operand" "")
10504 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10505 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10506 "*
10507 { return rs6000_output_load_multiple (operands); }"
10508 [(set_attr "type" "load_ux")
10509 (set_attr "length" "32")])
10511 (define_expand "store_multiple"
10512 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10513 (match_operand:SI 1 "" ""))
10514 (clobber (scratch:SI))
10515 (use (match_operand:SI 2 "" ""))])]
10516 "TARGET_STRING && !TARGET_POWERPC64"
10517 "
10518 {
10519 int regno;
10520 int count;
10521 rtx to;
10522 rtx op0;
10523 int i;
10525 /* Support only storing a constant number of fixed-point registers to
10526 memory and only bother with this if more than two; the machine
10527 doesn't support more than eight. */
10528 if (GET_CODE (operands[2]) != CONST_INT
10529 || INTVAL (operands[2]) <= 2
10530 || INTVAL (operands[2]) > 8
10531 || GET_CODE (operands[0]) != MEM
10532 || GET_CODE (operands[1]) != REG
10533 || REGNO (operands[1]) >= 32)
10534 FAIL;
10536 count = INTVAL (operands[2]);
10537 regno = REGNO (operands[1]);
10539 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10540 to = force_reg (SImode, XEXP (operands[0], 0));
10541 op0 = replace_equiv_address (operands[0], to);
10543 XVECEXP (operands[3], 0, 0)
10544 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10545 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10546 gen_rtx_SCRATCH (SImode));
10548 for (i = 1; i < count; i++)
10549 XVECEXP (operands[3], 0, i + 1)
10550 = gen_rtx_SET (VOIDmode,
10551 adjust_address_nv (op0, SImode, i * 4),
10552 gen_rtx_REG (SImode, regno + i));
10553 }")
10555 (define_insn "*stmsi8"
10556 [(match_parallel 0 "store_multiple_operation"
10557 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10558 (match_operand:SI 2 "gpc_reg_operand" "r"))
10559 (clobber (match_scratch:SI 3 "=X"))
10560 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10561 (match_operand:SI 4 "gpc_reg_operand" "r"))
10562 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10563 (match_operand:SI 5 "gpc_reg_operand" "r"))
10564 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10565 (match_operand:SI 6 "gpc_reg_operand" "r"))
10566 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10567 (match_operand:SI 7 "gpc_reg_operand" "r"))
10568 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10569 (match_operand:SI 8 "gpc_reg_operand" "r"))
10570 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10571 (match_operand:SI 9 "gpc_reg_operand" "r"))
10572 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10573 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10574 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
10575 "stswi %2,%1,%O0"
10576 [(set_attr "type" "store_ux")
10577 (set_attr "cell_micro" "always")])
10579 (define_insn "*stmsi7"
10580 [(match_parallel 0 "store_multiple_operation"
10581 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10582 (match_operand:SI 2 "gpc_reg_operand" "r"))
10583 (clobber (match_scratch:SI 3 "=X"))
10584 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10585 (match_operand:SI 4 "gpc_reg_operand" "r"))
10586 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10587 (match_operand:SI 5 "gpc_reg_operand" "r"))
10588 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10589 (match_operand:SI 6 "gpc_reg_operand" "r"))
10590 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10591 (match_operand:SI 7 "gpc_reg_operand" "r"))
10592 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10593 (match_operand:SI 8 "gpc_reg_operand" "r"))
10594 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10595 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10596 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
10597 "stswi %2,%1,%O0"
10598 [(set_attr "type" "store_ux")
10599 (set_attr "cell_micro" "always")])
10601 (define_insn "*stmsi6"
10602 [(match_parallel 0 "store_multiple_operation"
10603 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10604 (match_operand:SI 2 "gpc_reg_operand" "r"))
10605 (clobber (match_scratch:SI 3 "=X"))
10606 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10607 (match_operand:SI 4 "gpc_reg_operand" "r"))
10608 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10609 (match_operand:SI 5 "gpc_reg_operand" "r"))
10610 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10611 (match_operand:SI 6 "gpc_reg_operand" "r"))
10612 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10613 (match_operand:SI 7 "gpc_reg_operand" "r"))
10614 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10615 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10616 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
10617 "stswi %2,%1,%O0"
10618 [(set_attr "type" "store_ux")
10619 (set_attr "cell_micro" "always")])
10621 (define_insn "*stmsi5"
10622 [(match_parallel 0 "store_multiple_operation"
10623 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10624 (match_operand:SI 2 "gpc_reg_operand" "r"))
10625 (clobber (match_scratch:SI 3 "=X"))
10626 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10627 (match_operand:SI 4 "gpc_reg_operand" "r"))
10628 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10629 (match_operand:SI 5 "gpc_reg_operand" "r"))
10630 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10631 (match_operand:SI 6 "gpc_reg_operand" "r"))
10632 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10633 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10634 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
10635 "stswi %2,%1,%O0"
10636 [(set_attr "type" "store_ux")
10637 (set_attr "cell_micro" "always")])
10639 (define_insn "*stmsi4"
10640 [(match_parallel 0 "store_multiple_operation"
10641 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10642 (match_operand:SI 2 "gpc_reg_operand" "r"))
10643 (clobber (match_scratch:SI 3 "=X"))
10644 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10645 (match_operand:SI 4 "gpc_reg_operand" "r"))
10646 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10647 (match_operand:SI 5 "gpc_reg_operand" "r"))
10648 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10649 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10650 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
10651 "stswi %2,%1,%O0"
10652 [(set_attr "type" "store_ux")
10653 (set_attr "cell_micro" "always")])
10655 (define_insn "*stmsi3"
10656 [(match_parallel 0 "store_multiple_operation"
10657 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10658 (match_operand:SI 2 "gpc_reg_operand" "r"))
10659 (clobber (match_scratch:SI 3 "=X"))
10660 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10661 (match_operand:SI 4 "gpc_reg_operand" "r"))
10662 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10663 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10664 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10665 "stswi %2,%1,%O0"
10666 [(set_attr "type" "store_ux")
10667 (set_attr "cell_micro" "always")])
10668 \f
10669 (define_expand "setmemsi"
10670 [(parallel [(set (match_operand:BLK 0 "" "")
10671 (match_operand 2 "const_int_operand" ""))
10672 (use (match_operand:SI 1 "" ""))
10673 (use (match_operand:SI 3 "" ""))])]
10674 ""
10675 "
10676 {
10677 /* If value to set is not zero, use the library routine. */
10678 if (operands[2] != const0_rtx)
10679 FAIL;
10681 if (expand_block_clear (operands))
10682 DONE;
10683 else
10684 FAIL;
10685 }")
10687 ;; String/block move insn.
10688 ;; Argument 0 is the destination
10689 ;; Argument 1 is the source
10690 ;; Argument 2 is the length
10691 ;; Argument 3 is the alignment
10693 (define_expand "movmemsi"
10694 [(parallel [(set (match_operand:BLK 0 "" "")
10695 (match_operand:BLK 1 "" ""))
10696 (use (match_operand:SI 2 "" ""))
10697 (use (match_operand:SI 3 "" ""))])]
10698 ""
10699 "
10700 {
10701 if (expand_block_move (operands))
10702 DONE;
10703 else
10704 FAIL;
10705 }")
10707 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10708 ;; register allocator doesn't have a clue about allocating 8 word registers.
10709 ;; rD/rS = r5 is preferred, efficient form.
10710 (define_expand "movmemsi_8reg"
10711 [(parallel [(set (match_operand 0 "" "")
10712 (match_operand 1 "" ""))
10713 (use (match_operand 2 "" ""))
10714 (use (match_operand 3 "" ""))
10715 (clobber (reg:SI 5))
10716 (clobber (reg:SI 6))
10717 (clobber (reg:SI 7))
10718 (clobber (reg:SI 8))
10719 (clobber (reg:SI 9))
10720 (clobber (reg:SI 10))
10721 (clobber (reg:SI 11))
10722 (clobber (reg:SI 12))
10723 (clobber (match_scratch:SI 4 ""))])]
10724 "TARGET_STRING"
10725 "")
10727 (define_insn ""
10728 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10729 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10730 (use (match_operand:SI 2 "immediate_operand" "i"))
10731 (use (match_operand:SI 3 "immediate_operand" "i"))
10732 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10733 (clobber (reg:SI 6))
10734 (clobber (reg:SI 7))
10735 (clobber (reg:SI 8))
10736 (clobber (reg:SI 9))
10737 (clobber (reg:SI 10))
10738 (clobber (reg:SI 11))
10739 (clobber (reg:SI 12))
10740 (clobber (match_scratch:SI 5 "=X"))]
10741 "TARGET_STRING
10742 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10743 || INTVAL (operands[2]) == 0)
10744 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10745 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10746 && REGNO (operands[4]) == 5"
10747 "lswi %4,%1,%2\;stswi %4,%0,%2"
10748 [(set_attr "type" "store_ux")
10749 (set_attr "cell_micro" "always")
10750 (set_attr "length" "8")])
10752 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10753 ;; register allocator doesn't have a clue about allocating 6 word registers.
10754 ;; rD/rS = r5 is preferred, efficient form.
10755 (define_expand "movmemsi_6reg"
10756 [(parallel [(set (match_operand 0 "" "")
10757 (match_operand 1 "" ""))
10758 (use (match_operand 2 "" ""))
10759 (use (match_operand 3 "" ""))
10760 (clobber (reg:SI 5))
10761 (clobber (reg:SI 6))
10762 (clobber (reg:SI 7))
10763 (clobber (reg:SI 8))
10764 (clobber (reg:SI 9))
10765 (clobber (reg:SI 10))
10766 (clobber (match_scratch:SI 4 ""))])]
10767 "TARGET_STRING"
10768 "")
10770 (define_insn ""
10771 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10772 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10773 (use (match_operand:SI 2 "immediate_operand" "i"))
10774 (use (match_operand:SI 3 "immediate_operand" "i"))
10775 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10776 (clobber (reg:SI 6))
10777 (clobber (reg:SI 7))
10778 (clobber (reg:SI 8))
10779 (clobber (reg:SI 9))
10780 (clobber (reg:SI 10))
10781 (clobber (match_scratch:SI 5 "=X"))]
10782 "TARGET_STRING
10783 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10784 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10785 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10786 && REGNO (operands[4]) == 5"
10787 "lswi %4,%1,%2\;stswi %4,%0,%2"
10788 [(set_attr "type" "store_ux")
10789 (set_attr "cell_micro" "always")
10790 (set_attr "length" "8")])
10792 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10793 ;; problems with TImode.
10794 ;; rD/rS = r5 is preferred, efficient form.
10795 (define_expand "movmemsi_4reg"
10796 [(parallel [(set (match_operand 0 "" "")
10797 (match_operand 1 "" ""))
10798 (use (match_operand 2 "" ""))
10799 (use (match_operand 3 "" ""))
10800 (clobber (reg:SI 5))
10801 (clobber (reg:SI 6))
10802 (clobber (reg:SI 7))
10803 (clobber (reg:SI 8))
10804 (clobber (match_scratch:SI 4 ""))])]
10805 "TARGET_STRING"
10806 "")
10808 (define_insn ""
10809 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10810 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10811 (use (match_operand:SI 2 "immediate_operand" "i"))
10812 (use (match_operand:SI 3 "immediate_operand" "i"))
10813 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10814 (clobber (reg:SI 6))
10815 (clobber (reg:SI 7))
10816 (clobber (reg:SI 8))
10817 (clobber (match_scratch:SI 5 "=X"))]
10818 "TARGET_STRING
10819 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10820 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10821 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10822 && REGNO (operands[4]) == 5"
10823 "lswi %4,%1,%2\;stswi %4,%0,%2"
10824 [(set_attr "type" "store_ux")
10825 (set_attr "cell_micro" "always")
10826 (set_attr "length" "8")])
10828 ;; Move up to 8 bytes at a time.
10829 (define_expand "movmemsi_2reg"
10830 [(parallel [(set (match_operand 0 "" "")
10831 (match_operand 1 "" ""))
10832 (use (match_operand 2 "" ""))
10833 (use (match_operand 3 "" ""))
10834 (clobber (match_scratch:DI 4 ""))
10835 (clobber (match_scratch:SI 5 ""))])]
10836 "TARGET_STRING && ! TARGET_POWERPC64"
10837 "")
10839 (define_insn ""
10840 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10841 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10842 (use (match_operand:SI 2 "immediate_operand" "i"))
10843 (use (match_operand:SI 3 "immediate_operand" "i"))
10844 (clobber (match_scratch:DI 4 "=&r"))
10845 (clobber (match_scratch:SI 5 "=X"))]
10846 "TARGET_STRING && ! TARGET_POWERPC64
10847 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10848 "lswi %4,%1,%2\;stswi %4,%0,%2"
10849 [(set_attr "type" "store_ux")
10850 (set_attr "cell_micro" "always")
10851 (set_attr "length" "8")])
10853 ;; Move up to 4 bytes at a time.
10854 (define_expand "movmemsi_1reg"
10855 [(parallel [(set (match_operand 0 "" "")
10856 (match_operand 1 "" ""))
10857 (use (match_operand 2 "" ""))
10858 (use (match_operand 3 "" ""))
10859 (clobber (match_scratch:SI 4 ""))
10860 (clobber (match_scratch:SI 5 ""))])]
10861 "TARGET_STRING"
10862 "")
10864 (define_insn ""
10865 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10866 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10867 (use (match_operand:SI 2 "immediate_operand" "i"))
10868 (use (match_operand:SI 3 "immediate_operand" "i"))
10869 (clobber (match_scratch:SI 4 "=&r"))
10870 (clobber (match_scratch:SI 5 "=X"))]
10871 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10872 "lswi %4,%1,%2\;stswi %4,%0,%2"
10873 [(set_attr "type" "store_ux")
10874 (set_attr "cell_micro" "always")
10875 (set_attr "length" "8")])
10876 \f
10877 ;; Define insns that do load or store with update. Some of these we can
10878 ;; get by using pre-decrement or pre-increment, but the hardware can also
10879 ;; do cases where the increment is not the size of the object.
10880 ;;
10881 ;; In all these cases, we use operands 0 and 1 for the register being
10882 ;; incremented because those are the operands that local-alloc will
10883 ;; tie and these are the pair most likely to be tieable (and the ones
10884 ;; that will benefit the most).
10886 (define_insn "*movdi_update1"
10887 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10888 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10889 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10890 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10891 (plus:DI (match_dup 1) (match_dup 2)))]
10892 "TARGET_POWERPC64 && TARGET_UPDATE
10893 && (!avoiding_indexed_address_p (DImode)
10894 || !gpc_reg_operand (operands[2], DImode))"
10895 "@
10896 ldux %3,%0,%2
10897 ldu %3,%2(%0)"
10898 [(set_attr "type" "load_ux,load_u")])
10900 (define_insn "movdi_<mode>_update"
10901 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10902 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10903 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10904 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10905 (plus:P (match_dup 1) (match_dup 2)))]
10906 "TARGET_POWERPC64 && TARGET_UPDATE
10907 && (!avoiding_indexed_address_p (Pmode)
10908 || !gpc_reg_operand (operands[2], Pmode)
10909 || (REG_P (operands[0])
10910 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10911 "@
10912 stdux %3,%0,%2
10913 stdu %3,%2(%0)"
10914 [(set_attr "type" "store_ux,store_u")])
10916 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10917 ;; needed for stack allocation, even if the user passes -mno-update.
10918 (define_insn "movdi_<mode>_update_stack"
10919 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10920 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10921 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10922 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10923 (plus:P (match_dup 1) (match_dup 2)))]
10924 "TARGET_POWERPC64"
10925 "@
10926 stdux %3,%0,%2
10927 stdu %3,%2(%0)"
10928 [(set_attr "type" "store_ux,store_u")])
10930 (define_insn "*movsi_update1"
10931 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10932 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10933 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10934 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10935 (plus:SI (match_dup 1) (match_dup 2)))]
10936 "TARGET_UPDATE
10937 && (!avoiding_indexed_address_p (SImode)
10938 || !gpc_reg_operand (operands[2], SImode))"
10939 "@
10940 lwzux %3,%0,%2
10941 lwzu %3,%2(%0)"
10942 [(set_attr "type" "load_ux,load_u")])
10944 (define_insn "*movsi_update2"
10945 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10946 (sign_extend:DI
10947 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10948 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10949 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10950 (plus:DI (match_dup 1) (match_dup 2)))]
10951 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10952 && !avoiding_indexed_address_p (DImode)"
10953 "lwaux %3,%0,%2"
10954 [(set_attr "type" "load_ext_ux")])
10956 (define_insn "movsi_update"
10957 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10958 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10959 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10960 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10961 (plus:SI (match_dup 1) (match_dup 2)))]
10962 "TARGET_UPDATE
10963 && (!avoiding_indexed_address_p (SImode)
10964 || !gpc_reg_operand (operands[2], SImode)
10965 || (REG_P (operands[0])
10966 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10967 "@
10968 stwux %3,%0,%2
10969 stwu %3,%2(%0)"
10970 [(set_attr "type" "store_ux,store_u")])
10972 ;; This is an unconditional pattern; needed for stack allocation, even
10973 ;; if the user passes -mno-update.
10974 (define_insn "movsi_update_stack"
10975 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10976 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10977 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10978 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10979 (plus:SI (match_dup 1) (match_dup 2)))]
10980 ""
10981 "@
10982 stwux %3,%0,%2
10983 stwu %3,%2(%0)"
10984 [(set_attr "type" "store_ux,store_u")])
10986 (define_insn "*movhi_update1"
10987 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10988 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10989 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10990 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10991 (plus:SI (match_dup 1) (match_dup 2)))]
10992 "TARGET_UPDATE
10993 && (!avoiding_indexed_address_p (SImode)
10994 || !gpc_reg_operand (operands[2], SImode))"
10995 "@
10996 lhzux %3,%0,%2
10997 lhzu %3,%2(%0)"
10998 [(set_attr "type" "load_ux,load_u")])
11000 (define_insn "*movhi_update2"
11001 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11002 (zero_extend:SI
11003 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11004 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11005 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11006 (plus:SI (match_dup 1) (match_dup 2)))]
11007 "TARGET_UPDATE
11008 && (!avoiding_indexed_address_p (SImode)
11009 || !gpc_reg_operand (operands[2], SImode))"
11010 "@
11011 lhzux %3,%0,%2
11012 lhzu %3,%2(%0)"
11013 [(set_attr "type" "load_ux,load_u")])
11015 (define_insn "*movhi_update3"
11016 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11017 (sign_extend:SI
11018 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11019 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11020 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11021 (plus:SI (match_dup 1) (match_dup 2)))]
11022 "TARGET_UPDATE && rs6000_gen_cell_microcode
11023 && (!avoiding_indexed_address_p (SImode)
11024 || !gpc_reg_operand (operands[2], SImode))"
11025 "@
11026 lhaux %3,%0,%2
11027 lhau %3,%2(%0)"
11028 [(set_attr "type" "load_ext_ux,load_ext_u")])
11030 (define_insn "*movhi_update4"
11031 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11032 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11033 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
11034 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11035 (plus:SI (match_dup 1) (match_dup 2)))]
11036 "TARGET_UPDATE
11037 && (!avoiding_indexed_address_p (SImode)
11038 || !gpc_reg_operand (operands[2], SImode))"
11039 "@
11040 sthux %3,%0,%2
11041 sthu %3,%2(%0)"
11042 [(set_attr "type" "store_ux,store_u")])
11044 (define_insn "*movqi_update1"
11045 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
11046 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11047 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11048 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11049 (plus:SI (match_dup 1) (match_dup 2)))]
11050 "TARGET_UPDATE
11051 && (!avoiding_indexed_address_p (SImode)
11052 || !gpc_reg_operand (operands[2], SImode))"
11053 "@
11054 lbzux %3,%0,%2
11055 lbzu %3,%2(%0)"
11056 [(set_attr "type" "load_ux,load_u")])
11058 (define_insn "*movqi_update2"
11059 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11060 (zero_extend:SI
11061 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11062 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
11063 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11064 (plus:SI (match_dup 1) (match_dup 2)))]
11065 "TARGET_UPDATE
11066 && (!avoiding_indexed_address_p (SImode)
11067 || !gpc_reg_operand (operands[2], SImode))"
11068 "@
11069 lbzux %3,%0,%2
11070 lbzu %3,%2(%0)"
11071 [(set_attr "type" "load_ux,load_u")])
11073 (define_insn "*movqi_update3"
11074 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11075 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11076 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
11077 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11078 (plus:SI (match_dup 1) (match_dup 2)))]
11079 "TARGET_UPDATE
11080 && (!avoiding_indexed_address_p (SImode)
11081 || !gpc_reg_operand (operands[2], SImode))"
11082 "@
11083 stbux %3,%0,%2
11084 stbu %3,%2(%0)"
11085 [(set_attr "type" "store_ux,store_u")])
11087 (define_insn "*movsf_update1"
11088 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
11089 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11090 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11091 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11092 (plus:SI (match_dup 1) (match_dup 2)))]
11093 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11094 && (!avoiding_indexed_address_p (SImode)
11095 || !gpc_reg_operand (operands[2], SImode))"
11096 "@
11097 lfsux %3,%0,%2
11098 lfsu %3,%2(%0)"
11099 [(set_attr "type" "fpload_ux,fpload_u")])
11101 (define_insn "*movsf_update2"
11102 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11103 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11104 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
11105 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11106 (plus:SI (match_dup 1) (match_dup 2)))]
11107 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
11108 && (!avoiding_indexed_address_p (SImode)
11109 || !gpc_reg_operand (operands[2], SImode))"
11110 "@
11111 stfsux %3,%0,%2
11112 stfsu %3,%2(%0)"
11113 [(set_attr "type" "fpstore_ux,fpstore_u")])
11115 (define_insn "*movsf_update3"
11116 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
11117 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11118 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11119 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11120 (plus:SI (match_dup 1) (match_dup 2)))]
11121 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11122 && (!avoiding_indexed_address_p (SImode)
11123 || !gpc_reg_operand (operands[2], SImode))"
11124 "@
11125 lwzux %3,%0,%2
11126 lwzu %3,%2(%0)"
11127 [(set_attr "type" "load_ux,load_u")])
11129 (define_insn "*movsf_update4"
11130 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11131 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11132 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
11133 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11134 (plus:SI (match_dup 1) (match_dup 2)))]
11135 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
11136 && (!avoiding_indexed_address_p (SImode)
11137 || !gpc_reg_operand (operands[2], SImode))"
11138 "@
11139 stwux %3,%0,%2
11140 stwu %3,%2(%0)"
11141 [(set_attr "type" "store_ux,store_u")])
11143 (define_insn "*movdf_update1"
11144 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
11145 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11146 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
11147 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11148 (plus:SI (match_dup 1) (match_dup 2)))]
11149 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11150 && (!avoiding_indexed_address_p (SImode)
11151 || !gpc_reg_operand (operands[2], SImode))"
11152 "@
11153 lfdux %3,%0,%2
11154 lfdu %3,%2(%0)"
11155 [(set_attr "type" "fpload_ux,fpload_u")])
11157 (define_insn "*movdf_update2"
11158 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
11159 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
11160 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
11161 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
11162 (plus:SI (match_dup 1) (match_dup 2)))]
11163 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
11164 && (!avoiding_indexed_address_p (SImode)
11165 || !gpc_reg_operand (operands[2], SImode))"
11166 "@
11167 stfdux %3,%0,%2
11168 stfdu %3,%2(%0)"
11169 [(set_attr "type" "fpstore_ux,fpstore_u")])
11172 ;; After inserting conditional returns we can sometimes have
11173 ;; unnecessary register moves. Unfortunately we cannot have a
11174 ;; modeless peephole here, because some single SImode sets have early
11175 ;; clobber outputs. Although those sets expand to multi-ppc-insn
11176 ;; sequences, using get_attr_length here will smash the operands
11177 ;; array. Neither is there an early_cobbler_p predicate.
11178 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
11179 (define_peephole2
11180 [(set (match_operand:DF 0 "gpc_reg_operand" "")
11181 (match_operand:DF 1 "any_operand" ""))
11182 (set (match_operand:DF 2 "gpc_reg_operand" "")
11183 (match_dup 0))]
11184 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
11185 && peep2_reg_dead_p (2, operands[0])"
11186 [(set (match_dup 2) (match_dup 1))])
11188 (define_peephole2
11189 [(set (match_operand:SF 0 "gpc_reg_operand" "")
11190 (match_operand:SF 1 "any_operand" ""))
11191 (set (match_operand:SF 2 "gpc_reg_operand" "")
11192 (match_dup 0))]
11193 "peep2_reg_dead_p (2, operands[0])"
11194 [(set (match_dup 2) (match_dup 1))])
11196 \f
11197 ;; TLS support.
11199 ;; Mode attributes for different ABIs.
11200 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
11201 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
11202 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
11203 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
11205 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
11206 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11207 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11208 (match_operand 4 "" "g")))
11209 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11210 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11211 UNSPEC_TLSGD)
11212 (clobber (reg:SI LR_REGNO))]
11213 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11214 {
11215 if (TARGET_CMODEL != CMODEL_SMALL)
11216 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;"
11217 "bl %z3\;nop";
11218 else
11219 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop";
11220 }
11221 "&& TARGET_TLS_MARKERS"
11222 [(set (match_dup 0)
11223 (unspec:TLSmode [(match_dup 1)
11224 (match_dup 2)]
11225 UNSPEC_TLSGD))
11226 (parallel [(set (match_dup 0)
11227 (call (mem:TLSmode (match_dup 3))
11228 (match_dup 4)))
11229 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11230 (clobber (reg:SI LR_REGNO))])]
11231 ""
11232 [(set_attr "type" "two")
11233 (set (attr "length")
11234 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11235 (const_int 16)
11236 (const_int 12)))])
11238 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
11239 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11240 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11241 (match_operand 4 "" "g")))
11242 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11243 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11244 UNSPEC_TLSGD)
11245 (clobber (reg:SI LR_REGNO))]
11246 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11247 {
11248 if (flag_pic)
11249 {
11250 if (TARGET_SECURE_PLT && flag_pic == 2)
11251 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11252 else
11253 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11254 }
11255 else
11256 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11257 }
11258 "&& TARGET_TLS_MARKERS"
11259 [(set (match_dup 0)
11260 (unspec:TLSmode [(match_dup 1)
11261 (match_dup 2)]
11262 UNSPEC_TLSGD))
11263 (parallel [(set (match_dup 0)
11264 (call (mem:TLSmode (match_dup 3))
11265 (match_dup 4)))
11266 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11267 (clobber (reg:SI LR_REGNO))])]
11268 ""
11269 [(set_attr "type" "two")
11270 (set_attr "length" "8")])
11272 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
11273 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11274 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11275 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11276 UNSPEC_TLSGD))]
11277 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11278 "addi %0,%1,%2@got@tlsgd"
11279 "&& TARGET_CMODEL != CMODEL_SMALL"
11280 [(set (match_dup 3)
11281 (high:TLSmode
11282 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
11283 (set (match_dup 0)
11284 (lo_sum:TLSmode (match_dup 3)
11285 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))]
11286 "
11287 {
11288 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11289 }"
11290 [(set (attr "length")
11291 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11292 (const_int 8)
11293 (const_int 4)))])
11295 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
11296 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11297 (high:TLSmode
11298 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11299 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11300 UNSPEC_TLSGD)))]
11301 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11302 "addis %0,%1,%2@got@tlsgd@ha"
11303 [(set_attr "length" "4")])
11305 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
11306 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11307 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11308 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11309 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11310 UNSPEC_TLSGD)))]
11311 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11312 "addi %0,%1,%2@got@tlsgd@l"
11313 [(set_attr "length" "4")])
11315 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11316 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11317 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11318 (match_operand 2 "" "g")))
11319 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11320 UNSPEC_TLSGD)
11321 (clobber (reg:SI LR_REGNO))]
11322 "HAVE_AS_TLS && TARGET_TLS_MARKERS
11323 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11324 "bl %z1(%3@tlsgd)\;nop"
11325 [(set_attr "type" "branch")
11326 (set_attr "length" "8")])
11328 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11329 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11330 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11331 (match_operand 2 "" "g")))
11332 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11333 UNSPEC_TLSGD)
11334 (clobber (reg:SI LR_REGNO))]
11335 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11336 {
11337 if (flag_pic)
11338 {
11339 if (TARGET_SECURE_PLT && flag_pic == 2)
11340 return "bl %z1+32768(%3@tlsgd)@plt";
11341 return "bl %z1(%3@tlsgd)@plt";
11342 }
11343 return "bl %z1(%3@tlsgd)";
11344 }
11345 [(set_attr "type" "branch")
11346 (set_attr "length" "4")])
11348 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11349 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11350 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11351 (match_operand 3 "" "g")))
11352 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11353 UNSPEC_TLSLD)
11354 (clobber (reg:SI LR_REGNO))]
11355 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11356 {
11357 if (TARGET_CMODEL != CMODEL_SMALL)
11358 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;"
11359 "bl %z2\;nop";
11360 else
11361 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop";
11362 }
11363 "&& TARGET_TLS_MARKERS"
11364 [(set (match_dup 0)
11365 (unspec:TLSmode [(match_dup 1)]
11366 UNSPEC_TLSLD))
11367 (parallel [(set (match_dup 0)
11368 (call (mem:TLSmode (match_dup 2))
11369 (match_dup 3)))
11370 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11371 (clobber (reg:SI LR_REGNO))])]
11372 ""
11373 [(set_attr "type" "two")
11374 (set (attr "length")
11375 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11376 (const_int 16)
11377 (const_int 12)))])
11379 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11380 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11381 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11382 (match_operand 3 "" "g")))
11383 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11384 UNSPEC_TLSLD)
11385 (clobber (reg:SI LR_REGNO))]
11386 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11387 {
11388 if (flag_pic)
11389 {
11390 if (TARGET_SECURE_PLT && flag_pic == 2)
11391 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11392 else
11393 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11394 }
11395 else
11396 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11397 }
11398 "&& TARGET_TLS_MARKERS"
11399 [(set (match_dup 0)
11400 (unspec:TLSmode [(match_dup 1)]
11401 UNSPEC_TLSLD))
11402 (parallel [(set (match_dup 0)
11403 (call (mem:TLSmode (match_dup 2))
11404 (match_dup 3)))
11405 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11406 (clobber (reg:SI LR_REGNO))])]
11407 ""
11408 [(set_attr "length" "8")])
11410 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
11411 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11412 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11413 UNSPEC_TLSLD))]
11414 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11415 "addi %0,%1,%&@got@tlsld"
11416 "&& TARGET_CMODEL != CMODEL_SMALL"
11417 [(set (match_dup 2)
11418 (high:TLSmode
11419 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
11420 (set (match_dup 0)
11421 (lo_sum:TLSmode (match_dup 2)
11422 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))]
11423 "
11424 {
11425 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11426 }"
11427 [(set (attr "length")
11428 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11429 (const_int 8)
11430 (const_int 4)))])
11432 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
11433 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11434 (high:TLSmode
11435 (unspec:TLSmode [(const_int 0)
11436 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11437 UNSPEC_TLSLD)))]
11438 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11439 "addis %0,%1,%&@got@tlsld@ha"
11440 [(set_attr "length" "4")])
11442 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
11443 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11444 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11445 (unspec:TLSmode [(const_int 0)
11446 (match_operand:TLSmode 2 "gpc_reg_operand" "b")]
11447 UNSPEC_TLSLD)))]
11448 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
11449 "addi %0,%1,%&@got@tlsld@l"
11450 [(set_attr "length" "4")])
11452 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11453 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11454 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11455 (match_operand 2 "" "g")))
11456 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11457 (clobber (reg:SI LR_REGNO))]
11458 "HAVE_AS_TLS && TARGET_TLS_MARKERS
11459 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)"
11460 "bl %z1(%&@tlsld)\;nop"
11461 [(set_attr "type" "branch")
11462 (set_attr "length" "8")])
11464 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11465 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11466 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11467 (match_operand 2 "" "g")))
11468 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11469 (clobber (reg:SI LR_REGNO))]
11470 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11471 {
11472 if (flag_pic)
11473 {
11474 if (TARGET_SECURE_PLT && flag_pic == 2)
11475 return "bl %z1+32768(%&@tlsld)@plt";
11476 return "bl %z1(%&@tlsld)@plt";
11477 }
11478 return "bl %z1(%&@tlsld)";
11479 }
11480 [(set_attr "type" "branch")
11481 (set_attr "length" "4")])
11483 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11484 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11485 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11486 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11487 UNSPEC_TLSDTPREL))]
11488 "HAVE_AS_TLS"
11489 "addi %0,%1,%2@dtprel")
11491 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11492 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11493 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11494 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11495 UNSPEC_TLSDTPRELHA))]
11496 "HAVE_AS_TLS"
11497 "addis %0,%1,%2@dtprel@ha")
11499 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11500 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11501 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11502 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11503 UNSPEC_TLSDTPRELLO))]
11504 "HAVE_AS_TLS"
11505 "addi %0,%1,%2@dtprel@l")
11507 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11508 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11509 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11510 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11511 UNSPEC_TLSGOTDTPREL))]
11512 "HAVE_AS_TLS"
11513 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
11514 "&& TARGET_CMODEL != CMODEL_SMALL"
11515 [(set (match_dup 3)
11516 (high:TLSmode
11517 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
11518 (set (match_dup 0)
11519 (lo_sum:TLSmode (match_dup 3)
11520 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
11521 "
11522 {
11523 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11524 }"
11525 [(set (attr "length")
11526 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11527 (const_int 8)
11528 (const_int 4)))])
11530 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
11531 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11532 (high:TLSmode
11533 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11534 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11535 UNSPEC_TLSGOTDTPREL)))]
11536 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11537 "addis %0,%1,%2@got@dtprel@ha"
11538 [(set_attr "length" "4")])
11540 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
11541 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11542 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11543 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11544 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11545 UNSPEC_TLSGOTDTPREL)))]
11546 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11547 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
11548 [(set_attr "length" "4")])
11550 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11551 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11552 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11553 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11554 UNSPEC_TLSTPREL))]
11555 "HAVE_AS_TLS"
11556 "addi %0,%1,%2@tprel")
11558 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11559 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11560 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11561 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11562 UNSPEC_TLSTPRELHA))]
11563 "HAVE_AS_TLS"
11564 "addis %0,%1,%2@tprel@ha")
11566 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11567 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11568 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11569 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11570 UNSPEC_TLSTPRELLO))]
11571 "HAVE_AS_TLS"
11572 "addi %0,%1,%2@tprel@l")
11574 ;; "b" output constraint here and on tls_tls input to support linker tls
11575 ;; optimization. The linker may edit the instructions emitted by a
11576 ;; tls_got_tprel/tls_tls pair to addis,addi.
11577 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11578 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11579 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11580 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11581 UNSPEC_TLSGOTTPREL))]
11582 "HAVE_AS_TLS"
11583 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
11584 "&& TARGET_CMODEL != CMODEL_SMALL"
11585 [(set (match_dup 3)
11586 (high:TLSmode
11587 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
11588 (set (match_dup 0)
11589 (lo_sum:TLSmode (match_dup 3)
11590 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))]
11591 "
11592 {
11593 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
11594 }"
11595 [(set (attr "length")
11596 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
11597 (const_int 8)
11598 (const_int 4)))])
11600 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
11601 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11602 (high:TLSmode
11603 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11604 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11605 UNSPEC_TLSGOTTPREL)))]
11606 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11607 "addis %0,%1,%2@got@tprel@ha"
11608 [(set_attr "length" "4")])
11610 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
11611 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11612 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
11613 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b")
11614 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11615 UNSPEC_TLSGOTTPREL)))]
11616 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
11617 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
11618 [(set_attr "length" "4")])
11620 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11621 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11622 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11623 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11624 UNSPEC_TLSTLS))]
11625 "TARGET_ELF && HAVE_AS_TLS"
11626 "add %0,%1,%2@tls")
11628 (define_expand "tls_get_tpointer"
11629 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11630 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))]
11631 "TARGET_XCOFF && HAVE_AS_TLS"
11632 "
11633 {
11634 emit_insn (gen_tls_get_tpointer_internal ());
11635 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
11636 DONE;
11637 }")
11639 (define_insn "tls_get_tpointer_internal"
11640 [(set (reg:SI 3)
11641 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))
11642 (clobber (reg:SI LR_REGNO))]
11643 "TARGET_XCOFF && HAVE_AS_TLS"
11644 "bla __get_tpointer")
11646 (define_expand "tls_get_addr<mode>"
11647 [(set (match_operand:P 0 "gpc_reg_operand" "")
11648 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "")
11649 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))]
11650 "TARGET_XCOFF && HAVE_AS_TLS"
11651 "
11652 {
11653 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]);
11654 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]);
11655 emit_insn (gen_tls_get_addr_internal<mode> ());
11656 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3));
11657 DONE;
11658 }")
11660 (define_insn "tls_get_addr_internal<mode>"
11661 [(set (reg:P 3)
11662 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS))
11663 (clobber (reg:P 0))
11664 (clobber (reg:P 4))
11665 (clobber (reg:P 5))
11666 (clobber (reg:P 11))
11667 (clobber (reg:CC CR0_REGNO))
11668 (clobber (reg:P LR_REGNO))]
11669 "TARGET_XCOFF && HAVE_AS_TLS"
11670 "bla __tls_get_addr")
11671 \f
11672 ;; Next come insns related to the calling sequence.
11673 ;;
11674 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11675 ;; We move the back-chain and decrement the stack pointer.
11677 (define_expand "allocate_stack"
11678 [(set (match_operand 0 "gpc_reg_operand" "")
11679 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11680 (set (reg 1)
11681 (minus (reg 1) (match_dup 1)))]
11682 ""
11683 "
11684 { rtx chain = gen_reg_rtx (Pmode);
11685 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11686 rtx neg_op0;
11687 rtx insn, par, set, mem;
11689 emit_move_insn (chain, stack_bot);
11691 /* Check stack bounds if necessary. */
11692 if (crtl->limit_stack)
11693 {
11694 rtx available;
11695 available = expand_binop (Pmode, sub_optab,
11696 stack_pointer_rtx, stack_limit_rtx,
11697 NULL_RTX, 1, OPTAB_WIDEN);
11698 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11699 }
11701 if (GET_CODE (operands[1]) != CONST_INT
11702 || INTVAL (operands[1]) < -32767
11703 || INTVAL (operands[1]) > 32768)
11704 {
11705 neg_op0 = gen_reg_rtx (Pmode);
11706 if (TARGET_32BIT)
11707 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11708 else
11709 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11710 }
11711 else
11712 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11714 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11715 : gen_movdi_di_update_stack))
11716 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11717 chain));
11718 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11719 it now and set the alias set/attributes. The above gen_*_update
11720 calls will generate a PARALLEL with the MEM set being the first
11721 operation. */
11722 par = PATTERN (insn);
11723 gcc_assert (GET_CODE (par) == PARALLEL);
11724 set = XVECEXP (par, 0, 0);
11725 gcc_assert (GET_CODE (set) == SET);
11726 mem = SET_DEST (set);
11727 gcc_assert (MEM_P (mem));
11728 MEM_NOTRAP_P (mem) = 1;
11729 set_mem_alias_set (mem, get_frame_alias_set ());
11731 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11732 DONE;
11733 }")
11735 ;; These patterns say how to save and restore the stack pointer. We need not
11736 ;; save the stack pointer at function level since we are careful to
11737 ;; preserve the backchain. At block level, we have to restore the backchain
11738 ;; when we restore the stack pointer.
11739 ;;
11740 ;; For nonlocal gotos, we must save both the stack pointer and its
11741 ;; backchain and restore both. Note that in the nonlocal case, the
11742 ;; save area is a memory location.
11744 (define_expand "save_stack_function"
11745 [(match_operand 0 "any_operand" "")
11746 (match_operand 1 "any_operand" "")]
11747 ""
11748 "DONE;")
11750 (define_expand "restore_stack_function"
11751 [(match_operand 0 "any_operand" "")
11752 (match_operand 1 "any_operand" "")]
11753 ""
11754 "DONE;")
11756 ;; Adjust stack pointer (op0) to a new value (op1).
11757 ;; First copy old stack backchain to new location, and ensure that the
11758 ;; scheduler won't reorder the sp assignment before the backchain write.
11759 (define_expand "restore_stack_block"
11760 [(set (match_dup 2) (match_dup 3))
11761 (set (match_dup 4) (match_dup 2))
11762 (match_dup 5)
11763 (set (match_operand 0 "register_operand" "")
11764 (match_operand 1 "register_operand" ""))]
11765 ""
11766 "
11767 {
11768 rtvec p;
11770 operands[1] = force_reg (Pmode, operands[1]);
11771 operands[2] = gen_reg_rtx (Pmode);
11772 operands[3] = gen_frame_mem (Pmode, operands[0]);
11773 operands[4] = gen_frame_mem (Pmode, operands[1]);
11774 p = rtvec_alloc (1);
11775 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11776 gen_frame_mem (BLKmode, operands[0]),
11777 const0_rtx);
11778 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
11779 }")
11781 (define_expand "save_stack_nonlocal"
11782 [(set (match_dup 3) (match_dup 4))
11783 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11784 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11785 ""
11786 "
11787 {
11788 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11790 /* Copy the backchain to the first word, sp to the second. */
11791 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11792 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11793 operands[3] = gen_reg_rtx (Pmode);
11794 operands[4] = gen_frame_mem (Pmode, operands[1]);
11795 }")
11797 (define_expand "restore_stack_nonlocal"
11798 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11799 (set (match_dup 3) (match_dup 4))
11800 (set (match_dup 5) (match_dup 2))
11801 (match_dup 6)
11802 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11803 ""
11804 "
11805 {
11806 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11807 rtvec p;
11809 /* Restore the backchain from the first word, sp from the second. */
11810 operands[2] = gen_reg_rtx (Pmode);
11811 operands[3] = gen_reg_rtx (Pmode);
11812 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11813 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11814 operands[5] = gen_frame_mem (Pmode, operands[3]);
11815 p = rtvec_alloc (1);
11816 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
11817 gen_frame_mem (BLKmode, operands[0]),
11818 const0_rtx);
11819 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
11820 }")
11821 \f
11822 ;; TOC register handling.
11824 ;; Code to initialize the TOC register...
11826 (define_insn "load_toc_aix_si"
11827 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11828 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11829 (use (reg:SI 2))])]
11830 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT"
11831 "*
11832 {
11833 char buf[30];
11834 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11835 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11836 operands[2] = gen_rtx_REG (Pmode, 2);
11837 return \"lwz %0,%1(%2)\";
11838 }"
11839 [(set_attr "type" "load")])
11841 (define_insn "load_toc_aix_di"
11842 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11843 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11844 (use (reg:DI 2))])]
11845 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT"
11846 "*
11847 {
11848 char buf[30];
11849 #ifdef TARGET_RELOCATABLE
11850 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11851 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11852 #else
11853 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11854 #endif
11855 if (TARGET_ELF)
11856 strcat (buf, \"@toc\");
11857 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11858 operands[2] = gen_rtx_REG (Pmode, 2);
11859 return \"ld %0,%1(%2)\";
11860 }"
11861 [(set_attr "type" "load")])
11863 (define_insn "load_toc_v4_pic_si"
11864 [(set (reg:SI LR_REGNO)
11865 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11866 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11867 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11868 [(set_attr "type" "branch")
11869 (set_attr "length" "4")])
11871 (define_expand "load_toc_v4_PIC_1"
11872 [(parallel [(set (reg:SI LR_REGNO)
11873 (match_operand:SI 0 "immediate_operand" "s"))
11874 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
11875 "TARGET_ELF && DEFAULT_ABI == ABI_V4
11876 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11877 "")
11879 (define_insn "load_toc_v4_PIC_1_normal"
11880 [(set (reg:SI LR_REGNO)
11881 (match_operand:SI 0 "immediate_operand" "s"))
11882 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11883 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11884 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11885 "bcl 20,31,%0\\n%0:"
11886 [(set_attr "type" "branch")
11887 (set_attr "length" "4")])
11889 (define_insn "load_toc_v4_PIC_1_476"
11890 [(set (reg:SI LR_REGNO)
11891 (match_operand:SI 0 "immediate_operand" "s"))
11892 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11893 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4
11894 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11895 "*
11896 {
11897 char name[32];
11898 static char templ[32];
11900 get_ppc476_thunk_name (name);
11901 sprintf (templ, \"bl %s\\n%%0:\", name);
11902 return templ;
11903 }"
11904 [(set_attr "type" "branch")
11905 (set_attr "length" "4")])
11907 (define_expand "load_toc_v4_PIC_1b"
11908 [(parallel [(set (reg:SI LR_REGNO)
11909 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11910 (label_ref (match_operand 1 "" ""))]
11911 UNSPEC_TOCPTR))
11912 (match_dup 1)])]
11913 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11914 "")
11916 (define_insn "load_toc_v4_PIC_1b_normal"
11917 [(set (reg:SI LR_REGNO)
11918 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11919 (label_ref (match_operand 1 "" ""))]
11920 UNSPEC_TOCPTR))
11921 (match_dup 1)]
11922 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11923 "bcl 20,31,$+8\;.long %0-$"
11924 [(set_attr "type" "branch")
11925 (set_attr "length" "8")])
11927 (define_insn "load_toc_v4_PIC_1b_476"
11928 [(set (reg:SI LR_REGNO)
11929 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
11930 (label_ref (match_operand 1 "" ""))]
11931 UNSPEC_TOCPTR))
11932 (match_dup 1)]
11933 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11934 "*
11935 {
11936 char name[32];
11937 static char templ[32];
11939 get_ppc476_thunk_name (name);
11940 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
11941 return templ;
11942 }"
11943 [(set_attr "type" "branch")
11944 (set_attr "length" "16")])
11946 (define_insn "load_toc_v4_PIC_2"
11947 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11948 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11949 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11950 (match_operand:SI 3 "immediate_operand" "s")))))]
11951 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2"
11952 "lwz %0,%2-%3(%1)"
11953 [(set_attr "type" "load")])
11955 (define_insn "load_toc_v4_PIC_3b"
11956 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11957 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11958 (high:SI
11959 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11960 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11961 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11962 "addis %0,%1,%2-%3@ha")
11964 (define_insn "load_toc_v4_PIC_3c"
11965 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11966 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11967 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11968 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11969 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic"
11970 "addi %0,%1,%2-%3@l")
11972 ;; If the TOC is shared over a translation unit, as happens with all
11973 ;; the kinds of PIC that we support, we need to restore the TOC
11974 ;; pointer only when jumping over units of translation.
11975 ;; On Darwin, we need to reload the picbase.
11977 (define_expand "builtin_setjmp_receiver"
11978 [(use (label_ref (match_operand 0 "" "")))]
11979 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11980 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11981 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11982 "
11983 {
11984 #if TARGET_MACHO
11985 if (DEFAULT_ABI == ABI_DARWIN)
11986 {
11987 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11988 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11989 rtx tmplabrtx;
11990 char tmplab[20];
11992 crtl->uses_pic_offset_table = 1;
11993 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11994 CODE_LABEL_NUMBER (operands[0]));
11995 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11997 emit_insn (gen_load_macho_picbase (tmplabrtx));
11998 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11999 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
12000 }
12001 else
12002 #endif
12003 rs6000_emit_load_toc_table (FALSE);
12004 DONE;
12005 }")
12007 ;; Largetoc support
12008 (define_insn "*largetoc_high"
12009 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
12010 (high:DI
12011 (unspec [(match_operand:DI 1 "" "")
12012 (match_operand:DI 2 "gpc_reg_operand" "b")]
12013 UNSPEC_TOCREL)))]
12014 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12015 "addis %0,%2,%1@toc@ha")
12017 (define_insn "*largetoc_high_aix<mode>"
12018 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12019 (high:P
12020 (unspec [(match_operand:P 1 "" "")
12021 (match_operand:P 2 "gpc_reg_operand" "b")]
12022 UNSPEC_TOCREL)))]
12023 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
12024 "addis %0,%1@u(%2)")
12026 (define_insn "*largetoc_high_plus"
12027 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
12028 (high:DI
12029 (plus:DI
12030 (unspec [(match_operand:DI 1 "" "")
12031 (match_operand:DI 2 "gpc_reg_operand" "b")]
12032 UNSPEC_TOCREL)
12033 (match_operand:DI 3 "add_cint_operand" "n"))))]
12034 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12035 "addis %0,%2,%1+%3@toc@ha")
12037 (define_insn "*largetoc_high_plus_aix<mode>"
12038 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12039 (high:P
12040 (plus:P
12041 (unspec [(match_operand:P 1 "" "")
12042 (match_operand:P 2 "gpc_reg_operand" "b")]
12043 UNSPEC_TOCREL)
12044 (match_operand:P 3 "add_cint_operand" "n"))))]
12045 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
12046 "addis %0,%1+%3@u(%2)")
12048 (define_insn "*largetoc_low"
12049 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12050 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
12051 (match_operand:DI 2 "" "")))]
12052 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
12053 "@
12054 addi %0,%1,%2@l
12055 addic %0,%1,%2@l")
12057 (define_insn "*largetoc_low_aix<mode>"
12058 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12059 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b")
12060 (match_operand:P 2 "" "")))]
12061 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL"
12062 "la %0,%2@l(%1)")
12064 (define_insn_and_split "*tocref<mode>"
12065 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
12066 (match_operand:P 1 "small_toc_ref" "R"))]
12067 "TARGET_TOC"
12068 "la %0,%a1"
12069 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed"
12070 [(set (match_dup 0) (high:P (match_dup 1)))
12071 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
12073 ;; Elf specific ways of loading addresses for non-PIC code.
12074 ;; The output of this could be r0, but we make a very strong
12075 ;; preference for a base register because it will usually
12076 ;; be needed there.
12077 (define_insn "elf_high"
12078 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
12079 (high:SI (match_operand 1 "" "")))]
12080 "TARGET_ELF && ! TARGET_64BIT"
12081 "lis %0,%1@ha")
12083 (define_insn "elf_low"
12084 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12085 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
12086 (match_operand 2 "" "")))]
12087 "TARGET_ELF && ! TARGET_64BIT"
12088 "@
12089 la %0,%2@l(%1)
12090 addic %0,%1,%K2")
12091 \f
12092 ;; Call and call_value insns
12093 (define_expand "call"
12094 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12095 (match_operand 1 "" ""))
12096 (use (match_operand 2 "" ""))
12097 (clobber (reg:SI LR_REGNO))])]
12098 ""
12099 "
12100 {
12101 #if TARGET_MACHO
12102 if (MACHOPIC_INDIRECT)
12103 operands[0] = machopic_indirect_call_target (operands[0]);
12104 #endif
12106 gcc_assert (GET_CODE (operands[0]) == MEM);
12107 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12109 operands[0] = XEXP (operands[0], 0);
12111 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12112 {
12113 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]);
12114 DONE;
12115 }
12117 if (GET_CODE (operands[0]) != SYMBOL_REF
12118 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
12119 {
12120 if (INTVAL (operands[2]) & CALL_LONG)
12121 operands[0] = rs6000_longcall_ref (operands[0]);
12123 switch (DEFAULT_ABI)
12124 {
12125 case ABI_V4:
12126 case ABI_DARWIN:
12127 operands[0] = force_reg (Pmode, operands[0]);
12128 break;
12130 default:
12131 gcc_unreachable ();
12132 }
12133 }
12134 }")
12136 (define_expand "call_value"
12137 [(parallel [(set (match_operand 0 "" "")
12138 (call (mem:SI (match_operand 1 "address_operand" ""))
12139 (match_operand 2 "" "")))
12140 (use (match_operand 3 "" ""))
12141 (clobber (reg:SI LR_REGNO))])]
12142 ""
12143 "
12144 {
12145 #if TARGET_MACHO
12146 if (MACHOPIC_INDIRECT)
12147 operands[1] = machopic_indirect_call_target (operands[1]);
12148 #endif
12150 gcc_assert (GET_CODE (operands[1]) == MEM);
12151 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12153 operands[1] = XEXP (operands[1], 0);
12155 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12156 {
12157 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]);
12158 DONE;
12159 }
12161 if (GET_CODE (operands[1]) != SYMBOL_REF
12162 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
12163 {
12164 if (INTVAL (operands[3]) & CALL_LONG)
12165 operands[1] = rs6000_longcall_ref (operands[1]);
12167 switch (DEFAULT_ABI)
12168 {
12169 case ABI_V4:
12170 case ABI_DARWIN:
12171 operands[1] = force_reg (Pmode, operands[1]);
12172 break;
12174 default:
12175 gcc_unreachable ();
12176 }
12177 }
12178 }")
12180 ;; Call to function in current module. No TOC pointer reload needed.
12181 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
12182 ;; either the function was not prototyped, or it was prototyped as a
12183 ;; variable argument function. It is > 0 if FP registers were passed
12184 ;; and < 0 if they were not.
12186 (define_insn "*call_local32"
12187 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12188 (match_operand 1 "" "g,g"))
12189 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12190 (clobber (reg:SI LR_REGNO))]
12191 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12192 "*
12193 {
12194 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12195 output_asm_insn (\"crxor 6,6,6\", operands);
12197 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12198 output_asm_insn (\"creqv 6,6,6\", operands);
12200 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12201 }"
12202 [(set_attr "type" "branch")
12203 (set_attr "length" "4,8")])
12205 (define_insn "*call_local64"
12206 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12207 (match_operand 1 "" "g,g"))
12208 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12209 (clobber (reg:SI LR_REGNO))]
12210 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12211 "*
12212 {
12213 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12214 output_asm_insn (\"crxor 6,6,6\", operands);
12216 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12217 output_asm_insn (\"creqv 6,6,6\", operands);
12219 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
12220 }"
12221 [(set_attr "type" "branch")
12222 (set_attr "length" "4,8")])
12224 (define_insn "*call_value_local32"
12225 [(set (match_operand 0 "" "")
12226 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12227 (match_operand 2 "" "g,g")))
12228 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12229 (clobber (reg:SI LR_REGNO))]
12230 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12231 "*
12232 {
12233 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12234 output_asm_insn (\"crxor 6,6,6\", operands);
12236 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12237 output_asm_insn (\"creqv 6,6,6\", operands);
12239 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12240 }"
12241 [(set_attr "type" "branch")
12242 (set_attr "length" "4,8")])
12245 (define_insn "*call_value_local64"
12246 [(set (match_operand 0 "" "")
12247 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12248 (match_operand 2 "" "g,g")))
12249 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12250 (clobber (reg:SI LR_REGNO))]
12251 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12252 "*
12253 {
12254 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12255 output_asm_insn (\"crxor 6,6,6\", operands);
12257 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12258 output_asm_insn (\"creqv 6,6,6\", operands);
12260 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
12261 }"
12262 [(set_attr "type" "branch")
12263 (set_attr "length" "4,8")])
12266 ;; A function pointer under System V is just a normal pointer
12267 ;; operands[0] is the function pointer
12268 ;; operands[1] is the stack size to clean up
12269 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12270 ;; which indicates how to set cr1
12272 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12273 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12274 (match_operand 1 "" "g,g,g,g"))
12275 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12276 (clobber (reg:SI LR_REGNO))]
12277 "DEFAULT_ABI == ABI_V4
12278 || DEFAULT_ABI == ABI_DARWIN"
12279 {
12280 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12281 output_asm_insn ("crxor 6,6,6", operands);
12283 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12284 output_asm_insn ("creqv 6,6,6", operands);
12286 return "b%T0l";
12287 }
12288 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12289 (set_attr "length" "4,4,8,8")])
12291 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12292 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12293 (match_operand 1 "" "g,g"))
12294 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12295 (clobber (reg:SI LR_REGNO))]
12296 "(DEFAULT_ABI == ABI_DARWIN
12297 || (DEFAULT_ABI == ABI_V4
12298 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12299 {
12300 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12301 output_asm_insn ("crxor 6,6,6", operands);
12303 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12304 output_asm_insn ("creqv 6,6,6", operands);
12306 #if TARGET_MACHO
12307 return output_call(insn, operands, 0, 2);
12308 #else
12309 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12310 {
12311 gcc_assert (!TARGET_SECURE_PLT);
12312 return "bl %z0@plt";
12313 }
12314 else
12315 return "bl %z0";
12316 #endif
12317 }
12318 "DEFAULT_ABI == ABI_V4
12319 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12320 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12321 [(parallel [(call (mem:SI (match_dup 0))
12322 (match_dup 1))
12323 (use (match_dup 2))
12324 (use (match_dup 3))
12325 (clobber (reg:SI LR_REGNO))])]
12326 {
12327 operands[3] = pic_offset_table_rtx;
12328 }
12329 [(set_attr "type" "branch,branch")
12330 (set_attr "length" "4,8")])
12332 (define_insn "*call_nonlocal_sysv_secure<mode>"
12333 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12334 (match_operand 1 "" "g,g"))
12335 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12336 (use (match_operand:SI 3 "register_operand" "r,r"))
12337 (clobber (reg:SI LR_REGNO))]
12338 "(DEFAULT_ABI == ABI_V4
12339 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12340 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12341 {
12342 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12343 output_asm_insn ("crxor 6,6,6", operands);
12345 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12346 output_asm_insn ("creqv 6,6,6", operands);
12348 if (flag_pic == 2)
12349 /* The magic 32768 offset here and in the other sysv call insns
12350 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12351 See sysv4.h:toc_section. */
12352 return "bl %z0+32768@plt";
12353 else
12354 return "bl %z0@plt";
12355 }
12356 [(set_attr "type" "branch,branch")
12357 (set_attr "length" "4,8")])
12359 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12360 [(set (match_operand 0 "" "")
12361 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12362 (match_operand 2 "" "g,g,g,g")))
12363 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12364 (clobber (reg:SI LR_REGNO))]
12365 "DEFAULT_ABI == ABI_V4
12366 || DEFAULT_ABI == ABI_DARWIN"
12367 {
12368 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12369 output_asm_insn ("crxor 6,6,6", operands);
12371 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12372 output_asm_insn ("creqv 6,6,6", operands);
12374 return "b%T1l";
12375 }
12376 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12377 (set_attr "length" "4,4,8,8")])
12379 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12380 [(set (match_operand 0 "" "")
12381 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12382 (match_operand 2 "" "g,g")))
12383 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12384 (clobber (reg:SI LR_REGNO))]
12385 "(DEFAULT_ABI == ABI_DARWIN
12386 || (DEFAULT_ABI == ABI_V4
12387 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12388 {
12389 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12390 output_asm_insn ("crxor 6,6,6", operands);
12392 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12393 output_asm_insn ("creqv 6,6,6", operands);
12395 #if TARGET_MACHO
12396 return output_call(insn, operands, 1, 3);
12397 #else
12398 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12399 {
12400 gcc_assert (!TARGET_SECURE_PLT);
12401 return "bl %z1@plt";
12402 }
12403 else
12404 return "bl %z1";
12405 #endif
12406 }
12407 "DEFAULT_ABI == ABI_V4
12408 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12409 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12410 [(parallel [(set (match_dup 0)
12411 (call (mem:SI (match_dup 1))
12412 (match_dup 2)))
12413 (use (match_dup 3))
12414 (use (match_dup 4))
12415 (clobber (reg:SI LR_REGNO))])]
12416 {
12417 operands[4] = pic_offset_table_rtx;
12418 }
12419 [(set_attr "type" "branch,branch")
12420 (set_attr "length" "4,8")])
12422 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12423 [(set (match_operand 0 "" "")
12424 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12425 (match_operand 2 "" "g,g")))
12426 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12427 (use (match_operand:SI 4 "register_operand" "r,r"))
12428 (clobber (reg:SI LR_REGNO))]
12429 "(DEFAULT_ABI == ABI_V4
12430 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12431 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12432 {
12433 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12434 output_asm_insn ("crxor 6,6,6", operands);
12436 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12437 output_asm_insn ("creqv 6,6,6", operands);
12439 if (flag_pic == 2)
12440 return "bl %z1+32768@plt";
12441 else
12442 return "bl %z1@plt";
12443 }
12444 [(set_attr "type" "branch,branch")
12445 (set_attr "length" "4,8")])
12448 ;; Call to AIX abi function in the same module.
12450 (define_insn "*call_local_aix<mode>"
12451 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s"))
12452 (match_operand 1 "" "g"))
12453 (clobber (reg:P LR_REGNO))]
12454 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12455 "bl %z0"
12456 [(set_attr "type" "branch")
12457 (set_attr "length" "4")])
12459 (define_insn "*call_value_local_aix<mode>"
12460 [(set (match_operand 0 "" "")
12461 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s"))
12462 (match_operand 2 "" "g")))
12463 (clobber (reg:P LR_REGNO))]
12464 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12465 "bl %z1"
12466 [(set_attr "type" "branch")
12467 (set_attr "length" "4")])
12469 ;; Call to AIX abi function which may be in another module.
12470 ;; Restore the TOC pointer (r2) after the call.
12472 (define_insn "*call_nonlocal_aix<mode>"
12473 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s"))
12474 (match_operand 1 "" "g"))
12475 (clobber (reg:P LR_REGNO))]
12476 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12477 "bl %z0\;nop"
12478 [(set_attr "type" "branch")
12479 (set_attr "length" "8")])
12481 (define_insn "*call_value_nonlocal_aix<mode>"
12482 [(set (match_operand 0 "" "")
12483 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s"))
12484 (match_operand 2 "" "g")))
12485 (clobber (reg:P LR_REGNO))]
12486 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12487 "bl %z1\;nop"
12488 [(set_attr "type" "branch")
12489 (set_attr "length" "8")])
12491 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
12492 ;; Operand0 is the addresss of the function to call
12493 ;; Operand2 is the location in the function descriptor to load r2 from
12494 ;; Operand3 is the stack location to hold the current TOC pointer
12496 (define_insn "*call_indirect_aix<mode>"
12497 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12498 (match_operand 1 "" "g,g"))
12499 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12500 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12501 (clobber (reg:P LR_REGNO))]
12502 "DEFAULT_ABI == ABI_AIX"
12503 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
12504 [(set_attr "type" "jmpreg")
12505 (set_attr "length" "12")])
12507 (define_insn "*call_value_indirect_aix<mode>"
12508 [(set (match_operand 0 "" "")
12509 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12510 (match_operand 2 "" "g,g")))
12511 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12512 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>"))
12513 (clobber (reg:P LR_REGNO))]
12514 "DEFAULT_ABI == ABI_AIX"
12515 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
12516 [(set_attr "type" "jmpreg")
12517 (set_attr "length" "12")])
12519 ;; Call to indirect functions with the ELFv2 ABI.
12520 ;; Operand0 is the addresss of the function to call
12521 ;; Operand2 is the stack location to hold the current TOC pointer
12523 (define_insn "*call_indirect_elfv2<mode>"
12524 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
12525 (match_operand 1 "" "g,g"))
12526 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>"))
12527 (clobber (reg:P LR_REGNO))]
12528 "DEFAULT_ABI == ABI_ELFv2"
12529 "b%T0l\;<ptrload> 2,%2"
12530 [(set_attr "type" "jmpreg")
12531 (set_attr "length" "8")])
12533 (define_insn "*call_value_indirect_elfv2<mode>"
12534 [(set (match_operand 0 "" "")
12535 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
12536 (match_operand 2 "" "g,g")))
12537 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>"))
12538 (clobber (reg:P LR_REGNO))]
12539 "DEFAULT_ABI == ABI_ELFv2"
12540 "b%T1l\;<ptrload> 2,%3"
12541 [(set_attr "type" "jmpreg")
12542 (set_attr "length" "8")])
12545 ;; Call subroutine returning any type.
12546 (define_expand "untyped_call"
12547 [(parallel [(call (match_operand 0 "" "")
12548 (const_int 0))
12549 (match_operand 1 "" "")
12550 (match_operand 2 "" "")])]
12551 ""
12552 "
12553 {
12554 int i;
12556 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12558 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12559 {
12560 rtx set = XVECEXP (operands[2], 0, i);
12561 emit_move_insn (SET_DEST (set), SET_SRC (set));
12562 }
12564 /* The optimizer does not know that the call sets the function value
12565 registers we stored in the result block. We avoid problems by
12566 claiming that all hard registers are used and clobbered at this
12567 point. */
12568 emit_insn (gen_blockage ());
12570 DONE;
12571 }")
12573 ;; sibling call patterns
12574 (define_expand "sibcall"
12575 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12576 (match_operand 1 "" ""))
12577 (use (match_operand 2 "" ""))
12578 (use (reg:SI LR_REGNO))
12579 (simple_return)])]
12580 ""
12581 "
12582 {
12583 #if TARGET_MACHO
12584 if (MACHOPIC_INDIRECT)
12585 operands[0] = machopic_indirect_call_target (operands[0]);
12586 #endif
12588 gcc_assert (GET_CODE (operands[0]) == MEM);
12589 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12591 operands[0] = XEXP (operands[0], 0);
12593 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12594 {
12595 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]);
12596 DONE;
12597 }
12598 }")
12600 (define_expand "sibcall_value"
12601 [(parallel [(set (match_operand 0 "register_operand" "")
12602 (call (mem:SI (match_operand 1 "address_operand" ""))
12603 (match_operand 2 "" "")))
12604 (use (match_operand 3 "" ""))
12605 (use (reg:SI LR_REGNO))
12606 (simple_return)])]
12607 ""
12608 "
12609 {
12610 #if TARGET_MACHO
12611 if (MACHOPIC_INDIRECT)
12612 operands[1] = machopic_indirect_call_target (operands[1]);
12613 #endif
12615 gcc_assert (GET_CODE (operands[1]) == MEM);
12616 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12618 operands[1] = XEXP (operands[1], 0);
12620 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)
12621 {
12622 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]);
12623 DONE;
12624 }
12625 }")
12627 ;; this and similar patterns must be marked as using LR, otherwise
12628 ;; dataflow will try to delete the store into it. This is true
12629 ;; even when the actual reg to jump to is in CTR, when LR was
12630 ;; saved and restored around the PIC-setting BCL.
12631 (define_insn "*sibcall_local32"
12632 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12633 (match_operand 1 "" "g,g"))
12634 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12635 (use (reg:SI LR_REGNO))
12636 (simple_return)]
12637 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12638 "*
12639 {
12640 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12641 output_asm_insn (\"crxor 6,6,6\", operands);
12643 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12644 output_asm_insn (\"creqv 6,6,6\", operands);
12646 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12647 }"
12648 [(set_attr "type" "branch")
12649 (set_attr "length" "4,8")])
12651 (define_insn "*sibcall_local64"
12652 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12653 (match_operand 1 "" "g,g"))
12654 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12655 (use (reg:SI LR_REGNO))
12656 (simple_return)]
12657 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12658 "*
12659 {
12660 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12661 output_asm_insn (\"crxor 6,6,6\", operands);
12663 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12664 output_asm_insn (\"creqv 6,6,6\", operands);
12666 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12667 }"
12668 [(set_attr "type" "branch")
12669 (set_attr "length" "4,8")])
12671 (define_insn "*sibcall_value_local32"
12672 [(set (match_operand 0 "" "")
12673 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12674 (match_operand 2 "" "g,g")))
12675 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12676 (use (reg:SI LR_REGNO))
12677 (simple_return)]
12678 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12679 "*
12680 {
12681 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12682 output_asm_insn (\"crxor 6,6,6\", operands);
12684 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12685 output_asm_insn (\"creqv 6,6,6\", operands);
12687 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12688 }"
12689 [(set_attr "type" "branch")
12690 (set_attr "length" "4,8")])
12692 (define_insn "*sibcall_value_local64"
12693 [(set (match_operand 0 "" "")
12694 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12695 (match_operand 2 "" "g,g")))
12696 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12697 (use (reg:SI LR_REGNO))
12698 (simple_return)]
12699 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12700 "*
12701 {
12702 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12703 output_asm_insn (\"crxor 6,6,6\", operands);
12705 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12706 output_asm_insn (\"creqv 6,6,6\", operands);
12708 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12709 }"
12710 [(set_attr "type" "branch")
12711 (set_attr "length" "4,8")])
12713 (define_insn "*sibcall_nonlocal_sysv<mode>"
12714 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
12715 (match_operand 1 "" ""))
12716 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
12717 (use (reg:SI LR_REGNO))
12718 (simple_return)]
12719 "(DEFAULT_ABI == ABI_DARWIN
12720 || DEFAULT_ABI == ABI_V4)
12721 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12722 "*
12723 {
12724 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12725 output_asm_insn (\"crxor 6,6,6\", operands);
12727 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12728 output_asm_insn (\"creqv 6,6,6\", operands);
12730 if (which_alternative >= 2)
12731 return \"b%T0\";
12732 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12733 {
12734 gcc_assert (!TARGET_SECURE_PLT);
12735 return \"b %z0@plt\";
12736 }
12737 else
12738 return \"b %z0\";
12739 }"
12740 [(set_attr "type" "branch")
12741 (set_attr "length" "4,8,4,8")])
12743 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12744 [(set (match_operand 0 "" "")
12745 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
12746 (match_operand 2 "" "")))
12747 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
12748 (use (reg:SI LR_REGNO))
12749 (simple_return)]
12750 "(DEFAULT_ABI == ABI_DARWIN
12751 || DEFAULT_ABI == ABI_V4)
12752 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12753 "*
12754 {
12755 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12756 output_asm_insn (\"crxor 6,6,6\", operands);
12758 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12759 output_asm_insn (\"creqv 6,6,6\", operands);
12761 if (which_alternative >= 2)
12762 return \"b%T1\";
12763 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
12764 {
12765 gcc_assert (!TARGET_SECURE_PLT);
12766 return \"b %z1@plt\";
12767 }
12768 else
12769 return \"b %z1\";
12770 }"
12771 [(set_attr "type" "branch")
12772 (set_attr "length" "4,8,4,8")])
12774 ;; AIX ABI sibling call patterns.
12776 (define_insn "*sibcall_aix<mode>"
12777 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
12778 (match_operand 1 "" "g,g"))
12779 (simple_return)]
12780 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12781 "@
12782 b %z0
12783 b%T0"
12784 [(set_attr "type" "branch")
12785 (set_attr "length" "4")])
12787 (define_insn "*sibcall_value_aix<mode>"
12788 [(set (match_operand 0 "" "")
12789 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
12790 (match_operand 2 "" "g,g")))
12791 (simple_return)]
12792 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2"
12793 "@
12794 b %z1
12795 b%T1"
12796 [(set_attr "type" "branch")
12797 (set_attr "length" "4")])
12799 (define_expand "sibcall_epilogue"
12800 [(use (const_int 0))]
12801 ""
12802 {
12803 if (!TARGET_SCHED_PROLOG)
12804 emit_insn (gen_blockage ());
12805 rs6000_emit_epilogue (TRUE);
12806 DONE;
12807 })
12809 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12810 ;; all of memory. This blocks insns from being moved across this point.
12812 (define_insn "blockage"
12813 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12814 ""
12815 "")
12817 (define_expand "probe_stack"
12818 [(set (match_operand 0 "memory_operand" "=m")
12819 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12820 ""
12821 {
12822 if (TARGET_64BIT)
12823 emit_insn (gen_probe_stack_di (operands[0]));
12824 else
12825 emit_insn (gen_probe_stack_si (operands[0]));
12826 DONE;
12827 })
12829 (define_insn "probe_stack_<mode>"
12830 [(set (match_operand:P 0 "memory_operand" "=m")
12831 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
12832 ""
12833 {
12834 operands[1] = gen_rtx_REG (Pmode, 0);
12835 return "st<wd>%U0%X0 %1,%0";
12836 }
12837 [(set (attr "type")
12838 (if_then_else
12839 (match_test "update_indexed_address_mem (operands[0], VOIDmode)")
12840 (const_string "store_ux")
12841 (if_then_else
12842 (match_test "update_address_mem (operands[0], VOIDmode)")
12843 (const_string "store_u")
12844 (const_string "store"))))
12845 (set_attr "length" "4")])
12847 (define_insn "probe_stack_range<P:mode>"
12848 [(set (match_operand:P 0 "register_operand" "=r")
12849 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
12850 (match_operand:P 2 "register_operand" "r")]
12851 UNSPECV_PROBE_STACK_RANGE))]
12852 ""
12853 "* return output_probe_stack_range (operands[0], operands[2]);"
12854 [(set_attr "type" "three")])
12855 \f
12856 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12857 ;; signed & unsigned, and one type of branch.
12858 ;;
12859 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12860 ;; insns, and branches.
12862 (define_expand "cbranch<mode>4"
12863 [(use (match_operator 0 "rs6000_cbranch_operator"
12864 [(match_operand:GPR 1 "gpc_reg_operand" "")
12865 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12866 (use (match_operand 3 ""))]
12867 ""
12868 "
12869 {
12870 /* Take care of the possibility that operands[2] might be negative but
12871 this might be a logical operation. That insn doesn't exist. */
12872 if (GET_CODE (operands[2]) == CONST_INT
12873 && INTVAL (operands[2]) < 0)
12874 {
12875 operands[2] = force_reg (<MODE>mode, operands[2]);
12876 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12877 GET_MODE (operands[0]),
12878 operands[1], operands[2]);
12879 }
12881 rs6000_emit_cbranch (<MODE>mode, operands);
12882 DONE;
12883 }")
12885 (define_expand "cbranch<mode>4"
12886 [(use (match_operator 0 "rs6000_cbranch_operator"
12887 [(match_operand:FP 1 "gpc_reg_operand" "")
12888 (match_operand:FP 2 "gpc_reg_operand" "")]))
12889 (use (match_operand 3 ""))]
12890 ""
12891 "
12892 {
12893 rs6000_emit_cbranch (<MODE>mode, operands);
12894 DONE;
12895 }")
12897 (define_expand "cstore<mode>4"
12898 [(use (match_operator 1 "rs6000_cbranch_operator"
12899 [(match_operand:GPR 2 "gpc_reg_operand" "")
12900 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12901 (clobber (match_operand:SI 0 "register_operand"))]
12902 ""
12903 "
12904 {
12905 /* Take care of the possibility that operands[3] might be negative but
12906 this might be a logical operation. That insn doesn't exist. */
12907 if (GET_CODE (operands[3]) == CONST_INT
12908 && INTVAL (operands[3]) < 0)
12909 {
12910 operands[3] = force_reg (<MODE>mode, operands[3]);
12911 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12912 GET_MODE (operands[1]),
12913 operands[2], operands[3]);
12914 }
12916 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12917 For SEQ, likewise, except that comparisons with zero should be done
12918 with an scc insns. However, due to the order that combine see the
12919 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12920 the cases we don't want to handle or are best handled by portable
12921 code. */
12922 if (GET_CODE (operands[1]) == NE)
12923 FAIL;
12924 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12925 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12926 && operands[3] == const0_rtx)
12927 FAIL;
12928 rs6000_emit_sCOND (<MODE>mode, operands);
12929 DONE;
12930 }")
12932 (define_expand "cstore<mode>4"
12933 [(use (match_operator 1 "rs6000_cbranch_operator"
12934 [(match_operand:FP 2 "gpc_reg_operand" "")
12935 (match_operand:FP 3 "gpc_reg_operand" "")]))
12936 (clobber (match_operand:SI 0 "register_operand"))]
12937 ""
12938 "
12939 {
12940 rs6000_emit_sCOND (<MODE>mode, operands);
12941 DONE;
12942 }")
12945 (define_expand "stack_protect_set"
12946 [(match_operand 0 "memory_operand" "")
12947 (match_operand 1 "memory_operand" "")]
12948 ""
12949 {
12950 #ifdef TARGET_THREAD_SSP_OFFSET
12951 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12952 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12953 operands[1] = gen_rtx_MEM (Pmode, addr);
12954 #endif
12955 if (TARGET_64BIT)
12956 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12957 else
12958 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12959 DONE;
12960 })
12962 (define_insn "stack_protect_setsi"
12963 [(set (match_operand:SI 0 "memory_operand" "=m")
12964 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12965 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12966 "TARGET_32BIT"
12967 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
12968 [(set_attr "type" "three")
12969 (set_attr "length" "12")])
12971 (define_insn "stack_protect_setdi"
12972 [(set (match_operand:DI 0 "memory_operand" "=Y")
12973 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
12974 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12975 "TARGET_64BIT"
12976 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0"
12977 [(set_attr "type" "three")
12978 (set_attr "length" "12")])
12980 (define_expand "stack_protect_test"
12981 [(match_operand 0 "memory_operand" "")
12982 (match_operand 1 "memory_operand" "")
12983 (match_operand 2 "" "")]
12984 ""
12985 {
12986 rtx test, op0, op1;
12987 #ifdef TARGET_THREAD_SSP_OFFSET
12988 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12989 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12990 operands[1] = gen_rtx_MEM (Pmode, addr);
12991 #endif
12992 op0 = operands[0];
12993 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12994 test = gen_rtx_EQ (VOIDmode, op0, op1);
12995 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12996 DONE;
12997 })
12999 (define_insn "stack_protect_testsi"
13000 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13001 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
13002 (match_operand:SI 2 "memory_operand" "m,m")]
13003 UNSPEC_SP_TEST))
13004 (set (match_scratch:SI 4 "=r,r") (const_int 0))
13005 (clobber (match_scratch:SI 3 "=&r,&r"))]
13006 "TARGET_32BIT"
13007 "@
13008 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
13009 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0"
13010 [(set_attr "length" "16,20")])
13012 (define_insn "stack_protect_testdi"
13013 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13014 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
13015 (match_operand:DI 2 "memory_operand" "Y,Y")]
13016 UNSPEC_SP_TEST))
13017 (set (match_scratch:DI 4 "=r,r") (const_int 0))
13018 (clobber (match_scratch:DI 3 "=&r,&r"))]
13019 "TARGET_64BIT"
13020 "@
13021 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0
13022 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0"
13023 [(set_attr "length" "16,20")])
13025 \f
13026 ;; Here are the actual compare insns.
13027 (define_insn "*cmp<mode>_internal1"
13028 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13029 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
13030 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
13031 ""
13032 "cmp<wd>%I2 %0,%1,%2"
13033 [(set_attr "type" "cmp")])
13035 ;; If we are comparing a register for equality with a large constant,
13036 ;; we can do this with an XOR followed by a compare. But this is profitable
13037 ;; only if the large constant is only used for the comparison (and in this
13038 ;; case we already have a register to reuse as scratch).
13039 ;;
13040 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
13041 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
13043 (define_peephole2
13044 [(set (match_operand:SI 0 "register_operand")
13045 (match_operand:SI 1 "logical_const_operand" ""))
13046 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
13047 [(match_dup 0)
13048 (match_operand:SI 2 "logical_const_operand" "")]))
13049 (set (match_operand:CC 4 "cc_reg_operand" "")
13050 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
13051 (match_dup 0)))
13052 (set (pc)
13053 (if_then_else (match_operator 6 "equality_operator"
13054 [(match_dup 4) (const_int 0)])
13055 (match_operand 7 "" "")
13056 (match_operand 8 "" "")))]
13057 "peep2_reg_dead_p (3, operands[0])
13058 && peep2_reg_dead_p (4, operands[4])"
13059 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
13060 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
13061 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
13063 {
13064 /* Get the constant we are comparing against, and see what it looks like
13065 when sign-extended from 16 to 32 bits. Then see what constant we could
13066 XOR with SEXTC to get the sign-extended value. */
13067 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
13068 SImode,
13069 operands[1], operands[2]);
13070 HOST_WIDE_INT c = INTVAL (cnst);
13071 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
13072 HOST_WIDE_INT xorv = c ^ sextc;
13074 operands[9] = GEN_INT (xorv);
13075 operands[10] = GEN_INT (sextc);
13076 })
13078 (define_insn "*cmpsi_internal2"
13079 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13080 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13081 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
13082 ""
13083 "cmplw%I2 %0,%1,%b2"
13084 [(set_attr "type" "cmp")])
13086 (define_insn "*cmpdi_internal2"
13087 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
13088 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
13089 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
13090 ""
13091 "cmpld%I2 %0,%1,%b2"
13092 [(set_attr "type" "cmp")])
13094 ;; The following two insns don't exist as single insns, but if we provide
13095 ;; them, we can swap an add and compare, which will enable us to overlap more
13096 ;; of the required delay between a compare and branch. We generate code for
13097 ;; them by splitting.
13099 (define_insn ""
13100 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13101 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
13102 (match_operand:SI 2 "short_cint_operand" "i")))
13103 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13104 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13105 ""
13106 "#"
13107 [(set_attr "length" "8")])
13109 (define_insn ""
13110 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
13111 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
13112 (match_operand:SI 2 "u_short_cint_operand" "i")))
13113 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
13114 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
13115 ""
13116 "#"
13117 [(set_attr "length" "8")])
13119 (define_split
13120 [(set (match_operand:CC 3 "cc_reg_operand" "")
13121 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
13122 (match_operand:SI 2 "short_cint_operand" "")))
13123 (set (match_operand:SI 0 "gpc_reg_operand" "")
13124 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13125 ""
13126 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
13127 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13129 (define_split
13130 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
13131 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
13132 (match_operand:SI 2 "u_short_cint_operand" "")))
13133 (set (match_operand:SI 0 "gpc_reg_operand" "")
13134 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
13135 ""
13136 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
13137 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
13139 ;; Only need to compare second words if first words equal
13140 (define_insn "*cmptf_internal1"
13141 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13142 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13143 (match_operand:TF 2 "gpc_reg_operand" "d")))]
13144 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
13145 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13146 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
13147 [(set_attr "type" "fpcompare")
13148 (set_attr "length" "12")])
13150 (define_insn_and_split "*cmptf_internal2"
13151 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
13152 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
13153 (match_operand:TF 2 "gpc_reg_operand" "d")))
13154 (clobber (match_scratch:DF 3 "=d"))
13155 (clobber (match_scratch:DF 4 "=d"))
13156 (clobber (match_scratch:DF 5 "=d"))
13157 (clobber (match_scratch:DF 6 "=d"))
13158 (clobber (match_scratch:DF 7 "=d"))
13159 (clobber (match_scratch:DF 8 "=d"))
13160 (clobber (match_scratch:DF 9 "=d"))
13161 (clobber (match_scratch:DF 10 "=d"))
13162 (clobber (match_scratch:GPR 11 "=b"))]
13163 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
13164 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
13165 "#"
13166 "&& reload_completed"
13167 [(set (match_dup 3) (match_dup 14))
13168 (set (match_dup 4) (match_dup 15))
13169 (set (match_dup 9) (abs:DF (match_dup 5)))
13170 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
13171 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
13172 (label_ref (match_dup 12))
13173 (pc)))
13174 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
13175 (set (pc) (label_ref (match_dup 13)))
13176 (match_dup 12)
13177 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
13178 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
13179 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
13180 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
13181 (match_dup 13)]
13182 {
13183 REAL_VALUE_TYPE rv;
13184 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0;
13185 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode);
13187 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
13188 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
13189 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
13190 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
13191 operands[12] = gen_label_rtx ();
13192 operands[13] = gen_label_rtx ();
13193 real_inf (&rv);
13194 operands[14] = force_const_mem (DFmode,
13195 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
13196 operands[15] = force_const_mem (DFmode,
13197 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
13198 DFmode));
13199 if (TARGET_TOC)
13200 {
13201 rtx tocref;
13202 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
13203 operands[14] = gen_const_mem (DFmode, tocref);
13204 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
13205 operands[15] = gen_const_mem (DFmode, tocref);
13206 set_mem_alias_set (operands[14], get_TOC_alias_set ());
13207 set_mem_alias_set (operands[15], get_TOC_alias_set ());
13208 }
13209 })
13210 \f
13211 ;; Now we have the scc insns. We can do some combinations because of the
13212 ;; way the machine works.
13213 ;;
13214 ;; Note that this is probably faster if we can put an insn between the
13215 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
13216 ;; cases the insns below which don't use an intermediate CR field will
13217 ;; be used instead.
13218 (define_insn ""
13219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13220 (match_operator:SI 1 "scc_comparison_operator"
13221 [(match_operand 2 "cc_reg_operand" "y")
13222 (const_int 0)]))]
13223 ""
13224 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
13225 [(set (attr "type")
13226 (cond [(match_test "TARGET_MFCRF")
13227 (const_string "mfcrf")
13228 ]
13229 (const_string "mfcr")))
13230 (set_attr "length" "8")])
13232 ;; Same as above, but get the GT bit.
13233 (define_insn "move_from_CR_gt_bit"
13234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13235 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
13236 "TARGET_HARD_FLOAT && !TARGET_FPRS"
13237 "mfcr %0\;rlwinm %0,%0,%D1,31,31"
13238 [(set_attr "type" "mfcr")
13239 (set_attr "length" "8")])
13241 ;; Same as above, but get the OV/ORDERED bit.
13242 (define_insn "move_from_CR_ov_bit"
13243 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13244 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")]
13245 UNSPEC_MV_CR_OV))]
13246 "TARGET_ISEL"
13247 "mfcr %0\;rlwinm %0,%0,%t1,1"
13248 [(set_attr "type" "mfcr")
13249 (set_attr "length" "8")])
13251 (define_insn ""
13252 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13253 (match_operator:DI 1 "scc_comparison_operator"
13254 [(match_operand 2 "cc_reg_operand" "y")
13255 (const_int 0)]))]
13256 "TARGET_POWERPC64"
13257 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1"
13258 [(set (attr "type")
13259 (cond [(match_test "TARGET_MFCRF")
13260 (const_string "mfcrf")
13261 ]
13262 (const_string "mfcr")))
13263 (set_attr "length" "8")])
13265 (define_insn ""
13266 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13267 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13268 [(match_operand 2 "cc_reg_operand" "y,y")
13269 (const_int 0)])
13270 (const_int 0)))
13271 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
13272 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13273 "TARGET_32BIT"
13274 "@
13275 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1
13276 #"
13277 [(set_attr "type" "delayed_compare")
13278 (set_attr "length" "8,16")])
13280 (define_split
13281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13282 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
13283 [(match_operand 2 "cc_reg_operand" "")
13284 (const_int 0)])
13285 (const_int 0)))
13286 (set (match_operand:SI 3 "gpc_reg_operand" "")
13287 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
13288 "TARGET_32BIT && reload_completed"
13289 [(set (match_dup 3)
13290 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
13291 (set (match_dup 0)
13292 (compare:CC (match_dup 3)
13293 (const_int 0)))]
13294 "")
13296 (define_insn ""
13297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13298 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13299 [(match_operand 2 "cc_reg_operand" "y")
13300 (const_int 0)])
13301 (match_operand:SI 3 "const_int_operand" "n")))]
13302 ""
13303 "*
13304 {
13305 int is_bit = ccr_bit (operands[1], 1);
13306 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13307 int count;
13309 if (is_bit >= put_bit)
13310 count = is_bit - put_bit;
13311 else
13312 count = 32 - (put_bit - is_bit);
13314 operands[4] = GEN_INT (count);
13315 operands[5] = GEN_INT (put_bit);
13317 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\";
13318 }"
13319 [(set (attr "type")
13320 (cond [(match_test "TARGET_MFCRF")
13321 (const_string "mfcrf")
13322 ]
13323 (const_string "mfcr")))
13324 (set_attr "length" "8")])
13326 (define_insn ""
13327 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13328 (compare:CC
13329 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13330 [(match_operand 2 "cc_reg_operand" "y,y")
13331 (const_int 0)])
13332 (match_operand:SI 3 "const_int_operand" "n,n"))
13333 (const_int 0)))
13334 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
13335 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13336 (match_dup 3)))]
13337 ""
13338 "*
13339 {
13340 int is_bit = ccr_bit (operands[1], 1);
13341 int put_bit = 31 - (INTVAL (operands[3]) & 31);
13342 int count;
13344 /* Force split for non-cc0 compare. */
13345 if (which_alternative == 1)
13346 return \"#\";
13348 if (is_bit >= put_bit)
13349 count = is_bit - put_bit;
13350 else
13351 count = 32 - (put_bit - is_bit);
13353 operands[5] = GEN_INT (count);
13354 operands[6] = GEN_INT (put_bit);
13356 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\";
13357 }"
13358 [(set_attr "type" "delayed_compare")
13359 (set_attr "length" "8,16")])
13361 (define_split
13362 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13363 (compare:CC
13364 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13365 [(match_operand 2 "cc_reg_operand" "")
13366 (const_int 0)])
13367 (match_operand:SI 3 "const_int_operand" ""))
13368 (const_int 0)))
13369 (set (match_operand:SI 4 "gpc_reg_operand" "")
13370 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13371 (match_dup 3)))]
13372 "reload_completed"
13373 [(set (match_dup 4)
13374 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13375 (match_dup 3)))
13376 (set (match_dup 0)
13377 (compare:CC (match_dup 4)
13378 (const_int 0)))]
13379 "")
13381 ;; There is a 3 cycle delay between consecutive mfcr instructions
13382 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13384 (define_peephole
13385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13386 (match_operator:SI 1 "scc_comparison_operator"
13387 [(match_operand 2 "cc_reg_operand" "y")
13388 (const_int 0)]))
13389 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13390 (match_operator:SI 4 "scc_comparison_operator"
13391 [(match_operand 5 "cc_reg_operand" "y")
13392 (const_int 0)]))]
13393 "REGNO (operands[2]) != REGNO (operands[5])"
13394 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13395 [(set_attr "type" "mfcr")
13396 (set_attr "length" "12")])
13398 (define_peephole
13399 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13400 (match_operator:DI 1 "scc_comparison_operator"
13401 [(match_operand 2 "cc_reg_operand" "y")
13402 (const_int 0)]))
13403 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13404 (match_operator:DI 4 "scc_comparison_operator"
13405 [(match_operand 5 "cc_reg_operand" "y")
13406 (const_int 0)]))]
13407 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13408 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1"
13409 [(set_attr "type" "mfcr")
13410 (set_attr "length" "12")])
13412 ;; There are some scc insns that can be done directly, without a compare.
13413 ;; These are faster because they don't involve the communications between
13414 ;; the FXU and branch units. In fact, we will be replacing all of the
13415 ;; integer scc insns here or in the portable methods in emit_store_flag.
13416 ;;
13417 ;; Also support (neg (scc ..)) since that construct is used to replace
13418 ;; branches, (plus (scc ..) ..) since that construct is common and
13419 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13420 ;; cases where it is no more expensive than (neg (scc ..)).
13422 ;; Have reload force a constant into a register for the simple insns that
13423 ;; otherwise won't accept constants. We do this because it is faster than
13424 ;; the cmp/mfcr sequence we would otherwise generate.
13426 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13427 (DI "rKJI")])
13429 (define_insn_and_split "*eq<mode>"
13430 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13431 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13432 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13433 ""
13434 "#"
13435 ""
13436 [(set (match_dup 0)
13437 (clz:GPR (match_dup 3)))
13438 (set (match_dup 0)
13439 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13440 {
13441 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13442 {
13443 /* Use output operand as intermediate. */
13444 operands[3] = operands[0];
13446 if (logical_operand (operands[2], <MODE>mode))
13447 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13448 gen_rtx_XOR (<MODE>mode,
13449 operands[1], operands[2])));
13450 else
13451 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13452 gen_rtx_PLUS (<MODE>mode, operands[1],
13453 negate_rtx (<MODE>mode,
13454 operands[2]))));
13455 }
13456 else
13457 operands[3] = operands[1];
13459 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13460 })
13462 (define_insn_and_split "*eq<mode>_compare"
13463 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13464 (compare:CC
13465 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13466 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13467 (const_int 0)))
13468 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13469 (eq:P (match_dup 1) (match_dup 2)))]
13470 "optimize_size"
13471 "#"
13472 "optimize_size"
13473 [(set (match_dup 0)
13474 (clz:P (match_dup 4)))
13475 (parallel [(set (match_dup 3)
13476 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13477 (const_int 0)))
13478 (set (match_dup 0)
13479 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13480 {
13481 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13482 {
13483 /* Use output operand as intermediate. */
13484 operands[4] = operands[0];
13486 if (logical_operand (operands[2], <MODE>mode))
13487 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13488 gen_rtx_XOR (<MODE>mode,
13489 operands[1], operands[2])));
13490 else
13491 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13492 gen_rtx_PLUS (<MODE>mode, operands[1],
13493 negate_rtx (<MODE>mode,
13494 operands[2]))));
13495 }
13496 else
13497 operands[4] = operands[1];
13499 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13500 })
13502 ;; We have insns of the form shown by the first define_insn below. If
13503 ;; there is something inside the comparison operation, we must split it.
13504 (define_split
13505 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13506 (plus:SI (match_operator 1 "comparison_operator"
13507 [(match_operand:SI 2 "" "")
13508 (match_operand:SI 3
13509 "reg_or_cint_operand" "")])
13510 (match_operand:SI 4 "gpc_reg_operand" "")))
13511 (clobber (match_operand:SI 5 "register_operand" ""))]
13512 "! gpc_reg_operand (operands[2], SImode)"
13513 [(set (match_dup 5) (match_dup 2))
13514 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)])
13515 (match_dup 4)))])
13517 (define_insn "*plus_eqsi"
13518 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13519 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13520 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13521 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13522 "TARGET_32BIT"
13523 "@
13524 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3
13525 subfic %0,%1,0\;addze %0,%3
13526 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3
13527 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3
13528 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3"
13529 [(set_attr "type" "three,two,three,three,three")
13530 (set_attr "length" "12,8,12,12,12")])
13532 (define_insn "*compare_plus_eqsi"
13533 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13534 (compare:CC
13535 (plus:SI
13536 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13537 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13538 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13539 (const_int 0)))
13540 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13541 "TARGET_32BIT && optimize_size"
13542 "@
13543 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13544 subfic %4,%1,0\;addze. %4,%3
13545 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3
13546 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3
13547 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3
13548 #
13549 #
13550 #
13551 #
13552 #"
13553 [(set_attr "type" "compare")
13554 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13556 (define_split
13557 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13558 (compare:CC
13559 (plus:SI
13560 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13561 (match_operand:SI 2 "scc_eq_operand" ""))
13562 (match_operand:SI 3 "gpc_reg_operand" ""))
13563 (const_int 0)))
13564 (clobber (match_scratch:SI 4 ""))]
13565 "TARGET_32BIT && optimize_size && reload_completed"
13566 [(set (match_dup 4)
13567 (plus:SI (eq:SI (match_dup 1)
13568 (match_dup 2))
13569 (match_dup 3)))
13570 (set (match_dup 0)
13571 (compare:CC (match_dup 4)
13572 (const_int 0)))]
13573 "")
13575 (define_insn "*plus_eqsi_compare"
13576 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13577 (compare:CC
13578 (plus:SI
13579 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13580 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13581 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13582 (const_int 0)))
13583 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13584 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13585 "TARGET_32BIT && optimize_size"
13586 "@
13587 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13588 subfic %0,%1,0\;addze. %0,%3
13589 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3
13590 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3
13591 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3
13592 #
13593 #
13594 #
13595 #
13596 #"
13597 [(set_attr "type" "compare")
13598 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13600 (define_split
13601 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13602 (compare:CC
13603 (plus:SI
13604 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13605 (match_operand:SI 2 "scc_eq_operand" ""))
13606 (match_operand:SI 3 "gpc_reg_operand" ""))
13607 (const_int 0)))
13608 (set (match_operand:SI 0 "gpc_reg_operand" "")
13609 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13610 "TARGET_32BIT && optimize_size && reload_completed"
13611 [(set (match_dup 0)
13612 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13613 (set (match_dup 4)
13614 (compare:CC (match_dup 0)
13615 (const_int 0)))]
13616 "")
13618 (define_insn "*neg_eq0<mode>"
13619 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13620 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13621 (const_int 0))))]
13622 ""
13623 "addic %0,%1,-1\;subfe %0,%0,%0"
13624 [(set_attr "type" "two")
13625 (set_attr "length" "8")])
13627 (define_insn_and_split "*neg_eq<mode>"
13628 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13629 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13630 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13631 ""
13632 "#"
13633 ""
13634 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13635 {
13636 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13637 {
13638 /* Use output operand as intermediate. */
13639 operands[3] = operands[0];
13641 if (logical_operand (operands[2], <MODE>mode))
13642 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13643 gen_rtx_XOR (<MODE>mode,
13644 operands[1], operands[2])));
13645 else
13646 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13647 gen_rtx_PLUS (<MODE>mode, operands[1],
13648 negate_rtx (<MODE>mode,
13649 operands[2]))));
13650 }
13651 else
13652 operands[3] = operands[1];
13653 })
13655 (define_insn "*ne0_<mode>"
13656 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13657 (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13658 (const_int 0)))
13659 (clobber (match_scratch:P 2 "=&r"))]
13660 "!(TARGET_32BIT && TARGET_ISEL)"
13661 "addic %2,%1,-1\;subfe %0,%2,%1"
13662 [(set_attr "type" "two")
13663 (set_attr "length" "8")])
13665 (define_insn "*plus_ne0_<mode>"
13666 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13667 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r")
13668 (const_int 0))
13669 (match_operand:P 2 "gpc_reg_operand" "r")))
13670 (clobber (match_scratch:P 3 "=&r"))]
13671 ""
13672 "addic %3,%1,-1\;addze %0,%2"
13673 [(set_attr "type" "two")
13674 (set_attr "length" "8")])
13676 (define_insn "*compare_plus_ne0_<mode>"
13677 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13678 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13679 (const_int 0))
13680 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13681 (const_int 0)))
13682 (clobber (match_scratch:P 3 "=&r,&r"))
13683 (clobber (match_scratch:P 4 "=X,&r"))]
13684 ""
13685 "@
13686 addic %3,%1,-1\;addze. %3,%2
13687 #"
13688 [(set_attr "type" "compare")
13689 (set_attr "length" "8,12")])
13691 (define_split
13692 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13693 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13694 (const_int 0))
13695 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13696 (clobber (match_scratch:P 3 ""))
13697 (clobber (match_scratch:P 4 ""))]
13698 "reload_completed"
13699 [(parallel [(set (match_dup 3)
13700 (plus:P (ne:P (match_dup 1)
13701 (const_int 0))
13702 (match_dup 2)))
13703 (clobber (match_dup 4))])
13704 (set (match_dup 0)
13705 (compare:CC (match_dup 3)
13706 (const_int 0)))]
13707 "")
13709 ; For combine.
13710 (define_insn "*compare_plus_ne0_<mode>_1"
13711 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
13712 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13713 (const_int 0))
13714 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r"))))
13715 (clobber (match_scratch:P 3 "=&r,&r"))
13716 (clobber (match_scratch:P 4 "=X,&r"))]
13717 ""
13718 "@
13719 addic %3,%1,-1\;addze. %3,%2
13720 #"
13721 [(set_attr "type" "compare")
13722 (set_attr "length" "8,12")])
13724 (define_split
13725 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "")
13726 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "")
13727 (const_int 0))
13728 (neg:P (match_operand:P 2 "gpc_reg_operand" ""))))
13729 (clobber (match_scratch:P 3 ""))
13730 (clobber (match_scratch:P 4 ""))]
13731 "reload_completed"
13732 [(parallel [(set (match_dup 3)
13733 (plus:P (ne:P (match_dup 1)
13734 (const_int 0))
13735 (match_dup 2)))
13736 (clobber (match_dup 4))])
13737 (set (match_dup 0)
13738 (compare:CC (match_dup 3)
13739 (const_int 0)))]
13740 "")
13742 (define_insn "*plus_ne0_<mode>_compare"
13743 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13744 (compare:CC
13745 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13746 (const_int 0))
13747 (match_operand:P 2 "gpc_reg_operand" "r,r"))
13748 (const_int 0)))
13749 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13750 (plus:P (ne:P (match_dup 1)
13751 (const_int 0))
13752 (match_dup 2)))
13753 (clobber (match_scratch:P 3 "=&r,&r"))]
13754 ""
13755 "@
13756 addic %3,%1,-1\;addze. %0,%2
13757 #"
13758 [(set_attr "type" "compare")
13759 (set_attr "length" "8,12")])
13761 (define_split
13762 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13763 (compare:CC
13764 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "")
13765 (const_int 0))
13766 (match_operand:P 2 "gpc_reg_operand" ""))
13767 (const_int 0)))
13768 (set (match_operand:P 0 "gpc_reg_operand" "")
13769 (plus:P (ne:P (match_dup 1)
13770 (const_int 0))
13771 (match_dup 2)))
13772 (clobber (match_scratch:P 3 ""))]
13773 "reload_completed"
13774 [(parallel [(set (match_dup 0)
13775 (plus:P (ne:P (match_dup 1)
13776 (const_int 0))
13777 (match_dup 2)))
13778 (clobber (match_dup 3))])
13779 (set (match_dup 4)
13780 (compare:CC (match_dup 0)
13781 (const_int 0)))]
13782 "")
13784 (define_insn "*leu<mode>"
13785 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13786 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13787 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13788 ""
13789 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
13790 [(set_attr "type" "three")
13791 (set_attr "length" "12")])
13793 (define_insn "*leu<mode>_compare"
13794 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13795 (compare:CC
13796 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13797 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13798 (const_int 0)))
13799 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13800 (leu:P (match_dup 1) (match_dup 2)))]
13801 ""
13802 "@
13803 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
13804 #"
13805 [(set_attr "type" "compare")
13806 (set_attr "length" "12,16")])
13808 (define_split
13809 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13810 (compare:CC
13811 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13812 (match_operand:P 2 "reg_or_short_operand" ""))
13813 (const_int 0)))
13814 (set (match_operand:P 0 "gpc_reg_operand" "")
13815 (leu:P (match_dup 1) (match_dup 2)))]
13816 "reload_completed"
13817 [(set (match_dup 0)
13818 (leu:P (match_dup 1) (match_dup 2)))
13819 (set (match_dup 3)
13820 (compare:CC (match_dup 0)
13821 (const_int 0)))]
13822 "")
13824 (define_insn "*plus_leu<mode>"
13825 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13826 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13827 (match_operand:P 2 "reg_or_short_operand" "rI"))
13828 (match_operand:P 3 "gpc_reg_operand" "r")))]
13829 ""
13830 "subf%I2c %0,%1,%2\;addze %0,%3"
13831 [(set_attr "type" "two")
13832 (set_attr "length" "8")])
13834 (define_insn ""
13835 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13836 (compare:CC
13837 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13838 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13839 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13840 (const_int 0)))
13841 (clobber (match_scratch:SI 4 "=&r,&r"))]
13842 "TARGET_32BIT"
13843 "@
13844 subf%I2c %4,%1,%2\;addze. %4,%3
13845 #"
13846 [(set_attr "type" "compare")
13847 (set_attr "length" "8,12")])
13849 (define_split
13850 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13851 (compare:CC
13852 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13853 (match_operand:SI 2 "reg_or_short_operand" ""))
13854 (match_operand:SI 3 "gpc_reg_operand" ""))
13855 (const_int 0)))
13856 (clobber (match_scratch:SI 4 ""))]
13857 "TARGET_32BIT && reload_completed"
13858 [(set (match_dup 4)
13859 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13860 (match_dup 3)))
13861 (set (match_dup 0)
13862 (compare:CC (match_dup 4)
13863 (const_int 0)))]
13864 "")
13866 (define_insn ""
13867 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13868 (compare:CC
13869 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13870 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13871 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13872 (const_int 0)))
13873 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13874 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13875 "TARGET_32BIT"
13876 "@
13877 subf%I2c %0,%1,%2\;addze. %0,%3
13878 #"
13879 [(set_attr "type" "compare")
13880 (set_attr "length" "8,12")])
13882 (define_split
13883 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13884 (compare:CC
13885 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13886 (match_operand:SI 2 "reg_or_short_operand" ""))
13887 (match_operand:SI 3 "gpc_reg_operand" ""))
13888 (const_int 0)))
13889 (set (match_operand:SI 0 "gpc_reg_operand" "")
13890 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13891 "TARGET_32BIT && reload_completed"
13892 [(set (match_dup 0)
13893 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13894 (set (match_dup 4)
13895 (compare:CC (match_dup 0)
13896 (const_int 0)))]
13897 "")
13899 (define_insn "*neg_leu<mode>"
13900 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13901 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13902 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13903 ""
13904 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0"
13905 [(set_attr "type" "three")
13906 (set_attr "length" "12")])
13908 (define_insn "*and_neg_leu<mode>"
13909 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13910 (and:P (neg:P
13911 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13912 (match_operand:P 2 "reg_or_short_operand" "rI")))
13913 (match_operand:P 3 "gpc_reg_operand" "r")))]
13914 ""
13915 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0"
13916 [(set_attr "type" "three")
13917 (set_attr "length" "12")])
13919 (define_insn ""
13920 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13921 (compare:CC
13922 (and:SI (neg:SI
13923 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13924 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13925 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13926 (const_int 0)))
13927 (clobber (match_scratch:SI 4 "=&r,&r"))]
13928 "TARGET_32BIT"
13929 "@
13930 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4
13931 #"
13932 [(set_attr "type" "compare")
13933 (set_attr "length" "12,16")])
13935 (define_split
13936 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13937 (compare:CC
13938 (and:SI (neg:SI
13939 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13940 (match_operand:SI 2 "reg_or_short_operand" "")))
13941 (match_operand:SI 3 "gpc_reg_operand" ""))
13942 (const_int 0)))
13943 (clobber (match_scratch:SI 4 ""))]
13944 "TARGET_32BIT && reload_completed"
13945 [(set (match_dup 4)
13946 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13947 (match_dup 3)))
13948 (set (match_dup 0)
13949 (compare:CC (match_dup 4)
13950 (const_int 0)))]
13951 "")
13953 (define_insn ""
13954 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13955 (compare:CC
13956 (and:SI (neg:SI
13957 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13958 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13959 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13960 (const_int 0)))
13961 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13962 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13963 "TARGET_32BIT"
13964 "@
13965 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0
13966 #"
13967 [(set_attr "type" "compare")
13968 (set_attr "length" "12,16")])
13970 (define_split
13971 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13972 (compare:CC
13973 (and:SI (neg:SI
13974 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13975 (match_operand:SI 2 "reg_or_short_operand" "")))
13976 (match_operand:SI 3 "gpc_reg_operand" ""))
13977 (const_int 0)))
13978 (set (match_operand:SI 0 "gpc_reg_operand" "")
13979 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13980 "TARGET_32BIT && reload_completed"
13981 [(set (match_dup 0)
13982 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13983 (match_dup 3)))
13984 (set (match_dup 4)
13985 (compare:CC (match_dup 0)
13986 (const_int 0)))]
13987 "")
13989 (define_insn_and_split "*ltu<mode>"
13990 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13991 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13992 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13993 ""
13994 "#"
13995 ""
13996 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13997 (set (match_dup 0) (neg:P (match_dup 0)))]
13998 "")
14000 (define_insn_and_split "*ltu<mode>_compare"
14001 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14002 (compare:CC
14003 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14004 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14005 (const_int 0)))
14006 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14007 (ltu:P (match_dup 1) (match_dup 2)))]
14008 ""
14009 "#"
14010 ""
14011 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14012 (parallel [(set (match_dup 3)
14013 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14014 (set (match_dup 0) (neg:P (match_dup 0)))])]
14015 "")
14017 (define_insn_and_split "*plus_ltu<mode>"
14018 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14019 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14020 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14021 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14022 ""
14023 "#"
14024 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14025 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14026 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14027 "")
14029 (define_insn_and_split "*plus_ltu<mode>_compare"
14030 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14031 (compare:CC
14032 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14033 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14034 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14035 (const_int 0)))
14036 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14037 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14038 ""
14039 "#"
14040 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14041 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14042 (parallel [(set (match_dup 4)
14043 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14044 (const_int 0)))
14045 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14046 "")
14048 (define_insn "*neg_ltu<mode>"
14049 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14050 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14051 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14052 ""
14053 "@
14054 subfc %0,%2,%1\;subfe %0,%0,%0
14055 addic %0,%1,%n2\;subfe %0,%0,%0"
14056 [(set_attr "type" "two")
14057 (set_attr "length" "8")])
14059 (define_insn "*geu<mode>"
14060 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14061 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14062 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14063 ""
14064 "@
14065 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
14066 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
14067 [(set_attr "type" "three")
14068 (set_attr "length" "12")])
14070 (define_insn "*geu<mode>_compare"
14071 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14072 (compare:CC
14073 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14074 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14075 (const_int 0)))
14076 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14077 (geu:P (match_dup 1) (match_dup 2)))]
14078 ""
14079 "@
14080 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
14081 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
14082 #
14083 #"
14084 [(set_attr "type" "compare")
14085 (set_attr "length" "12,12,16,16")])
14087 (define_split
14088 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14089 (compare:CC
14090 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14091 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14092 (const_int 0)))
14093 (set (match_operand:P 0 "gpc_reg_operand" "")
14094 (geu:P (match_dup 1) (match_dup 2)))]
14095 "reload_completed"
14096 [(set (match_dup 0)
14097 (geu:P (match_dup 1) (match_dup 2)))
14098 (set (match_dup 3)
14099 (compare:CC (match_dup 0)
14100 (const_int 0)))]
14101 "")
14103 (define_insn "*plus_geu<mode>"
14104 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14105 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14106 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14107 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14108 ""
14109 "@
14110 subfc %0,%2,%1\;addze %0,%3
14111 addic %0,%1,%n2\;addze %0,%3"
14112 [(set_attr "type" "two")
14113 (set_attr "length" "8")])
14115 (define_insn ""
14116 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14117 (compare:CC
14118 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14119 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14120 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14121 (const_int 0)))
14122 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14123 "TARGET_32BIT"
14124 "@
14125 subfc %4,%2,%1\;addze. %4,%3
14126 addic %4,%1,%n2\;addze. %4,%3
14127 #
14128 #"
14129 [(set_attr "type" "compare")
14130 (set_attr "length" "8,8,12,12")])
14132 (define_split
14133 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14134 (compare:CC
14135 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14136 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14137 (match_operand:SI 3 "gpc_reg_operand" ""))
14138 (const_int 0)))
14139 (clobber (match_scratch:SI 4 ""))]
14140 "TARGET_32BIT && reload_completed"
14141 [(set (match_dup 4)
14142 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14143 (match_dup 3)))
14144 (set (match_dup 0)
14145 (compare:CC (match_dup 4)
14146 (const_int 0)))]
14147 "")
14149 (define_insn ""
14150 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14151 (compare:CC
14152 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14153 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14154 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14155 (const_int 0)))
14156 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14157 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14158 "TARGET_32BIT"
14159 "@
14160 subfc %0,%2,%1\;addze. %0,%3
14161 addic %0,%1,%n2\;addze. %0,%3
14162 #
14163 #"
14164 [(set_attr "type" "compare")
14165 (set_attr "length" "8,8,12,12")])
14167 (define_split
14168 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14169 (compare:CC
14170 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14171 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14172 (match_operand:SI 3 "gpc_reg_operand" ""))
14173 (const_int 0)))
14174 (set (match_operand:SI 0 "gpc_reg_operand" "")
14175 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14176 "TARGET_32BIT && reload_completed"
14177 [(set (match_dup 0)
14178 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14179 (set (match_dup 4)
14180 (compare:CC (match_dup 0)
14181 (const_int 0)))]
14182 "")
14184 (define_insn "*neg_geu<mode>"
14185 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14186 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14187 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14188 ""
14189 "@
14190 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0
14191 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0"
14192 [(set_attr "type" "three")
14193 (set_attr "length" "12")])
14195 (define_insn "*and_neg_geu<mode>"
14196 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14197 (and:P (neg:P
14198 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14199 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14200 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14201 ""
14202 "@
14203 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0
14204 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0"
14205 [(set_attr "type" "three")
14206 (set_attr "length" "12")])
14208 (define_insn ""
14209 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14210 (compare:CC
14211 (and:SI (neg:SI
14212 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14213 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14214 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14215 (const_int 0)))
14216 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14217 "TARGET_32BIT"
14218 "@
14219 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4
14220 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4
14221 #
14222 #"
14223 [(set_attr "type" "compare")
14224 (set_attr "length" "12,12,16,16")])
14226 (define_split
14227 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14228 (compare:CC
14229 (and:SI (neg:SI
14230 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14231 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14232 (match_operand:SI 3 "gpc_reg_operand" ""))
14233 (const_int 0)))
14234 (clobber (match_scratch:SI 4 ""))]
14235 "TARGET_32BIT && reload_completed"
14236 [(set (match_dup 4)
14237 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14238 (match_dup 3)))
14239 (set (match_dup 0)
14240 (compare:CC (match_dup 4)
14241 (const_int 0)))]
14242 "")
14244 (define_insn ""
14245 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14246 (compare:CC
14247 (and:SI (neg:SI
14248 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14249 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14250 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14251 (const_int 0)))
14252 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14253 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14254 "TARGET_32BIT"
14255 "@
14256 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0
14257 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0
14258 #
14259 #"
14260 [(set_attr "type" "compare")
14261 (set_attr "length" "12,12,16,16")])
14263 (define_split
14264 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14265 (compare:CC
14266 (and:SI (neg:SI
14267 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14268 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14269 (match_operand:SI 3 "gpc_reg_operand" ""))
14270 (const_int 0)))
14271 (set (match_operand:SI 0 "gpc_reg_operand" "")
14272 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14273 "TARGET_32BIT && reload_completed"
14274 [(set (match_dup 0)
14275 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14276 (set (match_dup 4)
14277 (compare:CC (match_dup 0)
14278 (const_int 0)))]
14279 "")
14281 (define_insn "*plus_gt0<mode>"
14282 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14283 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14284 (const_int 0))
14285 (match_operand:P 2 "gpc_reg_operand" "r")))]
14286 ""
14287 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
14288 [(set_attr "type" "three")
14289 (set_attr "length" "12")])
14291 (define_insn ""
14292 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14293 (compare:CC
14294 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14295 (const_int 0))
14296 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14297 (const_int 0)))
14298 (clobber (match_scratch:SI 3 "=&r,&r"))]
14299 "TARGET_32BIT"
14300 "@
14301 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14302 #"
14303 [(set_attr "type" "compare")
14304 (set_attr "length" "12,16")])
14306 (define_split
14307 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14308 (compare:CC
14309 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14310 (const_int 0))
14311 (match_operand:SI 2 "gpc_reg_operand" ""))
14312 (const_int 0)))
14313 (clobber (match_scratch:SI 3 ""))]
14314 "TARGET_32BIT && reload_completed"
14315 [(set (match_dup 3)
14316 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14317 (match_dup 2)))
14318 (set (match_dup 0)
14319 (compare:CC (match_dup 3)
14320 (const_int 0)))]
14321 "")
14323 (define_insn ""
14324 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14325 (compare:CC
14326 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14327 (const_int 0))
14328 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14329 (const_int 0)))
14330 (clobber (match_scratch:DI 3 "=&r,&r"))]
14331 "TARGET_64BIT"
14332 "@
14333 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14334 #"
14335 [(set_attr "type" "compare")
14336 (set_attr "length" "12,16")])
14338 (define_split
14339 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14340 (compare:CC
14341 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14342 (const_int 0))
14343 (match_operand:DI 2 "gpc_reg_operand" ""))
14344 (const_int 0)))
14345 (clobber (match_scratch:DI 3 ""))]
14346 "TARGET_64BIT && reload_completed"
14347 [(set (match_dup 3)
14348 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14349 (match_dup 2)))
14350 (set (match_dup 0)
14351 (compare:CC (match_dup 3)
14352 (const_int 0)))]
14353 "")
14355 (define_insn ""
14356 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14357 (compare:CC
14358 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14359 (const_int 0))
14360 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14361 (const_int 0)))
14362 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14363 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14364 "TARGET_32BIT"
14365 "@
14366 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14367 #"
14368 [(set_attr "type" "compare")
14369 (set_attr "length" "12,16")])
14371 (define_split
14372 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14373 (compare:CC
14374 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14375 (const_int 0))
14376 (match_operand:SI 2 "gpc_reg_operand" ""))
14377 (const_int 0)))
14378 (set (match_operand:SI 0 "gpc_reg_operand" "")
14379 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14380 "TARGET_32BIT && reload_completed"
14381 [(set (match_dup 0)
14382 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14383 (set (match_dup 3)
14384 (compare:CC (match_dup 0)
14385 (const_int 0)))]
14386 "")
14388 (define_insn ""
14389 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14390 (compare:CC
14391 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14392 (const_int 0))
14393 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14394 (const_int 0)))
14395 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14396 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14397 "TARGET_64BIT"
14398 "@
14399 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14400 #"
14401 [(set_attr "type" "compare")
14402 (set_attr "length" "12,16")])
14404 (define_split
14405 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14406 (compare:CC
14407 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14408 (const_int 0))
14409 (match_operand:DI 2 "gpc_reg_operand" ""))
14410 (const_int 0)))
14411 (set (match_operand:DI 0 "gpc_reg_operand" "")
14412 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14413 "TARGET_64BIT && reload_completed"
14414 [(set (match_dup 0)
14415 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14416 (set (match_dup 3)
14417 (compare:CC (match_dup 0)
14418 (const_int 0)))]
14419 "")
14421 (define_insn_and_split "*gtu<mode>"
14422 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14423 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14424 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14425 ""
14426 "#"
14427 ""
14428 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14429 (set (match_dup 0) (neg:P (match_dup 0)))]
14430 "")
14432 (define_insn_and_split "*gtu<mode>_compare"
14433 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14434 (compare:CC
14435 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14436 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14437 (const_int 0)))
14438 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14439 (gtu:P (match_dup 1) (match_dup 2)))]
14440 ""
14441 "#"
14442 ""
14443 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14444 (parallel [(set (match_dup 3)
14445 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14446 (set (match_dup 0) (neg:P (match_dup 0)))])]
14447 "")
14449 (define_insn_and_split "*plus_gtu<mode>"
14450 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14451 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14452 (match_operand:P 2 "reg_or_short_operand" "rI"))
14453 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14454 ""
14455 "#"
14456 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14457 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14458 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14459 "")
14461 (define_insn_and_split "*plus_gtu<mode>_compare"
14462 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14463 (compare:CC
14464 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14465 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14466 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14467 (const_int 0)))
14468 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14469 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14470 ""
14471 "#"
14472 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14473 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14474 (parallel [(set (match_dup 4)
14475 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14476 (const_int 0)))
14477 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14478 "")
14480 (define_insn "*neg_gtu<mode>"
14481 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14482 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14483 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14484 ""
14485 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
14486 [(set_attr "type" "two")
14487 (set_attr "length" "8")])
14489 \f
14490 ;; Define both directions of branch and return. If we need a reload
14491 ;; register, we'd rather use CR0 since it is much easier to copy a
14492 ;; register CC value to there.
14494 (define_insn ""
14495 [(set (pc)
14496 (if_then_else (match_operator 1 "branch_comparison_operator"
14497 [(match_operand 2
14498 "cc_reg_operand" "y")
14499 (const_int 0)])
14500 (label_ref (match_operand 0 "" ""))
14501 (pc)))]
14502 ""
14503 "*
14504 {
14505 return output_cbranch (operands[1], \"%l0\", 0, insn);
14506 }"
14507 [(set_attr "type" "branch")])
14509 (define_insn ""
14510 [(set (pc)
14511 (if_then_else (match_operator 0 "branch_comparison_operator"
14512 [(match_operand 1
14513 "cc_reg_operand" "y")
14514 (const_int 0)])
14515 (any_return)
14516 (pc)))]
14517 "<return_pred>"
14518 "*
14519 {
14520 return output_cbranch (operands[0], NULL, 0, insn);
14521 }"
14522 [(set_attr "type" "jmpreg")
14523 (set_attr "length" "4")])
14525 (define_insn ""
14526 [(set (pc)
14527 (if_then_else (match_operator 1 "branch_comparison_operator"
14528 [(match_operand 2
14529 "cc_reg_operand" "y")
14530 (const_int 0)])
14531 (pc)
14532 (label_ref (match_operand 0 "" ""))))]
14533 ""
14534 "*
14535 {
14536 return output_cbranch (operands[1], \"%l0\", 1, insn);
14537 }"
14538 [(set_attr "type" "branch")])
14540 (define_insn ""
14541 [(set (pc)
14542 (if_then_else (match_operator 0 "branch_comparison_operator"
14543 [(match_operand 1
14544 "cc_reg_operand" "y")
14545 (const_int 0)])
14546 (pc)
14547 (any_return)))]
14548 "<return_pred>"
14549 "*
14550 {
14551 return output_cbranch (operands[0], NULL, 1, insn);
14552 }"
14553 [(set_attr "type" "jmpreg")
14554 (set_attr "length" "4")])
14556 ;; Logic on condition register values.
14558 ; This pattern matches things like
14559 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14560 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14561 ; (const_int 1)))
14562 ; which are generated by the branch logic.
14563 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14565 (define_insn "*cceq_ior_compare"
14566 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14567 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14568 [(match_operator:SI 2
14569 "branch_positive_comparison_operator"
14570 [(match_operand 3
14571 "cc_reg_operand" "y,y")
14572 (const_int 0)])
14573 (match_operator:SI 4
14574 "branch_positive_comparison_operator"
14575 [(match_operand 5
14576 "cc_reg_operand" "0,y")
14577 (const_int 0)])])
14578 (const_int 1)))]
14579 ""
14580 "cr%q1 %E0,%j2,%j4"
14581 [(set_attr "type" "cr_logical,delayed_cr")])
14583 ; Why is the constant -1 here, but 1 in the previous pattern?
14584 ; Because ~1 has all but the low bit set.
14585 (define_insn ""
14586 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14587 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14588 [(not:SI (match_operator:SI 2
14589 "branch_positive_comparison_operator"
14590 [(match_operand 3
14591 "cc_reg_operand" "y,y")
14592 (const_int 0)]))
14593 (match_operator:SI 4
14594 "branch_positive_comparison_operator"
14595 [(match_operand 5
14596 "cc_reg_operand" "0,y")
14597 (const_int 0)])])
14598 (const_int -1)))]
14599 ""
14600 "cr%q1 %E0,%j2,%j4"
14601 [(set_attr "type" "cr_logical,delayed_cr")])
14603 (define_insn "*cceq_rev_compare"
14604 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14605 (compare:CCEQ (match_operator:SI 1
14606 "branch_positive_comparison_operator"
14607 [(match_operand 2
14608 "cc_reg_operand" "0,y")
14609 (const_int 0)])
14610 (const_int 0)))]
14611 ""
14612 "crnot %E0,%j1"
14613 [(set_attr "type" "cr_logical,delayed_cr")])
14615 ;; If we are comparing the result of two comparisons, this can be done
14616 ;; using creqv or crxor.
14618 (define_insn_and_split ""
14619 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14620 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14621 [(match_operand 2 "cc_reg_operand" "y")
14622 (const_int 0)])
14623 (match_operator 3 "branch_comparison_operator"
14624 [(match_operand 4 "cc_reg_operand" "y")
14625 (const_int 0)])))]
14626 ""
14627 "#"
14628 ""
14629 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14630 (match_dup 5)))]
14631 "
14632 {
14633 int positive_1, positive_2;
14635 positive_1 = branch_positive_comparison_operator (operands[1],
14636 GET_MODE (operands[1]));
14637 positive_2 = branch_positive_comparison_operator (operands[3],
14638 GET_MODE (operands[3]));
14640 if (! positive_1)
14641 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14642 GET_CODE (operands[1])),
14643 SImode,
14644 operands[2], const0_rtx);
14645 else if (GET_MODE (operands[1]) != SImode)
14646 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14647 operands[2], const0_rtx);
14649 if (! positive_2)
14650 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14651 GET_CODE (operands[3])),
14652 SImode,
14653 operands[4], const0_rtx);
14654 else if (GET_MODE (operands[3]) != SImode)
14655 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14656 operands[4], const0_rtx);
14658 if (positive_1 == positive_2)
14659 {
14660 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14661 operands[5] = constm1_rtx;
14662 }
14663 else
14664 {
14665 operands[5] = const1_rtx;
14666 }
14667 }")
14669 ;; Unconditional branch and return.
14671 (define_insn "jump"
14672 [(set (pc)
14673 (label_ref (match_operand 0 "" "")))]
14674 ""
14675 "b %l0"
14676 [(set_attr "type" "branch")])
14678 (define_insn "<return_str>return"
14679 [(any_return)]
14680 "<return_pred>"
14681 "blr"
14682 [(set_attr "type" "jmpreg")])
14684 (define_expand "indirect_jump"
14685 [(set (pc) (match_operand 0 "register_operand" ""))])
14687 (define_insn "*indirect_jump<mode>"
14688 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14689 ""
14690 "@
14691 bctr
14692 blr"
14693 [(set_attr "type" "jmpreg")])
14695 ;; Table jump for switch statements:
14696 (define_expand "tablejump"
14697 [(use (match_operand 0 "" ""))
14698 (use (label_ref (match_operand 1 "" "")))]
14699 ""
14700 "
14701 {
14702 if (TARGET_32BIT)
14703 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14704 else
14705 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14706 DONE;
14707 }")
14709 (define_expand "tablejumpsi"
14710 [(set (match_dup 3)
14711 (plus:SI (match_operand:SI 0 "" "")
14712 (match_dup 2)))
14713 (parallel [(set (pc) (match_dup 3))
14714 (use (label_ref (match_operand 1 "" "")))])]
14715 "TARGET_32BIT"
14716 "
14717 { operands[0] = force_reg (SImode, operands[0]);
14718 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14719 operands[3] = gen_reg_rtx (SImode);
14720 }")
14722 (define_expand "tablejumpdi"
14723 [(set (match_dup 4)
14724 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14725 (set (match_dup 3)
14726 (plus:DI (match_dup 4)
14727 (match_dup 2)))
14728 (parallel [(set (pc) (match_dup 3))
14729 (use (label_ref (match_operand 1 "" "")))])]
14730 "TARGET_64BIT"
14731 "
14732 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14733 operands[3] = gen_reg_rtx (DImode);
14734 operands[4] = gen_reg_rtx (DImode);
14735 }")
14737 (define_insn "*tablejump<mode>_internal1"
14738 [(set (pc)
14739 (match_operand:P 0 "register_operand" "c,*l"))
14740 (use (label_ref (match_operand 1 "" "")))]
14741 ""
14742 "@
14743 bctr
14744 blr"
14745 [(set_attr "type" "jmpreg")])
14747 (define_insn "nop"
14748 [(const_int 0)]
14749 ""
14750 "nop")
14752 (define_insn "group_ending_nop"
14753 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
14754 ""
14755 "*
14756 {
14757 if (rs6000_cpu_attr == CPU_POWER6)
14758 return \"ori 1,1,0\";
14759 return \"ori 2,2,0\";
14760 }")
14761 \f
14762 ;; Define the subtract-one-and-jump insns, starting with the template
14763 ;; so loop.c knows what to generate.
14765 (define_expand "doloop_end"
14766 [(use (match_operand 0 "" "")) ; loop pseudo
14767 (use (match_operand 1 "" ""))] ; label
14768 ""
14769 "
14770 {
14771 if (TARGET_64BIT)
14772 {
14773 if (GET_MODE (operands[0]) != DImode)
14774 FAIL;
14775 emit_jump_insn (gen_ctrdi (operands[0], operands[1]));
14776 }
14777 else
14778 {
14779 if (GET_MODE (operands[0]) != SImode)
14780 FAIL;
14781 emit_jump_insn (gen_ctrsi (operands[0], operands[1]));
14782 }
14783 DONE;
14784 }")
14786 (define_expand "ctr<mode>"
14787 [(parallel [(set (pc)
14788 (if_then_else (ne (match_operand:P 0 "register_operand" "")
14789 (const_int 1))
14790 (label_ref (match_operand 1 "" ""))
14791 (pc)))
14792 (set (match_dup 0)
14793 (plus:P (match_dup 0)
14794 (const_int -1)))
14795 (clobber (match_scratch:CC 2 ""))
14796 (clobber (match_scratch:P 3 ""))])]
14797 ""
14798 "")
14800 ;; We need to be able to do this for any operand, including MEM, or we
14801 ;; will cause reload to blow up since we don't allow output reloads on
14802 ;; JUMP_INSNs.
14803 ;; For the length attribute to be calculated correctly, the
14804 ;; label MUST be operand 0.
14806 (define_insn "*ctr<mode>_internal1"
14807 [(set (pc)
14808 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14809 (const_int 1))
14810 (label_ref (match_operand 0 "" ""))
14811 (pc)))
14812 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14813 (plus:P (match_dup 1)
14814 (const_int -1)))
14815 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14816 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14817 ""
14818 "*
14819 {
14820 if (which_alternative != 0)
14821 return \"#\";
14822 else if (get_attr_length (insn) == 4)
14823 return \"bdnz %l0\";
14824 else
14825 return \"bdz $+8\;b %l0\";
14826 }"
14827 [(set_attr "type" "branch")
14828 (set_attr "length" "*,12,16,16")])
14830 (define_insn "*ctr<mode>_internal2"
14831 [(set (pc)
14832 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14833 (const_int 1))
14834 (pc)
14835 (label_ref (match_operand 0 "" ""))))
14836 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14837 (plus:P (match_dup 1)
14838 (const_int -1)))
14839 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14840 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14841 ""
14842 "*
14843 {
14844 if (which_alternative != 0)
14845 return \"#\";
14846 else if (get_attr_length (insn) == 4)
14847 return \"bdz %l0\";
14848 else
14849 return \"bdnz $+8\;b %l0\";
14850 }"
14851 [(set_attr "type" "branch")
14852 (set_attr "length" "*,12,16,16")])
14854 ;; Similar but use EQ
14856 (define_insn "*ctr<mode>_internal5"
14857 [(set (pc)
14858 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14859 (const_int 1))
14860 (label_ref (match_operand 0 "" ""))
14861 (pc)))
14862 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14863 (plus:P (match_dup 1)
14864 (const_int -1)))
14865 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14866 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14867 ""
14868 "*
14869 {
14870 if (which_alternative != 0)
14871 return \"#\";
14872 else if (get_attr_length (insn) == 4)
14873 return \"bdz %l0\";
14874 else
14875 return \"bdnz $+8\;b %l0\";
14876 }"
14877 [(set_attr "type" "branch")
14878 (set_attr "length" "*,12,16,16")])
14880 (define_insn "*ctr<mode>_internal6"
14881 [(set (pc)
14882 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
14883 (const_int 1))
14884 (pc)
14885 (label_ref (match_operand 0 "" ""))))
14886 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l")
14887 (plus:P (match_dup 1)
14888 (const_int -1)))
14889 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14890 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14891 ""
14892 "*
14893 {
14894 if (which_alternative != 0)
14895 return \"#\";
14896 else if (get_attr_length (insn) == 4)
14897 return \"bdnz %l0\";
14898 else
14899 return \"bdz $+8\;b %l0\";
14900 }"
14901 [(set_attr "type" "branch")
14902 (set_attr "length" "*,12,16,16")])
14904 ;; Now the splitters if we could not allocate the CTR register
14906 (define_split
14907 [(set (pc)
14908 (if_then_else (match_operator 2 "comparison_operator"
14909 [(match_operand:P 1 "gpc_reg_operand" "")
14910 (const_int 1)])
14911 (match_operand 5 "" "")
14912 (match_operand 6 "" "")))
14913 (set (match_operand:P 0 "gpc_reg_operand" "")
14914 (plus:P (match_dup 1) (const_int -1)))
14915 (clobber (match_scratch:CC 3 ""))
14916 (clobber (match_scratch:P 4 ""))]
14917 "reload_completed"
14918 [(parallel [(set (match_dup 3)
14919 (compare:CC (plus:P (match_dup 1)
14920 (const_int -1))
14921 (const_int 0)))
14922 (set (match_dup 0)
14923 (plus:P (match_dup 1)
14924 (const_int -1)))])
14925 (set (pc) (if_then_else (match_dup 7)
14926 (match_dup 5)
14927 (match_dup 6)))]
14928 "
14929 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14930 operands[3], const0_rtx); }")
14932 (define_split
14933 [(set (pc)
14934 (if_then_else (match_operator 2 "comparison_operator"
14935 [(match_operand:P 1 "gpc_reg_operand" "")
14936 (const_int 1)])
14937 (match_operand 5 "" "")
14938 (match_operand 6 "" "")))
14939 (set (match_operand:P 0 "nonimmediate_operand" "")
14940 (plus:P (match_dup 1) (const_int -1)))
14941 (clobber (match_scratch:CC 3 ""))
14942 (clobber (match_scratch:P 4 ""))]
14943 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
14944 [(parallel [(set (match_dup 3)
14945 (compare:CC (plus:P (match_dup 1)
14946 (const_int -1))
14947 (const_int 0)))
14948 (set (match_dup 4)
14949 (plus:P (match_dup 1)
14950 (const_int -1)))])
14951 (set (match_dup 0)
14952 (match_dup 4))
14953 (set (pc) (if_then_else (match_dup 7)
14954 (match_dup 5)
14955 (match_dup 6)))]
14956 "
14957 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14958 operands[3], const0_rtx); }")
14959 \f
14960 (define_insn "trap"
14961 [(trap_if (const_int 1) (const_int 0))]
14962 ""
14963 "trap"
14964 [(set_attr "type" "trap")])
14966 (define_expand "ctrap<mode>4"
14967 [(trap_if (match_operator 0 "ordered_comparison_operator"
14968 [(match_operand:GPR 1 "register_operand")
14969 (match_operand:GPR 2 "reg_or_short_operand")])
14970 (match_operand 3 "zero_constant" ""))]
14971 ""
14972 "")
14974 (define_insn ""
14975 [(trap_if (match_operator 0 "ordered_comparison_operator"
14976 [(match_operand:GPR 1 "register_operand" "r")
14977 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
14978 (const_int 0))]
14979 ""
14980 "t<wd>%V0%I2 %1,%2"
14981 [(set_attr "type" "trap")])
14982 \f
14983 ;; Insns related to generating the function prologue and epilogue.
14985 (define_expand "prologue"
14986 [(use (const_int 0))]
14987 ""
14988 {
14989 rs6000_emit_prologue ();
14990 if (!TARGET_SCHED_PROLOG)
14991 emit_insn (gen_blockage ());
14992 DONE;
14993 })
14995 (define_insn "*movesi_from_cr_one"
14996 [(match_parallel 0 "mfcr_operation"
14997 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14998 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14999 (match_operand 3 "immediate_operand" "n")]
15000 UNSPEC_MOVESI_FROM_CR))])]
15001 "TARGET_MFCRF"
15002 "*
15003 {
15004 int mask = 0;
15005 int i;
15006 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15007 {
15008 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15009 operands[4] = GEN_INT (mask);
15010 output_asm_insn (\"mfcr %1,%4\", operands);
15011 }
15012 return \"\";
15013 }"
15014 [(set_attr "type" "mfcrf")])
15016 (define_insn "movesi_from_cr"
15017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15018 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15019 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15020 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15021 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15022 UNSPEC_MOVESI_FROM_CR))]
15023 ""
15024 "mfcr %0"
15025 [(set_attr "type" "mfcr")])
15027 (define_insn "*crsave"
15028 [(match_parallel 0 "crsave_operation"
15029 [(set (match_operand:SI 1 "memory_operand" "=m")
15030 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15031 ""
15032 "stw %2,%1"
15033 [(set_attr "type" "store")])
15035 (define_insn "*stmw"
15036 [(match_parallel 0 "stmw_operation"
15037 [(set (match_operand:SI 1 "memory_operand" "=m")
15038 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15039 "TARGET_MULTIPLE"
15040 "stmw %2,%1"
15041 [(set_attr "type" "store_ux")])
15043 ; The following comment applies to:
15044 ; save_gpregs_*
15045 ; save_fpregs_*
15046 ; restore_gpregs*
15047 ; return_and_restore_gpregs*
15048 ; return_and_restore_fpregs*
15049 ; return_and_restore_fpregs_aix*
15050 ;
15051 ; The out-of-line save / restore functions expects one input argument.
15052 ; Since those are not standard call_insn's, we must avoid using
15053 ; MATCH_OPERAND for that argument. That way the register rename
15054 ; optimization will not try to rename this register.
15055 ; Each pattern is repeated for each possible register number used in
15056 ; various ABIs (r11, r1, and for some functions r12)
15058 (define_insn "*save_gpregs_<mode>_r11"
15059 [(match_parallel 0 "any_parallel_operand"
15060 [(clobber (reg:P 65))
15061 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15062 (use (reg:P 11))
15063 (set (match_operand:P 2 "memory_operand" "=m")
15064 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15065 ""
15066 "bl %1"
15067 [(set_attr "type" "branch")
15068 (set_attr "length" "4")])
15070 (define_insn "*save_gpregs_<mode>_r12"
15071 [(match_parallel 0 "any_parallel_operand"
15072 [(clobber (reg:P 65))
15073 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15074 (use (reg:P 12))
15075 (set (match_operand:P 2 "memory_operand" "=m")
15076 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15077 ""
15078 "bl %1"
15079 [(set_attr "type" "branch")
15080 (set_attr "length" "4")])
15082 (define_insn "*save_gpregs_<mode>_r1"
15083 [(match_parallel 0 "any_parallel_operand"
15084 [(clobber (reg:P 65))
15085 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15086 (use (reg:P 1))
15087 (set (match_operand:P 2 "memory_operand" "=m")
15088 (match_operand:P 3 "gpc_reg_operand" "r"))])]
15089 ""
15090 "bl %1"
15091 [(set_attr "type" "branch")
15092 (set_attr "length" "4")])
15094 (define_insn "*save_fpregs_<mode>_r11"
15095 [(match_parallel 0 "any_parallel_operand"
15096 [(clobber (reg:P 65))
15097 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15098 (use (reg:P 11))
15099 (set (match_operand:DF 2 "memory_operand" "=m")
15100 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15101 ""
15102 "bl %1"
15103 [(set_attr "type" "branch")
15104 (set_attr "length" "4")])
15106 (define_insn "*save_fpregs_<mode>_r12"
15107 [(match_parallel 0 "any_parallel_operand"
15108 [(clobber (reg:P 65))
15109 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15110 (use (reg:P 12))
15111 (set (match_operand:DF 2 "memory_operand" "=m")
15112 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15113 ""
15114 "bl %1"
15115 [(set_attr "type" "branch")
15116 (set_attr "length" "4")])
15118 (define_insn "*save_fpregs_<mode>_r1"
15119 [(match_parallel 0 "any_parallel_operand"
15120 [(clobber (reg:P 65))
15121 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15122 (use (reg:P 1))
15123 (set (match_operand:DF 2 "memory_operand" "=m")
15124 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
15125 ""
15126 "bl %1"
15127 [(set_attr "type" "branch")
15128 (set_attr "length" "4")])
15130 ; This is to explain that changes to the stack pointer should
15131 ; not be moved over loads from or stores to stack memory.
15132 (define_insn "stack_tie"
15133 [(match_parallel 0 "tie_operand"
15134 [(set (mem:BLK (reg 1)) (const_int 0))])]
15135 ""
15136 ""
15137 [(set_attr "length" "0")])
15139 (define_expand "epilogue"
15140 [(use (const_int 0))]
15141 ""
15142 {
15143 if (!TARGET_SCHED_PROLOG)
15144 emit_insn (gen_blockage ());
15145 rs6000_emit_epilogue (FALSE);
15146 DONE;
15147 })
15149 ; On some processors, doing the mtcrf one CC register at a time is
15150 ; faster (like on the 604e). On others, doing them all at once is
15151 ; faster; for instance, on the 601 and 750.
15153 (define_expand "movsi_to_cr_one"
15154 [(set (match_operand:CC 0 "cc_reg_operand" "")
15155 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15156 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15157 ""
15158 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15160 (define_insn "*movsi_to_cr"
15161 [(match_parallel 0 "mtcrf_operation"
15162 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15163 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15164 (match_operand 3 "immediate_operand" "n")]
15165 UNSPEC_MOVESI_TO_CR))])]
15166 ""
15167 "*
15168 {
15169 int mask = 0;
15170 int i;
15171 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15172 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15173 operands[4] = GEN_INT (mask);
15174 return \"mtcrf %4,%2\";
15175 }"
15176 [(set_attr "type" "mtcr")])
15178 (define_insn "*mtcrfsi"
15179 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15180 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15181 (match_operand 2 "immediate_operand" "n")]
15182 UNSPEC_MOVESI_TO_CR))]
15183 "GET_CODE (operands[0]) == REG
15184 && CR_REGNO_P (REGNO (operands[0]))
15185 && GET_CODE (operands[2]) == CONST_INT
15186 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15187 "mtcrf %R0,%1"
15188 [(set_attr "type" "mtcr")])
15190 ; The load-multiple instructions have similar properties.
15191 ; Note that "load_multiple" is a name known to the machine-independent
15192 ; code that actually corresponds to the PowerPC load-string.
15194 (define_insn "*lmw"
15195 [(match_parallel 0 "lmw_operation"
15196 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15197 (match_operand:SI 2 "memory_operand" "m"))])]
15198 "TARGET_MULTIPLE"
15199 "lmw %1,%2"
15200 [(set_attr "type" "load_ux")
15201 (set_attr "cell_micro" "always")])
15203 (define_insn "*return_internal_<mode>"
15204 [(simple_return)
15205 (use (match_operand:P 0 "register_operand" "lc"))]
15206 ""
15207 "b%T0"
15208 [(set_attr "type" "jmpreg")])
15210 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15211 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15213 ; The following comment applies to:
15214 ; save_gpregs_*
15215 ; save_fpregs_*
15216 ; restore_gpregs*
15217 ; return_and_restore_gpregs*
15218 ; return_and_restore_fpregs*
15219 ; return_and_restore_fpregs_aix*
15220 ;
15221 ; The out-of-line save / restore functions expects one input argument.
15222 ; Since those are not standard call_insn's, we must avoid using
15223 ; MATCH_OPERAND for that argument. That way the register rename
15224 ; optimization will not try to rename this register.
15225 ; Each pattern is repeated for each possible register number used in
15226 ; various ABIs (r11, r1, and for some functions r12)
15228 (define_insn "*restore_gpregs_<mode>_r11"
15229 [(match_parallel 0 "any_parallel_operand"
15230 [(clobber (match_operand:P 1 "register_operand" "=l"))
15231 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15232 (use (reg:P 11))
15233 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15234 (match_operand:P 4 "memory_operand" "m"))])]
15235 ""
15236 "bl %2"
15237 [(set_attr "type" "branch")
15238 (set_attr "length" "4")])
15240 (define_insn "*restore_gpregs_<mode>_r12"
15241 [(match_parallel 0 "any_parallel_operand"
15242 [(clobber (match_operand:P 1 "register_operand" "=l"))
15243 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15244 (use (reg:P 12))
15245 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15246 (match_operand:P 4 "memory_operand" "m"))])]
15247 ""
15248 "bl %2"
15249 [(set_attr "type" "branch")
15250 (set_attr "length" "4")])
15252 (define_insn "*restore_gpregs_<mode>_r1"
15253 [(match_parallel 0 "any_parallel_operand"
15254 [(clobber (match_operand:P 1 "register_operand" "=l"))
15255 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15256 (use (reg:P 1))
15257 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15258 (match_operand:P 4 "memory_operand" "m"))])]
15259 ""
15260 "bl %2"
15261 [(set_attr "type" "branch")
15262 (set_attr "length" "4")])
15264 (define_insn "*return_and_restore_gpregs_<mode>_r11"
15265 [(match_parallel 0 "any_parallel_operand"
15266 [(return)
15267 (clobber (match_operand:P 1 "register_operand" "=l"))
15268 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15269 (use (reg:P 11))
15270 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15271 (match_operand:P 4 "memory_operand" "m"))])]
15272 ""
15273 "b %2"
15274 [(set_attr "type" "branch")
15275 (set_attr "length" "4")])
15277 (define_insn "*return_and_restore_gpregs_<mode>_r12"
15278 [(match_parallel 0 "any_parallel_operand"
15279 [(return)
15280 (clobber (match_operand:P 1 "register_operand" "=l"))
15281 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15282 (use (reg:P 12))
15283 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15284 (match_operand:P 4 "memory_operand" "m"))])]
15285 ""
15286 "b %2"
15287 [(set_attr "type" "branch")
15288 (set_attr "length" "4")])
15290 (define_insn "*return_and_restore_gpregs_<mode>_r1"
15291 [(match_parallel 0 "any_parallel_operand"
15292 [(return)
15293 (clobber (match_operand:P 1 "register_operand" "=l"))
15294 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15295 (use (reg:P 1))
15296 (set (match_operand:P 3 "gpc_reg_operand" "=r")
15297 (match_operand:P 4 "memory_operand" "m"))])]
15298 ""
15299 "b %2"
15300 [(set_attr "type" "branch")
15301 (set_attr "length" "4")])
15303 (define_insn "*return_and_restore_fpregs_<mode>_r11"
15304 [(match_parallel 0 "any_parallel_operand"
15305 [(return)
15306 (clobber (match_operand:P 1 "register_operand" "=l"))
15307 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15308 (use (reg:P 11))
15309 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15310 (match_operand:DF 4 "memory_operand" "m"))])]
15311 ""
15312 "b %2"
15313 [(set_attr "type" "branch")
15314 (set_attr "length" "4")])
15316 (define_insn "*return_and_restore_fpregs_<mode>_r12"
15317 [(match_parallel 0 "any_parallel_operand"
15318 [(return)
15319 (clobber (match_operand:P 1 "register_operand" "=l"))
15320 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15321 (use (reg:P 12))
15322 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15323 (match_operand:DF 4 "memory_operand" "m"))])]
15324 ""
15325 "b %2"
15326 [(set_attr "type" "branch")
15327 (set_attr "length" "4")])
15329 (define_insn "*return_and_restore_fpregs_<mode>_r1"
15330 [(match_parallel 0 "any_parallel_operand"
15331 [(return)
15332 (clobber (match_operand:P 1 "register_operand" "=l"))
15333 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15334 (use (reg:P 1))
15335 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15336 (match_operand:DF 4 "memory_operand" "m"))])]
15337 ""
15338 "b %2"
15339 [(set_attr "type" "branch")
15340 (set_attr "length" "4")])
15342 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
15343 [(match_parallel 0 "any_parallel_operand"
15344 [(return)
15345 (use (match_operand:P 1 "register_operand" "l"))
15346 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15347 (use (reg:P 11))
15348 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15349 (match_operand:DF 4 "memory_operand" "m"))])]
15350 ""
15351 "b %2"
15352 [(set_attr "type" "branch")
15353 (set_attr "length" "4")])
15355 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
15356 [(match_parallel 0 "any_parallel_operand"
15357 [(return)
15358 (use (match_operand:P 1 "register_operand" "l"))
15359 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15360 (use (reg:P 1))
15361 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
15362 (match_operand:DF 4 "memory_operand" "m"))])]
15363 ""
15364 "b %2"
15365 [(set_attr "type" "branch")
15366 (set_attr "length" "4")])
15368 ; This is used in compiling the unwind routines.
15369 (define_expand "eh_return"
15370 [(use (match_operand 0 "general_operand" ""))]
15371 ""
15372 "
15373 {
15374 if (TARGET_32BIT)
15375 emit_insn (gen_eh_set_lr_si (operands[0]));
15376 else
15377 emit_insn (gen_eh_set_lr_di (operands[0]));
15378 DONE;
15379 }")
15381 ; We can't expand this before we know where the link register is stored.
15382 (define_insn "eh_set_lr_<mode>"
15383 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15384 UNSPECV_EH_RR)
15385 (clobber (match_scratch:P 1 "=&b"))]
15386 ""
15387 "#")
15389 (define_split
15390 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15391 (clobber (match_scratch 1 ""))]
15392 "reload_completed"
15393 [(const_int 0)]
15394 "
15395 {
15396 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15397 DONE;
15398 }")
15400 (define_insn "prefetch"
15401 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15402 (match_operand:SI 1 "const_int_operand" "n")
15403 (match_operand:SI 2 "const_int_operand" "n"))]
15404 ""
15405 "*
15406 {
15407 if (GET_CODE (operands[0]) == REG)
15408 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15409 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15410 }"
15411 [(set_attr "type" "load")])
15412 \f
15413 (define_insn "bpermd_<mode>"
15414 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15415 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15416 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15417 "TARGET_POPCNTD"
15418 "bpermd %0,%1,%2"
15419 [(set_attr "type" "popcnt")])
15421 \f
15422 ;; Builtin fma support. Handle
15423 ;; Note that the conditions for expansion are in the FMA_F iterator.
15425 (define_expand "fma<mode>4"
15426 [(set (match_operand:FMA_F 0 "register_operand" "")
15427 (fma:FMA_F
15428 (match_operand:FMA_F 1 "register_operand" "")
15429 (match_operand:FMA_F 2 "register_operand" "")
15430 (match_operand:FMA_F 3 "register_operand" "")))]
15431 ""
15432 "")
15434 (define_insn "*fma<mode>4_fpr"
15435 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15436 (fma:SFDF
15437 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
15438 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15439 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
15440 "TARGET_<MODE>_FPR"
15441 "@
15442 fmadd<Ftrad> %0,%1,%2,%3
15443 xsmadda<Fvsx> %x0,%x1,%x2
15444 xsmaddm<Fvsx> %x0,%x1,%x3"
15445 [(set_attr "type" "fp")
15446 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15448 ; Altivec only has fma and nfms.
15449 (define_expand "fms<mode>4"
15450 [(set (match_operand:FMA_F 0 "register_operand" "")
15451 (fma:FMA_F
15452 (match_operand:FMA_F 1 "register_operand" "")
15453 (match_operand:FMA_F 2 "register_operand" "")
15454 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
15455 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15456 "")
15458 (define_insn "*fms<mode>4_fpr"
15459 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15460 (fma:SFDF
15461 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15462 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15463 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
15464 "TARGET_<MODE>_FPR"
15465 "@
15466 fmsub<Ftrad> %0,%1,%2,%3
15467 xsmsuba<Fvsx> %x0,%x1,%x2
15468 xsmsubm<Fvsx> %x0,%x1,%x3"
15469 [(set_attr "type" "fp")
15470 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15472 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
15473 (define_expand "fnma<mode>4"
15474 [(set (match_operand:FMA_F 0 "register_operand" "")
15475 (neg:FMA_F
15476 (fma:FMA_F
15477 (match_operand:FMA_F 1 "register_operand" "")
15478 (match_operand:FMA_F 2 "register_operand" "")
15479 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15480 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
15481 "")
15483 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
15484 (define_expand "fnms<mode>4"
15485 [(set (match_operand:FMA_F 0 "register_operand" "")
15486 (neg:FMA_F
15487 (fma:FMA_F
15488 (match_operand:FMA_F 1 "register_operand" "")
15489 (match_operand:FMA_F 2 "register_operand" "")
15490 (match_operand:FMA_F 3 "register_operand" ""))))]
15491 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15492 "")
15494 ; Not an official optab name, but used from builtins.
15495 (define_expand "nfma<mode>4"
15496 [(set (match_operand:FMA_F 0 "register_operand" "")
15497 (neg:FMA_F
15498 (fma:FMA_F
15499 (match_operand:FMA_F 1 "register_operand" "")
15500 (match_operand:FMA_F 2 "register_operand" "")
15501 (match_operand:FMA_F 3 "register_operand" ""))))]
15502 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
15503 "")
15505 (define_insn "*nfma<mode>4_fpr"
15506 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15507 (neg:SFDF
15508 (fma:SFDF
15509 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15510 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15511 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
15512 "TARGET_<MODE>_FPR"
15513 "@
15514 fnmadd<Ftrad> %0,%1,%2,%3
15515 xsnmadda<Fvsx> %x0,%x1,%x2
15516 xsnmaddm<Fvsx> %x0,%x1,%x3"
15517 [(set_attr "type" "fp")
15518 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15520 ; Not an official optab name, but used from builtins.
15521 (define_expand "nfms<mode>4"
15522 [(set (match_operand:FMA_F 0 "register_operand" "")
15523 (neg:FMA_F
15524 (fma:FMA_F
15525 (match_operand:FMA_F 1 "register_operand" "")
15526 (match_operand:FMA_F 2 "register_operand" "")
15527 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
15528 ""
15529 "")
15531 (define_insn "*nfmssf4_fpr"
15532 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
15533 (neg:SFDF
15534 (fma:SFDF
15535 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
15536 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
15537 (neg:SFDF
15538 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
15539 "TARGET_<MODE>_FPR"
15540 "@
15541 fnmsub<Ftrad> %0,%1,%2,%3
15542 xsnmsuba<Fvsx> %x0,%x1,%x2
15543 xsnmsubm<Fvsx> %x0,%x1,%x3"
15544 [(set_attr "type" "fp")
15545 (set_attr "fp_type" "fp_maddsub_<Fs>")])
15547 \f
15548 (define_expand "rs6000_get_timebase"
15549 [(use (match_operand:DI 0 "gpc_reg_operand" ""))]
15550 ""
15551 {
15552 if (TARGET_POWERPC64)
15553 emit_insn (gen_rs6000_mftb_di (operands[0]));
15554 else
15555 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0]));
15556 DONE;
15557 })
15559 (define_insn "rs6000_get_timebase_ppc32"
15560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
15561 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB))
15562 (clobber (match_scratch:SI 1 "=r"))
15563 (clobber (match_scratch:CC 2 "=y"))]
15564 "!TARGET_POWERPC64"
15565 {
15566 if (WORDS_BIG_ENDIAN)
15567 if (TARGET_MFCRF)
15568 {
15569 return "mfspr %0,269\;"
15570 "mfspr %L0,268\;"
15571 "mfspr %1,269\;"
15572 "cmpw %2,%0,%1\;"
15573 "bne- %2,$-16";
15574 }
15575 else
15576 {
15577 return "mftbu %0\;"
15578 "mftb %L0\;"
15579 "mftbu %1\;"
15580 "cmpw %2,%0,%1\;"
15581 "bne- %2,$-16";
15582 }
15583 else
15584 if (TARGET_MFCRF)
15585 {
15586 return "mfspr %L0,269\;"
15587 "mfspr %0,268\;"
15588 "mfspr %1,269\;"
15589 "cmpw %2,%L0,%1\;"
15590 "bne- %2,$-16";
15591 }
15592 else
15593 {
15594 return "mftbu %L0\;"
15595 "mftb %0\;"
15596 "mftbu %1\;"
15597 "cmpw %2,%L0,%1\;"
15598 "bne- %2,$-16";
15599 }
15600 }
15601 [(set_attr "length" "20")])
15603 (define_insn "rs6000_mftb_<mode>"
15604 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15605 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))]
15606 ""
15607 {
15608 if (TARGET_MFCRF)
15609 return "mfspr %0,268";
15610 else
15611 return "mftb %0";
15612 })
15614 \f
15615 (define_insn "rs6000_mffs"
15616 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
15617 (unspec_volatile:DF [(const_int 0)] UNSPECV_MFFS))]
15618 "TARGET_HARD_FLOAT && TARGET_FPRS"
15619 "mffs %0")
15621 (define_insn "rs6000_mtfsf"
15622 [(unspec_volatile [(match_operand:SI 0 "const_int_operand" "i")
15623 (match_operand:DF 1 "gpc_reg_operand" "d")]
15624 UNSPECV_MTFSF)]
15625 "TARGET_HARD_FLOAT && TARGET_FPRS"
15626 "mtfsf %0,%1")
15628 \f
15629 ;; Power8 fusion support for fusing an addis instruction with a D-form load of
15630 ;; a GPR. The addis instruction must be adjacent to the load, and use the same
15631 ;; register that is being loaded. The fused ops must be physically adjacent.
15633 ;; We use define_peephole for the actual addis/load, and the register used to
15634 ;; hold the addis value must be the same as the register being loaded. We use
15635 ;; define_peephole2 to change the register used for addis to be the register
15636 ;; being loaded, since we can look at whether it is dead after the load insn.
15638 (define_peephole
15639 [(set (match_operand:P 0 "base_reg_operand" "")
15640 (match_operand:P 1 "fusion_gpr_addis" ""))
15641 (set (match_operand:INT1 2 "base_reg_operand" "")
15642 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15643 "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)"
15644 {
15645 return emit_fusion_gpr_load (operands);
15646 }
15647 [(set_attr "type" "load")
15648 (set_attr "length" "8")])
15650 (define_peephole2
15651 [(set (match_operand:P 0 "base_reg_operand" "")
15652 (match_operand:P 1 "fusion_gpr_addis" ""))
15653 (set (match_operand:INT1 2 "base_reg_operand" "")
15654 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))]
15655 "TARGET_P8_FUSION
15656 && (REGNO (operands[0]) != REGNO (operands[2])
15657 || GET_CODE (operands[3]) == SIGN_EXTEND)
15658 && fusion_gpr_load_p (operands, true)"
15659 [(const_int 0)]
15660 {
15661 expand_fusion_gpr_load (operands);
15662 DONE;
15663 })
15665 \f
15667 (include "sync.md")
15668 (include "vector.md")
15669 (include "vsx.md")
15670 (include "altivec.md")
15671 (include "spe.md")
15672 (include "dfp.md")
15673 (include "paired.md")
15674 (include "crypto.md")
15675 (include "htm.md")