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mips.md (UNSPEC_COMPARE_AND_SWAP, [...]): New define_constants.
[official-gcc.git] / gcc / config / mips / mips.h
bloba44460b08532cf9fc4b01cefde519057aa01685c
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_M4K,
51 PROCESSOR_R3900,
52 PROCESSOR_R6000,
53 PROCESSOR_R4000,
54 PROCESSOR_R4100,
55 PROCESSOR_R4111,
56 PROCESSOR_R4120,
57 PROCESSOR_R4130,
58 PROCESSOR_R4300,
59 PROCESSOR_R4600,
60 PROCESSOR_R4650,
61 PROCESSOR_R5000,
62 PROCESSOR_R5400,
63 PROCESSOR_R5500,
64 PROCESSOR_R7000,
65 PROCESSOR_R8000,
66 PROCESSOR_R9000,
67 PROCESSOR_SB1,
68 PROCESSOR_SB1A,
69 PROCESSOR_SR71000,
70 PROCESSOR_MAX
71 };
72
73 /* Costs of various operations on the different architectures. */
74
75 struct mips_rtx_cost_data
76 {
77 unsigned short fp_add;
78 unsigned short fp_mult_sf;
79 unsigned short fp_mult_df;
80 unsigned short fp_div_sf;
81 unsigned short fp_div_df;
82 unsigned short int_mult_si;
83 unsigned short int_mult_di;
84 unsigned short int_div_si;
85 unsigned short int_div_di;
86 unsigned short branch_cost;
87 unsigned short memory_latency;
88 };
89
90 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
91 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
92 to work on a 64-bit machine. */
93
94 #define ABI_32 0
95 #define ABI_N32 1
96 #define ABI_64 2
97 #define ABI_EABI 3
98 #define ABI_O64 4
99
100 /* Information about one recognized processor. Defined here for the
101 benefit of TARGET_CPU_CPP_BUILTINS. */
102 struct mips_cpu_info {
103 /* The 'canonical' name of the processor as far as GCC is concerned.
104 It's typically a manufacturer's prefix followed by a numerical
105 designation. It should be lowercase. */
106 const char *name;
107
108 /* The internal processor number that most closely matches this
109 entry. Several processors can have the same value, if there's no
110 difference between them from GCC's point of view. */
111 enum processor_type cpu;
112
113 /* The ISA level that the processor implements. */
114 int isa;
115 };
116
117 /* Enumerates the setting of the -mcode-readable option. */
118 enum mips_code_readable_setting {
119 CODE_READABLE_NO,
120 CODE_READABLE_PCREL,
121 CODE_READABLE_YES
122 };
123
124 #ifndef USED_FOR_TARGET
125 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
126 extern const char *current_function_file; /* filename current function is in */
127 extern int num_source_filenames; /* current .file # */
128 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
129 extern int sym_lineno; /* sgi next label # for each stmt */
130 extern int set_noreorder; /* # of nested .set noreorder's */
131 extern int set_nomacro; /* # of nested .set nomacro's */
132 extern int set_noat; /* # of nested .set noat's */
133 extern int set_volatile; /* # of nested .set volatile's */
134 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
135 extern int mips_dbx_regno[];
136 extern int mips_dwarf_regno[];
137 extern bool mips_split_p[];
138 extern GTY(()) rtx cmp_operands[2];
139 extern enum processor_type mips_arch; /* which cpu to codegen for */
140 extern enum processor_type mips_tune; /* which cpu to schedule for */
141 extern int mips_isa; /* architectural level */
142 extern int mips_abi; /* which ABI to use */
143 extern const struct mips_cpu_info mips_cpu_info_table[];
144 extern const struct mips_cpu_info *mips_arch_info;
145 extern const struct mips_cpu_info *mips_tune_info;
146 extern const struct mips_rtx_cost_data *mips_cost;
147 extern enum mips_code_readable_setting mips_code_readable;
148 #endif
149
150 /* Macros to silence warnings about numbers being signed in traditional
151 C and unsigned in ISO C when compiled on 32-bit hosts. */
152
153 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
154 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
155 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
156
157 \f
158 /* Run-time compilation parameters selecting different hardware subsets. */
159
160 /* True if we are generating position-independent VxWorks RTP code. */
161 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
162
163 /* True if the call patterns should be split into a jalr followed by
164 an instruction to restore $gp. It is only safe to split the load
165 from the call when every use of $gp is explicit. */
166
167 #define TARGET_SPLIT_CALLS \
168 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
169
170 /* True if we're generating a form of -mabicalls in which we can use
171 operators like %hi and %lo to refer to locally-binding symbols.
172 We can only do this for -mno-shared, and only then if we can use
173 relocation operations instead of assembly macros. It isn't really
174 worth using absolute sequences for 64-bit symbols because GOT
175 accesses are so much shorter. */
176
177 #define TARGET_ABSOLUTE_ABICALLS \
178 (TARGET_ABICALLS \
179 && !TARGET_SHARED \
180 && TARGET_EXPLICIT_RELOCS \
181 && !ABI_HAS_64BIT_SYMBOLS)
182
183 /* True if we can optimize sibling calls. For simplicity, we only
184 handle cases in which call_insn_operand will reject invalid
185 sibcall addresses. There are two cases in which this isn't true:
186
187 - TARGET_MIPS16. call_insn_operand accepts constant addresses
188 but there is no direct jump instruction. It isn't worth
189 using sibling calls in this case anyway; they would usually
190 be longer than normal calls.
191
192 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
193 accepts global constants, but all sibcalls must be indirect. */
194 #define TARGET_SIBCALLS \
195 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
196
197 /* True if we need to use a global offset table to access some symbols. */
198 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
199
200 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
201 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
202
203 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
204 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
205
206 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
207 This is true for both the PIC and non-PIC VxWorks RTP modes. */
208 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
209
210 /* True if .gpword or .gpdword should be used for switch tables.
211
212 Although GAS does understand .gpdword, the SGI linker mishandles
213 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
214 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
215 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
216
217 /* Generate mips16 code */
218 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
219 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
220 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
221 /* Generate mips16e register save/restore sequences. */
222 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
223
224 /* True if we're generating a form of MIPS16 code in which general
225 text loads are allowed. */
226 #define TARGET_MIPS16_TEXT_LOADS \
227 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
228
229 /* True if we're generating a form of MIPS16 code in which PC-relative
230 loads are allowed. */
231 #define TARGET_MIPS16_PCREL_LOADS \
232 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
233
234 /* Generic ISA defines. */
235 #define ISA_MIPS1 (mips_isa == 1)
236 #define ISA_MIPS2 (mips_isa == 2)
237 #define ISA_MIPS3 (mips_isa == 3)
238 #define ISA_MIPS4 (mips_isa == 4)
239 #define ISA_MIPS32 (mips_isa == 32)
240 #define ISA_MIPS32R2 (mips_isa == 33)
241 #define ISA_MIPS64 (mips_isa == 64)
242
243 /* Architecture target defines. */
244 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
245 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
246 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
247 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
248 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
249 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
250 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
251 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
252 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
253 || mips_arch == PROCESSOR_SB1A)
254 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
255
256 /* Scheduling target defines. */
257 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
258 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
259 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
260 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
261 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
262 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
263 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
264 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
265 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
266 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
267 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
268 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
269 || mips_tune == PROCESSOR_SB1A)
270 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
271 || mips_tune == PROCESSOR_24KF2_1 \
272 || mips_tune == PROCESSOR_24KF1_1)
273 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
274 || mips_tune == PROCESSOR_74KF2_1 \
275 || mips_tune == PROCESSOR_74KF1_1 \
276 || mips_tune == PROCESSOR_74KF3_2)
277 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
278
279 /* True if the pre-reload scheduler should try to create chains of
280 multiply-add or multiply-subtract instructions. For example,
281 suppose we have:
282
283 t1 = a * b
284 t2 = t1 + c * d
285 t3 = e * f
286 t4 = t3 - g * h
287
288 t1 will have a higher priority than t2 and t3 will have a higher
289 priority than t4. However, before reload, there is no dependence
290 between t1 and t3, and they can often have similar priorities.
291 The scheduler will then tend to prefer:
292
293 t1 = a * b
294 t3 = e * f
295 t2 = t1 + c * d
296 t4 = t3 - g * h
297
298 which stops us from making full use of macc/madd-style instructions.
299 This sort of situation occurs frequently in Fourier transforms and
300 in unrolled loops.
301
302 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
303 queue so that chained multiply-add and multiply-subtract instructions
304 appear ahead of any other instruction that is likely to clobber lo.
305 In the example above, if t2 and t3 become ready at the same time,
306 the code ensures that t2 is scheduled first.
307
308 Multiply-accumulate instructions are a bigger win for some targets
309 than others, so this macro is defined on an opt-in basis. */
310 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
311 || TUNE_MIPS4120 \
312 || TUNE_MIPS4130 \
313 || TUNE_24K)
314
315 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
316 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
317
318 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
319 directly accessible, while the command-line options select
320 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
321 in use. */
322 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
323 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
324
325 /* IRIX specific stuff. */
326 #define TARGET_IRIX 0
327 #define TARGET_IRIX6 0
328
329 /* Define preprocessor macros for the -march and -mtune options.
330 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
331 processor. If INFO's canonical name is "foo", define PREFIX to
332 be "foo", and define an additional macro PREFIX_FOO. */
333 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
334 do \
335 { \
336 char *macro, *p; \
337 \
338 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
339 for (p = macro; *p != 0; p++) \
340 *p = TOUPPER (*p); \
341 \
342 builtin_define (macro); \
343 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
344 free (macro); \
345 } \
346 while (0)
347
348 /* Target CPU builtins. */
349 #define TARGET_CPU_CPP_BUILTINS() \
350 do \
351 { \
352 /* Everyone but IRIX defines this to mips. */ \
353 if (!TARGET_IRIX) \
354 builtin_assert ("machine=mips"); \
355 \
356 builtin_assert ("cpu=mips"); \
357 builtin_define ("__mips__"); \
358 builtin_define ("_mips"); \
359 \
360 /* We do this here because __mips is defined below and so we \
361 can't use builtin_define_std. We don't ever want to define \
362 "mips" for VxWorks because some of the VxWorks headers \
363 construct include filenames from a root directory macro, \
364 an architecture macro and a filename, where the architecture \
365 macro expands to 'mips'. If we define 'mips' to 1, the \
366 architecture macro expands to 1 as well. */ \
367 if (!flag_iso && !TARGET_VXWORKS) \
368 builtin_define ("mips"); \
369 \
370 if (TARGET_64BIT) \
371 builtin_define ("__mips64"); \
372 \
373 if (!TARGET_IRIX) \
374 { \
375 /* Treat _R3000 and _R4000 like register-size \
376 defines, which is how they've historically \
377 been used. */ \
378 if (TARGET_64BIT) \
379 { \
380 builtin_define_std ("R4000"); \
381 builtin_define ("_R4000"); \
382 } \
383 else \
384 { \
385 builtin_define_std ("R3000"); \
386 builtin_define ("_R3000"); \
387 } \
388 } \
389 if (TARGET_FLOAT64) \
390 builtin_define ("__mips_fpr=64"); \
391 else \
392 builtin_define ("__mips_fpr=32"); \
393 \
394 if (TARGET_MIPS16) \
395 builtin_define ("__mips16"); \
396 \
397 if (TARGET_MIPS3D) \
398 builtin_define ("__mips3d"); \
399 \
400 if (TARGET_SMARTMIPS) \
401 builtin_define ("__mips_smartmips"); \
402 \
403 if (TARGET_DSP) \
404 { \
405 builtin_define ("__mips_dsp"); \
406 if (TARGET_DSPR2) \
407 { \
408 builtin_define ("__mips_dspr2"); \
409 builtin_define ("__mips_dsp_rev=2"); \
410 } \
411 else \
412 builtin_define ("__mips_dsp_rev=1"); \
413 } \
414 \
415 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
416 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
417 \
418 if (ISA_MIPS1) \
419 { \
420 builtin_define ("__mips=1"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
422 } \
423 else if (ISA_MIPS2) \
424 { \
425 builtin_define ("__mips=2"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
427 } \
428 else if (ISA_MIPS3) \
429 { \
430 builtin_define ("__mips=3"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
432 } \
433 else if (ISA_MIPS4) \
434 { \
435 builtin_define ("__mips=4"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
437 } \
438 else if (ISA_MIPS32) \
439 { \
440 builtin_define ("__mips=32"); \
441 builtin_define ("__mips_isa_rev=1"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
443 } \
444 else if (ISA_MIPS32R2) \
445 { \
446 builtin_define ("__mips=32"); \
447 builtin_define ("__mips_isa_rev=2"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
449 } \
450 else if (ISA_MIPS64) \
451 { \
452 builtin_define ("__mips=64"); \
453 builtin_define ("__mips_isa_rev=1"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
455 } \
456 \
457 switch (mips_abi) \
458 { \
459 case ABI_32: \
460 builtin_define ("_ABIO32=1"); \
461 builtin_define ("_MIPS_SIM=_ABIO32"); \
462 break; \
463 \
464 case ABI_N32: \
465 builtin_define ("_ABIN32=2"); \
466 builtin_define ("_MIPS_SIM=_ABIN32"); \
467 break; \
468 \
469 case ABI_64: \
470 builtin_define ("_ABI64=3"); \
471 builtin_define ("_MIPS_SIM=_ABI64"); \
472 break; \
473 \
474 case ABI_O64: \
475 builtin_define ("_ABIO64=4"); \
476 builtin_define ("_MIPS_SIM=_ABIO64"); \
477 break; \
478 } \
479 \
480 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
481 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
482 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
483 builtin_define_with_int_value ("_MIPS_FPSET", \
484 32 / MAX_FPRS_PER_FMT); \
485 \
486 /* These defines reflect the ABI in use, not whether the \
487 FPU is directly accessible. */ \
488 if (TARGET_HARD_FLOAT_ABI) \
489 builtin_define ("__mips_hard_float"); \
490 else \
491 builtin_define ("__mips_soft_float"); \
492 \
493 if (TARGET_SINGLE_FLOAT) \
494 builtin_define ("__mips_single_float"); \
495 \
496 if (TARGET_PAIRED_SINGLE_FLOAT) \
497 builtin_define ("__mips_paired_single_float"); \
498 \
499 if (TARGET_BIG_ENDIAN) \
500 { \
501 builtin_define_std ("MIPSEB"); \
502 builtin_define ("_MIPSEB"); \
503 } \
504 else \
505 { \
506 builtin_define_std ("MIPSEL"); \
507 builtin_define ("_MIPSEL"); \
508 } \
509 \
510 /* Macros dependent on the C dialect. */ \
511 if (preprocessing_asm_p ()) \
512 { \
513 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
514 builtin_define ("_LANGUAGE_ASSEMBLY"); \
515 } \
516 else if (c_dialect_cxx ()) \
517 { \
518 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
519 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
520 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
521 } \
522 else \
523 { \
524 builtin_define_std ("LANGUAGE_C"); \
525 builtin_define ("_LANGUAGE_C"); \
526 } \
527 if (c_dialect_objc ()) \
528 { \
529 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
530 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
531 /* Bizarre, but needed at least for Irix. */ \
532 builtin_define_std ("LANGUAGE_C"); \
533 builtin_define ("_LANGUAGE_C"); \
534 } \
535 \
536 if (mips_abi == ABI_EABI) \
537 builtin_define ("__mips_eabi"); \
538 } \
539 while (0)
540
541 /* Default target_flags if no switches are specified */
542
543 #ifndef TARGET_DEFAULT
544 #define TARGET_DEFAULT 0
545 #endif
546
547 #ifndef TARGET_CPU_DEFAULT
548 #define TARGET_CPU_DEFAULT 0
549 #endif
550
551 #ifndef TARGET_ENDIAN_DEFAULT
552 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
553 #endif
554
555 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
556 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
557 #endif
558
559 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
560 #ifndef MIPS_ISA_DEFAULT
561 #ifndef MIPS_CPU_STRING_DEFAULT
562 #define MIPS_CPU_STRING_DEFAULT "from-abi"
563 #endif
564 #endif
565
566 #ifdef IN_LIBGCC2
567 #undef TARGET_64BIT
568 /* Make this compile time constant for libgcc2 */
569 #ifdef __mips64
570 #define TARGET_64BIT 1
571 #else
572 #define TARGET_64BIT 0
573 #endif
574 #endif /* IN_LIBGCC2 */
575
576 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
577
578 #ifndef MULTILIB_ENDIAN_DEFAULT
579 #if TARGET_ENDIAN_DEFAULT == 0
580 #define MULTILIB_ENDIAN_DEFAULT "EL"
581 #else
582 #define MULTILIB_ENDIAN_DEFAULT "EB"
583 #endif
584 #endif
585
586 #ifndef MULTILIB_ISA_DEFAULT
587 # if MIPS_ISA_DEFAULT == 1
588 # define MULTILIB_ISA_DEFAULT "mips1"
589 # else
590 # if MIPS_ISA_DEFAULT == 2
591 # define MULTILIB_ISA_DEFAULT "mips2"
592 # else
593 # if MIPS_ISA_DEFAULT == 3
594 # define MULTILIB_ISA_DEFAULT "mips3"
595 # else
596 # if MIPS_ISA_DEFAULT == 4
597 # define MULTILIB_ISA_DEFAULT "mips4"
598 # else
599 # if MIPS_ISA_DEFAULT == 32
600 # define MULTILIB_ISA_DEFAULT "mips32"
601 # else
602 # if MIPS_ISA_DEFAULT == 33
603 # define MULTILIB_ISA_DEFAULT "mips32r2"
604 # else
605 # if MIPS_ISA_DEFAULT == 64
606 # define MULTILIB_ISA_DEFAULT "mips64"
607 # else
608 # define MULTILIB_ISA_DEFAULT "mips1"
609 # endif
610 # endif
611 # endif
612 # endif
613 # endif
614 # endif
615 # endif
616 #endif
617
618 #ifndef MULTILIB_DEFAULTS
619 #define MULTILIB_DEFAULTS \
620 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
621 #endif
622
623 /* We must pass -EL to the linker by default for little endian embedded
624 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
625 linker will default to using big-endian output files. The OUTPUT_FORMAT
626 line must be in the linker script, otherwise -EB/-EL will not work. */
627
628 #ifndef ENDIAN_SPEC
629 #if TARGET_ENDIAN_DEFAULT == 0
630 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
631 #else
632 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
633 #endif
634 #endif
635
636 /* A spec condition that matches all non-mips16 -mips arguments. */
637
638 #define MIPS_ISA_LEVEL_OPTION_SPEC \
639 "mips1|mips2|mips3|mips4|mips32*|mips64*"
640
641 /* A spec condition that matches all non-mips16 architecture arguments. */
642
643 #define MIPS_ARCH_OPTION_SPEC \
644 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
645
646 /* A spec that infers a -mips argument from an -march argument,
647 or injects the default if no architecture is specified. */
648
649 #define MIPS_ISA_LEVEL_SPEC \
650 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
651 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
652 %{march=mips2|march=r6000:-mips2} \
653 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
654 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
655 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
656 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
657 |march=34k*|march=74k*: -mips32r2} \
658 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
659 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
660
661 /* A spec condition that matches 32-bit options. It only works if
662 MIPS_ISA_LEVEL_SPEC has been applied. */
663
664 #define MIPS_32BIT_OPTION_SPEC \
665 "mips1|mips2|mips32*|mgp32"
666
667 /* Support for a compile-time default CPU, et cetera. The rules are:
668 --with-arch is ignored if -march is specified or a -mips is specified
669 (other than -mips16).
670 --with-tune is ignored if -mtune is specified.
671 --with-abi is ignored if -mabi is specified.
672 --with-float is ignored if -mhard-float or -msoft-float are
673 specified.
674 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
675 specified. */
676 #define OPTION_DEFAULT_SPECS \
677 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
678 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
679 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
680 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
681 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
682
683
684 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
685 && ISA_HAS_COND_TRAP)
686
687 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
688 && !TARGET_SR71K \
689 && !TARGET_MIPS16)
690
691 /* True if the ABI can only work with 64-bit integer registers. We
692 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
693 otherwise floating-point registers must also be 64-bit. */
694 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
695
696 /* Likewise for 32-bit regs. */
697 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
698
699 /* True if symbols are 64 bits wide. At present, n64 is the only
700 ABI for which this is true. */
701 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
702
703 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
704 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
705 || ISA_MIPS4 \
706 || ISA_MIPS64)
707
708 /* ISA has branch likely instructions (e.g. mips2). */
709 /* Disable branchlikely for tx39 until compare rewrite. They haven't
710 been generated up to this point. */
711 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
712
713 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
714 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
715 || TARGET_MIPS5400 \
716 || TARGET_MIPS5500 \
717 || TARGET_MIPS7000 \
718 || TARGET_MIPS9000 \
719 || TARGET_MAD \
720 || ISA_MIPS32 \
721 || ISA_MIPS32R2 \
722 || ISA_MIPS64) \
723 && !TARGET_MIPS16)
724
725 /* ISA has the conditional move instructions introduced in mips4. */
726 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
727 || ISA_MIPS32 \
728 || ISA_MIPS32R2 \
729 || ISA_MIPS64) \
730 && !TARGET_MIPS5500 \
731 && !TARGET_MIPS16)
732
733 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
734 branch on CC, and move (both FP and non-FP) on CC. */
735 #define ISA_HAS_8CC (ISA_MIPS4 \
736 || ISA_MIPS32 \
737 || ISA_MIPS32R2 \
738 || ISA_MIPS64)
739
740 /* This is a catch all for other mips4 instructions: indexed load, the
741 FP madd and msub instructions, and the FP recip and recip sqrt
742 instructions. */
743 #define ISA_HAS_FP4 ((ISA_MIPS4 \
744 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
745 || ISA_MIPS64) \
746 && !TARGET_MIPS16)
747
748 /* ISA has conditional trap instructions. */
749 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
750 && !TARGET_MIPS16)
751
752 /* ISA has integer multiply-accumulate instructions, madd and msub. */
753 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
754 || ISA_MIPS32R2 \
755 || ISA_MIPS64) \
756 && !TARGET_MIPS16)
757
758 /* Integer multiply-accumulate instructions should be generated. */
759 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
760
761 /* ISA has floating-point nmadd and nmsub instructions. */
762 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
763 || ISA_MIPS64) \
764 && (!TARGET_MIPS5400 || TARGET_MAD) \
765 && !TARGET_MIPS16)
766
767 /* ISA has count leading zeroes/ones instruction (not implemented). */
768 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
769 || ISA_MIPS32R2 \
770 || ISA_MIPS64) \
771 && !TARGET_MIPS16)
772
773 /* ISA has three operand multiply instructions that put
774 the high part in an accumulator: mulhi or mulhiu. */
775 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
776 || TARGET_MIPS5500 \
777 || TARGET_SR71K) \
778 && !TARGET_MIPS16)
779
780 /* ISA has three operand multiply instructions that
781 negates the result and puts the result in an accumulator. */
782 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
783 || TARGET_MIPS5500 \
784 || TARGET_SR71K) \
785 && !TARGET_MIPS16)
786
787 /* ISA has three operand multiply instructions that subtracts the
788 result from a 4th operand and puts the result in an accumulator. */
789 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
790 || TARGET_MIPS5500 \
791 || TARGET_SR71K) \
792 && !TARGET_MIPS16)
793
794 /* ISA has three operand multiply instructions that the result
795 from a 4th operand and puts the result in an accumulator. */
796 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
797 || TARGET_MIPS4130 \
798 || TARGET_MIPS5400 \
799 || TARGET_MIPS5500 \
800 || TARGET_SR71K) \
801 && !TARGET_MIPS16)
802
803 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
804 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
805 || TARGET_MIPS4130) \
806 && !TARGET_MIPS16)
807
808 /* ISA has the "ror" (rotate right) instructions. */
809 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
810 || TARGET_MIPS5400 \
811 || TARGET_MIPS5500 \
812 || TARGET_SR71K \
813 || TARGET_SMARTMIPS) \
814 && !TARGET_MIPS16)
815
816 /* ISA has data prefetch instructions. This controls use of 'pref'. */
817 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
818 || ISA_MIPS32 \
819 || ISA_MIPS32R2 \
820 || ISA_MIPS64) \
821 && !TARGET_MIPS16)
822
823 /* ISA has data indexed prefetch instructions. This controls use of
824 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
825 (prefx is a cop1x instruction, so can only be used if FP is
826 enabled.) */
827 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
828 || ISA_MIPS32R2 \
829 || ISA_MIPS64) \
830 && !TARGET_MIPS16)
831
832 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
833 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
834 also requires TARGET_DOUBLE_FLOAT. */
835 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
836
837 /* ISA includes the MIPS32r2 seb and seh instructions. */
838 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
839 && !TARGET_MIPS16)
840
841 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
842 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
843 && !TARGET_MIPS16)
844
845 /* ISA has instructions for accessing top part of 64-bit fp regs. */
846 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
847
848 /* ISA has lwxs instruction (load w/scaled index address. */
849 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
850
851 /* True if the result of a load is not available to the next instruction.
852 A nop will then be needed between instructions like "lw $4,..."
853 and "addiu $4,$4,1". */
854 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
855 && !TARGET_MIPS3900 \
856 && !TARGET_MIPS16)
857
858 /* Likewise mtc1 and mfc1. */
859 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
860
861 /* Likewise floating-point comparisons. */
862 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
863
864 /* True if mflo and mfhi can be immediately followed by instructions
865 which write to the HI and LO registers.
866
867 According to MIPS specifications, MIPS ISAs I, II, and III need
868 (at least) two instructions between the reads of HI/LO and
869 instructions which write them, and later ISAs do not. Contradicting
870 the MIPS specifications, some MIPS IV processor user manuals (e.g.
871 the UM for the NEC Vr5000) document needing the instructions between
872 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
873 MIPS64 and later ISAs to have the interlocks, plus any specific
874 earlier-ISA CPUs for which CPU documentation declares that the
875 instructions are really interlocked. */
876 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
877 || ISA_MIPS32R2 \
878 || ISA_MIPS64 \
879 || TARGET_MIPS5500)
880
881 /* ISA includes synci, jr.hb and jalr.hb. */
882 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
883
884 /* ISA includes sync. */
885 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
886
887 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
888 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
889 instructions. */
890 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
891 \f
892 /* Add -G xx support. */
893
894 #undef SWITCH_TAKES_ARG
895 #define SWITCH_TAKES_ARG(CHAR) \
896 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
897
898 #define OVERRIDE_OPTIONS override_options ()
899
900 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
901
902 /* Show we can debug even without a frame pointer. */
903 #define CAN_DEBUG_WITHOUT_FP
904 \f
905 /* Tell collect what flags to pass to nm. */
906 #ifndef NM_FLAGS
907 #define NM_FLAGS "-Bn"
908 #endif
909
910 \f
911 #ifndef MIPS_ABI_DEFAULT
912 #define MIPS_ABI_DEFAULT ABI_32
913 #endif
914
915 /* Use the most portable ABI flag for the ASM specs. */
916
917 #if MIPS_ABI_DEFAULT == ABI_32
918 #define MULTILIB_ABI_DEFAULT "mabi=32"
919 #endif
920
921 #if MIPS_ABI_DEFAULT == ABI_O64
922 #define MULTILIB_ABI_DEFAULT "mabi=o64"
923 #endif
924
925 #if MIPS_ABI_DEFAULT == ABI_N32
926 #define MULTILIB_ABI_DEFAULT "mabi=n32"
927 #endif
928
929 #if MIPS_ABI_DEFAULT == ABI_64
930 #define MULTILIB_ABI_DEFAULT "mabi=64"
931 #endif
932
933 #if MIPS_ABI_DEFAULT == ABI_EABI
934 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
935 #endif
936
937 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
938 to the assembler. It may be overridden by subtargets. */
939 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
940 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
941 %{noasmopt:-O0} \
942 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
943 #endif
944
945 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
946 the assembler. It may be overridden by subtargets.
947
948 Beginning with gas 2.13, -mdebug must be passed to correctly handle
949 COFF debugging info. */
950
951 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
952 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
953 %{g} %{g0} %{g1} %{g2} %{g3} \
954 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
955 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
956 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
957 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
958 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
959 #endif
960
961 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
962 overridden by subtargets. */
963
964 #ifndef SUBTARGET_ASM_SPEC
965 #define SUBTARGET_ASM_SPEC ""
966 #endif
967
968 #undef ASM_SPEC
969 #define ASM_SPEC "\
970 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
971 %{mips32} %{mips32r2} %{mips64} \
972 %{mips16} %{mno-mips16:-no-mips16} \
973 %{mips3d} %{mno-mips3d:-no-mips3d} \
974 %{mdmx} %{mno-mdmx:-no-mdmx} \
975 %{mdsp} %{mno-dsp} \
976 %{mdspr2} %{mno-dspr2} \
977 %{msmartmips} %{mno-smartmips} \
978 %{mmt} %{mno-mt} \
979 %{mfix-vr4120} %{mfix-vr4130} \
980 %(subtarget_asm_optimizing_spec) \
981 %(subtarget_asm_debugging_spec) \
982 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
983 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
984 %{mfp32} %{mfp64} \
985 %{mshared} %{mno-shared} \
986 %{msym32} %{mno-sym32} \
987 %{mtune=*} %{v} \
988 %(subtarget_asm_spec)"
989
990 /* Extra switches sometimes passed to the linker. */
991 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
992 will interpret it as a -b option. */
993
994 #ifndef LINK_SPEC
995 #define LINK_SPEC "\
996 %(endian_spec) \
997 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
998 %{bestGnum} %{shared} %{non_shared}"
999 #endif /* LINK_SPEC defined */
1000
1001
1002 /* Specs for the compiler proper */
1003
1004 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1005 overridden by subtargets. */
1006 #ifndef SUBTARGET_CC1_SPEC
1007 #define SUBTARGET_CC1_SPEC ""
1008 #endif
1009
1010 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1011
1012 #undef CC1_SPEC
1013 #define CC1_SPEC "\
1014 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1015 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1016 %{save-temps: } \
1017 %(subtarget_cc1_spec)"
1018
1019 /* Preprocessor specs. */
1020
1021 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1022 overridden by subtargets. */
1023 #ifndef SUBTARGET_CPP_SPEC
1024 #define SUBTARGET_CPP_SPEC ""
1025 #endif
1026
1027 #define CPP_SPEC "%(subtarget_cpp_spec)"
1028
1029 /* This macro defines names of additional specifications to put in the specs
1030 that can be used in various specifications like CC1_SPEC. Its definition
1031 is an initializer with a subgrouping for each command option.
1032
1033 Each subgrouping contains a string constant, that defines the
1034 specification name, and a string constant that used by the GCC driver
1035 program.
1036
1037 Do not define this macro if it does not need to do anything. */
1038
1039 #define EXTRA_SPECS \
1040 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1041 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1042 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1043 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1044 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1045 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1046 { "endian_spec", ENDIAN_SPEC }, \
1047 SUBTARGET_EXTRA_SPECS
1048
1049 #ifndef SUBTARGET_EXTRA_SPECS
1050 #define SUBTARGET_EXTRA_SPECS
1051 #endif
1052 \f
1053 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1054 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1055 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1056
1057 #ifndef PREFERRED_DEBUGGING_TYPE
1058 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1059 #endif
1060
1061 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1062
1063 /* By default, turn on GDB extensions. */
1064 #define DEFAULT_GDB_EXTENSIONS 1
1065
1066 /* Local compiler-generated symbols must have a prefix that the assembler
1067 understands. By default, this is $, although some targets (e.g.,
1068 NetBSD-ELF) need to override this. */
1069
1070 #ifndef LOCAL_LABEL_PREFIX
1071 #define LOCAL_LABEL_PREFIX "$"
1072 #endif
1073
1074 /* By default on the mips, external symbols do not have an underscore
1075 prepended, but some targets (e.g., NetBSD) require this. */
1076
1077 #ifndef USER_LABEL_PREFIX
1078 #define USER_LABEL_PREFIX ""
1079 #endif
1080
1081 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1082 since the length can run past this up to a continuation point. */
1083 #undef DBX_CONTIN_LENGTH
1084 #define DBX_CONTIN_LENGTH 1500
1085
1086 /* How to renumber registers for dbx and gdb. */
1087 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1088
1089 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1090 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1091
1092 /* The DWARF 2 CFA column which tracks the return address. */
1093 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1094
1095 /* Before the prologue, RA lives in r31. */
1096 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1097
1098 /* Describe how we implement __builtin_eh_return. */
1099 #define EH_RETURN_DATA_REGNO(N) \
1100 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1101
1102 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1103
1104 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1105 The default for this in 64-bit mode is 8, which causes problems with
1106 SFmode register saves. */
1107 #define DWARF_CIE_DATA_ALIGNMENT -4
1108
1109 /* Correct the offset of automatic variables and arguments. Note that
1110 the MIPS debug format wants all automatic variables and arguments
1111 to be in terms of the virtual frame pointer (stack pointer before
1112 any adjustment in the function), while the MIPS 3.0 linker wants
1113 the frame pointer to be the stack pointer after the initial
1114 adjustment. */
1115
1116 #define DEBUGGER_AUTO_OFFSET(X) \
1117 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1118 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1119 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1120 \f
1121 /* Target machine storage layout */
1122
1123 #define BITS_BIG_ENDIAN 0
1124 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1125 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1126
1127 /* Define this to set the endianness to use in libgcc2.c, which can
1128 not depend on target_flags. */
1129 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1130 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1131 #else
1132 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1133 #endif
1134
1135 #define MAX_BITS_PER_WORD 64
1136
1137 /* Width of a word, in units (bytes). */
1138 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1139 #ifndef IN_LIBGCC2
1140 #define MIN_UNITS_PER_WORD 4
1141 #endif
1142
1143 /* For MIPS, width of a floating point register. */
1144 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1145
1146 /* The number of consecutive floating-point registers needed to store the
1147 largest format supported by the FPU. */
1148 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1149
1150 /* The number of consecutive floating-point registers needed to store the
1151 smallest format supported by the FPU. */
1152 #define MIN_FPRS_PER_FMT \
1153 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1154
1155 /* The largest size of value that can be held in floating-point
1156 registers and moved with a single instruction. */
1157 #define UNITS_PER_HWFPVALUE \
1158 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1159
1160 /* The largest size of value that can be held in floating-point
1161 registers. */
1162 #define UNITS_PER_FPVALUE \
1163 (TARGET_SOFT_FLOAT_ABI ? 0 \
1164 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1165 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1166
1167 /* The number of bytes in a double. */
1168 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1169
1170 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1171
1172 /* Set the sizes of the core types. */
1173 #define SHORT_TYPE_SIZE 16
1174 #define INT_TYPE_SIZE 32
1175 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1176 #define LONG_LONG_TYPE_SIZE 64
1177
1178 #define FLOAT_TYPE_SIZE 32
1179 #define DOUBLE_TYPE_SIZE 64
1180 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1181
1182 /* long double is not a fixed mode, but the idea is that, if we
1183 support long double, we also want a 128-bit integer type. */
1184 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1185
1186 #ifdef IN_LIBGCC2
1187 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1188 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1189 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1190 # else
1191 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1192 # endif
1193 #endif
1194
1195 /* Width in bits of a pointer. */
1196 #ifndef POINTER_SIZE
1197 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1198 #endif
1199
1200 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1201 #define PARM_BOUNDARY BITS_PER_WORD
1202
1203 /* Allocation boundary (in *bits*) for the code of a function. */
1204 #define FUNCTION_BOUNDARY 32
1205
1206 /* Alignment of field after `int : 0' in a structure. */
1207 #define EMPTY_FIELD_BOUNDARY 32
1208
1209 /* Every structure's size must be a multiple of this. */
1210 /* 8 is observed right on a DECstation and on riscos 4.02. */
1211 #define STRUCTURE_SIZE_BOUNDARY 8
1212
1213 /* There is no point aligning anything to a rounder boundary than this. */
1214 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1215
1216 /* All accesses must be aligned. */
1217 #define STRICT_ALIGNMENT 1
1218
1219 /* Define this if you wish to imitate the way many other C compilers
1220 handle alignment of bitfields and the structures that contain
1221 them.
1222
1223 The behavior is that the type written for a bit-field (`int',
1224 `short', or other integer type) imposes an alignment for the
1225 entire structure, as if the structure really did contain an
1226 ordinary field of that type. In addition, the bit-field is placed
1227 within the structure so that it would fit within such a field,
1228 not crossing a boundary for it.
1229
1230 Thus, on most machines, a bit-field whose type is written as `int'
1231 would not cross a four-byte boundary, and would force four-byte
1232 alignment for the whole structure. (The alignment used may not
1233 be four bytes; it is controlled by the other alignment
1234 parameters.)
1235
1236 If the macro is defined, its definition should be a C expression;
1237 a nonzero value for the expression enables this behavior. */
1238
1239 #define PCC_BITFIELD_TYPE_MATTERS 1
1240
1241 /* If defined, a C expression to compute the alignment given to a
1242 constant that is being placed in memory. CONSTANT is the constant
1243 and ALIGN is the alignment that the object would ordinarily have.
1244 The value of this macro is used instead of that alignment to align
1245 the object.
1246
1247 If this macro is not defined, then ALIGN is used.
1248
1249 The typical use of this macro is to increase alignment for string
1250 constants to be word aligned so that `strcpy' calls that copy
1251 constants can be done inline. */
1252
1253 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1254 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1255 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1256
1257 /* If defined, a C expression to compute the alignment for a static
1258 variable. TYPE is the data type, and ALIGN is the alignment that
1259 the object would ordinarily have. The value of this macro is used
1260 instead of that alignment to align the object.
1261
1262 If this macro is not defined, then ALIGN is used.
1263
1264 One use of this macro is to increase alignment of medium-size
1265 data to make it all fit in fewer cache lines. Another is to
1266 cause character arrays to be word-aligned so that `strcpy' calls
1267 that copy constants to character arrays can be done inline. */
1268
1269 #undef DATA_ALIGNMENT
1270 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1271 ((((ALIGN) < BITS_PER_WORD) \
1272 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1273 || TREE_CODE (TYPE) == UNION_TYPE \
1274 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1275
1276
1277 #define PAD_VARARGS_DOWN \
1278 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1279
1280 /* Define if operations between registers always perform the operation
1281 on the full register even if a narrower mode is specified. */
1282 #define WORD_REGISTER_OPERATIONS
1283
1284 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1285 moves. All other references are zero extended. */
1286 #define LOAD_EXTEND_OP(MODE) \
1287 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1288 ? SIGN_EXTEND : ZERO_EXTEND)
1289
1290 /* Define this macro if it is advisable to hold scalars in registers
1291 in a wider mode than that declared by the program. In such cases,
1292 the value is constrained to be within the bounds of the declared
1293 type, but kept valid in the wider mode. The signedness of the
1294 extension may differ from that of the type. */
1295
1296 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1297 if (GET_MODE_CLASS (MODE) == MODE_INT \
1298 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1299 { \
1300 if ((MODE) == SImode) \
1301 (UNSIGNEDP) = 0; \
1302 (MODE) = Pmode; \
1303 }
1304
1305 /* Define if loading short immediate values into registers sign extends. */
1306 #define SHORT_IMMEDIATES_SIGN_EXTEND
1307
1308 /* The [d]clz instructions have the natural values at 0. */
1309
1310 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1311 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1312 \f
1313 /* Standard register usage. */
1314
1315 /* Number of hardware registers. We have:
1316
1317 - 32 integer registers
1318 - 32 floating point registers
1319 - 8 condition code registers
1320 - 2 accumulator registers (hi and lo)
1321 - 32 registers each for coprocessors 0, 2 and 3
1322 - 3 fake registers:
1323 - ARG_POINTER_REGNUM
1324 - FRAME_POINTER_REGNUM
1325 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1326 - 3 dummy entries that were used at various times in the past.
1327 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1328 - 6 DSP control registers */
1329
1330 #define FIRST_PSEUDO_REGISTER 188
1331
1332 /* By default, fix the kernel registers ($26 and $27), the global
1333 pointer ($28) and the stack pointer ($29). This can change
1334 depending on the command-line options.
1335
1336 Regarding coprocessor registers: without evidence to the contrary,
1337 it's best to assume that each coprocessor register has a unique
1338 use. This can be overridden, in, e.g., override_options() or
1339 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1340 for a particular target. */
1341
1342 #define FIXED_REGISTERS \
1343 { \
1344 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1345 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1346 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1347 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1348 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1349 /* COP0 registers */ \
1350 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1351 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1352 /* COP2 registers */ \
1353 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1354 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1355 /* COP3 registers */ \
1356 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1357 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1358 /* 6 DSP accumulator registers & 6 control registers */ \
1359 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1360 }
1361
1362
1363 /* Set up this array for o32 by default.
1364
1365 Note that we don't mark $31 as a call-clobbered register. The idea is
1366 that it's really the call instructions themselves which clobber $31.
1367 We don't care what the called function does with it afterwards.
1368
1369 This approach makes it easier to implement sibcalls. Unlike normal
1370 calls, sibcalls don't clobber $31, so the register reaches the
1371 called function in tact. EPILOGUE_USES says that $31 is useful
1372 to the called function. */
1373
1374 #define CALL_USED_REGISTERS \
1375 { \
1376 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1377 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1378 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1379 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1380 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1381 /* COP0 registers */ \
1382 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1383 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1384 /* COP2 registers */ \
1385 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1386 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1387 /* COP3 registers */ \
1388 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1389 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1390 /* 6 DSP accumulator registers & 6 control registers */ \
1391 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1392 }
1393
1394
1395 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1396
1397 #define CALL_REALLY_USED_REGISTERS \
1398 { /* General registers. */ \
1399 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1400 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1401 /* Floating-point registers. */ \
1402 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1403 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1404 /* Others. */ \
1405 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1406 /* COP0 registers */ \
1407 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1408 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1409 /* COP2 registers */ \
1410 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1411 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1412 /* COP3 registers */ \
1413 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1414 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1415 /* 6 DSP accumulator registers & 6 control registers */ \
1416 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1417 }
1418
1419 /* Internal macros to classify a register number as to whether it's a
1420 general purpose register, a floating point register, a
1421 multiply/divide register, or a status register. */
1422
1423 #define GP_REG_FIRST 0
1424 #define GP_REG_LAST 31
1425 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1426 #define GP_DBX_FIRST 0
1427
1428 #define FP_REG_FIRST 32
1429 #define FP_REG_LAST 63
1430 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1431 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1432
1433 #define MD_REG_FIRST 64
1434 #define MD_REG_LAST 65
1435 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1436 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1437
1438 /* The DWARF 2 CFA column which tracks the return address from a
1439 signal handler context. This means that to maintain backwards
1440 compatibility, no hard register can be assigned this column if it
1441 would need to be handled by the DWARF unwinder. */
1442 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1443
1444 #define ST_REG_FIRST 67
1445 #define ST_REG_LAST 74
1446 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1447
1448
1449 /* FIXME: renumber. */
1450 #define COP0_REG_FIRST 80
1451 #define COP0_REG_LAST 111
1452 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1453
1454 #define COP2_REG_FIRST 112
1455 #define COP2_REG_LAST 143
1456 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1457
1458 #define COP3_REG_FIRST 144
1459 #define COP3_REG_LAST 175
1460 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1461 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1462 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1463
1464 #define DSP_ACC_REG_FIRST 176
1465 #define DSP_ACC_REG_LAST 181
1466 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1467
1468 #define AT_REGNUM (GP_REG_FIRST + 1)
1469 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1470 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1471
1472 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1473 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1474 should be used instead. */
1475 #define FPSW_REGNUM ST_REG_FIRST
1476
1477 #define GP_REG_P(REGNO) \
1478 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1479 #define M16_REG_P(REGNO) \
1480 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1481 #define FP_REG_P(REGNO) \
1482 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1483 #define MD_REG_P(REGNO) \
1484 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1485 #define ST_REG_P(REGNO) \
1486 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1487 #define COP0_REG_P(REGNO) \
1488 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1489 #define COP2_REG_P(REGNO) \
1490 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1491 #define COP3_REG_P(REGNO) \
1492 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1493 #define ALL_COP_REG_P(REGNO) \
1494 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1495 /* Test if REGNO is one of the 6 new DSP accumulators. */
1496 #define DSP_ACC_REG_P(REGNO) \
1497 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1498 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1499 #define ACC_REG_P(REGNO) \
1500 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1501
1502 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1503
1504 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1505 to initialize the mips16 gp pseudo register. */
1506 #define CONST_GP_P(X) \
1507 (GET_CODE (X) == CONST \
1508 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1509 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1510
1511 /* Return coprocessor number from register number. */
1512
1513 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1514 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1515 : COP3_REG_P (REGNO) ? '3' : '?')
1516
1517
1518 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1519
1520 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1521 array built in override_options. Because machmodes.h is not yet
1522 included before this file is processed, the MODE bound can't be
1523 expressed here. */
1524
1525 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1526
1527 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1528 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1529
1530 /* Value is 1 if it is a good idea to tie two pseudo registers
1531 when one has mode MODE1 and one has mode MODE2.
1532 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1533 for any hard reg, then this must be 0 for correct output. */
1534 #define MODES_TIEABLE_P(MODE1, MODE2) \
1535 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1536 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1537 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1538 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1539
1540 /* Register to use for pushing function arguments. */
1541 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1542
1543 /* These two registers don't really exist: they get eliminated to either
1544 the stack or hard frame pointer. */
1545 #define ARG_POINTER_REGNUM 77
1546 #define FRAME_POINTER_REGNUM 78
1547
1548 /* $30 is not available on the mips16, so we use $17 as the frame
1549 pointer. */
1550 #define HARD_FRAME_POINTER_REGNUM \
1551 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1552
1553 /* Value should be nonzero if functions must have frame pointers.
1554 Zero means the frame pointer need not be set up (and parms
1555 may be accessed via the stack pointer) in functions that seem suitable.
1556 This is computed in `reload', in reload1.c. */
1557 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1558
1559 /* Register in which static-chain is passed to a function. */
1560 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1561
1562 /* Registers used as temporaries in prologue/epilogue code. If we're
1563 generating mips16 code, these registers must come from the core set
1564 of 8. The prologue register mustn't conflict with any incoming
1565 arguments, the static chain pointer, or the frame pointer. The
1566 epilogue temporary mustn't conflict with the return registers, the
1567 frame pointer, the EH stack adjustment, or the EH data registers. */
1568
1569 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1570 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1571
1572 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1573 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1574
1575 /* Define this macro if it is as good or better to call a constant
1576 function address than to call an address kept in a register. */
1577 #define NO_FUNCTION_CSE 1
1578
1579 /* The ABI-defined global pointer. Sometimes we use a different
1580 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1581 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1582
1583 /* We normally use $28 as the global pointer. However, when generating
1584 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1585 register instead. They can then avoid saving and restoring $28
1586 and perhaps avoid using a frame at all.
1587
1588 When a leaf function uses something other than $28, mips_expand_prologue
1589 will modify pic_offset_table_rtx in place. Take the register number
1590 from there after reload. */
1591 #define PIC_OFFSET_TABLE_REGNUM \
1592 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1593
1594 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1595 \f
1596 /* Define the classes of registers for register constraints in the
1597 machine description. Also define ranges of constants.
1598
1599 One of the classes must always be named ALL_REGS and include all hard regs.
1600 If there is more than one class, another class must be named NO_REGS
1601 and contain no registers.
1602
1603 The name GENERAL_REGS must be the name of a class (or an alias for
1604 another name such as ALL_REGS). This is the class of registers
1605 that is allowed by "g" or "r" in a register constraint.
1606 Also, registers outside this class are allocated only when
1607 instructions express preferences for them.
1608
1609 The classes must be numbered in nondecreasing order; that is,
1610 a larger-numbered class must never be contained completely
1611 in a smaller-numbered class.
1612
1613 For any two classes, it is very desirable that there be another
1614 class that represents their union. */
1615
1616 enum reg_class
1617 {
1618 NO_REGS, /* no registers in set */
1619 M16_NA_REGS, /* mips16 regs not used to pass args */
1620 M16_REGS, /* mips16 directly accessible registers */
1621 T_REG, /* mips16 T register ($24) */
1622 M16_T_REGS, /* mips16 registers plus T register */
1623 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1624 V1_REG, /* Register $v1 ($3) used for TLS access. */
1625 LEA_REGS, /* Every GPR except $25 */
1626 GR_REGS, /* integer registers */
1627 FP_REGS, /* floating point registers */
1628 MD0_REG, /* first multiply/divide register */
1629 MD1_REG, /* second multiply/divide register */
1630 MD_REGS, /* multiply/divide registers (hi/lo) */
1631 COP0_REGS, /* generic coprocessor classes */
1632 COP2_REGS,
1633 COP3_REGS,
1634 HI_AND_GR_REGS, /* union classes */
1635 LO_AND_GR_REGS,
1636 HI_AND_FP_REGS,
1637 COP0_AND_GR_REGS,
1638 COP2_AND_GR_REGS,
1639 COP3_AND_GR_REGS,
1640 ALL_COP_REGS,
1641 ALL_COP_AND_GR_REGS,
1642 ST_REGS, /* status registers (fp status) */
1643 DSP_ACC_REGS, /* DSP accumulator registers */
1644 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1645 ALL_REGS, /* all registers */
1646 LIM_REG_CLASSES /* max value + 1 */
1647 };
1648
1649 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1650
1651 #define GENERAL_REGS GR_REGS
1652
1653 /* An initializer containing the names of the register classes as C
1654 string constants. These names are used in writing some of the
1655 debugging dumps. */
1656
1657 #define REG_CLASS_NAMES \
1658 { \
1659 "NO_REGS", \
1660 "M16_NA_REGS", \
1661 "M16_REGS", \
1662 "T_REG", \
1663 "M16_T_REGS", \
1664 "PIC_FN_ADDR_REG", \
1665 "V1_REG", \
1666 "LEA_REGS", \
1667 "GR_REGS", \
1668 "FP_REGS", \
1669 "MD0_REG", \
1670 "MD1_REG", \
1671 "MD_REGS", \
1672 /* coprocessor registers */ \
1673 "COP0_REGS", \
1674 "COP2_REGS", \
1675 "COP3_REGS", \
1676 "HI_AND_GR_REGS", \
1677 "LO_AND_GR_REGS", \
1678 "HI_AND_FP_REGS", \
1679 "COP0_AND_GR_REGS", \
1680 "COP2_AND_GR_REGS", \
1681 "COP3_AND_GR_REGS", \
1682 "ALL_COP_REGS", \
1683 "ALL_COP_AND_GR_REGS", \
1684 "ST_REGS", \
1685 "DSP_ACC_REGS", \
1686 "ACC_REGS", \
1687 "ALL_REGS" \
1688 }
1689
1690 /* An initializer containing the contents of the register classes,
1691 as integers which are bit masks. The Nth integer specifies the
1692 contents of class N. The way the integer MASK is interpreted is
1693 that register R is in the class if `MASK & (1 << R)' is 1.
1694
1695 When the machine has more than 32 registers, an integer does not
1696 suffice. Then the integers are replaced by sub-initializers,
1697 braced groupings containing several integers. Each
1698 sub-initializer must be suitable as an initializer for the type
1699 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1700
1701 #define REG_CLASS_CONTENTS \
1702 { \
1703 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1704 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1705 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1706 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1707 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1708 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1709 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1710 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1711 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1712 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1713 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1714 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1715 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1716 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1717 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1718 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1719 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1720 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1721 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1722 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1723 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1724 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1725 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1726 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1727 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1728 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1729 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1730 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1731 }
1732
1733
1734 /* A C expression whose value is a register class containing hard
1735 register REGNO. In general there is more that one such class;
1736 choose a class which is "minimal", meaning that no smaller class
1737 also contains the register. */
1738
1739 extern const enum reg_class mips_regno_to_class[];
1740
1741 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1742
1743 /* A macro whose definition is the name of the class to which a
1744 valid base register must belong. A base register is one used in
1745 an address which is the register value plus a displacement. */
1746
1747 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1748
1749 /* A macro whose definition is the name of the class to which a
1750 valid index register must belong. An index register is one used
1751 in an address where its value is either multiplied by a scale
1752 factor or added to another register (as well as added to a
1753 displacement). */
1754
1755 #define INDEX_REG_CLASS NO_REGS
1756
1757 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1758 registers explicitly used in the rtl to be used as spill registers
1759 but prevents the compiler from extending the lifetime of these
1760 registers. */
1761
1762 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1763
1764 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1765 is the default value (allocate the registers in numeric order). We
1766 define it just so that we can override it for the mips16 target in
1767 ORDER_REGS_FOR_LOCAL_ALLOC. */
1768
1769 #define REG_ALLOC_ORDER \
1770 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1771 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1772 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1773 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1774 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1775 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1776 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1777 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1778 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1779 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1780 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1781 176,177,178,179,180,181,182,183,184,185,186,187 \
1782 }
1783
1784 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1785 to be rearranged based on a particular function. On the mips16, we
1786 want to allocate $24 (T_REG) before other registers for
1787 instructions for which it is possible. */
1788
1789 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1790
1791 /* True if VALUE is an unsigned 6-bit number. */
1792
1793 #define UIMM6_OPERAND(VALUE) \
1794 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1795
1796 /* True if VALUE is a signed 10-bit number. */
1797
1798 #define IMM10_OPERAND(VALUE) \
1799 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1800
1801 /* True if VALUE is a signed 16-bit number. */
1802
1803 #define SMALL_OPERAND(VALUE) \
1804 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1805
1806 /* True if VALUE is an unsigned 16-bit number. */
1807
1808 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1809 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1810
1811 /* True if VALUE can be loaded into a register using LUI. */
1812
1813 #define LUI_OPERAND(VALUE) \
1814 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1815 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1816
1817 /* Return a value X with the low 16 bits clear, and such that
1818 VALUE - X is a signed 16-bit value. */
1819
1820 #define CONST_HIGH_PART(VALUE) \
1821 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1822
1823 #define CONST_LOW_PART(VALUE) \
1824 ((VALUE) - CONST_HIGH_PART (VALUE))
1825
1826 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1827 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1828 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1829
1830 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1831 mips_preferred_reload_class (X, CLASS)
1832
1833 /* The HI and LO registers can only be reloaded via the general
1834 registers. Condition code registers can only be loaded to the
1835 general registers, and from the floating point registers. */
1836
1837 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1838 mips_secondary_reload_class (CLASS, MODE, X, 1)
1839 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1840 mips_secondary_reload_class (CLASS, MODE, X, 0)
1841
1842 /* Return the maximum number of consecutive registers
1843 needed to represent mode MODE in a register of class CLASS. */
1844
1845 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1846
1847 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1848 mips_cannot_change_mode_class (FROM, TO, CLASS)
1849 \f
1850 /* Stack layout; function entry, exit and calling. */
1851
1852 #define STACK_GROWS_DOWNWARD
1853
1854 /* The offset of the first local variable from the beginning of the frame.
1855 See compute_frame_size for details about the frame layout.
1856
1857 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1858 we assume that we will need 16 bytes of argument space. This is because
1859 the value profiling code may emit calls to cmpdi2 in leaf functions.
1860 Without this hack, the local variables will start at sp+8 and the gp save
1861 area will be at sp+16, and thus they will overlap. compute_frame_size is
1862 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1863 will end up as 24 instead of 8. This won't be needed if profiling code is
1864 inserted before virtual register instantiation. */
1865
1866 #define STARTING_FRAME_OFFSET \
1867 ((flag_profile_values && ! TARGET_64BIT \
1868 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1869 : current_function_outgoing_args_size) \
1870 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1871
1872 #define RETURN_ADDR_RTX mips_return_addr
1873
1874 /* Since the mips16 ISA mode is encoded in the least-significant bit
1875 of the address, mask it off return addresses for purposes of
1876 finding exception handling regions. */
1877
1878 #define MASK_RETURN_ADDR GEN_INT (-2)
1879
1880
1881 /* Similarly, don't use the least-significant bit to tell pointers to
1882 code from vtable index. */
1883
1884 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1885
1886 /* The eliminations to $17 are only used for mips16 code. See the
1887 definition of HARD_FRAME_POINTER_REGNUM. */
1888
1889 #define ELIMINABLE_REGS \
1890 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1891 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1892 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1893 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1894 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1895 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1896
1897 /* We can always eliminate to the hard frame pointer. We can eliminate
1898 to the stack pointer unless a frame pointer is needed.
1899
1900 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1901 reload may be unable to compute the address of a local variable,
1902 since there is no way to add a large constant to the stack pointer
1903 without using a temporary register. */
1904 #define CAN_ELIMINATE(FROM, TO) \
1905 ((TO) == HARD_FRAME_POINTER_REGNUM \
1906 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1907 && (!TARGET_MIPS16 \
1908 || compute_frame_size (get_frame_size ()) < 32768)))
1909
1910 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1911 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1912
1913 /* Allocate stack space for arguments at the beginning of each function. */
1914 #define ACCUMULATE_OUTGOING_ARGS 1
1915
1916 /* The argument pointer always points to the first argument. */
1917 #define FIRST_PARM_OFFSET(FNDECL) 0
1918
1919 /* o32 and o64 reserve stack space for all argument registers. */
1920 #define REG_PARM_STACK_SPACE(FNDECL) \
1921 (TARGET_OLDABI \
1922 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1923 : 0)
1924
1925 /* Define this if it is the responsibility of the caller to
1926 allocate the area reserved for arguments passed in registers.
1927 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1928 of this macro is to determine whether the space is included in
1929 `current_function_outgoing_args_size'. */
1930 #define OUTGOING_REG_PARM_STACK_SPACE 1
1931
1932 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1933 \f
1934 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1935
1936 /* Symbolic macros for the registers used to return integer and floating
1937 point values. */
1938
1939 #define GP_RETURN (GP_REG_FIRST + 2)
1940 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1941
1942 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1943
1944 /* Symbolic macros for the first/last argument registers. */
1945
1946 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1947 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1948 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1949 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
1950
1951 #define LIBCALL_VALUE(MODE) \
1952 mips_function_value (NULL_TREE, NULL, (MODE))
1953
1954 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1955 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
1956
1957 /* 1 if N is a possible register number for a function value.
1958 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1959 Currently, R2 and F0 are only implemented here (C has no complex type) */
1960
1961 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
1962 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
1963 && (N) == FP_RETURN + 2))
1964
1965 /* 1 if N is a possible register number for function argument passing.
1966 We have no FP argument registers when soft-float. When FP registers
1967 are 32 bits, we can't directly reference the odd numbered ones. */
1968
1969 #define FUNCTION_ARG_REGNO_P(N) \
1970 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
1971 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
1972 && !fixed_regs[N])
1973 \f
1974 /* This structure has to cope with two different argument allocation
1975 schemes. Most MIPS ABIs view the arguments as a structure, of which
1976 the first N words go in registers and the rest go on the stack. If I
1977 < N, the Ith word might go in Ith integer argument register or in a
1978 floating-point register. For these ABIs, we only need to remember
1979 the offset of the current argument into the structure.
1980
1981 The EABI instead allocates the integer and floating-point arguments
1982 separately. The first N words of FP arguments go in FP registers,
1983 the rest go on the stack. Likewise, the first N words of the other
1984 arguments go in integer registers, and the rest go on the stack. We
1985 need to maintain three counts: the number of integer registers used,
1986 the number of floating-point registers used, and the number of words
1987 passed on the stack.
1988
1989 We could keep separate information for the two ABIs (a word count for
1990 the standard ABIs, and three separate counts for the EABI). But it
1991 seems simpler to view the standard ABIs as forms of EABI that do not
1992 allocate floating-point registers.
1993
1994 So for the standard ABIs, the first N words are allocated to integer
1995 registers, and function_arg decides on an argument-by-argument basis
1996 whether that argument should really go in an integer register, or in
1997 a floating-point one. */
1998
1999 typedef struct mips_args {
2000 /* Always true for varargs functions. Otherwise true if at least
2001 one argument has been passed in an integer register. */
2002 int gp_reg_found;
2003
2004 /* The number of arguments seen so far. */
2005 unsigned int arg_number;
2006
2007 /* The number of integer registers used so far. For all ABIs except
2008 EABI, this is the number of words that have been added to the
2009 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2010 unsigned int num_gprs;
2011
2012 /* For EABI, the number of floating-point registers used so far. */
2013 unsigned int num_fprs;
2014
2015 /* The number of words passed on the stack. */
2016 unsigned int stack_words;
2017
2018 /* On the mips16, we need to keep track of which floating point
2019 arguments were passed in general registers, but would have been
2020 passed in the FP regs if this were a 32-bit function, so that we
2021 can move them to the FP regs if we wind up calling a 32-bit
2022 function. We record this information in fp_code, encoded in base
2023 four. A zero digit means no floating point argument, a one digit
2024 means an SFmode argument, and a two digit means a DFmode argument,
2025 and a three digit is not used. The low order digit is the first
2026 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2027 an SFmode argument. ??? A more sophisticated approach will be
2028 needed if MIPS_ABI != ABI_32. */
2029 int fp_code;
2030
2031 /* True if the function has a prototype. */
2032 int prototype;
2033 } CUMULATIVE_ARGS;
2034
2035 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2036 for a call to a function whose data type is FNTYPE.
2037 For a library call, FNTYPE is 0. */
2038
2039 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2040 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2041
2042 /* Update the data in CUM to advance over an argument
2043 of mode MODE and data type TYPE.
2044 (TYPE is null for libcalls where that information may not be available.) */
2045
2046 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2047 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2048
2049 /* Determine where to put an argument to a function.
2050 Value is zero to push the argument on the stack,
2051 or a hard register in which to store the argument.
2052
2053 MODE is the argument's machine mode.
2054 TYPE is the data type of the argument (as a tree).
2055 This is null for libcalls where that information may
2056 not be available.
2057 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2058 the preceding args and about the function being called.
2059 NAMED is nonzero if this argument is a named parameter
2060 (otherwise it is an extra parameter matching an ellipsis). */
2061
2062 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2063 function_arg( &CUM, MODE, TYPE, NAMED)
2064
2065 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2066
2067 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2068 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2069
2070 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2071 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2072
2073 /* True if using EABI and varargs can be passed in floating-point
2074 registers. Under these conditions, we need a more complex form
2075 of va_list, which tracks GPR, FPR and stack arguments separately. */
2076 #define EABI_FLOAT_VARARGS_P \
2077 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2078
2079 \f
2080 /* Say that the epilogue uses the return address register. Note that
2081 in the case of sibcalls, the values "used by the epilogue" are
2082 considered live at the start of the called function. */
2083 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2084
2085 /* Treat LOC as a byte offset from the stack pointer and round it up
2086 to the next fully-aligned offset. */
2087 #define MIPS_STACK_ALIGN(LOC) \
2088 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2089
2090 \f
2091 /* Implement `va_start' for varargs and stdarg. */
2092 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2093 mips_va_start (valist, nextarg)
2094 \f
2095 /* Output assembler code to FILE to increment profiler label # LABELNO
2096 for profiling a function entry. */
2097
2098 #define FUNCTION_PROFILER(FILE, LABELNO) \
2099 { \
2100 if (TARGET_MIPS16) \
2101 sorry ("mips16 function profiling"); \
2102 fprintf (FILE, "\t.set\tnoat\n"); \
2103 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2104 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2105 if (!TARGET_NEWABI) \
2106 { \
2107 fprintf (FILE, \
2108 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2109 TARGET_64BIT ? "dsubu" : "subu", \
2110 reg_names[STACK_POINTER_REGNUM], \
2111 reg_names[STACK_POINTER_REGNUM], \
2112 Pmode == DImode ? 16 : 8); \
2113 } \
2114 fprintf (FILE, "\tjal\t_mcount\n"); \
2115 fprintf (FILE, "\t.set\tat\n"); \
2116 }
2117
2118 /* No mips port has ever used the profiler counter word, so don't emit it
2119 or the label for it. */
2120
2121 #define NO_PROFILE_COUNTERS 1
2122
2123 /* Define this macro if the code for function profiling should come
2124 before the function prologue. Normally, the profiling code comes
2125 after. */
2126
2127 /* #define PROFILE_BEFORE_PROLOGUE */
2128
2129 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2130 the stack pointer does not matter. The value is tested only in
2131 functions that have frame pointers.
2132 No definition is equivalent to always zero. */
2133
2134 #define EXIT_IGNORE_STACK 1
2135
2136 \f
2137 /* A C statement to output, on the stream FILE, assembler code for a
2138 block of data that contains the constant parts of a trampoline.
2139 This code should not include a label--the label is taken care of
2140 automatically. */
2141
2142 #define TRAMPOLINE_TEMPLATE(STREAM) \
2143 { \
2144 if (ptr_mode == DImode) \
2145 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2146 else \
2147 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2148 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2149 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2150 if (ptr_mode == DImode) \
2151 { \
2152 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2153 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2154 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2155 } \
2156 else \
2157 { \
2158 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2159 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2160 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2161 } \
2162 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2163 if (ptr_mode == DImode) \
2164 { \
2165 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2166 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2167 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2168 } \
2169 else \
2170 { \
2171 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2172 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2173 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2174 } \
2175 }
2176
2177 /* A C expression for the size in bytes of the trampoline, as an
2178 integer. */
2179
2180 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2181
2182 /* Alignment required for trampolines, in bits. */
2183
2184 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2185
2186 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2187 program and data caches. */
2188
2189 #ifndef CACHE_FLUSH_FUNC
2190 #define CACHE_FLUSH_FUNC "_flush_cache"
2191 #endif
2192
2193 /* A C statement to initialize the variable parts of a trampoline.
2194 ADDR is an RTX for the address of the trampoline; FNADDR is an
2195 RTX for the address of the nested function; STATIC_CHAIN is an
2196 RTX for the static chain value that should be passed to the
2197 function when it is called. */
2198
2199 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2200 { \
2201 rtx func_addr, chain_addr, end_addr; \
2202 \
2203 func_addr = plus_constant (ADDR, 32); \
2204 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2205 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2206 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2207 end_addr = gen_reg_rtx (Pmode); \
2208 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2209 GEN_INT (TRAMPOLINE_SIZE))); \
2210 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2211 }
2212 \f
2213 /* Addressing modes, and classification of registers for them. */
2214
2215 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2216 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2217 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2218
2219 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2220 and check its validity for a certain class.
2221 We have two alternate definitions for each of them.
2222 The usual definition accepts all pseudo regs; the other rejects them all.
2223 The symbol REG_OK_STRICT causes the latter definition to be used.
2224
2225 Most source files want to accept pseudo regs in the hope that
2226 they will get allocated to the class that the insn wants them to be in.
2227 Some source files that are used after register allocation
2228 need to be strict. */
2229
2230 #ifndef REG_OK_STRICT
2231 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2232 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2233 #else
2234 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2235 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2236 #endif
2237
2238 #define REG_OK_FOR_INDEX_P(X) 0
2239
2240 \f
2241 /* Maximum number of registers that can appear in a valid memory address. */
2242
2243 #define MAX_REGS_PER_ADDRESS 1
2244
2245 #ifdef REG_OK_STRICT
2246 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2247 { \
2248 if (mips_legitimate_address_p (MODE, X, 1)) \
2249 goto ADDR; \
2250 }
2251 #else
2252 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2253 { \
2254 if (mips_legitimate_address_p (MODE, X, 0)) \
2255 goto ADDR; \
2256 }
2257 #endif
2258
2259 /* Check for constness inline but use mips_legitimate_address_p
2260 to check whether a constant really is an address. */
2261
2262 #define CONSTANT_ADDRESS_P(X) \
2263 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2264
2265 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2266
2267 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2268 do { \
2269 if (mips_legitimize_address (&(X), MODE)) \
2270 goto WIN; \
2271 } while (0)
2272
2273
2274 /* A C statement or compound statement with a conditional `goto
2275 LABEL;' executed if memory address X (an RTX) can have different
2276 meanings depending on the machine mode of the memory reference it
2277 is used for.
2278
2279 Autoincrement and autodecrement addresses typically have
2280 mode-dependent effects because the amount of the increment or
2281 decrement is the size of the operand being addressed. Some
2282 machines have other mode-dependent addresses. Many RISC machines
2283 have no mode-dependent addresses.
2284
2285 You may assume that ADDR is a valid address for the machine. */
2286
2287 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2288
2289 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2290 'the start of the function that this code is output in'. */
2291
2292 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2293 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2294 asm_fprintf ((FILE), "%U%s", \
2295 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2296 else \
2297 asm_fprintf ((FILE), "%U%s", (NAME))
2298 \f
2299 /* Flag to mark a function decl symbol that requires a long call. */
2300 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2301 #define SYMBOL_REF_LONG_CALL_P(X) \
2302 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2303
2304 /* True if we're generating a form of MIPS16 code in which jump tables
2305 are stored in the text section and encoded as 16-bit PC-relative
2306 offsets. This is only possible when general text loads are allowed,
2307 since the table access itself will be an "lh" instruction. */
2308 /* ??? 16-bit offsets can overflow in large functions. */
2309 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2310
2311 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2312
2313 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2314
2315 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2316
2317 /* Define this as 1 if `char' should by default be signed; else as 0. */
2318 #ifndef DEFAULT_SIGNED_CHAR
2319 #define DEFAULT_SIGNED_CHAR 1
2320 #endif
2321
2322 /* Max number of bytes we can move from memory to memory
2323 in one reasonably fast instruction. */
2324 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2325 #define MAX_MOVE_MAX 8
2326
2327 /* Define this macro as a C expression which is nonzero if
2328 accessing less than a word of memory (i.e. a `char' or a
2329 `short') is no faster than accessing a word of memory, i.e., if
2330 such access require more than one instruction or if there is no
2331 difference in cost between byte and (aligned) word loads.
2332
2333 On RISC machines, it tends to generate better code to define
2334 this as 1, since it avoids making a QI or HI mode register.
2335
2336 But, generating word accesses for -mips16 is generally bad as shifts
2337 (often extended) would be needed for byte accesses. */
2338 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2339
2340 /* Define this to be nonzero if shift instructions ignore all but the low-order
2341 few bits. */
2342 #define SHIFT_COUNT_TRUNCATED 1
2343
2344 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2345 is done just by pretending it is already truncated. */
2346 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2347 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2348
2349
2350 /* Specify the machine mode that pointers have.
2351 After generation of rtl, the compiler makes no further distinction
2352 between pointers and any other objects of this machine mode. */
2353
2354 #ifndef Pmode
2355 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2356 #endif
2357
2358 /* Give call MEMs SImode since it is the "most permissive" mode
2359 for both 32-bit and 64-bit targets. */
2360
2361 #define FUNCTION_MODE SImode
2362
2363 \f
2364 /* The cost of loading values from the constant pool. It should be
2365 larger than the cost of any constant we want to synthesize in-line. */
2366
2367 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2368
2369 /* A C expression for the cost of moving data from a register in
2370 class FROM to one in class TO. The classes are expressed using
2371 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2372 the default; other values are interpreted relative to that.
2373
2374 It is not required that the cost always equal 2 when FROM is the
2375 same as TO; on some machines it is expensive to move between
2376 registers if they are not general registers.
2377
2378 If reload sees an insn consisting of a single `set' between two
2379 hard registers, and if `REGISTER_MOVE_COST' applied to their
2380 classes returns a value of 2, reload does not check to ensure
2381 that the constraints of the insn are met. Setting a cost of
2382 other than 2 will allow reload to verify that the constraints are
2383 met. You should do this if the `movM' pattern's constraints do
2384 not allow such copying. */
2385
2386 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2387 mips_register_move_cost (MODE, FROM, TO)
2388
2389 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2390 (mips_cost->memory_latency \
2391 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2392
2393 /* Define if copies to/from condition code registers should be avoided.
2394
2395 This is needed for the MIPS because reload_outcc is not complete;
2396 it needs to handle cases where the source is a general or another
2397 condition code register. */
2398 #define AVOID_CCMODE_COPIES
2399
2400 /* A C expression for the cost of a branch instruction. A value of
2401 1 is the default; other values are interpreted relative to that. */
2402
2403 #define BRANCH_COST mips_branch_cost
2404 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2405
2406 /* If defined, modifies the length assigned to instruction INSN as a
2407 function of the context in which it is used. LENGTH is an lvalue
2408 that contains the initially computed length of the insn and should
2409 be updated with the correct length of the insn. */
2410 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2411 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2412
2413 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2414 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2415 its operands. */
2416 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2417 "%*" OPCODE "%?\t" OPERANDS "%/"
2418
2419 /* Return the asm template for a call. INSN is the instruction's mnemonic
2420 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2421 of the target.
2422
2423 When generating GOT code without explicit relocation operators,
2424 all calls should use assembly macros. Otherwise, all indirect
2425 calls should use "jr" or "jalr"; we will arrange to restore $gp
2426 afterwards if necessary. Finally, we can only generate direct
2427 calls for -mabicalls by temporarily switching to non-PIC mode. */
2428 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2429 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2430 ? "%*" INSN "\t%" #OPNO "%/" \
2431 : REG_P (OPERANDS[OPNO]) \
2432 ? "%*" INSN "r\t%" #OPNO "%/" \
2433 : TARGET_ABICALLS \
2434 ? (".option\tpic0\n\t" \
2435 "%*" INSN "\t%" #OPNO "%/\n\t" \
2436 ".option\tpic2") \
2437 : "%*" INSN "\t%" #OPNO "%/")
2438 \f
2439 /* Control the assembler format that we output. */
2440
2441 /* Output to assembler file text saying following lines
2442 may contain character constants, extra white space, comments, etc. */
2443
2444 #ifndef ASM_APP_ON
2445 #define ASM_APP_ON " #APP\n"
2446 #endif
2447
2448 /* Output to assembler file text saying following lines
2449 no longer contain unusual constructs. */
2450
2451 #ifndef ASM_APP_OFF
2452 #define ASM_APP_OFF " #NO_APP\n"
2453 #endif
2454
2455 #define REGISTER_NAMES \
2456 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2457 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2458 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2459 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2460 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2461 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2462 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2463 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2464 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2465 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2466 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2467 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2468 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2469 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2470 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2471 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2472 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2473 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2474 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2475 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2476 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2477 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2478 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2479 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2480
2481 /* List the "software" names for each register. Also list the numerical
2482 names for $fp and $sp. */
2483
2484 #define ADDITIONAL_REGISTER_NAMES \
2485 { \
2486 { "$29", 29 + GP_REG_FIRST }, \
2487 { "$30", 30 + GP_REG_FIRST }, \
2488 { "at", 1 + GP_REG_FIRST }, \
2489 { "v0", 2 + GP_REG_FIRST }, \
2490 { "v1", 3 + GP_REG_FIRST }, \
2491 { "a0", 4 + GP_REG_FIRST }, \
2492 { "a1", 5 + GP_REG_FIRST }, \
2493 { "a2", 6 + GP_REG_FIRST }, \
2494 { "a3", 7 + GP_REG_FIRST }, \
2495 { "t0", 8 + GP_REG_FIRST }, \
2496 { "t1", 9 + GP_REG_FIRST }, \
2497 { "t2", 10 + GP_REG_FIRST }, \
2498 { "t3", 11 + GP_REG_FIRST }, \
2499 { "t4", 12 + GP_REG_FIRST }, \
2500 { "t5", 13 + GP_REG_FIRST }, \
2501 { "t6", 14 + GP_REG_FIRST }, \
2502 { "t7", 15 + GP_REG_FIRST }, \
2503 { "s0", 16 + GP_REG_FIRST }, \
2504 { "s1", 17 + GP_REG_FIRST }, \
2505 { "s2", 18 + GP_REG_FIRST }, \
2506 { "s3", 19 + GP_REG_FIRST }, \
2507 { "s4", 20 + GP_REG_FIRST }, \
2508 { "s5", 21 + GP_REG_FIRST }, \
2509 { "s6", 22 + GP_REG_FIRST }, \
2510 { "s7", 23 + GP_REG_FIRST }, \
2511 { "t8", 24 + GP_REG_FIRST }, \
2512 { "t9", 25 + GP_REG_FIRST }, \
2513 { "k0", 26 + GP_REG_FIRST }, \
2514 { "k1", 27 + GP_REG_FIRST }, \
2515 { "gp", 28 + GP_REG_FIRST }, \
2516 { "sp", 29 + GP_REG_FIRST }, \
2517 { "fp", 30 + GP_REG_FIRST }, \
2518 { "ra", 31 + GP_REG_FIRST }, \
2519 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2520 }
2521
2522 /* This is meant to be redefined in the host dependent files. It is a
2523 set of alternative names and regnums for mips coprocessors. */
2524
2525 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2526
2527 /* A C compound statement to output to stdio stream STREAM the
2528 assembler syntax for an instruction operand X. X is an RTL
2529 expression.
2530
2531 CODE is a value that can be used to specify one of several ways
2532 of printing the operand. It is used when identical operands
2533 must be printed differently depending on the context. CODE
2534 comes from the `%' specification that was used to request
2535 printing of the operand. If the specification was just `%DIGIT'
2536 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2537 is the ASCII code for LTR.
2538
2539 If X is a register, this macro should print the register's name.
2540 The names can be found in an array `reg_names' whose type is
2541 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2542
2543 When the machine description has a specification `%PUNCT' (a `%'
2544 followed by a punctuation character), this macro is called with
2545 a null pointer for X and the punctuation character for CODE.
2546
2547 See mips.c for the MIPS specific codes. */
2548
2549 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2550
2551 /* A C expression which evaluates to true if CODE is a valid
2552 punctuation character for use in the `PRINT_OPERAND' macro. If
2553 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2554 punctuation characters (except for the standard one, `%') are
2555 used in this way. */
2556
2557 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2558
2559 /* A C compound statement to output to stdio stream STREAM the
2560 assembler syntax for an instruction operand that is a memory
2561 reference whose address is ADDR. ADDR is an RTL expression. */
2562
2563 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2564
2565
2566 /* A C statement, to be executed after all slot-filler instructions
2567 have been output. If necessary, call `dbr_sequence_length' to
2568 determine the number of slots filled in a sequence (zero if not
2569 currently outputting a sequence), to decide how many no-ops to
2570 output, or whatever.
2571
2572 Don't define this macro if it has nothing to do, but it is
2573 helpful in reading assembly output if the extent of the delay
2574 sequence is made explicit (e.g. with white space).
2575
2576 Note that output routines for instructions with delay slots must
2577 be prepared to deal with not being output as part of a sequence
2578 (i.e. when the scheduling pass is not run, or when no slot
2579 fillers could be found.) The variable `final_sequence' is null
2580 when not processing a sequence, otherwise it contains the
2581 `sequence' rtx being output. */
2582
2583 #define DBR_OUTPUT_SEQEND(STREAM) \
2584 do \
2585 { \
2586 if (set_nomacro > 0 && --set_nomacro == 0) \
2587 fputs ("\t.set\tmacro\n", STREAM); \
2588 \
2589 if (set_noreorder > 0 && --set_noreorder == 0) \
2590 fputs ("\t.set\treorder\n", STREAM); \
2591 \
2592 fputs ("\n", STREAM); \
2593 } \
2594 while (0)
2595
2596
2597 /* How to tell the debugger about changes of source files. */
2598 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2599 mips_output_filename (STREAM, NAME)
2600
2601 /* mips-tfile does not understand .stabd directives. */
2602 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2603 dbxout_begin_stabn_sline (LINE); \
2604 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2605 } while (0)
2606
2607 /* Use .loc directives for SDB line numbers. */
2608 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2609 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2610
2611 /* The MIPS implementation uses some labels for its own purpose. The
2612 following lists what labels are created, and are all formed by the
2613 pattern $L[a-z].*. The machine independent portion of GCC creates
2614 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2615
2616 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2617 $Lb[0-9]+ Begin blocks for MIPS debug support
2618 $Lc[0-9]+ Label for use in s<xx> operation.
2619 $Le[0-9]+ End blocks for MIPS debug support */
2620
2621 #undef ASM_DECLARE_OBJECT_NAME
2622 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2623 mips_declare_object (STREAM, NAME, "", ":\n")
2624
2625 /* Globalizing directive for a label. */
2626 #define GLOBAL_ASM_OP "\t.globl\t"
2627
2628 /* This says how to define a global common symbol. */
2629
2630 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2631
2632 /* This says how to define a local common symbol (i.e., not visible to
2633 linker). */
2634
2635 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2636 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2637 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2638 #endif
2639
2640 /* This says how to output an external. It would be possible not to
2641 output anything and let undefined symbol become external. However
2642 the assembler uses length information on externals to allocate in
2643 data/sdata bss/sbss, thereby saving exec time. */
2644
2645 #undef ASM_OUTPUT_EXTERNAL
2646 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2647 mips_output_external(STREAM,DECL,NAME)
2648
2649 /* This is how to declare a function name. The actual work of
2650 emitting the label is moved to function_prologue, so that we can
2651 get the line number correctly emitted before the .ent directive,
2652 and after any .file directives. Define as empty so that the function
2653 is not declared before the .ent directive elsewhere. */
2654
2655 #undef ASM_DECLARE_FUNCTION_NAME
2656 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2657
2658 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2659 #define FUNCTION_NAME_ALREADY_DECLARED 0
2660 #endif
2661
2662 /* This is how to store into the string LABEL
2663 the symbol_ref name of an internal numbered label where
2664 PREFIX is the class of label and NUM is the number within the class.
2665 This is suitable for output with `assemble_name'. */
2666
2667 #undef ASM_GENERATE_INTERNAL_LABEL
2668 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2669 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2670
2671 /* This is how to output an element of a case-vector that is absolute. */
2672
2673 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2674 fprintf (STREAM, "\t%s\t%sL%d\n", \
2675 ptr_mode == DImode ? ".dword" : ".word", \
2676 LOCAL_LABEL_PREFIX, \
2677 VALUE)
2678
2679 /* This is how to output an element of a case-vector. We can make the
2680 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2681 is supported. */
2682
2683 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2684 do { \
2685 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2686 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2687 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2688 else if (TARGET_GPWORD) \
2689 fprintf (STREAM, "\t%s\t%sL%d\n", \
2690 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2691 LOCAL_LABEL_PREFIX, VALUE); \
2692 else if (TARGET_RTP_PIC) \
2693 { \
2694 /* Make the entry relative to the start of the function. */ \
2695 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2696 fprintf (STREAM, "\t%s\t%sL%d-", \
2697 Pmode == DImode ? ".dword" : ".word", \
2698 LOCAL_LABEL_PREFIX, VALUE); \
2699 assemble_name (STREAM, XSTR (fnsym, 0)); \
2700 fprintf (STREAM, "\n"); \
2701 } \
2702 else \
2703 fprintf (STREAM, "\t%s\t%sL%d\n", \
2704 ptr_mode == DImode ? ".dword" : ".word", \
2705 LOCAL_LABEL_PREFIX, VALUE); \
2706 } while (0)
2707
2708 /* This is how to output an assembler line
2709 that says to advance the location counter
2710 to a multiple of 2**LOG bytes. */
2711
2712 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2713 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2714
2715 /* This is how to output an assembler line to advance the location
2716 counter by SIZE bytes. */
2717
2718 #undef ASM_OUTPUT_SKIP
2719 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2720 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2721
2722 /* This is how to output a string. */
2723 #undef ASM_OUTPUT_ASCII
2724 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2725 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2726
2727 /* Output #ident as a in the read-only data section. */
2728 #undef ASM_OUTPUT_IDENT
2729 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2730 { \
2731 const char *p = STRING; \
2732 int size = strlen (p) + 1; \
2733 switch_to_section (readonly_data_section); \
2734 assemble_string (p, size); \
2735 }
2736 \f
2737 /* Default to -G 8 */
2738 #ifndef MIPS_DEFAULT_GVALUE
2739 #define MIPS_DEFAULT_GVALUE 8
2740 #endif
2741
2742 /* Define the strings to put out for each section in the object file. */
2743 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2744 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2745
2746 #undef READONLY_DATA_SECTION_ASM_OP
2747 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2748 \f
2749 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2750 do \
2751 { \
2752 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2753 TARGET_64BIT ? "dsubu" : "subu", \
2754 reg_names[STACK_POINTER_REGNUM], \
2755 reg_names[STACK_POINTER_REGNUM], \
2756 TARGET_64BIT ? "sd" : "sw", \
2757 reg_names[REGNO], \
2758 reg_names[STACK_POINTER_REGNUM]); \
2759 } \
2760 while (0)
2761
2762 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2763 do \
2764 { \
2765 if (! set_noreorder) \
2766 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2767 \
2768 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2769 TARGET_64BIT ? "ld" : "lw", \
2770 reg_names[REGNO], \
2771 reg_names[STACK_POINTER_REGNUM], \
2772 TARGET_64BIT ? "daddu" : "addu", \
2773 reg_names[STACK_POINTER_REGNUM], \
2774 reg_names[STACK_POINTER_REGNUM]); \
2775 \
2776 if (! set_noreorder) \
2777 fprintf (STREAM, "\t.set\treorder\n"); \
2778 } \
2779 while (0)
2780
2781 /* How to start an assembler comment.
2782 The leading space is important (the mips native assembler requires it). */
2783 #ifndef ASM_COMMENT_START
2784 #define ASM_COMMENT_START " #"
2785 #endif
2786 \f
2787 /* Default definitions for size_t and ptrdiff_t. We must override the
2788 definitions from ../svr4.h on mips-*-linux-gnu. */
2789
2790 #undef SIZE_TYPE
2791 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2792
2793 #undef PTRDIFF_TYPE
2794 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2795
2796 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2797 values were determined experimentally by benchmarking with CSiBE.
2798 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2799 for o32 where we have to restore $gp afterwards as well as make an
2800 indirect call), but in practice, bumping this up higher for
2801 TARGET_ABICALLS doesn't make much difference to code size. */
2802
2803 #define MIPS_CALL_RATIO 8
2804
2805 /* Define MOVE_RATIO to encourage use of movmemsi when enabled,
2806 since it should always generate code at least as good as
2807 move_by_pieces(). But when inline movmemsi pattern is disabled
2808 (i.e., with -mips16 or -mmemcpy), instead use a value approximating
2809 the length of a memcpy call sequence, so that move_by_pieces will
2810 generate inline code if it is shorter than a function call.
2811 Since move_by_pieces_ninsns() counts memory-to-memory moves, but
2812 we'll have to generate a load/store pair for each, halve the value of
2813 MIPS_CALL_RATIO to take that into account.
2814 The default value for MOVE_RATIO when HAVE_movmemsi is true is 2.
2815 There is no point to setting it to less than this to try to disable
2816 move_by_pieces entirely, because that also disables some desirable
2817 tree-level optimizations, specifically related to optimizing a
2818 one-byte string copy into a simple move byte operation. */
2819
2820 #define MOVE_RATIO \
2821 ((TARGET_MIPS16 || TARGET_MEMCPY) ? MIPS_CALL_RATIO / 2 : 2)
2822
2823 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2824 of the length of a memset call, but use the default otherwise. */
2825
2826 #define CLEAR_RATIO \
2827 (optimize_size ? MIPS_CALL_RATIO : 15)
2828
2829 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2830 optimizing for size adjust the ratio to account for the overhead of
2831 loading the constant and replicating it across the word. */
2832
2833 #define SET_RATIO \
2834 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2835
2836 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2837 in that case each word takes 3 insns (lui, ori, sw), or more in
2838 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2839 and let the move_by_pieces code copy the string from read-only
2840 memory. In the future, this could be tuned further for multi-issue
2841 CPUs that can issue stores down one pipe and arithmetic instructions
2842 down another; in that case, the lui/ori/sw combination would be a
2843 win for long enough strings. */
2844
2845 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2846 \f
2847 #ifndef __mips16
2848 /* Since the bits of the _init and _fini function is spread across
2849 many object files, each potentially with its own GP, we must assume
2850 we need to load our GP. We don't preserve $gp or $ra, since each
2851 init/fini chunk is supposed to initialize $gp, and crti/crtn
2852 already take care of preserving $ra and, when appropriate, $gp. */
2853 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2854 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2855 asm (SECTION_OP "\n\
2856 .set noreorder\n\
2857 bal 1f\n\
2858 nop\n\
2859 1: .cpload $31\n\
2860 .set reorder\n\
2861 jal " USER_LABEL_PREFIX #FUNC "\n\
2862 " TEXT_SECTION_ASM_OP);
2863 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2864 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2865 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2866 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2867 asm (SECTION_OP "\n\
2868 .set noreorder\n\
2869 bal 1f\n\
2870 nop\n\
2871 1: .set reorder\n\
2872 .cpsetup $31, $2, 1b\n\
2873 jal " USER_LABEL_PREFIX #FUNC "\n\
2874 " TEXT_SECTION_ASM_OP);
2875 #endif
2876 #endif
2877
2878 #ifndef HAVE_AS_TLS
2879 #define HAVE_AS_TLS 0
2880 #endif
2881
2882 /* Return an asm string that atomically:
2883
2884 - Compares memory reference %1 to register %2 and, if they are
2885 equal, changes %1 to %3.
2886
2887 - Sets register %0 to the old value of memory reference %1.
2888
2889 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
2890 and OP is the instruction that should be used to load %3 into a
2891 register. */
2892 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
2893 "%(%<%[sync\n" \
2894 "1:\tll" SUFFIX "\t%0,%1\n" \
2895 "\tbne\t%0,%2,2f\n" \
2896 "\t" OP "\t%@,%3\n" \
2897 "\tsc" SUFFIX "\t%@,%1\n" \
2898 "\tbeq\t%@,%.,1b\n" \
2899 "\tnop\n" \
2900 "2:%]%>%)"
2901
2902 /* Return an asm string that atomically:
2903
2904 - Sets memory reference %0 to %0 INSN %1.
2905
2906 SUFFIX is the suffix that should be added to "ll" and "sc"
2907 instructions. */
2908 #define MIPS_SYNC_OP(SUFFIX, INSN) \
2909 "%(%<%[sync\n" \
2910 "1:\tll" SUFFIX "\t%@,%0\n" \
2911 "\t" INSN "\t%@,%@,%1\n" \
2912 "\tsc" SUFFIX "\t%@,%0\n" \
2913 "\tbeq\t%@,%.,1b\n" \
2914 "\tnop%]%>%)"
2915
2916 /* Return an asm string that atomically:
2917
2918 - Sets memory reference %1 to %1 INSN %2.
2919
2920 - Sets register %0 to the old value of memory reference %1.
2921
2922 SUFFIX is the suffix that should be added to "ll" and "sc"
2923 instructions. */
2924 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
2925 "%(%<%[sync\n" \
2926 "1:\tll" SUFFIX "\t%0,%1\n" \
2927 "\t" INSN "\t%@,%0,%2\n" \
2928 "\tsc" SUFFIX "\t%@,%1\n" \
2929 "\tbeq\t%@,%.,1b\n" \
2930 "\tnop%]%>%)"
2931
2932 /* Return an asm string that atomically:
2933
2934 - Sets memory reference %1 to %1 INSN %2.
2935
2936 - Sets register %0 to the new value of memory reference %1.
2937
2938 SUFFIX is the suffix that should be added to "ll" and "sc"
2939 instructions. */
2940 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
2941 "%(%<%[sync\n" \
2942 "1:\tll" SUFFIX "\t%0,%1\n" \
2943 "\t" INSN "\t%@,%0,%2\n" \
2944 "\tsc" SUFFIX "\t%@,%1\n" \
2945 "\tbeq\t%@,%.,1b\n" \
2946 "\t" INSN "\t%0,%0,%2%]%>%)"
2947
2948 /* Return an asm string that atomically:
2949
2950 - Sets memory reference %0 to ~%0 AND %1.
2951
2952 SUFFIX is the suffix that should be added to "ll" and "sc"
2953 instructions. INSN is the and instruction needed to and a register
2954 with %2. */
2955 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
2956 "%(%<%[sync\n" \
2957 "1:\tll" SUFFIX "\t%@,%0\n" \
2958 "\tnor\t%@,%@,%.\n" \
2959 "\t" INSN "\t%@,%@,%1\n" \
2960 "\tsc" SUFFIX "\t%@,%0\n" \
2961 "\tbeq\t%@,%.,1b\n" \
2962 "\tnop%]%>%)"
2963
2964 /* Return an asm string that atomically:
2965
2966 - Sets memory reference %1 to ~%1 AND %2.
2967
2968 - Sets register %0 to the old value of memory reference %1.
2969
2970 SUFFIX is the suffix that should be added to "ll" and "sc"
2971 instructions. INSN is the and instruction needed to and a register
2972 with %2. */
2973 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
2974 "%(%<%[sync\n" \
2975 "1:\tll" SUFFIX "\t%0,%1\n" \
2976 "\tnor\t%@,%0,%.\n" \
2977 "\t" INSN "\t%@,%@,%2\n" \
2978 "\tsc" SUFFIX "\t%@,%1\n" \
2979 "\tbeq\t%@,%.,1b\n" \
2980 "\tnop%]%>%)"
2981
2982 /* Return an asm string that atomically:
2983
2984 - Sets memory reference %1 to ~%1 AND %2.
2985
2986 - Sets register %0 to the new value of memory reference %1.
2987
2988 SUFFIX is the suffix that should be added to "ll" and "sc"
2989 instructions. INSN is the and instruction needed to and a register
2990 with %2. */
2991 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
2992 "%(%<%[sync\n" \
2993 "1:\tll" SUFFIX "\t%0,%1\n" \
2994 "\tnor\t%0,%0,%.\n" \
2995 "\t" INSN "\t%@,%0,%2\n" \
2996 "\tsc" SUFFIX "\t%@,%1\n" \
2997 "\tbeq\t%@,%.,1b\n" \
2998 "\t" INSN "\t%0,%0,%2%]%>%)"
2999
3000 /* Return an asm string that atomically:
3001
3002 - Sets memory reference %1 to %2.
3003
3004 - Sets register %0 to the old value of memory reference %1.
3005
3006 SUFFIX is the suffix that should be added to "ll" and "sc"
3007 instructions. OP is the and instruction that should be used to
3008 load %2 into a register. */
3009 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3010 "%(%<%[\n" \
3011 "1:\tll" SUFFIX "\t%0,%1\n" \
3012 "\t" OP "\t%@,%2\n" \
3013 "\tsc" SUFFIX "\t%@,%1\n" \
3014 "\tbeq\t%@,%.,1b\n" \
3015 "\tnop\n" \
3016 "\tsync%]%>%)"
3017
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