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Handle Octeon 3 not supporting MIPS paired-single instructions.
[official-gcc.git] / gcc / config / mips / mips.h
blob803ab98e760a61c268f026ac05982bd60e0f8ddb
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target, typically because the branches are always predicted
50 taken and so incur a large overhead when not taken.
51
52 PTF_AVOID_IMADD
53 Set if it is usually not profitable to use the integer MADD or MSUB
54 instructions because of the overhead of getting the result out of
55 the HI/LO registers. */
56
57 #define PTF_AVOID_BRANCHLIKELY 0x1
58 #define PTF_AVOID_IMADD 0x2
59
60 /* Information about one recognized processor. Defined here for the
61 benefit of TARGET_CPU_CPP_BUILTINS. */
62 struct mips_cpu_info {
63 /* The 'canonical' name of the processor as far as GCC is concerned.
64 It's typically a manufacturer's prefix followed by a numerical
65 designation. It should be lowercase. */
66 const char *name;
67
68 /* The internal processor number that most closely matches this
69 entry. Several processors can have the same value, if there's no
70 difference between them from GCC's point of view. */
71 enum processor cpu;
72
73 /* The ISA level that the processor implements. */
74 int isa;
75
76 /* A mask of PTF_* values. */
77 unsigned int tune_flags;
78 };
79
80 #include "config/mips/mips-opts.h"
81
82 /* Macros to silence warnings about numbers being signed in traditional
83 C and unsigned in ISO C when compiled on 32-bit hosts. */
84
85 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
86 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
87 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
88
89 \f
90 /* Run-time compilation parameters selecting different hardware subsets. */
91
92 /* True if we are generating position-independent VxWorks RTP code. */
93 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
94
95 /* Compact branches must not be used if the user either selects the
96 'never' policy or the 'optimal' policy on a core that lacks
97 compact branch instructions. */
98 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \
99 || (mips_cb == MIPS_CB_OPTIMAL \
100 && !ISA_HAS_COMPACT_BRANCHES))
101
102 /* Compact branches may be used if the user either selects the
103 'always' policy or the 'optimal' policy on a core that supports
104 compact branch instructions. */
105 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \
106 || (mips_cb == MIPS_CB_OPTIMAL \
107 && ISA_HAS_COMPACT_BRANCHES))
108
109 /* Compact branches must always be generated if the user selects
110 the 'always' policy or the 'optimal' policy om a core that
111 lacks delay slot branch instructions. */
112 #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \
113 || (mips_cb == MIPS_CB_OPTIMAL \
114 && !ISA_HAS_DELAY_SLOTS))
115
116 /* Special handling for JRC that exists in microMIPSR3 as well as R6
117 ISAs with full compact branch support. */
118 #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \
119 || TARGET_MICROMIPS) \
120 && mips_cb != MIPS_CB_NEVER)
121
122 /* True if the output file is marked as ".abicalls; .option pic0"
123 (-call_nonpic). */
124 #define TARGET_ABICALLS_PIC0 \
125 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
126
127 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
128 #define TARGET_ABICALLS_PIC2 \
129 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
130
131 /* True if the call patterns should be split into a jalr followed by
132 an instruction to restore $gp. It is only safe to split the load
133 from the call when every use of $gp is explicit.
134
135 See mips_must_initialize_gp_p for details about how we manage the
136 global pointer. */
137
138 #define TARGET_SPLIT_CALLS \
139 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
140
141 /* True if we're generating a form of -mabicalls in which we can use
142 operators like %hi and %lo to refer to locally-binding symbols.
143 We can only do this for -mno-shared, and only then if we can use
144 relocation operations instead of assembly macros. It isn't really
145 worth using absolute sequences for 64-bit symbols because GOT
146 accesses are so much shorter. */
147
148 #define TARGET_ABSOLUTE_ABICALLS \
149 (TARGET_ABICALLS \
150 && !TARGET_SHARED \
151 && TARGET_EXPLICIT_RELOCS \
152 && !ABI_HAS_64BIT_SYMBOLS)
153
154 /* True if we can optimize sibling calls. For simplicity, we only
155 handle cases in which call_insn_operand will reject invalid
156 sibcall addresses. There are two cases in which this isn't true:
157
158 - TARGET_MIPS16. call_insn_operand accepts constant addresses
159 but there is no direct jump instruction. It isn't worth
160 using sibling calls in this case anyway; they would usually
161 be longer than normal calls.
162
163 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
164 accepts global constants, but all sibcalls must be indirect. */
165 #define TARGET_SIBCALLS \
166 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
167
168 /* True if we need to use a global offset table to access some symbols. */
169 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
170
171 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
172 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
173
174 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
175 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
176
177 /* True if we should use .cprestore to store to the cprestore slot.
178
179 We continue to use .cprestore for explicit-reloc code so that JALs
180 inside inline asms will work correctly. */
181 #define TARGET_CPRESTORE_DIRECTIVE \
182 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
183
184 /* True if we can use the J and JAL instructions. */
185 #define TARGET_ABSOLUTE_JUMPS \
186 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
187
188 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
189 This is true for both the PIC and non-PIC VxWorks RTP modes. */
190 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
191
192 /* True if .gpword or .gpdword should be used for switch tables. */
193 #define TARGET_GPWORD \
194 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
195
196 /* True if the output must have a writable .eh_frame.
197 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
198 #ifdef HAVE_LD_PERSONALITY_RELAXATION
199 #define TARGET_WRITABLE_EH_FRAME 0
200 #else
201 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
202 #endif
203
204 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
205 #ifdef HAVE_AS_DSPR1_MULT
206 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
207 #else
208 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
209 #endif
210
211 /* ISA has LSA available. */
212 #define ISA_HAS_LSA (mips_isa_rev >= 6)
213
214 /* ISA has DLSA available. */
215 #define ISA_HAS_DLSA (TARGET_64BIT && mips_isa_rev >= 6)
216
217 /* The ISA compression flags that are currently in effect. */
218 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
219
220 /* Generate mips16 code */
221 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
222 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
223 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
224 /* Generate mips16e register save/restore sequences. */
225 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
226
227 /* True if we're generating a form of MIPS16 code in which general
228 text loads are allowed. */
229 #define TARGET_MIPS16_TEXT_LOADS \
230 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
231
232 /* True if we're generating a form of MIPS16 code in which PC-relative
233 loads are allowed. */
234 #define TARGET_MIPS16_PCREL_LOADS \
235 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
236
237 /* Generic ISA defines. */
238 #define ISA_MIPS1 (mips_isa == 1)
239 #define ISA_MIPS2 (mips_isa == 2)
240 #define ISA_MIPS3 (mips_isa == 3)
241 #define ISA_MIPS4 (mips_isa == 4)
242 #define ISA_MIPS32 (mips_isa == 32)
243 #define ISA_MIPS32R2 (mips_isa == 33)
244 #define ISA_MIPS32R3 (mips_isa == 34)
245 #define ISA_MIPS32R5 (mips_isa == 36)
246 #define ISA_MIPS32R6 (mips_isa == 37)
247 #define ISA_MIPS64 (mips_isa == 64)
248 #define ISA_MIPS64R2 (mips_isa == 65)
249 #define ISA_MIPS64R3 (mips_isa == 66)
250 #define ISA_MIPS64R5 (mips_isa == 68)
251 #define ISA_MIPS64R6 (mips_isa == 69)
252
253 /* Architecture target defines. */
254 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
255 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
256 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
257 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
258 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
259 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
260 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
261 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
262 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
263 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
264 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
265 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
266 #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000)
267 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
268 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
269 || mips_arch == PROCESSOR_OCTEON2 \
270 || mips_arch == PROCESSOR_OCTEON3)
271 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
272 || mips_arch == PROCESSOR_OCTEON3)
273 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
274 || mips_arch == PROCESSOR_SB1A)
275 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
276 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
277
278 /* Scheduling target defines. */
279 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
280 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
281 || mips_tune == PROCESSOR_24KF2_1 \
282 || mips_tune == PROCESSOR_24KF1_1)
283 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
284 || mips_tune == PROCESSOR_74KF2_1 \
285 || mips_tune == PROCESSOR_74KF1_1 \
286 || mips_tune == PROCESSOR_74KF3_2)
287 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
288 || mips_tune == PROCESSOR_LOONGSON_2F)
289 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
290 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
291 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
292 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
293 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
294 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
295 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
296 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
297 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
298 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
299 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
300 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
301 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
302 || mips_tune == PROCESSOR_OCTEON2 \
303 || mips_tune == PROCESSOR_OCTEON3)
304 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
305 || mips_tune == PROCESSOR_SB1A)
306 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
307 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
308
309 /* Whether vector modes and intrinsics for ST Microelectronics
310 Loongson-2E/2F processors should be enabled. In o32 pairs of
311 floating-point registers provide 64-bit values. */
312 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
313 && (TARGET_LOONGSON_2EF \
314 || TARGET_LOONGSON_3A))
315
316 /* True if the pre-reload scheduler should try to create chains of
317 multiply-add or multiply-subtract instructions. For example,
318 suppose we have:
319
320 t1 = a * b
321 t2 = t1 + c * d
322 t3 = e * f
323 t4 = t3 - g * h
324
325 t1 will have a higher priority than t2 and t3 will have a higher
326 priority than t4. However, before reload, there is no dependence
327 between t1 and t3, and they can often have similar priorities.
328 The scheduler will then tend to prefer:
329
330 t1 = a * b
331 t3 = e * f
332 t2 = t1 + c * d
333 t4 = t3 - g * h
334
335 which stops us from making full use of macc/madd-style instructions.
336 This sort of situation occurs frequently in Fourier transforms and
337 in unrolled loops.
338
339 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
340 queue so that chained multiply-add and multiply-subtract instructions
341 appear ahead of any other instruction that is likely to clobber lo.
342 In the example above, if t2 and t3 become ready at the same time,
343 the code ensures that t2 is scheduled first.
344
345 Multiply-accumulate instructions are a bigger win for some targets
346 than others, so this macro is defined on an opt-in basis. */
347 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
348 || TUNE_MIPS4120 \
349 || TUNE_MIPS4130 \
350 || TUNE_24K \
351 || TUNE_P5600)
352
353 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
354 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
355
356 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
357 directly accessible, while the command-line options select
358 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
359 in use. */
360 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
361 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
362
363 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
364 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
365 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
366
367 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
368 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
369 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
370 && !TARGET_ODD_SPREG)
371
372 /* False if SC acts as a memory barrier with respect to itself,
373 otherwise a SYNC will be emitted after SC for atomic operations
374 that require ordering between the SC and following loads and
375 stores. It does not tell anything about ordering of loads and
376 stores prior to and following the SC, only about the SC itself and
377 those loads and stores follow it. */
378 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
379
380 /* Define preprocessor macros for the -march and -mtune options.
381 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
382 processor. If INFO's canonical name is "foo", define PREFIX to
383 be "foo", and define an additional macro PREFIX_FOO. */
384 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
385 do \
386 { \
387 char *macro, *p; \
388 \
389 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
390 for (p = macro; *p != 0; p++) \
391 if (*p == '+') \
392 *p = 'P'; \
393 else \
394 *p = TOUPPER (*p); \
395 \
396 builtin_define (macro); \
397 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
398 free (macro); \
399 } \
400 while (0)
401
402 /* Target CPU builtins. */
403 #define TARGET_CPU_CPP_BUILTINS() \
404 do \
405 { \
406 builtin_assert ("machine=mips"); \
407 builtin_assert ("cpu=mips"); \
408 builtin_define ("__mips__"); \
409 builtin_define ("_mips"); \
410 \
411 /* We do this here because __mips is defined below and so we \
412 can't use builtin_define_std. We don't ever want to define \
413 "mips" for VxWorks because some of the VxWorks headers \
414 construct include filenames from a root directory macro, \
415 an architecture macro and a filename, where the architecture \
416 macro expands to 'mips'. If we define 'mips' to 1, the \
417 architecture macro expands to 1 as well. */ \
418 if (!flag_iso && !TARGET_VXWORKS) \
419 builtin_define ("mips"); \
420 \
421 if (TARGET_64BIT) \
422 builtin_define ("__mips64"); \
423 \
424 /* Treat _R3000 and _R4000 like register-size \
425 defines, which is how they've historically \
426 been used. */ \
427 if (TARGET_64BIT) \
428 { \
429 builtin_define_std ("R4000"); \
430 builtin_define ("_R4000"); \
431 } \
432 else \
433 { \
434 builtin_define_std ("R3000"); \
435 builtin_define ("_R3000"); \
436 } \
437 \
438 if (TARGET_FLOAT64) \
439 builtin_define ("__mips_fpr=64"); \
440 else if (TARGET_FLOATXX) \
441 builtin_define ("__mips_fpr=0"); \
442 else \
443 builtin_define ("__mips_fpr=32"); \
444 \
445 if (mips_base_compression_flags & MASK_MIPS16) \
446 builtin_define ("__mips16"); \
447 \
448 if (TARGET_MIPS3D) \
449 builtin_define ("__mips3d"); \
450 \
451 if (TARGET_SMARTMIPS) \
452 builtin_define ("__mips_smartmips"); \
453 \
454 if (mips_base_compression_flags & MASK_MICROMIPS) \
455 builtin_define ("__mips_micromips"); \
456 \
457 if (TARGET_MCU) \
458 builtin_define ("__mips_mcu"); \
459 \
460 if (TARGET_EVA) \
461 builtin_define ("__mips_eva"); \
462 \
463 if (TARGET_DSP) \
464 { \
465 builtin_define ("__mips_dsp"); \
466 if (TARGET_DSPR2) \
467 { \
468 builtin_define ("__mips_dspr2"); \
469 builtin_define ("__mips_dsp_rev=2"); \
470 } \
471 else \
472 builtin_define ("__mips_dsp_rev=1"); \
473 } \
474 \
475 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
476 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
477 \
478 if (ISA_MIPS1) \
479 { \
480 builtin_define ("__mips=1"); \
481 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
482 } \
483 else if (ISA_MIPS2) \
484 { \
485 builtin_define ("__mips=2"); \
486 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
487 } \
488 else if (ISA_MIPS3) \
489 { \
490 builtin_define ("__mips=3"); \
491 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
492 } \
493 else if (ISA_MIPS4) \
494 { \
495 builtin_define ("__mips=4"); \
496 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
497 } \
498 else if (mips_isa >= 32 && mips_isa < 64) \
499 { \
500 builtin_define ("__mips=32"); \
501 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
502 } \
503 else if (mips_isa >= 64) \
504 { \
505 builtin_define ("__mips=64"); \
506 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
507 } \
508 if (mips_isa_rev > 0) \
509 builtin_define_with_int_value ("__mips_isa_rev", \
510 mips_isa_rev); \
511 \
512 switch (mips_abi) \
513 { \
514 case ABI_32: \
515 builtin_define ("_ABIO32=1"); \
516 builtin_define ("_MIPS_SIM=_ABIO32"); \
517 break; \
518 \
519 case ABI_N32: \
520 builtin_define ("_ABIN32=2"); \
521 builtin_define ("_MIPS_SIM=_ABIN32"); \
522 break; \
523 \
524 case ABI_64: \
525 builtin_define ("_ABI64=3"); \
526 builtin_define ("_MIPS_SIM=_ABI64"); \
527 break; \
528 \
529 case ABI_O64: \
530 builtin_define ("_ABIO64=4"); \
531 builtin_define ("_MIPS_SIM=_ABIO64"); \
532 break; \
533 } \
534 \
535 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
536 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
537 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
538 builtin_define_with_int_value ("_MIPS_FPSET", \
539 32 / MAX_FPRS_PER_FMT); \
540 builtin_define_with_int_value ("_MIPS_SPFPSET", \
541 TARGET_ODD_SPREG ? 32 : 16); \
542 \
543 /* These defines reflect the ABI in use, not whether the \
544 FPU is directly accessible. */ \
545 if (TARGET_NO_FLOAT) \
546 builtin_define ("__mips_no_float"); \
547 else if (TARGET_HARD_FLOAT_ABI) \
548 builtin_define ("__mips_hard_float"); \
549 else \
550 builtin_define ("__mips_soft_float"); \
551 \
552 if (TARGET_SINGLE_FLOAT) \
553 builtin_define ("__mips_single_float"); \
554 \
555 if (TARGET_PAIRED_SINGLE_FLOAT) \
556 builtin_define ("__mips_paired_single_float"); \
557 \
558 if (mips_abs == MIPS_IEEE_754_2008) \
559 builtin_define ("__mips_abs2008"); \
560 \
561 if (mips_nan == MIPS_IEEE_754_2008) \
562 builtin_define ("__mips_nan2008"); \
563 \
564 if (TARGET_BIG_ENDIAN) \
565 { \
566 builtin_define_std ("MIPSEB"); \
567 builtin_define ("_MIPSEB"); \
568 } \
569 else \
570 { \
571 builtin_define_std ("MIPSEL"); \
572 builtin_define ("_MIPSEL"); \
573 } \
574 \
575 /* Whether calls should go through $25. The separate __PIC__ \
576 macro indicates whether abicalls code might use a GOT. */ \
577 if (TARGET_ABICALLS) \
578 builtin_define ("__mips_abicalls"); \
579 \
580 /* Whether Loongson vector modes are enabled. */ \
581 if (TARGET_LOONGSON_VECTORS) \
582 builtin_define ("__mips_loongson_vector_rev"); \
583 \
584 /* Historical Octeon macro. */ \
585 if (TARGET_OCTEON) \
586 builtin_define ("__OCTEON__"); \
587 \
588 if (TARGET_SYNCI) \
589 builtin_define ("__mips_synci"); \
590 \
591 /* Macros dependent on the C dialect. */ \
592 if (preprocessing_asm_p ()) \
593 { \
594 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
595 builtin_define ("_LANGUAGE_ASSEMBLY"); \
596 } \
597 else if (c_dialect_cxx ()) \
598 { \
599 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
600 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
601 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
602 } \
603 else \
604 { \
605 builtin_define_std ("LANGUAGE_C"); \
606 builtin_define ("_LANGUAGE_C"); \
607 } \
608 if (c_dialect_objc ()) \
609 { \
610 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
611 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
612 /* Bizarre, but retained for backwards compatibility. */ \
613 builtin_define_std ("LANGUAGE_C"); \
614 builtin_define ("_LANGUAGE_C"); \
615 } \
616 \
617 if (mips_abi == ABI_EABI) \
618 builtin_define ("__mips_eabi"); \
619 \
620 if (TARGET_CACHE_BUILTIN) \
621 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
622 } \
623 while (0)
624
625 /* Default target_flags if no switches are specified */
626
627 #ifndef TARGET_DEFAULT
628 #define TARGET_DEFAULT 0
629 #endif
630
631 #ifndef TARGET_CPU_DEFAULT
632 #define TARGET_CPU_DEFAULT 0
633 #endif
634
635 #ifndef TARGET_ENDIAN_DEFAULT
636 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
637 #endif
638
639 #ifdef IN_LIBGCC2
640 #undef TARGET_64BIT
641 /* Make this compile time constant for libgcc2 */
642 #ifdef __mips64
643 #define TARGET_64BIT 1
644 #else
645 #define TARGET_64BIT 0
646 #endif
647 #endif /* IN_LIBGCC2 */
648
649 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
650 when compiled with hardware floating point. This is because MIPS16
651 code cannot save and restore the floating-point registers, which is
652 important if in a mixed MIPS16/non-MIPS16 environment. */
653
654 #ifdef IN_LIBGCC2
655 #if __mips_hard_float
656 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
657 #endif
658 #endif /* IN_LIBGCC2 */
659
660 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
661
662 #ifndef MULTILIB_ENDIAN_DEFAULT
663 #if TARGET_ENDIAN_DEFAULT == 0
664 #define MULTILIB_ENDIAN_DEFAULT "EL"
665 #else
666 #define MULTILIB_ENDIAN_DEFAULT "EB"
667 #endif
668 #endif
669
670 #ifndef MULTILIB_ISA_DEFAULT
671 #if MIPS_ISA_DEFAULT == 1
672 #define MULTILIB_ISA_DEFAULT "mips1"
673 #elif MIPS_ISA_DEFAULT == 2
674 #define MULTILIB_ISA_DEFAULT "mips2"
675 #elif MIPS_ISA_DEFAULT == 3
676 #define MULTILIB_ISA_DEFAULT "mips3"
677 #elif MIPS_ISA_DEFAULT == 4
678 #define MULTILIB_ISA_DEFAULT "mips4"
679 #elif MIPS_ISA_DEFAULT == 32
680 #define MULTILIB_ISA_DEFAULT "mips32"
681 #elif MIPS_ISA_DEFAULT == 33
682 #define MULTILIB_ISA_DEFAULT "mips32r2"
683 #elif MIPS_ISA_DEFAULT == 37
684 #define MULTILIB_ISA_DEFAULT "mips32r6"
685 #elif MIPS_ISA_DEFAULT == 64
686 #define MULTILIB_ISA_DEFAULT "mips64"
687 #elif MIPS_ISA_DEFAULT == 65
688 #define MULTILIB_ISA_DEFAULT "mips64r2"
689 #elif MIPS_ISA_DEFAULT == 69
690 #define MULTILIB_ISA_DEFAULT "mips64r6"
691 #else
692 #define MULTILIB_ISA_DEFAULT "mips1"
693 #endif
694 #endif
695
696 #ifndef MIPS_ABI_DEFAULT
697 #define MIPS_ABI_DEFAULT ABI_32
698 #endif
699
700 /* Use the most portable ABI flag for the ASM specs. */
701
702 #if MIPS_ABI_DEFAULT == ABI_32
703 #define MULTILIB_ABI_DEFAULT "mabi=32"
704 #elif MIPS_ABI_DEFAULT == ABI_O64
705 #define MULTILIB_ABI_DEFAULT "mabi=o64"
706 #elif MIPS_ABI_DEFAULT == ABI_N32
707 #define MULTILIB_ABI_DEFAULT "mabi=n32"
708 #elif MIPS_ABI_DEFAULT == ABI_64
709 #define MULTILIB_ABI_DEFAULT "mabi=64"
710 #elif MIPS_ABI_DEFAULT == ABI_EABI
711 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
712 #endif
713
714 #ifndef MULTILIB_DEFAULTS
715 #define MULTILIB_DEFAULTS \
716 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
717 #endif
718
719 /* We must pass -EL to the linker by default for little endian embedded
720 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
721 linker will default to using big-endian output files. The OUTPUT_FORMAT
722 line must be in the linker script, otherwise -EB/-EL will not work. */
723
724 #ifndef ENDIAN_SPEC
725 #if TARGET_ENDIAN_DEFAULT == 0
726 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
727 #else
728 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
729 #endif
730 #endif
731
732 /* A spec condition that matches all non-mips16 -mips arguments. */
733
734 #define MIPS_ISA_LEVEL_OPTION_SPEC \
735 "mips1|mips2|mips3|mips4|mips32*|mips64*"
736
737 /* A spec condition that matches all non-mips16 architecture arguments. */
738
739 #define MIPS_ARCH_OPTION_SPEC \
740 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
741
742 /* A spec that infers a -mips argument from an -march argument. */
743
744 #define MIPS_ISA_LEVEL_SPEC \
745 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
746 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
747 %{march=mips2|march=r6000:-mips2} \
748 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
749 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
750 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
751 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
752 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
753 |march=34k*|march=74k*|march=m14k*|march=1004k* \
754 |march=interaptiv: -mips32r2} \
755 %{march=mips32r3: -mips32r3} \
756 %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \
757 %{march=mips32r6: -mips32r6} \
758 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
759 |march=xlr: -mips64} \
760 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
761 %{march=mips64r3: -mips64r3} \
762 %{march=mips64r5: -mips64r5} \
763 %{march=mips64r6|march=i6400: -mips64r6}}"
764
765 /* A spec that injects the default multilib ISA if no architecture is
766 specified. */
767
768 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
769 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
770 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
771
772 /* A spec that infers a -mhard-float or -msoft-float setting from an
773 -march argument. Note that soft-float and hard-float code are not
774 link-compatible. */
775
776 #define MIPS_ARCH_FLOAT_SPEC \
777 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
778 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
779 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
780 |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
781 march=*: -mhard-float}"
782
783 /* A spec condition that matches 32-bit options. It only works if
784 MIPS_ISA_LEVEL_SPEC has been applied. */
785
786 #define MIPS_32BIT_OPTION_SPEC \
787 "mips1|mips2|mips32*|mgp32"
788
789 /* A spec condition that matches architectures should be targeted with
790 o32 FPXX for compatibility reasons. */
791 #define MIPS_FPXX_OPTION_SPEC \
792 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
793 mips64|mips64r2|mips64r3|mips64r5"
794
795 /* Infer a -msynci setting from a -mips argument, on the assumption that
796 -msynci is desired where possible. */
797 #define MIPS_ISA_SYNCI_SPEC \
798 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
799 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
800
801 /* Infer a -mnan=2008 setting from a -mips argument. */
802 #define MIPS_ISA_NAN2008_SPEC \
803 "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \
804 %{!msoft-float:-mnan=2008}}"
805
806 #if (MIPS_ABI_DEFAULT == ABI_O64 \
807 || MIPS_ABI_DEFAULT == ABI_N32 \
808 || MIPS_ABI_DEFAULT == ABI_64)
809 #define OPT_ARCH64 "mabi=32|mgp32:;"
810 #define OPT_ARCH32 "mabi=32|mgp32"
811 #else
812 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
813 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
814 #endif
815
816 /* Support for a compile-time default CPU, et cetera. The rules are:
817 --with-arch is ignored if -march is specified or a -mips is specified
818 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
819 --with-tune is ignored if -mtune is specified; likewise
820 --with-tune-32 and --with-tune-64.
821 --with-abi is ignored if -mabi is specified.
822 --with-float is ignored if -mhard-float or -msoft-float are
823 specified.
824 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
825 specified.
826 --with-nan is ignored if -mnan is specified.
827 --with-fp-32 is ignored if -msoft-float, -msingle-float or -mfp are specified.
828 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
829 or -mno-odd-spreg are specified.
830 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
831 specified. */
832 #define OPTION_DEFAULT_SPECS \
833 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
834 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
835 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
836 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
837 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
838 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
839 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
840 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
841 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
842 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
843 {"fp_32", "%{" OPT_ARCH32 \
844 ":%{!msoft-float:%{!msingle-float:%{!mfp*:-mfp%(VALUE)}}}}" }, \
845 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
846 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
847 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
848 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
849 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
850 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
851
852 /* A spec that infers the:
853 -mnan=2008 setting from a -mips argument,
854 -mdsp setting from a -march argument. */
855 #define BASE_DRIVER_SELF_SPECS \
856 MIPS_ISA_NAN2008_SPEC, \
857 "%{!mno-dsp: \
858 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \
859 |march=interaptiv: -mdsp} \
860 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
861
862 #define DRIVER_SELF_SPECS \
863 MIPS_ISA_LEVEL_SPEC, \
864 BASE_DRIVER_SELF_SPECS
865
866 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
867 && ISA_HAS_COND_TRAP)
868
869 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
870
871 /* True if the ABI can only work with 64-bit integer registers. We
872 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
873 otherwise floating-point registers must also be 64-bit. */
874 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
875
876 /* Likewise for 32-bit regs. */
877 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
878
879 /* True if the file format uses 64-bit symbols. At present, this is
880 only true for n64, which uses 64-bit ELF. */
881 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
882
883 /* True if symbols are 64 bits wide. This is usually determined by
884 the ABI's file format, but it can be overridden by -msym32. Note that
885 overriding the size with -msym32 changes the ABI of relocatable objects,
886 although it doesn't change the ABI of a fully-linked object. */
887 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
888 && Pmode == DImode \
889 && !TARGET_SYM32)
890
891 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
892 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
893 || ISA_MIPS4 \
894 || ISA_MIPS64 \
895 || ISA_MIPS64R2 \
896 || ISA_MIPS64R3 \
897 || ISA_MIPS64R5 \
898 || ISA_MIPS64R6)
899
900 #define ISA_HAS_JR (mips_isa_rev <= 5)
901
902 #define ISA_HAS_DELAY_SLOTS 1
903
904 #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6)
905
906 /* ISA has branch likely instructions (e.g. mips2). */
907 /* Disable branchlikely for tx39 until compare rewrite. They haven't
908 been generated up to this point. */
909 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
910
911 /* ISA has 32 single-precision registers. */
912 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
913 && !TARGET_LOONGSON_3A) \
914 || TARGET_FLOAT64 \
915 || TARGET_MIPS5900)
916
917 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
918 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
919 || TARGET_MIPS5400 \
920 || TARGET_MIPS5500 \
921 || TARGET_MIPS5900 \
922 || TARGET_MIPS7000 \
923 || TARGET_MIPS9000 \
924 || TARGET_MAD \
925 || (mips_isa_rev >= 1 \
926 && mips_isa_rev <= 5)) \
927 && !TARGET_MIPS16)
928
929 /* ISA has a three-operand multiplication instruction. */
930 #define ISA_HAS_DMUL3 (TARGET_64BIT \
931 && TARGET_OCTEON \
932 && !TARGET_MIPS16)
933
934 /* ISA has HI and LO registers. */
935 #define ISA_HAS_HILO (mips_isa_rev <= 5)
936
937 /* ISA supports instructions DMULT and DMULTU. */
938 #define ISA_HAS_DMULT (TARGET_64BIT \
939 && !TARGET_MIPS5900 \
940 && mips_isa_rev <= 5)
941
942 /* ISA supports instructions MULT and MULTU. */
943 #define ISA_HAS_MULT (mips_isa_rev <= 5)
944
945 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
946 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
947
948 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
949 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
950
951 /* ISA supports instructions DDIV and DDIVU. */
952 #define ISA_HAS_DDIV (TARGET_64BIT \
953 && !TARGET_MIPS5900 \
954 && mips_isa_rev <= 5)
955
956 /* ISA supports instructions DIV and DIVU.
957 This is always true, but the macro is needed for ISA_HAS_<D>DIV
958 in mips.md. */
959 #define ISA_HAS_DIV (mips_isa_rev <= 5)
960
961 #define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \
962 || TARGET_LOONGSON_3A) \
963 && !TARGET_MIPS16)
964
965 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
966 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
967
968 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
969 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
970
971 /* ISA has the floating-point conditional move instructions introduced
972 in mips4. */
973 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
974 || (mips_isa_rev >= 1 \
975 && mips_isa_rev <= 5)) \
976 && !TARGET_MIPS5500 \
977 && !TARGET_MIPS16)
978
979 /* ISA has the integer conditional move instructions introduced in mips4 and
980 ST Loongson 2E/2F. */
981 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
982 || TARGET_MIPS5900 \
983 || TARGET_LOONGSON_2EF)
984
985 /* ISA has LDC1 and SDC1. */
986 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
987 && !TARGET_MIPS5900 \
988 && !TARGET_MIPS16)
989
990 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
991 branch on CC, and move (both FP and non-FP) on CC. */
992 #define ISA_HAS_8CC (ISA_MIPS4 \
993 || (mips_isa_rev >= 1 \
994 && mips_isa_rev <= 5))
995
996 /* ISA has the FP condition code instructions that store the flag in an
997 FP register. */
998 #define ISA_HAS_CCF (mips_isa_rev >= 6)
999
1000 #define ISA_HAS_SEL (mips_isa_rev >= 6)
1001
1002 /* This is a catch all for other mips4 instructions: indexed load, the
1003 FP madd and msub instructions, and the FP recip and recip sqrt
1004 instructions. Note that this macro should only be used by other
1005 ISA_HAS_* macros. */
1006 #define ISA_HAS_FP4 ((ISA_MIPS4 \
1007 || ISA_MIPS64 \
1008 || (mips_isa_rev >= 2 \
1009 && mips_isa_rev <= 5)) \
1010 && !TARGET_MIPS16)
1011
1012 /* ISA has floating-point indexed load and store instructions
1013 (LWXC1, LDXC1, SWXC1 and SDXC1). */
1014 #define ISA_HAS_LXC1_SXC1 ISA_HAS_FP4
1015
1016 /* ISA has paired-single instructions. */
1017 #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \
1018 || (mips_isa_rev >= 2 \
1019 && mips_isa_rev <= 5)) \
1020 && !TARGET_OCTEON)
1021
1022 /* ISA has conditional trap instructions. */
1023 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
1024 && !TARGET_MIPS16)
1025
1026 /* ISA has conditional trap with immediate instructions. */
1027 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
1028 && mips_isa_rev <= 5 \
1029 && !TARGET_MIPS16)
1030
1031 /* ISA has integer multiply-accumulate instructions, madd and msub. */
1032 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
1033 && mips_isa_rev <= 5)
1034
1035 /* Integer multiply-accumulate instructions should be generated. */
1036 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
1037
1038 /* ISA has 4 operand fused madd instructions of the form
1039 'd = [+-] (a * b [+-] c)'. */
1040 #define ISA_HAS_FUSED_MADD4 TARGET_MIPS8000
1041
1042 /* ISA has 4 operand unfused madd instructions of the form
1043 'd = [+-] (a * b [+-] c)'. */
1044 #define ISA_HAS_UNFUSED_MADD4 (ISA_HAS_FP4 && !TARGET_MIPS8000)
1045
1046 /* ISA has 3 operand r6 fused madd instructions of the form
1047 'c = c [+-] (a * b)'. */
1048 #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6)
1049
1050 /* ISA has 3 operand loongson fused madd instructions of the form
1051 'c = [+-] (a * b [+-] c)'. */
1052 #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF
1053
1054 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1055 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1056 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1057 this restriction to the MIPS IV ISA too. */
1058 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1059 (((ISA_HAS_FP4 \
1060 && ((MODE) == SFmode \
1061 || ((TARGET_FLOAT64 \
1062 || mips_isa_rev >= 2) \
1063 && (MODE) == DFmode))) \
1064 || (((MODE) == SFmode \
1065 || (MODE) == DFmode) \
1066 && (mips_isa_rev >= 6)) \
1067 || (TARGET_SB1 \
1068 && (MODE) == V2SFmode)) \
1069 && !TARGET_MIPS16)
1070
1071 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1072
1073 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1074
1075 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1076
1077 /* ISA has count leading zeroes/ones instruction (not implemented). */
1078 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1079
1080 /* ISA has three operand multiply instructions that put
1081 the high part in an accumulator: mulhi or mulhiu. */
1082 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1083 || TARGET_MIPS5500 \
1084 || TARGET_SR71K) \
1085 && !TARGET_MIPS16)
1086
1087 /* ISA has three operand multiply instructions that negate the
1088 result and put the result in an accumulator. */
1089 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1090 || TARGET_MIPS5500 \
1091 || TARGET_SR71K) \
1092 && !TARGET_MIPS16)
1093
1094 /* ISA has three operand multiply instructions that subtract the
1095 result from a 4th operand and put the result in an accumulator. */
1096 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1097 || TARGET_MIPS5500 \
1098 || TARGET_SR71K) \
1099 && !TARGET_MIPS16)
1100
1101 /* ISA has three operand multiply instructions that add the result
1102 to a 4th operand and put the result in an accumulator. */
1103 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1104 || TARGET_MIPS4130 \
1105 || TARGET_MIPS5400 \
1106 || TARGET_MIPS5500 \
1107 || TARGET_SR71K) \
1108 && !TARGET_MIPS16)
1109
1110 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1111 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1112 || TARGET_MIPS4130) \
1113 && !TARGET_MIPS16)
1114
1115 /* ISA has the "ror" (rotate right) instructions. */
1116 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1117 || TARGET_MIPS5400 \
1118 || TARGET_MIPS5500 \
1119 || TARGET_SR71K \
1120 || TARGET_SMARTMIPS) \
1121 && !TARGET_MIPS16)
1122
1123 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1124 64-bit targets also provide DSBH and DSHD. */
1125 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1126
1127 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1128 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1129 || TARGET_LOONGSON_2EF \
1130 || TARGET_MIPS5900 \
1131 || mips_isa_rev >= 1) \
1132 && !TARGET_MIPS16)
1133
1134 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1135 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
1136
1137 /* ISA has data indexed prefetch instructions. This controls use of
1138 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1139 (prefx is a cop1x instruction, so can only be used if FP is
1140 enabled.) */
1141 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1142
1143 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1144 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1145 also requires TARGET_DOUBLE_FLOAT. */
1146 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1147
1148 /* ISA includes the MIPS32r2 seb and seh instructions. */
1149 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1150
1151 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1152 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1153
1154 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1155 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1156 && mips_isa_rev >= 2)
1157
1158 /* ISA has lwxs instruction (load w/scaled index address. */
1159 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1160 && !TARGET_MIPS16)
1161
1162 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1163 #define ISA_HAS_LBX (TARGET_OCTEON2)
1164 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1165 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1166 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1167 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1168 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1169 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1170 && TARGET_64BIT)
1171
1172 /* The DSP ASE is available. */
1173 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1174
1175 /* Revision 2 of the DSP ASE is available. */
1176 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1177
1178 /* True if the result of a load is not available to the next instruction.
1179 A nop will then be needed between instructions like "lw $4,..."
1180 and "addiu $4,$4,1". */
1181 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1182 && !TARGET_MIPS3900 \
1183 && !TARGET_MIPS5900 \
1184 && !TARGET_MIPS16 \
1185 && !TARGET_MICROMIPS)
1186
1187 /* Likewise mtc1 and mfc1. */
1188 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1189 && !TARGET_MIPS5900 \
1190 && !TARGET_LOONGSON_2EF)
1191
1192 /* Likewise floating-point comparisons. */
1193 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1194 && !TARGET_MIPS5900 \
1195 && !TARGET_LOONGSON_2EF)
1196
1197 /* True if mflo and mfhi can be immediately followed by instructions
1198 which write to the HI and LO registers.
1199
1200 According to MIPS specifications, MIPS ISAs I, II, and III need
1201 (at least) two instructions between the reads of HI/LO and
1202 instructions which write them, and later ISAs do not. Contradicting
1203 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1204 the UM for the NEC Vr5000) document needing the instructions between
1205 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1206 MIPS64 and later ISAs to have the interlocks, plus any specific
1207 earlier-ISA CPUs for which CPU documentation declares that the
1208 instructions are really interlocked. */
1209 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1210 || TARGET_MIPS5500 \
1211 || TARGET_MIPS5900 \
1212 || TARGET_LOONGSON_2EF)
1213
1214 /* ISA includes synci, jr.hb and jalr.hb. */
1215 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1216
1217 /* ISA includes sync. */
1218 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1219 #define GENERATE_SYNC \
1220 (target_flags_explicit & MASK_LLSC \
1221 ? TARGET_LLSC && !TARGET_MIPS16 \
1222 : ISA_HAS_SYNC)
1223
1224 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1225 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1226 instructions. */
1227 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1228 #define GENERATE_LL_SC \
1229 (target_flags_explicit & MASK_LLSC \
1230 ? TARGET_LLSC && !TARGET_MIPS16 \
1231 : ISA_HAS_LL_SC)
1232
1233 #define ISA_HAS_SWAP (TARGET_XLP)
1234 #define ISA_HAS_LDADD (TARGET_XLP)
1235
1236 /* ISA includes the baddu instruction. */
1237 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1238
1239 /* ISA includes the bbit* instructions. */
1240 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1241
1242 /* ISA includes the cins instruction. */
1243 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1244
1245 /* ISA includes the exts instruction. */
1246 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1247
1248 /* ISA includes the seq and sne instructions. */
1249 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1250
1251 /* ISA includes the pop instruction. */
1252 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1253
1254 /* The CACHE instruction is available in non-MIPS16 code. */
1255 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1256
1257 /* The CACHE instruction is available. */
1258 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1259 \f
1260 /* Tell collect what flags to pass to nm. */
1261 #ifndef NM_FLAGS
1262 #define NM_FLAGS "-Bn"
1263 #endif
1264
1265 \f
1266 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1267 the assembler. It may be overridden by subtargets.
1268
1269 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1270 COFF debugging info. */
1271
1272 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1273 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1274 %{g} %{g0} %{g1} %{g2} %{g3} \
1275 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1276 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1277 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1278 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1279 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1280 #endif
1281
1282 /* FP_ASM_SPEC represents the floating-point options that must be passed
1283 to the assembler when FPXX support exists. Prior to that point the
1284 assembler could accept the options but were not required for
1285 correctness. We only add the options when absolutely necessary
1286 because passing -msoft-float to the assembler will cause it to reject
1287 all hard-float instructions which may require some user code to be
1288 updated. */
1289
1290 #ifdef HAVE_AS_DOT_MODULE
1291 #define FP_ASM_SPEC "\
1292 %{mhard-float} %{msoft-float} \
1293 %{msingle-float} %{mdouble-float}"
1294 #else
1295 #define FP_ASM_SPEC
1296 #endif
1297
1298 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1299 overridden by subtargets. */
1300
1301 #ifndef SUBTARGET_ASM_SPEC
1302 #define SUBTARGET_ASM_SPEC ""
1303 #endif
1304
1305 #undef ASM_SPEC
1306 #define ASM_SPEC "\
1307 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1308 %{mips32*} %{mips64*} \
1309 %{mips16} %{mno-mips16:-no-mips16} \
1310 %{mmicromips} %{mno-micromips} \
1311 %{mips3d} %{mno-mips3d:-no-mips3d} \
1312 %{mdmx} %{mno-mdmx:-no-mdmx} \
1313 %{mdsp} %{mno-dsp} \
1314 %{mdspr2} %{mno-dspr2} \
1315 %{mmcu} %{mno-mcu} \
1316 %{meva} %{mno-eva} \
1317 %{mvirt} %{mno-virt} \
1318 %{mxpa} %{mno-xpa} \
1319 %{msmartmips} %{mno-smartmips} \
1320 %{mmt} %{mno-mt} \
1321 %{mfix-rm7000} %{mno-fix-rm7000} \
1322 %{mfix-vr4120} %{mfix-vr4130} \
1323 %{mfix-24k} \
1324 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1325 %(subtarget_asm_debugging_spec) \
1326 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1327 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1328 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1329 %{modd-spreg} %{mno-odd-spreg} \
1330 %{mshared} %{mno-shared} \
1331 %{msym32} %{mno-sym32} \
1332 %{mtune=*}" \
1333 FP_ASM_SPEC "\
1334 %(subtarget_asm_spec)"
1335
1336 /* Extra switches sometimes passed to the linker. */
1337
1338 #ifndef LINK_SPEC
1339 #define LINK_SPEC "\
1340 %(endian_spec) \
1341 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1342 %{shared}"
1343 #endif /* LINK_SPEC defined */
1344
1345
1346 /* Specs for the compiler proper */
1347
1348 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1349 overridden by subtargets. */
1350 #ifndef SUBTARGET_CC1_SPEC
1351 #define SUBTARGET_CC1_SPEC ""
1352 #endif
1353
1354 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1355
1356 #undef CC1_SPEC
1357 #define CC1_SPEC "\
1358 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1359 %(subtarget_cc1_spec)"
1360
1361 /* Preprocessor specs. */
1362
1363 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1364 overridden by subtargets. */
1365 #ifndef SUBTARGET_CPP_SPEC
1366 #define SUBTARGET_CPP_SPEC ""
1367 #endif
1368
1369 #define CPP_SPEC "%(subtarget_cpp_spec)"
1370
1371 /* This macro defines names of additional specifications to put in the specs
1372 that can be used in various specifications like CC1_SPEC. Its definition
1373 is an initializer with a subgrouping for each command option.
1374
1375 Each subgrouping contains a string constant, that defines the
1376 specification name, and a string constant that used by the GCC driver
1377 program.
1378
1379 Do not define this macro if it does not need to do anything. */
1380
1381 #define EXTRA_SPECS \
1382 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1383 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1384 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1385 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1386 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1387 { "endian_spec", ENDIAN_SPEC }, \
1388 SUBTARGET_EXTRA_SPECS
1389
1390 #ifndef SUBTARGET_EXTRA_SPECS
1391 #define SUBTARGET_EXTRA_SPECS
1392 #endif
1393 \f
1394 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1395 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1396
1397 #ifndef PREFERRED_DEBUGGING_TYPE
1398 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1399 #endif
1400
1401 /* The size of DWARF addresses should be the same as the size of symbols
1402 in the target file format. They shouldn't depend on things like -msym32,
1403 because many DWARF consumers do not allow the mixture of address sizes
1404 that one would then get from linking -msym32 code with -msym64 code.
1405
1406 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1407 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1408 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1409
1410 /* By default, turn on GDB extensions. */
1411 #define DEFAULT_GDB_EXTENSIONS 1
1412
1413 /* Registers may have a prefix which can be ignored when matching
1414 user asm and register definitions. */
1415 #ifndef REGISTER_PREFIX
1416 #define REGISTER_PREFIX "$"
1417 #endif
1418
1419 /* Local compiler-generated symbols must have a prefix that the assembler
1420 understands. By default, this is $, although some targets (e.g.,
1421 NetBSD-ELF) need to override this. */
1422
1423 #ifndef LOCAL_LABEL_PREFIX
1424 #define LOCAL_LABEL_PREFIX "$"
1425 #endif
1426
1427 /* By default on the mips, external symbols do not have an underscore
1428 prepended, but some targets (e.g., NetBSD) require this. */
1429
1430 #ifndef USER_LABEL_PREFIX
1431 #define USER_LABEL_PREFIX ""
1432 #endif
1433
1434 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1435 since the length can run past this up to a continuation point. */
1436 #undef DBX_CONTIN_LENGTH
1437 #define DBX_CONTIN_LENGTH 1500
1438
1439 /* How to renumber registers for dbx and gdb. */
1440 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1441
1442 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1443 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1444
1445 /* The DWARF 2 CFA column which tracks the return address. */
1446 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1447
1448 /* Before the prologue, RA lives in r31. */
1449 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
1450
1451 /* Describe how we implement __builtin_eh_return. */
1452 #define EH_RETURN_DATA_REGNO(N) \
1453 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1454
1455 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1456
1457 #define EH_USES(N) mips_eh_uses (N)
1458
1459 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1460 The default for this in 64-bit mode is 8, which causes problems with
1461 SFmode register saves. */
1462 #define DWARF_CIE_DATA_ALIGNMENT -4
1463
1464 /* Correct the offset of automatic variables and arguments. Note that
1465 the MIPS debug format wants all automatic variables and arguments
1466 to be in terms of the virtual frame pointer (stack pointer before
1467 any adjustment in the function), while the MIPS 3.0 linker wants
1468 the frame pointer to be the stack pointer after the initial
1469 adjustment. */
1470
1471 #define DEBUGGER_AUTO_OFFSET(X) \
1472 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1473 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1474 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1475 \f
1476 /* Target machine storage layout */
1477
1478 #define BITS_BIG_ENDIAN 0
1479 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1480 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1481
1482 #define MAX_BITS_PER_WORD 64
1483
1484 /* Width of a word, in units (bytes). */
1485 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1486 #ifndef IN_LIBGCC2
1487 #define MIN_UNITS_PER_WORD 4
1488 #endif
1489
1490 /* For MIPS, width of a floating point register. */
1491 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1492
1493 /* The number of consecutive floating-point registers needed to store the
1494 largest format supported by the FPU. */
1495 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1496
1497 /* The number of consecutive floating-point registers needed to store the
1498 smallest format supported by the FPU. */
1499 #define MIN_FPRS_PER_FMT \
1500 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1501
1502 /* The largest size of value that can be held in floating-point
1503 registers and moved with a single instruction. */
1504 #define UNITS_PER_HWFPVALUE \
1505 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1506
1507 /* The largest size of value that can be held in floating-point
1508 registers. */
1509 #define UNITS_PER_FPVALUE \
1510 (TARGET_SOFT_FLOAT_ABI ? 0 \
1511 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1512 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1513
1514 /* The number of bytes in a double. */
1515 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1516
1517 /* Set the sizes of the core types. */
1518 #define SHORT_TYPE_SIZE 16
1519 #define INT_TYPE_SIZE 32
1520 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1521 #define LONG_LONG_TYPE_SIZE 64
1522
1523 #define FLOAT_TYPE_SIZE 32
1524 #define DOUBLE_TYPE_SIZE 64
1525 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1526
1527 /* Define the sizes of fixed-point types. */
1528 #define SHORT_FRACT_TYPE_SIZE 8
1529 #define FRACT_TYPE_SIZE 16
1530 #define LONG_FRACT_TYPE_SIZE 32
1531 #define LONG_LONG_FRACT_TYPE_SIZE 64
1532
1533 #define SHORT_ACCUM_TYPE_SIZE 16
1534 #define ACCUM_TYPE_SIZE 32
1535 #define LONG_ACCUM_TYPE_SIZE 64
1536 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1537 doesn't support 128-bit integers for MIPS32 currently. */
1538 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1539
1540 /* long double is not a fixed mode, but the idea is that, if we
1541 support long double, we also want a 128-bit integer type. */
1542 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1543
1544 /* Width in bits of a pointer. */
1545 #ifndef POINTER_SIZE
1546 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1547 #endif
1548
1549 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1550 #define PARM_BOUNDARY BITS_PER_WORD
1551
1552 /* Allocation boundary (in *bits*) for the code of a function. */
1553 #define FUNCTION_BOUNDARY 32
1554
1555 /* Alignment of field after `int : 0' in a structure. */
1556 #define EMPTY_FIELD_BOUNDARY 32
1557
1558 /* Every structure's size must be a multiple of this. */
1559 /* 8 is observed right on a DECstation and on riscos 4.02. */
1560 #define STRUCTURE_SIZE_BOUNDARY 8
1561
1562 /* There is no point aligning anything to a rounder boundary than this. */
1563 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1564
1565 /* All accesses must be aligned. */
1566 #define STRICT_ALIGNMENT 1
1567
1568 /* Define this if you wish to imitate the way many other C compilers
1569 handle alignment of bitfields and the structures that contain
1570 them.
1571
1572 The behavior is that the type written for a bit-field (`int',
1573 `short', or other integer type) imposes an alignment for the
1574 entire structure, as if the structure really did contain an
1575 ordinary field of that type. In addition, the bit-field is placed
1576 within the structure so that it would fit within such a field,
1577 not crossing a boundary for it.
1578
1579 Thus, on most machines, a bit-field whose type is written as `int'
1580 would not cross a four-byte boundary, and would force four-byte
1581 alignment for the whole structure. (The alignment used may not
1582 be four bytes; it is controlled by the other alignment
1583 parameters.)
1584
1585 If the macro is defined, its definition should be a C expression;
1586 a nonzero value for the expression enables this behavior. */
1587
1588 #define PCC_BITFIELD_TYPE_MATTERS 1
1589
1590 /* If defined, a C expression to compute the alignment given to a
1591 constant that is being placed in memory. CONSTANT is the constant
1592 and ALIGN is the alignment that the object would ordinarily have.
1593 The value of this macro is used instead of that alignment to align
1594 the object.
1595
1596 If this macro is not defined, then ALIGN is used.
1597
1598 The typical use of this macro is to increase alignment for string
1599 constants to be word aligned so that `strcpy' calls that copy
1600 constants can be done inline. */
1601
1602 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1603 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1604 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1605
1606 /* If defined, a C expression to compute the alignment for a static
1607 variable. TYPE is the data type, and ALIGN is the alignment that
1608 the object would ordinarily have. The value of this macro is used
1609 instead of that alignment to align the object.
1610
1611 If this macro is not defined, then ALIGN is used.
1612
1613 One use of this macro is to increase alignment of medium-size
1614 data to make it all fit in fewer cache lines. Another is to
1615 cause character arrays to be word-aligned so that `strcpy' calls
1616 that copy constants to character arrays can be done inline. */
1617
1618 #undef DATA_ALIGNMENT
1619 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1620 ((((ALIGN) < BITS_PER_WORD) \
1621 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1622 || TREE_CODE (TYPE) == UNION_TYPE \
1623 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1624
1625 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1626 character arrays to be word-aligned so that `strcpy' calls that copy
1627 constants to character arrays can be done inline, and 'strcmp' can be
1628 optimised to use word loads. */
1629 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1630 DATA_ALIGNMENT (TYPE, ALIGN)
1631
1632 #define PAD_VARARGS_DOWN \
1633 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1634
1635 /* Define if operations between registers always perform the operation
1636 on the full register even if a narrower mode is specified. */
1637 #define WORD_REGISTER_OPERATIONS 1
1638
1639 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1640 moves. All other references are zero extended. */
1641 #define LOAD_EXTEND_OP(MODE) \
1642 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1643 ? SIGN_EXTEND : ZERO_EXTEND)
1644
1645 /* Define this macro if it is advisable to hold scalars in registers
1646 in a wider mode than that declared by the program. In such cases,
1647 the value is constrained to be within the bounds of the declared
1648 type, but kept valid in the wider mode. The signedness of the
1649 extension may differ from that of the type. */
1650
1651 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1652 if (GET_MODE_CLASS (MODE) == MODE_INT \
1653 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1654 { \
1655 if ((MODE) == SImode) \
1656 (UNSIGNEDP) = 0; \
1657 (MODE) = Pmode; \
1658 }
1659
1660 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1661 Extensions of pointers to word_mode must be signed. */
1662 #define POINTERS_EXTEND_UNSIGNED false
1663
1664 /* Define if loading short immediate values into registers sign extends. */
1665 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1666
1667 /* The [d]clz instructions have the natural values at 0. */
1668
1669 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1670 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1671 \f
1672 /* Standard register usage. */
1673
1674 /* Number of hardware registers. We have:
1675
1676 - 32 integer registers
1677 - 32 floating point registers
1678 - 8 condition code registers
1679 - 2 accumulator registers (hi and lo)
1680 - 32 registers each for coprocessors 0, 2 and 3
1681 - 4 fake registers:
1682 - ARG_POINTER_REGNUM
1683 - FRAME_POINTER_REGNUM
1684 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1685 - CPRESTORE_SLOT_REGNUM
1686 - 2 dummy entries that were used at various times in the past.
1687 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1688 - 6 DSP control registers */
1689
1690 #define FIRST_PSEUDO_REGISTER 188
1691
1692 /* By default, fix the kernel registers ($26 and $27), the global
1693 pointer ($28) and the stack pointer ($29). This can change
1694 depending on the command-line options.
1695
1696 Regarding coprocessor registers: without evidence to the contrary,
1697 it's best to assume that each coprocessor register has a unique
1698 use. This can be overridden, in, e.g., mips_option_override or
1699 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1700 inappropriate for a particular target. */
1701
1702 #define FIXED_REGISTERS \
1703 { \
1704 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1705 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1706 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1707 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1708 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1709 /* COP0 registers */ \
1710 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1711 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1712 /* COP2 registers */ \
1713 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1714 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1715 /* COP3 registers */ \
1716 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1717 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1718 /* 6 DSP accumulator registers & 6 control registers */ \
1719 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1720 }
1721
1722
1723 /* Set up this array for o32 by default.
1724
1725 Note that we don't mark $31 as a call-clobbered register. The idea is
1726 that it's really the call instructions themselves which clobber $31.
1727 We don't care what the called function does with it afterwards.
1728
1729 This approach makes it easier to implement sibcalls. Unlike normal
1730 calls, sibcalls don't clobber $31, so the register reaches the
1731 called function in tact. EPILOGUE_USES says that $31 is useful
1732 to the called function. */
1733
1734 #define CALL_USED_REGISTERS \
1735 { \
1736 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1737 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1738 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1739 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1740 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1741 /* COP0 registers */ \
1742 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1743 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1744 /* COP2 registers */ \
1745 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1746 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1747 /* COP3 registers */ \
1748 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1749 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1750 /* 6 DSP accumulator registers & 6 control registers */ \
1751 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1752 }
1753
1754
1755 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1756
1757 #define CALL_REALLY_USED_REGISTERS \
1758 { /* General registers. */ \
1759 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1760 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1761 /* Floating-point registers. */ \
1762 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1763 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1764 /* Others. */ \
1765 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1766 /* COP0 registers */ \
1767 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1769 /* COP2 registers */ \
1770 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1771 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1772 /* COP3 registers */ \
1773 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1774 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1775 /* 6 DSP accumulator registers & 6 control registers */ \
1776 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1777 }
1778
1779 /* Internal macros to classify a register number as to whether it's a
1780 general purpose register, a floating point register, a
1781 multiply/divide register, or a status register. */
1782
1783 #define GP_REG_FIRST 0
1784 #define GP_REG_LAST 31
1785 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1786 #define GP_DBX_FIRST 0
1787 #define K0_REG_NUM (GP_REG_FIRST + 26)
1788 #define K1_REG_NUM (GP_REG_FIRST + 27)
1789 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1790
1791 #define FP_REG_FIRST 32
1792 #define FP_REG_LAST 63
1793 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1794 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1795
1796 #define MD_REG_FIRST 64
1797 #define MD_REG_LAST 65
1798 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1799 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1800
1801 /* The DWARF 2 CFA column which tracks the return address from a
1802 signal handler context. This means that to maintain backwards
1803 compatibility, no hard register can be assigned this column if it
1804 would need to be handled by the DWARF unwinder. */
1805 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1806
1807 #define ST_REG_FIRST 67
1808 #define ST_REG_LAST 74
1809 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1810
1811
1812 /* FIXME: renumber. */
1813 #define COP0_REG_FIRST 80
1814 #define COP0_REG_LAST 111
1815 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1816
1817 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1818 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1819 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1820
1821 #define COP2_REG_FIRST 112
1822 #define COP2_REG_LAST 143
1823 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1824
1825 #define COP3_REG_FIRST 144
1826 #define COP3_REG_LAST 175
1827 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1828
1829 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1830 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1831 #define ALL_COP_REG_LAST COP3_REG_LAST
1832 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1833
1834 #define DSP_ACC_REG_FIRST 176
1835 #define DSP_ACC_REG_LAST 181
1836 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1837
1838 #define AT_REGNUM (GP_REG_FIRST + 1)
1839 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1840 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1841
1842 /* A few bitfield locations for the coprocessor registers. */
1843 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1844 the cause register for the EIC interrupt mode. */
1845 #define CAUSE_IPL 10
1846 /* COP1 Enable is at bit 29 of the status register. */
1847 #define SR_COP1 29
1848 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1849 #define SR_IPL 10
1850 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status
1851 register. */
1852 #define SR_IM0 8
1853 /* Exception Level is at bit 1 of the status register. */
1854 #define SR_EXL 1
1855 /* Interrupt Enable is at bit 0 of the status register. */
1856 #define SR_IE 0
1857
1858 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1859 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1860 should be used instead. */
1861 #define FPSW_REGNUM ST_REG_FIRST
1862
1863 #define GP_REG_P(REGNO) \
1864 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1865 #define M16_REG_P(REGNO) \
1866 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1867 #define M16STORE_REG_P(REGNO) \
1868 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1869 #define FP_REG_P(REGNO) \
1870 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1871 #define MD_REG_P(REGNO) \
1872 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1873 #define ST_REG_P(REGNO) \
1874 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1875 #define COP0_REG_P(REGNO) \
1876 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1877 #define COP2_REG_P(REGNO) \
1878 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1879 #define COP3_REG_P(REGNO) \
1880 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1881 #define ALL_COP_REG_P(REGNO) \
1882 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1883 /* Test if REGNO is one of the 6 new DSP accumulators. */
1884 #define DSP_ACC_REG_P(REGNO) \
1885 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1886 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1887 #define ACC_REG_P(REGNO) \
1888 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1889
1890 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1891
1892 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1893 to initialize the mips16 gp pseudo register. */
1894 #define CONST_GP_P(X) \
1895 (GET_CODE (X) == CONST \
1896 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1897 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1898
1899 /* Return coprocessor number from register number. */
1900
1901 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1902 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1903 : COP3_REG_P (REGNO) ? '3' : '?')
1904
1905
1906 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1907
1908 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1909 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1910
1911 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1912 mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
1913
1914 /* Select a register mode required for caller save of hard regno REGNO. */
1915 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1916 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1917
1918 /* Odd-numbered single-precision registers are not considered callee-saved
1919 for o32 FPXX as they will be clobbered when run on an FR=1 FPU. */
1920 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1921 (TARGET_FLOATXX && hard_regno_nregs[REGNO][MODE] == 1 \
1922 && FP_REG_P (REGNO) && ((REGNO) & 1))
1923
1924 #define MODES_TIEABLE_P mips_modes_tieable_p
1925
1926 /* Register to use for pushing function arguments. */
1927 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1928
1929 /* These two registers don't really exist: they get eliminated to either
1930 the stack or hard frame pointer. */
1931 #define ARG_POINTER_REGNUM 77
1932 #define FRAME_POINTER_REGNUM 78
1933
1934 /* $30 is not available on the mips16, so we use $17 as the frame
1935 pointer. */
1936 #define HARD_FRAME_POINTER_REGNUM \
1937 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1938
1939 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1940 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1941
1942 /* Register in which static-chain is passed to a function. */
1943 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1944
1945 /* Registers used as temporaries in prologue/epilogue code:
1946
1947 - If a MIPS16 PIC function needs access to _gp, it first loads
1948 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1949
1950 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1951 register. The register must not conflict with MIPS16_PIC_TEMP.
1952
1953 - If we aren't generating MIPS16 code, the prologue can also use
1954 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1955
1956 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1957 register.
1958
1959 If we're generating MIPS16 code, these registers must come from the
1960 core set of 8. The prologue registers mustn't conflict with any
1961 incoming arguments, the static chain pointer, or the frame pointer.
1962 The epilogue temporary mustn't conflict with the return registers,
1963 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1964 or the EH data registers.
1965
1966 If we're generating interrupt handlers, we use K0 as a temporary register
1967 in prologue/epilogue code. */
1968
1969 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1970 #define MIPS_PROLOGUE_TEMP_REGNUM \
1971 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1972 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1973 (TARGET_MIPS16 \
1974 ? (gcc_unreachable (), INVALID_REGNUM) \
1975 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
1976 #define MIPS_EPILOGUE_TEMP_REGNUM \
1977 (cfun->machine->interrupt_handler_p \
1978 ? K0_REG_NUM \
1979 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1980
1981 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1982 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1983 #define MIPS_PROLOGUE_TEMP2(MODE) \
1984 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
1985 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1986
1987 /* Define this macro if it is as good or better to call a constant
1988 function address than to call an address kept in a register. */
1989 #define NO_FUNCTION_CSE 1
1990
1991 /* The ABI-defined global pointer. Sometimes we use a different
1992 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1993 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1994
1995 /* We normally use $28 as the global pointer. However, when generating
1996 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1997 register instead. They can then avoid saving and restoring $28
1998 and perhaps avoid using a frame at all.
1999
2000 When a leaf function uses something other than $28, mips_expand_prologue
2001 will modify pic_offset_table_rtx in place. Take the register number
2002 from there after reload. */
2003 #define PIC_OFFSET_TABLE_REGNUM \
2004 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
2005 \f
2006 /* Define the classes of registers for register constraints in the
2007 machine description. Also define ranges of constants.
2008
2009 One of the classes must always be named ALL_REGS and include all hard regs.
2010 If there is more than one class, another class must be named NO_REGS
2011 and contain no registers.
2012
2013 The name GENERAL_REGS must be the name of a class (or an alias for
2014 another name such as ALL_REGS). This is the class of registers
2015 that is allowed by "g" or "r" in a register constraint.
2016 Also, registers outside this class are allocated only when
2017 instructions express preferences for them.
2018
2019 The classes must be numbered in nondecreasing order; that is,
2020 a larger-numbered class must never be contained completely
2021 in a smaller-numbered class.
2022
2023 For any two classes, it is very desirable that there be another
2024 class that represents their union. */
2025
2026 enum reg_class
2027 {
2028 NO_REGS, /* no registers in set */
2029 M16_STORE_REGS, /* microMIPS store registers */
2030 M16_REGS, /* mips16 directly accessible registers */
2031 M16_SP_REGS, /* mips16 + $sp */
2032 T_REG, /* mips16 T register ($24) */
2033 M16_T_REGS, /* mips16 registers plus T register */
2034 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2035 V1_REG, /* Register $v1 ($3) used for TLS access. */
2036 SPILL_REGS, /* All but $sp and call preserved regs are in here */
2037 LEA_REGS, /* Every GPR except $25 */
2038 GR_REGS, /* integer registers */
2039 FP_REGS, /* floating point registers */
2040 MD0_REG, /* first multiply/divide register */
2041 MD1_REG, /* second multiply/divide register */
2042 MD_REGS, /* multiply/divide registers (hi/lo) */
2043 COP0_REGS, /* generic coprocessor classes */
2044 COP2_REGS,
2045 COP3_REGS,
2046 ST_REGS, /* status registers (fp status) */
2047 DSP_ACC_REGS, /* DSP accumulator registers */
2048 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
2049 FRAME_REGS, /* $arg and $frame */
2050 GR_AND_MD0_REGS, /* union classes */
2051 GR_AND_MD1_REGS,
2052 GR_AND_MD_REGS,
2053 GR_AND_ACC_REGS,
2054 ALL_REGS, /* all registers */
2055 LIM_REG_CLASSES /* max value + 1 */
2056 };
2057
2058 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2059
2060 #define GENERAL_REGS GR_REGS
2061
2062 /* An initializer containing the names of the register classes as C
2063 string constants. These names are used in writing some of the
2064 debugging dumps. */
2065
2066 #define REG_CLASS_NAMES \
2067 { \
2068 "NO_REGS", \
2069 "M16_STORE_REGS", \
2070 "M16_REGS", \
2071 "M16_SP_REGS", \
2072 "T_REG", \
2073 "M16_T_REGS", \
2074 "PIC_FN_ADDR_REG", \
2075 "V1_REG", \
2076 "SPILL_REGS", \
2077 "LEA_REGS", \
2078 "GR_REGS", \
2079 "FP_REGS", \
2080 "MD0_REG", \
2081 "MD1_REG", \
2082 "MD_REGS", \
2083 /* coprocessor registers */ \
2084 "COP0_REGS", \
2085 "COP2_REGS", \
2086 "COP3_REGS", \
2087 "ST_REGS", \
2088 "DSP_ACC_REGS", \
2089 "ACC_REGS", \
2090 "FRAME_REGS", \
2091 "GR_AND_MD0_REGS", \
2092 "GR_AND_MD1_REGS", \
2093 "GR_AND_MD_REGS", \
2094 "GR_AND_ACC_REGS", \
2095 "ALL_REGS" \
2096 }
2097
2098 /* An initializer containing the contents of the register classes,
2099 as integers which are bit masks. The Nth integer specifies the
2100 contents of class N. The way the integer MASK is interpreted is
2101 that register R is in the class if `MASK & (1 << R)' is 1.
2102
2103 When the machine has more than 32 registers, an integer does not
2104 suffice. Then the integers are replaced by sub-initializers,
2105 braced groupings containing several integers. Each
2106 sub-initializer must be suitable as an initializer for the type
2107 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2108
2109 #define REG_CLASS_CONTENTS \
2110 { \
2111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2112 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2113 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2114 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2115 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2116 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2117 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2118 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2119 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2120 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2121 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2122 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2123 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2124 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2125 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2126 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2127 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2128 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2129 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2130 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2131 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2132 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2133 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2134 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2135 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2136 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2137 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2138 }
2139
2140
2141 /* A C expression whose value is a register class containing hard
2142 register REGNO. In general there is more that one such class;
2143 choose a class which is "minimal", meaning that no smaller class
2144 also contains the register. */
2145
2146 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2147
2148 /* A macro whose definition is the name of the class to which a
2149 valid base register must belong. A base register is one used in
2150 an address which is the register value plus a displacement. */
2151
2152 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2153
2154 /* A macro whose definition is the name of the class to which a
2155 valid index register must belong. An index register is one used
2156 in an address where its value is either multiplied by a scale
2157 factor or added to another register (as well as added to a
2158 displacement). */
2159
2160 #define INDEX_REG_CLASS NO_REGS
2161
2162 /* We generally want to put call-clobbered registers ahead of
2163 call-saved ones. (IRA expects this.) */
2164
2165 #define REG_ALLOC_ORDER \
2166 { /* Accumulator registers. When GPRs and accumulators have equal \
2167 cost, we generally prefer to use accumulators. For example, \
2168 a division of multiplication result is better allocated to LO, \
2169 so that we put the MFLO at the point of use instead of at the \
2170 point of definition. It's also needed if we're to take advantage \
2171 of the extra accumulators available with -mdspr2. In some cases, \
2172 it can also help to reduce register pressure. */ \
2173 64, 65,176,177,178,179,180,181, \
2174 /* Call-clobbered GPRs. */ \
2175 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2176 24, 25, 31, \
2177 /* The global pointer. This is call-clobbered for o32 and o64 \
2178 abicalls, call-saved for n32 and n64 abicalls, and a program \
2179 invariant otherwise. Putting it between the call-clobbered \
2180 and call-saved registers should cope with all eventualities. */ \
2181 28, \
2182 /* Call-saved GPRs. */ \
2183 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2184 /* GPRs that can never be exposed to the register allocator. */ \
2185 0, 26, 27, 29, \
2186 /* Call-clobbered FPRs. */ \
2187 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2188 48, 49, 50, 51, \
2189 /* FPRs that are usually call-saved. The odd ones are actually \
2190 call-clobbered for n32, but listing them ahead of the even \
2191 registers might encourage the register allocator to fragment \
2192 the available FPR pairs. We need paired FPRs to store long \
2193 doubles, so it isn't clear that using a different order \
2194 for n32 would be a win. */ \
2195 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2196 /* None of the remaining classes have defined call-saved \
2197 registers. */ \
2198 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2199 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2200 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2201 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2202 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2203 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2204 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2205 182,183,184,185,186,187 \
2206 }
2207
2208 /* True if VALUE is an unsigned 6-bit number. */
2209
2210 #define UIMM6_OPERAND(VALUE) \
2211 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2212
2213 /* True if VALUE is a signed 10-bit number. */
2214
2215 #define IMM10_OPERAND(VALUE) \
2216 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2217
2218 /* True if VALUE is a signed 16-bit number. */
2219
2220 #define SMALL_OPERAND(VALUE) \
2221 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2222
2223 /* True if VALUE is an unsigned 16-bit number. */
2224
2225 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2226 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2227
2228 /* True if VALUE can be loaded into a register using LUI. */
2229
2230 #define LUI_OPERAND(VALUE) \
2231 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2232 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2233
2234 /* Return a value X with the low 16 bits clear, and such that
2235 VALUE - X is a signed 16-bit value. */
2236
2237 #define CONST_HIGH_PART(VALUE) \
2238 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2239
2240 #define CONST_LOW_PART(VALUE) \
2241 ((VALUE) - CONST_HIGH_PART (VALUE))
2242
2243 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2244 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2245 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2246 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2247 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2248
2249 /* The HI and LO registers can only be reloaded via the general
2250 registers. Condition code registers can only be loaded to the
2251 general registers, and from the floating point registers. */
2252
2253 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2254 mips_secondary_reload_class (CLASS, MODE, X, true)
2255 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2256 mips_secondary_reload_class (CLASS, MODE, X, false)
2257
2258 /* When targeting the o32 FPXX ABI, all moves with a length of doubleword
2259 or greater must be performed by FR-mode-aware instructions.
2260 This can be achieved using MFHC1/MTHC1 when these instructions are
2261 available but otherwise moves must go via memory.
2262 For the o32 FP64A ABI, all odd-numbered moves with a length of
2263 doubleword or greater are required to use memory. Using MTC1/MFC1
2264 to access the lower-half of these registers would require a forbidden
2265 single-precision access. We require all double-word moves to use
2266 memory because adding even and odd floating-point registers classes
2267 would have a significant impact on the backend. */
2268 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2269 mips_secondary_memory_needed ((CLASS1), (CLASS2), (MODE))
2270
2271 /* Return the maximum number of consecutive registers
2272 needed to represent mode MODE in a register of class CLASS. */
2273
2274 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2275
2276 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2277 mips_cannot_change_mode_class (FROM, TO, CLASS)
2278 \f
2279 /* Stack layout; function entry, exit and calling. */
2280
2281 #define STACK_GROWS_DOWNWARD 1
2282
2283 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2284
2285 /* Size of the area allocated in the frame to save the GP. */
2286
2287 #define MIPS_GP_SAVE_AREA_SIZE \
2288 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2289
2290 /* The offset of the first local variable from the frame pointer. See
2291 mips_compute_frame_info for details about the frame layout. */
2292
2293 #define STARTING_FRAME_OFFSET \
2294 (FRAME_GROWS_DOWNWARD \
2295 ? 0 \
2296 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2297
2298 #define RETURN_ADDR_RTX mips_return_addr
2299
2300 /* Mask off the MIPS16 ISA bit in unwind addresses.
2301
2302 The reason for this is a little subtle. When unwinding a call,
2303 we are given the call's return address, which on most targets
2304 is the address of the following instruction. However, what we
2305 actually want to find is the EH region for the call itself.
2306 The target-independent unwind code therefore searches for "RA - 1".
2307
2308 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2309 RA - 1 is therefore the real (even-valued) start of the return
2310 instruction. EH region labels are usually odd-valued MIPS16 symbols
2311 too, so a search for an even address within a MIPS16 region would
2312 usually work.
2313
2314 However, there is an exception. If the end of an EH region is also
2315 the end of a function, the end label is allowed to be even. This is
2316 necessary because a following non-MIPS16 function may also need EH
2317 information for its first instruction.
2318
2319 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2320 non-ISA-encoded address. This probably isn't ideal, but it is
2321 the traditional (legacy) behavior. It is therefore only safe
2322 to search MIPS EH regions for an _odd-valued_ address.
2323
2324 Masking off the ISA bit means that the target-independent code
2325 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2326 #define MASK_RETURN_ADDR GEN_INT (-2)
2327
2328
2329 /* Similarly, don't use the least-significant bit to tell pointers to
2330 code from vtable index. */
2331
2332 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2333
2334 /* The eliminations to $17 are only used for mips16 code. See the
2335 definition of HARD_FRAME_POINTER_REGNUM. */
2336
2337 #define ELIMINABLE_REGS \
2338 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2339 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2340 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2341 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2342 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2343 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2344
2345 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2346 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2347
2348 /* Allocate stack space for arguments at the beginning of each function. */
2349 #define ACCUMULATE_OUTGOING_ARGS 1
2350
2351 /* The argument pointer always points to the first argument. */
2352 #define FIRST_PARM_OFFSET(FNDECL) 0
2353
2354 /* o32 and o64 reserve stack space for all argument registers. */
2355 #define REG_PARM_STACK_SPACE(FNDECL) \
2356 (TARGET_OLDABI \
2357 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2358 : 0)
2359
2360 /* Define this if it is the responsibility of the caller to
2361 allocate the area reserved for arguments passed in registers.
2362 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2363 of this macro is to determine whether the space is included in
2364 `crtl->outgoing_args_size'. */
2365 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2366
2367 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2368 \f
2369 /* Symbolic macros for the registers used to return integer and floating
2370 point values. */
2371
2372 #define GP_RETURN (GP_REG_FIRST + 2)
2373 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2374
2375 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2376
2377 /* Symbolic macros for the first/last argument registers. */
2378
2379 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2380 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2381 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2382 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2383
2384 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2385 are used for returning complex double values in soft-float code, so $6 is the
2386 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2387 $gp itself as the temporary. */
2388 #define POST_CALL_TMP_REG \
2389 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2390
2391 /* 1 if N is a possible register number for function argument passing.
2392 We have no FP argument registers when soft-float. Special handling
2393 is required for O32 where only even numbered registers are used for
2394 O32-FPXX and O32-FP64. */
2395
2396 #define FUNCTION_ARG_REGNO_P(N) \
2397 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2398 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2399 && (mips_abi != ABI_32 \
2400 || TARGET_FLOAT32 \
2401 || ((N) % 2 == 0)))) \
2402 && !fixed_regs[N])
2403 \f
2404 /* This structure has to cope with two different argument allocation
2405 schemes. Most MIPS ABIs view the arguments as a structure, of which
2406 the first N words go in registers and the rest go on the stack. If I
2407 < N, the Ith word might go in Ith integer argument register or in a
2408 floating-point register. For these ABIs, we only need to remember
2409 the offset of the current argument into the structure.
2410
2411 The EABI instead allocates the integer and floating-point arguments
2412 separately. The first N words of FP arguments go in FP registers,
2413 the rest go on the stack. Likewise, the first N words of the other
2414 arguments go in integer registers, and the rest go on the stack. We
2415 need to maintain three counts: the number of integer registers used,
2416 the number of floating-point registers used, and the number of words
2417 passed on the stack.
2418
2419 We could keep separate information for the two ABIs (a word count for
2420 the standard ABIs, and three separate counts for the EABI). But it
2421 seems simpler to view the standard ABIs as forms of EABI that do not
2422 allocate floating-point registers.
2423
2424 So for the standard ABIs, the first N words are allocated to integer
2425 registers, and mips_function_arg decides on an argument-by-argument
2426 basis whether that argument should really go in an integer register,
2427 or in a floating-point one. */
2428
2429 typedef struct mips_args {
2430 /* Always true for varargs functions. Otherwise true if at least
2431 one argument has been passed in an integer register. */
2432 int gp_reg_found;
2433
2434 /* The number of arguments seen so far. */
2435 unsigned int arg_number;
2436
2437 /* The number of integer registers used so far. For all ABIs except
2438 EABI, this is the number of words that have been added to the
2439 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2440 unsigned int num_gprs;
2441
2442 /* For EABI, the number of floating-point registers used so far. */
2443 unsigned int num_fprs;
2444
2445 /* The number of words passed on the stack. */
2446 unsigned int stack_words;
2447
2448 /* On the mips16, we need to keep track of which floating point
2449 arguments were passed in general registers, but would have been
2450 passed in the FP regs if this were a 32-bit function, so that we
2451 can move them to the FP regs if we wind up calling a 32-bit
2452 function. We record this information in fp_code, encoded in base
2453 four. A zero digit means no floating point argument, a one digit
2454 means an SFmode argument, and a two digit means a DFmode argument,
2455 and a three digit is not used. The low order digit is the first
2456 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2457 an SFmode argument. ??? A more sophisticated approach will be
2458 needed if MIPS_ABI != ABI_32. */
2459 int fp_code;
2460
2461 /* True if the function has a prototype. */
2462 int prototype;
2463 } CUMULATIVE_ARGS;
2464
2465 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2466 for a call to a function whose data type is FNTYPE.
2467 For a library call, FNTYPE is 0. */
2468
2469 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2470 mips_init_cumulative_args (&CUM, FNTYPE)
2471
2472 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2473 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2474
2475 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2476 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2477
2478 /* True if using EABI and varargs can be passed in floating-point
2479 registers. Under these conditions, we need a more complex form
2480 of va_list, which tracks GPR, FPR and stack arguments separately. */
2481 #define EABI_FLOAT_VARARGS_P \
2482 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2483
2484 \f
2485 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2486
2487 /* Treat LOC as a byte offset from the stack pointer and round it up
2488 to the next fully-aligned offset. */
2489 #define MIPS_STACK_ALIGN(LOC) \
2490 (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
2491
2492 \f
2493 /* Output assembler code to FILE to increment profiler label # LABELNO
2494 for profiling a function entry. */
2495
2496 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2497
2498 /* The profiler preserves all interesting registers, including $31. */
2499 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2500
2501 /* No mips port has ever used the profiler counter word, so don't emit it
2502 or the label for it. */
2503
2504 #define NO_PROFILE_COUNTERS 1
2505
2506 /* Define this macro if the code for function profiling should come
2507 before the function prologue. Normally, the profiling code comes
2508 after. */
2509
2510 /* #define PROFILE_BEFORE_PROLOGUE */
2511
2512 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2513 the stack pointer does not matter. The value is tested only in
2514 functions that have frame pointers.
2515 No definition is equivalent to always zero. */
2516
2517 #define EXIT_IGNORE_STACK 1
2518
2519 \f
2520 /* Trampolines are a block of code followed by two pointers. */
2521
2522 #define TRAMPOLINE_SIZE \
2523 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2524
2525 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2526 pointers from a single LUI base. */
2527
2528 #define TRAMPOLINE_ALIGNMENT 64
2529
2530 /* mips_trampoline_init calls this library function to flush
2531 program and data caches. */
2532
2533 #ifndef CACHE_FLUSH_FUNC
2534 #define CACHE_FLUSH_FUNC "_flush_cache"
2535 #endif
2536
2537 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2538 /* Flush both caches. We need to flush the data cache in case \
2539 the system has a write-back cache. */ \
2540 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2541 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2542 GEN_INT (3), TYPE_MODE (integer_type_node))
2543
2544 \f
2545 /* Addressing modes, and classification of registers for them. */
2546
2547 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2548 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2549 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2550 \f
2551 /* Maximum number of registers that can appear in a valid memory address. */
2552
2553 #define MAX_REGS_PER_ADDRESS 1
2554
2555 /* Check for constness inline but use mips_legitimate_address_p
2556 to check whether a constant really is an address. */
2557
2558 #define CONSTANT_ADDRESS_P(X) \
2559 (CONSTANT_P (X) && memory_address_p (SImode, X))
2560
2561 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2562 'the start of the function that this code is output in'. */
2563
2564 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2565 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2566 asm_fprintf ((FILE), "%U%s", \
2567 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2568 else \
2569 asm_fprintf ((FILE), "%U%s", (NAME))
2570 \f
2571 /* Flag to mark a function decl symbol that requires a long call. */
2572 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2573 #define SYMBOL_REF_LONG_CALL_P(X) \
2574 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2575
2576 /* This flag marks functions that cannot be lazily bound. */
2577 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2578 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2579 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2580
2581 /* True if we're generating a form of MIPS16 code in which jump tables
2582 are stored in the text section and encoded as 16-bit PC-relative
2583 offsets. This is only possible when general text loads are allowed,
2584 since the table access itself will be an "lh" instruction. If the
2585 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2586 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2587
2588 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2589
2590 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2591
2592 /* Only use short offsets if their range will not overflow. */
2593 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2594 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2595 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2596 : SImode)
2597
2598 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2599
2600 /* Define this as 1 if `char' should by default be signed; else as 0. */
2601 #ifndef DEFAULT_SIGNED_CHAR
2602 #define DEFAULT_SIGNED_CHAR 1
2603 #endif
2604
2605 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2606 we generally don't want to use them for copying arbitrary data.
2607 A single N-word move is usually the same cost as N single-word moves. */
2608 #define MOVE_MAX UNITS_PER_WORD
2609 #define MAX_MOVE_MAX 8
2610
2611 /* Define this macro as a C expression which is nonzero if
2612 accessing less than a word of memory (i.e. a `char' or a
2613 `short') is no faster than accessing a word of memory, i.e., if
2614 such access require more than one instruction or if there is no
2615 difference in cost between byte and (aligned) word loads.
2616
2617 On RISC machines, it tends to generate better code to define
2618 this as 1, since it avoids making a QI or HI mode register.
2619
2620 But, generating word accesses for -mips16 is generally bad as shifts
2621 (often extended) would be needed for byte accesses. */
2622 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2623
2624 /* Standard MIPS integer shifts truncate the shift amount to the
2625 width of the shifted operand. However, Loongson vector shifts
2626 do not truncate the shift amount at all. */
2627 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2628
2629 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2630 is done just by pretending it is already truncated. */
2631 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2632 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2633
2634
2635 /* Specify the machine mode that pointers have.
2636 After generation of rtl, the compiler makes no further distinction
2637 between pointers and any other objects of this machine mode. */
2638
2639 #ifndef Pmode
2640 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2641 #endif
2642
2643 /* Give call MEMs SImode since it is the "most permissive" mode
2644 for both 32-bit and 64-bit targets. */
2645
2646 #define FUNCTION_MODE SImode
2647
2648 \f
2649 /* We allocate $fcc registers by hand and can't cope with moves of
2650 CCmode registers to and from pseudos (or memory). */
2651 #define AVOID_CCMODE_COPIES
2652
2653 /* A C expression for the cost of a branch instruction. A value of
2654 1 is the default; other values are interpreted relative to that. */
2655
2656 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2657 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2658
2659 /* The MIPS port has several functions that return an instruction count.
2660 Multiplying the count by this value gives the number of bytes that
2661 the instructions occupy. */
2662 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2663
2664 /* The length of a NOP in bytes. */
2665 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2666
2667 /* If defined, modifies the length assigned to instruction INSN as a
2668 function of the context in which it is used. LENGTH is an lvalue
2669 that contains the initially computed length of the insn and should
2670 be updated with the correct length of the insn. */
2671 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2672 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2673
2674 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2675 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2676 its operands. */
2677 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2678 "%*" OPCODE "%?\t" OPERANDS "%/"
2679
2680 #define MIPS_BRANCH_C(OPCODE, OPERANDS) \
2681 "%*" OPCODE "%:\t" OPERANDS
2682
2683 /* Return an asm string that forces INSN to be treated as an absolute
2684 J or JAL instruction instead of an assembler macro. */
2685 #define MIPS_ABSOLUTE_JUMP(INSN) \
2686 (TARGET_ABICALLS_PIC2 \
2687 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2688 : INSN)
2689
2690 \f
2691 /* Control the assembler format that we output. */
2692
2693 /* Output to assembler file text saying following lines
2694 may contain character constants, extra white space, comments, etc. */
2695
2696 #ifndef ASM_APP_ON
2697 #define ASM_APP_ON " #APP\n"
2698 #endif
2699
2700 /* Output to assembler file text saying following lines
2701 no longer contain unusual constructs. */
2702
2703 #ifndef ASM_APP_OFF
2704 #define ASM_APP_OFF " #NO_APP\n"
2705 #endif
2706
2707 #define REGISTER_NAMES \
2708 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2709 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2710 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2711 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2712 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2713 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2714 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2715 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2716 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2717 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2718 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2719 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2720 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2721 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2722 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2723 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2724 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2725 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2726 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2727 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2728 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2729 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2730 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2731 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2732
2733 /* List the "software" names for each register. Also list the numerical
2734 names for $fp and $sp. */
2735
2736 #define ADDITIONAL_REGISTER_NAMES \
2737 { \
2738 { "$29", 29 + GP_REG_FIRST }, \
2739 { "$30", 30 + GP_REG_FIRST }, \
2740 { "at", 1 + GP_REG_FIRST }, \
2741 { "v0", 2 + GP_REG_FIRST }, \
2742 { "v1", 3 + GP_REG_FIRST }, \
2743 { "a0", 4 + GP_REG_FIRST }, \
2744 { "a1", 5 + GP_REG_FIRST }, \
2745 { "a2", 6 + GP_REG_FIRST }, \
2746 { "a3", 7 + GP_REG_FIRST }, \
2747 { "t0", 8 + GP_REG_FIRST }, \
2748 { "t1", 9 + GP_REG_FIRST }, \
2749 { "t2", 10 + GP_REG_FIRST }, \
2750 { "t3", 11 + GP_REG_FIRST }, \
2751 { "t4", 12 + GP_REG_FIRST }, \
2752 { "t5", 13 + GP_REG_FIRST }, \
2753 { "t6", 14 + GP_REG_FIRST }, \
2754 { "t7", 15 + GP_REG_FIRST }, \
2755 { "s0", 16 + GP_REG_FIRST }, \
2756 { "s1", 17 + GP_REG_FIRST }, \
2757 { "s2", 18 + GP_REG_FIRST }, \
2758 { "s3", 19 + GP_REG_FIRST }, \
2759 { "s4", 20 + GP_REG_FIRST }, \
2760 { "s5", 21 + GP_REG_FIRST }, \
2761 { "s6", 22 + GP_REG_FIRST }, \
2762 { "s7", 23 + GP_REG_FIRST }, \
2763 { "t8", 24 + GP_REG_FIRST }, \
2764 { "t9", 25 + GP_REG_FIRST }, \
2765 { "k0", 26 + GP_REG_FIRST }, \
2766 { "k1", 27 + GP_REG_FIRST }, \
2767 { "gp", 28 + GP_REG_FIRST }, \
2768 { "sp", 29 + GP_REG_FIRST }, \
2769 { "fp", 30 + GP_REG_FIRST }, \
2770 { "ra", 31 + GP_REG_FIRST } \
2771 }
2772
2773 #define DBR_OUTPUT_SEQEND(STREAM) \
2774 do \
2775 { \
2776 /* Undo the effect of '%*'. */ \
2777 mips_pop_asm_switch (&mips_nomacro); \
2778 mips_pop_asm_switch (&mips_noreorder); \
2779 /* Emit a blank line after the delay slot for emphasis. */ \
2780 fputs ("\n", STREAM); \
2781 } \
2782 while (0)
2783
2784 /* The MIPS implementation uses some labels for its own purpose. The
2785 following lists what labels are created, and are all formed by the
2786 pattern $L[a-z].*. The machine independent portion of GCC creates
2787 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2788
2789 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2790 $Lb[0-9]+ Begin blocks for MIPS debug support
2791 $Lc[0-9]+ Label for use in s<xx> operation.
2792 $Le[0-9]+ End blocks for MIPS debug support */
2793
2794 #undef ASM_DECLARE_OBJECT_NAME
2795 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2796 mips_declare_object (STREAM, NAME, "", ":\n")
2797
2798 /* Globalizing directive for a label. */
2799 #define GLOBAL_ASM_OP "\t.globl\t"
2800
2801 /* This says how to define a global common symbol. */
2802
2803 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2804
2805 /* This says how to define a local common symbol (i.e., not visible to
2806 linker). */
2807
2808 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2809 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2810 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2811 #endif
2812
2813 /* This says how to output an external. It would be possible not to
2814 output anything and let undefined symbol become external. However
2815 the assembler uses length information on externals to allocate in
2816 data/sdata bss/sbss, thereby saving exec time. */
2817
2818 #undef ASM_OUTPUT_EXTERNAL
2819 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2820 mips_output_external(STREAM,DECL,NAME)
2821
2822 /* This is how to declare a function name. The actual work of
2823 emitting the label is moved to function_prologue, so that we can
2824 get the line number correctly emitted before the .ent directive,
2825 and after any .file directives. Define as empty so that the function
2826 is not declared before the .ent directive elsewhere. */
2827
2828 #undef ASM_DECLARE_FUNCTION_NAME
2829 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2830
2831 /* This is how to store into the string LABEL
2832 the symbol_ref name of an internal numbered label where
2833 PREFIX is the class of label and NUM is the number within the class.
2834 This is suitable for output with `assemble_name'. */
2835
2836 #undef ASM_GENERATE_INTERNAL_LABEL
2837 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2838 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2839
2840 /* Print debug labels as "foo = ." rather than "foo:" because they should
2841 represent a byte pointer rather than an ISA-encoded address. This is
2842 particularly important for code like:
2843
2844 $LFBxxx = .
2845 .cfi_startproc
2846 ...
2847 .section .gcc_except_table,...
2848 ...
2849 .uleb128 foo-$LFBxxx
2850
2851 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2852 likewise a byte pointer rather than an ISA-encoded address.
2853
2854 At the time of writing, this hook is not used for the function end
2855 label:
2856
2857 $LFExxx:
2858 .end foo
2859
2860 But this doesn't matter, because GAS doesn't treat a pre-.end label
2861 as a MIPS16 one anyway. */
2862
2863 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2864 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2865
2866 /* This is how to output an element of a case-vector that is absolute. */
2867
2868 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2869 fprintf (STREAM, "\t%s\t%sL%d\n", \
2870 ptr_mode == DImode ? ".dword" : ".word", \
2871 LOCAL_LABEL_PREFIX, \
2872 VALUE)
2873
2874 /* This is how to output an element of a case-vector. We can make the
2875 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2876 is supported. */
2877
2878 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2879 do { \
2880 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2881 { \
2882 if (GET_MODE (BODY) == HImode) \
2883 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2884 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2885 else \
2886 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2887 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2888 } \
2889 else if (TARGET_GPWORD) \
2890 fprintf (STREAM, "\t%s\t%sL%d\n", \
2891 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2892 LOCAL_LABEL_PREFIX, VALUE); \
2893 else if (TARGET_RTP_PIC) \
2894 { \
2895 /* Make the entry relative to the start of the function. */ \
2896 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2897 fprintf (STREAM, "\t%s\t%sL%d-", \
2898 Pmode == DImode ? ".dword" : ".word", \
2899 LOCAL_LABEL_PREFIX, VALUE); \
2900 assemble_name (STREAM, XSTR (fnsym, 0)); \
2901 fprintf (STREAM, "\n"); \
2902 } \
2903 else \
2904 fprintf (STREAM, "\t%s\t%sL%d\n", \
2905 ptr_mode == DImode ? ".dword" : ".word", \
2906 LOCAL_LABEL_PREFIX, VALUE); \
2907 } while (0)
2908
2909 /* This is how to output an assembler line
2910 that says to advance the location counter
2911 to a multiple of 2**LOG bytes. */
2912
2913 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2914 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2915
2916 /* This is how to output an assembler line to advance the location
2917 counter by SIZE bytes. */
2918
2919 #undef ASM_OUTPUT_SKIP
2920 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2921 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2922
2923 /* This is how to output a string. */
2924 #undef ASM_OUTPUT_ASCII
2925 #define ASM_OUTPUT_ASCII mips_output_ascii
2926
2927 \f
2928 /* Default to -G 8 */
2929 #ifndef MIPS_DEFAULT_GVALUE
2930 #define MIPS_DEFAULT_GVALUE 8
2931 #endif
2932
2933 /* Define the strings to put out for each section in the object file. */
2934 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2935 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2936
2937 #undef READONLY_DATA_SECTION_ASM_OP
2938 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2939 \f
2940 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2941 do \
2942 { \
2943 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2944 TARGET_64BIT ? "daddiu" : "addiu", \
2945 reg_names[STACK_POINTER_REGNUM], \
2946 reg_names[STACK_POINTER_REGNUM], \
2947 TARGET_64BIT ? "sd" : "sw", \
2948 reg_names[REGNO], \
2949 reg_names[STACK_POINTER_REGNUM]); \
2950 } \
2951 while (0)
2952
2953 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2954 do \
2955 { \
2956 mips_push_asm_switch (&mips_noreorder); \
2957 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2958 TARGET_64BIT ? "ld" : "lw", \
2959 reg_names[REGNO], \
2960 reg_names[STACK_POINTER_REGNUM], \
2961 TARGET_64BIT ? "daddu" : "addu", \
2962 reg_names[STACK_POINTER_REGNUM], \
2963 reg_names[STACK_POINTER_REGNUM]); \
2964 mips_pop_asm_switch (&mips_noreorder); \
2965 } \
2966 while (0)
2967
2968 /* How to start an assembler comment.
2969 The leading space is important (the mips native assembler requires it). */
2970 #ifndef ASM_COMMENT_START
2971 #define ASM_COMMENT_START " #"
2972 #endif
2973 \f
2974 #undef SIZE_TYPE
2975 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2976
2977 #undef PTRDIFF_TYPE
2978 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2979
2980 /* The minimum alignment of any expanded block move. */
2981 #define MIPS_MIN_MOVE_MEM_ALIGN 16
2982
2983 /* The maximum number of bytes that can be copied by one iteration of
2984 a movmemsi loop; see mips_block_move_loop. */
2985 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2986 (UNITS_PER_WORD * 4)
2987
2988 /* The maximum number of bytes that can be copied by a straight-line
2989 implementation of movmemsi; see mips_block_move_straight. We want
2990 to make sure that any loop-based implementation will iterate at
2991 least twice. */
2992 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2993 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2994
2995 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2996 values were determined experimentally by benchmarking with CSiBE.
2997 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2998 for o32 where we have to restore $gp afterwards as well as make an
2999 indirect call), but in practice, bumping this up higher for
3000 TARGET_ABICALLS doesn't make much difference to code size. */
3001
3002 #define MIPS_CALL_RATIO 8
3003
3004 /* Any loop-based implementation of movmemsi will have at least
3005 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3006 moves, so allow individual copies of fewer elements.
3007
3008 When movmemsi is not available, use a value approximating
3009 the length of a memcpy call sequence, so that move_by_pieces
3010 will generate inline code if it is shorter than a function call.
3011 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3012 we'll have to generate a load/store pair for each, halve the
3013 value of MIPS_CALL_RATIO to take that into account. */
3014
3015 #define MOVE_RATIO(speed) \
3016 (HAVE_movmemsi \
3017 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3018 : MIPS_CALL_RATIO / 2)
3019
3020 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3021 of the length of a memset call, but use the default otherwise. */
3022
3023 #define CLEAR_RATIO(speed)\
3024 ((speed) ? 15 : MIPS_CALL_RATIO)
3025
3026 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3027 optimizing for size adjust the ratio to account for the overhead of
3028 loading the constant and replicating it across the word. */
3029
3030 #define SET_RATIO(speed) \
3031 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3032 \f
3033 /* Since the bits of the _init and _fini function is spread across
3034 many object files, each potentially with its own GP, we must assume
3035 we need to load our GP. We don't preserve $gp or $ra, since each
3036 init/fini chunk is supposed to initialize $gp, and crti/crtn
3037 already take care of preserving $ra and, when appropriate, $gp. */
3038 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3039 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3040 asm (SECTION_OP "\n\
3041 .set push\n\
3042 .set nomips16\n\
3043 .set noreorder\n\
3044 bal 1f\n\
3045 nop\n\
3046 1: .cpload $31\n\
3047 .set reorder\n\
3048 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3049 jalr $25\n\
3050 .set pop\n\
3051 " TEXT_SECTION_ASM_OP);
3052 #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32)
3053 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3054 asm (SECTION_OP "\n\
3055 .set push\n\
3056 .set nomips16\n\
3057 .set noreorder\n\
3058 bal 1f\n\
3059 nop\n\
3060 1: .set reorder\n\
3061 .cpsetup $31, $2, 1b\n\
3062 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3063 jalr $25\n\
3064 .set pop\n\
3065 " TEXT_SECTION_ASM_OP);
3066 #elif (defined _ABI64 && _MIPS_SIM == _ABI64)
3067 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3068 asm (SECTION_OP "\n\
3069 .set push\n\
3070 .set nomips16\n\
3071 .set noreorder\n\
3072 bal 1f\n\
3073 nop\n\
3074 1: .set reorder\n\
3075 .cpsetup $31, $2, 1b\n\
3076 dla $25, " USER_LABEL_PREFIX #FUNC "\n\
3077 jalr $25\n\
3078 .set pop\n\
3079 " TEXT_SECTION_ASM_OP);
3080 #endif
3081
3082 #ifndef HAVE_AS_TLS
3083 #define HAVE_AS_TLS 0
3084 #endif
3085
3086 #ifndef HAVE_AS_NAN
3087 #define HAVE_AS_NAN 0
3088 #endif
3089
3090 #ifndef USED_FOR_TARGET
3091 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3092 struct mips_asm_switch {
3093 /* The FOO in the description above. */
3094 const char *name;
3095
3096 /* The current block nesting level, or 0 if we aren't in a block. */
3097 int nesting_level;
3098 };
3099
3100 extern const enum reg_class mips_regno_to_class[];
3101 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3102 extern const char *current_function_file; /* filename current function is in */
3103 extern int num_source_filenames; /* current .file # */
3104 extern struct mips_asm_switch mips_noreorder;
3105 extern struct mips_asm_switch mips_nomacro;
3106 extern struct mips_asm_switch mips_noat;
3107 extern int mips_dbx_regno[];
3108 extern int mips_dwarf_regno[];
3109 extern bool mips_split_p[];
3110 extern bool mips_split_hi_p[];
3111 extern bool mips_use_pcrel_pool_p[];
3112 extern const char *mips_lo_relocs[];
3113 extern const char *mips_hi_relocs[];
3114 extern enum processor mips_arch; /* which cpu to codegen for */
3115 extern enum processor mips_tune; /* which cpu to schedule for */
3116 extern int mips_isa; /* architectural level */
3117 extern int mips_isa_rev;
3118 extern const struct mips_cpu_info *mips_arch_info;
3119 extern const struct mips_cpu_info *mips_tune_info;
3120 extern unsigned int mips_base_compression_flags;
3121 extern GTY(()) struct target_globals *mips16_globals;
3122 extern GTY(()) struct target_globals *micromips_globals;
3123
3124 /* Information about a function's frame layout. */
3125 struct GTY(()) mips_frame_info {
3126 /* The size of the frame in bytes. */
3127 HOST_WIDE_INT total_size;
3128
3129 /* The number of bytes allocated to variables. */
3130 HOST_WIDE_INT var_size;
3131
3132 /* The number of bytes allocated to outgoing function arguments. */
3133 HOST_WIDE_INT args_size;
3134
3135 /* The number of bytes allocated to the .cprestore slot, or 0 if there
3136 is no such slot. */
3137 HOST_WIDE_INT cprestore_size;
3138
3139 /* Bit X is set if the function saves or restores GPR X. */
3140 unsigned int mask;
3141
3142 /* Likewise FPR X. */
3143 unsigned int fmask;
3144
3145 /* Likewise doubleword accumulator X ($acX). */
3146 unsigned int acc_mask;
3147
3148 /* The number of GPRs, FPRs, doubleword accumulators and COP0
3149 registers saved. */
3150 unsigned int num_gp;
3151 unsigned int num_fp;
3152 unsigned int num_acc;
3153 unsigned int num_cop0_regs;
3154
3155 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
3156 save slots from the top of the frame, or zero if no such slots are
3157 needed. */
3158 HOST_WIDE_INT gp_save_offset;
3159 HOST_WIDE_INT fp_save_offset;
3160 HOST_WIDE_INT acc_save_offset;
3161 HOST_WIDE_INT cop0_save_offset;
3162
3163 /* Likewise, but giving offsets from the bottom of the frame. */
3164 HOST_WIDE_INT gp_sp_offset;
3165 HOST_WIDE_INT fp_sp_offset;
3166 HOST_WIDE_INT acc_sp_offset;
3167 HOST_WIDE_INT cop0_sp_offset;
3168
3169 /* Similar, but the value passed to _mcount. */
3170 HOST_WIDE_INT ra_fp_offset;
3171
3172 /* The offset of arg_pointer_rtx from the bottom of the frame. */
3173 HOST_WIDE_INT arg_pointer_offset;
3174
3175 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
3176 HOST_WIDE_INT hard_frame_pointer_offset;
3177 };
3178
3179 /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */
3180 enum mips_int_mask
3181 {
3182 INT_MASK_EIC = -1,
3183 INT_MASK_SW0 = 0,
3184 INT_MASK_SW1 = 1,
3185 INT_MASK_HW0 = 2,
3186 INT_MASK_HW1 = 3,
3187 INT_MASK_HW2 = 4,
3188 INT_MASK_HW3 = 5,
3189 INT_MASK_HW4 = 6,
3190 INT_MASK_HW5 = 7
3191 };
3192
3193 /* Enumeration to mark the existence of the shadow register set.
3194 SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack
3195 pointer. */
3196 enum mips_shadow_set
3197 {
3198 SHADOW_SET_NO,
3199 SHADOW_SET_YES,
3200 SHADOW_SET_INTSTACK
3201 };
3202
3203 struct GTY(()) machine_function {
3204 /* The next floating-point condition-code register to allocate
3205 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
3206 unsigned int next_fcc;
3207
3208 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
3209 rtx mips16_gp_pseudo_rtx;
3210
3211 /* The number of extra stack bytes taken up by register varargs.
3212 This area is allocated by the callee at the very top of the frame. */
3213 int varargs_size;
3214
3215 /* The current frame information, calculated by mips_compute_frame_info. */
3216 struct mips_frame_info frame;
3217
3218 /* The register to use as the function's global pointer, or INVALID_REGNUM
3219 if the function doesn't need one. */
3220 unsigned int global_pointer;
3221
3222 /* How many instructions it takes to load a label into $AT, or 0 if
3223 this property hasn't yet been calculated. */
3224 unsigned int load_label_num_insns;
3225
3226 /* True if mips_adjust_insn_length should ignore an instruction's
3227 hazard attribute. */
3228 bool ignore_hazard_length_p;
3229
3230 /* True if the whole function is suitable for .set noreorder and
3231 .set nomacro. */
3232 bool all_noreorder_p;
3233
3234 /* True if the function has "inflexible" and "flexible" references
3235 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
3236 and mips_cfun_has_flexible_gp_ref_p for details. */
3237 bool has_inflexible_gp_insn_p;
3238 bool has_flexible_gp_insn_p;
3239
3240 /* True if the function's prologue must load the global pointer
3241 value into pic_offset_table_rtx and store the same value in
3242 the function's cprestore slot (if any). Even if this value
3243 is currently false, we may decide to set it to true later;
3244 see mips_must_initialize_gp_p () for details. */
3245 bool must_initialize_gp_p;
3246
3247 /* True if the current function must restore $gp after any potential
3248 clobber. This value is only meaningful during the first post-epilogue
3249 split_insns pass; see mips_must_initialize_gp_p () for details. */
3250 bool must_restore_gp_when_clobbered_p;
3251
3252 /* True if this is an interrupt handler. */
3253 bool interrupt_handler_p;
3254
3255 /* Records the way in which interrupts should be masked. Only used if
3256 interrupts are not kept masked. */
3257 enum mips_int_mask int_mask;
3258
3259 /* Records if this is an interrupt handler that uses shadow registers. */
3260 enum mips_shadow_set use_shadow_register_set;
3261
3262 /* True if this is an interrupt handler that should keep interrupts
3263 masked. */
3264 bool keep_interrupts_masked_p;
3265
3266 /* True if this is an interrupt handler that should use DERET
3267 instead of ERET. */
3268 bool use_debug_exception_return_p;
3269
3270 /* True if at least one of the formal parameters to a function must be
3271 written to the frame header (probably so its address can be taken). */
3272 bool does_not_use_frame_header;
3273
3274 /* True if none of the functions that are called by this function need
3275 stack space allocated for their arguments. */
3276 bool optimize_call_stack;
3277
3278 /* True if one of the functions calling this function may not allocate
3279 a frame header. */
3280 bool callers_may_not_allocate_frame;
3281
3282 /* True if GCC stored callee saved registers in the frame header. */
3283 bool use_frame_header_for_callee_saved_regs;
3284 };
3285 #endif
3286
3287 /* Enable querying of DFA units. */
3288 #define CPU_UNITS_QUERY 1
3289
3290 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3291 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3292
3293 /* As on most targets, we want the .eh_frame section to be read-only where
3294 possible. And as on most targets, this means two things:
3295
3296 (a) Non-locally-binding pointers must have an indirect encoding,
3297 so that the addresses in the .eh_frame section itself become
3298 locally-binding.
3299
3300 (b) A shared library's .eh_frame section must encode locally-binding
3301 pointers in a relative (relocation-free) form.
3302
3303 However, MIPS has traditionally not allowed directives like:
3304
3305 .long x-.
3306
3307 in cases where "x" is in a different section, or is not defined in the
3308 same assembly file. We are therefore unable to emit the PC-relative
3309 form required by (b) at assembly time.
3310
3311 Fortunately, the linker is able to convert absolute addresses into
3312 PC-relative addresses on our behalf. Unfortunately, only certain
3313 versions of the linker know how to do this for indirect pointers,
3314 and for personality data. We must fall back on using writable
3315 .eh_frame sections for shared libraries if the linker does not
3316 support this feature. */
3317 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3318 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3319
3320 /* For switching between MIPS16 and non-MIPS16 modes. */
3321 #define SWITCHABLE_TARGET 1
3322
3323 /* Several named MIPS patterns depend on Pmode. These patterns have the
3324 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3325 Add the appropriate suffix to generator function NAME and invoke it
3326 with arguments ARGS. */
3327 #define PMODE_INSN(NAME, ARGS) \
3328 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3329
3330 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3331 need to change these from /lib and /usr/lib. */
3332 #if MIPS_ABI_DEFAULT == ABI_N32
3333 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3334 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3335 #elif MIPS_ABI_DEFAULT == ABI_64
3336 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3337 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3338 #endif
3339
3340 /* Load store bonding is not supported by micromips and fix_24k. The
3341 performance can be degraded for those targets. Hence, do not bond for
3342 micromips or fix_24k. */
3343 #define ENABLE_LD_ST_PAIRS \
3344 (TARGET_LOAD_STORE_PAIRS && (TUNE_P5600 || TUNE_I6400) \
3345 && !TARGET_MICROMIPS && !TARGET_FIX_24K)
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