| blob | 81f675cd06a8fd604304bcff306853bf06b81298 |
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
35 /* MIPS external variables defined in mips.c. */
37 /* comparison type */
43 CMP_MAX /* max comparison type */
44 };
46 /* types of delay slot */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
52 };
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
60 PROCESSOR_DEFAULT,
61 PROCESSOR_R3000,
62 PROCESSOR_R3900,
63 PROCESSOR_R6000,
64 PROCESSOR_R4000,
65 PROCESSOR_R4100,
66 PROCESSOR_R4300,
67 PROCESSOR_R4600,
68 PROCESSOR_R4650,
69 PROCESSOR_R5000,
70 PROCESSOR_R8000
71 };
73 /* Recast the cpu class to be the cpu attribute. */
74 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
76 /* Which ABI to use. These are constants because abi64.h must check their
77 value at preprocessing time.
79 ABI_32 (original 32, or o32), ABI_N32 (n32), ABI_64 (n64) are all
80 defined by SGI. ABI_O64 is o32 extended to work on a 64 bit machine. */
82 #define ABI_32 0
83 #define ABI_N32 1
84 #define ABI_64 2
85 #define ABI_EABI 3
86 #define ABI_O64 4
88 #ifndef MIPS_ABI_DEFAULT
89 /* We define this away so that there is no extra runtime cost if the target
90 doesn't support multiple ABIs. */
91 #define mips_abi ABI_32
92 #else
94 #endif
96 /* Whether to emit abicalls code sequences or not. */
99 MIPS_ABICALLS_NO,
100 MIPS_ABICALLS_YES
101 };
103 /* Recast the abicalls class to be the abicalls attribute. */
104 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
106 /* Which type of block move to do (whether or not the last store is
107 split out so it can fill a branch delay slot). */
112 BLOCK_MOVE_LAST /* generate just the last store */
113 };
166 /* Functions to change what output section we are using. */
171 /* Stubs for half-pic support if not OSF/1 reference platform. */
173 #ifndef HALF_PIC_P
174 #define HALF_PIC_P() 0
175 #define HALF_PIC_NUMBER_PTRS 0
176 #define HALF_PIC_NUMBER_REFS 0
177 #define HALF_PIC_ENCODE(DECL)
178 #define HALF_PIC_DECLARE(NAME)
180 #define HALF_PIC_ADDRESS_P(X) 0
181 #define HALF_PIC_PTR(X) X
182 #define HALF_PIC_FINISH(STREAM)
183 #endif
185 /* Macros to silence warnings about numbers being signed in traditional
186 C and unsigned in ISO C when compiled on 32-bit hosts. */
192 \f
193 /* Run-time compilation parameters selecting different hardware subsets. */
195 /* Macros used in the machine description to test the flags. */
197 /* Bits for real switches */
219 #define MASK_NO_CHECK_ZERO_DIV \
221 #define MASK_CHECK_RANGE_DIV \
223 #define MASK_UNINIT_CONST_IN_RODATA \
225 consts in rodata */
227 multiply-add operations. */
229 /* Debug switches, not documented */
241 /* Dummy switches used only in specs */
244 /* r4000 64 bit sizes */
245 #define TARGET_INT64 (target_flags & MASK_INT64)
246 #define TARGET_LONG64 (target_flags & MASK_LONG64)
247 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
248 #define TARGET_64BIT (target_flags & MASK_64BIT)
250 /* Mips vs. GNU linker */
251 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
253 /* Mips vs. GNU assembler */
254 #define TARGET_GAS (target_flags & MASK_GAS)
255 #define TARGET_MIPS_AS (!TARGET_GAS)
257 /* Debug Modes */
258 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
259 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
260 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
261 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
262 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
263 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
264 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
265 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
266 #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
267 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
269 /* Reg. Naming in .s ($21 vs. $a0) */
270 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
272 /* Optimize for Sdata/Sbss */
273 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
275 /* print program statistics */
276 #define TARGET_STATS (target_flags & MASK_STATS)
278 /* call memcpy instead of inline code */
279 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
281 /* .abicalls, etc from Pyramid V.4 */
282 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
284 /* OSF pic references to externs */
285 #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
287 /* software floating point */
288 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
289 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
291 /* always call through a register */
292 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
294 /* generate embedded PIC code;
295 requires gas. */
296 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
298 /* for embedded systems, optimize for
299 reduced RAM space instead of for
300 fastest code. */
301 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
303 /* always store uninitialized const
304 variables in rodata, requires
305 TARGET_EMBEDDED_DATA. */
306 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
308 /* generate big endian code. */
309 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
311 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
312 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
314 #define TARGET_MAD (target_flags & MASK_MAD)
316 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
318 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
320 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
321 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
323 /* This is true if we must enable the assembly language file switching
324 code. */
326 #define TARGET_FILE_SWITCHING \
327 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
329 /* We must disable the function end stabs when doing the file switching trick,
330 because the Lscope stabs end up in the wrong place, making it impossible
331 to debug the resulting code. */
332 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
334 /* Generate mips16 code */
335 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
337 /* Architecture target defines. */
338 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
339 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
340 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100)
341 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
343 /* Scheduling target defines. */
344 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
345 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
346 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
347 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
348 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
350 /* Macro to define tables used to set the flags.
351 This is a list in braces of pairs in braces,
352 each pair being { "NAME", VALUE }
353 where VALUE is the bits to set or minus the bits to clear.
354 An empty string NAME is used to identify the default VALUE. */
356 #define TARGET_SWITCHES \
357 { \
467 NULL}, \
469 NULL}, \
471 NULL}, \
473 NULL}, \
475 NULL}, \
477 NULL}, \
479 NULL}, \
481 NULL}, \
483 NULL}, \
485 NULL}, \
487 | TARGET_CPU_DEFAULT \
488 | TARGET_ENDIAN_DEFAULT), \
489 NULL}, \
490 }
492 /* Default target_flags if no switches are specified */
494 #ifndef TARGET_DEFAULT
495 #define TARGET_DEFAULT 0
496 #endif
498 #ifndef TARGET_CPU_DEFAULT
499 #define TARGET_CPU_DEFAULT 0
500 #endif
502 #ifndef TARGET_ENDIAN_DEFAULT
503 #ifndef DECSTATION
504 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
505 #else
506 #define TARGET_ENDIAN_DEFAULT 0
507 #endif
508 #endif
510 #ifndef MIPS_ISA_DEFAULT
511 #define MIPS_ISA_DEFAULT 1
512 #endif
514 #ifdef IN_LIBGCC2
515 #undef TARGET_64BIT
516 /* Make this compile time constant for libgcc2 */
517 #ifdef __mips64
518 #define TARGET_64BIT 1
519 #else
520 #define TARGET_64BIT 0
521 #endif
524 #ifndef MULTILIB_ENDIAN_DEFAULT
525 #if TARGET_ENDIAN_DEFAULT == 0
527 #else
529 #endif
530 #endif
532 #ifndef MULTILIB_ISA_DEFAULT
533 # if MIPS_ISA_DEFAULT == 1
535 # else
536 # if MIPS_ISA_DEFAULT == 2
538 # else
539 # if MIPS_ISA_DEFAULT == 3
541 # else
542 # if MIPS_ISA_DEFAULT == 4
544 # else
546 # endif
547 # endif
548 # endif
549 # endif
550 #endif
552 #ifndef MULTILIB_DEFAULTS
553 #define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
554 #endif
556 /* We must pass -EL to the linker by default for little endian embedded
557 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
558 linker will default to using big-endian output files. The OUTPUT_FORMAT
559 line must be in the linker script, otherwise -EB/-EL will not work. */
561 #ifndef ENDIAN_SPEC
562 #if TARGET_ENDIAN_DEFAULT == 0
564 #else
566 #endif
567 #endif
569 /* This macro is similar to `TARGET_SWITCHES' but defines names of
570 command options that have values. Its definition is an
571 initializer with a subgrouping for each command option.
573 Each subgrouping contains a string constant, that defines the
574 fixed part of the option name, and the address of a variable.
575 The variable, type `char *', is set to the variable part of the
576 given option if the fixed part matches. The actual option name
577 is made by appending `-m' to the specified name.
579 Here is an example which defines `-mshort-data-NUMBER'. If the
580 given option is `-mshort-data-512', the variable `m88k_short_data'
581 will be set to the string `"512"'.
583 extern char *m88k_short_data;
584 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
586 #define TARGET_OPTIONS \
587 { \
588 SUBTARGET_TARGET_OPTIONS \
602 NULL}, \
603 }
605 /* This is meant to be redefined in the host dependent files. */
606 #define SUBTARGET_TARGET_OPTIONS
608 #define GENERATE_BRANCHLIKELY (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)
610 /* Generate three-operand multiply instructions for both SImode and DImode. */
611 #define GENERATE_MULT3 (TARGET_MIPS3900 \
612 && !TARGET_MIPS16)
614 /* Macros to decide whether certain features are available or not,
615 depending on the instruction set architecture level. */
617 #define BRANCH_LIKELY_P() GENERATE_BRANCHLIKELY
618 #define HAVE_SQRT_P() (mips_isa != 1)
620 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
621 #define ISA_HAS_64BIT_REGS (mips_isa == 3 || mips_isa == 4 \
622 )
624 /* ISA has branch likely instructions (eg. mips2). */
625 /* Disable branchlikely for tx39 until compare rewrite. They haven't
626 been generated up to this point. */
627 #define ISA_HAS_BRANCHLIKELY (mips_isa != 1 \
630 /* ISA has the conditional move instructions introduced in mips4. */
631 #define ISA_HAS_CONDMOVE (mips_isa == 4 \
632 )
634 /* ISA has just the integer condition move instructions (movn,movz) */
635 #define ISA_HAS_INT_CONDMOVE 0
639 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
640 branch on CC, and move (both FP and non-FP) on CC. */
641 #define ISA_HAS_8CC (mips_isa == 4 \
642 )
645 /* This is a catch all for the other new mips4 instructions: indexed load and
646 indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
647 and the FP recip and recip sqrt instructions */
648 #define ISA_HAS_FP4 (mips_isa == 4 \
649 )
651 /* ISA has conditional trap instructions. */
652 #define ISA_HAS_COND_TRAP (mips_isa >= 2)
654 /* ISA has nmadd and nmsub instructions. */
655 #define ISA_HAS_NMADD_NMSUB (mips_isa == 4 \
656 )
658 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
659 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
660 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
661 target_flags, and -mgp64 sets MASK_64BIT.
663 Setting MASK_64BIT in target_flags will cause gcc to assume that
664 registers are 64 bits wide. int, long and void * will be 32 bit;
665 this may be changed with -mint64 or -mlong64.
667 The gen* programs link code that refers to MASK_64BIT. They don't
668 actually use the information in target_flags; they just refer to
669 it. */
670 \f
671 /* Switch Recognition by gcc.c. Add -G xx support */
673 #ifdef SWITCH_TAKES_ARG
674 #undef SWITCH_TAKES_ARG
675 #endif
677 #define SWITCH_TAKES_ARG(CHAR) \
680 /* Sometimes certain combinations of command options do not make sense
681 on a particular target machine. You can define a macro
682 `OVERRIDE_OPTIONS' to take account of this. This macro, if
683 defined, is executed once just after all the command options have
684 been parsed.
686 On the MIPS, it is used to handle -G. We also use it to set up all
687 of the tables referenced in the other macros. */
689 #define OVERRIDE_OPTIONS override_options ()
691 /* Zero or more C statements that may conditionally modify two
692 variables `fixed_regs' and `call_used_regs' (both of type `char
693 []') after they have been initialized from the two preceding
694 macros.
696 This is necessary in case the fixed or call-clobbered registers
697 depend on target flags.
699 You need not define this macro if it has no work to do.
701 If the usage of an entire class of registers depends on the target
702 flags, you may indicate this to GCC by using this macro to modify
703 `fixed_regs' and `call_used_regs' to 1 for each of the registers in
704 the classes which should not be used by GCC. Also define the macro
705 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
706 letter for a class that shouldn't be used.
708 (However, if this class is not included in `GENERAL_REGS' and all
709 of the insn patterns whose constraints permit this class are
710 controlled by target switches, then GCC will automatically avoid
711 using these registers when the target switches are opposed to
712 them.) */
714 #define CONDITIONAL_REGISTER_USAGE \
715 do \
716 { \
717 if (!TARGET_HARD_FLOAT) \
718 { \
719 int regno; \
720 \
721 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
722 fixed_regs[regno] = call_used_regs[regno] = 1; \
723 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
724 fixed_regs[regno] = call_used_regs[regno] = 1; \
725 } \
726 else if (! ISA_HAS_8CC) \
727 { \
728 int regno; \
729 \
730 /* We only have a single condition code register. We \
731 implement this by hiding all the condition code registers, \
733 for (regno = ST_REG_FIRST; regno <= ST_REG_LAST; regno++) \
734 fixed_regs[regno] = call_used_regs[regno] = 1; \
735 } \
736 /* In mips16 mode, we permit the $t temporary registers to be used \
737 for reload. We prohibit the unused $s registers, since they \
738 are caller saved, and saving them via a mips16 register would \
740 if (TARGET_MIPS16) \
741 { \
742 fixed_regs[18] = call_used_regs[18] = 1; \
743 fixed_regs[19] = call_used_regs[19] = 1; \
744 fixed_regs[20] = call_used_regs[20] = 1; \
745 fixed_regs[21] = call_used_regs[21] = 1; \
746 fixed_regs[22] = call_used_regs[22] = 1; \
747 fixed_regs[23] = call_used_regs[23] = 1; \
748 fixed_regs[26] = call_used_regs[26] = 1; \
749 fixed_regs[27] = call_used_regs[27] = 1; \
750 fixed_regs[30] = call_used_regs[30] = 1; \
751 } \
752 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
753 } \
754 while (0)
756 /* This is meant to be redefined in the host dependent files. */
757 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
759 /* Show we can debug even without a frame pointer. */
760 #define CAN_DEBUG_WITHOUT_FP
761 \f
762 /* Complain about missing specs and predefines that should be defined in each
763 of the target tm files to override the defaults. This is mostly a place-
764 holder until I can get each of the files updated [mm]. */
766 #if defined(OSF_OS) \
767 || defined(DECSTATION) \
768 || defined(SGI_TARGET) \
769 || defined(MIPS_NEWS) \
770 || defined(MIPS_SYSV) \
771 || defined(MIPS_SVR4) \
772 || defined(MIPS_BSD43)
774 #ifndef CPP_PREDEFINES
776 #endif
778 #ifndef LIB_SPEC
780 #endif
782 #ifndef STARTFILE_SPEC
784 #endif
786 #ifndef MACHINE_TYPE
788 #endif
789 #endif
791 /* Tell collect what flags to pass to nm. */
792 #ifndef NM_FLAGS
794 #endif
796 \f
797 /* Names to predefine in the preprocessor for this target machine. */
799 #ifndef CPP_PREDEFINES
801 -D_mips -D_unix -D_host_mips -D_MIPSEB -D_R3000 -D_SYSTYPE_BSD43 \
802 -Asystem=unix -Asystem=bsd -Acpu=mips -Amachine=mips"
803 #endif
805 /* Assembler specs. */
807 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
808 than gas. */
811 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
812 %{pipe: %e-pipe is not supported.} \
813 %{K} %(subtarget_mips_as_asm_spec)"
815 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
816 rather than gas. It may be overridden by subtargets. */
818 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
820 #endif
822 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
823 assembler. */
825 #define GAS_ASM_SPEC "%{march=*} %{mtune=*} %{mcpu=*} %{m4650} %{mmad:-m4650} %{m3900} %{v} %{mgp32} %{mgp64}"
827 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
828 GAS_ASM_SPEC as the default, depending upon the value of
829 TARGET_DEFAULT. */
831 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
832 /* GAS */
835 %{mmips-as: %(mips_as_asm_spec)} \
836 %{!mmips-as: %(gas_asm_spec)}"
841 %{!mgas: %(mips_as_asm_spec)} \
842 %{mgas: %(gas_asm_spec)}"
846 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
847 to the assembler. It may be overridden by subtargets. */
848 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
850 %{noasmopt:-O0} \
851 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
852 #endif
854 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
855 the assembler. It may be overridden by subtargets. */
856 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
858 %{g} %{g0} %{g1} %{g2} %{g3} \
859 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
860 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
861 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
862 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3}"
863 #endif
865 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
866 overridden by subtargets. */
868 #ifndef SUBTARGET_ASM_SPEC
870 #endif
872 /* ASM_SPEC is the set of arguments to pass to the assembler. */
874 #undef ASM_SPEC
876 %{!membedded-pic:%{G*}} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
877 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
878 %(subtarget_asm_optimizing_spec) \
879 %(subtarget_asm_debugging_spec) \
880 %{membedded-pic} \
881 %{mfix7000} \
882 %{mabi=32:-32}%{mabi=o32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
883 %(target_asm_spec) \
884 %(subtarget_asm_spec)"
886 /* Specify to run a post-processor, mips-tfile after the assembler
887 has run to stuff the mips debug information into the object file.
888 This is needed because the $#!%^ MIPS assembler provides no way
889 of specifying such information in the assembly file. If we are
890 cross compiling, disable mips-tfile unless the user specifies
891 -mmips-tfile. */
893 #ifndef ASM_FINAL_SPEC
894 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
895 /* GAS */
897 %{mmips-as: %{!mno-mips-tfile: \
899 %{K: -I %b.o~} \
900 %{!K: %{save-temps: -I %b.o~}} \
901 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
902 %{.s:%i} %{!.s:%g.s}}}"
904 #else
905 /* not GAS */
907 %{!mgas: %{!mno-mips-tfile: \
909 %{K: -I %b.o~} \
910 %{!K: %{save-temps: -I %b.o~}} \
911 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
912 %{.s:%i} %{!.s:%g.s}}}"
914 #endif
917 /* Redefinition of libraries used. Mips doesn't support normal
918 UNIX style profiling via calling _mcount. It does offer
919 profiling that samples the PC, so do what we can... */
921 #ifndef LIB_SPEC
923 #endif
925 /* Extra switches sometimes passed to the linker. */
926 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
927 will interpret it as a -b option. */
929 #ifndef LINK_SPEC
931 %(endian_spec) \
932 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} \
933 %{bestGnum} %{shared} %{non_shared}"
936 /* Specs for the compiler proper */
938 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
939 overridden by subtargets. */
940 #ifndef SUBTARGET_CC1_SPEC
942 #endif
944 /* Deal with historic options. */
945 #ifndef CC1_CPU_SPEC
947 %{!mcpu*: \
948 %{m3900:-march=r3900 -mips1 -mfp32 -mgp32 \
950 %{m4650:-march=r4650 -mmad -msingle-float \
952 #endif
954 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
955 /* Note, we will need to adjust the following if we ever find a MIPS variant
956 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
957 that show up in this case. */
959 #ifndef CC1_SPEC
961 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
962 %{mips1:-mfp32 -mgp32} %{mips2:-mfp32 -mgp32}\
963 %{mips3:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
964 %{mips4:%{!msingle-float:%{!m4650:-mfp64}} -mgp64} \
965 %{mfp64:%{msingle-float:%emay not use both -mfp64 and -msingle-float}} \
966 %{mfp64:%{m4650:%emay not use both -mfp64 and -m4650}} \
967 %{mint64|mlong64|mlong32:-mexplicit-type-size }\
968 %{mgp32: %{mfp64:%emay not use both -mgp32 and -mfp64} %{!mfp32: -mfp32}} \
969 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
970 %{pic-none: -mno-half-pic} \
971 %{pic-lib: -mhalf-pic} \
972 %{pic-extern: -mhalf-pic} \
973 %{pic-calls: -mhalf-pic} \
974 %{save-temps: } \
975 %(subtarget_cc1_spec) \
976 %(cc1_cpu_spec)"
977 #endif
979 /* Preprocessor specs. */
981 /* SUBTARGET_CPP_SIZE_SPEC defines SIZE_TYPE and PTRDIFF_TYPE. It may
982 be overridden by subtargets. */
984 #ifndef SUBTARGET_CPP_SIZE_SPEC
986 %{mlong64:%{!mips1:%{!mips2:-D__SIZE_TYPE__=long\\ unsigned\\ int -D__PTRDIFF_TYPE__=long\\ int}}} \
988 #endif
990 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
991 overridden by subtargets. */
992 #ifndef SUBTARGET_CPP_SPEC
994 #endif
996 /* If we're using 64bit longs, then we have to define __LONG_MAX__
997 correctly. Similarly for 64bit ints and __INT_MAX__. */
998 #ifndef LONG_MAX_SPEC
999 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_LONG64)
1001 #else
1003 #endif
1004 #endif
1006 /* Define appropriate macros for fpr register size. */
1007 #ifndef CPP_FPR_SPEC
1008 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_FLOAT64)
1010 #else
1012 #endif
1013 #endif
1015 /* For C++ we need to ensure that _LANGUAGE_C_PLUS_PLUS is defined independent
1016 of the source file extension. */
1017 #undef CPLUSPLUS_CPP_SPEC
1019 -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS \
1020 %(cpp) \
1021 "
1022 /* CPP_SPEC is the set of arguments to pass to the preprocessor. */
1024 #ifndef CPP_SPEC
1026 %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C -D__LANGUAGE_C -D_LANGUAGE_C} \
1027 %{.S|.s: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
1028 %{!.S: %{!.s: %{!.cc: %{!.cxx: %{!.cpp: %{!.cp: %{!.c++: %{!.C: %{!.m: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}}}}}}}}} \
1029 %(subtarget_cpp_size_spec) \
1030 %{mips3:-U__mips -D__mips=3 -D__mips64} \
1031 %{mips4:-U__mips -D__mips=4 -D__mips64} \
1032 %{mgp32:-U__mips64} %{mgp64:-D__mips64} \
1033 %{mfp32:-D__mips_fpr=32} %{mfp64:-D__mips_fpr=64} %{!mfp32: %{!mfp64: %{mgp32:-D__mips_fpr=32} %{!mgp32: %(cpp_fpr_spec)}}} \
1034 %{msingle-float:%{!msoft-float:-D__mips_single_float}} \
1035 %{m4650:%{!msoft-float:-D__mips_single_float}} \
1036 %{msoft-float:-D__mips_soft_float} \
1037 %{mabi=eabi:-D__mips_eabi} \
1038 %{mips16:%{!mno-mips16:-D__mips16}} \
1039 %{EB:-UMIPSEL -U_MIPSEL -U__MIPSEL -U__MIPSEL__ -D_MIPSEB -D__MIPSEB -D__MIPSEB__ %{!ansi:-DMIPSEB}} \
1040 %{EL:-UMIPSEB -U_MIPSEB -U__MIPSEB -U__MIPSEB__ -D_MIPSEL -D__MIPSEL -D__MIPSEL__ %{!ansi:-DMIPSEL}} \
1041 %(long_max_spec) \
1042 %(subtarget_cpp_spec) "
1043 #endif
1045 /* This macro defines names of additional specifications to put in the specs
1046 that can be used in various specifications like CC1_SPEC. Its definition
1047 is an initializer with a subgrouping for each command option.
1049 Each subgrouping contains a string constant, that defines the
1050 specification name, and a string constant that used by the GNU CC driver
1051 program.
1053 Do not define this macro if it does not need to do anything. */
1055 #define EXTRA_SPECS \
1070 SUBTARGET_EXTRA_SPECS
1072 #ifndef SUBTARGET_EXTRA_SPECS
1073 #define SUBTARGET_EXTRA_SPECS
1074 #endif
1076 /* If defined, this macro is an additional prefix to try after
1077 `STANDARD_EXEC_PREFIX'. */
1079 #ifndef MD_EXEC_PREFIX
1081 #endif
1083 #ifndef MD_STARTFILE_PREFIX
1085 #endif
1087 \f
1088 /* Print subsidiary information on the compiler version in use. */
1092 #ifndef MACHINE_TYPE
1094 #endif
1096 #ifndef TARGET_VERSION_INTERNAL
1097 #define TARGET_VERSION_INTERNAL(STREAM) \
1099 #endif
1101 #ifndef TARGET_VERSION
1102 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1103 #endif
1105 \f
1111 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1112 #endif
1114 /* By default, turn on GDB extensions. */
1115 #define DEFAULT_GDB_EXTENSIONS 1
1117 /* If we are passing smuggling stabs through the MIPS ECOFF object
1118 format, put a comment in front of the .stab<x> operation so
1119 that the MIPS assembler does not choke. The mips-tfile program
1120 will correctly put the stab into the object file. */
1126 /* Local compiler-generated symbols must have a prefix that the assembler
1127 understands. By default, this is $, although some targets (e.g.,
1128 NetBSD-ELF) need to override this. */
1130 #ifndef LOCAL_LABEL_PREFIX
1132 #endif
1134 /* By default on the mips, external symbols do not have an underscore
1135 prepended, but some targets (e.g., NetBSD) require this. */
1137 #ifndef USER_LABEL_PREFIX
1139 #endif
1141 /* Forward references to tags are allowed. */
1142 #define SDB_ALLOW_FORWARD_REFERENCES
1144 /* Unknown tags are also allowed. */
1145 #define SDB_ALLOW_UNKNOWN_REFERENCES
1147 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1148 since the length can run past this up to a continuation point. */
1149 #undef DBX_CONTIN_LENGTH
1150 #define DBX_CONTIN_LENGTH 1500
1152 /* How to renumber registers for dbx and gdb. */
1153 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1155 /* The mapping from gcc register number to DWARF 2 CFA column number.
1156 This mapping does not allow for tracking register 0, since SGI's broken
1157 dwarf reader thinks column 0 is used for the frame address, but since
1158 register 0 is fixed this is not a problem. */
1159 #define DWARF_FRAME_REGNUM(REG) \
1160 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1162 /* The DWARF 2 CFA column which tracks the return address. */
1163 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1165 /* Before the prologue, RA lives in r31. */
1166 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1168 /* Describe how we implement __builtin_eh_return. */
1169 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1170 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1172 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1173 The default for this in 64-bit mode is 8, which causes problems with
1174 SFmode register saves. */
1175 #define DWARF_CIE_DATA_ALIGNMENT 4
1177 /* Overrides for the COFF debug format. */
1178 #define PUT_SDB_SCL(a) \
1179 do { \
1180 extern FILE *asm_out_text_file; \
1182 } while (0)
1184 #define PUT_SDB_INT_VAL(a) \
1185 do { \
1186 extern FILE *asm_out_text_file; \
1188 } while (0)
1190 #define PUT_SDB_VAL(a) \
1191 do { \
1192 extern FILE *asm_out_text_file; \
1194 output_addr_const (asm_out_text_file, (a)); \
1196 } while (0)
1198 #define PUT_SDB_DEF(a) \
1199 do { \
1200 extern FILE *asm_out_text_file; \
1203 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1205 } while (0)
1207 #define PUT_SDB_PLAIN_DEF(a) \
1208 do { \
1209 extern FILE *asm_out_text_file; \
1212 } while (0)
1214 #define PUT_SDB_ENDEF \
1215 do { \
1216 extern FILE *asm_out_text_file; \
1218 } while (0)
1220 #define PUT_SDB_TYPE(a) \
1221 do { \
1222 extern FILE *asm_out_text_file; \
1224 } while (0)
1226 #define PUT_SDB_SIZE(a) \
1227 do { \
1228 extern FILE *asm_out_text_file; \
1230 } while (0)
1232 #define PUT_SDB_DIM(a) \
1233 do { \
1234 extern FILE *asm_out_text_file; \
1236 } while (0)
1238 #ifndef PUT_SDB_START_DIM
1239 #define PUT_SDB_START_DIM \
1240 do { \
1241 extern FILE *asm_out_text_file; \
1243 } while (0)
1244 #endif
1246 #ifndef PUT_SDB_NEXT_DIM
1247 #define PUT_SDB_NEXT_DIM(a) \
1248 do { \
1249 extern FILE *asm_out_text_file; \
1251 } while (0)
1252 #endif
1254 #ifndef PUT_SDB_LAST_DIM
1255 #define PUT_SDB_LAST_DIM(a) \
1256 do { \
1257 extern FILE *asm_out_text_file; \
1259 } while (0)
1260 #endif
1262 #define PUT_SDB_TAG(a) \
1263 do { \
1264 extern FILE *asm_out_text_file; \
1266 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1268 } while (0)
1270 /* For block start and end, we create labels, so that
1271 later we can figure out where the correct offset is.
1272 The normal .ent/.end serve well enough for functions,
1273 so those are just commented out. */
1275 #define PUT_SDB_BLOCK_START(LINE) \
1276 do { \
1277 extern FILE *asm_out_text_file; \
1278 fprintf (asm_out_text_file, \
1280 LOCAL_LABEL_PREFIX, \
1281 sdb_label_count, \
1283 LOCAL_LABEL_PREFIX, \
1284 sdb_label_count, \
1285 (LINE)); \
1286 sdb_label_count++; \
1287 } while (0)
1289 #define PUT_SDB_BLOCK_END(LINE) \
1290 do { \
1291 extern FILE *asm_out_text_file; \
1292 fprintf (asm_out_text_file, \
1294 LOCAL_LABEL_PREFIX, \
1295 sdb_label_count, \
1297 LOCAL_LABEL_PREFIX, \
1298 sdb_label_count, \
1299 (LINE)); \
1300 sdb_label_count++; \
1301 } while (0)
1303 #define PUT_SDB_FUNCTION_START(LINE)
1305 #define PUT_SDB_FUNCTION_END(LINE) \
1306 do { \
1307 extern FILE *asm_out_text_file; \
1308 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1309 } while (0)
1311 #define PUT_SDB_EPILOGUE_END(NAME)
1313 #define PUT_SDB_SRC_FILE(FILENAME) \
1314 do { \
1315 extern FILE *asm_out_text_file; \
1316 output_file_directive (asm_out_text_file, (FILENAME)); \
1317 } while (0)
1319 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1322 /* Correct the offset of automatic variables and arguments. Note that
1323 the MIPS debug format wants all automatic variables and arguments
1324 to be in terms of the virtual frame pointer (stack pointer before
1325 any adjustment in the function), while the MIPS 3.0 linker wants
1326 the frame pointer to be the stack pointer after the initial
1327 adjustment. */
1329 #define DEBUGGER_AUTO_OFFSET(X) \
1330 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1331 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1332 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1334 /* Tell collect that the object format is ECOFF */
1335 #ifndef OBJECT_FORMAT_ROSE
1338 #endif
1339 \f
1340 /* Target machine storage layout */
1342 /* Define in order to support both big and little endian float formats
1343 in the same gcc binary. */
1344 #define REAL_ARITHMETIC
1346 /* Define this if most significant bit is lowest numbered
1347 in instructions that operate on numbered bit-fields.
1348 */
1349 #define BITS_BIG_ENDIAN 0
1351 /* Define this if most significant byte of a word is the lowest numbered. */
1352 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1354 /* Define this if most significant word of a multiword number is the lowest. */
1355 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1357 /* Define this to set the endianness to use in libgcc2.c, which can
1358 not depend on target_flags. */
1359 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1360 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1361 #else
1362 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1363 #endif
1365 /* Number of bits in an addressable storage unit */
1366 #define BITS_PER_UNIT 8
1368 /* Width in bits of a "word", which is the contents of a machine register.
1369 Note that this is not necessarily the width of data type `int';
1370 if using 16-bit ints on a 68000, this would still be 32.
1371 But on a machine with 16-bit registers, this would be 16. */
1372 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
1373 #define MAX_BITS_PER_WORD 64
1375 /* Width of a word, in units (bytes). */
1376 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1377 #define MIN_UNITS_PER_WORD 4
1379 /* For MIPS, width of a floating point register. */
1380 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1382 /* A C expression for the size in bits of the type `int' on the
1383 target machine. If you don't define this, the default is one
1384 word. */
1385 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1386 #define MAX_INT_TYPE_SIZE 64
1388 /* Tell the preprocessor the maximum size of wchar_t. */
1389 #ifndef MAX_WCHAR_TYPE_SIZE
1390 #ifndef WCHAR_TYPE_SIZE
1391 #define MAX_WCHAR_TYPE_SIZE MAX_INT_TYPE_SIZE
1392 #endif
1393 #endif
1395 /* A C expression for the size in bits of the type `short' on the
1396 target machine. If you don't define this, the default is half a
1397 word. (If this would be less than one storage unit, it is
1398 rounded up to one unit.) */
1399 #define SHORT_TYPE_SIZE 16
1401 /* A C expression for the size in bits of the type `long' on the
1402 target machine. If you don't define this, the default is one
1403 word. */
1404 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1405 #define MAX_LONG_TYPE_SIZE 64
1407 /* A C expression for the size in bits of the type `long long' on the
1408 target machine. If you don't define this, the default is two
1409 words. */
1410 #define LONG_LONG_TYPE_SIZE 64
1412 /* A C expression for the size in bits of the type `char' on the
1413 target machine. If you don't define this, the default is one
1414 quarter of a word. (If this would be less than one storage unit,
1415 it is rounded up to one unit.) */
1416 #define CHAR_TYPE_SIZE BITS_PER_UNIT
1418 /* A C expression for the size in bits of the type `float' on the
1419 target machine. If you don't define this, the default is one
1420 word. */
1421 #define FLOAT_TYPE_SIZE 32
1423 /* A C expression for the size in bits of the type `double' on the
1424 target machine. If you don't define this, the default is two
1425 words. */
1426 #define DOUBLE_TYPE_SIZE 64
1428 /* A C expression for the size in bits of the type `long double' on
1429 the target machine. If you don't define this, the default is two
1430 words. */
1431 #define LONG_DOUBLE_TYPE_SIZE 64
1433 /* Width in bits of a pointer.
1434 See also the macro `Pmode' defined below. */
1435 #ifndef POINTER_SIZE
1436 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1437 #endif
1439 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1440 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1442 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1443 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)
1445 /* Allocation boundary (in *bits*) for the code of a function. */
1446 #define FUNCTION_BOUNDARY 32
1448 /* Alignment of field after `int : 0' in a structure. */
1449 #define EMPTY_FIELD_BOUNDARY 32
1451 /* Every structure's size must be a multiple of this. */
1452 /* 8 is observed right on a DECstation and on riscos 4.02. */
1453 #define STRUCTURE_SIZE_BOUNDARY 8
1455 /* There is no point aligning anything to a rounder boundary than this. */
1456 #define BIGGEST_ALIGNMENT 64
1458 /* Set this nonzero if move instructions will actually fail to work
1459 when given unaligned data. */
1460 #define STRICT_ALIGNMENT 1
1462 /* Define this if you wish to imitate the way many other C compilers
1463 handle alignment of bitfields and the structures that contain
1464 them.
1466 The behavior is that the type written for a bitfield (`int',
1467 `short', or other integer type) imposes an alignment for the
1468 entire structure, as if the structure really did contain an
1469 ordinary field of that type. In addition, the bitfield is placed
1470 within the structure so that it would fit within such a field,
1471 not crossing a boundary for it.
1473 Thus, on most machines, a bitfield whose type is written as `int'
1474 would not cross a four-byte boundary, and would force four-byte
1475 alignment for the whole structure. (The alignment used may not
1476 be four bytes; it is controlled by the other alignment
1477 parameters.)
1479 If the macro is defined, its definition should be a C expression;
1480 a nonzero value for the expression enables this behavior. */
1482 #define PCC_BITFIELD_TYPE_MATTERS 1
1484 /* If defined, a C expression to compute the alignment given to a
1485 constant that is being placed in memory. CONSTANT is the constant
1486 and ALIGN is the alignment that the object would ordinarily have.
1487 The value of this macro is used instead of that alignment to align
1488 the object.
1490 If this macro is not defined, then ALIGN is used.
1492 The typical use of this macro is to increase alignment for string
1493 constants to be word aligned so that `strcpy' calls that copy
1494 constants can be done inline. */
1496 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1497 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1498 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1500 /* If defined, a C expression to compute the alignment for a static
1501 variable. TYPE is the data type, and ALIGN is the alignment that
1502 the object would ordinarily have. The value of this macro is used
1503 instead of that alignment to align the object.
1505 If this macro is not defined, then ALIGN is used.
1507 One use of this macro is to increase alignment of medium-size
1508 data to make it all fit in fewer cache lines. Another is to
1509 cause character arrays to be word-aligned so that `strcpy' calls
1510 that copy constants to character arrays can be done inline. */
1512 #undef DATA_ALIGNMENT
1513 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1514 ((((ALIGN) < BITS_PER_WORD) \
1515 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1516 || TREE_CODE (TYPE) == UNION_TYPE \
1517 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1520 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1522 #define PAD_VARARGS_DOWN (TARGET_64BIT ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1524 /* Define this macro if an argument declared as `char' or `short' in a
1525 prototype should actually be passed as an `int'. In addition to
1526 avoiding errors in certain cases of mismatch, it also makes for
1527 better code on certain machines. */
1529 #define PROMOTE_PROTOTYPES 1
1531 /* Define if operations between registers always perform the operation
1532 on the full register even if a narrower mode is specified. */
1533 #define WORD_REGISTER_OPERATIONS
1535 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1536 will either zero-extend or sign-extend. The value of this macro should
1537 be the code that says which one of the two operations is implicitly
1538 done, NIL if none.
1540 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1541 moves. All other referces are zero extended. */
1542 #define LOAD_EXTEND_OP(MODE) \
1543 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1544 ? SIGN_EXTEND : ZERO_EXTEND)
1546 /* Define this macro if it is advisable to hold scalars in registers
1547 in a wider mode than that declared by the program. In such cases,
1548 the value is constrained to be within the bounds of the declared
1549 type, but kept valid in the wider mode. The signedness of the
1550 extension may differ from that of the type.
1552 We promote any value smaller than SImode up to SImode. We don't
1553 want to promote to DImode when in 64 bit mode, because that would
1554 prevent us from using the faster SImode multiply and divide
1555 instructions. */
1557 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1558 if (GET_MODE_CLASS (MODE) == MODE_INT \
1559 && GET_MODE_SIZE (MODE) < 4) \
1560 (MODE) = SImode;
1562 /* Define this if function arguments should also be promoted using the above
1563 procedure. */
1565 #define PROMOTE_FUNCTION_ARGS
1567 /* Likewise, if the function return value is promoted. */
1569 #define PROMOTE_FUNCTION_RETURN
1570 \f
1571 /* Standard register usage. */
1573 /* Number of actual hardware registers.
1574 The hardware registers are assigned numbers for the compiler
1575 from 0 to just below FIRST_PSEUDO_REGISTER.
1576 All registers that the compiler knows about must be given numbers,
1577 even those that are not normally considered general registers.
1579 On the Mips, we have 32 integer registers, 32 floating point
1580 registers, 8 condition code registers, and the special registers
1581 hi, lo, hilo, and rap. The 8 condition code registers are only
1582 used if mips_isa >= 4. The hilo register is only used in 64 bit
1583 mode. It represents a 64 bit value stored as two 32 bit values in
1584 the hi and lo registers; this is the result of the mult
1585 instruction. rap is a pointer to the stack where the return
1586 address reg ($31) was stored. This is needed for C++ exception
1587 handling. */
1589 #define FIRST_PSEUDO_REGISTER 76
1591 /* 1 for registers that have pervasive standard uses
1592 and are not available for the register allocator.
1594 On the MIPS, see conventions, page D-2 */
1596 #define FIXED_REGISTERS \
1597 { \
1598 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1599 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1600 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1601 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1602 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
1603 }
1606 /* 1 for registers not available across function calls.
1607 These must include the FIXED_REGISTERS and also any
1608 registers that can be used without being saved.
1609 The latter must include the registers where values are returned
1610 and the register where structure-value addresses are passed.
1611 Aside from that, you can include as many other registers as you like. */
1613 #define CALL_USED_REGISTERS \
1614 { \
1615 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1616 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1617 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1618 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1619 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1620 }
1623 /* Internal macros to classify a register number as to whether it's a
1624 general purpose register, a floating point register, a
1625 multiply/divide register, or a status register. */
1627 #define GP_REG_FIRST 0
1628 #define GP_REG_LAST 31
1629 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1630 #define GP_DBX_FIRST 0
1632 #define FP_REG_FIRST 32
1633 #define FP_REG_LAST 63
1634 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1635 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1637 #define MD_REG_FIRST 64
1638 #define MD_REG_LAST 66
1639 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1641 #define ST_REG_FIRST 67
1642 #define ST_REG_LAST 74
1643 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1645 #define RAP_REG_NUM 75
1647 #define AT_REGNUM (GP_REG_FIRST + 1)
1648 #define HI_REGNUM (MD_REG_FIRST + 0)
1649 #define LO_REGNUM (MD_REG_FIRST + 1)
1650 #define HILO_REGNUM (MD_REG_FIRST + 2)
1652 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1653 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1654 should be used instead. */
1655 #define FPSW_REGNUM ST_REG_FIRST
1657 #define GP_REG_P(REGNO) \
1658 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1659 #define M16_REG_P(REGNO) \
1660 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1661 #define FP_REG_P(REGNO) \
1662 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1663 #define MD_REG_P(REGNO) \
1664 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1665 #define ST_REG_P(REGNO) \
1666 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1668 /* Return number of consecutive hard regs needed starting at reg REGNO
1669 to hold something of mode MODE.
1670 This is ordinarily the length in words of a value of mode MODE
1671 but can be less for certain modes in special long registers.
1673 On the MIPS, all general registers are one word long. Except on
1674 the R4000 with the FR bit set, the floating point uses register
1675 pairs, with the second register not being allocable. */
1677 #define HARD_REGNO_NREGS(REGNO, MODE) \
1678 (! FP_REG_P (REGNO) \
1679 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1680 : ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG))
1682 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1683 MODE. In 32 bit mode, require that DImode and DFmode be in even
1684 registers. For DImode, this makes some of the insns easier to
1685 write, since you don't have to worry about a DImode value in
1686 registers 3 & 4, producing a result in 4 & 5.
1688 To make the code simpler HARD_REGNO_MODE_OK now just references an
1689 array built in override_options. Because machmodes.h is not yet
1690 included before this file is processed, the MODE bound can't be
1691 expressed here. */
1695 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1696 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1698 /* Value is 1 if it is a good idea to tie two pseudo registers
1699 when one has mode MODE1 and one has mode MODE2.
1700 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1701 for any hard reg, then this must be 0 for correct output. */
1702 #define MODES_TIEABLE_P(MODE1, MODE2) \
1703 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1704 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1705 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1706 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1708 /* MIPS pc is not overloaded on a register. */
1709 /* #define PC_REGNUM xx */
1711 /* Register to use for pushing function arguments. */
1712 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1714 /* Offset from the stack pointer to the first available location. Use
1715 the default value zero. */
1716 /* #define STACK_POINTER_OFFSET 0 */
1718 /* Base register for access to local variables of the function. We
1719 pretend that the frame pointer is $1, and then eliminate it to
1720 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1721 a fixed register, and will not be used for anything else. */
1722 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1724 /* Temporary scratch register for use by the assembler. */
1725 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1727 /* $30 is not available on the mips16, so we use $17 as the frame
1728 pointer. */
1729 #define HARD_FRAME_POINTER_REGNUM \
1730 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1732 /* Value should be nonzero if functions must have frame pointers.
1733 Zero means the frame pointer need not be set up (and parms
1734 may be accessed via the stack pointer) in functions that seem suitable.
1735 This is computed in `reload', in reload1.c. */
1736 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1738 /* Base register for access to arguments of the function. */
1739 #define ARG_POINTER_REGNUM GP_REG_FIRST
1741 /* Fake register that holds the address on the stack of the
1742 current function's return address. */
1743 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1745 /* Register in which static-chain is passed to a function. */
1746 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1748 /* If the structure value address is passed in a register, then
1749 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1750 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1752 /* If the structure value address is not passed in a register, define
1753 `STRUCT_VALUE' as an expression returning an RTX for the place
1754 where the address is passed. If it returns 0, the address is
1755 passed as an "invisible" first argument. */
1756 #define STRUCT_VALUE 0
1758 /* Mips registers used in prologue/epilogue code when the stack frame
1759 is larger than 32K bytes. These registers must come from the
1760 scratch register set, and not used for passing and returning
1761 arguments and any other information used in the calling sequence
1762 (such as pic). Must start at 12, since t0/t3 are parameter passing
1763 registers in the 64 bit ABI. */
1765 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1766 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1768 /* Define this macro if it is as good or better to call a constant
1769 function address than to call an address kept in a register. */
1770 #define NO_FUNCTION_CSE 1
1772 /* Define this macro if it is as good or better for a function to
1773 call itself with an explicit address than to call an address
1774 kept in a register. */
1775 #define NO_RECURSIVE_FUNCTION_CSE 1
1777 /* The register number of the register used to address a table of
1778 static data addresses in memory. In some cases this register is
1779 defined by a processor's "application binary interface" (ABI).
1780 When this macro is defined, RTL is generated for this register
1781 once, as with the stack pointer and frame pointer registers. If
1782 this macro is not defined, it is up to the machine-dependent
1783 files to allocate such a register (if necessary). */
1784 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1786 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1788 /* Initialize embedded_pic_fnaddr_rtx before RTL generation for
1789 each function. We used to do this in FINALIZE_PIC, but FINALIZE_PIC
1790 isn't always called for static inline functions. */
1791 #define INIT_EXPANDERS \
1792 do { \
1793 embedded_pic_fnaddr_rtx = NULL; \
1794 mips16_gp_pseudo_rtx = NULL; \
1795 } while (0)
1796 \f
1797 /* Define the classes of registers for register constraints in the
1798 machine description. Also define ranges of constants.
1800 One of the classes must always be named ALL_REGS and include all hard regs.
1801 If there is more than one class, another class must be named NO_REGS
1802 and contain no registers.
1804 The name GENERAL_REGS must be the name of a class (or an alias for
1805 another name such as ALL_REGS). This is the class of registers
1806 that is allowed by "g" or "r" in a register constraint.
1807 Also, registers outside this class are allocated only when
1808 instructions express preferences for them.
1810 The classes must be numbered in nondecreasing order; that is,
1811 a larger-numbered class must never be contained completely
1812 in a smaller-numbered class.
1814 For any two classes, it is very desirable that there be another
1815 class that represents their union. */
1817 enum reg_class
1818 {
1831 LO_AND_GR_REGS,
1832 HILO_AND_GR_REGS,
1835 LIM_REG_CLASSES /* max value + 1 */
1836 };
1838 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1840 #define GENERAL_REGS GR_REGS
1842 /* An initializer containing the names of the register classes as C
1843 string constants. These names are used in writing some of the
1844 debugging dumps. */
1846 #define REG_CLASS_NAMES \
1847 { \
1864 }
1866 /* An initializer containing the contents of the register classes,
1867 as integers which are bit masks. The Nth integer specifies the
1868 contents of class N. The way the integer MASK is interpreted is
1869 that register R is in the class if `MASK & (1 << R)' is 1.
1871 When the machine has more than 32 registers, an integer does not
1872 suffice. Then the integers are replaced by sub-initializers,
1873 braced groupings containing several integers. Each
1874 sub-initializer must be suitable as an initializer for the type
1875 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1877 #define REG_CLASS_CONTENTS \
1878 { \
1891 { 0xffffffff, 0x00000000, 0x00000002 }, \
1892 { 0xffffffff, 0x00000000, 0x00000004 }, \
1895 }
1898 /* A C expression whose value is a register class containing hard
1899 register REGNO. In general there is more that one such class;
1900 choose a class which is "minimal", meaning that no smaller class
1901 also contains the register. */
1905 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1907 /* A macro whose definition is the name of the class to which a
1908 valid base register must belong. A base register is one used in
1909 an address which is the register value plus a displacement. */
1911 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1913 /* A macro whose definition is the name of the class to which a
1914 valid index register must belong. An index register is one used
1915 in an address where its value is either multiplied by a scale
1916 factor or added to another register (as well as added to a
1917 displacement). */
1919 #define INDEX_REG_CLASS NO_REGS
1921 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1922 registers explicitly used in the rtl to be used as spill registers
1923 but prevents the compiler from extending the lifetime of these
1924 registers. */
1926 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1928 /* This macro is used later on in the file. */
1929 #define GR_REG_CLASS_P(CLASS) \
1930 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1931 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
1933 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1934 is the default value (allocate the registers in numeric order). We
1935 define it just so that we can override it for the mips16 target in
1936 ORDER_REGS_FOR_LOCAL_ALLOC. */
1938 #define REG_ALLOC_ORDER \
1939 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1940 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1941 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1942 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1943 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 \
1944 }
1946 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1947 to be rearranged based on a particular function. On the mips16, we
1948 want to allocate $24 (T_REG) before other registers for
1949 instructions for which it is possible. */
1951 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1953 /* REGISTER AND CONSTANT CLASSES */
1955 /* Get reg_class from a letter such as appears in the machine
1956 description.
1958 DEFINED REGISTER CLASSES:
1960 'd' General (aka integer) registers
1961 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1962 'y' General registers (in both mips16 and non mips16 mode)
1963 'e' mips16 non argument registers (M16_NA_REGS)
1964 't' mips16 temporary register ($24)
1965 'f' Floating point registers
1966 'h' Hi register
1967 'l' Lo register
1968 'x' Multiply/divide registers
1969 'a' HILO_REG
1970 'z' FP Status register
1971 'b' All registers */
1975 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1977 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1978 string can be used to stand for particular ranges of immediate
1979 operands. This macro defines what the ranges are. C is the
1980 letter, and VALUE is a constant value. Return 1 if VALUE is
1981 in the range specified by C. */
1983 /* For MIPS:
1985 `I' is used for the range of constants an arithmetic insn can
1986 actually contain (16 bits signed integers).
1988 `J' is used for the range which is just zero (ie, $r0).
1990 `K' is used for the range of constants a logical insn can actually
1991 contain (16 bit zero-extended integers).
1993 `L' is used for the range of constants that be loaded with lui
1994 (ie, the bottom 16 bits are zero).
1996 `M' is used for the range of constants that take two words to load
1997 (ie, not matched by `I', `K', and `L').
1999 `N' is used for negative 16 bit constants other than -65536.
2001 `O' is a 15 bit signed integer.
2003 `P' is used for positive 16 bit constants. */
2005 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2006 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2008 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2013 && (((VALUE) & ~2147483647) == 0 \
2014 || ((VALUE) & ~2147483647) == ~2147483647)) \
2016 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2017 && (((VALUE) & 0x0000ffff) != 0 \
2018 || (((VALUE) & ~2147483647) != 0 \
2019 && ((VALUE) & ~2147483647) != ~2147483647))) \
2023 : 0)
2025 /* Similar, but for floating constants, and defining letters G and H.
2026 Here VALUE is the CONST_DOUBLE rtx itself. */
2028 /* For Mips
2030 'G' : Floating point 0 */
2032 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2034 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2036 /* Letters in the range `Q' through `U' may be defined in a
2037 machine-dependent fashion to stand for arbitrary operand types.
2038 The machine description macro `EXTRA_CONSTRAINT' is passed the
2039 operand as its first argument and the constraint letter as its
2040 second operand.
2042 `Q' is for mips16 GP relative constants
2043 `R' is for memory references which take 1 word for the instruction.
2044 `S' is for references to extern items which are PIC for OSF/rose.
2045 `T' is for memory addresses that can be used to load two words. */
2047 #define EXTRA_CONSTRAINT(OP,CODE) \
2050 && mips16_gp_offset_p (OP)) \
2051 : (GET_CODE (OP) != MEM) ? FALSE \
2054 && HALF_PIC_ADDRESS_P (OP)) \
2055 : FALSE)
2057 /* Given an rtx X being reloaded into a reg required to be
2058 in class CLASS, return the class of reg to actually use.
2059 In general this is just CLASS; but on some machines
2060 in some cases it is preferable to use a more restrictive class. */
2062 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2063 ((CLASS) != ALL_REGS \
2064 ? (! TARGET_MIPS16 \
2065 ? (CLASS) \
2066 : ((CLASS) != GR_REGS \
2067 ? (CLASS) \
2068 : M16_REGS)) \
2069 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2070 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2071 ? (TARGET_SOFT_FLOAT \
2072 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2073 : FP_REGS) \
2074 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2075 || GET_MODE (X) == VOIDmode) \
2076 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2077 : (CLASS))))
2079 /* Certain machines have the property that some registers cannot be
2080 copied to some other registers without using memory. Define this
2081 macro on those machines to be a C expression that is non-zero if
2082 objects of mode MODE in registers of CLASS1 can only be copied to
2083 registers of class CLASS2 by storing a register of CLASS1 into
2084 memory and loading that memory location into a register of CLASS2.
2086 Do not define this macro if its value would always be zero. */
2088 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2089 ((!TARGET_DEBUG_H_MODE \
2090 && GET_MODE_CLASS (MODE) == MODE_INT \
2091 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2092 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2093 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2094 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2095 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2097 /* The HI and LO registers can only be reloaded via the general
2098 registers. Condition code registers can only be loaded to the
2099 general registers, and from the floating point registers. */
2101 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2102 mips_secondary_reload_class (CLASS, MODE, X, 1)
2103 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2104 mips_secondary_reload_class (CLASS, MODE, X, 0)
2106 /* Return the maximum number of consecutive registers
2107 needed to represent mode MODE in a register of class CLASS. */
2109 #define CLASS_UNITS(mode, size) \
2110 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
2112 #define CLASS_MAX_NREGS(CLASS, MODE) \
2113 ((CLASS) == FP_REGS \
2114 ? (TARGET_FLOAT64 \
2115 ? CLASS_UNITS (MODE, 8) \
2116 : 2 * CLASS_UNITS (MODE, 8)) \
2117 : CLASS_UNITS (MODE, UNITS_PER_WORD))
2119 /* If defined, gives a class of registers that cannot be used as the
2120 operand of a SUBREG that changes the mode of the object illegally. */
2122 #define CLASS_CANNOT_CHANGE_MODE \
2123 (TARGET_FLOAT64 && ! TARGET_64BIT ? FP_REGS : NO_REGS)
2125 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2127 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2128 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2129 \f
2130 /* Stack layout; function entry, exit and calling. */
2132 /* Define this if pushing a word on the stack
2133 makes the stack pointer a smaller address. */
2134 #define STACK_GROWS_DOWNWARD
2136 /* Define this if the nominal address of the stack frame
2137 is at the high-address end of the local variables;
2138 that is, each additional local variable allocated
2139 goes at a more negative offset in the frame. */
2140 /* #define FRAME_GROWS_DOWNWARD */
2142 /* Offset within stack frame to start allocating local variables at.
2143 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2144 first local allocated. Otherwise, it is the offset to the BEGINNING
2145 of the first local allocated. */
2146 #define STARTING_FRAME_OFFSET \
2147 (current_function_outgoing_args_size \
2148 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2150 /* Offset from the stack pointer register to an item dynamically
2151 allocated on the stack, e.g., by `alloca'.
2153 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2154 length of the outgoing arguments. The default is correct for most
2155 machines. See `function.c' for details.
2157 The MIPS ABI states that functions which dynamically allocate the
2158 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2159 we are trying to create a second frame pointer to the function, so
2160 allocate some stack space to make it happy.
2162 However, the linker currently complains about linking any code that
2163 dynamically allocates stack space, and there seems to be a bug in
2164 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2166 #if 0
2167 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2168 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2169 ? 4*UNITS_PER_WORD \
2170 : current_function_outgoing_args_size)
2171 #endif
2173 /* The return address for the current frame is in r31 is this is a leaf
2174 function. Otherwise, it is on the stack. It is at a variable offset
2175 from sp/fp/ap, so we define a fake hard register rap which is a
2176 poiner to the return address on the stack. This always gets eliminated
2177 during reload to be either the frame pointer or the stack pointer plus
2178 an offset. */
2180 /* ??? This definition fails for leaf functions. There is currently no
2181 general solution for this problem. */
2183 /* ??? There appears to be no way to get the return address of any previous
2184 frame except by disassembling instructions in the prologue/epilogue.
2185 So currently we support only the current frame. */
2187 #define RETURN_ADDR_RTX(count, frame) \
2188 ((count == 0) \
2189 ? gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM))\
2190 : (rtx) 0)
2192 /* Structure to be filled in by compute_frame_size with register
2193 save masks, and offsets for the current function. */
2195 struct mips_frame_info
2196 {
2213 };
2217 /* If defined, this macro specifies a table of register pairs used to
2218 eliminate unneeded registers that point into the stack frame. If
2219 it is not defined, the only elimination attempted by the compiler
2220 is to replace references to the frame pointer with references to
2221 the stack pointer.
2223 The definition of this macro is a list of structure
2224 initializations, each of which specifies an original and
2225 replacement register.
2227 On some machines, the position of the argument pointer is not
2228 known until the compilation is completed. In such a case, a
2229 separate hard register must be used for the argument pointer.
2230 This register can be eliminated by replacing it with either the
2231 frame pointer or the argument pointer, depending on whether or not
2232 the frame pointer has been eliminated.
2234 In this case, you might specify:
2235 #define ELIMINABLE_REGS \
2236 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2237 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2238 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2240 Note that the elimination of the argument pointer with the stack
2241 pointer is specified first since that is the preferred elimination.
2243 The eliminations to $17 are only used on the mips16. See the
2244 definition of HARD_FRAME_POINTER_REGNUM. */
2246 #define ELIMINABLE_REGS \
2247 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2248 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2249 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2250 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2251 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2252 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2253 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 31}, \
2254 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2255 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2256 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2258 /* A C expression that returns non-zero if the compiler is allowed to
2259 try to replace register number FROM-REG with register number
2260 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2261 defined, and will usually be the constant 1, since most of the
2262 cases preventing register elimination are things that the compiler
2263 already knows about.
2265 When not in mips16 and mips64, we can always eliminate to the
2266 frame pointer. We can eliminate to the stack pointer unless
2267 a frame pointer is needed. In mips16 mode, we need a frame
2268 pointer for a large frame; otherwise, reload may be unable
2269 to compute the address of a local variable, since there is
2270 no way to add a large constant to the stack pointer
2271 without using a temporary register.
2273 In mips16, for some instructions (eg lwu), we can't eliminate the
2274 frame pointer for the stack pointer. These instructions are
2275 only generated in TARGET_64BIT mode.
2276 */
2278 #define CAN_ELIMINATE(FROM, TO) \
2279 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM && (! leaf_function_p () \
2280 || (TO == GP_REG_FIRST + 31 && leaf_function_p))) \
2281 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2282 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2283 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2284 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2285 && (! TARGET_MIPS16 \
2286 || compute_frame_size (get_frame_size ()) < 32768)))))
2288 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It
2289 specifies the initial difference between the specified pair of
2290 registers. This macro must be defined if `ELIMINABLE_REGS' is
2291 defined. */
2293 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2294 { compute_frame_size (get_frame_size ()); \
2295 if (TARGET_MIPS16 && (FROM) == FRAME_POINTER_REGNUM \
2296 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2297 (OFFSET) = - current_function_outgoing_args_size; \
2298 else if ((FROM) == FRAME_POINTER_REGNUM) \
2299 (OFFSET) = 0; \
2300 else if (TARGET_MIPS16 && (FROM) == ARG_POINTER_REGNUM \
2301 && (TO) == HARD_FRAME_POINTER_REGNUM) \
2302 (OFFSET) = (current_frame_info.total_size \
2303 - current_function_outgoing_args_size \
2304 - ((mips_abi != ABI_32 \
2305 && mips_abi != ABI_O64 \
2306 && mips_abi != ABI_EABI) \
2307 ? current_function_pretend_args_size \
2308 : 0)); \
2309 else if ((FROM) == ARG_POINTER_REGNUM) \
2310 (OFFSET) = (current_frame_info.total_size \
2311 - ((mips_abi != ABI_32 \
2312 && mips_abi != ABI_O64 \
2313 && mips_abi != ABI_EABI) \
2314 ? current_function_pretend_args_size \
2315 : 0)); \
2316 /* Some ABIs store 64 bits to the stack, but Pmode is 32 bits, \
2318 else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM) \
2319 { \
2320 if (leaf_function_p ()) \
2321 (OFFSET) = 0; \
2322 else (OFFSET) = current_frame_info.gp_sp_offset \
2323 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT)) \
2324 * (BYTES_BIG_ENDIAN != 0)); \
2325 } \
2326 else \
2327 abort(); \
2328 }
2330 /* If we generate an insn to push BYTES bytes,
2331 this says how many the stack pointer really advances by.
2332 On the VAX, sp@- in a byte insn really pushes a word. */
2334 /* #define PUSH_ROUNDING(BYTES) 0 */
2336 /* If defined, the maximum amount of space required for outgoing
2337 arguments will be computed and placed into the variable
2338 `current_function_outgoing_args_size'. No space will be pushed
2339 onto the stack for each call; instead, the function prologue
2340 should increase the stack frame size by this amount.
2342 It is not proper to define both `PUSH_ROUNDING' and
2343 `ACCUMULATE_OUTGOING_ARGS'. */
2344 #define ACCUMULATE_OUTGOING_ARGS 1
2346 /* Offset from the argument pointer register to the first argument's
2347 address. On some machines it may depend on the data type of the
2348 function.
2350 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2351 the first argument's address.
2353 On the MIPS, we must skip the first argument position if we are
2354 returning a structure or a union, to account for its address being
2355 passed in $4. However, at the current time, this produces a compiler
2356 that can't bootstrap, so comment it out for now. */
2358 #if 0
2359 #define FIRST_PARM_OFFSET(FNDECL) \
2360 (FNDECL != 0 \
2361 && TREE_TYPE (FNDECL) != 0 \
2362 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2363 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2364 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2365 ? UNITS_PER_WORD \
2366 : 0)
2367 #else
2368 #define FIRST_PARM_OFFSET(FNDECL) 0
2369 #endif
2371 /* When a parameter is passed in a register, stack space is still
2372 allocated for it. For the MIPS, stack space must be allocated, cf
2373 Asm Lang Prog Guide page 7-8.
2375 BEWARE that some space is also allocated for non existing arguments
2376 in register. In case an argument list is of form GF used registers
2377 are a0 (a2,a3), but we should push over a1... */
2379 #define REG_PARM_STACK_SPACE(FNDECL) \
2380 ((MAX_ARGS_IN_REGISTERS*UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL))
2382 /* Define this if it is the responsibility of the caller to
2383 allocate the area reserved for arguments passed in registers.
2384 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2385 of this macro is to determine whether the space is included in
2386 `current_function_outgoing_args_size'. */
2387 #define OUTGOING_REG_PARM_STACK_SPACE
2389 /* Align stack frames on 64 bits (Double Word ). */
2390 #ifndef STACK_BOUNDARY
2391 #define STACK_BOUNDARY 64
2392 #endif
2394 /* Make sure 4 words are always allocated on the stack. */
2396 #ifndef STACK_ARGS_ADJUST
2397 #define STACK_ARGS_ADJUST(SIZE) \
2398 { \
2399 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2400 SIZE.constant = 4 * UNITS_PER_WORD; \
2401 }
2402 #endif
2404 \f
2405 /* A C expression that should indicate the number of bytes of its
2406 own arguments that a function pops on returning, or 0
2407 if the function pops no arguments and the caller must therefore
2408 pop them all after the function returns.
2410 FUNDECL is the declaration node of the function (as a tree).
2412 FUNTYPE is a C variable whose value is a tree node that
2413 describes the function in question. Normally it is a node of
2414 type `FUNCTION_TYPE' that describes the data type of the function.
2415 From this it is possible to obtain the data types of the value
2416 and arguments (if known).
2418 When a call to a library function is being considered, FUNTYPE
2419 will contain an identifier node for the library function. Thus,
2420 if you need to distinguish among various library functions, you
2421 can do so by their names. Note that "library function" in this
2422 context means a function used to perform arithmetic, whose name
2423 is known specially in the compiler and was not mentioned in the
2424 C code being compiled.
2426 STACK-SIZE is the number of bytes of arguments passed on the
2427 stack. If a variable number of bytes is passed, it is zero, and
2428 argument popping will always be the responsibility of the
2429 calling function. */
2431 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2434 /* Symbolic macros for the registers used to return integer and floating
2435 point values. */
2437 #define GP_RETURN (GP_REG_FIRST + 2)
2438 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2440 /* Symbolic macros for the first/last argument registers. */
2442 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2443 #define GP_ARG_LAST (GP_REG_FIRST + 7)
2444 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2445 #define FP_ARG_LAST (FP_REG_FIRST + 15)
2447 #define MAX_ARGS_IN_REGISTERS 4
2449 /* Define how to find the value returned by a library function
2450 assuming the value has mode MODE. Because we define
2451 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2452 PROMOTE_MODE does. */
2454 #define LIBCALL_VALUE(MODE) \
2455 gen_rtx (REG, \
2456 ((GET_MODE_CLASS (MODE) != MODE_INT \
2457 || GET_MODE_SIZE (MODE) >= 4) \
2458 ? (MODE) \
2459 : SImode), \
2460 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
2461 && (! TARGET_SINGLE_FLOAT \
2462 || GET_MODE_SIZE (MODE) <= 4)) \
2463 ? FP_RETURN \
2464 : GP_RETURN))
2466 /* Define how to find the value returned by a function.
2467 VALTYPE is the data type of the value (as a tree).
2468 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2469 otherwise, FUNC is 0. */
2471 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
2474 /* 1 if N is a possible register number for a function value.
2475 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2476 Currently, R2 and F0 are only implemented here (C has no complex type) */
2478 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2480 /* 1 if N is a possible register number for function argument passing.
2481 We have no FP argument registers when soft-float. When FP registers
2482 are 32 bits, we can't directly reference the odd numbered ones. */
2484 #define FUNCTION_ARG_REGNO_P(N) \
2485 (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
2486 || ((! TARGET_SOFT_FLOAT \
2487 && ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST) \
2488 && (TARGET_FLOAT64 || (0 == (N) % 2))) \
2489 && ! fixed_regs[N]))
2491 /* A C expression which can inhibit the returning of certain function
2492 values in registers, based on the type of value. A nonzero value says
2493 to return the function value in memory, just as large structures are
2494 always returned. Here TYPE will be a C expression of type
2495 `tree', representing the data type of the value.
2497 Note that values of mode `BLKmode' must be explicitly
2498 handled by this macro. Also, the option `-fpcc-struct-return'
2499 takes effect regardless of this macro. On most systems, it is
2500 possible to leave the macro undefined; this causes a default
2501 definition to be used, whose value is the constant 1 for BLKmode
2502 values, and 0 otherwise.
2504 GCC normally converts 1 byte structures into chars, 2 byte
2505 structs into shorts, and 4 byte structs into ints, and returns
2506 them this way. Defining the following macro overrides this,
2507 to give us MIPS cc compatibility. */
2509 #define RETURN_IN_MEMORY(TYPE) \
2510 (TYPE_MODE (TYPE) == BLKmode)
2511 \f
2512 /* A code distinguishing the floating point format of the target
2513 machine. There are three defined values: IEEE_FLOAT_FORMAT,
2514 VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
2516 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
2518 \f
2519 /* Define a data type for recording info about an argument list
2520 during the scan of that argument list. This data type should
2521 hold all necessary information about the function itself
2522 and about the args processed so far, enough to enable macros
2523 such as FUNCTION_ARG to determine where the next arg should go.
2525 On the mips16, we need to keep track of which floating point
2526 arguments were passed in general registers, but would have been
2527 passed in the FP regs if this were a 32 bit function, so that we
2528 can move them to the FP regs if we wind up calling a 32 bit
2529 function. We record this information in fp_code, encoded in base
2530 four. A zero digit means no floating point argument, a one digit
2531 means an SFmode argument, and a two digit means a DFmode argument,
2532 and a three digit is not used. The low order digit is the first
2533 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2534 an SFmode argument. ??? A more sophisticated approach will be
2535 needed if MIPS_ABI != ABI_32. */
2545 /* Adjustments made to args pass in regs. */
2546 /* ??? The size is doubled to work around a
2547 bug in the code that sets the adjustments
2548 in function_arg. */
2552 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2553 for a call to a function whose data type is FNTYPE.
2554 For a library call, FNTYPE is 0.
2556 */
2558 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2559 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2561 /* Update the data in CUM to advance over an argument
2562 of mode MODE and data type TYPE.
2563 (TYPE is null for libcalls where that information may not be available.) */
2565 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2566 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2568 /* Determine where to put an argument to a function.
2569 Value is zero to push the argument on the stack,
2570 or a hard register in which to store the argument.
2572 MODE is the argument's machine mode.
2573 TYPE is the data type of the argument (as a tree).
2574 This is null for libcalls where that information may
2575 not be available.
2576 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2577 the preceding args and about the function being called.
2578 NAMED is nonzero if this argument is a named parameter
2579 (otherwise it is an extra parameter matching an ellipsis). */
2581 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2582 function_arg( &CUM, MODE, TYPE, NAMED)
2584 /* For an arg passed partly in registers and partly in memory,
2585 this is the number of registers used.
2586 For args passed entirely in registers or entirely in memory, zero. */
2588 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2589 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2591 /* If defined, a C expression that gives the alignment boundary, in
2592 bits, of an argument with the specified mode and type. If it is
2593 not defined, `PARM_BOUNDARY' is used for all arguments. */
2595 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2596 (((TYPE) != 0) \
2597 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2598 ? PARM_BOUNDARY \
2599 : TYPE_ALIGN(TYPE)) \
2600 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2601 ? PARM_BOUNDARY \
2602 : GET_MODE_ALIGNMENT(MODE)))
2604 \f
2605 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2607 #define MUST_SAVE_REGISTER(regno) \
2608 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2609 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2610 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2612 /* ALIGN FRAMES on double word boundaries */
2613 #ifndef MIPS_STACK_ALIGN
2614 #define MIPS_STACK_ALIGN(LOC) (((LOC) + 7) & ~7)
2615 #endif
2617 \f
2618 /* Define the `__builtin_va_list' type for the ABI. */
2619 #define BUILD_VA_LIST_TYPE(VALIST) \
2620 (VALIST) = mips_build_va_list ()
2622 /* Implement `va_start' for varargs and stdarg. */
2623 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
2624 mips_va_start (stdarg, valist, nextarg)
2626 /* Implement `va_arg'. */
2627 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2628 mips_va_arg (valist, type)
2629 \f
2630 /* Output assembler code to FILE to increment profiler label # LABELNO
2631 for profiling a function entry. */
2633 #define FUNCTION_PROFILER(FILE, LABELNO) \
2634 { \
2635 if (TARGET_MIPS16) \
2640 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2642 fprintf (FILE, \
2645 reg_names[STACK_POINTER_REGNUM], \
2646 reg_names[STACK_POINTER_REGNUM], \
2647 Pmode == DImode ? 16 : 8); \
2650 }
2652 /* Define this macro if the code for function profiling should come
2653 before the function prologue. Normally, the profiling code comes
2654 after. */
2656 /* #define PROFILE_BEFORE_PROLOGUE */
2658 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2659 the stack pointer does not matter. The value is tested only in
2660 functions that have frame pointers.
2661 No definition is equivalent to always zero. */
2663 #define EXIT_IGNORE_STACK 1
2665 \f
2666 /* A C statement to output, on the stream FILE, assembler code for a
2667 block of data that contains the constant parts of a trampoline.
2668 This code should not include a label--the label is taken care of
2669 automatically. */
2671 #define TRAMPOLINE_TEMPLATE(STREAM) \
2672 { \
2676 if (Pmode == DImode) \
2677 { \
2680 } \
2681 else \
2682 { \
2685 } \
2689 if (Pmode == DImode) \
2690 { \
2693 } \
2694 else \
2695 { \
2698 } \
2699 }
2701 /* A C expression for the size in bytes of the trampoline, as an
2702 integer. */
2704 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2706 /* Alignment required for trampolines, in bits. */
2708 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2710 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2711 program and data caches. */
2713 #ifndef CACHE_FLUSH_FUNC
2715 #endif
2717 /* A C statement to initialize the variable parts of a trampoline.
2718 ADDR is an RTX for the address of the trampoline; FNADDR is an
2719 RTX for the address of the nested function; STATIC_CHAIN is an
2720 RTX for the static chain value that should be passed to the
2721 function when it is called. */
2723 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2724 { \
2725 rtx addr = ADDR; \
2726 if (Pmode == DImode) \
2727 { \
2728 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2729 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2730 } \
2731 else \
2732 { \
2733 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2734 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2735 } \
2736 \
2737 /* Flush both caches. We need to flush the data cache in case \
2740 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, CACHE_FLUSH_FUNC), \
2741 0, VOIDmode, 3, addr, Pmode, \
2742 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2743 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2744 }
2745 \f
2746 /* Addressing modes, and classification of registers for them. */
2748 /* #define HAVE_POST_INCREMENT 0 */
2749 /* #define HAVE_POST_DECREMENT 0 */
2751 /* #define HAVE_PRE_DECREMENT 0 */
2752 /* #define HAVE_PRE_INCREMENT 0 */
2754 /* These assume that REGNO is a hard or pseudo reg number.
2755 They give nonzero only if REGNO is a hard reg of the suitable class
2756 or a pseudo reg currently allocated to a suitable hard reg.
2757 These definitions are NOT overridden anywhere. */
2759 #define BASE_REG_P(regno, mode) \
2760 (TARGET_MIPS16 \
2761 ? (M16_REG_P (regno) \
2762 || (regno) == FRAME_POINTER_REGNUM \
2763 || (regno) == ARG_POINTER_REGNUM \
2764 || ((regno) == STACK_POINTER_REGNUM \
2765 && (GET_MODE_SIZE (mode) == 4 \
2766 || GET_MODE_SIZE (mode) == 8))) \
2767 : GP_REG_P (regno))
2769 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
2770 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
2771 (mode))
2773 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
2774 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
2776 #define REGNO_OK_FOR_INDEX_P(regno) 0
2777 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
2778 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
2780 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2781 and check its validity for a certain class.
2782 We have two alternate definitions for each of them.
2783 The usual definition accepts all pseudo regs; the other rejects them all.
2784 The symbol REG_OK_STRICT causes the latter definition to be used.
2786 Most source files want to accept pseudo regs in the hope that
2787 they will get allocated to the class that the insn wants them to be in.
2788 Some source files that are used after register allocation
2789 need to be strict. */
2791 #ifndef REG_OK_STRICT
2792 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2793 mips_reg_mode_ok_for_base_p (X, MODE, 0)
2794 #else
2795 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2796 mips_reg_mode_ok_for_base_p (X, MODE, 1)
2797 #endif
2799 #define REG_OK_FOR_INDEX_P(X) 0
2801 \f
2802 /* Maximum number of registers that can appear in a valid memory address. */
2804 #define MAX_REGS_PER_ADDRESS 1
2806 /* A C compound statement with a conditional `goto LABEL;' executed
2807 if X (an RTX) is a legitimate memory address on the target
2808 machine for a memory operand of mode MODE.
2810 It usually pays to define several simpler macros to serve as
2811 subroutines for this one. Otherwise it may be too complicated
2812 to understand.
2814 This macro must exist in two variants: a strict variant and a
2815 non-strict one. The strict variant is used in the reload pass.
2816 It must be defined so that any pseudo-register that has not been
2817 allocated a hard register is considered a memory reference. In
2818 contexts where some kind of register is required, a
2819 pseudo-register with no hard register must be rejected.
2821 The non-strict variant is used in other passes. It must be
2822 defined to accept all pseudo-registers in every context where
2823 some kind of register is required.
2825 Compiler source files that want to use the strict variant of
2826 this macro define the macro `REG_OK_STRICT'. You should use an
2827 `#ifdef REG_OK_STRICT' conditional to define the strict variant
2828 in that case and the non-strict variant otherwise.
2830 Typically among the subroutines used to define
2831 `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
2832 acceptable registers for various purposes (one for base
2833 registers, one for index registers, and so on). Then only these
2834 subroutine macros need have two variants; the higher levels of
2835 macros may be the same whether strict or not.
2837 Normally, constant addresses which are the sum of a `symbol_ref'
2838 and an integer are stored inside a `const' RTX to mark them as
2839 constant. Therefore, there is no need to recognize such sums
2840 specifically as legitimate addresses. Normally you would simply
2841 recognize any `const' as legitimate.
2843 Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
2844 constant sums that are not marked with `const'. It assumes
2845 that a naked `plus' indicates indexing. If so, then you *must*
2846 reject such naked constant sums as illegitimate addresses, so
2847 that none of them will be given to `PRINT_OPERAND_ADDRESS'.
2849 On some machines, whether a symbolic address is legitimate
2850 depends on the section that the address refers to. On these
2851 machines, define the macro `ENCODE_SECTION_INFO' to store the
2852 information into the `symbol_ref', and then check for it here.
2853 When you see a `const', you will have to look inside it to find
2854 the `symbol_ref' in order to determine the section. */
2856 #if 1
2857 #define GO_PRINTF(x) fprintf(stderr, (x))
2858 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
2859 #define GO_DEBUG_RTX(x) debug_rtx(x)
2861 #else
2862 #define GO_PRINTF(x)
2863 #define GO_PRINTF2(x,y)
2864 #define GO_DEBUG_RTX(x)
2865 #endif
2867 #ifdef REG_OK_STRICT
2868 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2869 { \
2870 if (mips_legitimate_address_p (MODE, X, 1)) \
2871 goto ADDR; \
2872 }
2873 #else
2874 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2875 { \
2876 if (mips_legitimate_address_p (MODE, X, 0)) \
2877 goto ADDR; \
2878 }
2879 #endif
2881 /* A C expression that is 1 if the RTX X is a constant which is a
2882 valid address. This is defined to be the same as `CONSTANT_P (X)',
2883 but rejecting CONST_DOUBLE. */
2884 /* When pic, we must reject addresses of the form symbol+large int.
2885 This is because an instruction `sw $4,s+70000' needs to be converted
2886 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
2887 assembler would use $at as a temp to load in the large offset. In this
2888 case $at is already in use. We convert such problem addresses to
2889 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
2890 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them. */
2891 #define CONSTANT_ADDRESS_P(X) \
2892 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2893 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
2894 || (GET_CODE (X) == CONST \
2895 && ! (flag_pic && pic_address_needs_scratch (X)) \
2896 && (mips_abi == ABI_32 \
2897 || mips_abi == ABI_O64 \
2898 || mips_abi == ABI_EABI))) \
2899 && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X)))
2901 /* Define this, so that when PIC, reload won't try to reload invalid
2902 addresses which require two reload registers. */
2904 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
2906 /* Nonzero if the constant value X is a legitimate general operand.
2907 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
2909 At present, GAS doesn't understand li.[sd], so don't allow it
2910 to be generated at present. Also, the MIPS assembler does not
2911 grok li.d Infinity. */
2913 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
2914 Note that the Irix 6 assembler problem may already be fixed.
2915 Note also that the GET_CODE (X) == CONST test catches the mips16
2916 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
2917 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
2918 ABI_64 to work together, we'll need to fix this. */
2919 #define LEGITIMATE_CONSTANT_P(X) \
2920 ((GET_CODE (X) != CONST_DOUBLE \
2921 || mips_const_double_ok (X, GET_MODE (X))) \
2922 && ! (GET_CODE (X) == CONST \
2923 && ! TARGET_GAS \
2924 && (mips_abi == ABI_N32 \
2925 || mips_abi == ABI_64)) \
2926 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
2928 /* A C compound statement that attempts to replace X with a valid
2929 memory address for an operand of mode MODE. WIN will be a C
2930 statement label elsewhere in the code; the macro definition may
2931 use
2933 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
2935 to avoid further processing if the address has become legitimate.
2937 X will always be the result of a call to `break_out_memory_refs',
2938 and OLDX will be the operand that was given to that function to
2939 produce X.
2941 The code generated by this macro should not alter the
2942 substructure of X. If it transforms X into a more legitimate
2943 form, it should assign X (which will always be a C variable) a
2944 new value.
2946 It is not necessary for this macro to come up with a legitimate
2947 address. The compiler has standard ways of doing so in all
2948 cases. In fact, it is safe for this macro to do nothing. But
2949 often a machine-dependent strategy can generate better code.
2951 For the MIPS, transform:
2953 memory(X + <large int>)
2955 into:
2957 Y = <large int> & ~0x7fff;
2958 Z = X + Y
2959 memory (Z + (<large int> & 0x7fff));
2961 This is for CSE to find several similar references, and only use one Z.
2963 When PIC, convert addresses of the form memory (symbol+large int) to
2964 memory (reg+large int). */
2967 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2968 { \
2969 register rtx xinsn = (X); \
2970 \
2971 if (TARGET_DEBUG_B_MODE) \
2972 { \
2974 GO_DEBUG_RTX (xinsn); \
2975 } \
2976 \
2977 if (mips_split_addresses && mips_check_split (X, MODE)) \
2978 { \
2980 X = gen_rtx_LO_SUM (Pmode, \
2981 copy_to_mode_reg (Pmode, \
2982 gen_rtx (HIGH, Pmode, X)), \
2983 X); \
2984 goto WIN; \
2985 } \
2986 \
2987 if (GET_CODE (xinsn) == CONST \
2988 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
2990 || (mips_abi != ABI_32 \
2991 && mips_abi != ABI_O64 \
2992 && mips_abi != ABI_EABI))) \
2993 { \
2994 rtx ptr_reg = gen_reg_rtx (Pmode); \
2995 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
2996 \
2997 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
2998 \
2999 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3000 if (SMALL_INT (constant)) \
3001 goto WIN; \
3002 /* Otherwise we fall through so the code below will fix the \
3004 xinsn = X; \
3005 } \
3006 \
3007 if (GET_CODE (xinsn) == PLUS) \
3008 { \
3009 register rtx xplus0 = XEXP (xinsn, 0); \
3010 register rtx xplus1 = XEXP (xinsn, 1); \
3011 register enum rtx_code code0 = GET_CODE (xplus0); \
3012 register enum rtx_code code1 = GET_CODE (xplus1); \
3013 \
3014 if (code0 != REG && code1 == REG) \
3015 { \
3016 xplus0 = XEXP (xinsn, 1); \
3017 xplus1 = XEXP (xinsn, 0); \
3018 code0 = GET_CODE (xplus0); \
3019 code1 = GET_CODE (xplus1); \
3020 } \
3021 \
3022 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3023 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3024 { \
3025 rtx int_reg = gen_reg_rtx (Pmode); \
3026 rtx ptr_reg = gen_reg_rtx (Pmode); \
3027 \
3028 emit_move_insn (int_reg, \
3029 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3030 \
3031 emit_insn (gen_rtx_SET (VOIDmode, \
3032 ptr_reg, \
3033 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3034 \
3035 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3036 goto WIN; \
3037 } \
3038 } \
3039 \
3040 if (TARGET_DEBUG_B_MODE) \
3042 }
3045 /* A C statement or compound statement with a conditional `goto
3046 LABEL;' executed if memory address X (an RTX) can have different
3047 meanings depending on the machine mode of the memory reference it
3048 is used for.
3050 Autoincrement and autodecrement addresses typically have
3051 mode-dependent effects because the amount of the increment or
3052 decrement is the size of the operand being addressed. Some
3053 machines have other mode-dependent addresses. Many RISC machines
3054 have no mode-dependent addresses.
3056 You may assume that ADDR is a valid address for the machine. */
3058 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3061 /* Define this macro if references to a symbol must be treated
3062 differently depending on something about the variable or
3063 function named by the symbol (such as what section it is in).
3065 The macro definition, if any, is executed immediately after the
3066 rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
3067 The value of the rtl will be a `mem' whose address is a
3068 `symbol_ref'.
3070 The usual thing for this macro to do is to a flag in the
3071 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
3072 name string in the `symbol_ref' (if one bit is not enough
3073 information).
3075 The best way to modify the name string is by adding text to the
3076 beginning, with suitable punctuation to prevent any ambiguity.
3077 Allocate the new name in `saveable_obstack'. You will have to
3078 modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
3079 and output the name accordingly.
3081 You can also check the information stored in the `symbol_ref' in
3082 the definition of `GO_IF_LEGITIMATE_ADDRESS' or
3083 `PRINT_OPERAND_ADDRESS'.
3085 When optimizing for the $gp pointer, SYMBOL_REF_FLAG is set for all
3086 small objects.
3088 When generating embedded PIC code, SYMBOL_REF_FLAG is set for
3089 symbols which are not in the .text section.
3091 When generating mips16 code, SYMBOL_REF_FLAG is set for string
3092 constants which are put in the .text section. We also record the
3093 total length of all such strings; this total is used to decide
3094 whether we need to split the constant table, and need not be
3095 precisely correct.
3097 When not mips16 code nor embedded PIC, if a symbol is in a
3098 gp addresable section, SYMBOL_REF_FLAG is set prevent gcc from
3099 splitting the reference so that gas can generate a gp relative
3100 reference.
3102 When TARGET_EMBEDDED_DATA is set, we assume that all const
3103 variables will be stored in ROM, which is too far from %gp to use
3104 %gprel addressing. Note that (1) we include "extern const"
3105 variables in this, which mips_select_section doesn't, and (2) we
3106 can't always tell if they're really const (they might be const C++
3107 objects with non-const constructors), so we err on the side of
3108 caution and won't use %gprel anyway (otherwise we'd have to defer
3109 this decision to the linker/loader). The handling of extern consts
3110 is why the DECL_INITIAL macros differ from mips_select_section.
3112 If you are changing this macro, you should look at
3113 mips_select_section and see if it needs a similar change. */
3115 #define ENCODE_SECTION_INFO(DECL) \
3116 do \
3117 { \
3118 if (TARGET_MIPS16) \
3119 { \
3120 if (TREE_CODE (DECL) == STRING_CST \
3121 && ! flag_writable_strings \
3122 /* If this string is from a function, and the function will \
3123 go in a gnu linkonce section, then we can't directly \
3124 access the string. This gets an assembler error \
3125 "unsupported PC relative reference to different section".\
3126 If we modify SELECT_SECTION to put it in function_section\
3127 instead of text_section, it still fails because \
3128 DECL_SECTION_NAME isn't set until assemble_start_function.\
3129 If we fix that, it still fails because strings are shared\
3130 among multiple functions, and we have cross section \
3131 references again. We force it to work by putting string \
3133 && (! current_function_decl \
3134 || ! DECL_ONE_ONLY (current_function_decl))) \
3135 { \
3136 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3137 mips_string_length += TREE_STRING_LENGTH (DECL); \
3138 } \
3139 } \
3140 \
3141 if (TARGET_EMBEDDED_DATA \
3142 && (TREE_CODE (DECL) == VAR_DECL \
3143 && TREE_READONLY (DECL) && !TREE_SIDE_EFFECTS (DECL)) \
3144 && (!DECL_INITIAL (DECL) \
3145 || TREE_CONSTANT (DECL_INITIAL (DECL)))) \
3146 { \
3147 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3148 } \
3149 \
3150 else if (TARGET_EMBEDDED_PIC) \
3151 { \
3152 if (TREE_CODE (DECL) == VAR_DECL) \
3153 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3154 else if (TREE_CODE (DECL) == FUNCTION_DECL) \
3155 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 0; \
3156 else if (TREE_CODE (DECL) == STRING_CST \
3157 && ! flag_writable_strings) \
3158 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 0; \
3159 else \
3160 SYMBOL_REF_FLAG (XEXP (TREE_CST_RTL (DECL), 0)) = 1; \
3161 } \
3162 \
3163 else if (TREE_CODE (DECL) == VAR_DECL \
3164 && DECL_SECTION_NAME (DECL) != NULL_TREE \
3165 && (0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)), \
3167 || 0 == strcmp (TREE_STRING_POINTER (DECL_SECTION_NAME (DECL)),\
3169 { \
3170 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3171 } \
3172 \
3173 /* We can not perform GP optimizations on variables which are in \
3174 specific sections, except for .sdata and .sbss which are \
3176 else if (TARGET_GP_OPT && TREE_CODE (DECL) == VAR_DECL \
3177 && DECL_SECTION_NAME (DECL) == NULL_TREE) \
3178 { \
3179 int size = int_size_in_bytes (TREE_TYPE (DECL)); \
3180 \
3181 if (size > 0 && size <= mips_section_threshold) \
3182 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
3183 } \
3184 \
3185 else if (HALF_PIC_P ()) \
3186 { \
3187 HALF_PIC_ENCODE (DECL); \
3188 } \
3189 } \
3190 while (0)
3192 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3193 'the start of the function that this code is output in'. */
3195 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3198 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3199 else \
3202 /* The mips16 wants the constant pool to be after the function,
3203 because the PC relative load instructions use unsigned offsets. */
3205 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3207 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3208 mips_string_length = 0;
3210 #if 0
3211 /* In mips16 mode, put most string constants after the function. */
3212 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3213 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3214 #endif
3215 \f
3216 /* Specify the machine mode that this machine uses
3217 for the index in the tablejump instruction.
3218 ??? Using HImode in mips16 mode can cause overflow. However, the
3219 overflow is no more likely than the overflow in a branch
3220 instruction. Large functions can currently break in both ways. */
3221 #define CASE_VECTOR_MODE \
3222 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3224 /* Define as C expression which evaluates to nonzero if the tablejump
3225 instruction expects the table to contain offsets from the address of the
3226 table.
3227 Do not define this if the table should contain absolute addresses. */
3228 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3230 /* Specify the tree operation to be used to convert reals to integers. */
3231 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
3233 /* This is the kind of divide that is easiest to do in the general case. */
3234 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
3236 /* Define this as 1 if `char' should by default be signed; else as 0. */
3237 #ifndef DEFAULT_SIGNED_CHAR
3238 #define DEFAULT_SIGNED_CHAR 1
3239 #endif
3241 /* Max number of bytes we can move from memory to memory
3242 in one reasonably fast instruction. */
3243 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3244 #define MAX_MOVE_MAX 8
3246 /* Define this macro as a C expression which is nonzero if
3247 accessing less than a word of memory (i.e. a `char' or a
3248 `short') is no faster than accessing a word of memory, i.e., if
3249 such access require more than one instruction or if there is no
3250 difference in cost between byte and (aligned) word loads.
3252 On RISC machines, it tends to generate better code to define
3253 this as 1, since it avoids making a QI or HI mode register. */
3254 #define SLOW_BYTE_ACCESS 1
3256 /* We assume that the store-condition-codes instructions store 0 for false
3257 and some other value for true. This is the value stored for true. */
3259 #define STORE_FLAG_VALUE 1
3261 /* Define this if zero-extension is slow (more than one real instruction). */
3262 #define SLOW_ZERO_EXTEND
3264 /* Define this to be nonzero if shift instructions ignore all but the low-order
3265 few bits. */
3266 #define SHIFT_COUNT_TRUNCATED 1
3268 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3269 is done just by pretending it is already truncated. */
3270 /* In 64 bit mode, 32 bit instructions require that register values be properly
3271 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3272 converts a value >32 bits to a value <32 bits. */
3273 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3274 Something needs to be done about this. Perhaps not use any 32 bit
3275 instructions? Perhaps use PROMOTE_MODE? */
3276 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3277 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3279 /* Specify the machine mode that pointers have.
3280 After generation of rtl, the compiler makes no further distinction
3281 between pointers and any other objects of this machine mode.
3283 For MIPS we make pointers are the smaller of longs and gp-registers. */
3285 #ifndef Pmode
3286 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3287 #endif
3289 /* A function address in a call instruction
3290 is a word address (for indexing purposes)
3291 so give the MEM rtx a words's mode. */
3293 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3295 /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
3296 memset, instead of the BSD functions bcopy and bzero. */
3298 #if defined(MIPS_SYSV) || defined(OSF_OS)
3299 #define TARGET_MEM_FUNCTIONS
3300 #endif
3302 \f
3303 /* A part of a C `switch' statement that describes the relative
3304 costs of constant RTL expressions. It must contain `case'
3305 labels for expression codes `const_int', `const', `symbol_ref',
3306 `label_ref' and `const_double'. Each case must ultimately reach
3307 a `return' statement to return the relative cost of the use of
3308 that kind of constant value in an expression. The cost may
3309 depend on the precise value of the constant, which is available
3310 for examination in X.
3312 CODE is the expression code--redundant, since it can be obtained
3313 with `GET_CODE (X)'. */
3315 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3316 case CONST_INT: \
3317 if (! TARGET_MIPS16) \
3318 { \
3319 /* Always return 0, since we don't have different sized \
3320 instructions, hence different costs according to Richard \
3322 return 0; \
3323 } \
3324 if ((OUTER_CODE) == SET) \
3325 { \
3326 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3327 return 0; \
3328 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3329 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3330 return COSTS_N_INSNS (1); \
3331 else \
3332 return COSTS_N_INSNS (2); \
3333 } \
3334 /* A PLUS could be an address. We don't want to force an address \
3335 to use a register, so accept any signed 16 bit value without \
3337 if ((OUTER_CODE) == PLUS \
3338 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3339 return 0; \
3340 /* A number between 1 and 8 inclusive is efficient for a shift. \
3342 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3343 || (OUTER_CODE) == LSHIFTRT) \
3344 { \
3345 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3346 return 0; \
3347 return COSTS_N_INSNS (1); \
3348 } \
3350 if ((OUTER_CODE) == XOR \
3351 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3352 return 0; \
3353 /* We may be able to use slt or sltu for a comparison with a \
3354 signed 16 bit value. (The boundary conditions aren't quite \
3356 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3357 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3358 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3359 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3360 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3361 return 0; \
3363 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3364 && INTVAL (X) == 0) \
3365 return 0; \
3366 \
3367 /* Otherwise, work out the cost to load the value into a \
3369 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3370 return COSTS_N_INSNS (1); \
3371 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3372 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3373 return COSTS_N_INSNS (2); \
3374 else \
3375 return COSTS_N_INSNS (3); \
3376 \
3377 case LABEL_REF: \
3378 return COSTS_N_INSNS (2); \
3379 \
3380 case CONST: \
3381 { \
3382 rtx offset = const0_rtx; \
3383 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3384 \
3385 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3386 { \
3388 if ((OUTER_CODE) == PLUS) \
3389 return 0; \
3390 else if ((OUTER_CODE) == SET) \
3391 return COSTS_N_INSNS (1); \
3392 else \
3393 return COSTS_N_INSNS (2); \
3394 } \
3395 \
3396 if (GET_CODE (symref) == LABEL_REF) \
3397 return COSTS_N_INSNS (2); \
3398 \
3399 if (GET_CODE (symref) != SYMBOL_REF) \
3400 return COSTS_N_INSNS (4); \
3401 \
3403 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3404 return COSTS_N_INSNS (2); \
3405 \
3406 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3407 } \
3408 \
3409 case SYMBOL_REF: \
3410 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3411 \
3412 case CONST_DOUBLE: \
3413 { \
3414 rtx high, low; \
3415 if (TARGET_MIPS16) \
3416 return COSTS_N_INSNS (4); \
3417 split_double (X, &high, &low); \
3418 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3419 || low == CONST0_RTX (GET_MODE (low))) \
3420 ? 2 : 4); \
3421 }
3423 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3424 This can be used, for example, to indicate how costly a multiply
3425 instruction is. In writing this macro, you can use the construct
3426 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3428 This macro is optional; do not define it if the default cost
3429 assumptions are adequate for the target machine.
3431 If -mdebugd is used, change the multiply cost to 2, so multiply by
3432 a constant isn't converted to a series of shifts. This helps
3433 strength reduction, and also makes it easier to identify what the
3434 compiler is doing. */
3436 /* ??? Fix this to be right for the R8000. */
3437 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3438 case MEM: \
3439 { \
3440 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3441 if (simple_memory_operand (X, GET_MODE (X))) \
3442 return COSTS_N_INSNS (num_words); \
3443 \
3444 return COSTS_N_INSNS (2*num_words); \
3445 } \
3446 \
3447 case FFS: \
3448 return COSTS_N_INSNS (6); \
3449 \
3450 case NOT: \
3451 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3452 \
3453 case AND: \
3454 case IOR: \
3455 case XOR: \
3456 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3457 return COSTS_N_INSNS (2); \
3458 \
3459 break; \
3460 \
3461 case ASHIFT: \
3462 case ASHIFTRT: \
3463 case LSHIFTRT: \
3464 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3465 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3466 \
3467 break; \
3468 \
3469 case ABS: \
3470 { \
3471 enum machine_mode xmode = GET_MODE (X); \
3472 if (xmode == SFmode || xmode == DFmode) \
3473 return COSTS_N_INSNS (1); \
3474 \
3475 return COSTS_N_INSNS (4); \
3476 } \
3477 \
3478 case PLUS: \
3479 case MINUS: \
3480 { \
3481 enum machine_mode xmode = GET_MODE (X); \
3482 if (xmode == SFmode || xmode == DFmode) \
3483 { \
3484 if (TUNE_MIPS3000 \
3485 || TUNE_MIPS3900) \
3486 return COSTS_N_INSNS (2); \
3487 else if (TUNE_MIPS6000) \
3488 return COSTS_N_INSNS (3); \
3489 else \
3490 return COSTS_N_INSNS (6); \
3491 } \
3492 \
3493 if (xmode == DImode && !TARGET_64BIT) \
3494 return COSTS_N_INSNS (4); \
3495 \
3496 break; \
3497 } \
3498 \
3499 case NEG: \
3500 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3501 return 4; \
3502 \
3503 break; \
3504 \
3505 case MULT: \
3506 { \
3507 enum machine_mode xmode = GET_MODE (X); \
3508 if (xmode == SFmode) \
3509 { \
3510 if (TUNE_MIPS3000 \
3511 || TUNE_MIPS3900 \
3512 || TUNE_MIPS5000) \
3513 return COSTS_N_INSNS (4); \
3514 else if (TUNE_MIPS6000) \
3515 return COSTS_N_INSNS (5); \
3516 else \
3517 return COSTS_N_INSNS (7); \
3518 } \
3519 \
3520 if (xmode == DFmode) \
3521 { \
3522 if (TUNE_MIPS3000 \
3523 || TUNE_MIPS3900 \
3524 || TUNE_MIPS5000) \
3525 return COSTS_N_INSNS (5); \
3526 else if (TUNE_MIPS6000) \
3527 return COSTS_N_INSNS (6); \
3528 else \
3529 return COSTS_N_INSNS (8); \
3530 } \
3531 \
3532 if (TUNE_MIPS3000) \
3533 return COSTS_N_INSNS (12); \
3534 else if (TUNE_MIPS3900) \
3535 return COSTS_N_INSNS (2); \
3536 else if (TUNE_MIPS6000) \
3537 return COSTS_N_INSNS (17); \
3538 else if (TUNE_MIPS5000) \
3539 return COSTS_N_INSNS (5); \
3540 else \
3541 return COSTS_N_INSNS (10); \
3542 } \
3543 \
3544 case DIV: \
3545 case MOD: \
3546 { \
3547 enum machine_mode xmode = GET_MODE (X); \
3548 if (xmode == SFmode) \
3549 { \
3550 if (TUNE_MIPS3000 \
3551 || TUNE_MIPS3900) \
3552 return COSTS_N_INSNS (12); \
3553 else if (TUNE_MIPS6000) \
3554 return COSTS_N_INSNS (15); \
3555 else \
3556 return COSTS_N_INSNS (23); \
3557 } \
3558 \
3559 if (xmode == DFmode) \
3560 { \
3561 if (TUNE_MIPS3000 \
3562 || TUNE_MIPS3900) \
3563 return COSTS_N_INSNS (19); \
3564 else if (TUNE_MIPS6000) \
3565 return COSTS_N_INSNS (16); \
3566 else \
3567 return COSTS_N_INSNS (36); \
3568 } \
3569 } \
3571 \
3572 case UDIV: \
3573 case UMOD: \
3574 if (TUNE_MIPS3000 \
3575 || TUNE_MIPS3900) \
3576 return COSTS_N_INSNS (35); \
3577 else if (TUNE_MIPS6000) \
3578 return COSTS_N_INSNS (38); \
3579 else if (TUNE_MIPS5000) \
3580 return COSTS_N_INSNS (36); \
3581 else \
3582 return COSTS_N_INSNS (69); \
3583 \
3584 case SIGN_EXTEND: \
3585 /* A sign extend from SImode to DImode in 64 bit mode is often \
3586 zero instructions, because the result can often be used \
3588 if (TARGET_64BIT && GET_MODE (X) == DImode \
3589 && GET_MODE (XEXP (X, 0)) == SImode) \
3590 return COSTS_N_INSNS (1); \
3591 else \
3592 return COSTS_N_INSNS (2); \
3593 \
3594 case ZERO_EXTEND: \
3595 if (TARGET_64BIT && GET_MODE (X) == DImode \
3596 && GET_MODE (XEXP (X, 0)) == SImode) \
3597 return COSTS_N_INSNS (2); \
3598 else \
3599 return COSTS_N_INSNS (1);
3601 /* An expression giving the cost of an addressing mode that
3602 contains ADDRESS. If not defined, the cost is computed from the
3603 form of the ADDRESS expression and the `CONST_COSTS' values.
3605 For most CISC machines, the default cost is a good approximation
3606 of the true cost of the addressing mode. However, on RISC
3607 machines, all instructions normally have the same length and
3608 execution time. Hence all addresses will have equal costs.
3610 In cases where more than one form of an address is known, the
3611 form with the lowest cost will be used. If multiple forms have
3612 the same, lowest, cost, the one that is the most complex will be
3613 used.
3615 For example, suppose an address that is equal to the sum of a
3616 register and a constant is used twice in the same basic block.
3617 When this macro is not defined, the address will be computed in
3618 a register and memory references will be indirect through that
3619 register. On machines where the cost of the addressing mode
3620 containing the sum is no higher than that of a simple indirect
3621 reference, this will produce an additional instruction and
3622 possibly require an additional register. Proper specification
3623 of this macro eliminates this overhead for such machines.
3625 Similar use of this macro is made in strength reduction of loops.
3627 ADDRESS need not be valid as an address. In such a case, the
3628 cost is not relevant and can be any value; invalid addresses
3629 need not be assigned a different cost.
3631 On machines where an address involving more than one register is
3632 as cheap as an address computation involving only one register,
3633 defining `ADDRESS_COST' to reflect this can cause two registers
3634 to be live over a region of code where only one would have been
3635 if `ADDRESS_COST' were not defined in that manner. This effect
3636 should be considered in the definition of this macro.
3637 Equivalent costs should probably only be given to addresses with
3638 different numbers of registers on machines with lots of registers.
3640 This macro will normally either not be defined or be defined as
3641 a constant. */
3643 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3645 /* A C expression for the cost of moving data from a register in
3646 class FROM to one in class TO. The classes are expressed using
3647 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3648 the default; other values are interpreted relative to that.
3650 It is not required that the cost always equal 2 when FROM is the
3651 same as TO; on some machines it is expensive to move between
3652 registers if they are not general registers.
3654 If reload sees an insn consisting of a single `set' between two
3655 hard registers, and if `REGISTER_MOVE_COST' applied to their
3656 classes returns a value of 2, reload does not check to ensure
3657 that the constraints of the insn are met. Setting a cost of
3658 other than 2 will allow reload to verify that the constraints are
3659 met. You should do this if the `movM' pattern's constraints do
3660 not allow such copying.
3662 ??? We make make the cost of moving from HI/LO/HILO/MD into general
3663 registers the same as for one of moving general registers to
3664 HI/LO/HILO/MD for TARGET_MIPS16 in order to prevent allocating a
3665 pseudo to HI/LO/HILO/MD. This might hurt optimizations though, it
3666 isn't clear if it is wise. And it might not work in all cases. We
3667 could solve the DImode LO reg problem by using a multiply, just like
3668 reload_{in,out}si. We could solve the SImode/HImode HI reg problem
3669 by using divide instructions. divu puts the remainder in the HI
3670 reg, so doing a divide by -1 will move the value in the HI reg for
3671 all values except -1. We could handle that case by using a signed
3672 divide, e.g. -1 / 2 (or maybe 1 / -2?). We'd have to emit a
3673 compare/branch to test the input value to see which instruction we
3674 need to use. This gets pretty messy, but it is feasible. */
3676 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3677 ((FROM) == M16_REGS && GR_REG_CLASS_P (TO) ? 2 \
3678 : (FROM) == M16_NA_REGS && GR_REG_CLASS_P (TO) ? 2 \
3679 : GR_REG_CLASS_P (FROM) && (TO) == M16_REGS ? 2 \
3680 : GR_REG_CLASS_P (FROM) && (TO) == M16_NA_REGS ? 2 \
3681 : GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? (TARGET_MIPS16 ? 4 : 2) \
3682 : (FROM) == FP_REGS && (TO) == FP_REGS ? 2 \
3683 : GR_REG_CLASS_P (FROM) && (TO) == FP_REGS ? 4 \
3684 : (FROM) == FP_REGS && GR_REG_CLASS_P (TO) ? 4 \
3685 : (((FROM) == HI_REG || (FROM) == LO_REG \
3686 || (FROM) == MD_REGS || (FROM) == HILO_REG) \
3687 && GR_REG_CLASS_P (TO)) ? (TARGET_MIPS16 ? 12 : 6) \
3688 : (((TO) == HI_REG || (TO) == LO_REG \
3689 || (TO) == MD_REGS || (TO) == HILO_REG) \
3690 && GR_REG_CLASS_P (FROM)) ? (TARGET_MIPS16 ? 12 : 6) \
3691 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
3692 : (FROM) == FP_REGS && (TO) == ST_REGS ? 8 \
3693 : 12)
3695 /* ??? Fix this to be right for the R8000. */
3696 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3697 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3698 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3700 /* Define if copies to/from condition code registers should be avoided.
3702 This is needed for the MIPS because reload_outcc is not complete;
3703 it needs to handle cases where the source is a general or another
3704 condition code register. */
3705 #define AVOID_CCMODE_COPIES
3707 /* A C expression for the cost of a branch instruction. A value of
3708 1 is the default; other values are interpreted relative to that. */
3710 /* ??? Fix this to be right for the R8000. */
3711 #define BRANCH_COST \
3712 ((! TARGET_MIPS16 \
3713 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3714 ? 2 : 1)
3716 /* If defined, modifies the length assigned to instruction INSN as a
3717 function of the context in which it is used. LENGTH is an lvalue
3718 that contains the initially computed length of the insn and should
3719 be updated with the correct length of the insn. */
3720 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3721 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3723 \f
3724 /* Optionally define this if you have added predicates to
3725 `MACHINE.c'. This macro is called within an initializer of an
3726 array of structures. The first field in the structure is the
3727 name of a predicate and the second field is an array of rtl
3728 codes. For each predicate, list all rtl codes that can be in
3729 expressions matched by the predicate. The list should have a
3730 trailing comma. Here is an example of two entries in the list
3731 for a typical RISC machine:
3733 #define PREDICATE_CODES \
3734 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3735 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3737 Defining this macro does not affect the generated code (however,
3738 incorrect definitions that omit an rtl code that may be matched
3739 by the predicate can cause the compiler to malfunction).
3740 Instead, it allows the table built by `genrecog' to be more
3741 compact and efficient, thus speeding up the compiler. The most
3742 important predicates to include in the list specified by this
3743 macro are thoses used in the most insn patterns. */
3745 #define PREDICATE_CODES \
3758 LTU, LEU }}, \
3763 SYMBOL_REF, LABEL_REF, SUBREG, \
3764 REG, MEM}}, \
3766 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3767 MEM, SIGN_EXTEND }}, \
3770 SIGN_EXTEND }}, \
3772 SIGN_EXTEND }}, \
3774 SIGN_EXTEND }}, \
3776 SYMBOL_REF, LABEL_REF, SUBREG, \
3777 REG, SIGN_EXTEND }}, \
3780 CONST_DOUBLE, CONST }}, \
3784 /* A list of predicates that do special things with modes, and so
3785 should not elicit warnings for VOIDmode match_operand. */
3787 #define SPECIAL_MODE_PREDICATES \
3790 \f
3791 /* If defined, a C statement to be executed just prior to the
3792 output of assembler code for INSN, to modify the extracted
3793 operands so they will be output differently.
3795 Here the argument OPVEC is the vector containing the operands
3796 extracted from INSN, and NOPERANDS is the number of elements of
3797 the vector which contain meaningful data for this insn. The
3798 contents of this vector are what will be used to convert the
3799 insn template into assembler code, so you can change the
3800 assembler output by changing the contents of the vector.
3802 We use it to check if the current insn needs a nop in front of it
3803 because of load delays, and also to update the delay slot
3804 statistics. */
3806 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3807 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3809 \f
3810 /* Control the assembler format that we output. */
3812 /* Output at beginning of assembler file.
3813 If we are optimizing to use the global pointer, create a temporary
3814 file to hold all of the text stuff, and write it out to the end.
3815 This is needed because the MIPS assembler is evidently one pass,
3816 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3817 declaration when the code is processed, it generates a two
3818 instruction sequence. */
3820 #undef ASM_FILE_START
3821 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3823 /* Output to assembler file text saying following lines
3824 may contain character constants, extra white space, comments, etc. */
3826 #ifndef ASM_APP_ON
3828 #endif
3830 /* Output to assembler file text saying following lines
3831 no longer contain unusual constructs. */
3833 #ifndef ASM_APP_OFF
3835 #endif
3837 /* How to refer to registers in assembler output.
3838 This sequence is indexed by compiler's hard-register-number (see above).
3840 In order to support the two different conventions for register names,
3841 we use the name of a table set up in mips.c, which is overwritten
3842 if -mrnames is used. */
3844 #define REGISTER_NAMES \
3845 { \
3846 &mips_reg_names[ 0][0], \
3847 &mips_reg_names[ 1][0], \
3848 &mips_reg_names[ 2][0], \
3849 &mips_reg_names[ 3][0], \
3850 &mips_reg_names[ 4][0], \
3851 &mips_reg_names[ 5][0], \
3852 &mips_reg_names[ 6][0], \
3853 &mips_reg_names[ 7][0], \
3854 &mips_reg_names[ 8][0], \
3855 &mips_reg_names[ 9][0], \
3856 &mips_reg_names[10][0], \
3857 &mips_reg_names[11][0], \
3858 &mips_reg_names[12][0], \
3859 &mips_reg_names[13][0], \
3860 &mips_reg_names[14][0], \
3861 &mips_reg_names[15][0], \
3862 &mips_reg_names[16][0], \
3863 &mips_reg_names[17][0], \
3864 &mips_reg_names[18][0], \
3865 &mips_reg_names[19][0], \
3866 &mips_reg_names[20][0], \
3867 &mips_reg_names[21][0], \
3868 &mips_reg_names[22][0], \
3869 &mips_reg_names[23][0], \
3870 &mips_reg_names[24][0], \
3871 &mips_reg_names[25][0], \
3872 &mips_reg_names[26][0], \
3873 &mips_reg_names[27][0], \
3874 &mips_reg_names[28][0], \
3875 &mips_reg_names[29][0], \
3876 &mips_reg_names[30][0], \
3877 &mips_reg_names[31][0], \
3878 &mips_reg_names[32][0], \
3879 &mips_reg_names[33][0], \
3880 &mips_reg_names[34][0], \
3881 &mips_reg_names[35][0], \
3882 &mips_reg_names[36][0], \
3883 &mips_reg_names[37][0], \
3884 &mips_reg_names[38][0], \
3885 &mips_reg_names[39][0], \
3886 &mips_reg_names[40][0], \
3887 &mips_reg_names[41][0], \
3888 &mips_reg_names[42][0], \
3889 &mips_reg_names[43][0], \
3890 &mips_reg_names[44][0], \
3891 &mips_reg_names[45][0], \
3892 &mips_reg_names[46][0], \
3893 &mips_reg_names[47][0], \
3894 &mips_reg_names[48][0], \
3895 &mips_reg_names[49][0], \
3896 &mips_reg_names[50][0], \
3897 &mips_reg_names[51][0], \
3898 &mips_reg_names[52][0], \
3899 &mips_reg_names[53][0], \
3900 &mips_reg_names[54][0], \
3901 &mips_reg_names[55][0], \
3902 &mips_reg_names[56][0], \
3903 &mips_reg_names[57][0], \
3904 &mips_reg_names[58][0], \
3905 &mips_reg_names[59][0], \
3906 &mips_reg_names[60][0], \
3907 &mips_reg_names[61][0], \
3908 &mips_reg_names[62][0], \
3909 &mips_reg_names[63][0], \
3910 &mips_reg_names[64][0], \
3911 &mips_reg_names[65][0], \
3912 &mips_reg_names[66][0], \
3913 &mips_reg_names[67][0], \
3914 &mips_reg_names[68][0], \
3915 &mips_reg_names[69][0], \
3916 &mips_reg_names[70][0], \
3917 &mips_reg_names[71][0], \
3918 &mips_reg_names[72][0], \
3919 &mips_reg_names[73][0], \
3920 &mips_reg_names[74][0], \
3921 &mips_reg_names[75][0], \
3922 }
3924 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
3925 So define this for it. */
3926 #define DEBUG_REGISTER_NAMES \
3927 { \
3938 }
3940 /* If defined, a C initializer for an array of structures
3941 containing a name and a register number. This macro defines
3942 additional names for hard registers, thus allowing the `asm'
3943 option in declarations to refer to registers using alternate
3944 names.
3946 We define both names for the integer registers here. */
3948 #define ADDITIONAL_REGISTER_NAMES \
3949 { \
4017 }
4019 /* A C compound statement to output to stdio stream STREAM the
4020 assembler syntax for an instruction operand X. X is an RTL
4021 expression.
4023 CODE is a value that can be used to specify one of several ways
4024 of printing the operand. It is used when identical operands
4025 must be printed differently depending on the context. CODE
4026 comes from the `%' specification that was used to request
4027 printing of the operand. If the specification was just `%DIGIT'
4028 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4029 is the ASCII code for LTR.
4031 If X is a register, this macro should print the register's name.
4032 The names can be found in an array `reg_names' whose type is
4033 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4035 When the machine description has a specification `%PUNCT' (a `%'
4036 followed by a punctuation character), this macro is called with
4037 a null pointer for X and the punctuation character for CODE.
4039 See mips.c for the MIPS specific codes. */
4041 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4043 /* A C expression which evaluates to true if CODE is a valid
4044 punctuation character for use in the `PRINT_OPERAND' macro. If
4045 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4046 punctuation characters (except for the standard one, `%') are
4047 used in this way. */
4049 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4051 /* A C compound statement to output to stdio stream STREAM the
4052 assembler syntax for an instruction operand that is a memory
4053 reference whose address is ADDR. ADDR is an RTL expression.
4055 On some machines, the syntax for a symbolic address depends on
4056 the section that the address refers to. On these machines,
4057 define the macro `ENCODE_SECTION_INFO' to store the information
4058 into the `symbol_ref', and then check for it here. */
4060 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4063 /* A C statement, to be executed after all slot-filler instructions
4064 have been output. If necessary, call `dbr_sequence_length' to
4065 determine the number of slots filled in a sequence (zero if not
4066 currently outputting a sequence), to decide how many no-ops to
4067 output, or whatever.
4069 Don't define this macro if it has nothing to do, but it is
4070 helpful in reading assembly output if the extent of the delay
4071 sequence is made explicit (e.g. with white space).
4073 Note that output routines for instructions with delay slots must
4074 be prepared to deal with not being output as part of a sequence
4075 (i.e. when the scheduling pass is not run, or when no slot
4076 fillers could be found.) The variable `final_sequence' is null
4077 when not processing a sequence, otherwise it contains the
4078 `sequence' rtx being output. */
4080 #define DBR_OUTPUT_SEQEND(STREAM) \
4081 do \
4082 { \
4083 if (set_nomacro > 0 && --set_nomacro == 0) \
4085 \
4086 if (set_noreorder > 0 && --set_noreorder == 0) \
4088 \
4089 dslots_jump_filled++; \
4091 } \
4092 while (0)
4095 /* How to tell the debugger about changes of source files. Note, the
4096 mips ECOFF format cannot deal with changes of files inside of
4097 functions, which means the output of parser generators like bison
4098 is generally not debuggable without using the -l switch. Lose,
4099 lose, lose. Silicon graphics seems to want all .file's hardwired
4100 to 1. */
4102 #ifndef SET_FILE_NUMBER
4103 #define SET_FILE_NUMBER() ++num_source_filenames
4104 #endif
4106 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4107 mips_output_filename (STREAM, NAME)
4109 /* This is defined so that it can be overridden in iris6.h. */
4110 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4111 do \
4112 { \
4114 output_quoted_string (STREAM, NAME); \
4116 } \
4117 while (0)
4119 /* This is how to output a note the debugger telling it the line number
4120 to which the following sequence of instructions corresponds.
4121 Silicon graphics puts a label after each .loc. */
4123 #ifndef LABEL_AFTER_LOC
4124 #define LABEL_AFTER_LOC(STREAM)
4125 #endif
4127 #ifndef ASM_OUTPUT_SOURCE_LINE
4128 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4129 mips_output_lineno (STREAM, LINE)
4130 #endif
4132 /* The MIPS implementation uses some labels for its own purpose. The
4133 following lists what labels are created, and are all formed by the
4134 pattern $L[a-z].*. The machine independent portion of GCC creates
4135 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4137 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4138 $Lb[0-9]+ Begin blocks for MIPS debug support
4139 $Lc[0-9]+ Label for use in s<xx> operation.
4140 $Le[0-9]+ End blocks for MIPS debug support
4141 $Lp\..+ Half-pic labels. */
4143 /* This is how to output the definition of a user-level label named NAME,
4144 such as the label on a static function or variable NAME.
4146 If we are optimizing the gp, remember that this label has been put
4147 out, so we know not to emit an .extern for it in mips_asm_file_end.
4148 We use one of the common bits in the IDENTIFIER tree node for this,
4149 since those bits seem to be unused, and we don't have any method
4150 of getting the decl nodes from the name. */
4152 #define ASM_OUTPUT_LABEL(STREAM,NAME) \
4153 do { \
4154 assemble_name (STREAM, NAME); \
4156 } while (0)
4159 /* A C statement (sans semicolon) to output to the stdio stream
4160 STREAM any text necessary for declaring the name NAME of an
4161 initialized variable which is being defined. This macro must
4162 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4163 The argument DECL is the `VAR_DECL' tree node representing the
4164 variable.
4166 If this macro is not defined, then the variable name is defined
4167 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4169 #undef ASM_DECLARE_OBJECT_NAME
4170 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4171 do \
4172 { \
4174 HALF_PIC_DECLARE (NAME); \
4175 } \
4176 while (0)
4179 /* This is how to output a command to make the user-level label named NAME
4180 defined for reference from other files. */
4182 #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
4183 do { \
4185 assemble_name (STREAM, NAME); \
4187 } while (0)
4189 /* This says how to define a global common symbol. */
4191 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4192 do { \
4193 /* If the target wants uninitialized const declarations in \
4195 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4196 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4197 && (DECL_INITIAL (DECL) == 0 \
4198 || DECL_INITIAL (DECL) == error_mark_node)) \
4199 { \
4200 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4201 ASM_GLOBALIZE_LABEL (STREAM, NAME); \
4202 \
4203 READONLY_DATA_SECTION (); \
4204 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4206 (SIZE)); \
4207 } \
4208 else \
4210 (SIZE)); \
4211 } while (0)
4214 /* This says how to define a local common symbol (ie, not visible to
4215 linker). */
4217 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4221 /* This says how to output an external. It would be possible not to
4222 output anything and let undefined symbol become external. However
4223 the assembler uses length information on externals to allocate in
4224 data/sdata bss/sbss, thereby saving exec time. */
4226 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4227 mips_output_external(STREAM,DECL,NAME)
4229 /* This says what to print at the end of the assembly file */
4230 #undef ASM_FILE_END
4231 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4234 /* Play switch file games if we're optimizing the global pointer. */
4236 #undef TEXT_SECTION
4237 #define TEXT_SECTION() \
4238 do { \
4239 extern FILE *asm_out_text_file; \
4240 if (TARGET_FILE_SWITCHING) \
4241 asm_out_file = asm_out_text_file; \
4242 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4244 } while (0)
4247 /* This is how to declare a function name. The actual work of
4248 emitting the label is moved to function_prologue, so that we can
4249 get the line number correctly emitted before the .ent directive,
4250 and after any .file directives. */
4252 #undef ASM_DECLARE_FUNCTION_NAME
4253 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
4254 HALF_PIC_DECLARE (NAME)
4256 /* This is how to output an internal numbered label where
4257 PREFIX is the class of label and NUM is the number within the class. */
4259 #undef ASM_OUTPUT_INTERNAL_LABEL
4260 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4263 /* This is how to store into the string LABEL
4264 the symbol_ref name of an internal numbered label where
4265 PREFIX is the class of label and NUM is the number within the class.
4266 This is suitable for output with `assemble_name'. */
4268 #undef ASM_GENERATE_INTERNAL_LABEL
4269 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4272 /* This is how to output an assembler line defining a `double' constant. */
4274 #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
4275 mips_output_double (STREAM, VALUE)
4278 /* This is how to output an assembler line defining a `float' constant. */
4280 #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
4281 mips_output_float (STREAM, VALUE)
4284 /* This is how to output an assembler line defining an `int' constant. */
4286 #define ASM_OUTPUT_INT(STREAM,VALUE) \
4287 do { \
4289 output_addr_const (STREAM, (VALUE)); \
4291 } while (0)
4293 /* Likewise for 64 bit, `char' and `short' constants.
4295 FIXME: operand_subword can't handle some complex constant expressions
4296 that output_addr_const can (for example it does not call
4297 simplify_subtraction). Since GAS can handle dword, even for mipsII,
4298 rely on that to avoid operand_subword for most of the cases where this
4299 matters. Try gcc.c-torture/compile/930326-1.c with -mips2 -mlong64,
4300 or the same case with the type of 'i' changed to long long.
4302 */
4304 #define ASM_OUTPUT_DOUBLE_INT(STREAM,VALUE) \
4305 do { \
4306 if (TARGET_64BIT || TARGET_GAS) \
4307 { \
4309 if (HOST_BITS_PER_WIDE_INT < 64 || GET_CODE (VALUE) != CONST_INT) \
4310 /* We can't use 'X' for negative numbers, because then we won't \
4312 output_addr_const (STREAM, VALUE); \
4313 else \
4314 /* We must use 'X', because otherwise LONG_MIN will print as \
4318 } \
4319 else \
4320 { \
4321 assemble_integer (operand_subword ((VALUE), 0, 0, DImode), \
4322 UNITS_PER_WORD, BITS_PER_WORD, 1); \
4323 assemble_integer (operand_subword ((VALUE), 1, 0, DImode), \
4324 UNITS_PER_WORD, BITS_PER_WORD, 1); \
4325 } \
4326 } while (0)
4328 #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
4329 { \
4331 output_addr_const (STREAM, (VALUE)); \
4333 }
4335 #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
4336 { \
4338 output_addr_const (STREAM, (VALUE)); \
4340 }
4342 /* This is how to output an assembler line for a numeric constant byte. */
4344 #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
4347 /* This is how to output an element of a case-vector that is absolute. */
4349 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4352 LOCAL_LABEL_PREFIX, \
4353 VALUE)
4355 /* This is how to output an element of a case-vector that is relative.
4356 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4357 TARGET_EMBEDDED_PIC). */
4359 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4360 do { \
4361 if (TARGET_MIPS16) \
4363 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4364 else if (TARGET_EMBEDDED_PIC) \
4367 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4368 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4371 LOCAL_LABEL_PREFIX, VALUE); \
4372 else \
4375 LOCAL_LABEL_PREFIX, VALUE); \
4376 } while (0)
4378 /* When generating embedded PIC or mips16 code we want to put the jump
4379 table in the .text section. In all other cases, we want to put the
4380 jump table in the .rdata section. Unfortunately, we can't use
4381 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4382 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4383 section if appropriate. */
4384 #undef ASM_OUTPUT_CASE_LABEL
4385 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4386 do { \
4387 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4388 function_section (current_function_decl); \
4389 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4390 } while (0)
4392 /* This is how to output an assembler line
4393 that says to advance the location counter
4394 to a multiple of 2**LOG bytes. */
4396 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4399 /* This is how to output an assembler line to advance the location
4400 counter by SIZE bytes. */
4402 #undef ASM_OUTPUT_SKIP
4403 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4406 /* This is how to output a string. */
4407 #undef ASM_OUTPUT_ASCII
4408 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4409 mips_output_ascii (STREAM, STRING, LEN)
4411 /* Handle certain cpp directives used in header files on sysV. */
4412 #define SCCS_DIRECTIVE
4414 #ifndef ASM_OUTPUT_IDENT
4415 /* Output #ident as a in the read-only data section. */
4416 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4417 { \
4418 const char *p = STRING; \
4419 int size = strlen (p) + 1; \
4420 rdata_section (); \
4421 assemble_string (p, size); \
4422 }
4423 #endif
4424 \f
4425 /* Default to -G 8 */
4426 #ifndef MIPS_DEFAULT_GVALUE
4427 #define MIPS_DEFAULT_GVALUE 8
4428 #endif
4430 /* Define the strings to put out for each section in the object file. */
4435 #undef READONLY_DATA_SECTION
4436 #define READONLY_DATA_SECTION rdata_section
4437 #define SMALL_DATA_SECTION sdata_section
4439 /* What other sections we support other than the normal .data/.text. */
4441 #undef EXTRA_SECTIONS
4442 #define EXTRA_SECTIONS in_sdata, in_rdata
4444 /* Define the additional functions to select our additional sections. */
4446 /* on the MIPS it is not a good idea to put constants in the text
4447 section, since this defeats the sdata/data mechanism. This is
4448 especially true when -O is used. In this case an effort is made to
4449 address with faster (gp) register relative addressing, which can
4450 only get at sdata and sbss items (there is no stext !!) However,
4451 if the constant is too large for sdata, and it's readonly, it
4452 will go into the .rdata section. */
4454 #undef EXTRA_SECTION_FUNCTIONS
4455 #define EXTRA_SECTION_FUNCTIONS \
4456 void \
4457 sdata_section () \
4458 { \
4459 if (in_section != in_sdata) \
4460 { \
4462 in_section = in_sdata; \
4463 } \
4464 } \
4465 \
4466 void \
4467 rdata_section () \
4468 { \
4469 if (in_section != in_rdata) \
4470 { \
4472 in_section = in_rdata; \
4473 } \
4474 }
4476 /* Given a decl node or constant node, choose the section to output it in
4477 and select that section. */
4479 #undef SELECT_RTX_SECTION
4480 #define SELECT_RTX_SECTION(MODE,RTX) mips_select_rtx_section (MODE, RTX)
4482 #undef SELECT_SECTION
4483 #define SELECT_SECTION(DECL, RELOC) mips_select_section (DECL, RELOC)
4485 \f
4486 /* Store in OUTPUT a string (made with alloca) containing
4487 an assembler-name for a local static variable named NAME.
4488 LABELNO is an integer which is different for each call. */
4490 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4491 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4494 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4495 do \
4496 { \
4499 reg_names[STACK_POINTER_REGNUM], \
4500 reg_names[STACK_POINTER_REGNUM], \
4502 reg_names[REGNO], \
4503 reg_names[STACK_POINTER_REGNUM]); \
4504 } \
4505 while (0)
4507 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4508 do \
4509 { \
4510 if (! set_noreorder) \
4512 \
4513 dslots_load_total++; \
4514 dslots_load_filled++; \
4517 reg_names[REGNO], \
4518 reg_names[STACK_POINTER_REGNUM], \
4520 reg_names[STACK_POINTER_REGNUM], \
4521 reg_names[STACK_POINTER_REGNUM]); \
4522 \
4523 if (! set_noreorder) \
4525 } \
4526 while (0)
4528 /* How to start an assembler comment.
4529 The leading space is important (the mips native assembler requires it). */
4530 #ifndef ASM_COMMENT_START
4532 #endif
4533 \f
4535 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4536 and mips-tdump.c to print them out.
4538 These must match the corresponding definitions in gdb/mipsread.c.
4539 Unfortunately, gcc and gdb do not currently share any directories. */
4541 #define CODE_MASK 0x8F300
4542 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4543 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4544 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4546 \f
4547 /* Default definitions for size_t and ptrdiff_t. */
4549 #ifndef SIZE_TYPE
4550 #define NO_BUILTIN_SIZE_TYPE
4552 #endif
4554 #ifndef PTRDIFF_TYPE
4555 #define NO_BUILTIN_PTRDIFF_TYPE
4557 #endif
4559 /* See mips_expand_prologue's use of loadgp for when this should be
4560 true. */
4562 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4563 && mips_abi != ABI_32 \
4564 && mips_abi != ABI_O64)
4565 \f
4566 /* In mips16 mode, we need to look through the function to check for
4567 PC relative loads that are out of range. */
4568 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4570 /* We need to use a special set of functions to handle hard floating
4571 point code in mips16 mode. */
4573 #ifndef INIT_SUBTARGET_OPTABS
4574 #define INIT_SUBTARGET_OPTABS
4575 #endif
4577 #define INIT_TARGET_OPTABS \
4578 do \
4579 { \
4580 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4581 INIT_SUBTARGET_OPTABS; \
4582 else \
4583 { \
4584 add_optab->handlers[(int) SFmode].libfunc = \
4586 sub_optab->handlers[(int) SFmode].libfunc = \
4588 smul_optab->handlers[(int) SFmode].libfunc = \
4590 sdiv_optab->handlers[(int) SFmode].libfunc = \
4592 \
4599 \
4600 floatsisf_libfunc = \
4602 fixsfsi_libfunc = \
4604 \
4605 if (TARGET_DOUBLE_FLOAT) \
4606 { \
4607 add_optab->handlers[(int) DFmode].libfunc = \
4609 sub_optab->handlers[(int) DFmode].libfunc = \
4611 smul_optab->handlers[(int) DFmode].libfunc = \
4613 sdiv_optab->handlers[(int) DFmode].libfunc = \
4615 \
4616 extendsfdf2_libfunc = \
4618 truncdfsf2_libfunc = \
4620 \
4621 eqdf2_libfunc = \
4623 nedf2_libfunc = \
4625 gtdf2_libfunc = \
4627 gedf2_libfunc = \
4629 ltdf2_libfunc = \
4631 ledf2_libfunc = \
4633 \
4634 floatsidf_libfunc = \
4636 fixdfsi_libfunc = \
4638 } \
4639 } \
4640 } \
4641 while (0)