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2004-03-04 Eric Christopher <echristo@redhat.com>
[official-gcc.git] / gcc / config / mips / mips.h
blobcb3a9f39349892fba2a1221c4dbbee3f15312f4f
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* comparison type */
34 enum cmp_type {
35 CMP_SI, /* compare four byte integers */
36 CMP_DI, /* compare eight byte integers */
37 CMP_SF, /* compare single precision floats */
38 CMP_DF, /* compare double precision floats */
39 CMP_MAX /* max comparison type */
40 };
41
42 /* Which processor to schedule for. Since there is no difference between
43 a R2000 and R3000 in terms of the scheduler, we collapse them into
44 just an R3000. The elements of the enumeration must match exactly
45 the cpu attribute in the mips.md machine description. */
46
47 enum processor_type {
48 PROCESSOR_DEFAULT,
49 PROCESSOR_4KC,
50 PROCESSOR_5KC,
51 PROCESSOR_20KC,
52 PROCESSOR_M4K,
53 PROCESSOR_R3000,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4300,
61 PROCESSOR_R4600,
62 PROCESSOR_R4650,
63 PROCESSOR_R5000,
64 PROCESSOR_R5400,
65 PROCESSOR_R5500,
66 PROCESSOR_R7000,
67 PROCESSOR_R8000,
68 PROCESSOR_R9000,
69 PROCESSOR_SB1,
70 PROCESSOR_SR71000
71 };
72
73 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
74 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
75 to work on a 64 bit machine. */
76
77 #define ABI_32 0
78 #define ABI_N32 1
79 #define ABI_64 2
80 #define ABI_EABI 3
81 #define ABI_O64 4
82
83 /* Information about one recognized processor. Defined here for the
84 benefit of TARGET_CPU_CPP_BUILTINS. */
85 struct mips_cpu_info {
86 /* The 'canonical' name of the processor as far as GCC is concerned.
87 It's typically a manufacturer's prefix followed by a numerical
88 designation. It should be lower case. */
89 const char *name;
90
91 /* The internal processor number that most closely matches this
92 entry. Several processors can have the same value, if there's no
93 difference between them from GCC's point of view. */
94 enum processor_type cpu;
95
96 /* The ISA level that the processor implements. */
97 int isa;
98 };
99
100 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
101 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
102 extern const char *current_function_file; /* filename current function is in */
103 extern int num_source_filenames; /* current .file # */
104 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
105 extern int sym_lineno; /* sgi next label # for each stmt */
106 extern int set_noreorder; /* # of nested .set noreorder's */
107 extern int set_nomacro; /* # of nested .set nomacro's */
108 extern int set_noat; /* # of nested .set noat's */
109 extern int set_volatile; /* # of nested .set volatile's */
110 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
111 extern int mips_dbx_regno[]; /* Map register # to debug register # */
112 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
113 extern enum cmp_type branch_type; /* what type of branch to use */
114 extern enum processor_type mips_arch; /* which cpu to codegen for */
115 extern enum processor_type mips_tune; /* which cpu to schedule for */
116 extern int mips_isa; /* architectural level */
117 extern int mips_abi; /* which ABI to use */
118 extern int mips16_hard_float; /* mips16 without -msoft-float */
119 extern int mips_entry; /* generate entry/exit for mips16 */
120 extern const char *mips_arch_string; /* for -march=<xxx> */
121 extern const char *mips_tune_string; /* for -mtune=<xxx> */
122 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
123 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
124 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
125 extern int mips_string_length; /* length of strings for mips16 */
126 extern const struct mips_cpu_info mips_cpu_info_table[];
127 extern const struct mips_cpu_info *mips_arch_info;
128 extern const struct mips_cpu_info *mips_tune_info;
129
130 /* Macros to silence warnings about numbers being signed in traditional
131 C and unsigned in ISO C when compiled on 32-bit hosts. */
132
133 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
134 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
135 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
136
137 \f
138 /* Run-time compilation parameters selecting different hardware subsets. */
139
140 /* Macros used in the machine description to test the flags. */
141
142 /* Bits for real switches */
143 #define MASK_INT64 0x00000001 /* ints are 64 bits */
144 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
145 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
146 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
147 multiply-add operations. */
148 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
149 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
150 #define MASK_EXPLICIT_RELOCS 0x00000040 /* Use relocation operators. */
151 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
152 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
153 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
154 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
155 #define MASK_XGOT 0x00000800 /* emit big-got PIC */
156 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
157 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
158 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
159 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
160 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
161 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
162 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
163 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
164 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
165 #define MASK_NO_CHECK_ZERO_DIV \
166 0x00200000 /* divide by zero checking */
167 #define MASK_BRANCHLIKELY 0x00400000 /* Generate Branch Likely
168 instructions. */
169 #define MASK_UNINIT_CONST_IN_RODATA \
170 0x00800000 /* Store uninitialized
171 consts in rodata */
172 #define MASK_FIX_R4000 0x01000000 /* Work around R4000 errata. */
173 #define MASK_FIX_R4400 0x02000000 /* Work around R4400 errata. */
174 #define MASK_FIX_SB1 0x04000000 /* Work around SB-1 errata. */
175
176 /* Debug switches, not documented */
177 #define MASK_DEBUG 0 /* unused */
178 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
179 #define MASK_DEBUG_D 0 /* don't do define_split's */
180 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
181
182 /* Dummy switches used only in specs */
183 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
184
185 /* r4000 64 bit sizes */
186 #define TARGET_INT64 (target_flags & MASK_INT64)
187 #define TARGET_LONG64 (target_flags & MASK_LONG64)
188 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
189 #define TARGET_64BIT (target_flags & MASK_64BIT)
190
191 /* Mips vs. GNU linker */
192 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
193
194 /* Mips vs. GNU assembler */
195 #define TARGET_GAS (target_flags & MASK_GAS)
196 #define TARGET_MIPS_AS (!TARGET_GAS)
197
198 /* Debug Modes */
199 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
200 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
201 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
202 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
203
204 /* Reg. Naming in .s ($21 vs. $a0) */
205 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
206
207 /* call memcpy instead of inline code */
208 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
209
210 /* .abicalls, etc from Pyramid V.4 */
211 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
212 #define TARGET_XGOT (target_flags & MASK_XGOT)
213
214 /* software floating point */
215 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
216 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
217
218 /* always call through a register */
219 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
220
221 /* generate embedded PIC code;
222 requires gas. */
223 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
224
225 /* for embedded systems, optimize for
226 reduced RAM space instead of for
227 fastest code. */
228 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
229
230 /* always store uninitialized const
231 variables in rodata, requires
232 TARGET_EMBEDDED_DATA. */
233 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
234
235 /* generate big endian code. */
236 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
237
238 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
239 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
240
241 #define TARGET_MAD (target_flags & MASK_MAD)
242
243 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
244
245 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
246
247 #define TARGET_CHECK_ZERO_DIV (!(target_flags & MASK_NO_CHECK_ZERO_DIV))
248
249 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
250
251 #define TARGET_FIX_SB1 (target_flags & MASK_FIX_SB1)
252
253 /* Work around R4000 errata. */
254 #define TARGET_FIX_R4000 (target_flags & MASK_FIX_R4000)
255
256 /* Work around R4400 errata. */
257 #define TARGET_FIX_R4400 (target_flags & MASK_FIX_R4400)
258
259 /* True if we should use NewABI-style relocation operators for
260 symbolic addresses. This is never true for mips16 code,
261 which has its own conventions. */
262
263 #define TARGET_EXPLICIT_RELOCS (target_flags & MASK_EXPLICIT_RELOCS)
264
265
266 /* True if the call patterns should be split into a jalr followed by
267 an instruction to restore $gp. This is only ever true for SVR4 PIC,
268 in which $gp is call-clobbered. It is only safe to split the load
269 from the call when every use of $gp is explicit. */
270
271 #define TARGET_SPLIT_CALLS \
272 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
273
274 /* True if we can optimize sibling calls. For simplicity, we only
275 handle cases in which call_insn_operand will reject invalid
276 sibcall addresses. There are two cases in which this isn't true:
277
278 - TARGET_MIPS16. call_insn_operand accepts constant addresses
279 but there is no direct jump instruction. It isn't worth
280 using sibling calls in this case anyway; they would usually
281 be longer than normal calls.
282
283 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
284 accepts global constants, but "jr $25" is the only allowed
285 sibcall. */
286
287 #define TARGET_SIBCALLS \
288 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
289
290 /* True if .gpword or .gpdword should be used for switch tables.
291 There are some problems with using these directives with the
292 native IRIX tools:
293
294 - It has been reported that some versions of the native n32
295 assembler mishandle .gpword, complaining that symbols are
296 global when they are in fact local.
297
298 - The native assemblers don't understand .gpdword.
299
300 - Although GAS does understand .gpdword, the native linker
301 mishandles the relocations GAS generates (R_MIPS_GPREL32
302 followed by R_MIPS_64).
303
304 We therefore disable GP-relative switch tables for n32 and n64
305 on IRIX targets. */
306 #define TARGET_GPWORD (TARGET_ABICALLS && !(TARGET_NEWABI && TARGET_IRIX))
307
308 /* Generate mips16 code */
309 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
310
311 /* Generic ISA defines. */
312 #define ISA_MIPS1 (mips_isa == 1)
313 #define ISA_MIPS2 (mips_isa == 2)
314 #define ISA_MIPS3 (mips_isa == 3)
315 #define ISA_MIPS4 (mips_isa == 4)
316 #define ISA_MIPS32 (mips_isa == 32)
317 #define ISA_MIPS32R2 (mips_isa == 33)
318 #define ISA_MIPS64 (mips_isa == 64)
319
320 /* Architecture target defines. */
321 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
322 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
323 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
324 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
325 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
326 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
327 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
328 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
329
330 /* Scheduling target defines. */
331 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
332 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
333 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
334 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
335 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
336 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
337 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
338 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
339 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
340
341 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
342 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
343
344 /* IRIX specific stuff. */
345 #define TARGET_IRIX 0
346 #define TARGET_IRIX5 0
347 #define TARGET_SGI_O32_AS (TARGET_IRIX && mips_abi == ABI_32 && !TARGET_GAS)
348
349 /* Define preprocessor macros for the -march and -mtune options.
350 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
351 processor. If INFO's canonical name is "foo", define PREFIX to
352 be "foo", and define an additional macro PREFIX_FOO. */
353 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
354 do \
355 { \
356 char *macro, *p; \
357 \
358 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
359 for (p = macro; *p != 0; p++) \
360 *p = TOUPPER (*p); \
361 \
362 builtin_define (macro); \
363 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
364 free (macro); \
365 } \
366 while (0)
367
368 /* Target CPU builtins. */
369 #define TARGET_CPU_CPP_BUILTINS() \
370 do \
371 { \
372 builtin_assert ("cpu=mips"); \
373 builtin_define ("__mips__"); \
374 builtin_define ("_mips"); \
375 \
376 /* We do this here because __mips is defined below \
377 and so we can't use builtin_define_std. */ \
378 if (!flag_iso) \
379 builtin_define ("mips"); \
380 \
381 /* Treat _R3000 and _R4000 like register-size defines, \
382 which is how they've historically been used. */ \
383 if (TARGET_64BIT) \
384 { \
385 builtin_define ("__mips64"); \
386 builtin_define_std ("R4000"); \
387 builtin_define ("_R4000"); \
388 } \
389 else \
390 { \
391 builtin_define_std ("R3000"); \
392 builtin_define ("_R3000"); \
393 } \
394 if (TARGET_FLOAT64) \
395 builtin_define ("__mips_fpr=64"); \
396 else \
397 builtin_define ("__mips_fpr=32"); \
398 \
399 if (TARGET_MIPS16) \
400 builtin_define ("__mips16"); \
401 \
402 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
403 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
404 \
405 if (ISA_MIPS1) \
406 { \
407 builtin_define ("__mips=1"); \
408 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
409 } \
410 else if (ISA_MIPS2) \
411 { \
412 builtin_define ("__mips=2"); \
413 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
414 } \
415 else if (ISA_MIPS3) \
416 { \
417 builtin_define ("__mips=3"); \
418 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
419 } \
420 else if (ISA_MIPS4) \
421 { \
422 builtin_define ("__mips=4"); \
423 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
424 } \
425 else if (ISA_MIPS32) \
426 { \
427 builtin_define ("__mips=32"); \
428 builtin_define ("__mips_isa_rev=1"); \
429 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
430 } \
431 else if (ISA_MIPS32R2) \
432 { \
433 builtin_define ("__mips=32"); \
434 builtin_define ("__mips_isa_rev=2"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
436 } \
437 else if (ISA_MIPS64) \
438 { \
439 builtin_define ("__mips=64"); \
440 builtin_define ("__mips_isa_rev=1"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
442 } \
443 \
444 if (TARGET_HARD_FLOAT) \
445 builtin_define ("__mips_hard_float"); \
446 else if (TARGET_SOFT_FLOAT) \
447 builtin_define ("__mips_soft_float"); \
448 \
449 if (TARGET_SINGLE_FLOAT) \
450 builtin_define ("__mips_single_float"); \
451 \
452 if (TARGET_BIG_ENDIAN) \
453 { \
454 builtin_define_std ("MIPSEB"); \
455 builtin_define ("_MIPSEB"); \
456 } \
457 else \
458 { \
459 builtin_define_std ("MIPSEL"); \
460 builtin_define ("_MIPSEL"); \
461 } \
462 \
463 /* Macros dependent on the C dialect. */ \
464 if (preprocessing_asm_p ()) \
465 { \
466 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
467 builtin_define ("_LANGUAGE_ASSEMBLY"); \
468 } \
469 else if (c_dialect_cxx ()) \
470 { \
471 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
472 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
473 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
474 } \
475 else \
476 { \
477 builtin_define_std ("LANGUAGE_C"); \
478 builtin_define ("_LANGUAGE_C"); \
479 } \
480 if (c_dialect_objc ()) \
481 { \
482 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
483 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
484 /* Bizarre, but needed at least for Irix. */ \
485 builtin_define_std ("LANGUAGE_C"); \
486 builtin_define ("_LANGUAGE_C"); \
487 } \
488 \
489 if (mips_abi == ABI_EABI) \
490 builtin_define ("__mips_eabi"); \
491 \
492 } while (0)
493
494
495
496 /* Macro to define tables used to set the flags.
497 This is a list in braces of pairs in braces,
498 each pair being { "NAME", VALUE }
499 where VALUE is the bits to set or minus the bits to clear.
500 An empty string NAME is used to identify the default VALUE. */
501
502 #define TARGET_SWITCHES \
503 { \
504 SUBTARGET_TARGET_SWITCHES \
505 {"int64", MASK_INT64 | MASK_LONG64, \
506 N_("Use 64-bit int type")}, \
507 {"long64", MASK_LONG64, \
508 N_("Use 64-bit long type")}, \
509 {"long32", -(MASK_LONG64 | MASK_INT64), \
510 N_("Use 32-bit long type")}, \
511 {"split-addresses", MASK_SPLIT_ADDR, \
512 N_("Optimize lui/addiu address loads")}, \
513 {"no-split-addresses", -MASK_SPLIT_ADDR, \
514 N_("Don't optimize lui/addiu address loads")}, \
515 {"mips-as", -MASK_GAS, \
516 N_("Use MIPS as")}, \
517 {"gas", MASK_GAS, \
518 N_("Use GNU as")}, \
519 {"rnames", MASK_NAME_REGS, \
520 N_("Use symbolic register names")}, \
521 {"no-rnames", -MASK_NAME_REGS, \
522 N_("Don't use symbolic register names")}, \
523 {"gpOPT", 0, \
524 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
525 {"gpopt", 0, \
526 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
527 {"no-gpOPT", 0, \
528 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
529 {"no-gpopt", 0, \
530 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
531 {"stats", 0, \
532 N_("Output compiler statistics (now ignored)")}, \
533 {"no-stats", 0, \
534 N_("Don't output compiler statistics")}, \
535 {"memcpy", MASK_MEMCPY, \
536 N_("Don't optimize block moves")}, \
537 {"no-memcpy", -MASK_MEMCPY, \
538 N_("Optimize block moves")}, \
539 {"mips-tfile", MASK_MIPS_TFILE, \
540 N_("Use mips-tfile asm postpass")}, \
541 {"no-mips-tfile", -MASK_MIPS_TFILE, \
542 N_("Don't use mips-tfile asm postpass")}, \
543 {"soft-float", MASK_SOFT_FLOAT, \
544 N_("Use software floating point")}, \
545 {"hard-float", -MASK_SOFT_FLOAT, \
546 N_("Use hardware floating point")}, \
547 {"fp64", MASK_FLOAT64, \
548 N_("Use 64-bit FP registers")}, \
549 {"fp32", -MASK_FLOAT64, \
550 N_("Use 32-bit FP registers")}, \
551 {"gp64", MASK_64BIT, \
552 N_("Use 64-bit general registers")}, \
553 {"gp32", -MASK_64BIT, \
554 N_("Use 32-bit general registers")}, \
555 {"abicalls", MASK_ABICALLS, \
556 N_("Use Irix PIC")}, \
557 {"no-abicalls", -MASK_ABICALLS, \
558 N_("Don't use Irix PIC")}, \
559 {"long-calls", MASK_LONG_CALLS, \
560 N_("Use indirect calls")}, \
561 {"no-long-calls", -MASK_LONG_CALLS, \
562 N_("Don't use indirect calls")}, \
563 {"embedded-pic", MASK_EMBEDDED_PIC, \
564 N_("Use embedded PIC")}, \
565 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
566 N_("Don't use embedded PIC")}, \
567 {"embedded-data", MASK_EMBEDDED_DATA, \
568 N_("Use ROM instead of RAM")}, \
569 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
570 N_("Don't use ROM instead of RAM")}, \
571 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
572 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
573 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
574 N_("Don't put uninitialized constants in ROM")}, \
575 {"eb", MASK_BIG_ENDIAN, \
576 N_("Use big-endian byte order")}, \
577 {"el", -MASK_BIG_ENDIAN, \
578 N_("Use little-endian byte order")}, \
579 {"single-float", MASK_SINGLE_FLOAT, \
580 N_("Use single (32-bit) FP only")}, \
581 {"double-float", -MASK_SINGLE_FLOAT, \
582 N_("Don't use single (32-bit) FP only")}, \
583 {"mad", MASK_MAD, \
584 N_("Use multiply accumulate")}, \
585 {"no-mad", -MASK_MAD, \
586 N_("Don't use multiply accumulate")}, \
587 {"no-fused-madd", MASK_NO_FUSED_MADD, \
588 N_("Don't generate fused multiply/add instructions")}, \
589 {"fused-madd", -MASK_NO_FUSED_MADD, \
590 N_("Generate fused multiply/add instructions")}, \
591 {"fix4300", MASK_4300_MUL_FIX, \
592 N_("Work around early 4300 hardware bug")}, \
593 {"no-fix4300", -MASK_4300_MUL_FIX, \
594 N_("Don't work around early 4300 hardware bug")}, \
595 {"fix-sb1", MASK_FIX_SB1, \
596 N_("Work around errata for early SB-1 revision 2 cores")}, \
597 {"no-fix-sb1", -MASK_FIX_SB1, \
598 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
599 {"fix-r4000", MASK_FIX_R4000, \
600 N_("Work around R4000 errata")}, \
601 {"no-fix-r4000", -MASK_FIX_R4000, \
602 N_("Don't work around R4000 errata")}, \
603 {"fix-r4400", MASK_FIX_R4400, \
604 N_("Work around R4400 errata")}, \
605 {"no-fix-r4400", -MASK_FIX_R4400, \
606 N_("Don't work around R4400 errata")}, \
607 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
608 N_("Trap on integer divide by zero")}, \
609 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
610 N_("Don't trap on integer divide by zero")}, \
611 { "branch-likely", MASK_BRANCHLIKELY, \
612 N_("Use Branch Likely instructions, overriding default for arch")}, \
613 { "no-branch-likely", -MASK_BRANCHLIKELY, \
614 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
615 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
616 N_("Use NewABI-style %reloc() assembly operators")}, \
617 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
618 N_("Use assembler macros instead of relocation operators")}, \
619 {"ips16", MASK_MIPS16, \
620 N_("Generate mips16 code") }, \
621 {"no-mips16", -MASK_MIPS16, \
622 N_("Generate normal-mode code") }, \
623 {"xgot", MASK_XGOT, \
624 N_("Lift restrictions on GOT size") }, \
625 {"no-xgot", -MASK_XGOT, \
626 N_("Do not lift restrictions on GOT size") }, \
627 {"debug", MASK_DEBUG, \
628 NULL}, \
629 {"debugc", MASK_DEBUG_C, \
630 NULL}, \
631 {"debugd", MASK_DEBUG_D, \
632 NULL}, \
633 {"debugg", MASK_DEBUG_G, \
634 NULL}, \
635 {"", (TARGET_DEFAULT \
636 | TARGET_CPU_DEFAULT \
637 | TARGET_ENDIAN_DEFAULT), \
638 NULL}, \
639 }
640
641 /* Default target_flags if no switches are specified */
642
643 #ifndef TARGET_DEFAULT
644 #define TARGET_DEFAULT 0
645 #endif
646
647 #ifndef TARGET_CPU_DEFAULT
648 #define TARGET_CPU_DEFAULT 0
649 #endif
650
651 #ifndef TARGET_ENDIAN_DEFAULT
652 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
653 #endif
654
655 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
656 #ifndef MIPS_ISA_DEFAULT
657 #ifndef MIPS_CPU_STRING_DEFAULT
658 #define MIPS_CPU_STRING_DEFAULT "from-abi"
659 #endif
660 #endif
661
662 #ifdef IN_LIBGCC2
663 #undef TARGET_64BIT
664 /* Make this compile time constant for libgcc2 */
665 #ifdef __mips64
666 #define TARGET_64BIT 1
667 #else
668 #define TARGET_64BIT 0
669 #endif
670 #endif /* IN_LIBGCC2 */
671
672 #ifndef MULTILIB_ENDIAN_DEFAULT
673 #if TARGET_ENDIAN_DEFAULT == 0
674 #define MULTILIB_ENDIAN_DEFAULT "EL"
675 #else
676 #define MULTILIB_ENDIAN_DEFAULT "EB"
677 #endif
678 #endif
679
680 #ifndef MULTILIB_ISA_DEFAULT
681 # if MIPS_ISA_DEFAULT == 1
682 # define MULTILIB_ISA_DEFAULT "mips1"
683 # else
684 # if MIPS_ISA_DEFAULT == 2
685 # define MULTILIB_ISA_DEFAULT "mips2"
686 # else
687 # if MIPS_ISA_DEFAULT == 3
688 # define MULTILIB_ISA_DEFAULT "mips3"
689 # else
690 # if MIPS_ISA_DEFAULT == 4
691 # define MULTILIB_ISA_DEFAULT "mips4"
692 # else
693 # if MIPS_ISA_DEFAULT == 32
694 # define MULTILIB_ISA_DEFAULT "mips32"
695 # else
696 # if MIPS_ISA_DEFAULT == 33
697 # define MULTILIB_ISA_DEFAULT "mips32r2"
698 # else
699 # if MIPS_ISA_DEFAULT == 64
700 # define MULTILIB_ISA_DEFAULT "mips64"
701 # else
702 # define MULTILIB_ISA_DEFAULT "mips1"
703 # endif
704 # endif
705 # endif
706 # endif
707 # endif
708 # endif
709 # endif
710 #endif
711
712 #ifndef MULTILIB_DEFAULTS
713 #define MULTILIB_DEFAULTS \
714 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
715 #endif
716
717 /* We must pass -EL to the linker by default for little endian embedded
718 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
719 linker will default to using big-endian output files. The OUTPUT_FORMAT
720 line must be in the linker script, otherwise -EB/-EL will not work. */
721
722 #ifndef ENDIAN_SPEC
723 #if TARGET_ENDIAN_DEFAULT == 0
724 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
725 #else
726 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
727 #endif
728 #endif
729
730 #define TARGET_OPTIONS \
731 { \
732 SUBTARGET_TARGET_OPTIONS \
733 { "tune=", &mips_tune_string, \
734 N_("Specify CPU for scheduling purposes"), 0}, \
735 { "arch=", &mips_arch_string, \
736 N_("Specify CPU for code generation purposes"), 0}, \
737 { "abi=", &mips_abi_string, \
738 N_("Specify an ABI"), 0}, \
739 { "ips", &mips_isa_string, \
740 N_("Specify a Standard MIPS ISA"), 0}, \
741 { "no-flush-func", &mips_cache_flush_func, \
742 N_("Don't call any cache flush functions"), 0}, \
743 { "flush-func=", &mips_cache_flush_func, \
744 N_("Specify cache flush function"), 0}, \
745 }
746
747 /* This is meant to be redefined in the host dependent files. */
748 #define SUBTARGET_TARGET_OPTIONS
749
750 /* Support for a compile-time default CPU, et cetera. The rules are:
751 --with-arch is ignored if -march is specified or a -mips is specified
752 (other than -mips16).
753 --with-tune is ignored if -mtune is specified.
754 --with-abi is ignored if -mabi is specified.
755 --with-float is ignored if -mhard-float or -msoft-float are
756 specified. */
757 #define OPTION_DEFAULT_SPECS \
758 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
759 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
760 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
761 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
762
763
764 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
765 && !TARGET_SR71K \
766 && !TARGET_MIPS16)
767
768 /* Generate three-operand multiply instructions for SImode. */
769 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
770 || TARGET_MIPS5400 \
771 || TARGET_MIPS5500 \
772 || TARGET_MIPS7000 \
773 || TARGET_MIPS9000 \
774 || ISA_MIPS32 \
775 || ISA_MIPS32R2 \
776 || ISA_MIPS64) \
777 && !TARGET_MIPS16)
778
779 /* Generate three-operand multiply instructions for DImode. */
780 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
781 && !TARGET_MIPS16)
782
783 /* Macros to decide whether certain features are available or not,
784 depending on the instruction set architecture level. */
785
786 #define HAVE_SQRT_P() (!ISA_MIPS1)
787
788 /* True if the ABI can only work with 64-bit integer registers. We
789 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
790 otherwise floating-point registers must also be 64-bit. */
791 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
792
793 /* Likewise for 32-bit regs. */
794 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
795
796 /* True if symbols are 64 bits wide. At present, n64 is the only
797 ABI for which this is true. */
798 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
799
800 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
801 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
802 || ISA_MIPS4 \
803 || ISA_MIPS64)
804
805 /* ISA has branch likely instructions (eg. mips2). */
806 /* Disable branchlikely for tx39 until compare rewrite. They haven't
807 been generated up to this point. */
808 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
809 && !TARGET_MIPS5500)
810
811 /* ISA has the conditional move instructions introduced in mips4. */
812 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
813 || ISA_MIPS32 \
814 || ISA_MIPS32R2 \
815 || ISA_MIPS64) \
816 && !TARGET_MIPS5500 \
817 && !TARGET_MIPS16)
818
819 /* ISA has just the integer condition move instructions (movn,movz) */
820 #define ISA_HAS_INT_CONDMOVE 0
821
822 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
823 branch on CC, and move (both FP and non-FP) on CC. */
824 #define ISA_HAS_8CC (ISA_MIPS4 \
825 || ISA_MIPS32 \
826 || ISA_MIPS32R2 \
827 || ISA_MIPS64)
828
829 /* This is a catch all for other mips4 instructions: indexed load, the
830 FP madd and msub instructions, and the FP recip and recip sqrt
831 instructions. */
832 #define ISA_HAS_FP4 ((ISA_MIPS4 \
833 || ISA_MIPS64) \
834 && !TARGET_MIPS16)
835
836 /* ISA has conditional trap instructions. */
837 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
838 && !TARGET_MIPS16)
839
840 /* ISA has integer multiply-accumulate instructions, madd and msub. */
841 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
842 || ISA_MIPS32R2 \
843 || ISA_MIPS64 \
844 ) && !TARGET_MIPS16)
845
846 /* ISA has floating-point nmadd and nmsub instructions. */
847 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
848 || ISA_MIPS64) \
849 && (!TARGET_MIPS5400 || TARGET_MAD) \
850 && ! TARGET_MIPS16)
851
852 /* ISA has count leading zeroes/ones instruction (not implemented). */
853 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
854 || ISA_MIPS32R2 \
855 || ISA_MIPS64 \
856 ) && !TARGET_MIPS16)
857
858 /* ISA has double-word count leading zeroes/ones instruction (not
859 implemented). */
860 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
861 && !TARGET_MIPS16)
862
863 /* ISA has three operand multiply instructions that put
864 the high part in an accumulator: mulhi or mulhiu. */
865 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
866 || TARGET_MIPS5500 \
867 || TARGET_SR71K \
868 )
869
870 /* ISA has three operand multiply instructions that
871 negates the result and puts the result in an accumulator. */
872 #define ISA_HAS_MULS (TARGET_MIPS5400 \
873 || TARGET_MIPS5500 \
874 || TARGET_SR71K \
875 )
876
877 /* ISA has three operand multiply instructions that subtracts the
878 result from a 4th operand and puts the result in an accumulator. */
879 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
880 || TARGET_MIPS5500 \
881 || TARGET_SR71K \
882 )
883 /* ISA has three operand multiply instructions that the result
884 from a 4th operand and puts the result in an accumulator. */
885 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
886 || TARGET_MIPS5400 \
887 || TARGET_MIPS5500 \
888 || TARGET_SR71K \
889 )
890
891 /* ISA has 32-bit rotate right instruction. */
892 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
893 && (ISA_MIPS32R2 \
894 || TARGET_MIPS5400 \
895 || TARGET_MIPS5500 \
896 || TARGET_SR71K \
897 ))
898
899 /* ISA has 64-bit rotate right instruction. */
900 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
901 && !TARGET_MIPS16 \
902 && (TARGET_MIPS5400 \
903 || TARGET_MIPS5500 \
904 || TARGET_SR71K \
905 ))
906
907 /* ISA has data prefetch instructions. This controls use of 'pref'. */
908 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
909 || ISA_MIPS32 \
910 || ISA_MIPS32R2 \
911 || ISA_MIPS64) \
912 && !TARGET_MIPS16)
913
914 /* ISA has data indexed prefetch instructions. This controls use of
915 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
916 (prefx is a cop1x instruction, so can only be used if FP is
917 enabled.) */
918 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
919 || ISA_MIPS64) \
920 && !TARGET_MIPS16)
921
922 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
923 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
924 also requires TARGET_DOUBLE_FLOAT. */
925 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
926
927 /* ISA includes the MIPS32r2 seb and seh instructions. */
928 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
929 && (ISA_MIPS32R2 \
930 ))
931
932 /* True if the result of a load is not available to the next instruction.
933 A nop will then be needed between instructions like "lw $4,..."
934 and "addiu $4,$4,1". */
935 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
936 && !TARGET_MIPS3900 \
937 && !TARGET_MIPS16)
938
939 /* Likewise mtc1 and mfc1. */
940 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
941
942 /* Likewise floating-point comparisons. */
943 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
944
945 /* True if mflo and mfhi can be immediately followed by instructions
946 which write to the HI and LO registers.
947
948 According to MIPS specifications, MIPS ISAs I, II, and III need
949 (at least) two instructions between the reads of HI/LO and
950 instructions which write them, and later ISAs do not. Contradicting
951 the MIPS specifications, some MIPS IV processor user manuals (e.g.
952 the UM for the NEC Vr5000) document needing the instructions between
953 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
954 MIPS64 and later ISAs to have the interlocks, plus any specific
955 earlier-ISA CPUs for which CPU documentation declares that the
956 instructions are really interlocked. */
957 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
958 || ISA_MIPS32R2 \
959 || ISA_MIPS64 \
960 || TARGET_MIPS5500)
961 \f
962 /* Add -G xx support. */
963
964 #undef SWITCH_TAKES_ARG
965 #define SWITCH_TAKES_ARG(CHAR) \
966 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
967
968 #define OVERRIDE_OPTIONS override_options ()
969
970 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
971
972 /* Show we can debug even without a frame pointer. */
973 #define CAN_DEBUG_WITHOUT_FP
974 \f
975 /* Tell collect what flags to pass to nm. */
976 #ifndef NM_FLAGS
977 #define NM_FLAGS "-Bn"
978 #endif
979
980 \f
981 /* Assembler specs. */
982
983 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
984 than gas. */
985
986 #define MIPS_AS_ASM_SPEC "\
987 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
988 %{pipe: %e-pipe is not supported} \
989 %{K} %(subtarget_mips_as_asm_spec)"
990
991 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
992 rather than gas. It may be overridden by subtargets. */
993
994 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
995 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
996 #endif
997
998 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
999 assembler. */
1000
1001 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
1002
1003 #define SUBTARGET_TARGET_SWITCHES
1004
1005 #ifndef MIPS_ABI_DEFAULT
1006 #define MIPS_ABI_DEFAULT ABI_32
1007 #endif
1008
1009 /* Use the most portable ABI flag for the ASM specs. */
1010
1011 #if MIPS_ABI_DEFAULT == ABI_32
1012 #define MULTILIB_ABI_DEFAULT "mabi=32"
1013 #define ASM_ABI_DEFAULT_SPEC "-32"
1014 #endif
1015
1016 #if MIPS_ABI_DEFAULT == ABI_O64
1017 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1018 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
1019 #endif
1020
1021 #if MIPS_ABI_DEFAULT == ABI_N32
1022 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1023 #define ASM_ABI_DEFAULT_SPEC "-n32"
1024 #endif
1025
1026 #if MIPS_ABI_DEFAULT == ABI_64
1027 #define MULTILIB_ABI_DEFAULT "mabi=64"
1028 #define ASM_ABI_DEFAULT_SPEC "-64"
1029 #endif
1030
1031 #if MIPS_ABI_DEFAULT == ABI_EABI
1032 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1033 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1034 #endif
1035
1036 /* Only ELF targets can switch the ABI. */
1037 #ifndef OBJECT_FORMAT_ELF
1038 #undef ASM_ABI_DEFAULT_SPEC
1039 #define ASM_ABI_DEFAULT_SPEC ""
1040 #endif
1041
1042 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1043 GAS_ASM_SPEC as the default, depending upon the value of
1044 TARGET_DEFAULT. */
1045
1046 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1047 /* GAS */
1048
1049 #define TARGET_ASM_SPEC "\
1050 %{mmips-as: %(mips_as_asm_spec)} \
1051 %{!mmips-as: %(gas_asm_spec)}"
1052
1053 #else /* not GAS */
1054
1055 #define TARGET_ASM_SPEC "\
1056 %{!mgas: %(mips_as_asm_spec)} \
1057 %{mgas: %(gas_asm_spec)}"
1058
1059 #endif /* not GAS */
1060
1061 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1062 to the assembler. It may be overridden by subtargets. */
1063 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1064 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1065 %{noasmopt:-O0} \
1066 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1067 #endif
1068
1069 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1070 the assembler. It may be overridden by subtargets. */
1071 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1072 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1073 %{g} %{g0} %{g1} %{g2} %{g3} \
1074 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1075 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1076 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1077 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1078 %(mdebug_asm_spec)"
1079 #endif
1080
1081 /* Beginning with gas 2.13, -mdebug must be passed to correctly handle COFF
1082 debugging info. */
1083 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1084 /* GAS */
1085 #define MDEBUG_ASM_SPEC "%{gcoff*:-mdebug} \
1086 %{!gcoff*:-no-mdebug}"
1087 #else /* not GAS */
1088 #define MDEBUG_ASM_SPEC ""
1089 #endif /* not GAS */
1090
1091 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1092 overridden by subtargets. */
1093
1094 #ifndef SUBTARGET_ASM_SPEC
1095 #define SUBTARGET_ASM_SPEC ""
1096 #endif
1097
1098 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1099 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1100 whether we're using GAS. These options can only be used properly
1101 with GAS, and it is better to get an error from a non-GAS assembler
1102 than to silently generate bad code. */
1103
1104 #undef ASM_SPEC
1105 #define ASM_SPEC "\
1106 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1107 %{mips32} %{mips32r2} %{mips64} \
1108 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1109 %(subtarget_asm_optimizing_spec) \
1110 %(subtarget_asm_debugging_spec) \
1111 %{membedded-pic} \
1112 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1113 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1114 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1115 %(target_asm_spec) \
1116 %(subtarget_asm_spec)"
1117
1118 /* Extra switches sometimes passed to the linker. */
1119 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1120 will interpret it as a -b option. */
1121
1122 #ifndef LINK_SPEC
1123 #define LINK_SPEC "\
1124 %(endian_spec) \
1125 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1126 %{bestGnum} %{shared} %{non_shared}"
1127 #endif /* LINK_SPEC defined */
1128
1129
1130 /* Specs for the compiler proper */
1131
1132 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1133 overridden by subtargets. */
1134 #ifndef SUBTARGET_CC1_SPEC
1135 #define SUBTARGET_CC1_SPEC ""
1136 #endif
1137
1138 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1139
1140 #ifndef CC1_SPEC
1141 #define CC1_SPEC "\
1142 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1143 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1144 %{save-temps: } \
1145 %(subtarget_cc1_spec)"
1146 #endif
1147
1148 /* Preprocessor specs. */
1149
1150 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1151 overridden by subtargets. */
1152 #ifndef SUBTARGET_CPP_SPEC
1153 #define SUBTARGET_CPP_SPEC ""
1154 #endif
1155
1156 #define CPP_SPEC "%(subtarget_cpp_spec)"
1157
1158 /* This macro defines names of additional specifications to put in the specs
1159 that can be used in various specifications like CC1_SPEC. Its definition
1160 is an initializer with a subgrouping for each command option.
1161
1162 Each subgrouping contains a string constant, that defines the
1163 specification name, and a string constant that used by the GCC driver
1164 program.
1165
1166 Do not define this macro if it does not need to do anything. */
1167
1168 #define EXTRA_SPECS \
1169 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1170 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1171 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1172 { "gas_asm_spec", GAS_ASM_SPEC }, \
1173 { "target_asm_spec", TARGET_ASM_SPEC }, \
1174 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1175 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1176 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1177 { "mdebug_asm_spec", MDEBUG_ASM_SPEC }, \
1178 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1179 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1180 { "endian_spec", ENDIAN_SPEC }, \
1181 SUBTARGET_EXTRA_SPECS
1182
1183 #ifndef SUBTARGET_EXTRA_SPECS
1184 #define SUBTARGET_EXTRA_SPECS
1185 #endif
1186
1187 /* If defined, this macro is an additional prefix to try after
1188 `STANDARD_EXEC_PREFIX'. */
1189
1190 #ifndef MD_EXEC_PREFIX
1191 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1192 #endif
1193
1194 #ifndef MD_STARTFILE_PREFIX
1195 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1196 #endif
1197
1198 \f
1199 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1200 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1201 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1202
1203 #ifndef PREFERRED_DEBUGGING_TYPE
1204 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1205 #endif
1206
1207 /* By default, turn on GDB extensions. */
1208 #define DEFAULT_GDB_EXTENSIONS 1
1209
1210 /* If we are passing smuggling stabs through the MIPS ECOFF object
1211 format, put a comment in front of the .stab<x> operation so
1212 that the MIPS assembler does not choke. The mips-tfile program
1213 will correctly put the stab into the object file. */
1214
1215 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1216 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1217 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1218
1219 /* Local compiler-generated symbols must have a prefix that the assembler
1220 understands. By default, this is $, although some targets (e.g.,
1221 NetBSD-ELF) need to override this. */
1222
1223 #ifndef LOCAL_LABEL_PREFIX
1224 #define LOCAL_LABEL_PREFIX "$"
1225 #endif
1226
1227 /* By default on the mips, external symbols do not have an underscore
1228 prepended, but some targets (e.g., NetBSD) require this. */
1229
1230 #ifndef USER_LABEL_PREFIX
1231 #define USER_LABEL_PREFIX ""
1232 #endif
1233
1234 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1235 since the length can run past this up to a continuation point. */
1236 #undef DBX_CONTIN_LENGTH
1237 #define DBX_CONTIN_LENGTH 1500
1238
1239 /* How to renumber registers for dbx and gdb. */
1240 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1241
1242 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1243 #define DWARF_FRAME_REGNUM(REG) (REG)
1244
1245 /* The DWARF 2 CFA column which tracks the return address. */
1246 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1247
1248 /* The DWARF 2 CFA column which tracks the return address from a
1249 signal handler context. */
1250 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1251
1252 /* Before the prologue, RA lives in r31. */
1253 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1254
1255 /* Describe how we implement __builtin_eh_return. */
1256 #define EH_RETURN_DATA_REGNO(N) \
1257 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1258
1259 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1260
1261 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1262 The default for this in 64-bit mode is 8, which causes problems with
1263 SFmode register saves. */
1264 #define DWARF_CIE_DATA_ALIGNMENT 4
1265
1266 /* Correct the offset of automatic variables and arguments. Note that
1267 the MIPS debug format wants all automatic variables and arguments
1268 to be in terms of the virtual frame pointer (stack pointer before
1269 any adjustment in the function), while the MIPS 3.0 linker wants
1270 the frame pointer to be the stack pointer after the initial
1271 adjustment. */
1272
1273 #define DEBUGGER_AUTO_OFFSET(X) \
1274 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1275 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1276 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1277 \f
1278 /* Target machine storage layout */
1279
1280 #define BITS_BIG_ENDIAN 0
1281 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1282 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1283
1284 /* Define this to set the endianness to use in libgcc2.c, which can
1285 not depend on target_flags. */
1286 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1287 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1288 #else
1289 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1290 #endif
1291
1292 #define MAX_BITS_PER_WORD 64
1293
1294 /* Width of a word, in units (bytes). */
1295 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1296 #define MIN_UNITS_PER_WORD 4
1297
1298 /* For MIPS, width of a floating point register. */
1299 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1300
1301 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1302 the next available register. */
1303 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1304
1305 /* The largest size of value that can be held in floating-point
1306 registers and moved with a single instruction. */
1307 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1308
1309 /* The largest size of value that can be held in floating-point
1310 registers. */
1311 #define UNITS_PER_FPVALUE \
1312 (TARGET_SOFT_FLOAT ? 0 : (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT))
1313
1314 /* The number of bytes in a double. */
1315 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1316
1317 /* Set the sizes of the core types. */
1318 #define SHORT_TYPE_SIZE 16
1319 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1320 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1321 #define LONG_LONG_TYPE_SIZE 64
1322
1323 #define FLOAT_TYPE_SIZE 32
1324 #define DOUBLE_TYPE_SIZE 64
1325 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1326
1327 /* long double is not a fixed mode, but the idea is that, if we
1328 support long double, we also want a 128-bit integer type. */
1329 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1330
1331 #ifdef IN_LIBGCC2
1332 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1333 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1334 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1335 # else
1336 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1337 # endif
1338 #endif
1339
1340 /* Width in bits of a pointer. */
1341 #ifndef POINTER_SIZE
1342 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1343 #endif
1344
1345 #define POINTERS_EXTEND_UNSIGNED 0
1346
1347 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1348 #define PARM_BOUNDARY ((mips_abi == ABI_O64 \
1349 || TARGET_NEWABI \
1350 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1351
1352
1353 /* Allocation boundary (in *bits*) for the code of a function. */
1354 #define FUNCTION_BOUNDARY 32
1355
1356 /* Alignment of field after `int : 0' in a structure. */
1357 #define EMPTY_FIELD_BOUNDARY 32
1358
1359 /* Every structure's size must be a multiple of this. */
1360 /* 8 is observed right on a DECstation and on riscos 4.02. */
1361 #define STRUCTURE_SIZE_BOUNDARY 8
1362
1363 /* There is no point aligning anything to a rounder boundary than this. */
1364 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1365
1366 /* All accesses must be aligned. */
1367 #define STRICT_ALIGNMENT 1
1368
1369 /* Define this if you wish to imitate the way many other C compilers
1370 handle alignment of bitfields and the structures that contain
1371 them.
1372
1373 The behavior is that the type written for a bit-field (`int',
1374 `short', or other integer type) imposes an alignment for the
1375 entire structure, as if the structure really did contain an
1376 ordinary field of that type. In addition, the bit-field is placed
1377 within the structure so that it would fit within such a field,
1378 not crossing a boundary for it.
1379
1380 Thus, on most machines, a bit-field whose type is written as `int'
1381 would not cross a four-byte boundary, and would force four-byte
1382 alignment for the whole structure. (The alignment used may not
1383 be four bytes; it is controlled by the other alignment
1384 parameters.)
1385
1386 If the macro is defined, its definition should be a C expression;
1387 a nonzero value for the expression enables this behavior. */
1388
1389 #define PCC_BITFIELD_TYPE_MATTERS 1
1390
1391 /* If defined, a C expression to compute the alignment given to a
1392 constant that is being placed in memory. CONSTANT is the constant
1393 and ALIGN is the alignment that the object would ordinarily have.
1394 The value of this macro is used instead of that alignment to align
1395 the object.
1396
1397 If this macro is not defined, then ALIGN is used.
1398
1399 The typical use of this macro is to increase alignment for string
1400 constants to be word aligned so that `strcpy' calls that copy
1401 constants can be done inline. */
1402
1403 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1404 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1405 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1406
1407 /* If defined, a C expression to compute the alignment for a static
1408 variable. TYPE is the data type, and ALIGN is the alignment that
1409 the object would ordinarily have. The value of this macro is used
1410 instead of that alignment to align the object.
1411
1412 If this macro is not defined, then ALIGN is used.
1413
1414 One use of this macro is to increase alignment of medium-size
1415 data to make it all fit in fewer cache lines. Another is to
1416 cause character arrays to be word-aligned so that `strcpy' calls
1417 that copy constants to character arrays can be done inline. */
1418
1419 #undef DATA_ALIGNMENT
1420 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1421 ((((ALIGN) < BITS_PER_WORD) \
1422 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1423 || TREE_CODE (TYPE) == UNION_TYPE \
1424 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1425
1426
1427 #define PAD_VARARGS_DOWN \
1428 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1429
1430 /* Define if operations between registers always perform the operation
1431 on the full register even if a narrower mode is specified. */
1432 #define WORD_REGISTER_OPERATIONS
1433
1434 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1435 moves. All other references are zero extended. */
1436 #define LOAD_EXTEND_OP(MODE) \
1437 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1438 ? SIGN_EXTEND : ZERO_EXTEND)
1439
1440 /* Define this macro if it is advisable to hold scalars in registers
1441 in a wider mode than that declared by the program. In such cases,
1442 the value is constrained to be within the bounds of the declared
1443 type, but kept valid in the wider mode. The signedness of the
1444 extension may differ from that of the type. */
1445
1446 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1447 if (GET_MODE_CLASS (MODE) == MODE_INT \
1448 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1449 { \
1450 if ((MODE) == SImode) \
1451 (UNSIGNEDP) = 0; \
1452 (MODE) = Pmode; \
1453 }
1454
1455 /* Define if loading short immediate values into registers sign extends. */
1456 #define SHORT_IMMEDIATES_SIGN_EXTEND
1457 \f
1458 /* Standard register usage. */
1459
1460 /* Number of hardware registers. We have:
1461
1462 - 32 integer registers
1463 - 32 floating point registers
1464 - 8 condition code registers
1465 - 2 accumulator registers (hi and lo)
1466 - 32 registers each for coprocessors 0, 2 and 3
1467 - 3 fake registers:
1468 - ARG_POINTER_REGNUM
1469 - FRAME_POINTER_REGNUM
1470 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1471 - 3 dummy entries that were used at various times in the past. */
1472
1473 #define FIRST_PSEUDO_REGISTER 176
1474
1475 /* By default, fix the kernel registers ($26 and $27), the global
1476 pointer ($28) and the stack pointer ($29). This can change
1477 depending on the command-line options.
1478
1479 Regarding coprocessor registers: without evidence to the contrary,
1480 it's best to assume that each coprocessor register has a unique
1481 use. This can be overridden, in, e.g., override_options() or
1482 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1483 for a particular target. */
1484
1485 #define FIXED_REGISTERS \
1486 { \
1487 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1488 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1489 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1490 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1491 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1492 /* COP0 registers */ \
1493 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1494 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1495 /* COP2 registers */ \
1496 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1497 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1498 /* COP3 registers */ \
1499 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1500 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1501 }
1502
1503
1504 /* Set up this array for o32 by default.
1505
1506 Note that we don't mark $31 as a call-clobbered register. The idea is
1507 that it's really the call instructions themselves which clobber $31.
1508 We don't care what the called function does with it afterwards.
1509
1510 This approach makes it easier to implement sibcalls. Unlike normal
1511 calls, sibcalls don't clobber $31, so the register reaches the
1512 called function in tact. EPILOGUE_USES says that $31 is useful
1513 to the called function. */
1514
1515 #define CALL_USED_REGISTERS \
1516 { \
1517 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1518 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1519 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1520 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1521 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1522 /* COP0 registers */ \
1523 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1524 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1525 /* COP2 registers */ \
1526 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1527 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1528 /* COP3 registers */ \
1529 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1531 }
1532
1533
1534 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1535
1536 #define CALL_REALLY_USED_REGISTERS \
1537 { /* General registers. */ \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1540 /* Floating-point registers. */ \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1542 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1543 /* Others. */ \
1544 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1545 /* COP0 registers */ \
1546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1548 /* COP2 registers */ \
1549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1551 /* COP3 registers */ \
1552 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1553 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1554 }
1555
1556 /* Internal macros to classify a register number as to whether it's a
1557 general purpose register, a floating point register, a
1558 multiply/divide register, or a status register. */
1559
1560 #define GP_REG_FIRST 0
1561 #define GP_REG_LAST 31
1562 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1563 #define GP_DBX_FIRST 0
1564
1565 #define FP_REG_FIRST 32
1566 #define FP_REG_LAST 63
1567 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1568 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1569
1570 #define MD_REG_FIRST 64
1571 #define MD_REG_LAST 65
1572 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1573 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1574
1575 #define ST_REG_FIRST 67
1576 #define ST_REG_LAST 74
1577 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1578
1579
1580 /* FIXME: renumber. */
1581 #define COP0_REG_FIRST 80
1582 #define COP0_REG_LAST 111
1583 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1584
1585 #define COP2_REG_FIRST 112
1586 #define COP2_REG_LAST 143
1587 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1588
1589 #define COP3_REG_FIRST 144
1590 #define COP3_REG_LAST 175
1591 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1592 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1593 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1594
1595 #define AT_REGNUM (GP_REG_FIRST + 1)
1596 #define HI_REGNUM (MD_REG_FIRST + 0)
1597 #define LO_REGNUM (MD_REG_FIRST + 1)
1598
1599 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1600 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1601 should be used instead. */
1602 #define FPSW_REGNUM ST_REG_FIRST
1603
1604 #define GP_REG_P(REGNO) \
1605 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1606 #define M16_REG_P(REGNO) \
1607 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1608 #define FP_REG_P(REGNO) \
1609 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1610 #define MD_REG_P(REGNO) \
1611 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1612 #define ST_REG_P(REGNO) \
1613 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1614 #define COP0_REG_P(REGNO) \
1615 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1616 #define COP2_REG_P(REGNO) \
1617 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1618 #define COP3_REG_P(REGNO) \
1619 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1620 #define ALL_COP_REG_P(REGNO) \
1621 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1622
1623 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1624
1625 /* Return coprocessor number from register number. */
1626
1627 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1628 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1629 : COP3_REG_P (REGNO) ? '3' : '?')
1630
1631
1632 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1633
1634 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1635 array built in override_options. Because machmodes.h is not yet
1636 included before this file is processed, the MODE bound can't be
1637 expressed here. */
1638
1639 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1640
1641 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1642 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1643
1644 /* Value is 1 if it is a good idea to tie two pseudo registers
1645 when one has mode MODE1 and one has mode MODE2.
1646 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1647 for any hard reg, then this must be 0 for correct output. */
1648 #define MODES_TIEABLE_P(MODE1, MODE2) \
1649 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1650 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1651 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1652 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1653
1654 /* Register to use for pushing function arguments. */
1655 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1656
1657 /* These two registers don't really exist: they get eliminated to either
1658 the stack or hard frame pointer. */
1659 #define ARG_POINTER_REGNUM 77
1660 #define FRAME_POINTER_REGNUM 78
1661
1662 /* $30 is not available on the mips16, so we use $17 as the frame
1663 pointer. */
1664 #define HARD_FRAME_POINTER_REGNUM \
1665 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1666
1667 /* Value should be nonzero if functions must have frame pointers.
1668 Zero means the frame pointer need not be set up (and parms
1669 may be accessed via the stack pointer) in functions that seem suitable.
1670 This is computed in `reload', in reload1.c. */
1671 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1672
1673 /* Register in which static-chain is passed to a function. */
1674 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1675
1676 /* Registers used as temporaries in prologue/epilogue code. If we're
1677 generating mips16 code, these registers must come from the core set
1678 of 8. The prologue register mustn't conflict with any incoming
1679 arguments, the static chain pointer, or the frame pointer. The
1680 epilogue temporary mustn't conflict with the return registers, the
1681 frame pointer, the EH stack adjustment, or the EH data registers. */
1682
1683 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1684 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1685
1686 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1687 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1688
1689 /* Define this macro if it is as good or better to call a constant
1690 function address than to call an address kept in a register. */
1691 #define NO_FUNCTION_CSE 1
1692
1693 /* Define this macro if it is as good or better for a function to
1694 call itself with an explicit address than to call an address
1695 kept in a register. */
1696 #define NO_RECURSIVE_FUNCTION_CSE 1
1697
1698 /* The ABI-defined global pointer. Sometimes we use a different
1699 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1700 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1701
1702 /* We normally use $28 as the global pointer. However, when generating
1703 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1704 register instead. They can then avoid saving and restoring $28
1705 and perhaps avoid using a frame at all.
1706
1707 When a leaf function uses something other than $28, mips_expand_prologue
1708 will modify pic_offset_table_rtx in place. Take the register number
1709 from there after reload. */
1710 #define PIC_OFFSET_TABLE_REGNUM \
1711 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1712
1713 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1714 \f
1715 /* Define the classes of registers for register constraints in the
1716 machine description. Also define ranges of constants.
1717
1718 One of the classes must always be named ALL_REGS and include all hard regs.
1719 If there is more than one class, another class must be named NO_REGS
1720 and contain no registers.
1721
1722 The name GENERAL_REGS must be the name of a class (or an alias for
1723 another name such as ALL_REGS). This is the class of registers
1724 that is allowed by "g" or "r" in a register constraint.
1725 Also, registers outside this class are allocated only when
1726 instructions express preferences for them.
1727
1728 The classes must be numbered in nondecreasing order; that is,
1729 a larger-numbered class must never be contained completely
1730 in a smaller-numbered class.
1731
1732 For any two classes, it is very desirable that there be another
1733 class that represents their union. */
1734
1735 enum reg_class
1736 {
1737 NO_REGS, /* no registers in set */
1738 M16_NA_REGS, /* mips16 regs not used to pass args */
1739 M16_REGS, /* mips16 directly accessible registers */
1740 T_REG, /* mips16 T register ($24) */
1741 M16_T_REGS, /* mips16 registers plus T register */
1742 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1743 LEA_REGS, /* Every GPR except $25 */
1744 GR_REGS, /* integer registers */
1745 FP_REGS, /* floating point registers */
1746 HI_REG, /* hi register */
1747 LO_REG, /* lo register */
1748 MD_REGS, /* multiply/divide registers (hi/lo) */
1749 COP0_REGS, /* generic coprocessor classes */
1750 COP2_REGS,
1751 COP3_REGS,
1752 HI_AND_GR_REGS, /* union classes */
1753 LO_AND_GR_REGS,
1754 HI_AND_FP_REGS,
1755 COP0_AND_GR_REGS,
1756 COP2_AND_GR_REGS,
1757 COP3_AND_GR_REGS,
1758 ALL_COP_REGS,
1759 ALL_COP_AND_GR_REGS,
1760 ST_REGS, /* status registers (fp status) */
1761 ALL_REGS, /* all registers */
1762 LIM_REG_CLASSES /* max value + 1 */
1763 };
1764
1765 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1766
1767 #define GENERAL_REGS GR_REGS
1768
1769 /* An initializer containing the names of the register classes as C
1770 string constants. These names are used in writing some of the
1771 debugging dumps. */
1772
1773 #define REG_CLASS_NAMES \
1774 { \
1775 "NO_REGS", \
1776 "M16_NA_REGS", \
1777 "M16_REGS", \
1778 "T_REG", \
1779 "M16_T_REGS", \
1780 "PIC_FN_ADDR_REG", \
1781 "LEA_REGS", \
1782 "GR_REGS", \
1783 "FP_REGS", \
1784 "HI_REG", \
1785 "LO_REG", \
1786 "MD_REGS", \
1787 /* coprocessor registers */ \
1788 "COP0_REGS", \
1789 "COP2_REGS", \
1790 "COP3_REGS", \
1791 "HI_AND_GR_REGS", \
1792 "LO_AND_GR_REGS", \
1793 "HI_AND_FP_REGS", \
1794 "COP0_AND_GR_REGS", \
1795 "COP2_AND_GR_REGS", \
1796 "COP3_AND_GR_REGS", \
1797 "ALL_COP_REGS", \
1798 "ALL_COP_AND_GR_REGS", \
1799 "ST_REGS", \
1800 "ALL_REGS" \
1801 }
1802
1803 /* An initializer containing the contents of the register classes,
1804 as integers which are bit masks. The Nth integer specifies the
1805 contents of class N. The way the integer MASK is interpreted is
1806 that register R is in the class if `MASK & (1 << R)' is 1.
1807
1808 When the machine has more than 32 registers, an integer does not
1809 suffice. Then the integers are replaced by sub-initializers,
1810 braced groupings containing several integers. Each
1811 sub-initializer must be suitable as an initializer for the type
1812 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1813
1814 #define REG_CLASS_CONTENTS \
1815 { \
1816 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1817 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1818 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1819 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1820 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1821 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1822 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1823 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1824 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1825 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1826 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1827 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1828 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1829 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1830 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1831 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1832 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1833 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1834 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1835 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1836 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1837 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1838 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1839 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1840 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1841 }
1842
1843
1844 /* A C expression whose value is a register class containing hard
1845 register REGNO. In general there is more that one such class;
1846 choose a class which is "minimal", meaning that no smaller class
1847 also contains the register. */
1848
1849 extern const enum reg_class mips_regno_to_class[];
1850
1851 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1852
1853 /* A macro whose definition is the name of the class to which a
1854 valid base register must belong. A base register is one used in
1855 an address which is the register value plus a displacement. */
1856
1857 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1858
1859 /* A macro whose definition is the name of the class to which a
1860 valid index register must belong. An index register is one used
1861 in an address where its value is either multiplied by a scale
1862 factor or added to another register (as well as added to a
1863 displacement). */
1864
1865 #define INDEX_REG_CLASS NO_REGS
1866
1867 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1868 registers explicitly used in the rtl to be used as spill registers
1869 but prevents the compiler from extending the lifetime of these
1870 registers. */
1871
1872 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1873
1874 /* This macro is used later on in the file. */
1875 #define GR_REG_CLASS_P(CLASS) \
1876 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1877 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1878 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1879
1880 /* This macro is also used later on in the file. */
1881 #define COP_REG_CLASS_P(CLASS) \
1882 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1883
1884 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1885 is the default value (allocate the registers in numeric order). We
1886 define it just so that we can override it for the mips16 target in
1887 ORDER_REGS_FOR_LOCAL_ALLOC. */
1888
1889 #define REG_ALLOC_ORDER \
1890 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1891 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1892 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1893 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1894 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1895 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1896 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1897 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1898 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1899 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1900 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1901 }
1902
1903 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1904 to be rearranged based on a particular function. On the mips16, we
1905 want to allocate $24 (T_REG) before other registers for
1906 instructions for which it is possible. */
1907
1908 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1909
1910 /* REGISTER AND CONSTANT CLASSES */
1911
1912 /* Get reg_class from a letter such as appears in the machine
1913 description.
1914
1915 DEFINED REGISTER CLASSES:
1916
1917 'd' General (aka integer) registers
1918 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1919 'y' General registers (in both mips16 and non mips16 mode)
1920 'e' Effective address registers (general registers except $25)
1921 't' mips16 temporary register ($24)
1922 'f' Floating point registers
1923 'h' Hi register
1924 'l' Lo register
1925 'x' Multiply/divide registers
1926 'z' FP Status register
1927 'B' Cop0 register
1928 'C' Cop2 register
1929 'D' Cop3 register
1930 'b' All registers */
1931
1932 extern enum reg_class mips_char_to_class[256];
1933
1934 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1935
1936 /* True if VALUE is a signed 16-bit number. */
1937
1938 #define SMALL_OPERAND(VALUE) \
1939 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1940
1941 /* True if VALUE is an unsigned 16-bit number. */
1942
1943 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1944 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1945
1946 /* True if VALUE can be loaded into a register using LUI. */
1947
1948 #define LUI_OPERAND(VALUE) \
1949 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1950 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1951
1952 /* Return a value X with the low 16 bits clear, and such that
1953 VALUE - X is a signed 16-bit value. */
1954
1955 #define CONST_HIGH_PART(VALUE) \
1956 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1957
1958 #define CONST_LOW_PART(VALUE) \
1959 ((VALUE) - CONST_HIGH_PART (VALUE))
1960
1961 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1962 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1963 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1964
1965 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1966 string can be used to stand for particular ranges of immediate
1967 operands. This macro defines what the ranges are. C is the
1968 letter, and VALUE is a constant value. Return 1 if VALUE is
1969 in the range specified by C. */
1970
1971 /* For MIPS:
1972
1973 `I' is used for the range of constants an arithmetic insn can
1974 actually contain (16 bits signed integers).
1975
1976 `J' is used for the range which is just zero (ie, $r0).
1977
1978 `K' is used for the range of constants a logical insn can actually
1979 contain (16 bit zero-extended integers).
1980
1981 `L' is used for the range of constants that be loaded with lui
1982 (ie, the bottom 16 bits are zero).
1983
1984 `M' is used for the range of constants that take two words to load
1985 (ie, not matched by `I', `K', and `L').
1986
1987 `N' is used for negative 16 bit constants other than -65536.
1988
1989 `O' is a 15 bit signed integer.
1990
1991 `P' is used for positive 16 bit constants. */
1992
1993 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1994 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1995 : (C) == 'J' ? ((VALUE) == 0) \
1996 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1997 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1998 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1999 && !SMALL_OPERAND_UNSIGNED (VALUE) \
2000 && !LUI_OPERAND (VALUE)) \
2001 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2002 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2003 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2004 : 0)
2005
2006 /* Similar, but for floating constants, and defining letters G and H.
2007 Here VALUE is the CONST_DOUBLE rtx itself. */
2008
2009 /* For Mips
2010
2011 'G' : Floating point 0 */
2012
2013 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2014 ((C) == 'G' \
2015 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2016
2017 /* Letters in the range `Q' through `U' may be defined in a
2018 machine-dependent fashion to stand for arbitrary operand types.
2019 The machine description macro `EXTRA_CONSTRAINT' is passed the
2020 operand as its first argument and the constraint letter as its
2021 second operand.
2022
2023 `Q' is for signed 16-bit constants.
2024 `R' is for single-instruction memory references. Note that this
2025 constraint has often been used in linux and glibc code.
2026 `S' is for legitimate constant call addresses.
2027 `T' is for constant move_operands that cannot be safely loaded into $25.
2028 `U' is for constant move_operands that can be safely loaded into $25.
2029 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2030 This is true for all non-mips16 references (although it can somtimes
2031 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2032 stack and constant-pool references. */
2033
2034 #define EXTRA_CONSTRAINT(OP,CODE) \
2035 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2036 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
2037 && mips_fetch_insns (OP) == 1) \
2038 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2039 && call_insn_operand (OP, VOIDmode)) \
2040 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2041 && move_operand (OP, VOIDmode) \
2042 && mips_dangerous_for_la25_p (OP)) \
2043 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2044 && move_operand (OP, VOIDmode) \
2045 && !mips_dangerous_for_la25_p (OP)) \
2046 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2047 && memory_operand (OP, VOIDmode) \
2048 && (!TARGET_MIPS16 \
2049 || (!stack_operand (OP, VOIDmode) \
2050 && !CONSTANT_P (XEXP (OP, 0))))) \
2051 : FALSE)
2052
2053 /* Say which of the above are memory constraints. */
2054 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2055
2056 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2057 mips_preferred_reload_class (X, CLASS)
2058
2059 /* Certain machines have the property that some registers cannot be
2060 copied to some other registers without using memory. Define this
2061 macro on those machines to be a C expression that is nonzero if
2062 objects of mode MODE in registers of CLASS1 can only be copied to
2063 registers of class CLASS2 by storing a register of CLASS1 into
2064 memory and loading that memory location into a register of CLASS2.
2065
2066 Do not define this macro if its value would always be zero. */
2067 #if 0
2068 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2069 ((!TARGET_DEBUG_H_MODE \
2070 && GET_MODE_CLASS (MODE) == MODE_INT \
2071 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2072 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2073 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2074 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2075 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2076 #endif
2077 /* The HI and LO registers can only be reloaded via the general
2078 registers. Condition code registers can only be loaded to the
2079 general registers, and from the floating point registers. */
2080
2081 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2082 mips_secondary_reload_class (CLASS, MODE, X, 1)
2083 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2084 mips_secondary_reload_class (CLASS, MODE, X, 0)
2085
2086 /* Return the maximum number of consecutive registers
2087 needed to represent mode MODE in a register of class CLASS. */
2088
2089 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2090
2091 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2092 mips_cannot_change_mode_class (FROM, TO, CLASS)
2093 \f
2094 /* Stack layout; function entry, exit and calling. */
2095
2096 #define STACK_GROWS_DOWNWARD
2097
2098 /* The offset of the first local variable from the beginning of the frame.
2099 See compute_frame_size for details about the frame layout. */
2100 #define STARTING_FRAME_OFFSET \
2101 (current_function_outgoing_args_size \
2102 + (TARGET_ABICALLS && !TARGET_NEWABI \
2103 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2104
2105 #define RETURN_ADDR_RTX mips_return_addr
2106
2107 /* Since the mips16 ISA mode is encoded in the least-significant bit
2108 of the address, mask it off return addresses for purposes of
2109 finding exception handling regions. */
2110
2111 #define MASK_RETURN_ADDR GEN_INT (-2)
2112
2113
2114 /* Similarly, don't use the least-significant bit to tell pointers to
2115 code from vtable index. */
2116
2117 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2118
2119 /* The eliminations to $17 are only used for mips16 code. See the
2120 definition of HARD_FRAME_POINTER_REGNUM. */
2121
2122 #define ELIMINABLE_REGS \
2123 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2124 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2125 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2126 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2127 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2128 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2129
2130 /* We can always eliminate to the hard frame pointer. We can eliminate
2131 to the stack pointer unless a frame pointer is needed.
2132
2133 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2134 reload may be unable to compute the address of a local variable,
2135 since there is no way to add a large constant to the stack pointer
2136 without using a temporary register. */
2137 #define CAN_ELIMINATE(FROM, TO) \
2138 ((TO) == HARD_FRAME_POINTER_REGNUM \
2139 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2140 && (!TARGET_MIPS16 \
2141 || compute_frame_size (get_frame_size ()) < 32768)))
2142
2143 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2144 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2145
2146 /* Allocate stack space for arguments at the beginning of each function. */
2147 #define ACCUMULATE_OUTGOING_ARGS 1
2148
2149 /* The argument pointer always points to the first argument. */
2150 #define FIRST_PARM_OFFSET(FNDECL) 0
2151
2152 /* o32 and o64 reserve stack space for all argument registers. */
2153 #define REG_PARM_STACK_SPACE(FNDECL) \
2154 (TARGET_OLDABI \
2155 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2156 : 0)
2157
2158 /* Define this if it is the responsibility of the caller to
2159 allocate the area reserved for arguments passed in registers.
2160 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2161 of this macro is to determine whether the space is included in
2162 `current_function_outgoing_args_size'. */
2163 #define OUTGOING_REG_PARM_STACK_SPACE
2164
2165 #define STACK_BOUNDARY ((TARGET_OLDABI || mips_abi == ABI_EABI) ? 64 : 128)
2166 \f
2167 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2168
2169 /* Symbolic macros for the registers used to return integer and floating
2170 point values. */
2171
2172 #define GP_RETURN (GP_REG_FIRST + 2)
2173 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2174
2175 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2176
2177 /* Symbolic macros for the first/last argument registers. */
2178
2179 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2180 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2181 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2182 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2183
2184 #define LIBCALL_VALUE(MODE) \
2185 mips_function_value (NULL_TREE, NULL, (MODE))
2186
2187 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2188 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2189
2190 /* 1 if N is a possible register number for a function value.
2191 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2192 Currently, R2 and F0 are only implemented here (C has no complex type) */
2193
2194 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2195 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2196 && (N) == FP_RETURN + 2))
2197
2198 /* 1 if N is a possible register number for function argument passing.
2199 We have no FP argument registers when soft-float. When FP registers
2200 are 32 bits, we can't directly reference the odd numbered ones. */
2201
2202 #define FUNCTION_ARG_REGNO_P(N) \
2203 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2204 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2205 && !fixed_regs[N])
2206 \f
2207 /* This structure has to cope with two different argument allocation
2208 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2209 first N words go in registers and the rest go on the stack. If I < N,
2210 the Ith word might go in Ith integer argument register or the
2211 Ith floating-point one. For these ABIs, we only need to remember
2212 the number of words passed so far.
2213
2214 The EABI instead allocates the integer and floating-point arguments
2215 separately. The first N words of FP arguments go in FP registers,
2216 the rest go on the stack. Likewise, the first N words of the other
2217 arguments go in integer registers, and the rest go on the stack. We
2218 need to maintain three counts: the number of integer registers used,
2219 the number of floating-point registers used, and the number of words
2220 passed on the stack.
2221
2222 We could keep separate information for the two ABIs (a word count for
2223 the standard ABIs, and three separate counts for the EABI). But it
2224 seems simpler to view the standard ABIs as forms of EABI that do not
2225 allocate floating-point registers.
2226
2227 So for the standard ABIs, the first N words are allocated to integer
2228 registers, and function_arg decides on an argument-by-argument basis
2229 whether that argument should really go in an integer register, or in
2230 a floating-point one. */
2231
2232 typedef struct mips_args {
2233 /* Always true for varargs functions. Otherwise true if at least
2234 one argument has been passed in an integer register. */
2235 int gp_reg_found;
2236
2237 /* The number of arguments seen so far. */
2238 unsigned int arg_number;
2239
2240 /* For EABI, the number of integer registers used so far. For other
2241 ABIs, the number of words passed in registers (whether integer
2242 or floating-point). */
2243 unsigned int num_gprs;
2244
2245 /* For EABI, the number of floating-point registers used so far. */
2246 unsigned int num_fprs;
2247
2248 /* The number of words passed on the stack. */
2249 unsigned int stack_words;
2250
2251 /* On the mips16, we need to keep track of which floating point
2252 arguments were passed in general registers, but would have been
2253 passed in the FP regs if this were a 32 bit function, so that we
2254 can move them to the FP regs if we wind up calling a 32 bit
2255 function. We record this information in fp_code, encoded in base
2256 four. A zero digit means no floating point argument, a one digit
2257 means an SFmode argument, and a two digit means a DFmode argument,
2258 and a three digit is not used. The low order digit is the first
2259 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2260 an SFmode argument. ??? A more sophisticated approach will be
2261 needed if MIPS_ABI != ABI_32. */
2262 int fp_code;
2263
2264 /* True if the function has a prototype. */
2265 int prototype;
2266 } CUMULATIVE_ARGS;
2267
2268 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2269 for a call to a function whose data type is FNTYPE.
2270 For a library call, FNTYPE is 0. */
2271
2272 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2273 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2274
2275 /* Update the data in CUM to advance over an argument
2276 of mode MODE and data type TYPE.
2277 (TYPE is null for libcalls where that information may not be available.) */
2278
2279 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2280 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2281
2282 /* Determine where to put an argument to a function.
2283 Value is zero to push the argument on the stack,
2284 or a hard register in which to store the argument.
2285
2286 MODE is the argument's machine mode.
2287 TYPE is the data type of the argument (as a tree).
2288 This is null for libcalls where that information may
2289 not be available.
2290 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2291 the preceding args and about the function being called.
2292 NAMED is nonzero if this argument is a named parameter
2293 (otherwise it is an extra parameter matching an ellipsis). */
2294
2295 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2296 function_arg( &CUM, MODE, TYPE, NAMED)
2297
2298 /* For an arg passed partly in registers and partly in memory,
2299 this is the number of registers used.
2300 For args passed entirely in registers or entirely in memory, zero. */
2301
2302 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2303 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2304
2305 /* If defined, a C expression that gives the alignment boundary, in
2306 bits, of an argument with the specified mode and type. If it is
2307 not defined, `PARM_BOUNDARY' is used for all arguments. */
2308
2309 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2310 (((TYPE) != 0) \
2311 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2312 ? PARM_BOUNDARY \
2313 : TYPE_ALIGN(TYPE)) \
2314 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2315 ? PARM_BOUNDARY \
2316 : GET_MODE_ALIGNMENT(MODE)))
2317
2318 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2319 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2320
2321 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2322 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2323
2324 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2325 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2326
2327 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2328 (mips_abi == ABI_EABI && (NAMED) \
2329 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2330
2331 /* Modified version of the macro in expr.h. Only return true if
2332 the type has a variable size or if the front end requires it
2333 to be passed by reference. */
2334 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2335 ((TYPE) != 0 \
2336 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2337 || TREE_ADDRESSABLE (TYPE)))
2338
2339 /* True if using EABI and varargs can be passed in floating-point
2340 registers. Under these conditions, we need a more complex form
2341 of va_list, which tracks GPR, FPR and stack arguments separately. */
2342 #define EABI_FLOAT_VARARGS_P \
2343 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2344
2345 \f
2346 /* Say that the epilogue uses the return address register. Note that
2347 in the case of sibcalls, the values "used by the epilogue" are
2348 considered live at the start of the called function. */
2349 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2350
2351 /* Treat LOC as a byte offset from the stack pointer and round it up
2352 to the next fully-aligned offset. */
2353 #define MIPS_STACK_ALIGN(LOC) \
2354 ((TARGET_OLDABI || mips_abi == ABI_EABI) \
2355 ? ((LOC) + 7) & ~7 \
2356 : ((LOC) + 15) & ~15)
2357
2358 \f
2359 /* Implement `va_start' for varargs and stdarg. */
2360 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2361 mips_va_start (valist, nextarg)
2362
2363 /* Implement `va_arg'. */
2364 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2365 mips_va_arg (valist, type)
2366 \f
2367 /* Output assembler code to FILE to increment profiler label # LABELNO
2368 for profiling a function entry. */
2369
2370 #define FUNCTION_PROFILER(FILE, LABELNO) \
2371 { \
2372 if (TARGET_MIPS16) \
2373 sorry ("mips16 function profiling"); \
2374 fprintf (FILE, "\t.set\tnoat\n"); \
2375 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2376 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2377 if (!TARGET_NEWABI) \
2378 { \
2379 fprintf (FILE, \
2380 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2381 TARGET_64BIT ? "dsubu" : "subu", \
2382 reg_names[STACK_POINTER_REGNUM], \
2383 reg_names[STACK_POINTER_REGNUM], \
2384 Pmode == DImode ? 16 : 8); \
2385 } \
2386 fprintf (FILE, "\tjal\t_mcount\n"); \
2387 fprintf (FILE, "\t.set\tat\n"); \
2388 }
2389
2390 /* Define this macro if the code for function profiling should come
2391 before the function prologue. Normally, the profiling code comes
2392 after. */
2393
2394 /* #define PROFILE_BEFORE_PROLOGUE */
2395
2396 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2397 the stack pointer does not matter. The value is tested only in
2398 functions that have frame pointers.
2399 No definition is equivalent to always zero. */
2400
2401 #define EXIT_IGNORE_STACK 1
2402
2403 \f
2404 /* A C statement to output, on the stream FILE, assembler code for a
2405 block of data that contains the constant parts of a trampoline.
2406 This code should not include a label--the label is taken care of
2407 automatically. */
2408
2409 #define TRAMPOLINE_TEMPLATE(STREAM) \
2410 { \
2411 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2412 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2413 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2414 if (ptr_mode == DImode) \
2415 { \
2416 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2417 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2418 } \
2419 else \
2420 { \
2421 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2422 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2423 } \
2424 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2425 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2426 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2427 if (ptr_mode == DImode) \
2428 { \
2429 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2430 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2431 } \
2432 else \
2433 { \
2434 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2435 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2436 } \
2437 }
2438
2439 /* A C expression for the size in bytes of the trampoline, as an
2440 integer. */
2441
2442 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2443
2444 /* Alignment required for trampolines, in bits. */
2445
2446 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2447
2448 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2449 program and data caches. */
2450
2451 #ifndef CACHE_FLUSH_FUNC
2452 #define CACHE_FLUSH_FUNC "_flush_cache"
2453 #endif
2454
2455 /* A C statement to initialize the variable parts of a trampoline.
2456 ADDR is an RTX for the address of the trampoline; FNADDR is an
2457 RTX for the address of the nested function; STATIC_CHAIN is an
2458 RTX for the static chain value that should be passed to the
2459 function when it is called. */
2460
2461 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2462 { \
2463 rtx func_addr, chain_addr; \
2464 \
2465 func_addr = plus_constant (ADDR, 32); \
2466 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2467 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2468 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2469 \
2470 /* Flush both caches. We need to flush the data cache in case \
2471 the system has a write-back cache. */ \
2472 /* ??? Should check the return value for errors. */ \
2473 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2474 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2475 0, VOIDmode, 3, ADDR, Pmode, \
2476 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2477 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2478 }
2479 \f
2480 /* Addressing modes, and classification of registers for them. */
2481
2482 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2483 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2484 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2485
2486 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2487 and check its validity for a certain class.
2488 We have two alternate definitions for each of them.
2489 The usual definition accepts all pseudo regs; the other rejects them all.
2490 The symbol REG_OK_STRICT causes the latter definition to be used.
2491
2492 Most source files want to accept pseudo regs in the hope that
2493 they will get allocated to the class that the insn wants them to be in.
2494 Some source files that are used after register allocation
2495 need to be strict. */
2496
2497 #ifndef REG_OK_STRICT
2498 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2499 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2500 #else
2501 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2502 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2503 #endif
2504
2505 #define REG_OK_FOR_INDEX_P(X) 0
2506
2507 \f
2508 /* Maximum number of registers that can appear in a valid memory address. */
2509
2510 #define MAX_REGS_PER_ADDRESS 1
2511
2512 #ifdef REG_OK_STRICT
2513 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2514 { \
2515 if (mips_legitimate_address_p (MODE, X, 1)) \
2516 goto ADDR; \
2517 }
2518 #else
2519 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2520 { \
2521 if (mips_legitimate_address_p (MODE, X, 0)) \
2522 goto ADDR; \
2523 }
2524 #endif
2525
2526 /* Check for constness inline but use mips_legitimate_address_p
2527 to check whether a constant really is an address. */
2528
2529 #define CONSTANT_ADDRESS_P(X) \
2530 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2531
2532 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2533
2534 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2535 do { \
2536 if (mips_legitimize_address (&(X), MODE)) \
2537 goto WIN; \
2538 } while (0)
2539
2540
2541 /* A C statement or compound statement with a conditional `goto
2542 LABEL;' executed if memory address X (an RTX) can have different
2543 meanings depending on the machine mode of the memory reference it
2544 is used for.
2545
2546 Autoincrement and autodecrement addresses typically have
2547 mode-dependent effects because the amount of the increment or
2548 decrement is the size of the operand being addressed. Some
2549 machines have other mode-dependent addresses. Many RISC machines
2550 have no mode-dependent addresses.
2551
2552 You may assume that ADDR is a valid address for the machine. */
2553
2554 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2555
2556 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2557 'the start of the function that this code is output in'. */
2558
2559 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2560 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2561 asm_fprintf ((FILE), "%U%s", \
2562 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2563 else \
2564 asm_fprintf ((FILE), "%U%s", (NAME))
2565
2566 /* The mips16 wants the constant pool to be after the function,
2567 because the PC relative load instructions use unsigned offsets. */
2568
2569 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
2570
2571 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
2572 mips_string_length = 0;
2573 \f
2574 /* Specify the machine mode that this machine uses
2575 for the index in the tablejump instruction.
2576 ??? Using HImode in mips16 mode can cause overflow. */
2577 #define CASE_VECTOR_MODE \
2578 (TARGET_MIPS16 ? HImode : ptr_mode)
2579
2580 /* Define as C expression which evaluates to nonzero if the tablejump
2581 instruction expects the table to contain offsets from the address of the
2582 table.
2583 Do not define this if the table should contain absolute addresses. */
2584 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2585
2586 /* Define this as 1 if `char' should by default be signed; else as 0. */
2587 #ifndef DEFAULT_SIGNED_CHAR
2588 #define DEFAULT_SIGNED_CHAR 1
2589 #endif
2590
2591 /* Max number of bytes we can move from memory to memory
2592 in one reasonably fast instruction. */
2593 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2594 #define MAX_MOVE_MAX 8
2595
2596 /* Define this macro as a C expression which is nonzero if
2597 accessing less than a word of memory (i.e. a `char' or a
2598 `short') is no faster than accessing a word of memory, i.e., if
2599 such access require more than one instruction or if there is no
2600 difference in cost between byte and (aligned) word loads.
2601
2602 On RISC machines, it tends to generate better code to define
2603 this as 1, since it avoids making a QI or HI mode register. */
2604 #define SLOW_BYTE_ACCESS 1
2605
2606 /* Define this to be nonzero if shift instructions ignore all but the low-order
2607 few bits. */
2608 #define SHIFT_COUNT_TRUNCATED 1
2609
2610 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2611 is done just by pretending it is already truncated. */
2612 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2613 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2614
2615
2616 /* Specify the machine mode that pointers have.
2617 After generation of rtl, the compiler makes no further distinction
2618 between pointers and any other objects of this machine mode. */
2619
2620 #ifndef Pmode
2621 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2622 #endif
2623
2624 /* Give call MEMs SImode since it is the "most permissive" mode
2625 for both 32-bit and 64-bit targets. */
2626
2627 #define FUNCTION_MODE SImode
2628
2629 \f
2630 /* The cost of loading values from the constant pool. It should be
2631 larger than the cost of any constant we want to synthesize in-line. */
2632
2633 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2634
2635 /* A C expression for the cost of moving data from a register in
2636 class FROM to one in class TO. The classes are expressed using
2637 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2638 the default; other values are interpreted relative to that.
2639
2640 It is not required that the cost always equal 2 when FROM is the
2641 same as TO; on some machines it is expensive to move between
2642 registers if they are not general registers.
2643
2644 If reload sees an insn consisting of a single `set' between two
2645 hard registers, and if `REGISTER_MOVE_COST' applied to their
2646 classes returns a value of 2, reload does not check to ensure
2647 that the constraints of the insn are met. Setting a cost of
2648 other than 2 will allow reload to verify that the constraints are
2649 met. You should do this if the `movM' pattern's constraints do
2650 not allow such copying. */
2651
2652 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2653 mips_register_move_cost (MODE, FROM, TO)
2654
2655 /* ??? Fix this to be right for the R8000. */
2656 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2657 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2658 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2659
2660 /* Define if copies to/from condition code registers should be avoided.
2661
2662 This is needed for the MIPS because reload_outcc is not complete;
2663 it needs to handle cases where the source is a general or another
2664 condition code register. */
2665 #define AVOID_CCMODE_COPIES
2666
2667 /* A C expression for the cost of a branch instruction. A value of
2668 1 is the default; other values are interpreted relative to that. */
2669
2670 /* ??? Fix this to be right for the R8000. */
2671 #define BRANCH_COST \
2672 ((! TARGET_MIPS16 \
2673 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2674 ? 2 : 1)
2675
2676 /* If defined, modifies the length assigned to instruction INSN as a
2677 function of the context in which it is used. LENGTH is an lvalue
2678 that contains the initially computed length of the insn and should
2679 be updated with the correct length of the insn. */
2680 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2681 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2682
2683 \f
2684 /* Optionally define this if you have added predicates to
2685 `MACHINE.c'. This macro is called within an initializer of an
2686 array of structures. The first field in the structure is the
2687 name of a predicate and the second field is an array of rtl
2688 codes. For each predicate, list all rtl codes that can be in
2689 expressions matched by the predicate. The list should have a
2690 trailing comma. Here is an example of two entries in the list
2691 for a typical RISC machine:
2692
2693 #define PREDICATE_CODES \
2694 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2695 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2696
2697 Defining this macro does not affect the generated code (however,
2698 incorrect definitions that omit an rtl code that may be matched
2699 by the predicate can cause the compiler to malfunction).
2700 Instead, it allows the table built by `genrecog' to be more
2701 compact and efficient, thus speeding up the compiler. The most
2702 important predicates to include in the list specified by this
2703 macro are thoses used in the most insn patterns. */
2704
2705 #define PREDICATE_CODES \
2706 {"uns_arith_operand", { REG, CONST_INT, SUBREG, ADDRESSOF }}, \
2707 {"symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2708 {"general_symbolic_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2709 {"global_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2710 {"local_got_operand", { CONST, SYMBOL_REF, LABEL_REF }}, \
2711 {"const_arith_operand", { CONST_INT }}, \
2712 {"small_data_pattern", { SET, PARALLEL, UNSPEC, \
2713 UNSPEC_VOLATILE }}, \
2714 {"arith_operand", { REG, CONST_INT, CONST, SUBREG, ADDRESSOF }}, \
2715 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, ADDRESSOF }}, \
2716 {"small_int", { CONST_INT }}, \
2717 {"const_float_1_operand", { CONST_DOUBLE }}, \
2718 {"reg_or_const_float_1_operand", { CONST_DOUBLE, REG}}, \
2719 {"equality_op", { EQ, NE }}, \
2720 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2721 LTU, LEU }}, \
2722 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
2723 {"pc_or_label_operand", { PC, LABEL_REF }}, \
2724 {"call_insn_operand", { CONST, SYMBOL_REF, LABEL_REF, REG }}, \
2725 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
2726 SYMBOL_REF, LABEL_REF, SUBREG, \
2727 REG, MEM}}, \
2728 {"stack_operand", { MEM }}, \
2729 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
2730 CONST_DOUBLE, CONST }}, \
2731 {"fcc_register_operand", { REG, SUBREG }}, \
2732 {"hilo_operand", { REG }}, \
2733 {"extend_operator", { ZERO_EXTEND, SIGN_EXTEND }},
2734
2735 /* A list of predicates that do special things with modes, and so
2736 should not elicit warnings for VOIDmode match_operand. */
2737
2738 #define SPECIAL_MODE_PREDICATES \
2739 "pc_or_label_operand",
2740 \f
2741 /* Control the assembler format that we output. */
2742
2743 /* Output to assembler file text saying following lines
2744 may contain character constants, extra white space, comments, etc. */
2745
2746 #ifndef ASM_APP_ON
2747 #define ASM_APP_ON " #APP\n"
2748 #endif
2749
2750 /* Output to assembler file text saying following lines
2751 no longer contain unusual constructs. */
2752
2753 #ifndef ASM_APP_OFF
2754 #define ASM_APP_OFF " #NO_APP\n"
2755 #endif
2756
2757 /* How to refer to registers in assembler output.
2758 This sequence is indexed by compiler's hard-register-number (see above).
2759
2760 In order to support the two different conventions for register names,
2761 we use the name of a table set up in mips.c, which is overwritten
2762 if -mrnames is used. */
2763
2764 #define REGISTER_NAMES \
2765 { \
2766 &mips_reg_names[ 0][0], \
2767 &mips_reg_names[ 1][0], \
2768 &mips_reg_names[ 2][0], \
2769 &mips_reg_names[ 3][0], \
2770 &mips_reg_names[ 4][0], \
2771 &mips_reg_names[ 5][0], \
2772 &mips_reg_names[ 6][0], \
2773 &mips_reg_names[ 7][0], \
2774 &mips_reg_names[ 8][0], \
2775 &mips_reg_names[ 9][0], \
2776 &mips_reg_names[10][0], \
2777 &mips_reg_names[11][0], \
2778 &mips_reg_names[12][0], \
2779 &mips_reg_names[13][0], \
2780 &mips_reg_names[14][0], \
2781 &mips_reg_names[15][0], \
2782 &mips_reg_names[16][0], \
2783 &mips_reg_names[17][0], \
2784 &mips_reg_names[18][0], \
2785 &mips_reg_names[19][0], \
2786 &mips_reg_names[20][0], \
2787 &mips_reg_names[21][0], \
2788 &mips_reg_names[22][0], \
2789 &mips_reg_names[23][0], \
2790 &mips_reg_names[24][0], \
2791 &mips_reg_names[25][0], \
2792 &mips_reg_names[26][0], \
2793 &mips_reg_names[27][0], \
2794 &mips_reg_names[28][0], \
2795 &mips_reg_names[29][0], \
2796 &mips_reg_names[30][0], \
2797 &mips_reg_names[31][0], \
2798 &mips_reg_names[32][0], \
2799 &mips_reg_names[33][0], \
2800 &mips_reg_names[34][0], \
2801 &mips_reg_names[35][0], \
2802 &mips_reg_names[36][0], \
2803 &mips_reg_names[37][0], \
2804 &mips_reg_names[38][0], \
2805 &mips_reg_names[39][0], \
2806 &mips_reg_names[40][0], \
2807 &mips_reg_names[41][0], \
2808 &mips_reg_names[42][0], \
2809 &mips_reg_names[43][0], \
2810 &mips_reg_names[44][0], \
2811 &mips_reg_names[45][0], \
2812 &mips_reg_names[46][0], \
2813 &mips_reg_names[47][0], \
2814 &mips_reg_names[48][0], \
2815 &mips_reg_names[49][0], \
2816 &mips_reg_names[50][0], \
2817 &mips_reg_names[51][0], \
2818 &mips_reg_names[52][0], \
2819 &mips_reg_names[53][0], \
2820 &mips_reg_names[54][0], \
2821 &mips_reg_names[55][0], \
2822 &mips_reg_names[56][0], \
2823 &mips_reg_names[57][0], \
2824 &mips_reg_names[58][0], \
2825 &mips_reg_names[59][0], \
2826 &mips_reg_names[60][0], \
2827 &mips_reg_names[61][0], \
2828 &mips_reg_names[62][0], \
2829 &mips_reg_names[63][0], \
2830 &mips_reg_names[64][0], \
2831 &mips_reg_names[65][0], \
2832 &mips_reg_names[66][0], \
2833 &mips_reg_names[67][0], \
2834 &mips_reg_names[68][0], \
2835 &mips_reg_names[69][0], \
2836 &mips_reg_names[70][0], \
2837 &mips_reg_names[71][0], \
2838 &mips_reg_names[72][0], \
2839 &mips_reg_names[73][0], \
2840 &mips_reg_names[74][0], \
2841 &mips_reg_names[75][0], \
2842 &mips_reg_names[76][0], \
2843 &mips_reg_names[77][0], \
2844 &mips_reg_names[78][0], \
2845 &mips_reg_names[79][0], \
2846 &mips_reg_names[80][0], \
2847 &mips_reg_names[81][0], \
2848 &mips_reg_names[82][0], \
2849 &mips_reg_names[83][0], \
2850 &mips_reg_names[84][0], \
2851 &mips_reg_names[85][0], \
2852 &mips_reg_names[86][0], \
2853 &mips_reg_names[87][0], \
2854 &mips_reg_names[88][0], \
2855 &mips_reg_names[89][0], \
2856 &mips_reg_names[90][0], \
2857 &mips_reg_names[91][0], \
2858 &mips_reg_names[92][0], \
2859 &mips_reg_names[93][0], \
2860 &mips_reg_names[94][0], \
2861 &mips_reg_names[95][0], \
2862 &mips_reg_names[96][0], \
2863 &mips_reg_names[97][0], \
2864 &mips_reg_names[98][0], \
2865 &mips_reg_names[99][0], \
2866 &mips_reg_names[100][0], \
2867 &mips_reg_names[101][0], \
2868 &mips_reg_names[102][0], \
2869 &mips_reg_names[103][0], \
2870 &mips_reg_names[104][0], \
2871 &mips_reg_names[105][0], \
2872 &mips_reg_names[106][0], \
2873 &mips_reg_names[107][0], \
2874 &mips_reg_names[108][0], \
2875 &mips_reg_names[109][0], \
2876 &mips_reg_names[110][0], \
2877 &mips_reg_names[111][0], \
2878 &mips_reg_names[112][0], \
2879 &mips_reg_names[113][0], \
2880 &mips_reg_names[114][0], \
2881 &mips_reg_names[115][0], \
2882 &mips_reg_names[116][0], \
2883 &mips_reg_names[117][0], \
2884 &mips_reg_names[118][0], \
2885 &mips_reg_names[119][0], \
2886 &mips_reg_names[120][0], \
2887 &mips_reg_names[121][0], \
2888 &mips_reg_names[122][0], \
2889 &mips_reg_names[123][0], \
2890 &mips_reg_names[124][0], \
2891 &mips_reg_names[125][0], \
2892 &mips_reg_names[126][0], \
2893 &mips_reg_names[127][0], \
2894 &mips_reg_names[128][0], \
2895 &mips_reg_names[129][0], \
2896 &mips_reg_names[130][0], \
2897 &mips_reg_names[131][0], \
2898 &mips_reg_names[132][0], \
2899 &mips_reg_names[133][0], \
2900 &mips_reg_names[134][0], \
2901 &mips_reg_names[135][0], \
2902 &mips_reg_names[136][0], \
2903 &mips_reg_names[137][0], \
2904 &mips_reg_names[138][0], \
2905 &mips_reg_names[139][0], \
2906 &mips_reg_names[140][0], \
2907 &mips_reg_names[141][0], \
2908 &mips_reg_names[142][0], \
2909 &mips_reg_names[143][0], \
2910 &mips_reg_names[144][0], \
2911 &mips_reg_names[145][0], \
2912 &mips_reg_names[146][0], \
2913 &mips_reg_names[147][0], \
2914 &mips_reg_names[148][0], \
2915 &mips_reg_names[149][0], \
2916 &mips_reg_names[150][0], \
2917 &mips_reg_names[151][0], \
2918 &mips_reg_names[152][0], \
2919 &mips_reg_names[153][0], \
2920 &mips_reg_names[154][0], \
2921 &mips_reg_names[155][0], \
2922 &mips_reg_names[156][0], \
2923 &mips_reg_names[157][0], \
2924 &mips_reg_names[158][0], \
2925 &mips_reg_names[159][0], \
2926 &mips_reg_names[160][0], \
2927 &mips_reg_names[161][0], \
2928 &mips_reg_names[162][0], \
2929 &mips_reg_names[163][0], \
2930 &mips_reg_names[164][0], \
2931 &mips_reg_names[165][0], \
2932 &mips_reg_names[166][0], \
2933 &mips_reg_names[167][0], \
2934 &mips_reg_names[168][0], \
2935 &mips_reg_names[169][0], \
2936 &mips_reg_names[170][0], \
2937 &mips_reg_names[171][0], \
2938 &mips_reg_names[172][0], \
2939 &mips_reg_names[173][0], \
2940 &mips_reg_names[174][0], \
2941 &mips_reg_names[175][0] \
2942 }
2943
2944 /* If defined, a C initializer for an array of structures
2945 containing a name and a register number. This macro defines
2946 additional names for hard registers, thus allowing the `asm'
2947 option in declarations to refer to registers using alternate
2948 names.
2949
2950 We define both names for the integer registers here. */
2951
2952 #define ADDITIONAL_REGISTER_NAMES \
2953 { \
2954 { "$0", 0 + GP_REG_FIRST }, \
2955 { "$1", 1 + GP_REG_FIRST }, \
2956 { "$2", 2 + GP_REG_FIRST }, \
2957 { "$3", 3 + GP_REG_FIRST }, \
2958 { "$4", 4 + GP_REG_FIRST }, \
2959 { "$5", 5 + GP_REG_FIRST }, \
2960 { "$6", 6 + GP_REG_FIRST }, \
2961 { "$7", 7 + GP_REG_FIRST }, \
2962 { "$8", 8 + GP_REG_FIRST }, \
2963 { "$9", 9 + GP_REG_FIRST }, \
2964 { "$10", 10 + GP_REG_FIRST }, \
2965 { "$11", 11 + GP_REG_FIRST }, \
2966 { "$12", 12 + GP_REG_FIRST }, \
2967 { "$13", 13 + GP_REG_FIRST }, \
2968 { "$14", 14 + GP_REG_FIRST }, \
2969 { "$15", 15 + GP_REG_FIRST }, \
2970 { "$16", 16 + GP_REG_FIRST }, \
2971 { "$17", 17 + GP_REG_FIRST }, \
2972 { "$18", 18 + GP_REG_FIRST }, \
2973 { "$19", 19 + GP_REG_FIRST }, \
2974 { "$20", 20 + GP_REG_FIRST }, \
2975 { "$21", 21 + GP_REG_FIRST }, \
2976 { "$22", 22 + GP_REG_FIRST }, \
2977 { "$23", 23 + GP_REG_FIRST }, \
2978 { "$24", 24 + GP_REG_FIRST }, \
2979 { "$25", 25 + GP_REG_FIRST }, \
2980 { "$26", 26 + GP_REG_FIRST }, \
2981 { "$27", 27 + GP_REG_FIRST }, \
2982 { "$28", 28 + GP_REG_FIRST }, \
2983 { "$29", 29 + GP_REG_FIRST }, \
2984 { "$30", 30 + GP_REG_FIRST }, \
2985 { "$31", 31 + GP_REG_FIRST }, \
2986 { "$sp", 29 + GP_REG_FIRST }, \
2987 { "$fp", 30 + GP_REG_FIRST }, \
2988 { "at", 1 + GP_REG_FIRST }, \
2989 { "v0", 2 + GP_REG_FIRST }, \
2990 { "v1", 3 + GP_REG_FIRST }, \
2991 { "a0", 4 + GP_REG_FIRST }, \
2992 { "a1", 5 + GP_REG_FIRST }, \
2993 { "a2", 6 + GP_REG_FIRST }, \
2994 { "a3", 7 + GP_REG_FIRST }, \
2995 { "t0", 8 + GP_REG_FIRST }, \
2996 { "t1", 9 + GP_REG_FIRST }, \
2997 { "t2", 10 + GP_REG_FIRST }, \
2998 { "t3", 11 + GP_REG_FIRST }, \
2999 { "t4", 12 + GP_REG_FIRST }, \
3000 { "t5", 13 + GP_REG_FIRST }, \
3001 { "t6", 14 + GP_REG_FIRST }, \
3002 { "t7", 15 + GP_REG_FIRST }, \
3003 { "s0", 16 + GP_REG_FIRST }, \
3004 { "s1", 17 + GP_REG_FIRST }, \
3005 { "s2", 18 + GP_REG_FIRST }, \
3006 { "s3", 19 + GP_REG_FIRST }, \
3007 { "s4", 20 + GP_REG_FIRST }, \
3008 { "s5", 21 + GP_REG_FIRST }, \
3009 { "s6", 22 + GP_REG_FIRST }, \
3010 { "s7", 23 + GP_REG_FIRST }, \
3011 { "t8", 24 + GP_REG_FIRST }, \
3012 { "t9", 25 + GP_REG_FIRST }, \
3013 { "k0", 26 + GP_REG_FIRST }, \
3014 { "k1", 27 + GP_REG_FIRST }, \
3015 { "gp", 28 + GP_REG_FIRST }, \
3016 { "sp", 29 + GP_REG_FIRST }, \
3017 { "fp", 30 + GP_REG_FIRST }, \
3018 { "ra", 31 + GP_REG_FIRST }, \
3019 { "$sp", 29 + GP_REG_FIRST }, \
3020 { "$fp", 30 + GP_REG_FIRST } \
3021 ALL_COP_ADDITIONAL_REGISTER_NAMES \
3022 }
3023
3024 /* This is meant to be redefined in the host dependent files. It is a
3025 set of alternative names and regnums for mips coprocessors. */
3026
3027 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
3028
3029 /* A C compound statement to output to stdio stream STREAM the
3030 assembler syntax for an instruction operand X. X is an RTL
3031 expression.
3032
3033 CODE is a value that can be used to specify one of several ways
3034 of printing the operand. It is used when identical operands
3035 must be printed differently depending on the context. CODE
3036 comes from the `%' specification that was used to request
3037 printing of the operand. If the specification was just `%DIGIT'
3038 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3039 is the ASCII code for LTR.
3040
3041 If X is a register, this macro should print the register's name.
3042 The names can be found in an array `reg_names' whose type is
3043 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3044
3045 When the machine description has a specification `%PUNCT' (a `%'
3046 followed by a punctuation character), this macro is called with
3047 a null pointer for X and the punctuation character for CODE.
3048
3049 See mips.c for the MIPS specific codes. */
3050
3051 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
3052
3053 /* A C expression which evaluates to true if CODE is a valid
3054 punctuation character for use in the `PRINT_OPERAND' macro. If
3055 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
3056 punctuation characters (except for the standard one, `%') are
3057 used in this way. */
3058
3059 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
3060
3061 /* A C compound statement to output to stdio stream STREAM the
3062 assembler syntax for an instruction operand that is a memory
3063 reference whose address is ADDR. ADDR is an RTL expression. */
3064
3065 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
3066
3067
3068 /* A C statement, to be executed after all slot-filler instructions
3069 have been output. If necessary, call `dbr_sequence_length' to
3070 determine the number of slots filled in a sequence (zero if not
3071 currently outputting a sequence), to decide how many no-ops to
3072 output, or whatever.
3073
3074 Don't define this macro if it has nothing to do, but it is
3075 helpful in reading assembly output if the extent of the delay
3076 sequence is made explicit (e.g. with white space).
3077
3078 Note that output routines for instructions with delay slots must
3079 be prepared to deal with not being output as part of a sequence
3080 (i.e. when the scheduling pass is not run, or when no slot
3081 fillers could be found.) The variable `final_sequence' is null
3082 when not processing a sequence, otherwise it contains the
3083 `sequence' rtx being output. */
3084
3085 #define DBR_OUTPUT_SEQEND(STREAM) \
3086 do \
3087 { \
3088 if (set_nomacro > 0 && --set_nomacro == 0) \
3089 fputs ("\t.set\tmacro\n", STREAM); \
3090 \
3091 if (set_noreorder > 0 && --set_noreorder == 0) \
3092 fputs ("\t.set\treorder\n", STREAM); \
3093 \
3094 fputs ("\n", STREAM); \
3095 } \
3096 while (0)
3097
3098
3099 /* How to tell the debugger about changes of source files. */
3100
3101 #ifndef SET_FILE_NUMBER
3102 #define SET_FILE_NUMBER() ++num_source_filenames
3103 #endif
3104
3105 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
3106 mips_output_filename (STREAM, NAME)
3107
3108 /* This is defined so that it can be overridden in iris6.h. */
3109 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
3110 do \
3111 { \
3112 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
3113 output_quoted_string (STREAM, NAME); \
3114 fputs ("\n", STREAM); \
3115 } \
3116 while (0)
3117
3118 /* This is how to output a note the debugger telling it the line number
3119 to which the following sequence of instructions corresponds.
3120 Silicon graphics puts a label after each .loc. */
3121
3122 #ifndef LABEL_AFTER_LOC
3123 #define LABEL_AFTER_LOC(STREAM)
3124 #endif
3125
3126 #ifndef ASM_OUTPUT_SOURCE_LINE
3127 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) \
3128 mips_output_lineno (STREAM, LINE)
3129 #endif
3130
3131 /* The MIPS implementation uses some labels for its own purpose. The
3132 following lists what labels are created, and are all formed by the
3133 pattern $L[a-z].*. The machine independent portion of GCC creates
3134 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
3135
3136 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
3137 $Lb[0-9]+ Begin blocks for MIPS debug support
3138 $Lc[0-9]+ Label for use in s<xx> operation.
3139 $Le[0-9]+ End blocks for MIPS debug support */
3140
3141 #undef ASM_DECLARE_OBJECT_NAME
3142 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
3143 mips_declare_object (STREAM, NAME, "", ":\n", 0)
3144
3145 /* Globalizing directive for a label. */
3146 #define GLOBAL_ASM_OP "\t.globl\t"
3147
3148 /* This says how to define a global common symbol. */
3149
3150 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
3151
3152 /* This says how to define a local common symbol (ie, not visible to
3153 linker). */
3154
3155 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
3156 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (int)(SIZE))
3157
3158
3159 /* This says how to output an external. It would be possible not to
3160 output anything and let undefined symbol become external. However
3161 the assembler uses length information on externals to allocate in
3162 data/sdata bss/sbss, thereby saving exec time. */
3163
3164 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
3165 mips_output_external(STREAM,DECL,NAME)
3166
3167 /* This is how to declare a function name. The actual work of
3168 emitting the label is moved to function_prologue, so that we can
3169 get the line number correctly emitted before the .ent directive,
3170 and after any .file directives. Define as empty so that the function
3171 is not declared before the .ent directive elsewhere. */
3172
3173 #undef ASM_DECLARE_FUNCTION_NAME
3174 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
3175
3176 #ifndef FUNCTION_NAME_ALREADY_DECLARED
3177 #define FUNCTION_NAME_ALREADY_DECLARED 0
3178 #endif
3179
3180 /* This is how to store into the string LABEL
3181 the symbol_ref name of an internal numbered label where
3182 PREFIX is the class of label and NUM is the number within the class.
3183 This is suitable for output with `assemble_name'. */
3184
3185 #undef ASM_GENERATE_INTERNAL_LABEL
3186 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
3187 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
3188
3189 /* This is how to output an element of a case-vector that is absolute. */
3190
3191 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3192 fprintf (STREAM, "\t%s\t%sL%d\n", \
3193 ptr_mode == DImode ? ".dword" : ".word", \
3194 LOCAL_LABEL_PREFIX, \
3195 VALUE)
3196
3197 /* This is how to output an element of a case-vector that is relative.
3198 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
3199 TARGET_EMBEDDED_PIC). */
3200
3201 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
3202 do { \
3203 if (TARGET_MIPS16) \
3204 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
3205 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3206 else if (TARGET_EMBEDDED_PIC) \
3207 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
3208 ptr_mode == DImode ? ".dword" : ".word", \
3209 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
3210 else if (TARGET_GPWORD) \
3211 fprintf (STREAM, "\t%s\t%sL%d\n", \
3212 ptr_mode == DImode ? ".gpdword" : ".gpword", \
3213 LOCAL_LABEL_PREFIX, VALUE); \
3214 else \
3215 fprintf (STREAM, "\t%s\t%sL%d\n", \
3216 ptr_mode == DImode ? ".dword" : ".word", \
3217 LOCAL_LABEL_PREFIX, VALUE); \
3218 } while (0)
3219
3220 /* When generating embedded PIC or mips16 code we want to put the jump
3221 table in the .text section. In all other cases, we want to put the
3222 jump table in the .rdata section. Unfortunately, we can't use
3223 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
3224 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
3225 section if appropriate. */
3226 #undef ASM_OUTPUT_CASE_LABEL
3227 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
3228 do { \
3229 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
3230 function_section (current_function_decl); \
3231 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
3232 } while (0)
3233
3234 /* This is how to output an assembler line
3235 that says to advance the location counter
3236 to a multiple of 2**LOG bytes. */
3237
3238 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3239 fprintf (STREAM, "\t.align\t%d\n", (LOG))
3240
3241 /* This is how to output an assembler line to advance the location
3242 counter by SIZE bytes. */
3243
3244 #undef ASM_OUTPUT_SKIP
3245 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3246 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
3247
3248 /* This is how to output a string. */
3249 #undef ASM_OUTPUT_ASCII
3250 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3251 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
3252
3253 /* Output #ident as a in the read-only data section. */
3254 #undef ASM_OUTPUT_IDENT
3255 #define ASM_OUTPUT_IDENT(FILE, STRING) \
3256 { \
3257 const char *p = STRING; \
3258 int size = strlen (p) + 1; \
3259 readonly_data_section (); \
3260 assemble_string (p, size); \
3261 }
3262 \f
3263 /* Default to -G 8 */
3264 #ifndef MIPS_DEFAULT_GVALUE
3265 #define MIPS_DEFAULT_GVALUE 8
3266 #endif
3267
3268 /* Define the strings to put out for each section in the object file. */
3269 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3270 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3271 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
3272
3273 #undef READONLY_DATA_SECTION_ASM_OP
3274 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3275
3276 /* Given a decl node or constant node, choose the section to output it in
3277 and select that section. */
3278
3279 #undef TARGET_ASM_SELECT_SECTION
3280 #define TARGET_ASM_SELECT_SECTION mips_select_section
3281 \f
3282 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3283 do \
3284 { \
3285 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
3286 TARGET_64BIT ? "dsubu" : "subu", \
3287 reg_names[STACK_POINTER_REGNUM], \
3288 reg_names[STACK_POINTER_REGNUM], \
3289 TARGET_64BIT ? "sd" : "sw", \
3290 reg_names[REGNO], \
3291 reg_names[STACK_POINTER_REGNUM]); \
3292 } \
3293 while (0)
3294
3295 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3296 do \
3297 { \
3298 if (! set_noreorder) \
3299 fprintf (STREAM, "\t.set\tnoreorder\n"); \
3300 \
3301 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3302 TARGET_64BIT ? "ld" : "lw", \
3303 reg_names[REGNO], \
3304 reg_names[STACK_POINTER_REGNUM], \
3305 TARGET_64BIT ? "daddu" : "addu", \
3306 reg_names[STACK_POINTER_REGNUM], \
3307 reg_names[STACK_POINTER_REGNUM]); \
3308 \
3309 if (! set_noreorder) \
3310 fprintf (STREAM, "\t.set\treorder\n"); \
3311 } \
3312 while (0)
3313
3314 /* How to start an assembler comment.
3315 The leading space is important (the mips native assembler requires it). */
3316 #ifndef ASM_COMMENT_START
3317 #define ASM_COMMENT_START " #"
3318 #endif
3319 \f
3320 /* Default definitions for size_t and ptrdiff_t. We must override the
3321 definitions from ../svr4.h on mips-*-linux-gnu. */
3322
3323 #undef SIZE_TYPE
3324 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3325
3326 #undef PTRDIFF_TYPE
3327 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3328
3329 /* See mips_expand_prologue's use of loadgp for when this should be
3330 true. */
3331
3332 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
3333 \f
3334 /* Generate calls to memcpy, etc., not bcopy, etc. */
3335 #define TARGET_MEM_FUNCTIONS
3336
3337 #ifndef __mips16
3338 /* Since the bits of the _init and _fini function is spread across
3339 many object files, each potentially with its own GP, we must assume
3340 we need to load our GP. We don't preserve $gp or $ra, since each
3341 init/fini chunk is supposed to initialize $gp, and crti/crtn
3342 already take care of preserving $ra and, when appropriate, $gp. */
3343 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3344 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3345 asm (SECTION_OP "\n\
3346 .set noreorder\n\
3347 bal 1f\n\
3348 nop\n\
3349 1: .cpload $31\n\
3350 .set reorder\n\
3351 jal " USER_LABEL_PREFIX #FUNC "\n\
3352 " TEXT_SECTION_ASM_OP);
3353 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3354 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3355 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3356 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3357 asm (SECTION_OP "\n\
3358 .set noreorder\n\
3359 bal 1f\n\
3360 nop\n\
3361 1: .set reorder\n\
3362 .cpsetup $31, $2, 1b\n\
3363 jal " USER_LABEL_PREFIX #FUNC "\n\
3364 " TEXT_SECTION_ASM_OP);
3365 #endif
3366 #endif
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