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* doc/invoke.texi: Document new MIPS -msym32 and -mno-sym32 options.
[official-gcc.git] / gcc / config / mips / mips.h
blob41328a34d65ae400ba7679a71d430b436d506e73
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* Which processor to schedule for. Since there is no difference between
34 a R2000 and R3000 in terms of the scheduler, we collapse them into
35 just an R3000. The elements of the enumeration must match exactly
36 the cpu attribute in the mips.md machine description. */
37
38 enum processor_type {
39 PROCESSOR_DEFAULT,
40 PROCESSOR_4KC,
41 PROCESSOR_5KC,
42 PROCESSOR_20KC,
43 PROCESSOR_M4K,
44 PROCESSOR_R3000,
45 PROCESSOR_R3900,
46 PROCESSOR_R6000,
47 PROCESSOR_R4000,
48 PROCESSOR_R4100,
49 PROCESSOR_R4111,
50 PROCESSOR_R4120,
51 PROCESSOR_R4130,
52 PROCESSOR_R4300,
53 PROCESSOR_R4600,
54 PROCESSOR_R4650,
55 PROCESSOR_R5000,
56 PROCESSOR_R5400,
57 PROCESSOR_R5500,
58 PROCESSOR_R7000,
59 PROCESSOR_R8000,
60 PROCESSOR_R9000,
61 PROCESSOR_SB1,
62 PROCESSOR_SR71000
63 };
64
65 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
66 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
67 to work on a 64 bit machine. */
68
69 #define ABI_32 0
70 #define ABI_N32 1
71 #define ABI_64 2
72 #define ABI_EABI 3
73 #define ABI_O64 4
74
75 /* Information about one recognized processor. Defined here for the
76 benefit of TARGET_CPU_CPP_BUILTINS. */
77 struct mips_cpu_info {
78 /* The 'canonical' name of the processor as far as GCC is concerned.
79 It's typically a manufacturer's prefix followed by a numerical
80 designation. It should be lower case. */
81 const char *name;
82
83 /* The internal processor number that most closely matches this
84 entry. Several processors can have the same value, if there's no
85 difference between them from GCC's point of view. */
86 enum processor_type cpu;
87
88 /* The ISA level that the processor implements. */
89 int isa;
90 };
91
92 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
93 extern const char *current_function_file; /* filename current function is in */
94 extern int num_source_filenames; /* current .file # */
95 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
96 extern int sym_lineno; /* sgi next label # for each stmt */
97 extern int set_noreorder; /* # of nested .set noreorder's */
98 extern int set_nomacro; /* # of nested .set nomacro's */
99 extern int set_noat; /* # of nested .set noat's */
100 extern int set_volatile; /* # of nested .set volatile's */
101 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
102 extern int mips_dbx_regno[]; /* Map register # to debug register # */
103 extern GTY(()) rtx cmp_operands[2];
104 extern enum processor_type mips_arch; /* which cpu to codegen for */
105 extern enum processor_type mips_tune; /* which cpu to schedule for */
106 extern int mips_isa; /* architectural level */
107 extern int mips_abi; /* which ABI to use */
108 extern int mips16_hard_float; /* mips16 without -msoft-float */
109 extern const char *mips_arch_string; /* for -march=<xxx> */
110 extern const char *mips_tune_string; /* for -mtune=<xxx> */
111 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
112 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
113 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
114 extern const struct mips_cpu_info mips_cpu_info_table[];
115 extern const struct mips_cpu_info *mips_arch_info;
116 extern const struct mips_cpu_info *mips_tune_info;
117
118 /* Macros to silence warnings about numbers being signed in traditional
119 C and unsigned in ISO C when compiled on 32-bit hosts. */
120
121 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
122 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
123 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
124
125 \f
126 /* Run-time compilation parameters selecting different hardware subsets. */
127
128 /* Macros used in the machine description to test the flags. */
129
130 /* Bits for real switches */
131 #define MASK_INT64 0x00000001 /* ints are 64 bits */
132 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
133 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
134 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
135 multiply-add operations. */
136 #define MASK_EXPLICIT_RELOCS 0x00000010 /* Use relocation operators. */
137 #define MASK_MEMCPY 0x00000020 /* call memcpy instead of inline code*/
138 #define MASK_SOFT_FLOAT 0x00000040 /* software floating point */
139 #define MASK_FLOAT64 0x00000080 /* fp registers are 64 bits */
140 #define MASK_ABICALLS 0x00000100 /* emit .abicalls/.cprestore/.cpload */
141 #define MASK_XGOT 0x00000200 /* emit big-got PIC */
142 #define MASK_LONG_CALLS 0x00000400 /* Always call through a register */
143 #define MASK_64BIT 0x00000800 /* Use 64 bit GP registers and insns */
144 #define MASK_EMBEDDED_DATA 0x00001000 /* Reduce RAM usage, not fast code */
145 #define MASK_BIG_ENDIAN 0x00002000 /* Generate big endian code */
146 #define MASK_SINGLE_FLOAT 0x00004000 /* Only single precision FPU. */
147 #define MASK_MAD 0x00008000 /* Generate mad/madu as on 4650. */
148 #define MASK_4300_MUL_FIX 0x00010000 /* Work-around early Vr4300 CPU bug */
149 #define MASK_MIPS16 0x00020000 /* Generate mips16 code */
150 #define MASK_NO_CHECK_ZERO_DIV \
151 0x00040000 /* divide by zero checking */
152 #define MASK_BRANCHLIKELY 0x00080000 /* Generate Branch Likely
153 instructions. */
154 #define MASK_UNINIT_CONST_IN_RODATA \
155 0x00100000 /* Store uninitialized
156 consts in rodata */
157 #define MASK_FIX_R4000 0x00200000 /* Work around R4000 errata. */
158 #define MASK_FIX_R4400 0x00400000 /* Work around R4400 errata. */
159 #define MASK_FIX_SB1 0x00800000 /* Work around SB-1 errata. */
160 #define MASK_FIX_VR4120 0x01000000 /* Work around VR4120 errata. */
161 #define MASK_VR4130_ALIGN 0x02000000 /* Perform VR4130 alignment opts. */
162 #define MASK_FP_EXCEPTIONS 0x04000000 /* FP exceptions are enabled. */
163 #define MASK_DIVIDE_BREAKS 0x08000000 /* Divide by zero check uses
164 break instead of trap. */
165 #define MASK_PAIRED_SINGLE 0x10000000 /* Support paired-single FPU. */
166 #define MASK_MIPS3D 0x20000000 /* Support MIPS-3D instructions. */
167 #define MASK_SYM32 0x40000000 /* Assume 32-bit symbol values. */
168
169 /* Debug switches, not documented */
170 #define MASK_DEBUG 0 /* unused */
171 #define MASK_DEBUG_D 0 /* don't do define_split's */
172
173 /* Dummy switches used only in specs */
174 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
175
176 /* r4000 64 bit sizes */
177 #define TARGET_INT64 ((target_flags & MASK_INT64) != 0)
178 #define TARGET_LONG64 ((target_flags & MASK_LONG64) != 0)
179 #define TARGET_FLOAT64 ((target_flags & MASK_FLOAT64) != 0)
180 #define TARGET_64BIT ((target_flags & MASK_64BIT) != 0)
181
182 /* Mips vs. GNU linker */
183 #define TARGET_SPLIT_ADDRESSES ((target_flags & MASK_SPLIT_ADDR) != 0)
184
185 /* Debug Modes */
186 #define TARGET_DEBUG_MODE ((target_flags & MASK_DEBUG) != 0)
187 #define TARGET_DEBUG_D_MODE ((target_flags & MASK_DEBUG_D) != 0)
188
189 /* call memcpy instead of inline code */
190 #define TARGET_MEMCPY ((target_flags & MASK_MEMCPY) != 0)
191
192 /* .abicalls, etc from Pyramid V.4 */
193 #define TARGET_ABICALLS ((target_flags & MASK_ABICALLS) != 0)
194 #define TARGET_XGOT ((target_flags & MASK_XGOT) != 0)
195
196 /* software floating point */
197 #define TARGET_SOFT_FLOAT ((target_flags & MASK_SOFT_FLOAT) != 0)
198 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
199
200 /* always call through a register */
201 #define TARGET_LONG_CALLS ((target_flags & MASK_LONG_CALLS) != 0)
202
203 /* for embedded systems, optimize for
204 reduced RAM space instead of for
205 fastest code. */
206 #define TARGET_EMBEDDED_DATA ((target_flags & MASK_EMBEDDED_DATA) != 0)
207
208 /* always store uninitialized const
209 variables in rodata, requires
210 TARGET_EMBEDDED_DATA. */
211 #define TARGET_UNINIT_CONST_IN_RODATA \
212 ((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)
213
214 /* generate big endian code. */
215 #define TARGET_BIG_ENDIAN ((target_flags & MASK_BIG_ENDIAN) != 0)
216
217 #define TARGET_SINGLE_FLOAT ((target_flags & MASK_SINGLE_FLOAT) != 0)
218 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
219
220 #define TARGET_MAD ((target_flags & MASK_MAD) != 0)
221
222 #define TARGET_FUSED_MADD ((target_flags & MASK_NO_FUSED_MADD) == 0)
223
224 #define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
225
226 #define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
227 #define TARGET_DIVIDE_TRAPS ((target_flags & MASK_DIVIDE_BREAKS) == 0)
228
229 #define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
230
231 #define TARGET_FIX_SB1 ((target_flags & MASK_FIX_SB1) != 0)
232
233 /* Work around R4000 errata. */
234 #define TARGET_FIX_R4000 ((target_flags & MASK_FIX_R4000) != 0)
235
236 /* Work around R4400 errata. */
237 #define TARGET_FIX_R4400 ((target_flags & MASK_FIX_R4400) != 0)
238 #define TARGET_FIX_VR4120 ((target_flags & MASK_FIX_VR4120) != 0)
239 #define TARGET_VR4130_ALIGN ((target_flags & MASK_VR4130_ALIGN) != 0)
240
241 #define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
242
243 #define TARGET_PAIRED_SINGLE_FLOAT \
244 ((target_flags & MASK_PAIRED_SINGLE) != 0)
245 #define TARGET_MIPS3D ((target_flags & MASK_MIPS3D) != 0)
246 #define TARGET_SYM32 ((target_flags & MASK_SYM32) != 0)
247
248 /* True if we should use NewABI-style relocation operators for
249 symbolic addresses. This is never true for mips16 code,
250 which has its own conventions. */
251
252 #define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
253
254
255 /* True if the call patterns should be split into a jalr followed by
256 an instruction to restore $gp. This is only ever true for SVR4 PIC,
257 in which $gp is call-clobbered. It is only safe to split the load
258 from the call when every use of $gp is explicit. */
259
260 #define TARGET_SPLIT_CALLS \
261 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
262
263 /* True if we can optimize sibling calls. For simplicity, we only
264 handle cases in which call_insn_operand will reject invalid
265 sibcall addresses. There are two cases in which this isn't true:
266
267 - TARGET_MIPS16. call_insn_operand accepts constant addresses
268 but there is no direct jump instruction. It isn't worth
269 using sibling calls in this case anyway; they would usually
270 be longer than normal calls.
271
272 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
273 accepts global constants, but "jr $25" is the only allowed
274 sibcall. */
275
276 #define TARGET_SIBCALLS \
277 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
278
279 /* True if .gpword or .gpdword should be used for switch tables.
280
281 Although GAS does understand .gpdword, the SGI linker mishandles
282 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
283 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
284 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
285
286 /* Generate mips16 code */
287 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
288
289 /* Generic ISA defines. */
290 #define ISA_MIPS1 (mips_isa == 1)
291 #define ISA_MIPS2 (mips_isa == 2)
292 #define ISA_MIPS3 (mips_isa == 3)
293 #define ISA_MIPS4 (mips_isa == 4)
294 #define ISA_MIPS32 (mips_isa == 32)
295 #define ISA_MIPS32R2 (mips_isa == 33)
296 #define ISA_MIPS64 (mips_isa == 64)
297
298 /* Architecture target defines. */
299 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
300 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
301 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
302 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
303 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
304 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
305 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
306 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
307 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
308 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
309
310 /* Scheduling target defines. */
311 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
312 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
313 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
314 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
315 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
316 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
317 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
318 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
319 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
320 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
321 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
322 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
323
324 /* True if the pre-reload scheduler should try to create chains of
325 multiply-add or multiply-subtract instructions. For example,
326 suppose we have:
327
328 t1 = a * b
329 t2 = t1 + c * d
330 t3 = e * f
331 t4 = t3 - g * h
332
333 t1 will have a higher priority than t2 and t3 will have a higher
334 priority than t4. However, before reload, there is no dependence
335 between t1 and t3, and they can often have similar priorities.
336 The scheduler will then tend to prefer:
337
338 t1 = a * b
339 t3 = e * f
340 t2 = t1 + c * d
341 t4 = t3 - g * h
342
343 which stops us from making full use of macc/madd-style instructions.
344 This sort of situation occurs frequently in Fourier transforms and
345 in unrolled loops.
346
347 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
348 queue so that chained multiply-add and multiply-subtract instructions
349 appear ahead of any other instruction that is likely to clobber lo.
350 In the example above, if t2 and t3 become ready at the same time,
351 the code ensures that t2 is scheduled first.
352
353 Multiply-accumulate instructions are a bigger win for some targets
354 than others, so this macro is defined on an opt-in basis. */
355 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
356 || TUNE_MIPS4120 \
357 || TUNE_MIPS4130)
358
359 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
360 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
361
362 /* IRIX specific stuff. */
363 #define TARGET_IRIX 0
364 #define TARGET_IRIX6 0
365
366 /* Define preprocessor macros for the -march and -mtune options.
367 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
368 processor. If INFO's canonical name is "foo", define PREFIX to
369 be "foo", and define an additional macro PREFIX_FOO. */
370 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
371 do \
372 { \
373 char *macro, *p; \
374 \
375 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
376 for (p = macro; *p != 0; p++) \
377 *p = TOUPPER (*p); \
378 \
379 builtin_define (macro); \
380 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
381 free (macro); \
382 } \
383 while (0)
384
385 /* Target CPU builtins. */
386 #define TARGET_CPU_CPP_BUILTINS() \
387 do \
388 { \
389 /* Everyone but IRIX defines this to mips. */ \
390 if (!TARGET_IRIX) \
391 builtin_assert ("machine=mips"); \
392 \
393 builtin_assert ("cpu=mips"); \
394 builtin_define ("__mips__"); \
395 builtin_define ("_mips"); \
396 \
397 /* We do this here because __mips is defined below \
398 and so we can't use builtin_define_std. */ \
399 if (!flag_iso) \
400 builtin_define ("mips"); \
401 \
402 if (TARGET_64BIT) \
403 builtin_define ("__mips64"); \
404 \
405 if (!TARGET_IRIX) \
406 { \
407 /* Treat _R3000 and _R4000 like register-size \
408 defines, which is how they've historically \
409 been used. */ \
410 if (TARGET_64BIT) \
411 { \
412 builtin_define_std ("R4000"); \
413 builtin_define ("_R4000"); \
414 } \
415 else \
416 { \
417 builtin_define_std ("R3000"); \
418 builtin_define ("_R3000"); \
419 } \
420 } \
421 if (TARGET_FLOAT64) \
422 builtin_define ("__mips_fpr=64"); \
423 else \
424 builtin_define ("__mips_fpr=32"); \
425 \
426 if (TARGET_MIPS16) \
427 builtin_define ("__mips16"); \
428 \
429 if (TARGET_MIPS3D) \
430 builtin_define ("__mips3d"); \
431 \
432 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
433 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
434 \
435 if (ISA_MIPS1) \
436 { \
437 builtin_define ("__mips=1"); \
438 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
439 } \
440 else if (ISA_MIPS2) \
441 { \
442 builtin_define ("__mips=2"); \
443 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
444 } \
445 else if (ISA_MIPS3) \
446 { \
447 builtin_define ("__mips=3"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
449 } \
450 else if (ISA_MIPS4) \
451 { \
452 builtin_define ("__mips=4"); \
453 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
454 } \
455 else if (ISA_MIPS32) \
456 { \
457 builtin_define ("__mips=32"); \
458 builtin_define ("__mips_isa_rev=1"); \
459 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
460 } \
461 else if (ISA_MIPS32R2) \
462 { \
463 builtin_define ("__mips=32"); \
464 builtin_define ("__mips_isa_rev=2"); \
465 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
466 } \
467 else if (ISA_MIPS64) \
468 { \
469 builtin_define ("__mips=64"); \
470 builtin_define ("__mips_isa_rev=1"); \
471 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
472 } \
473 \
474 if (TARGET_HARD_FLOAT) \
475 builtin_define ("__mips_hard_float"); \
476 else if (TARGET_SOFT_FLOAT) \
477 builtin_define ("__mips_soft_float"); \
478 \
479 if (TARGET_SINGLE_FLOAT) \
480 builtin_define ("__mips_single_float"); \
481 \
482 if (TARGET_PAIRED_SINGLE_FLOAT) \
483 builtin_define ("__mips_paired_single_float"); \
484 \
485 if (TARGET_BIG_ENDIAN) \
486 { \
487 builtin_define_std ("MIPSEB"); \
488 builtin_define ("_MIPSEB"); \
489 } \
490 else \
491 { \
492 builtin_define_std ("MIPSEL"); \
493 builtin_define ("_MIPSEL"); \
494 } \
495 \
496 /* Macros dependent on the C dialect. */ \
497 if (preprocessing_asm_p ()) \
498 { \
499 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
500 builtin_define ("_LANGUAGE_ASSEMBLY"); \
501 } \
502 else if (c_dialect_cxx ()) \
503 { \
504 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
505 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
506 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
507 } \
508 else \
509 { \
510 builtin_define_std ("LANGUAGE_C"); \
511 builtin_define ("_LANGUAGE_C"); \
512 } \
513 if (c_dialect_objc ()) \
514 { \
515 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
516 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
517 /* Bizarre, but needed at least for Irix. */ \
518 builtin_define_std ("LANGUAGE_C"); \
519 builtin_define ("_LANGUAGE_C"); \
520 } \
521 \
522 if (mips_abi == ABI_EABI) \
523 builtin_define ("__mips_eabi"); \
524 \
525 } while (0)
526
527
528
529 /* Macro to define tables used to set the flags.
530 This is a list in braces of pairs in braces,
531 each pair being { "NAME", VALUE }
532 where VALUE is the bits to set or minus the bits to clear.
533 An empty string NAME is used to identify the default VALUE. */
534
535 #define TARGET_SWITCHES \
536 { \
537 SUBTARGET_TARGET_SWITCHES \
538 {"int64", MASK_INT64 | MASK_LONG64, \
539 N_("Use 64-bit int type")}, \
540 {"long64", MASK_LONG64, \
541 N_("Use 64-bit long type")}, \
542 {"long32", -(MASK_LONG64 | MASK_INT64), \
543 N_("Use 32-bit long type")}, \
544 {"split-addresses", MASK_SPLIT_ADDR, \
545 N_("Optimize lui/addiu address loads")}, \
546 {"no-split-addresses", -MASK_SPLIT_ADDR, \
547 N_("Don't optimize lui/addiu address loads")}, \
548 {"gas", 0, \
549 N_("Use GNU as (now ignored)")}, \
550 {"gpOPT", 0, \
551 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
552 {"gpopt", 0, \
553 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
554 {"no-gpOPT", 0, \
555 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
556 {"no-gpopt", 0, \
557 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
558 {"stats", 0, \
559 N_("Output compiler statistics (now ignored)")}, \
560 {"no-stats", 0, \
561 N_("Don't output compiler statistics")}, \
562 {"memcpy", MASK_MEMCPY, \
563 N_("Don't optimize block moves")}, \
564 {"no-memcpy", -MASK_MEMCPY, \
565 N_("Optimize block moves")}, \
566 {"mips-tfile", MASK_MIPS_TFILE, \
567 N_("Use mips-tfile asm postpass")}, \
568 {"no-mips-tfile", -MASK_MIPS_TFILE, \
569 N_("Don't use mips-tfile asm postpass")}, \
570 {"soft-float", MASK_SOFT_FLOAT, \
571 N_("Use software floating point")}, \
572 {"hard-float", -MASK_SOFT_FLOAT, \
573 N_("Use hardware floating point")}, \
574 {"fp64", MASK_FLOAT64, \
575 N_("Use 64-bit FP registers")}, \
576 {"fp32", -MASK_FLOAT64, \
577 N_("Use 32-bit FP registers")}, \
578 {"gp64", MASK_64BIT, \
579 N_("Use 64-bit general registers")}, \
580 {"gp32", -MASK_64BIT, \
581 N_("Use 32-bit general registers")}, \
582 {"abicalls", MASK_ABICALLS, \
583 N_("Use Irix PIC")}, \
584 {"no-abicalls", -MASK_ABICALLS, \
585 N_("Don't use Irix PIC")}, \
586 {"long-calls", MASK_LONG_CALLS, \
587 N_("Use indirect calls")}, \
588 {"no-long-calls", -MASK_LONG_CALLS, \
589 N_("Don't use indirect calls")}, \
590 {"embedded-data", MASK_EMBEDDED_DATA, \
591 N_("Use ROM instead of RAM")}, \
592 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
593 N_("Don't use ROM instead of RAM")}, \
594 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
595 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
596 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
597 N_("Don't put uninitialized constants in ROM")}, \
598 {"eb", MASK_BIG_ENDIAN, \
599 N_("Use big-endian byte order")}, \
600 {"el", -MASK_BIG_ENDIAN, \
601 N_("Use little-endian byte order")}, \
602 {"single-float", MASK_SINGLE_FLOAT, \
603 N_("Use single (32-bit) FP only")}, \
604 {"double-float", -MASK_SINGLE_FLOAT, \
605 N_("Don't use single (32-bit) FP only")}, \
606 {"paired-single", MASK_PAIRED_SINGLE, \
607 N_("Use paired-single floating point instructions")}, \
608 {"no-paired-single", -MASK_PAIRED_SINGLE, \
609 N_("Use paired-single floating point instructions")}, \
610 {"ips3d", MASK_MIPS3D, \
611 N_("Use MIPS-3D instructions")}, \
612 {"no-mips3d", -MASK_MIPS3D, \
613 N_("Use MIPS-3D instructions")}, \
614 {"mad", MASK_MAD, \
615 N_("Use multiply accumulate")}, \
616 {"no-mad", -MASK_MAD, \
617 N_("Don't use multiply accumulate")}, \
618 {"no-fused-madd", MASK_NO_FUSED_MADD, \
619 N_("Don't generate fused multiply/add instructions")}, \
620 {"fused-madd", -MASK_NO_FUSED_MADD, \
621 N_("Generate fused multiply/add instructions")}, \
622 {"vr4130-align", MASK_VR4130_ALIGN, \
623 N_("Perform VR4130-specific alignment optimizations")}, \
624 {"no-vr4130-align", -MASK_VR4130_ALIGN, \
625 N_("Don't perform VR4130-specific alignment optimizations")}, \
626 {"fix4300", MASK_4300_MUL_FIX, \
627 N_("Work around early 4300 hardware bug")}, \
628 {"no-fix4300", -MASK_4300_MUL_FIX, \
629 N_("Don't work around early 4300 hardware bug")}, \
630 {"fix-sb1", MASK_FIX_SB1, \
631 N_("Work around errata for early SB-1 revision 2 cores")}, \
632 {"no-fix-sb1", -MASK_FIX_SB1, \
633 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
634 {"fix-r4000", MASK_FIX_R4000, \
635 N_("Work around R4000 errata")}, \
636 {"no-fix-r4000", -MASK_FIX_R4000, \
637 N_("Don't work around R4000 errata")}, \
638 {"fix-r4400", MASK_FIX_R4400, \
639 N_("Work around R4400 errata")}, \
640 {"no-fix-r4400", -MASK_FIX_R4400, \
641 N_("Don't work around R4400 errata")}, \
642 {"fix-vr4120", MASK_FIX_VR4120, \
643 N_("Work around certain VR4120 errata")}, \
644 {"no-fix-vr4120", -MASK_FIX_VR4120, \
645 N_("Don't work around certain VR4120 errata")}, \
646 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
647 N_("Trap on integer divide by zero")}, \
648 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
649 N_("Don't trap on integer divide by zero")}, \
650 {"divide-traps", -MASK_DIVIDE_BREAKS, \
651 N_("Use trap to check for integer divide by zero")}, \
652 {"divide-breaks", MASK_DIVIDE_BREAKS, \
653 N_("Use break to check for integer divide by zero")}, \
654 { "branch-likely", MASK_BRANCHLIKELY, \
655 N_("Use Branch Likely instructions, overriding default for arch")}, \
656 { "no-branch-likely", -MASK_BRANCHLIKELY, \
657 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
658 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
659 N_("Use NewABI-style %reloc() assembly operators")}, \
660 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
661 N_("Use assembler macros instead of relocation operators")}, \
662 {"ips16", MASK_MIPS16, \
663 N_("Generate mips16 code") }, \
664 {"no-mips16", -MASK_MIPS16, \
665 N_("Generate normal-mode code") }, \
666 {"xgot", MASK_XGOT, \
667 N_("Lift restrictions on GOT size") }, \
668 {"no-xgot", -MASK_XGOT, \
669 N_("Do not lift restrictions on GOT size") }, \
670 {"fp-exceptions", MASK_FP_EXCEPTIONS, \
671 N_("FP exceptions are enabled") }, \
672 {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
673 N_("FP exceptions are not enabled") }, \
674 {"sym32", MASK_SYM32, \
675 N_("Assume all symbols have 32-bit values") }, \
676 {"no-sym32", -MASK_SYM32, \
677 N_("Don't assume all symbols have 32-bit values") }, \
678 {"debug", MASK_DEBUG, \
679 NULL}, \
680 {"debugd", MASK_DEBUG_D, \
681 NULL}, \
682 {"", (TARGET_DEFAULT \
683 | TARGET_CPU_DEFAULT \
684 | TARGET_ENDIAN_DEFAULT \
685 | TARGET_FP_EXCEPTIONS_DEFAULT), \
686 NULL}, \
687 }
688
689 /* Default target_flags if no switches are specified */
690
691 #ifndef TARGET_DEFAULT
692 #define TARGET_DEFAULT 0
693 #endif
694
695 #ifndef TARGET_CPU_DEFAULT
696 #define TARGET_CPU_DEFAULT 0
697 #endif
698
699 #ifndef TARGET_ENDIAN_DEFAULT
700 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
701 #endif
702
703 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
704 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
705 #endif
706
707 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
708 #ifndef MIPS_ISA_DEFAULT
709 #ifndef MIPS_CPU_STRING_DEFAULT
710 #define MIPS_CPU_STRING_DEFAULT "from-abi"
711 #endif
712 #endif
713
714 #ifdef IN_LIBGCC2
715 #undef TARGET_64BIT
716 /* Make this compile time constant for libgcc2 */
717 #ifdef __mips64
718 #define TARGET_64BIT 1
719 #else
720 #define TARGET_64BIT 0
721 #endif
722 #endif /* IN_LIBGCC2 */
723
724 #ifndef MULTILIB_ENDIAN_DEFAULT
725 #if TARGET_ENDIAN_DEFAULT == 0
726 #define MULTILIB_ENDIAN_DEFAULT "EL"
727 #else
728 #define MULTILIB_ENDIAN_DEFAULT "EB"
729 #endif
730 #endif
731
732 #ifndef MULTILIB_ISA_DEFAULT
733 # if MIPS_ISA_DEFAULT == 1
734 # define MULTILIB_ISA_DEFAULT "mips1"
735 # else
736 # if MIPS_ISA_DEFAULT == 2
737 # define MULTILIB_ISA_DEFAULT "mips2"
738 # else
739 # if MIPS_ISA_DEFAULT == 3
740 # define MULTILIB_ISA_DEFAULT "mips3"
741 # else
742 # if MIPS_ISA_DEFAULT == 4
743 # define MULTILIB_ISA_DEFAULT "mips4"
744 # else
745 # if MIPS_ISA_DEFAULT == 32
746 # define MULTILIB_ISA_DEFAULT "mips32"
747 # else
748 # if MIPS_ISA_DEFAULT == 33
749 # define MULTILIB_ISA_DEFAULT "mips32r2"
750 # else
751 # if MIPS_ISA_DEFAULT == 64
752 # define MULTILIB_ISA_DEFAULT "mips64"
753 # else
754 # define MULTILIB_ISA_DEFAULT "mips1"
755 # endif
756 # endif
757 # endif
758 # endif
759 # endif
760 # endif
761 # endif
762 #endif
763
764 #ifndef MULTILIB_DEFAULTS
765 #define MULTILIB_DEFAULTS \
766 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
767 #endif
768
769 /* We must pass -EL to the linker by default for little endian embedded
770 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
771 linker will default to using big-endian output files. The OUTPUT_FORMAT
772 line must be in the linker script, otherwise -EB/-EL will not work. */
773
774 #ifndef ENDIAN_SPEC
775 #if TARGET_ENDIAN_DEFAULT == 0
776 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
777 #else
778 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
779 #endif
780 #endif
781
782 #define TARGET_OPTIONS \
783 { \
784 SUBTARGET_TARGET_OPTIONS \
785 { "tune=", &mips_tune_string, \
786 N_("Specify CPU for scheduling purposes"), 0}, \
787 { "arch=", &mips_arch_string, \
788 N_("Specify CPU for code generation purposes"), 0}, \
789 { "abi=", &mips_abi_string, \
790 N_("Specify an ABI"), 0}, \
791 { "ips", &mips_isa_string, \
792 N_("Specify a Standard MIPS ISA"), 0}, \
793 { "no-flush-func", &mips_cache_flush_func, \
794 N_("Don't call any cache flush functions"), 0}, \
795 { "flush-func=", &mips_cache_flush_func, \
796 N_("Specify cache flush function"), 0}, \
797 }
798
799 /* This is meant to be redefined in the host dependent files. */
800 #define SUBTARGET_TARGET_OPTIONS
801
802 /* Support for a compile-time default CPU, et cetera. The rules are:
803 --with-arch is ignored if -march is specified or a -mips is specified
804 (other than -mips16).
805 --with-tune is ignored if -mtune is specified.
806 --with-abi is ignored if -mabi is specified.
807 --with-float is ignored if -mhard-float or -msoft-float are
808 specified.
809 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
810 specified. */
811 #define OPTION_DEFAULT_SPECS \
812 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
813 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
814 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
815 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
816 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
817
818
819 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
820 && ISA_HAS_COND_TRAP)
821
822 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
823 && !TARGET_SR71K \
824 && !TARGET_MIPS16)
825
826 /* Generate three-operand multiply instructions for SImode. */
827 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
828 || TARGET_MIPS5400 \
829 || TARGET_MIPS5500 \
830 || TARGET_MIPS7000 \
831 || TARGET_MIPS9000 \
832 || TARGET_MAD \
833 || ISA_MIPS32 \
834 || ISA_MIPS32R2 \
835 || ISA_MIPS64) \
836 && !TARGET_MIPS16)
837
838 /* Generate three-operand multiply instructions for DImode. */
839 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
840 && !TARGET_MIPS16)
841
842 /* True if the ABI can only work with 64-bit integer registers. We
843 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
844 otherwise floating-point registers must also be 64-bit. */
845 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
846
847 /* Likewise for 32-bit regs. */
848 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
849
850 /* True if symbols are 64 bits wide. At present, n64 is the only
851 ABI for which this is true. */
852 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
853
854 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
855 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
856 || ISA_MIPS4 \
857 || ISA_MIPS64)
858
859 /* ISA has branch likely instructions (e.g. mips2). */
860 /* Disable branchlikely for tx39 until compare rewrite. They haven't
861 been generated up to this point. */
862 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
863
864 /* ISA has the conditional move instructions introduced in mips4. */
865 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
866 || ISA_MIPS32 \
867 || ISA_MIPS32R2 \
868 || ISA_MIPS64) \
869 && !TARGET_MIPS5500 \
870 && !TARGET_MIPS16)
871
872 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
873 branch on CC, and move (both FP and non-FP) on CC. */
874 #define ISA_HAS_8CC (ISA_MIPS4 \
875 || ISA_MIPS32 \
876 || ISA_MIPS32R2 \
877 || ISA_MIPS64)
878
879 /* This is a catch all for other mips4 instructions: indexed load, the
880 FP madd and msub instructions, and the FP recip and recip sqrt
881 instructions. */
882 #define ISA_HAS_FP4 ((ISA_MIPS4 \
883 || ISA_MIPS64) \
884 && !TARGET_MIPS16)
885
886 /* ISA has conditional trap instructions. */
887 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
888 && !TARGET_MIPS16)
889
890 /* ISA has integer multiply-accumulate instructions, madd and msub. */
891 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
892 || ISA_MIPS32R2 \
893 || ISA_MIPS64 \
894 ) && !TARGET_MIPS16)
895
896 /* ISA has floating-point nmadd and nmsub instructions. */
897 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
898 || ISA_MIPS64) \
899 && (!TARGET_MIPS5400 || TARGET_MAD) \
900 && ! TARGET_MIPS16)
901
902 /* ISA has count leading zeroes/ones instruction (not implemented). */
903 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
904 || ISA_MIPS32R2 \
905 || ISA_MIPS64 \
906 ) && !TARGET_MIPS16)
907
908 /* ISA has double-word count leading zeroes/ones instruction (not
909 implemented). */
910 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
911 && !TARGET_MIPS16)
912
913 /* ISA has three operand multiply instructions that put
914 the high part in an accumulator: mulhi or mulhiu. */
915 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
916 || TARGET_MIPS5500 \
917 || TARGET_SR71K \
918 )
919
920 /* ISA has three operand multiply instructions that
921 negates the result and puts the result in an accumulator. */
922 #define ISA_HAS_MULS (TARGET_MIPS5400 \
923 || TARGET_MIPS5500 \
924 || TARGET_SR71K \
925 )
926
927 /* ISA has three operand multiply instructions that subtracts the
928 result from a 4th operand and puts the result in an accumulator. */
929 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
930 || TARGET_MIPS5500 \
931 || TARGET_SR71K \
932 )
933 /* ISA has three operand multiply instructions that the result
934 from a 4th operand and puts the result in an accumulator. */
935 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
936 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
937 || TARGET_MIPS5400 \
938 || TARGET_MIPS5500 \
939 || TARGET_SR71K \
940 )
941
942 /* ISA has 32-bit rotate right instruction. */
943 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
944 && (ISA_MIPS32R2 \
945 || TARGET_MIPS5400 \
946 || TARGET_MIPS5500 \
947 || TARGET_SR71K \
948 ))
949
950 /* ISA has 64-bit rotate right instruction. */
951 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
952 && !TARGET_MIPS16 \
953 && (TARGET_MIPS5400 \
954 || TARGET_MIPS5500 \
955 || TARGET_SR71K \
956 ))
957
958 /* ISA has data prefetch instructions. This controls use of 'pref'. */
959 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
960 || ISA_MIPS32 \
961 || ISA_MIPS32R2 \
962 || ISA_MIPS64) \
963 && !TARGET_MIPS16)
964
965 /* ISA has data indexed prefetch instructions. This controls use of
966 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
967 (prefx is a cop1x instruction, so can only be used if FP is
968 enabled.) */
969 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
970 || ISA_MIPS64) \
971 && !TARGET_MIPS16)
972
973 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
974 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
975 also requires TARGET_DOUBLE_FLOAT. */
976 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
977
978 /* ISA includes the MIPS32r2 seb and seh instructions. */
979 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
980 && (ISA_MIPS32R2 \
981 ))
982
983 /* True if the result of a load is not available to the next instruction.
984 A nop will then be needed between instructions like "lw $4,..."
985 and "addiu $4,$4,1". */
986 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
987 && !TARGET_MIPS3900 \
988 && !TARGET_MIPS16)
989
990 /* Likewise mtc1 and mfc1. */
991 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
992
993 /* Likewise floating-point comparisons. */
994 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
995
996 /* True if mflo and mfhi can be immediately followed by instructions
997 which write to the HI and LO registers.
998
999 According to MIPS specifications, MIPS ISAs I, II, and III need
1000 (at least) two instructions between the reads of HI/LO and
1001 instructions which write them, and later ISAs do not. Contradicting
1002 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1003 the UM for the NEC Vr5000) document needing the instructions between
1004 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1005 MIPS64 and later ISAs to have the interlocks, plus any specific
1006 earlier-ISA CPUs for which CPU documentation declares that the
1007 instructions are really interlocked. */
1008 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1009 || ISA_MIPS32R2 \
1010 || ISA_MIPS64 \
1011 || TARGET_MIPS5500)
1012 \f
1013 /* Add -G xx support. */
1014
1015 #undef SWITCH_TAKES_ARG
1016 #define SWITCH_TAKES_ARG(CHAR) \
1017 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1018
1019 #define OVERRIDE_OPTIONS override_options ()
1020
1021 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1022
1023 /* Show we can debug even without a frame pointer. */
1024 #define CAN_DEBUG_WITHOUT_FP
1025 \f
1026 /* Tell collect what flags to pass to nm. */
1027 #ifndef NM_FLAGS
1028 #define NM_FLAGS "-Bn"
1029 #endif
1030
1031 \f
1032 #define SUBTARGET_TARGET_SWITCHES
1033
1034 #ifndef MIPS_ABI_DEFAULT
1035 #define MIPS_ABI_DEFAULT ABI_32
1036 #endif
1037
1038 /* Use the most portable ABI flag for the ASM specs. */
1039
1040 #if MIPS_ABI_DEFAULT == ABI_32
1041 #define MULTILIB_ABI_DEFAULT "mabi=32"
1042 #endif
1043
1044 #if MIPS_ABI_DEFAULT == ABI_O64
1045 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1046 #endif
1047
1048 #if MIPS_ABI_DEFAULT == ABI_N32
1049 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1050 #endif
1051
1052 #if MIPS_ABI_DEFAULT == ABI_64
1053 #define MULTILIB_ABI_DEFAULT "mabi=64"
1054 #endif
1055
1056 #if MIPS_ABI_DEFAULT == ABI_EABI
1057 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1058 #endif
1059
1060 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1061 to the assembler. It may be overridden by subtargets. */
1062 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1063 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1064 %{noasmopt:-O0} \
1065 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1066 #endif
1067
1068 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1069 the assembler. It may be overridden by subtargets.
1070
1071 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1072 COFF debugging info. */
1073
1074 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1075 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1076 %{g} %{g0} %{g1} %{g2} %{g3} \
1077 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1078 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1079 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1080 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1081 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1082 #endif
1083
1084 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1085 overridden by subtargets. */
1086
1087 #ifndef SUBTARGET_ASM_SPEC
1088 #define SUBTARGET_ASM_SPEC ""
1089 #endif
1090
1091 #undef ASM_SPEC
1092 #define ASM_SPEC "\
1093 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1094 %{mips32} %{mips32r2} %{mips64} \
1095 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1096 %{mips3d:-mips3d} \
1097 %{mfix-vr4120} \
1098 %(subtarget_asm_optimizing_spec) \
1099 %(subtarget_asm_debugging_spec) \
1100 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1101 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1102 %{msym32} %{mno-sym32} \
1103 %{mtune=*} %{v} \
1104 %(subtarget_asm_spec)"
1105
1106 /* Extra switches sometimes passed to the linker. */
1107 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1108 will interpret it as a -b option. */
1109
1110 #ifndef LINK_SPEC
1111 #define LINK_SPEC "\
1112 %(endian_spec) \
1113 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1114 %{bestGnum} %{shared} %{non_shared}"
1115 #endif /* LINK_SPEC defined */
1116
1117
1118 /* Specs for the compiler proper */
1119
1120 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1121 overridden by subtargets. */
1122 #ifndef SUBTARGET_CC1_SPEC
1123 #define SUBTARGET_CC1_SPEC ""
1124 #endif
1125
1126 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1127
1128 #ifndef CC1_SPEC
1129 #define CC1_SPEC "\
1130 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1131 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1132 %{save-temps: } \
1133 %(subtarget_cc1_spec)"
1134 #endif
1135
1136 /* Preprocessor specs. */
1137
1138 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1139 overridden by subtargets. */
1140 #ifndef SUBTARGET_CPP_SPEC
1141 #define SUBTARGET_CPP_SPEC ""
1142 #endif
1143
1144 #define CPP_SPEC "%(subtarget_cpp_spec)"
1145
1146 /* This macro defines names of additional specifications to put in the specs
1147 that can be used in various specifications like CC1_SPEC. Its definition
1148 is an initializer with a subgrouping for each command option.
1149
1150 Each subgrouping contains a string constant, that defines the
1151 specification name, and a string constant that used by the GCC driver
1152 program.
1153
1154 Do not define this macro if it does not need to do anything. */
1155
1156 #define EXTRA_SPECS \
1157 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1158 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1159 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1160 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1161 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1162 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1163 { "endian_spec", ENDIAN_SPEC }, \
1164 SUBTARGET_EXTRA_SPECS
1165
1166 #ifndef SUBTARGET_EXTRA_SPECS
1167 #define SUBTARGET_EXTRA_SPECS
1168 #endif
1169 \f
1170 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1171 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1172 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1173
1174 #ifndef PREFERRED_DEBUGGING_TYPE
1175 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1176 #endif
1177
1178 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1179
1180 /* By default, turn on GDB extensions. */
1181 #define DEFAULT_GDB_EXTENSIONS 1
1182
1183 /* Local compiler-generated symbols must have a prefix that the assembler
1184 understands. By default, this is $, although some targets (e.g.,
1185 NetBSD-ELF) need to override this. */
1186
1187 #ifndef LOCAL_LABEL_PREFIX
1188 #define LOCAL_LABEL_PREFIX "$"
1189 #endif
1190
1191 /* By default on the mips, external symbols do not have an underscore
1192 prepended, but some targets (e.g., NetBSD) require this. */
1193
1194 #ifndef USER_LABEL_PREFIX
1195 #define USER_LABEL_PREFIX ""
1196 #endif
1197
1198 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1199 since the length can run past this up to a continuation point. */
1200 #undef DBX_CONTIN_LENGTH
1201 #define DBX_CONTIN_LENGTH 1500
1202
1203 /* How to renumber registers for dbx and gdb. */
1204 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1205
1206 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1207 #define DWARF_FRAME_REGNUM(REG) (REG)
1208
1209 /* The DWARF 2 CFA column which tracks the return address. */
1210 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1211
1212 /* The DWARF 2 CFA column which tracks the return address from a
1213 signal handler context. */
1214 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1215
1216 /* Before the prologue, RA lives in r31. */
1217 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1218
1219 /* Describe how we implement __builtin_eh_return. */
1220 #define EH_RETURN_DATA_REGNO(N) \
1221 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1222
1223 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1224
1225 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1226 The default for this in 64-bit mode is 8, which causes problems with
1227 SFmode register saves. */
1228 #define DWARF_CIE_DATA_ALIGNMENT 4
1229
1230 /* Correct the offset of automatic variables and arguments. Note that
1231 the MIPS debug format wants all automatic variables and arguments
1232 to be in terms of the virtual frame pointer (stack pointer before
1233 any adjustment in the function), while the MIPS 3.0 linker wants
1234 the frame pointer to be the stack pointer after the initial
1235 adjustment. */
1236
1237 #define DEBUGGER_AUTO_OFFSET(X) \
1238 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1239 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1240 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1241 \f
1242 /* Target machine storage layout */
1243
1244 #define BITS_BIG_ENDIAN 0
1245 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1246 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1247
1248 /* Define this to set the endianness to use in libgcc2.c, which can
1249 not depend on target_flags. */
1250 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1251 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1252 #else
1253 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1254 #endif
1255
1256 #define MAX_BITS_PER_WORD 64
1257
1258 /* Width of a word, in units (bytes). */
1259 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1260 #define MIN_UNITS_PER_WORD 4
1261
1262 /* For MIPS, width of a floating point register. */
1263 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1264
1265 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1266 the next available register. */
1267 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1268
1269 /* The largest size of value that can be held in floating-point
1270 registers and moved with a single instruction. */
1271 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1272
1273 /* The largest size of value that can be held in floating-point
1274 registers. */
1275 #define UNITS_PER_FPVALUE \
1276 (TARGET_SOFT_FLOAT ? 0 \
1277 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1278 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1279
1280 /* The number of bytes in a double. */
1281 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1282
1283 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : 0)
1284
1285 /* Set the sizes of the core types. */
1286 #define SHORT_TYPE_SIZE 16
1287 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1288 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1289 #define LONG_LONG_TYPE_SIZE 64
1290
1291 #define FLOAT_TYPE_SIZE 32
1292 #define DOUBLE_TYPE_SIZE 64
1293 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1294
1295 /* long double is not a fixed mode, but the idea is that, if we
1296 support long double, we also want a 128-bit integer type. */
1297 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1298
1299 #ifdef IN_LIBGCC2
1300 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1301 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1302 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1303 # else
1304 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1305 # endif
1306 #endif
1307
1308 /* Width in bits of a pointer. */
1309 #ifndef POINTER_SIZE
1310 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1311 #endif
1312
1313 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1314 #define PARM_BOUNDARY BITS_PER_WORD
1315
1316 /* Allocation boundary (in *bits*) for the code of a function. */
1317 #define FUNCTION_BOUNDARY 32
1318
1319 /* Alignment of field after `int : 0' in a structure. */
1320 #define EMPTY_FIELD_BOUNDARY 32
1321
1322 /* Every structure's size must be a multiple of this. */
1323 /* 8 is observed right on a DECstation and on riscos 4.02. */
1324 #define STRUCTURE_SIZE_BOUNDARY 8
1325
1326 /* There is no point aligning anything to a rounder boundary than this. */
1327 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1328
1329 /* All accesses must be aligned. */
1330 #define STRICT_ALIGNMENT 1
1331
1332 /* Define this if you wish to imitate the way many other C compilers
1333 handle alignment of bitfields and the structures that contain
1334 them.
1335
1336 The behavior is that the type written for a bit-field (`int',
1337 `short', or other integer type) imposes an alignment for the
1338 entire structure, as if the structure really did contain an
1339 ordinary field of that type. In addition, the bit-field is placed
1340 within the structure so that it would fit within such a field,
1341 not crossing a boundary for it.
1342
1343 Thus, on most machines, a bit-field whose type is written as `int'
1344 would not cross a four-byte boundary, and would force four-byte
1345 alignment for the whole structure. (The alignment used may not
1346 be four bytes; it is controlled by the other alignment
1347 parameters.)
1348
1349 If the macro is defined, its definition should be a C expression;
1350 a nonzero value for the expression enables this behavior. */
1351
1352 #define PCC_BITFIELD_TYPE_MATTERS 1
1353
1354 /* If defined, a C expression to compute the alignment given to a
1355 constant that is being placed in memory. CONSTANT is the constant
1356 and ALIGN is the alignment that the object would ordinarily have.
1357 The value of this macro is used instead of that alignment to align
1358 the object.
1359
1360 If this macro is not defined, then ALIGN is used.
1361
1362 The typical use of this macro is to increase alignment for string
1363 constants to be word aligned so that `strcpy' calls that copy
1364 constants can be done inline. */
1365
1366 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1367 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1368 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1369
1370 /* If defined, a C expression to compute the alignment for a static
1371 variable. TYPE is the data type, and ALIGN is the alignment that
1372 the object would ordinarily have. The value of this macro is used
1373 instead of that alignment to align the object.
1374
1375 If this macro is not defined, then ALIGN is used.
1376
1377 One use of this macro is to increase alignment of medium-size
1378 data to make it all fit in fewer cache lines. Another is to
1379 cause character arrays to be word-aligned so that `strcpy' calls
1380 that copy constants to character arrays can be done inline. */
1381
1382 #undef DATA_ALIGNMENT
1383 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1384 ((((ALIGN) < BITS_PER_WORD) \
1385 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1386 || TREE_CODE (TYPE) == UNION_TYPE \
1387 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1388
1389
1390 #define PAD_VARARGS_DOWN \
1391 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1392
1393 /* Define if operations between registers always perform the operation
1394 on the full register even if a narrower mode is specified. */
1395 #define WORD_REGISTER_OPERATIONS
1396
1397 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1398 moves. All other references are zero extended. */
1399 #define LOAD_EXTEND_OP(MODE) \
1400 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1401 ? SIGN_EXTEND : ZERO_EXTEND)
1402
1403 /* Define this macro if it is advisable to hold scalars in registers
1404 in a wider mode than that declared by the program. In such cases,
1405 the value is constrained to be within the bounds of the declared
1406 type, but kept valid in the wider mode. The signedness of the
1407 extension may differ from that of the type. */
1408
1409 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1410 if (GET_MODE_CLASS (MODE) == MODE_INT \
1411 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1412 { \
1413 if ((MODE) == SImode) \
1414 (UNSIGNEDP) = 0; \
1415 (MODE) = Pmode; \
1416 }
1417
1418 /* Define if loading short immediate values into registers sign extends. */
1419 #define SHORT_IMMEDIATES_SIGN_EXTEND
1420 \f
1421 /* Standard register usage. */
1422
1423 /* Number of hardware registers. We have:
1424
1425 - 32 integer registers
1426 - 32 floating point registers
1427 - 8 condition code registers
1428 - 2 accumulator registers (hi and lo)
1429 - 32 registers each for coprocessors 0, 2 and 3
1430 - 3 fake registers:
1431 - ARG_POINTER_REGNUM
1432 - FRAME_POINTER_REGNUM
1433 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1434 - 3 dummy entries that were used at various times in the past. */
1435
1436 #define FIRST_PSEUDO_REGISTER 176
1437
1438 /* By default, fix the kernel registers ($26 and $27), the global
1439 pointer ($28) and the stack pointer ($29). This can change
1440 depending on the command-line options.
1441
1442 Regarding coprocessor registers: without evidence to the contrary,
1443 it's best to assume that each coprocessor register has a unique
1444 use. This can be overridden, in, e.g., override_options() or
1445 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1446 for a particular target. */
1447
1448 #define FIXED_REGISTERS \
1449 { \
1450 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1451 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1452 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1453 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1454 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1455 /* COP0 registers */ \
1456 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1457 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1458 /* COP2 registers */ \
1459 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1460 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1461 /* COP3 registers */ \
1462 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1463 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1464 }
1465
1466
1467 /* Set up this array for o32 by default.
1468
1469 Note that we don't mark $31 as a call-clobbered register. The idea is
1470 that it's really the call instructions themselves which clobber $31.
1471 We don't care what the called function does with it afterwards.
1472
1473 This approach makes it easier to implement sibcalls. Unlike normal
1474 calls, sibcalls don't clobber $31, so the register reaches the
1475 called function in tact. EPILOGUE_USES says that $31 is useful
1476 to the called function. */
1477
1478 #define CALL_USED_REGISTERS \
1479 { \
1480 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1481 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1482 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1483 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1484 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1485 /* COP0 registers */ \
1486 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1487 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1488 /* COP2 registers */ \
1489 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1490 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1491 /* COP3 registers */ \
1492 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1493 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1494 }
1495
1496
1497 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1498
1499 #define CALL_REALLY_USED_REGISTERS \
1500 { /* General registers. */ \
1501 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1502 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1503 /* Floating-point registers. */ \
1504 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1505 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1506 /* Others. */ \
1507 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1508 /* COP0 registers */ \
1509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1510 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1511 /* COP2 registers */ \
1512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1514 /* COP3 registers */ \
1515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1517 }
1518
1519 /* Internal macros to classify a register number as to whether it's a
1520 general purpose register, a floating point register, a
1521 multiply/divide register, or a status register. */
1522
1523 #define GP_REG_FIRST 0
1524 #define GP_REG_LAST 31
1525 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1526 #define GP_DBX_FIRST 0
1527
1528 #define FP_REG_FIRST 32
1529 #define FP_REG_LAST 63
1530 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1531 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1532
1533 #define MD_REG_FIRST 64
1534 #define MD_REG_LAST 65
1535 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1536 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1537
1538 #define ST_REG_FIRST 67
1539 #define ST_REG_LAST 74
1540 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1541
1542
1543 /* FIXME: renumber. */
1544 #define COP0_REG_FIRST 80
1545 #define COP0_REG_LAST 111
1546 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1547
1548 #define COP2_REG_FIRST 112
1549 #define COP2_REG_LAST 143
1550 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1551
1552 #define COP3_REG_FIRST 144
1553 #define COP3_REG_LAST 175
1554 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1555 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1556 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1557
1558 #define AT_REGNUM (GP_REG_FIRST + 1)
1559 #define HI_REGNUM (MD_REG_FIRST + 0)
1560 #define LO_REGNUM (MD_REG_FIRST + 1)
1561
1562 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1563 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1564 should be used instead. */
1565 #define FPSW_REGNUM ST_REG_FIRST
1566
1567 #define GP_REG_P(REGNO) \
1568 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1569 #define M16_REG_P(REGNO) \
1570 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1571 #define FP_REG_P(REGNO) \
1572 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1573 #define MD_REG_P(REGNO) \
1574 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1575 #define ST_REG_P(REGNO) \
1576 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1577 #define COP0_REG_P(REGNO) \
1578 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1579 #define COP2_REG_P(REGNO) \
1580 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1581 #define COP3_REG_P(REGNO) \
1582 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1583 #define ALL_COP_REG_P(REGNO) \
1584 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1585
1586 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1587
1588 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1589 to initialize the mips16 gp pseudo register. */
1590 #define CONST_GP_P(X) \
1591 (GET_CODE (X) == CONST \
1592 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1593 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1594
1595 /* Return coprocessor number from register number. */
1596
1597 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1598 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1599 : COP3_REG_P (REGNO) ? '3' : '?')
1600
1601
1602 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1603
1604 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1605 array built in override_options. Because machmodes.h is not yet
1606 included before this file is processed, the MODE bound can't be
1607 expressed here. */
1608
1609 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1610
1611 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1612 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1613
1614 /* Value is 1 if it is a good idea to tie two pseudo registers
1615 when one has mode MODE1 and one has mode MODE2.
1616 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1617 for any hard reg, then this must be 0 for correct output. */
1618 #define MODES_TIEABLE_P(MODE1, MODE2) \
1619 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1620 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1621 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1622 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1623
1624 /* Register to use for pushing function arguments. */
1625 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1626
1627 /* These two registers don't really exist: they get eliminated to either
1628 the stack or hard frame pointer. */
1629 #define ARG_POINTER_REGNUM 77
1630 #define FRAME_POINTER_REGNUM 78
1631
1632 /* $30 is not available on the mips16, so we use $17 as the frame
1633 pointer. */
1634 #define HARD_FRAME_POINTER_REGNUM \
1635 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1636
1637 /* Value should be nonzero if functions must have frame pointers.
1638 Zero means the frame pointer need not be set up (and parms
1639 may be accessed via the stack pointer) in functions that seem suitable.
1640 This is computed in `reload', in reload1.c. */
1641 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1642
1643 /* Register in which static-chain is passed to a function. */
1644 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1645
1646 /* Registers used as temporaries in prologue/epilogue code. If we're
1647 generating mips16 code, these registers must come from the core set
1648 of 8. The prologue register mustn't conflict with any incoming
1649 arguments, the static chain pointer, or the frame pointer. The
1650 epilogue temporary mustn't conflict with the return registers, the
1651 frame pointer, the EH stack adjustment, or the EH data registers. */
1652
1653 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1654 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1655
1656 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1657 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1658
1659 /* Define this macro if it is as good or better to call a constant
1660 function address than to call an address kept in a register. */
1661 #define NO_FUNCTION_CSE 1
1662
1663 /* The ABI-defined global pointer. Sometimes we use a different
1664 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1665 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1666
1667 /* We normally use $28 as the global pointer. However, when generating
1668 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1669 register instead. They can then avoid saving and restoring $28
1670 and perhaps avoid using a frame at all.
1671
1672 When a leaf function uses something other than $28, mips_expand_prologue
1673 will modify pic_offset_table_rtx in place. Take the register number
1674 from there after reload. */
1675 #define PIC_OFFSET_TABLE_REGNUM \
1676 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1677
1678 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1679 \f
1680 /* Define the classes of registers for register constraints in the
1681 machine description. Also define ranges of constants.
1682
1683 One of the classes must always be named ALL_REGS and include all hard regs.
1684 If there is more than one class, another class must be named NO_REGS
1685 and contain no registers.
1686
1687 The name GENERAL_REGS must be the name of a class (or an alias for
1688 another name such as ALL_REGS). This is the class of registers
1689 that is allowed by "g" or "r" in a register constraint.
1690 Also, registers outside this class are allocated only when
1691 instructions express preferences for them.
1692
1693 The classes must be numbered in nondecreasing order; that is,
1694 a larger-numbered class must never be contained completely
1695 in a smaller-numbered class.
1696
1697 For any two classes, it is very desirable that there be another
1698 class that represents their union. */
1699
1700 enum reg_class
1701 {
1702 NO_REGS, /* no registers in set */
1703 M16_NA_REGS, /* mips16 regs not used to pass args */
1704 M16_REGS, /* mips16 directly accessible registers */
1705 T_REG, /* mips16 T register ($24) */
1706 M16_T_REGS, /* mips16 registers plus T register */
1707 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1708 LEA_REGS, /* Every GPR except $25 */
1709 GR_REGS, /* integer registers */
1710 FP_REGS, /* floating point registers */
1711 HI_REG, /* hi register */
1712 LO_REG, /* lo register */
1713 MD_REGS, /* multiply/divide registers (hi/lo) */
1714 COP0_REGS, /* generic coprocessor classes */
1715 COP2_REGS,
1716 COP3_REGS,
1717 HI_AND_GR_REGS, /* union classes */
1718 LO_AND_GR_REGS,
1719 HI_AND_FP_REGS,
1720 COP0_AND_GR_REGS,
1721 COP2_AND_GR_REGS,
1722 COP3_AND_GR_REGS,
1723 ALL_COP_REGS,
1724 ALL_COP_AND_GR_REGS,
1725 ST_REGS, /* status registers (fp status) */
1726 ALL_REGS, /* all registers */
1727 LIM_REG_CLASSES /* max value + 1 */
1728 };
1729
1730 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1731
1732 #define GENERAL_REGS GR_REGS
1733
1734 /* An initializer containing the names of the register classes as C
1735 string constants. These names are used in writing some of the
1736 debugging dumps. */
1737
1738 #define REG_CLASS_NAMES \
1739 { \
1740 "NO_REGS", \
1741 "M16_NA_REGS", \
1742 "M16_REGS", \
1743 "T_REG", \
1744 "M16_T_REGS", \
1745 "PIC_FN_ADDR_REG", \
1746 "LEA_REGS", \
1747 "GR_REGS", \
1748 "FP_REGS", \
1749 "HI_REG", \
1750 "LO_REG", \
1751 "MD_REGS", \
1752 /* coprocessor registers */ \
1753 "COP0_REGS", \
1754 "COP2_REGS", \
1755 "COP3_REGS", \
1756 "HI_AND_GR_REGS", \
1757 "LO_AND_GR_REGS", \
1758 "HI_AND_FP_REGS", \
1759 "COP0_AND_GR_REGS", \
1760 "COP2_AND_GR_REGS", \
1761 "COP3_AND_GR_REGS", \
1762 "ALL_COP_REGS", \
1763 "ALL_COP_AND_GR_REGS", \
1764 "ST_REGS", \
1765 "ALL_REGS" \
1766 }
1767
1768 /* An initializer containing the contents of the register classes,
1769 as integers which are bit masks. The Nth integer specifies the
1770 contents of class N. The way the integer MASK is interpreted is
1771 that register R is in the class if `MASK & (1 << R)' is 1.
1772
1773 When the machine has more than 32 registers, an integer does not
1774 suffice. Then the integers are replaced by sub-initializers,
1775 braced groupings containing several integers. Each
1776 sub-initializer must be suitable as an initializer for the type
1777 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1778
1779 #define REG_CLASS_CONTENTS \
1780 { \
1781 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1782 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1783 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1784 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1785 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1786 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1787 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1788 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1789 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1790 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1791 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1792 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1793 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1794 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1795 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1796 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1797 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1798 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1799 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1800 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1801 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1802 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1803 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1804 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1805 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1806 }
1807
1808
1809 /* A C expression whose value is a register class containing hard
1810 register REGNO. In general there is more that one such class;
1811 choose a class which is "minimal", meaning that no smaller class
1812 also contains the register. */
1813
1814 extern const enum reg_class mips_regno_to_class[];
1815
1816 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1817
1818 /* A macro whose definition is the name of the class to which a
1819 valid base register must belong. A base register is one used in
1820 an address which is the register value plus a displacement. */
1821
1822 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1823
1824 /* A macro whose definition is the name of the class to which a
1825 valid index register must belong. An index register is one used
1826 in an address where its value is either multiplied by a scale
1827 factor or added to another register (as well as added to a
1828 displacement). */
1829
1830 #define INDEX_REG_CLASS NO_REGS
1831
1832 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1833 registers explicitly used in the rtl to be used as spill registers
1834 but prevents the compiler from extending the lifetime of these
1835 registers. */
1836
1837 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1838
1839 /* This macro is used later on in the file. */
1840 #define GR_REG_CLASS_P(CLASS) \
1841 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1842 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1843 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1844
1845 /* This macro is also used later on in the file. */
1846 #define COP_REG_CLASS_P(CLASS) \
1847 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1848
1849 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1850 is the default value (allocate the registers in numeric order). We
1851 define it just so that we can override it for the mips16 target in
1852 ORDER_REGS_FOR_LOCAL_ALLOC. */
1853
1854 #define REG_ALLOC_ORDER \
1855 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1856 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1857 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1858 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1859 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1860 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1861 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1862 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1863 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1864 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1865 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1866 }
1867
1868 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1869 to be rearranged based on a particular function. On the mips16, we
1870 want to allocate $24 (T_REG) before other registers for
1871 instructions for which it is possible. */
1872
1873 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1874
1875 /* REGISTER AND CONSTANT CLASSES */
1876
1877 /* Get reg_class from a letter such as appears in the machine
1878 description.
1879
1880 DEFINED REGISTER CLASSES:
1881
1882 'd' General (aka integer) registers
1883 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1884 'y' General registers (in both mips16 and non mips16 mode)
1885 'e' Effective address registers (general registers except $25)
1886 't' mips16 temporary register ($24)
1887 'f' Floating point registers
1888 'h' Hi register
1889 'l' Lo register
1890 'x' Multiply/divide registers
1891 'z' FP Status register
1892 'B' Cop0 register
1893 'C' Cop2 register
1894 'D' Cop3 register
1895 'b' All registers */
1896
1897 extern enum reg_class mips_char_to_class[256];
1898
1899 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1900
1901 /* True if VALUE is a signed 16-bit number. */
1902
1903 #define SMALL_OPERAND(VALUE) \
1904 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1905
1906 /* True if VALUE is an unsigned 16-bit number. */
1907
1908 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1909 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1910
1911 /* True if VALUE can be loaded into a register using LUI. */
1912
1913 #define LUI_OPERAND(VALUE) \
1914 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1915 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1916
1917 /* Return a value X with the low 16 bits clear, and such that
1918 VALUE - X is a signed 16-bit value. */
1919
1920 #define CONST_HIGH_PART(VALUE) \
1921 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1922
1923 #define CONST_LOW_PART(VALUE) \
1924 ((VALUE) - CONST_HIGH_PART (VALUE))
1925
1926 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1927 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1928 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1929
1930 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1931 string can be used to stand for particular ranges of immediate
1932 operands. This macro defines what the ranges are. C is the
1933 letter, and VALUE is a constant value. Return 1 if VALUE is
1934 in the range specified by C. */
1935
1936 /* For MIPS:
1937
1938 `I' is used for the range of constants an arithmetic insn can
1939 actually contain (16 bits signed integers).
1940
1941 `J' is used for the range which is just zero (i.e., $r0).
1942
1943 `K' is used for the range of constants a logical insn can actually
1944 contain (16 bit zero-extended integers).
1945
1946 `L' is used for the range of constants that be loaded with lui
1947 (i.e., the bottom 16 bits are zero).
1948
1949 `M' is used for the range of constants that take two words to load
1950 (i.e., not matched by `I', `K', and `L').
1951
1952 `N' is used for negative 16 bit constants other than -65536.
1953
1954 `O' is a 15 bit signed integer.
1955
1956 `P' is used for positive 16 bit constants. */
1957
1958 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1959 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1960 : (C) == 'J' ? ((VALUE) == 0) \
1961 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1962 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1963 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1964 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1965 && !LUI_OPERAND (VALUE)) \
1966 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1967 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1968 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1969 : 0)
1970
1971 /* Similar, but for floating constants, and defining letters G and H.
1972 Here VALUE is the CONST_DOUBLE rtx itself. */
1973
1974 /* For Mips
1975
1976 'G' : Floating point 0 */
1977
1978 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1979 ((C) == 'G' \
1980 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1981
1982 /* Letters in the range `Q' through `U' may be defined in a
1983 machine-dependent fashion to stand for arbitrary operand types.
1984 The machine description macro `EXTRA_CONSTRAINT' is passed the
1985 operand as its first argument and the constraint letter as its
1986 second operand.
1987
1988 `Q' is for signed 16-bit constants.
1989 `R' is for single-instruction memory references. Note that this
1990 constraint has often been used in linux and glibc code.
1991 `S' is for legitimate constant call addresses.
1992 `T' is for constant move_operands that cannot be safely loaded into $25.
1993 `U' is for constant move_operands that can be safely loaded into $25.
1994 `W' is for memory references that are based on a member of BASE_REG_CLASS.
1995 This is true for all non-mips16 references (although it can sometimes
1996 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
1997 stack and constant-pool references.
1998 `YG' is for 0 valued vector constants. */
1999
2000 #define EXTRA_CONSTRAINT_Y(OP,STR) \
2001 (((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
2002 && (OP) == CONST0_RTX (GET_MODE (OP))) \
2003 : FALSE)
2004
2005
2006 #define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
2007 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2008 : ((CODE) == 'R') ? (MEM_P (OP) \
2009 && mips_fetch_insns (OP) == 1) \
2010 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2011 && call_insn_operand (OP, VOIDmode)) \
2012 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2013 && move_operand (OP, VOIDmode) \
2014 && mips_dangerous_for_la25_p (OP)) \
2015 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2016 && move_operand (OP, VOIDmode) \
2017 && !mips_dangerous_for_la25_p (OP)) \
2018 : ((CODE) == 'W') ? (MEM_P (OP) \
2019 && memory_operand (OP, VOIDmode) \
2020 && (!TARGET_MIPS16 \
2021 || (!stack_operand (OP, VOIDmode) \
2022 && !CONSTANT_P (XEXP (OP, 0))))) \
2023 : ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
2024 : FALSE)
2025
2026 /* Y is the only multi-letter constraint, and has length 2. */
2027
2028 #define CONSTRAINT_LEN(C,STR) \
2029 (((C) == 'Y') ? 2 \
2030 : DEFAULT_CONSTRAINT_LEN (C, STR))
2031
2032 /* Say which of the above are memory constraints. */
2033 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2034
2035 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2036 mips_preferred_reload_class (X, CLASS)
2037
2038 /* Certain machines have the property that some registers cannot be
2039 copied to some other registers without using memory. Define this
2040 macro on those machines to be a C expression that is nonzero if
2041 objects of mode MODE in registers of CLASS1 can only be copied to
2042 registers of class CLASS2 by storing a register of CLASS1 into
2043 memory and loading that memory location into a register of CLASS2.
2044
2045 Do not define this macro if its value would always be zero. */
2046 #if 0
2047 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2048 ((!TARGET_DEBUG_H_MODE \
2049 && GET_MODE_CLASS (MODE) == MODE_INT \
2050 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2051 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2052 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2053 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2054 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2055 #endif
2056 /* The HI and LO registers can only be reloaded via the general
2057 registers. Condition code registers can only be loaded to the
2058 general registers, and from the floating point registers. */
2059
2060 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2061 mips_secondary_reload_class (CLASS, MODE, X, 1)
2062 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2063 mips_secondary_reload_class (CLASS, MODE, X, 0)
2064
2065 /* Return the maximum number of consecutive registers
2066 needed to represent mode MODE in a register of class CLASS. */
2067
2068 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2069
2070 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2071 mips_cannot_change_mode_class (FROM, TO, CLASS)
2072 \f
2073 /* Stack layout; function entry, exit and calling. */
2074
2075 #define STACK_GROWS_DOWNWARD
2076
2077 /* The offset of the first local variable from the beginning of the frame.
2078 See compute_frame_size for details about the frame layout.
2079
2080 ??? If flag_profile_values is true, and we are generating 32-bit code, then
2081 we assume that we will need 16 bytes of argument space. This is because
2082 the value profiling code may emit calls to cmpdi2 in leaf functions.
2083 Without this hack, the local variables will start at sp+8 and the gp save
2084 area will be at sp+16, and thus they will overlap. compute_frame_size is
2085 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
2086 will end up as 24 instead of 8. This won't be needed if profiling code is
2087 inserted before virtual register instantiation. */
2088
2089 #define STARTING_FRAME_OFFSET \
2090 ((flag_profile_values && ! TARGET_64BIT \
2091 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
2092 : current_function_outgoing_args_size) \
2093 + (TARGET_ABICALLS && !TARGET_NEWABI \
2094 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2095
2096 #define RETURN_ADDR_RTX mips_return_addr
2097
2098 /* Since the mips16 ISA mode is encoded in the least-significant bit
2099 of the address, mask it off return addresses for purposes of
2100 finding exception handling regions. */
2101
2102 #define MASK_RETURN_ADDR GEN_INT (-2)
2103
2104
2105 /* Similarly, don't use the least-significant bit to tell pointers to
2106 code from vtable index. */
2107
2108 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2109
2110 /* The eliminations to $17 are only used for mips16 code. See the
2111 definition of HARD_FRAME_POINTER_REGNUM. */
2112
2113 #define ELIMINABLE_REGS \
2114 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2115 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2116 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2117 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2118 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2119 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2120
2121 /* We can always eliminate to the hard frame pointer. We can eliminate
2122 to the stack pointer unless a frame pointer is needed.
2123
2124 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2125 reload may be unable to compute the address of a local variable,
2126 since there is no way to add a large constant to the stack pointer
2127 without using a temporary register. */
2128 #define CAN_ELIMINATE(FROM, TO) \
2129 ((TO) == HARD_FRAME_POINTER_REGNUM \
2130 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2131 && (!TARGET_MIPS16 \
2132 || compute_frame_size (get_frame_size ()) < 32768)))
2133
2134 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2135 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2136
2137 /* Allocate stack space for arguments at the beginning of each function. */
2138 #define ACCUMULATE_OUTGOING_ARGS 1
2139
2140 /* The argument pointer always points to the first argument. */
2141 #define FIRST_PARM_OFFSET(FNDECL) 0
2142
2143 /* o32 and o64 reserve stack space for all argument registers. */
2144 #define REG_PARM_STACK_SPACE(FNDECL) \
2145 (TARGET_OLDABI \
2146 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2147 : 0)
2148
2149 /* Define this if it is the responsibility of the caller to
2150 allocate the area reserved for arguments passed in registers.
2151 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2152 of this macro is to determine whether the space is included in
2153 `current_function_outgoing_args_size'. */
2154 #define OUTGOING_REG_PARM_STACK_SPACE
2155
2156 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2157 \f
2158 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2159
2160 /* Symbolic macros for the registers used to return integer and floating
2161 point values. */
2162
2163 #define GP_RETURN (GP_REG_FIRST + 2)
2164 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2165
2166 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2167
2168 /* Symbolic macros for the first/last argument registers. */
2169
2170 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2171 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2172 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2173 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2174
2175 #define LIBCALL_VALUE(MODE) \
2176 mips_function_value (NULL_TREE, NULL, (MODE))
2177
2178 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2179 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2180
2181 /* 1 if N is a possible register number for a function value.
2182 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2183 Currently, R2 and F0 are only implemented here (C has no complex type) */
2184
2185 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2186 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2187 && (N) == FP_RETURN + 2))
2188
2189 /* 1 if N is a possible register number for function argument passing.
2190 We have no FP argument registers when soft-float. When FP registers
2191 are 32 bits, we can't directly reference the odd numbered ones. */
2192
2193 #define FUNCTION_ARG_REGNO_P(N) \
2194 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2195 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2196 && !fixed_regs[N])
2197 \f
2198 /* This structure has to cope with two different argument allocation
2199 schemes. Most MIPS ABIs view the arguments as a structure, of which
2200 the first N words go in registers and the rest go on the stack. If I
2201 < N, the Ith word might go in Ith integer argument register or in a
2202 floating-point register. For these ABIs, we only need to remember
2203 the offset of the current argument into the structure.
2204
2205 The EABI instead allocates the integer and floating-point arguments
2206 separately. The first N words of FP arguments go in FP registers,
2207 the rest go on the stack. Likewise, the first N words of the other
2208 arguments go in integer registers, and the rest go on the stack. We
2209 need to maintain three counts: the number of integer registers used,
2210 the number of floating-point registers used, and the number of words
2211 passed on the stack.
2212
2213 We could keep separate information for the two ABIs (a word count for
2214 the standard ABIs, and three separate counts for the EABI). But it
2215 seems simpler to view the standard ABIs as forms of EABI that do not
2216 allocate floating-point registers.
2217
2218 So for the standard ABIs, the first N words are allocated to integer
2219 registers, and function_arg decides on an argument-by-argument basis
2220 whether that argument should really go in an integer register, or in
2221 a floating-point one. */
2222
2223 typedef struct mips_args {
2224 /* Always true for varargs functions. Otherwise true if at least
2225 one argument has been passed in an integer register. */
2226 int gp_reg_found;
2227
2228 /* The number of arguments seen so far. */
2229 unsigned int arg_number;
2230
2231 /* The number of integer registers used so far. For all ABIs except
2232 EABI, this is the number of words that have been added to the
2233 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2234 unsigned int num_gprs;
2235
2236 /* For EABI, the number of floating-point registers used so far. */
2237 unsigned int num_fprs;
2238
2239 /* The number of words passed on the stack. */
2240 unsigned int stack_words;
2241
2242 /* On the mips16, we need to keep track of which floating point
2243 arguments were passed in general registers, but would have been
2244 passed in the FP regs if this were a 32 bit function, so that we
2245 can move them to the FP regs if we wind up calling a 32 bit
2246 function. We record this information in fp_code, encoded in base
2247 four. A zero digit means no floating point argument, a one digit
2248 means an SFmode argument, and a two digit means a DFmode argument,
2249 and a three digit is not used. The low order digit is the first
2250 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2251 an SFmode argument. ??? A more sophisticated approach will be
2252 needed if MIPS_ABI != ABI_32. */
2253 int fp_code;
2254
2255 /* True if the function has a prototype. */
2256 int prototype;
2257 } CUMULATIVE_ARGS;
2258
2259 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2260 for a call to a function whose data type is FNTYPE.
2261 For a library call, FNTYPE is 0. */
2262
2263 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2264 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2265
2266 /* Update the data in CUM to advance over an argument
2267 of mode MODE and data type TYPE.
2268 (TYPE is null for libcalls where that information may not be available.) */
2269
2270 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2271 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2272
2273 /* Determine where to put an argument to a function.
2274 Value is zero to push the argument on the stack,
2275 or a hard register in which to store the argument.
2276
2277 MODE is the argument's machine mode.
2278 TYPE is the data type of the argument (as a tree).
2279 This is null for libcalls where that information may
2280 not be available.
2281 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2282 the preceding args and about the function being called.
2283 NAMED is nonzero if this argument is a named parameter
2284 (otherwise it is an extra parameter matching an ellipsis). */
2285
2286 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2287 function_arg( &CUM, MODE, TYPE, NAMED)
2288
2289 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2290
2291 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2292 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2293
2294 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2295 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2296
2297 /* True if using EABI and varargs can be passed in floating-point
2298 registers. Under these conditions, we need a more complex form
2299 of va_list, which tracks GPR, FPR and stack arguments separately. */
2300 #define EABI_FLOAT_VARARGS_P \
2301 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2302
2303 \f
2304 /* Say that the epilogue uses the return address register. Note that
2305 in the case of sibcalls, the values "used by the epilogue" are
2306 considered live at the start of the called function. */
2307 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2308
2309 /* Treat LOC as a byte offset from the stack pointer and round it up
2310 to the next fully-aligned offset. */
2311 #define MIPS_STACK_ALIGN(LOC) \
2312 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2313
2314 \f
2315 /* Implement `va_start' for varargs and stdarg. */
2316 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2317 mips_va_start (valist, nextarg)
2318 \f
2319 /* Output assembler code to FILE to increment profiler label # LABELNO
2320 for profiling a function entry. */
2321
2322 #define FUNCTION_PROFILER(FILE, LABELNO) \
2323 { \
2324 if (TARGET_MIPS16) \
2325 sorry ("mips16 function profiling"); \
2326 fprintf (FILE, "\t.set\tnoat\n"); \
2327 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2328 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2329 if (!TARGET_NEWABI) \
2330 { \
2331 fprintf (FILE, \
2332 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2333 TARGET_64BIT ? "dsubu" : "subu", \
2334 reg_names[STACK_POINTER_REGNUM], \
2335 reg_names[STACK_POINTER_REGNUM], \
2336 Pmode == DImode ? 16 : 8); \
2337 } \
2338 fprintf (FILE, "\tjal\t_mcount\n"); \
2339 fprintf (FILE, "\t.set\tat\n"); \
2340 }
2341
2342 /* No mips port has ever used the profiler counter word, so don't emit it
2343 or the label for it. */
2344
2345 #define NO_PROFILE_COUNTERS 1
2346
2347 /* Define this macro if the code for function profiling should come
2348 before the function prologue. Normally, the profiling code comes
2349 after. */
2350
2351 /* #define PROFILE_BEFORE_PROLOGUE */
2352
2353 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2354 the stack pointer does not matter. The value is tested only in
2355 functions that have frame pointers.
2356 No definition is equivalent to always zero. */
2357
2358 #define EXIT_IGNORE_STACK 1
2359
2360 \f
2361 /* A C statement to output, on the stream FILE, assembler code for a
2362 block of data that contains the constant parts of a trampoline.
2363 This code should not include a label--the label is taken care of
2364 automatically. */
2365
2366 #define TRAMPOLINE_TEMPLATE(STREAM) \
2367 { \
2368 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2369 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2370 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2371 if (ptr_mode == DImode) \
2372 { \
2373 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2374 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2375 } \
2376 else \
2377 { \
2378 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2379 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2380 } \
2381 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2382 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2383 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2384 if (ptr_mode == DImode) \
2385 { \
2386 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2387 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2388 } \
2389 else \
2390 { \
2391 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2392 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2393 } \
2394 }
2395
2396 /* A C expression for the size in bytes of the trampoline, as an
2397 integer. */
2398
2399 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2400
2401 /* Alignment required for trampolines, in bits. */
2402
2403 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2404
2405 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2406 program and data caches. */
2407
2408 #ifndef CACHE_FLUSH_FUNC
2409 #define CACHE_FLUSH_FUNC "_flush_cache"
2410 #endif
2411
2412 /* A C statement to initialize the variable parts of a trampoline.
2413 ADDR is an RTX for the address of the trampoline; FNADDR is an
2414 RTX for the address of the nested function; STATIC_CHAIN is an
2415 RTX for the static chain value that should be passed to the
2416 function when it is called. */
2417
2418 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2419 { \
2420 rtx func_addr, chain_addr; \
2421 \
2422 func_addr = plus_constant (ADDR, 32); \
2423 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2424 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2425 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2426 \
2427 /* Flush both caches. We need to flush the data cache in case \
2428 the system has a write-back cache. */ \
2429 /* ??? Should check the return value for errors. */ \
2430 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2431 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2432 0, VOIDmode, 3, ADDR, Pmode, \
2433 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2434 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2435 }
2436 \f
2437 /* Addressing modes, and classification of registers for them. */
2438
2439 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2440 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2441 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2442
2443 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2444 and check its validity for a certain class.
2445 We have two alternate definitions for each of them.
2446 The usual definition accepts all pseudo regs; the other rejects them all.
2447 The symbol REG_OK_STRICT causes the latter definition to be used.
2448
2449 Most source files want to accept pseudo regs in the hope that
2450 they will get allocated to the class that the insn wants them to be in.
2451 Some source files that are used after register allocation
2452 need to be strict. */
2453
2454 #ifndef REG_OK_STRICT
2455 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2456 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2457 #else
2458 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2459 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2460 #endif
2461
2462 #define REG_OK_FOR_INDEX_P(X) 0
2463
2464 \f
2465 /* Maximum number of registers that can appear in a valid memory address. */
2466
2467 #define MAX_REGS_PER_ADDRESS 1
2468
2469 #ifdef REG_OK_STRICT
2470 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2471 { \
2472 if (mips_legitimate_address_p (MODE, X, 1)) \
2473 goto ADDR; \
2474 }
2475 #else
2476 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2477 { \
2478 if (mips_legitimate_address_p (MODE, X, 0)) \
2479 goto ADDR; \
2480 }
2481 #endif
2482
2483 /* Check for constness inline but use mips_legitimate_address_p
2484 to check whether a constant really is an address. */
2485
2486 #define CONSTANT_ADDRESS_P(X) \
2487 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2488
2489 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2490
2491 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2492 do { \
2493 if (mips_legitimize_address (&(X), MODE)) \
2494 goto WIN; \
2495 } while (0)
2496
2497
2498 /* A C statement or compound statement with a conditional `goto
2499 LABEL;' executed if memory address X (an RTX) can have different
2500 meanings depending on the machine mode of the memory reference it
2501 is used for.
2502
2503 Autoincrement and autodecrement addresses typically have
2504 mode-dependent effects because the amount of the increment or
2505 decrement is the size of the operand being addressed. Some
2506 machines have other mode-dependent addresses. Many RISC machines
2507 have no mode-dependent addresses.
2508
2509 You may assume that ADDR is a valid address for the machine. */
2510
2511 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2512
2513 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2514 'the start of the function that this code is output in'. */
2515
2516 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2517 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2518 asm_fprintf ((FILE), "%U%s", \
2519 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2520 else \
2521 asm_fprintf ((FILE), "%U%s", (NAME))
2522 \f
2523 /* Specify the machine mode that this machine uses
2524 for the index in the tablejump instruction.
2525 ??? Using HImode in mips16 mode can cause overflow. */
2526 #define CASE_VECTOR_MODE \
2527 (TARGET_MIPS16 ? HImode : ptr_mode)
2528
2529 /* Define as C expression which evaluates to nonzero if the tablejump
2530 instruction expects the table to contain offsets from the address of the
2531 table.
2532 Do not define this if the table should contain absolute addresses. */
2533 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2534
2535 /* Define this as 1 if `char' should by default be signed; else as 0. */
2536 #ifndef DEFAULT_SIGNED_CHAR
2537 #define DEFAULT_SIGNED_CHAR 1
2538 #endif
2539
2540 /* Max number of bytes we can move from memory to memory
2541 in one reasonably fast instruction. */
2542 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2543 #define MAX_MOVE_MAX 8
2544
2545 /* Define this macro as a C expression which is nonzero if
2546 accessing less than a word of memory (i.e. a `char' or a
2547 `short') is no faster than accessing a word of memory, i.e., if
2548 such access require more than one instruction or if there is no
2549 difference in cost between byte and (aligned) word loads.
2550
2551 On RISC machines, it tends to generate better code to define
2552 this as 1, since it avoids making a QI or HI mode register. */
2553 #define SLOW_BYTE_ACCESS 1
2554
2555 /* Define this to be nonzero if shift instructions ignore all but the low-order
2556 few bits. */
2557 #define SHIFT_COUNT_TRUNCATED 1
2558
2559 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2560 is done just by pretending it is already truncated. */
2561 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2562 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2563
2564
2565 /* Specify the machine mode that pointers have.
2566 After generation of rtl, the compiler makes no further distinction
2567 between pointers and any other objects of this machine mode. */
2568
2569 #ifndef Pmode
2570 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2571 #endif
2572
2573 /* Give call MEMs SImode since it is the "most permissive" mode
2574 for both 32-bit and 64-bit targets. */
2575
2576 #define FUNCTION_MODE SImode
2577
2578 \f
2579 /* The cost of loading values from the constant pool. It should be
2580 larger than the cost of any constant we want to synthesize in-line. */
2581
2582 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2583
2584 /* A C expression for the cost of moving data from a register in
2585 class FROM to one in class TO. The classes are expressed using
2586 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2587 the default; other values are interpreted relative to that.
2588
2589 It is not required that the cost always equal 2 when FROM is the
2590 same as TO; on some machines it is expensive to move between
2591 registers if they are not general registers.
2592
2593 If reload sees an insn consisting of a single `set' between two
2594 hard registers, and if `REGISTER_MOVE_COST' applied to their
2595 classes returns a value of 2, reload does not check to ensure
2596 that the constraints of the insn are met. Setting a cost of
2597 other than 2 will allow reload to verify that the constraints are
2598 met. You should do this if the `movM' pattern's constraints do
2599 not allow such copying. */
2600
2601 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2602 mips_register_move_cost (MODE, FROM, TO)
2603
2604 /* ??? Fix this to be right for the R8000. */
2605 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2606 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2607 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2608
2609 /* Define if copies to/from condition code registers should be avoided.
2610
2611 This is needed for the MIPS because reload_outcc is not complete;
2612 it needs to handle cases where the source is a general or another
2613 condition code register. */
2614 #define AVOID_CCMODE_COPIES
2615
2616 /* A C expression for the cost of a branch instruction. A value of
2617 1 is the default; other values are interpreted relative to that. */
2618
2619 /* ??? Fix this to be right for the R8000. */
2620 #define BRANCH_COST \
2621 ((! TARGET_MIPS16 \
2622 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2623 ? 2 : 1)
2624
2625 /* If defined, modifies the length assigned to instruction INSN as a
2626 function of the context in which it is used. LENGTH is an lvalue
2627 that contains the initially computed length of the insn and should
2628 be updated with the correct length of the insn. */
2629 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2630 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2631 \f
2632 /* Control the assembler format that we output. */
2633
2634 /* Output to assembler file text saying following lines
2635 may contain character constants, extra white space, comments, etc. */
2636
2637 #ifndef ASM_APP_ON
2638 #define ASM_APP_ON " #APP\n"
2639 #endif
2640
2641 /* Output to assembler file text saying following lines
2642 no longer contain unusual constructs. */
2643
2644 #ifndef ASM_APP_OFF
2645 #define ASM_APP_OFF " #NO_APP\n"
2646 #endif
2647
2648 #define REGISTER_NAMES \
2649 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2650 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2651 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2652 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2653 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2654 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2655 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2656 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2657 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2658 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2659 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2660 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2661 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2662 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2663 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2664 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2665 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2666 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2667 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2668 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2669 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2670 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
2671
2672 /* List the "software" names for each register. Also list the numerical
2673 names for $fp and $sp. */
2674
2675 #define ADDITIONAL_REGISTER_NAMES \
2676 { \
2677 { "$29", 29 + GP_REG_FIRST }, \
2678 { "$30", 30 + GP_REG_FIRST }, \
2679 { "at", 1 + GP_REG_FIRST }, \
2680 { "v0", 2 + GP_REG_FIRST }, \
2681 { "v1", 3 + GP_REG_FIRST }, \
2682 { "a0", 4 + GP_REG_FIRST }, \
2683 { "a1", 5 + GP_REG_FIRST }, \
2684 { "a2", 6 + GP_REG_FIRST }, \
2685 { "a3", 7 + GP_REG_FIRST }, \
2686 { "t0", 8 + GP_REG_FIRST }, \
2687 { "t1", 9 + GP_REG_FIRST }, \
2688 { "t2", 10 + GP_REG_FIRST }, \
2689 { "t3", 11 + GP_REG_FIRST }, \
2690 { "t4", 12 + GP_REG_FIRST }, \
2691 { "t5", 13 + GP_REG_FIRST }, \
2692 { "t6", 14 + GP_REG_FIRST }, \
2693 { "t7", 15 + GP_REG_FIRST }, \
2694 { "s0", 16 + GP_REG_FIRST }, \
2695 { "s1", 17 + GP_REG_FIRST }, \
2696 { "s2", 18 + GP_REG_FIRST }, \
2697 { "s3", 19 + GP_REG_FIRST }, \
2698 { "s4", 20 + GP_REG_FIRST }, \
2699 { "s5", 21 + GP_REG_FIRST }, \
2700 { "s6", 22 + GP_REG_FIRST }, \
2701 { "s7", 23 + GP_REG_FIRST }, \
2702 { "t8", 24 + GP_REG_FIRST }, \
2703 { "t9", 25 + GP_REG_FIRST }, \
2704 { "k0", 26 + GP_REG_FIRST }, \
2705 { "k1", 27 + GP_REG_FIRST }, \
2706 { "gp", 28 + GP_REG_FIRST }, \
2707 { "sp", 29 + GP_REG_FIRST }, \
2708 { "fp", 30 + GP_REG_FIRST }, \
2709 { "ra", 31 + GP_REG_FIRST }, \
2710 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2711 }
2712
2713 /* This is meant to be redefined in the host dependent files. It is a
2714 set of alternative names and regnums for mips coprocessors. */
2715
2716 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2717
2718 /* A C compound statement to output to stdio stream STREAM the
2719 assembler syntax for an instruction operand X. X is an RTL
2720 expression.
2721
2722 CODE is a value that can be used to specify one of several ways
2723 of printing the operand. It is used when identical operands
2724 must be printed differently depending on the context. CODE
2725 comes from the `%' specification that was used to request
2726 printing of the operand. If the specification was just `%DIGIT'
2727 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2728 is the ASCII code for LTR.
2729
2730 If X is a register, this macro should print the register's name.
2731 The names can be found in an array `reg_names' whose type is
2732 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2733
2734 When the machine description has a specification `%PUNCT' (a `%'
2735 followed by a punctuation character), this macro is called with
2736 a null pointer for X and the punctuation character for CODE.
2737
2738 See mips.c for the MIPS specific codes. */
2739
2740 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2741
2742 /* A C expression which evaluates to true if CODE is a valid
2743 punctuation character for use in the `PRINT_OPERAND' macro. If
2744 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2745 punctuation characters (except for the standard one, `%') are
2746 used in this way. */
2747
2748 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2749
2750 /* A C compound statement to output to stdio stream STREAM the
2751 assembler syntax for an instruction operand that is a memory
2752 reference whose address is ADDR. ADDR is an RTL expression. */
2753
2754 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2755
2756
2757 /* A C statement, to be executed after all slot-filler instructions
2758 have been output. If necessary, call `dbr_sequence_length' to
2759 determine the number of slots filled in a sequence (zero if not
2760 currently outputting a sequence), to decide how many no-ops to
2761 output, or whatever.
2762
2763 Don't define this macro if it has nothing to do, but it is
2764 helpful in reading assembly output if the extent of the delay
2765 sequence is made explicit (e.g. with white space).
2766
2767 Note that output routines for instructions with delay slots must
2768 be prepared to deal with not being output as part of a sequence
2769 (i.e. when the scheduling pass is not run, or when no slot
2770 fillers could be found.) The variable `final_sequence' is null
2771 when not processing a sequence, otherwise it contains the
2772 `sequence' rtx being output. */
2773
2774 #define DBR_OUTPUT_SEQEND(STREAM) \
2775 do \
2776 { \
2777 if (set_nomacro > 0 && --set_nomacro == 0) \
2778 fputs ("\t.set\tmacro\n", STREAM); \
2779 \
2780 if (set_noreorder > 0 && --set_noreorder == 0) \
2781 fputs ("\t.set\treorder\n", STREAM); \
2782 \
2783 fputs ("\n", STREAM); \
2784 } \
2785 while (0)
2786
2787
2788 /* How to tell the debugger about changes of source files. */
2789 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2790 mips_output_filename (STREAM, NAME)
2791
2792 /* mips-tfile does not understand .stabd directives. */
2793 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2794 dbxout_begin_stabn_sline (LINE); \
2795 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2796 } while (0)
2797
2798 /* Use .loc directives for SDB line numbers. */
2799 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2800 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2801
2802 /* The MIPS implementation uses some labels for its own purpose. The
2803 following lists what labels are created, and are all formed by the
2804 pattern $L[a-z].*. The machine independent portion of GCC creates
2805 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2806
2807 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2808 $Lb[0-9]+ Begin blocks for MIPS debug support
2809 $Lc[0-9]+ Label for use in s<xx> operation.
2810 $Le[0-9]+ End blocks for MIPS debug support */
2811
2812 #undef ASM_DECLARE_OBJECT_NAME
2813 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2814 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2815
2816 /* Globalizing directive for a label. */
2817 #define GLOBAL_ASM_OP "\t.globl\t"
2818
2819 /* This says how to define a global common symbol. */
2820
2821 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2822
2823 /* This says how to define a local common symbol (i.e., not visible to
2824 linker). */
2825
2826 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2827 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2828 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2829 #endif
2830
2831 /* This says how to output an external. It would be possible not to
2832 output anything and let undefined symbol become external. However
2833 the assembler uses length information on externals to allocate in
2834 data/sdata bss/sbss, thereby saving exec time. */
2835
2836 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2837 mips_output_external(STREAM,DECL,NAME)
2838
2839 /* This is how to declare a function name. The actual work of
2840 emitting the label is moved to function_prologue, so that we can
2841 get the line number correctly emitted before the .ent directive,
2842 and after any .file directives. Define as empty so that the function
2843 is not declared before the .ent directive elsewhere. */
2844
2845 #undef ASM_DECLARE_FUNCTION_NAME
2846 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2847
2848 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2849 #define FUNCTION_NAME_ALREADY_DECLARED 0
2850 #endif
2851
2852 /* This is how to store into the string LABEL
2853 the symbol_ref name of an internal numbered label where
2854 PREFIX is the class of label and NUM is the number within the class.
2855 This is suitable for output with `assemble_name'. */
2856
2857 #undef ASM_GENERATE_INTERNAL_LABEL
2858 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2859 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2860
2861 /* This is how to output an element of a case-vector that is absolute. */
2862
2863 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2864 fprintf (STREAM, "\t%s\t%sL%d\n", \
2865 ptr_mode == DImode ? ".dword" : ".word", \
2866 LOCAL_LABEL_PREFIX, \
2867 VALUE)
2868
2869 /* This is how to output an element of a case-vector. We can make the
2870 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2871 is supported. */
2872
2873 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2874 do { \
2875 if (TARGET_MIPS16) \
2876 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2877 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2878 else if (TARGET_GPWORD) \
2879 fprintf (STREAM, "\t%s\t%sL%d\n", \
2880 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2881 LOCAL_LABEL_PREFIX, VALUE); \
2882 else \
2883 fprintf (STREAM, "\t%s\t%sL%d\n", \
2884 ptr_mode == DImode ? ".dword" : ".word", \
2885 LOCAL_LABEL_PREFIX, VALUE); \
2886 } while (0)
2887
2888 /* When generating mips16 code we want to put the jump table in the .text
2889 section. In all other cases, we want to put the jump table in the .rdata
2890 section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
2891 it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
2892 to the .text section if appropriate. */
2893 #undef ASM_OUTPUT_CASE_LABEL
2894 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
2895 do { \
2896 if (TARGET_MIPS16) \
2897 function_section (current_function_decl); \
2898 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2899 } while (0)
2900
2901 /* This is how to output an assembler line
2902 that says to advance the location counter
2903 to a multiple of 2**LOG bytes. */
2904
2905 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2906 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2907
2908 /* This is how to output an assembler line to advance the location
2909 counter by SIZE bytes. */
2910
2911 #undef ASM_OUTPUT_SKIP
2912 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2913 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2914
2915 /* This is how to output a string. */
2916 #undef ASM_OUTPUT_ASCII
2917 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2918 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2919
2920 /* Output #ident as a in the read-only data section. */
2921 #undef ASM_OUTPUT_IDENT
2922 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2923 { \
2924 const char *p = STRING; \
2925 int size = strlen (p) + 1; \
2926 readonly_data_section (); \
2927 assemble_string (p, size); \
2928 }
2929 \f
2930 /* Default to -G 8 */
2931 #ifndef MIPS_DEFAULT_GVALUE
2932 #define MIPS_DEFAULT_GVALUE 8
2933 #endif
2934
2935 /* Define the strings to put out for each section in the object file. */
2936 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2937 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2938 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
2939
2940 #undef READONLY_DATA_SECTION_ASM_OP
2941 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2942 \f
2943 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2944 do \
2945 { \
2946 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2947 TARGET_64BIT ? "dsubu" : "subu", \
2948 reg_names[STACK_POINTER_REGNUM], \
2949 reg_names[STACK_POINTER_REGNUM], \
2950 TARGET_64BIT ? "sd" : "sw", \
2951 reg_names[REGNO], \
2952 reg_names[STACK_POINTER_REGNUM]); \
2953 } \
2954 while (0)
2955
2956 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2957 do \
2958 { \
2959 if (! set_noreorder) \
2960 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2961 \
2962 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2963 TARGET_64BIT ? "ld" : "lw", \
2964 reg_names[REGNO], \
2965 reg_names[STACK_POINTER_REGNUM], \
2966 TARGET_64BIT ? "daddu" : "addu", \
2967 reg_names[STACK_POINTER_REGNUM], \
2968 reg_names[STACK_POINTER_REGNUM]); \
2969 \
2970 if (! set_noreorder) \
2971 fprintf (STREAM, "\t.set\treorder\n"); \
2972 } \
2973 while (0)
2974
2975 /* How to start an assembler comment.
2976 The leading space is important (the mips native assembler requires it). */
2977 #ifndef ASM_COMMENT_START
2978 #define ASM_COMMENT_START " #"
2979 #endif
2980 \f
2981 /* Default definitions for size_t and ptrdiff_t. We must override the
2982 definitions from ../svr4.h on mips-*-linux-gnu. */
2983
2984 #undef SIZE_TYPE
2985 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2986
2987 #undef PTRDIFF_TYPE
2988 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2989
2990 /* See mips_expand_prologue's use of loadgp for when this should be
2991 true. */
2992
2993 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
2994 \f
2995 #ifndef __mips16
2996 /* Since the bits of the _init and _fini function is spread across
2997 many object files, each potentially with its own GP, we must assume
2998 we need to load our GP. We don't preserve $gp or $ra, since each
2999 init/fini chunk is supposed to initialize $gp, and crti/crtn
3000 already take care of preserving $ra and, when appropriate, $gp. */
3001 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3002 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3003 asm (SECTION_OP "\n\
3004 .set noreorder\n\
3005 bal 1f\n\
3006 nop\n\
3007 1: .cpload $31\n\
3008 .set reorder\n\
3009 jal " USER_LABEL_PREFIX #FUNC "\n\
3010 " TEXT_SECTION_ASM_OP);
3011 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3012 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3013 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3014 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3015 asm (SECTION_OP "\n\
3016 .set noreorder\n\
3017 bal 1f\n\
3018 nop\n\
3019 1: .set reorder\n\
3020 .cpsetup $31, $2, 1b\n\
3021 jal " USER_LABEL_PREFIX #FUNC "\n\
3022 " TEXT_SECTION_ASM_OP);
3023 #endif
3024 #endif
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