Sun Niagara specific optimizations.
[official-gcc.git] / gcc / config / sparc / sparc.h
blob1d595bc395b9bfced4aef8c7c5917d36c325fa65
1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
6 at Cygnus Support.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 /* Define the specific costs for a given cpu */
30 struct processor_costs {
31 /* Integer load */
32 const int int_load;
34 /* Integer signed load */
35 const int int_sload;
37 /* Integer zeroed load */
38 const int int_zload;
40 /* Float load */
41 const int float_load;
43 /* fmov, fneg, fabs */
44 const int float_move;
46 /* fadd, fsub */
47 const int float_plusminus;
49 /* fcmp */
50 const int float_cmp;
52 /* fmov, fmovr */
53 const int float_cmove;
55 /* fmul */
56 const int float_mul;
58 /* fdivs */
59 const int float_div_sf;
61 /* fdivd */
62 const int float_div_df;
64 /* fsqrts */
65 const int float_sqrt_sf;
67 /* fsqrtd */
68 const int float_sqrt_df;
70 /* umul/smul */
71 const int int_mul;
73 /* mulX */
74 const int int_mulX;
76 /* integer multiply cost for each bit set past the most
77 significant 3, so the formula for multiply cost becomes:
79 if (rs1 < 0)
80 highest_bit = highest_clear_bit(rs1);
81 else
82 highest_bit = highest_set_bit(rs1);
83 if (highest_bit < 3)
84 highest_bit = 3;
85 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
87 A value of zero indicates that the multiply costs is fixed,
88 and not variable. */
89 const int int_mul_bit_factor;
91 /* udiv/sdiv */
92 const int int_div;
94 /* divX */
95 const int int_divX;
97 /* movcc, movr */
98 const int int_cmove;
100 /* penalty for shifts, due to scheduling rules etc. */
101 const int shift_penalty;
104 extern const struct processor_costs *sparc_costs;
106 /* Target CPU builtins. FIXME: Defining sparc is for the benefit of
107 Solaris only; otherwise just define __sparc__. Sadly the headers
108 are such a mess there is no Solaris-specific header. */
109 #define TARGET_CPU_CPP_BUILTINS() \
110 do \
112 builtin_define_std ("sparc"); \
113 if (TARGET_64BIT) \
115 builtin_assert ("cpu=sparc64"); \
116 builtin_assert ("machine=sparc64"); \
118 else \
120 builtin_assert ("cpu=sparc"); \
121 builtin_assert ("machine=sparc"); \
124 while (0)
126 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
127 /* #define SPARC_BI_ARCH */
129 /* Macro used later in this file to determine default architecture. */
130 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
132 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
133 architectures to compile for. We allow targets to choose compile time or
134 runtime selection. */
135 #ifdef IN_LIBGCC2
136 #if defined(__sparcv9) || defined(__arch64__)
137 #define TARGET_ARCH32 0
138 #else
139 #define TARGET_ARCH32 1
140 #endif /* sparc64 */
141 #else
142 #ifdef SPARC_BI_ARCH
143 #define TARGET_ARCH32 (! TARGET_64BIT)
144 #else
145 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
146 #endif /* SPARC_BI_ARCH */
147 #endif /* IN_LIBGCC2 */
148 #define TARGET_ARCH64 (! TARGET_ARCH32)
150 /* Code model selection in 64-bit environment.
152 The machine mode used for addresses is 32-bit wide:
154 TARGET_CM_32: 32-bit address space.
155 It is the code model used when generating 32-bit code.
157 The machine mode used for addresses is 64-bit wide:
159 TARGET_CM_MEDLOW: 32-bit address space.
160 The executable must be in the low 32 bits of memory.
161 This avoids generating %uhi and %ulo terms. Programs
162 can be statically or dynamically linked.
164 TARGET_CM_MEDMID: 44-bit address space.
165 The executable must be in the low 44 bits of memory,
166 and the %[hml]44 terms are used. The text and data
167 segments have a maximum size of 2GB (31-bit span).
168 The maximum offset from any instruction to the label
169 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
171 TARGET_CM_MEDANY: 64-bit address space.
172 The text and data segments have a maximum size of 2GB
173 (31-bit span) and may be located anywhere in memory.
174 The maximum offset from any instruction to the label
175 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
177 TARGET_CM_EMBMEDANY: 64-bit address space.
178 The text and data segments have a maximum size of 2GB
179 (31-bit span) and may be located anywhere in memory.
180 The global register %g4 contains the start address of
181 the data segment. Programs are statically linked and
182 PIC is not supported.
184 Different code models are not supported in 32-bit environment. */
186 enum cmodel {
187 CM_32,
188 CM_MEDLOW,
189 CM_MEDMID,
190 CM_MEDANY,
191 CM_EMBMEDANY
194 /* One of CM_FOO. */
195 extern enum cmodel sparc_cmodel;
197 /* V9 code model selection. */
198 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
199 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
200 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
201 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
203 #define SPARC_DEFAULT_CMODEL CM_32
205 /* The SPARC-V9 architecture defines a relaxed memory ordering model (RMO)
206 which requires the following macro to be true if enabled. Prior to V9,
207 there are no instructions to even talk about memory synchronization.
208 Note that the UltraSPARC III processors don't implement RMO, unlike the
209 UltraSPARC II processors. Niagara does not implement RMO either.
211 Default to false; for example, Solaris never enables RMO, only ever uses
212 total memory ordering (TMO). */
213 #define SPARC_RELAXED_ORDERING false
215 /* Do not use the .note.GNU-stack convention by default. */
216 #define NEED_INDICATE_EXEC_STACK 0
218 /* This is call-clobbered in the normal ABI, but is reserved in the
219 home grown (aka upward compatible) embedded ABI. */
220 #define EMBMEDANY_BASE_REG "%g4"
222 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
223 and specified by the user via --with-cpu=foo.
224 This specifies the cpu implementation, not the architecture size. */
225 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
226 capable cpu's. */
227 #define TARGET_CPU_sparc 0
228 #define TARGET_CPU_v7 0 /* alias for previous */
229 #define TARGET_CPU_sparclet 1
230 #define TARGET_CPU_sparclite 2
231 #define TARGET_CPU_v8 3 /* generic v8 implementation */
232 #define TARGET_CPU_supersparc 4
233 #define TARGET_CPU_hypersparc 5
234 #define TARGET_CPU_sparc86x 6
235 #define TARGET_CPU_sparclite86x 6
236 #define TARGET_CPU_v9 7 /* generic v9 implementation */
237 #define TARGET_CPU_sparcv9 7 /* alias */
238 #define TARGET_CPU_sparc64 7 /* alias */
239 #define TARGET_CPU_ultrasparc 8
240 #define TARGET_CPU_ultrasparc3 9
241 #define TARGET_CPU_niagara 10
243 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
244 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
245 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
246 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
248 #define CPP_CPU32_DEFAULT_SPEC ""
249 #define ASM_CPU32_DEFAULT_SPEC ""
251 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
252 /* ??? What does Sun's CC pass? */
253 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
254 /* ??? It's not clear how other assemblers will handle this, so by default
255 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
256 is handled in sol2.h. */
257 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
258 #endif
259 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
260 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
261 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
262 #endif
263 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
264 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
265 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
266 #endif
267 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
268 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
269 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
270 #endif
272 #else
274 #define CPP_CPU64_DEFAULT_SPEC ""
275 #define ASM_CPU64_DEFAULT_SPEC ""
277 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
278 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
279 #define CPP_CPU32_DEFAULT_SPEC ""
280 #define ASM_CPU32_DEFAULT_SPEC ""
281 #endif
283 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
284 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
285 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
286 #endif
288 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
289 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
290 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
291 #endif
293 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
294 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
295 #define ASM_CPU32_DEFAULT_SPEC ""
296 #endif
298 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
299 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
300 #define ASM_CPU32_DEFAULT_SPEC ""
301 #endif
303 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
304 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
305 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
306 #endif
308 #endif
310 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
311 #error Unrecognized value in TARGET_CPU_DEFAULT.
312 #endif
314 #ifdef SPARC_BI_ARCH
316 #define CPP_CPU_DEFAULT_SPEC \
317 (DEFAULT_ARCH32_P ? "\
318 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
319 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
320 " : "\
321 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
322 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
324 #define ASM_CPU_DEFAULT_SPEC \
325 (DEFAULT_ARCH32_P ? "\
326 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
327 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
328 " : "\
329 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
330 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
333 #else /* !SPARC_BI_ARCH */
335 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
336 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
338 #endif /* !SPARC_BI_ARCH */
340 /* Define macros to distinguish architectures. */
342 /* Common CPP definitions used by CPP_SPEC amongst the various targets
343 for handling -mcpu=xxx switches. */
344 #define CPP_CPU_SPEC "\
345 %{msoft-float:-D_SOFT_FLOAT} \
346 %{mcypress:} \
347 %{msparclite:-D__sparclite__} \
348 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
349 %{mv8:-D__sparc_v8__} \
350 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
351 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
352 %{mcpu=sparclite:-D__sparclite__} \
353 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
354 %{mcpu=v8:-D__sparc_v8__} \
355 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
356 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
357 %{mcpu=sparclite86x:-D__sparclite86x__} \
358 %{mcpu=v9:-D__sparc_v9__} \
359 %{mcpu=ultrasparc:-D__sparc_v9__} \
360 %{mcpu=ultrasparc3:-D__sparc_v9__} \
361 %{mcpu=niagara:-D__sparc_v9__} \
362 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
364 #define CPP_ARCH32_SPEC ""
365 #define CPP_ARCH64_SPEC "-D__arch64__"
367 #define CPP_ARCH_DEFAULT_SPEC \
368 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
370 #define CPP_ARCH_SPEC "\
371 %{m32:%(cpp_arch32)} \
372 %{m64:%(cpp_arch64)} \
373 %{!m32:%{!m64:%(cpp_arch_default)}} \
376 /* Macros to distinguish endianness. */
377 #define CPP_ENDIAN_SPEC "\
378 %{mlittle-endian:-D__LITTLE_ENDIAN__} \
379 %{mlittle-endian-data:-D__LITTLE_ENDIAN_DATA__}"
381 /* Macros to distinguish the particular subtarget. */
382 #define CPP_SUBTARGET_SPEC ""
384 #define CPP_SPEC "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_subtarget)"
386 /* Prevent error on `-sun4' and `-target sun4' options. */
387 /* This used to translate -dalign to -malign, but that is no good
388 because it can't turn off the usual meaning of making debugging dumps. */
389 /* Translate old style -m<cpu> into new style -mcpu=<cpu>.
390 ??? Delete support for -m<cpu> for 2.9. */
392 #define CC1_SPEC "\
393 %{sun4:} %{target:} \
394 %{mcypress:-mcpu=cypress} \
395 %{msparclite:-mcpu=sparclite} %{mf930:-mcpu=f930} %{mf934:-mcpu=f934} \
396 %{mv8:-mcpu=v8} %{msupersparc:-mcpu=supersparc} \
399 /* Override in target specific files. */
400 #define ASM_CPU_SPEC "\
401 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
402 %{msparclite:-Asparclite} \
403 %{mf930:-Asparclite} %{mf934:-Asparclite} \
404 %{mcpu=sparclite:-Asparclite} \
405 %{mcpu=sparclite86x:-Asparclite} \
406 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
407 %{mv8plus:-Av8plus} \
408 %{mcpu=v9:-Av9} \
409 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
410 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
411 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
412 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
415 /* Word size selection, among other things.
416 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
418 #define ASM_ARCH32_SPEC "-32"
419 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
420 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
421 #else
422 #define ASM_ARCH64_SPEC "-64"
423 #endif
424 #define ASM_ARCH_DEFAULT_SPEC \
425 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
427 #define ASM_ARCH_SPEC "\
428 %{m32:%(asm_arch32)} \
429 %{m64:%(asm_arch64)} \
430 %{!m32:%{!m64:%(asm_arch_default)}} \
433 #ifdef HAVE_AS_RELAX_OPTION
434 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
435 #else
436 #define ASM_RELAX_SPEC ""
437 #endif
439 /* Special flags to the Sun-4 assembler when using pipe for input. */
441 #define ASM_SPEC "\
442 %{R} %{!pg:%{!p:%{fpic|fPIC|fpie|fPIE:-k}}} %{keep-local-as-symbols:-L} \
443 %(asm_cpu) %(asm_relax)"
445 #define AS_NEEDS_DASH_FOR_PIPED_INPUT
447 /* This macro defines names of additional specifications to put in the specs
448 that can be used in various specifications like CC1_SPEC. Its definition
449 is an initializer with a subgrouping for each command option.
451 Each subgrouping contains a string constant, that defines the
452 specification name, and a string constant that used by the GCC driver
453 program.
455 Do not define this macro if it does not need to do anything. */
457 #define EXTRA_SPECS \
458 { "cpp_cpu", CPP_CPU_SPEC }, \
459 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
460 { "cpp_arch32", CPP_ARCH32_SPEC }, \
461 { "cpp_arch64", CPP_ARCH64_SPEC }, \
462 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
463 { "cpp_arch", CPP_ARCH_SPEC }, \
464 { "cpp_endian", CPP_ENDIAN_SPEC }, \
465 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
466 { "asm_cpu", ASM_CPU_SPEC }, \
467 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
468 { "asm_arch32", ASM_ARCH32_SPEC }, \
469 { "asm_arch64", ASM_ARCH64_SPEC }, \
470 { "asm_relax", ASM_RELAX_SPEC }, \
471 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
472 { "asm_arch", ASM_ARCH_SPEC }, \
473 SUBTARGET_EXTRA_SPECS
475 #define SUBTARGET_EXTRA_SPECS
477 /* Because libgcc can generate references back to libc (via .umul etc.) we have
478 to list libc again after the second libgcc. */
479 #define LINK_GCC_C_SEQUENCE_SPEC "%G %L %G %L"
482 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
483 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
485 /* ??? This should be 32 bits for v9 but what can we do? */
486 #define WCHAR_TYPE "short unsigned int"
487 #define WCHAR_TYPE_SIZE 16
489 /* Show we can debug even without a frame pointer. */
490 #define CAN_DEBUG_WITHOUT_FP
492 /* Option handling. */
494 #define OVERRIDE_OPTIONS sparc_override_options ()
496 /* Mask of all CPU selection flags. */
497 #define MASK_ISA \
498 (MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
500 /* TARGET_HARD_MUL: Use hardware multiply instructions but not %y.
501 TARGET_HARD_MUL32: Use hardware multiply instructions with rd %y
502 to get high 32 bits. False in V8+ or V9 because multiply stores
503 a 64 bit result in a register. */
505 #define TARGET_HARD_MUL32 \
506 ((TARGET_V8 || TARGET_SPARCLITE \
507 || TARGET_SPARCLET || TARGET_DEPRECATED_V8_INSNS) \
508 && ! TARGET_V8PLUS && TARGET_ARCH32)
510 #define TARGET_HARD_MUL \
511 (TARGET_V8 || TARGET_SPARCLITE || TARGET_SPARCLET \
512 || TARGET_DEPRECATED_V8_INSNS || TARGET_V8PLUS)
514 /* MASK_APP_REGS must always be the default because that's what
515 FIXED_REGISTERS is set to and -ffixed- is processed before
516 CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */
517 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
519 /* Processor type.
520 These must match the values for the cpu attribute in sparc.md. */
521 enum processor_type {
522 PROCESSOR_V7,
523 PROCESSOR_CYPRESS,
524 PROCESSOR_V8,
525 PROCESSOR_SUPERSPARC,
526 PROCESSOR_SPARCLITE,
527 PROCESSOR_F930,
528 PROCESSOR_F934,
529 PROCESSOR_HYPERSPARC,
530 PROCESSOR_SPARCLITE86X,
531 PROCESSOR_SPARCLET,
532 PROCESSOR_TSC701,
533 PROCESSOR_V9,
534 PROCESSOR_ULTRASPARC,
535 PROCESSOR_ULTRASPARC3,
536 PROCESSOR_NIAGARA
539 /* This is set from -m{cpu,tune}=xxx. */
540 extern enum processor_type sparc_cpu;
542 /* Recast the cpu class to be the cpu attribute.
543 Every file includes us, but not every file includes insn-attr.h. */
544 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
546 /* Support for a compile-time default CPU, et cetera. The rules are:
547 --with-cpu is ignored if -mcpu is specified.
548 --with-tune is ignored if -mtune is specified.
549 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
550 are specified. */
551 #define OPTION_DEFAULT_SPECS \
552 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
553 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
554 {"float", "%{!msoft-float:%{!mhard-float:%{!fpu:%{!no-fpu:-m%(VALUE)-float}}}}" }
556 /* sparc_select[0] is reserved for the default cpu. */
557 struct sparc_cpu_select
559 const char *string;
560 const char *const name;
561 const int set_tune_p;
562 const int set_arch_p;
565 extern struct sparc_cpu_select sparc_select[];
567 /* target machine storage layout */
569 /* Define this if most significant bit is lowest numbered
570 in instructions that operate on numbered bit-fields. */
571 #define BITS_BIG_ENDIAN 1
573 /* Define this if most significant byte of a word is the lowest numbered. */
574 #define BYTES_BIG_ENDIAN 1
576 /* Define this if most significant word of a multiword number is the lowest
577 numbered. */
578 #define WORDS_BIG_ENDIAN 1
580 /* Define this to set the endianness to use in libgcc2.c, which can
581 not depend on target_flags. */
582 #if defined (__LITTLE_ENDIAN__) || defined(__LITTLE_ENDIAN_DATA__)
583 #define LIBGCC2_WORDS_BIG_ENDIAN 0
584 #else
585 #define LIBGCC2_WORDS_BIG_ENDIAN 1
586 #endif
588 #define MAX_BITS_PER_WORD 64
590 /* Width of a word, in units (bytes). */
591 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
592 #ifdef IN_LIBGCC2
593 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
594 #else
595 #define MIN_UNITS_PER_WORD 4
596 #endif
598 #define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : UNITS_PER_WORD)
600 /* Now define the sizes of the C data types. */
602 #define SHORT_TYPE_SIZE 16
603 #define INT_TYPE_SIZE 32
604 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
605 #define LONG_LONG_TYPE_SIZE 64
606 #define FLOAT_TYPE_SIZE 32
607 #define DOUBLE_TYPE_SIZE 64
608 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
609 SPARC ABI says that it is 128-bit wide. */
610 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
612 /* Width in bits of a pointer.
613 See also the macro `Pmode' defined below. */
614 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
616 /* If we have to extend pointers (only when TARGET_ARCH64 and not
617 TARGET_PTR64), we want to do it unsigned. This macro does nothing
618 if ptr_mode and Pmode are the same. */
619 #define POINTERS_EXTEND_UNSIGNED 1
621 /* For TARGET_ARCH64 we need this, as we don't have instructions
622 for arithmetic operations which do zero/sign extension at the same time,
623 so without this we end up with a srl/sra after every assignment to an
624 user variable, which means very very bad code. */
625 #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
626 if (TARGET_ARCH64 \
627 && GET_MODE_CLASS (MODE) == MODE_INT \
628 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
629 (MODE) = word_mode;
631 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
632 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
634 /* Boundary (in *bits*) on which stack pointer should be aligned. */
635 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
636 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */
637 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
638 /* Temporary hack until the FIXME above is fixed. */
639 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
641 /* ALIGN FRAMES on double word boundaries */
643 #define SPARC_STACK_ALIGN(LOC) \
644 (TARGET_ARCH64 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
646 /* Allocation boundary (in *bits*) for the code of a function. */
647 #define FUNCTION_BOUNDARY 32
649 /* Alignment of field after `int : 0' in a structure. */
650 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
652 /* Every structure's size must be a multiple of this. */
653 #define STRUCTURE_SIZE_BOUNDARY 8
655 /* A bit-field declared as `int' forces `int' alignment for the struct. */
656 #define PCC_BITFIELD_TYPE_MATTERS 1
658 /* No data type wants to be aligned rounder than this. */
659 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
661 /* The best alignment to use in cases where we have a choice. */
662 #define FASTEST_ALIGNMENT 64
664 /* Define this macro as an expression for the alignment of a structure
665 (given by STRUCT as a tree node) if the alignment computed in the
666 usual way is COMPUTED and the alignment explicitly specified was
667 SPECIFIED.
669 The default is to use SPECIFIED if it is larger; otherwise, use
670 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
671 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
672 (TARGET_FASTER_STRUCTS ? \
673 ((TREE_CODE (STRUCT) == RECORD_TYPE \
674 || TREE_CODE (STRUCT) == UNION_TYPE \
675 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
676 && TYPE_FIELDS (STRUCT) != 0 \
677 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
678 : MAX ((COMPUTED), (SPECIFIED))) \
679 : MAX ((COMPUTED), (SPECIFIED)))
681 /* Make strings word-aligned so strcpy from constants will be faster. */
682 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
683 ((TREE_CODE (EXP) == STRING_CST \
684 && (ALIGN) < FASTEST_ALIGNMENT) \
685 ? FASTEST_ALIGNMENT : (ALIGN))
687 /* Make arrays of chars word-aligned for the same reasons. */
688 #define DATA_ALIGNMENT(TYPE, ALIGN) \
689 (TREE_CODE (TYPE) == ARRAY_TYPE \
690 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
691 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
693 /* Set this nonzero if move instructions will actually fail to work
694 when given unaligned data. */
695 #define STRICT_ALIGNMENT 1
697 /* Things that must be doubleword aligned cannot go in the text section,
698 because the linker fails to align the text section enough!
699 Put them in the data section. This macro is only used in this file. */
700 #define MAX_TEXT_ALIGN 32
702 /* Standard register usage. */
704 /* Number of actual hardware registers.
705 The hardware registers are assigned numbers for the compiler
706 from 0 to just below FIRST_PSEUDO_REGISTER.
707 All registers that the compiler knows about must be given numbers,
708 even those that are not normally considered general registers.
710 SPARC has 32 integer registers and 32 floating point registers.
711 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
712 accessible. We still account for them to simplify register computations
713 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
714 32+32+32+4 == 100.
715 Register 100 is used as the integer condition code register.
716 Register 101 is used as the soft frame pointer register. */
718 #define FIRST_PSEUDO_REGISTER 102
720 #define SPARC_FIRST_FP_REG 32
721 /* Additional V9 fp regs. */
722 #define SPARC_FIRST_V9_FP_REG 64
723 #define SPARC_LAST_V9_FP_REG 95
724 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
725 #define SPARC_FIRST_V9_FCC_REG 96
726 #define SPARC_LAST_V9_FCC_REG 99
727 /* V8 fcc reg. */
728 #define SPARC_FCC_REG 96
729 /* Integer CC reg. We don't distinguish %icc from %xcc. */
730 #define SPARC_ICC_REG 100
732 /* Nonzero if REGNO is an fp reg. */
733 #define SPARC_FP_REG_P(REGNO) \
734 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
736 /* Argument passing regs. */
737 #define SPARC_OUTGOING_INT_ARG_FIRST 8
738 #define SPARC_INCOMING_INT_ARG_FIRST 24
739 #define SPARC_FP_ARG_FIRST 32
741 /* 1 for registers that have pervasive standard uses
742 and are not available for the register allocator.
744 On non-v9 systems:
745 g1 is free to use as temporary.
746 g2-g4 are reserved for applications. Gcc normally uses them as
747 temporaries, but this can be disabled via the -mno-app-regs option.
748 g5 through g7 are reserved for the operating system.
750 On v9 systems:
751 g1,g5 are free to use as temporaries, and are free to use between calls
752 if the call is to an external function via the PLT.
753 g4 is free to use as a temporary in the non-embedded case.
754 g4 is reserved in the embedded case.
755 g2-g3 are reserved for applications. Gcc normally uses them as
756 temporaries, but this can be disabled via the -mno-app-regs option.
757 g6-g7 are reserved for the operating system (or application in
758 embedded case).
759 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
760 currently be a fixed register until this pattern is rewritten.
761 Register 1 is also used when restoring call-preserved registers in large
762 stack frames.
764 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
765 CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
768 #define FIXED_REGISTERS \
769 {1, 0, 2, 2, 2, 2, 1, 1, \
770 0, 0, 0, 0, 0, 0, 1, 0, \
771 0, 0, 0, 0, 0, 0, 0, 0, \
772 0, 0, 0, 0, 0, 0, 1, 1, \
774 0, 0, 0, 0, 0, 0, 0, 0, \
775 0, 0, 0, 0, 0, 0, 0, 0, \
776 0, 0, 0, 0, 0, 0, 0, 0, \
777 0, 0, 0, 0, 0, 0, 0, 0, \
779 0, 0, 0, 0, 0, 0, 0, 0, \
780 0, 0, 0, 0, 0, 0, 0, 0, \
781 0, 0, 0, 0, 0, 0, 0, 0, \
782 0, 0, 0, 0, 0, 0, 0, 0, \
784 0, 0, 0, 0, 0, 1}
786 /* 1 for registers not available across function calls.
787 These must include the FIXED_REGISTERS and also any
788 registers that can be used without being saved.
789 The latter must include the registers where values are returned
790 and the register where structure-value addresses are passed.
791 Aside from that, you can include as many other registers as you like. */
793 #define CALL_USED_REGISTERS \
794 {1, 1, 1, 1, 1, 1, 1, 1, \
795 1, 1, 1, 1, 1, 1, 1, 1, \
796 0, 0, 0, 0, 0, 0, 0, 0, \
797 0, 0, 0, 0, 0, 0, 1, 1, \
799 1, 1, 1, 1, 1, 1, 1, 1, \
800 1, 1, 1, 1, 1, 1, 1, 1, \
801 1, 1, 1, 1, 1, 1, 1, 1, \
802 1, 1, 1, 1, 1, 1, 1, 1, \
804 1, 1, 1, 1, 1, 1, 1, 1, \
805 1, 1, 1, 1, 1, 1, 1, 1, \
806 1, 1, 1, 1, 1, 1, 1, 1, \
807 1, 1, 1, 1, 1, 1, 1, 1, \
809 1, 1, 1, 1, 1, 1}
811 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
812 they won't be allocated. */
814 #define CONDITIONAL_REGISTER_USAGE \
815 do \
817 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
819 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
820 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
822 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ \
823 /* then honor it. */ \
824 if (TARGET_ARCH32 && fixed_regs[5]) \
825 fixed_regs[5] = 1; \
826 else if (TARGET_ARCH64 && fixed_regs[5] == 2) \
827 fixed_regs[5] = 0; \
828 if (! TARGET_V9) \
830 int regno; \
831 for (regno = SPARC_FIRST_V9_FP_REG; \
832 regno <= SPARC_LAST_V9_FP_REG; \
833 regno++) \
834 fixed_regs[regno] = 1; \
835 /* %fcc0 is used by v8 and v9. */ \
836 for (regno = SPARC_FIRST_V9_FCC_REG + 1; \
837 regno <= SPARC_LAST_V9_FCC_REG; \
838 regno++) \
839 fixed_regs[regno] = 1; \
841 if (! TARGET_FPU) \
843 int regno; \
844 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) \
845 fixed_regs[regno] = 1; \
847 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ \
848 /* then honor it. Likewise with g3 and g4. */ \
849 if (fixed_regs[2] == 2) \
850 fixed_regs[2] = ! TARGET_APP_REGS; \
851 if (fixed_regs[3] == 2) \
852 fixed_regs[3] = ! TARGET_APP_REGS; \
853 if (TARGET_ARCH32 && fixed_regs[4] == 2) \
854 fixed_regs[4] = ! TARGET_APP_REGS; \
855 else if (TARGET_CM_EMBMEDANY) \
856 fixed_regs[4] = 1; \
857 else if (fixed_regs[4] == 2) \
858 fixed_regs[4] = 0; \
860 while (0)
862 /* Return number of consecutive hard regs needed starting at reg REGNO
863 to hold something of mode MODE.
864 This is ordinarily the length in words of a value of mode MODE
865 but can be less for certain modes in special long registers.
867 On SPARC, ordinary registers hold 32 bits worth;
868 this means both integer and floating point registers.
869 On v9, integer regs hold 64 bits worth; floating point regs hold
870 32 bits worth (this includes the new fp regs as even the odd ones are
871 included in the hard register count). */
873 #define HARD_REGNO_NREGS(REGNO, MODE) \
874 (TARGET_ARCH64 \
875 ? ((REGNO) < 32 || (REGNO) == FRAME_POINTER_REGNUM \
876 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
877 : (GET_MODE_SIZE (MODE) + 3) / 4) \
878 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
880 /* Due to the ARCH64 discrepancy above we must override this next
881 macro too. */
882 #define REGMODE_NATURAL_SIZE(MODE) \
883 ((TARGET_ARCH64 && FLOAT_MODE_P (MODE)) ? 4 : UNITS_PER_WORD)
885 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
886 See sparc.c for how we initialize this. */
887 extern const int *hard_regno_mode_classes;
888 extern int sparc_mode_class[];
890 /* ??? Because of the funny way we pass parameters we should allow certain
891 ??? types of float/complex values to be in integer registers during
892 ??? RTL generation. This only matters on arch32. */
893 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
894 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
896 /* Value is 1 if it is OK to rename a hard register FROM to another hard
897 register TO. We cannot rename %g1 as it may be used before the save
898 register window instruction in the prologue. */
899 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
901 /* Value is 1 if it is a good idea to tie two pseudo registers
902 when one has mode MODE1 and one has mode MODE2.
903 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
904 for any hard reg, then this must be 0 for correct output.
906 For V9: SFmode can't be combined with other float modes, because they can't
907 be allocated to the %d registers. Also, DFmode won't fit in odd %f
908 registers, but SFmode will. */
909 #define MODES_TIEABLE_P(MODE1, MODE2) \
910 ((MODE1) == (MODE2) \
911 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
912 && (! TARGET_V9 \
913 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
914 || (MODE1 != SFmode && MODE2 != SFmode)))))
916 /* Specify the registers used for certain standard purposes.
917 The values of these macros are register numbers. */
919 /* Register to use for pushing function arguments. */
920 #define STACK_POINTER_REGNUM 14
922 /* The stack bias (amount by which the hardware register is offset by). */
923 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
925 /* Actual top-of-stack address is 92/176 greater than the contents of the
926 stack pointer register for !v9/v9. That is:
927 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
928 address, and 6*4 bytes for the 6 register parameters.
929 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
930 parameter regs. */
931 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
933 /* Base register for access to local variables of the function. */
934 #define HARD_FRAME_POINTER_REGNUM 30
936 /* The soft frame pointer does not have the stack bias applied. */
937 #define FRAME_POINTER_REGNUM 101
939 /* Given the stack bias, the stack pointer isn't actually aligned. */
940 #define INIT_EXPANDERS \
941 do { \
942 if (cfun && cfun->emit->regno_pointer_align && SPARC_STACK_BIAS) \
944 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
945 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
947 } while (0)
949 /* Value should be nonzero if functions must have frame pointers.
950 Zero means the frame pointer need not be set up (and parms
951 may be accessed via the stack pointer) in functions that seem suitable.
952 Used in flow.c, global.c, ra.c and reload1.c. */
953 #define FRAME_POINTER_REQUIRED \
954 (! (leaf_function_p () && only_leaf_regs_used ()))
956 /* Base register for access to arguments of the function. */
957 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
959 /* Register in which static-chain is passed to a function. This must
960 not be a register used by the prologue. */
961 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
963 /* Register which holds offset table for position-independent
964 data references. */
966 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 23 : INVALID_REGNUM)
968 /* Pick a default value we can notice from override_options:
969 !v9: Default is on.
970 v9: Default is off. */
972 #define DEFAULT_PCC_STRUCT_RETURN -1
974 /* Functions which return large structures get the address
975 to place the wanted value at offset 64 from the frame.
976 Must reserve 64 bytes for the in and local registers.
977 v9: Functions which return large structures get the address to place the
978 wanted value from an invisible first argument. */
979 #define STRUCT_VALUE_OFFSET 64
981 /* Define the classes of registers for register constraints in the
982 machine description. Also define ranges of constants.
984 One of the classes must always be named ALL_REGS and include all hard regs.
985 If there is more than one class, another class must be named NO_REGS
986 and contain no registers.
988 The name GENERAL_REGS must be the name of a class (or an alias for
989 another name such as ALL_REGS). This is the class of registers
990 that is allowed by "g" or "r" in a register constraint.
991 Also, registers outside this class are allocated only when
992 instructions express preferences for them.
994 The classes must be numbered in nondecreasing order; that is,
995 a larger-numbered class must never be contained completely
996 in a smaller-numbered class.
998 For any two classes, it is very desirable that there be another
999 class that represents their union. */
1001 /* The SPARC has various kinds of registers: general, floating point,
1002 and condition codes [well, it has others as well, but none that we
1003 care directly about].
1005 For v9 we must distinguish between the upper and lower floating point
1006 registers because the upper ones can't hold SFmode values.
1007 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
1008 satisfying a group need for a class will also satisfy a single need for
1009 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
1010 regs.
1012 It is important that one class contains all the general and all the standard
1013 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
1014 because reg_class_record() will bias the selection in favor of fp regs,
1015 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
1016 because FP_REGS > GENERAL_REGS.
1018 It is also important that one class contain all the general and all
1019 the fp regs. Otherwise when spilling a DFmode reg, it may be from
1020 EXTRA_FP_REGS but find_reloads() may use class
1021 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
1022 because the compiler thinks it doesn't have a spill reg when in
1023 fact it does.
1025 v9 also has 4 floating point condition code registers. Since we don't
1026 have a class that is the union of FPCC_REGS with either of the others,
1027 it is important that it appear first. Otherwise the compiler will die
1028 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
1029 constraints.
1031 It is important that SPARC_ICC_REG have class NO_REGS. Otherwise combine
1032 may try to use it to hold an SImode value. See register_operand.
1033 ??? Should %fcc[0123] be handled similarly?
1036 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
1037 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
1038 ALL_REGS, LIM_REG_CLASSES };
1040 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1042 /* Give names of register classes as strings for dump file. */
1044 #define REG_CLASS_NAMES \
1045 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
1046 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
1047 "ALL_REGS" }
1049 /* Define which registers fit in which classes.
1050 This is an initializer for a vector of HARD_REG_SET
1051 of length N_REG_CLASSES. */
1053 #define REG_CLASS_CONTENTS \
1054 {{0, 0, 0, 0}, /* NO_REGS */ \
1055 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
1056 {0xffff, 0, 0, 0}, /* I64_REGS */ \
1057 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
1058 {0, -1, 0, 0}, /* FP_REGS */ \
1059 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
1060 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
1061 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
1062 {-1, -1, -1, 0x3f}} /* ALL_REGS */
1064 /* Defines invalid mode changes. Borrowed from pa64-regs.h.
1066 SImode loads to floating-point registers are not zero-extended.
1067 The definition for LOAD_EXTEND_OP specifies that integer loads
1068 narrower than BITS_PER_WORD will be zero-extended. As a result,
1069 we inhibit changes from SImode unless they are to a mode that is
1070 identical in size. */
1072 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1073 (TARGET_ARCH64 \
1074 && (FROM) == SImode \
1075 && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1076 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
1078 /* The same information, inverted:
1079 Return the class number of the smallest class containing
1080 reg number REGNO. This could be a conditional expression
1081 or could index an array. */
1083 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
1085 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
1087 /* This is the order in which to allocate registers normally.
1089 We put %f0-%f7 last among the float registers, so as to make it more
1090 likely that a pseudo-register which dies in the float return register
1091 area will get allocated to the float return register, thus saving a move
1092 instruction at the end of the function.
1094 Similarly for integer return value registers.
1096 We know in this case that we will not end up with a leaf function.
1098 The register allocator is given the global and out registers first
1099 because these registers are call clobbered and thus less useful to
1100 global register allocation.
1102 Next we list the local and in registers. They are not call clobbered
1103 and thus very useful for global register allocation. We list the input
1104 registers before the locals so that it is more likely the incoming
1105 arguments received in those registers can just stay there and not be
1106 reloaded. */
1108 #define REG_ALLOC_ORDER \
1109 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1110 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1111 15, /* %o7 */ \
1112 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1113 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
1114 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1115 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1116 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1117 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1118 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1119 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1120 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1121 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1122 96, 97, 98, 99, /* %fcc0-3 */ \
1123 100, 0, 14, 30, 101} /* %icc, %g0, %o6, %i6, %sfp */
1125 /* This is the order in which to allocate registers for
1126 leaf functions. If all registers can fit in the global and
1127 output registers, then we have the possibility of having a leaf
1128 function.
1130 The macro actually mentioned the input registers first,
1131 because they get renumbered into the output registers once
1132 we know really do have a leaf function.
1134 To be more precise, this register allocation order is used
1135 when %o7 is found to not be clobbered right before register
1136 allocation. Normally, the reason %o7 would be clobbered is
1137 due to a call which could not be transformed into a sibling
1138 call.
1140 As a consequence, it is possible to use the leaf register
1141 allocation order and not end up with a leaf function. We will
1142 not get suboptimal register allocation in that case because by
1143 definition of being potentially leaf, there were no function
1144 calls. Therefore, allocation order within the local register
1145 window is not critical like it is when we do have function calls. */
1147 #define REG_LEAF_ALLOC_ORDER \
1148 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
1149 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
1150 15, /* %o7 */ \
1151 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
1152 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
1153 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
1154 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
1155 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
1156 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
1157 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
1158 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
1159 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
1160 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
1161 96, 97, 98, 99, /* %fcc0-3 */ \
1162 100, 0, 14, 30, 31, 101} /* %icc, %g0, %o6, %i6, %i7, %sfp */
1164 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
1166 extern char sparc_leaf_regs[];
1167 #define LEAF_REGISTERS sparc_leaf_regs
1169 extern char leaf_reg_remap[];
1170 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1172 /* The class value for index registers, and the one for base regs. */
1173 #define INDEX_REG_CLASS GENERAL_REGS
1174 #define BASE_REG_CLASS GENERAL_REGS
1176 /* Local macro to handle the two v9 classes of FP regs. */
1177 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1179 /* Get reg_class from a letter such as appears in the machine description.
1180 In the not-v9 case, coerce v9's 'e' class to 'f', so we can use 'e' in the
1181 .md file for v8 and v9.
1182 'd' and 'b' are used for single and double precision VIS operations,
1183 if TARGET_VIS.
1184 'h' is used for V8+ 64 bit global and out registers. */
1186 #define REG_CLASS_FROM_LETTER(C) \
1187 (TARGET_V9 \
1188 ? ((C) == 'f' ? FP_REGS \
1189 : (C) == 'e' ? EXTRA_FP_REGS \
1190 : (C) == 'c' ? FPCC_REGS \
1191 : ((C) == 'd' && TARGET_VIS) ? FP_REGS\
1192 : ((C) == 'b' && TARGET_VIS) ? EXTRA_FP_REGS\
1193 : ((C) == 'h' && TARGET_V8PLUS) ? I64_REGS\
1194 : NO_REGS) \
1195 : ((C) == 'f' ? FP_REGS \
1196 : (C) == 'e' ? FP_REGS \
1197 : (C) == 'c' ? FPCC_REGS \
1198 : NO_REGS))
1200 /* The letters I, J, K, L, M, N, O, P in a register constraint string
1201 can be used to stand for particular ranges of CONST_INTs.
1202 This macro defines what the ranges are.
1203 C is the letter, and VALUE is a constant value.
1204 Return 1 if VALUE is in the range specified by C.
1206 `I' is used for the range of constants an insn can actually contain.
1207 `J' is used for the range which is just zero (since that is R0).
1208 `K' is used for constants which can be loaded with a single sethi insn.
1209 `L' is used for the range of constants supported by the movcc insns.
1210 `M' is used for the range of constants supported by the movrcc insns.
1211 `N' is like K, but for constants wider than 32 bits.
1212 `O' is used for the range which is just 4096.
1213 `P' is free. */
1215 /* Predicates for 10-bit, 11-bit and 13-bit signed constants. */
1216 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1217 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1218 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1220 /* 10- and 11-bit immediates are only used for a few specific insns.
1221 SMALL_INT is used throughout the port so we continue to use it. */
1222 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1224 /* Predicate for constants that can be loaded with a sethi instruction.
1225 This is the general, 64-bit aware, bitwise version that ensures that
1226 only constants whose representation fits in the mask
1228 0x00000000fffffc00
1230 are accepted. It will reject, for example, negative SImode constants
1231 on 64-bit hosts, so correct handling is to mask the value beforehand
1232 according to the mode of the instruction. */
1233 #define SPARC_SETHI_P(X) \
1234 (((unsigned HOST_WIDE_INT) (X) \
1235 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1237 /* Version of the above predicate for SImode constants and below. */
1238 #define SPARC_SETHI32_P(X) \
1239 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1241 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1242 ((C) == 'I' ? SPARC_SIMM13_P (VALUE) \
1243 : (C) == 'J' ? (VALUE) == 0 \
1244 : (C) == 'K' ? SPARC_SETHI32_P (VALUE) \
1245 : (C) == 'L' ? SPARC_SIMM11_P (VALUE) \
1246 : (C) == 'M' ? SPARC_SIMM10_P (VALUE) \
1247 : (C) == 'N' ? SPARC_SETHI_P (VALUE) \
1248 : (C) == 'O' ? (VALUE) == 4096 \
1249 : 0)
1251 /* Similar, but for CONST_DOUBLEs, and defining letters G and H.
1252 Here VALUE is the CONST_DOUBLE rtx itself. */
1254 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1255 ((C) == 'G' ? const_zero_operand (VALUE, GET_MODE (VALUE)) \
1256 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1257 : 0)
1259 /* Given an rtx X being reloaded into a reg required to be
1260 in class CLASS, return the class of reg to actually use.
1261 In general this is just CLASS; but on some machines
1262 in some cases it is preferable to use a more restrictive class. */
1263 /* - We can't load constants into FP registers.
1264 - We can't load FP constants into integer registers when soft-float,
1265 because there is no soft-float pattern with a r/F constraint.
1266 - We can't load FP constants into integer registers for TFmode unless
1267 it is 0.0L, because there is no movtf pattern with a r/F constraint.
1268 - Try and reload integer constants (symbolic or otherwise) back into
1269 registers directly, rather than having them dumped to memory. */
1271 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1272 (CONSTANT_P (X) \
1273 ? ((FP_REG_CLASS_P (CLASS) \
1274 || (CLASS) == GENERAL_OR_FP_REGS \
1275 || (CLASS) == GENERAL_OR_EXTRA_FP_REGS \
1276 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1277 && ! TARGET_FPU) \
1278 || (GET_MODE (X) == TFmode \
1279 && ! const_zero_operand (X, TFmode))) \
1280 ? NO_REGS \
1281 : (!FP_REG_CLASS_P (CLASS) \
1282 && GET_MODE_CLASS (GET_MODE (X)) == MODE_INT) \
1283 ? GENERAL_REGS \
1284 : (CLASS)) \
1285 : (CLASS))
1287 /* Return the register class of a scratch register needed to load IN into
1288 a register of class CLASS in MODE.
1290 We need a temporary when loading/storing a HImode/QImode value
1291 between memory and the FPU registers. This can happen when combine puts
1292 a paradoxical subreg in a float/fix conversion insn.
1294 We need a temporary when loading/storing a DFmode value between
1295 unaligned memory and the upper FPU registers. */
1297 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1298 ((FP_REG_CLASS_P (CLASS) \
1299 && ((MODE) == HImode || (MODE) == QImode) \
1300 && (GET_CODE (IN) == MEM \
1301 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1302 && true_regnum (IN) == -1))) \
1303 ? GENERAL_REGS \
1304 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1305 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1306 && ! mem_min_alignment ((IN), 8)) \
1307 ? FP_REGS \
1308 : (((TARGET_CM_MEDANY \
1309 && symbolic_operand ((IN), (MODE))) \
1310 || (TARGET_CM_EMBMEDANY \
1311 && text_segment_operand ((IN), (MODE)))) \
1312 && !flag_pic) \
1313 ? GENERAL_REGS \
1314 : NO_REGS)
1316 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1317 ((FP_REG_CLASS_P (CLASS) \
1318 && ((MODE) == HImode || (MODE) == QImode) \
1319 && (GET_CODE (IN) == MEM \
1320 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1321 && true_regnum (IN) == -1))) \
1322 ? GENERAL_REGS \
1323 : ((CLASS) == EXTRA_FP_REGS && (MODE) == DFmode \
1324 && GET_CODE (IN) == MEM && TARGET_ARCH32 \
1325 && ! mem_min_alignment ((IN), 8)) \
1326 ? FP_REGS \
1327 : (((TARGET_CM_MEDANY \
1328 && symbolic_operand ((IN), (MODE))) \
1329 || (TARGET_CM_EMBMEDANY \
1330 && text_segment_operand ((IN), (MODE)))) \
1331 && !flag_pic) \
1332 ? GENERAL_REGS \
1333 : NO_REGS)
1335 /* On SPARC it is not possible to directly move data between
1336 GENERAL_REGS and FP_REGS. */
1337 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1338 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
1340 /* Return the stack location to use for secondary memory needed reloads.
1341 We want to use the reserved location just below the frame pointer.
1342 However, we must ensure that there is a frame, so use assign_stack_local
1343 if the frame size is zero. */
1344 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1345 (get_frame_size () == 0 \
1346 ? assign_stack_local (MODE, GET_MODE_SIZE (MODE), 0) \
1347 : gen_rtx_MEM (MODE, plus_constant (frame_pointer_rtx, \
1348 STARTING_FRAME_OFFSET)))
1350 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1351 because the movsi and movsf patterns don't handle r/f moves.
1352 For v8 we copy the default definition. */
1353 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1354 (TARGET_ARCH64 \
1355 ? (GET_MODE_BITSIZE (MODE) < 32 \
1356 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1357 : MODE) \
1358 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1359 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1360 : MODE))
1362 /* Return the maximum number of consecutive registers
1363 needed to represent mode MODE in a register of class CLASS. */
1364 /* On SPARC, this is the size of MODE in words. */
1365 #define CLASS_MAX_NREGS(CLASS, MODE) \
1366 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1367 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1369 /* Stack layout; function entry, exit and calling. */
1371 /* Define this if pushing a word on the stack
1372 makes the stack pointer a smaller address. */
1373 #define STACK_GROWS_DOWNWARD
1375 /* Define this to nonzero if the nominal address of the stack frame
1376 is at the high-address end of the local variables;
1377 that is, each additional local variable allocated
1378 goes at a more negative offset in the frame. */
1379 #define FRAME_GROWS_DOWNWARD 1
1381 /* Offset within stack frame to start allocating local variables at.
1382 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1383 first local allocated. Otherwise, it is the offset to the BEGINNING
1384 of the first local allocated. */
1385 /* This allows space for one TFmode floating point value, which is used
1386 by SECONDARY_MEMORY_NEEDED_RTX. */
1387 #define STARTING_FRAME_OFFSET \
1388 (TARGET_ARCH64 ? -16 \
1389 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1391 /* Offset of first parameter from the argument pointer register value.
1392 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1393 even if this function isn't going to use it.
1394 v9: This is 128 for the ins and locals. */
1395 #define FIRST_PARM_OFFSET(FNDECL) \
1396 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1398 /* Offset from the argument pointer register value to the CFA.
1399 This is different from FIRST_PARM_OFFSET because the register window
1400 comes between the CFA and the arguments. */
1401 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1403 /* When a parameter is passed in a register, stack space is still
1404 allocated for it.
1405 !v9: All 6 possible integer registers have backing store allocated.
1406 v9: Only space for the arguments passed is allocated. */
1407 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1408 meaning to the backend. Further, we need to be able to detect if a
1409 varargs/unprototyped function is called, as they may want to spill more
1410 registers than we've provided space. Ugly, ugly. So for now we retain
1411 all 6 slots even for v9. */
1412 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1414 /* Definitions for register elimination. */
1416 #define ELIMINABLE_REGS \
1417 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1418 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1420 /* The way this is structured, we can't eliminate SFP in favor of SP
1421 if the frame pointer is required: we want to use the SFP->HFP elimination
1422 in that case. But the test in update_eliminables doesn't know we are
1423 assuming below that we only do the former elimination. */
1424 #define CAN_ELIMINATE(FROM, TO) \
1425 ((TO) == HARD_FRAME_POINTER_REGNUM || !FRAME_POINTER_REQUIRED)
1427 /* We always pretend that this is a leaf function because if it's not,
1428 there's no point in trying to eliminate the frame pointer. If it
1429 is a leaf function, we guessed right! */
1430 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1431 do { \
1432 if ((TO) == STACK_POINTER_REGNUM) \
1433 (OFFSET) = sparc_compute_frame_size (get_frame_size (), 1); \
1434 else \
1435 (OFFSET) = 0; \
1436 (OFFSET) += SPARC_STACK_BIAS; \
1437 } while (0)
1439 /* Keep the stack pointer constant throughout the function.
1440 This is both an optimization and a necessity: longjmp
1441 doesn't behave itself when the stack pointer moves within
1442 the function! */
1443 #define ACCUMULATE_OUTGOING_ARGS 1
1445 /* Value is the number of bytes of arguments automatically
1446 popped when returning from a subroutine call.
1447 FUNDECL is the declaration node of the function (as a tree),
1448 FUNTYPE is the data type of the function (as a tree),
1449 or for a library call it is an identifier node for the subroutine name.
1450 SIZE is the number of bytes of arguments passed on the stack. */
1452 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1454 /* Define this macro if the target machine has "register windows". This
1455 C expression returns the register number as seen by the called function
1456 corresponding to register number OUT as seen by the calling function.
1457 Return OUT if register number OUT is not an outbound register. */
1459 #define INCOMING_REGNO(OUT) \
1460 (((OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1462 /* Define this macro if the target machine has "register windows". This
1463 C expression returns the register number as seen by the calling function
1464 corresponding to register number IN as seen by the called function.
1465 Return IN if register number IN is not an inbound register. */
1467 #define OUTGOING_REGNO(IN) \
1468 (((IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1470 /* Define this macro if the target machine has register windows. This
1471 C expression returns true if the register is call-saved but is in the
1472 register window. */
1474 #define LOCAL_REGNO(REGNO) \
1475 ((REGNO) >= 16 && (REGNO) <= 31)
1477 /* Define how to find the value returned by a function.
1478 VALTYPE is the data type of the value (as a tree).
1479 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1480 otherwise, FUNC is 0. */
1482 /* On SPARC the value is found in the first "output" register. */
1484 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1485 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 1)
1487 /* But the called function leaves it in the first "input" register. */
1489 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1490 function_value ((VALTYPE), TYPE_MODE (VALTYPE), 0)
1492 /* Define how to find the value returned by a library function
1493 assuming the value has mode MODE. */
1495 #define LIBCALL_VALUE(MODE) \
1496 function_value (NULL_TREE, (MODE), 1)
1498 /* 1 if N is a possible register number for a function value
1499 as seen by the caller.
1500 On SPARC, the first "output" reg is used for integer values,
1501 and the first floating point register is used for floating point values. */
1503 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1505 /* Define the size of space to allocate for the return value of an
1506 untyped_call. */
1508 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1510 /* 1 if N is a possible register number for function argument passing.
1511 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1513 #define FUNCTION_ARG_REGNO_P(N) \
1514 (TARGET_ARCH64 \
1515 ? (((N) >= 8 && (N) <= 13) || ((N) >= 32 && (N) <= 63)) \
1516 : ((N) >= 8 && (N) <= 13))
1518 /* Define a data type for recording info about an argument list
1519 during the scan of that argument list. This data type should
1520 hold all necessary information about the function itself
1521 and about the args processed so far, enough to enable macros
1522 such as FUNCTION_ARG to determine where the next arg should go.
1524 On SPARC (!v9), this is a single integer, which is a number of words
1525 of arguments scanned so far (including the invisible argument,
1526 if any, which holds the structure-value-address).
1527 Thus 7 or more means all following args should go on the stack.
1529 For v9, we also need to know whether a prototype is present. */
1531 struct sparc_args {
1532 int words; /* number of words passed so far */
1533 int prototype_p; /* nonzero if a prototype is present */
1534 int libcall_p; /* nonzero if a library call */
1536 #define CUMULATIVE_ARGS struct sparc_args
1538 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1539 for a call to a function whose data type is FNTYPE.
1540 For a library call, FNTYPE is 0. */
1542 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1543 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1545 /* Update the data in CUM to advance over an argument
1546 of mode MODE and data type TYPE.
1547 TYPE is null for libcalls where that information may not be available. */
1549 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1550 function_arg_advance (& (CUM), (MODE), (TYPE), (NAMED))
1552 /* Determine where to put an argument to a function.
1553 Value is zero to push the argument on the stack,
1554 or a hard register in which to store the argument.
1556 MODE is the argument's machine mode.
1557 TYPE is the data type of the argument (as a tree).
1558 This is null for libcalls where that information may
1559 not be available.
1560 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1561 the preceding args and about the function being called.
1562 NAMED is nonzero if this argument is a named parameter
1563 (otherwise it is an extra parameter matching an ellipsis). */
1565 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1566 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 0)
1568 /* Define where a function finds its arguments.
1569 This is different from FUNCTION_ARG because of register windows. */
1571 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1572 function_arg (& (CUM), (MODE), (TYPE), (NAMED), 1)
1574 /* If defined, a C expression which determines whether, and in which direction,
1575 to pad out an argument with extra space. The value should be of type
1576 `enum direction': either `upward' to pad above the argument,
1577 `downward' to pad below, or `none' to inhibit padding. */
1579 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1580 function_arg_padding ((MODE), (TYPE))
1582 /* If defined, a C expression that gives the alignment boundary, in bits,
1583 of an argument with the specified mode and type. If it is not defined,
1584 PARM_BOUNDARY is used for all arguments.
1585 For sparc64, objects requiring 16 byte alignment are passed that way. */
1587 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1588 ((TARGET_ARCH64 \
1589 && (GET_MODE_ALIGNMENT (MODE) == 128 \
1590 || ((TYPE) && TYPE_ALIGN (TYPE) == 128))) \
1591 ? 128 : PARM_BOUNDARY)
1593 /* Define the information needed to generate branch and scc insns. This is
1594 stored from the compare operation. Note that we can't use "rtx" here
1595 since it hasn't been defined! */
1597 extern GTY(()) rtx sparc_compare_op0;
1598 extern GTY(()) rtx sparc_compare_op1;
1599 extern GTY(()) rtx sparc_compare_emitted;
1602 /* Generate the special assembly code needed to tell the assembler whatever
1603 it might need to know about the return value of a function.
1605 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1606 information to the assembler relating to peephole optimization (done in
1607 the assembler). */
1609 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1610 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1612 /* Output the special assembly code needed to tell the assembler some
1613 register is used as global register variable.
1615 SPARC 64bit psABI declares registers %g2 and %g3 as application
1616 registers and %g6 and %g7 as OS registers. Any object using them
1617 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1618 and how they are used (scratch or some global variable).
1619 Linker will then refuse to link together objects which use those
1620 registers incompatibly.
1622 Unless the registers are used for scratch, two different global
1623 registers cannot be declared to the same name, so in the unlikely
1624 case of a global register variable occupying more than one register
1625 we prefix the second and following registers with .gnu.part1. etc. */
1627 extern GTY(()) char sparc_hard_reg_printed[8];
1629 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1630 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1631 do { \
1632 if (TARGET_ARCH64) \
1634 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1635 int reg; \
1636 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1637 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1639 if (reg == (REGNO)) \
1640 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1641 else \
1642 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1643 reg, reg - (REGNO), (NAME)); \
1644 sparc_hard_reg_printed[reg] = 1; \
1647 } while (0)
1648 #endif
1651 /* Emit rtl for profiling. */
1652 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1654 /* All the work done in PROFILE_HOOK, but still required. */
1655 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1657 /* Set the name of the mcount function for the system. */
1658 #define MCOUNT_FUNCTION "*mcount"
1660 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1661 the stack pointer does not matter. The value is tested only in
1662 functions that have frame pointers.
1663 No definition is equivalent to always zero. */
1665 #define EXIT_IGNORE_STACK \
1666 (get_frame_size () != 0 \
1667 || current_function_calls_alloca || current_function_outgoing_args_size)
1669 /* Define registers used by the epilogue and return instruction. */
1670 #define EPILOGUE_USES(REGNO) ((REGNO) == 31 \
1671 || (current_function_calls_eh_return && (REGNO) == 1))
1673 /* Length in units of the trampoline for entering a nested function. */
1675 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1677 #define TRAMPOLINE_ALIGNMENT 128 /* 16 bytes */
1679 /* Emit RTL insns to initialize the variable parts of a trampoline.
1680 FNADDR is an RTX for the address of the function's pure code.
1681 CXT is an RTX for the static chain value for the function. */
1683 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1684 if (TARGET_ARCH64) \
1685 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1686 else \
1687 sparc_initialize_trampoline (TRAMP, FNADDR, CXT)
1689 /* Implement `va_start' for varargs and stdarg. */
1690 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1691 sparc_va_start (valist, nextarg)
1693 /* Generate RTL to flush the register windows so as to make arbitrary frames
1694 available. */
1695 #define SETUP_FRAME_ADDRESSES() \
1696 emit_insn (gen_flush_register_windows ())
1698 /* Given an rtx for the address of a frame,
1699 return an rtx for the address of the word in the frame
1700 that holds the dynamic chain--the previous frame's address. */
1701 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1702 plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1704 /* The return address isn't on the stack, it is in a register, so we can't
1705 access it from the current frame pointer. We can access it from the
1706 previous frame pointer though by reading a value from the register window
1707 save area. */
1708 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1710 /* This is the offset of the return address to the true next instruction to be
1711 executed for the current function. */
1712 #define RETURN_ADDR_OFFSET \
1713 (8 + 4 * (! TARGET_ARCH64 && current_function_returns_struct))
1715 /* The current return address is in %i7. The return address of anything
1716 farther back is in the register window save area at [%fp+60]. */
1717 /* ??? This ignores the fact that the actual return address is +8 for normal
1718 returns, and +12 for structure returns. */
1719 #define RETURN_ADDR_RTX(count, frame) \
1720 ((count == -1) \
1721 ? gen_rtx_REG (Pmode, 31) \
1722 : gen_rtx_MEM (Pmode, \
1723 memory_address (Pmode, plus_constant (frame, \
1724 15 * UNITS_PER_WORD \
1725 + SPARC_STACK_BIAS))))
1727 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1728 +12, but always using +8 is close enough for frame unwind purposes.
1729 Actually, just using %o7 is close enough for unwinding, but %o7+8
1730 is something you can return to. */
1731 #define INCOMING_RETURN_ADDR_RTX \
1732 plus_constant (gen_rtx_REG (word_mode, 15), 8)
1733 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (15)
1735 /* The offset from the incoming value of %sp to the top of the stack frame
1736 for the current function. On sparc64, we have to account for the stack
1737 bias if present. */
1738 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1740 /* Describe how we implement __builtin_eh_return. */
1741 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1742 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 1) /* %g1 */
1743 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 31) /* %i7 */
1745 /* Select a format to encode pointers in exception handling data. CODE
1746 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1747 true if the symbol may be affected by dynamic relocations.
1749 If assembler and linker properly support .uaword %r_disp32(foo),
1750 then use PC relative 32-bit relocations instead of absolute relocs
1751 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1752 for binaries, to save memory.
1754 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1755 symbol %r_disp32() is against was not local, but .hidden. In that
1756 case, we have to use DW_EH_PE_absptr for pic personality. */
1757 #ifdef HAVE_AS_SPARC_UA_PCREL
1758 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1759 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1760 (flag_pic \
1761 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1762 : ((TARGET_ARCH64 && ! GLOBAL) \
1763 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1764 : DW_EH_PE_absptr))
1765 #else
1766 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1767 (flag_pic \
1768 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1769 : ((TARGET_ARCH64 && ! GLOBAL) \
1770 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1771 : DW_EH_PE_absptr))
1772 #endif
1774 /* Emit a PC-relative relocation. */
1775 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1776 do { \
1777 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1778 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1779 assemble_name (FILE, LABEL); \
1780 fputc (')', FILE); \
1781 } while (0)
1782 #endif
1784 /* Addressing modes, and classification of registers for them. */
1786 /* Macros to check register numbers against specific register classes. */
1788 /* These assume that REGNO is a hard or pseudo reg number.
1789 They give nonzero only if REGNO is a hard reg of the suitable class
1790 or a pseudo reg currently allocated to a suitable hard reg.
1791 Since they use reg_renumber, they are safe only once reg_renumber
1792 has been allocated, which happens in local-alloc.c. */
1794 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1795 ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < (unsigned)32 \
1796 || (REGNO) == FRAME_POINTER_REGNUM \
1797 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1799 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1801 #define REGNO_OK_FOR_FP_P(REGNO) \
1802 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1803 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1804 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1805 (TARGET_V9 \
1806 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1807 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1809 /* Now macros that check whether X is a register and also,
1810 strictly, whether it is in a specified class.
1812 These macros are specific to the SPARC, and may be used only
1813 in code for printing assembler insns and in conditions for
1814 define_optimization. */
1816 /* 1 if X is an fp register. */
1818 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1820 /* Is X, a REG, an in or global register? i.e. is regno 0..7 or 24..31 */
1821 #define IN_OR_GLOBAL_P(X) (REGNO (X) < 8 || (REGNO (X) >= 24 && REGNO (X) <= 31))
1823 /* Maximum number of registers that can appear in a valid memory address. */
1825 #define MAX_REGS_PER_ADDRESS 2
1827 /* Recognize any constant value that is a valid address.
1828 When PIC, we do not accept an address that would require a scratch reg
1829 to load into a register. */
1831 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1833 /* Define this, so that when PIC, reload won't try to reload invalid
1834 addresses which require two reload registers. */
1836 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1838 /* Nonzero if the constant value X is a legitimate general operand.
1839 Anything can be made to work except floating point constants.
1840 If TARGET_VIS, 0.0 can be made to work as well. */
1842 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X)
1844 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1845 and check its validity for a certain class.
1846 We have two alternate definitions for each of them.
1847 The usual definition accepts all pseudo regs; the other rejects
1848 them unless they have been allocated suitable hard regs.
1849 The symbol REG_OK_STRICT causes the latter definition to be used.
1851 Most source files want to accept pseudo regs in the hope that
1852 they will get allocated to the class that the insn wants them to be in.
1853 Source files for reload pass need to be strict.
1854 After reload, it makes no difference, since pseudo regs have
1855 been eliminated by then. */
1857 /* Optional extra constraints for this machine.
1859 'Q' handles floating point constants which can be moved into
1860 an integer register with a single sethi instruction.
1862 'R' handles floating point constants which can be moved into
1863 an integer register with a single mov instruction.
1865 'S' handles floating point constants which can be moved into
1866 an integer register using a high/lo_sum sequence.
1868 'T' handles memory addresses where the alignment is known to
1869 be at least 8 bytes.
1871 `U' handles all pseudo registers or a hard even numbered
1872 integer register, needed for ldd/std instructions.
1874 'W' handles the memory operand when moving operands in/out
1875 of 'e' constraint floating point registers.
1877 'Y' handles the zero vector constant. */
1879 #ifndef REG_OK_STRICT
1881 /* Nonzero if X is a hard reg that can be used as an index
1882 or if it is a pseudo reg. */
1883 #define REG_OK_FOR_INDEX_P(X) \
1884 (REGNO (X) < 32 \
1885 || REGNO (X) == FRAME_POINTER_REGNUM \
1886 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
1888 /* Nonzero if X is a hard reg that can be used as a base reg
1889 or if it is a pseudo reg. */
1890 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_INDEX_P (X)
1892 /* 'T', 'U' are for aligned memory loads which aren't needed for arch64.
1893 'W' is like 'T' but is assumed true on arch64.
1895 Remember to accept pseudo-registers for memory constraints if reload is
1896 in progress. */
1898 #define EXTRA_CONSTRAINT(OP, C) \
1899 sparc_extra_constraint_check(OP, C, 0)
1901 #else
1903 /* Nonzero if X is a hard reg that can be used as an index. */
1904 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1905 /* Nonzero if X is a hard reg that can be used as a base reg. */
1906 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1908 #define EXTRA_CONSTRAINT(OP, C) \
1909 sparc_extra_constraint_check(OP, C, 1)
1911 #endif
1913 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1915 #ifdef HAVE_AS_OFFSETABLE_LO10
1916 #define USE_AS_OFFSETABLE_LO10 1
1917 #else
1918 #define USE_AS_OFFSETABLE_LO10 0
1919 #endif
1921 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1922 that is a valid memory address for an instruction.
1923 The MODE argument is the machine mode for the MEM expression
1924 that wants to use this address.
1926 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1927 ordinarily. This changes a bit when generating PIC.
1929 If you change this, execute "rm explow.o recog.o reload.o". */
1931 #define SYMBOLIC_CONST(X) symbolic_operand (X, VOIDmode)
1933 #define RTX_OK_FOR_BASE_P(X) \
1934 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1935 || (GET_CODE (X) == SUBREG \
1936 && GET_CODE (SUBREG_REG (X)) == REG \
1937 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1939 #define RTX_OK_FOR_INDEX_P(X) \
1940 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1941 || (GET_CODE (X) == SUBREG \
1942 && GET_CODE (SUBREG_REG (X)) == REG \
1943 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1945 #define RTX_OK_FOR_OFFSET_P(X) \
1946 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000 - 8)
1948 #define RTX_OK_FOR_OLO10_P(X) \
1949 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0xc00 - 8)
1951 #ifdef REG_OK_STRICT
1952 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1954 if (legitimate_address_p (MODE, X, 1)) \
1955 goto ADDR; \
1957 #else
1958 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1960 if (legitimate_address_p (MODE, X, 0)) \
1961 goto ADDR; \
1963 #endif
1965 /* Go to LABEL if ADDR (a legitimate address expression)
1966 has an effect that depends on the machine mode it is used for.
1968 In PIC mode,
1970 (mem:HI [%l7+a])
1972 is not equivalent to
1974 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
1976 because [%l7+a+1] is interpreted as the address of (a+1). */
1978 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1980 if (flag_pic == 1) \
1982 if (GET_CODE (ADDR) == PLUS) \
1984 rtx op0 = XEXP (ADDR, 0); \
1985 rtx op1 = XEXP (ADDR, 1); \
1986 if (op0 == pic_offset_table_rtx \
1987 && SYMBOLIC_CONST (op1)) \
1988 goto LABEL; \
1993 /* Try machine-dependent ways of modifying an illegitimate address
1994 to be legitimate. If we find one, return the new, valid address.
1995 This macro is used in only one place: `memory_address' in explow.c.
1997 OLDX is the address as it was before break_out_memory_refs was called.
1998 In some cases it is useful to look at this to decide what needs to be done.
2000 MODE and WIN are passed so that this macro can use
2001 GO_IF_LEGITIMATE_ADDRESS.
2003 It is always safe for this macro to do nothing. It exists to recognize
2004 opportunities to optimize the output. */
2006 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
2007 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2009 (X) = legitimize_address (X, OLDX, MODE); \
2010 if (memory_address_p (MODE, X)) \
2011 goto WIN; \
2014 /* Try a machine-dependent way of reloading an illegitimate address
2015 operand. If we find one, push the reload and jump to WIN. This
2016 macro is used in only one place: `find_reloads_address' in reload.c.
2018 For SPARC 32, we wish to handle addresses by splitting them into
2019 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
2020 This cuts the number of extra insns by one.
2022 Do nothing when generating PIC code and the address is a
2023 symbolic operand or requires a scratch register. */
2025 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2026 do { \
2027 /* Decompose SImode constants into hi+lo_sum. We do have to \
2028 rerecognize what we produce, so be careful. */ \
2029 if (CONSTANT_P (X) \
2030 && (MODE != TFmode || TARGET_ARCH64) \
2031 && GET_MODE (X) == SImode \
2032 && GET_CODE (X) != LO_SUM && GET_CODE (X) != HIGH \
2033 && ! (flag_pic \
2034 && (symbolic_operand (X, Pmode) \
2035 || pic_address_needs_scratch (X))) \
2036 && sparc_cmodel <= CM_MEDLOW) \
2038 X = gen_rtx_LO_SUM (GET_MODE (X), \
2039 gen_rtx_HIGH (GET_MODE (X), X), X); \
2040 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
2041 BASE_REG_CLASS, GET_MODE (X), VOIDmode, 0, 0, \
2042 OPNUM, TYPE); \
2043 goto WIN; \
2045 /* ??? 64-bit reloads. */ \
2046 } while (0)
2048 /* Specify the machine mode that this machine uses
2049 for the index in the tablejump instruction. */
2050 /* If we ever implement any of the full models (such as CM_FULLANY),
2051 this has to be DImode in that case */
2052 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2053 #define CASE_VECTOR_MODE \
2054 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
2055 #else
2056 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
2057 we have to sign extend which slows things down. */
2058 #define CASE_VECTOR_MODE \
2059 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
2060 #endif
2062 /* Define this as 1 if `char' should by default be signed; else as 0. */
2063 #define DEFAULT_SIGNED_CHAR 1
2065 /* Max number of bytes we can move from memory to memory
2066 in one reasonably fast instruction. */
2067 #define MOVE_MAX 8
2069 /* If a memory-to-memory move would take MOVE_RATIO or more simple
2070 move-instruction pairs, we will do a movmem or libcall instead. */
2072 #define MOVE_RATIO (optimize_size ? 3 : 8)
2074 /* Define if operations between registers always perform the operation
2075 on the full register even if a narrower mode is specified. */
2076 #define WORD_REGISTER_OPERATIONS
2078 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2079 will either zero-extend or sign-extend. The value of this macro should
2080 be the code that says which one of the two operations is implicitly
2081 done, UNKNOWN if none. */
2082 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2084 /* Nonzero if access to memory by bytes is slow and undesirable.
2085 For RISC chips, it means that access to memory by bytes is no
2086 better than access by words when possible, so grab a whole word
2087 and maybe make use of that. */
2088 #define SLOW_BYTE_ACCESS 1
2090 /* Define this to be nonzero if shift instructions ignore all but the low-order
2091 few bits. */
2092 #define SHIFT_COUNT_TRUNCATED 1
2094 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2095 is done just by pretending it is already truncated. */
2096 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2098 /* Specify the machine mode used for addresses. */
2099 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
2101 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2102 return the mode to be used for the comparison. For floating-point,
2103 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2104 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2105 processing is needed. */
2106 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
2108 /* Return nonzero if MODE implies a floating point inequality can be
2109 reversed. For SPARC this is always true because we have a full
2110 compliment of ordered and unordered comparisons, but until generic
2111 code knows how to reverse it correctly we keep the old definition. */
2112 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
2114 /* A function address in a call instruction for indexing purposes. */
2115 #define FUNCTION_MODE Pmode
2117 /* Define this if addresses of constant functions
2118 shouldn't be put through pseudo regs where they can be cse'd.
2119 Desirable on machines where ordinary constants are expensive
2120 but a CALL with constant address is cheap. */
2121 #define NO_FUNCTION_CSE
2123 /* alloca should avoid clobbering the old register save area. */
2124 #define SETJMP_VIA_SAVE_AREA
2126 /* The _Q_* comparison libcalls return booleans. */
2127 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
2129 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
2130 that the inputs are fully consumed before the output memory is clobbered. */
2132 #define TARGET_BUGGY_QP_LIB 0
2134 /* Assume by default that we do not have the Solaris-specific conversion
2135 routines nor 64-bit integer multiply and divide routines. */
2137 #define SUN_CONVERSION_LIBFUNCS 0
2138 #define DITF_CONVERSION_LIBFUNCS 0
2139 #define SUN_INTEGER_MULTIPLY_64 0
2141 /* Compute extra cost of moving data between one register class
2142 and another. */
2143 #define GENERAL_OR_I64(C) ((C) == GENERAL_REGS || (C) == I64_REGS)
2144 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
2145 (((FP_REG_CLASS_P (CLASS1) && GENERAL_OR_I64 (CLASS2)) \
2146 || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
2147 || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
2148 ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
2149 || sparc_cpu == PROCESSOR_ULTRASPARC3 \
2150 || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2)
2152 /* Provide the cost of a branch. For pre-v9 processors we use
2153 a value of 3 to take into account the potential annulling of
2154 the delay slot (which ends up being a bubble in the pipeline slot)
2155 plus a cycle to take into consideration the instruction cache
2156 effects.
2158 On v9 and later, which have branch prediction facilities, we set
2159 it to the depth of the pipeline as that is the cost of a
2160 mispredicted branch.
2162 On Niagara, normal branches insert 3 bubbles into the pipe
2163 and annulled branches insert 4 bubbles. */
2165 #define BRANCH_COST \
2166 ((sparc_cpu == PROCESSOR_V9 \
2167 || sparc_cpu == PROCESSOR_ULTRASPARC) \
2168 ? 7 \
2169 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2170 ? 9 \
2171 : (sparc_cpu == PROCESSOR_NIAGARA \
2172 ? 4 \
2173 : 3)))
2175 #define PREFETCH_BLOCK \
2176 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2177 || sparc_cpu == PROCESSOR_ULTRASPARC3 \
2178 || sparc_cpu == PROCESSOR_NIAGARA) \
2179 ? 64 : 32)
2181 #define SIMULTANEOUS_PREFETCHES \
2182 ((sparc_cpu == PROCESSOR_ULTRASPARC \
2183 || sparc_cpu == PROCESSOR_NIAGARA) \
2184 ? 2 \
2185 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
2186 ? 8 : 3))
2188 /* Control the assembler format that we output. */
2190 /* A C string constant describing how to begin a comment in the target
2191 assembler language. The compiler assumes that the comment will end at
2192 the end of the line. */
2194 #define ASM_COMMENT_START "!"
2196 /* Output to assembler file text saying following lines
2197 may contain character constants, extra white space, comments, etc. */
2199 #define ASM_APP_ON ""
2201 /* Output to assembler file text saying following lines
2202 no longer contain unusual constructs. */
2204 #define ASM_APP_OFF ""
2206 /* How to refer to registers in assembler output.
2207 This sequence is indexed by compiler's hard-register-number (see above). */
2209 #define REGISTER_NAMES \
2210 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2211 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2212 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2213 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2214 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2215 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2216 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2217 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2218 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2219 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2220 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2221 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2222 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp" }
2224 /* Define additional names for use in asm clobbers and asm declarations. */
2226 #define ADDITIONAL_REGISTER_NAMES \
2227 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
2229 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
2230 can run past this up to a continuation point. Once we used 1500, but
2231 a single entry in C++ can run more than 500 bytes, due to the length of
2232 mangled symbol names. dbxout.c should really be fixed to do
2233 continuations when they are actually needed instead of trying to
2234 guess... */
2235 #define DBX_CONTIN_LENGTH 1000
2237 /* This is how to output a command to make the user-level label named NAME
2238 defined for reference from other files. */
2240 /* Globalizing directive for a label. */
2241 #define GLOBAL_ASM_OP "\t.global "
2243 /* The prefix to add to user-visible assembler symbols. */
2245 #define USER_LABEL_PREFIX "_"
2247 /* This is how to store into the string LABEL
2248 the symbol_ref name of an internal numbered label where
2249 PREFIX is the class of label and NUM is the number within the class.
2250 This is suitable for output with `assemble_name'. */
2252 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2253 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
2255 /* This is how we hook in and defer the case-vector until the end of
2256 the function. */
2257 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
2258 sparc_defer_case_vector ((LAB),(VEC), 0)
2260 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
2261 sparc_defer_case_vector ((LAB),(VEC), 1)
2263 /* This is how to output an element of a case-vector that is absolute. */
2265 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2266 do { \
2267 char label[30]; \
2268 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2269 if (CASE_VECTOR_MODE == SImode) \
2270 fprintf (FILE, "\t.word\t"); \
2271 else \
2272 fprintf (FILE, "\t.xword\t"); \
2273 assemble_name (FILE, label); \
2274 fputc ('\n', FILE); \
2275 } while (0)
2277 /* This is how to output an element of a case-vector that is relative.
2278 (SPARC uses such vectors only when generating PIC.) */
2280 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2281 do { \
2282 char label[30]; \
2283 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
2284 if (CASE_VECTOR_MODE == SImode) \
2285 fprintf (FILE, "\t.word\t"); \
2286 else \
2287 fprintf (FILE, "\t.xword\t"); \
2288 assemble_name (FILE, label); \
2289 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
2290 fputc ('-', FILE); \
2291 assemble_name (FILE, label); \
2292 fputc ('\n', FILE); \
2293 } while (0)
2295 /* This is what to output before and after case-vector (both
2296 relative and absolute). If .subsection -1 works, we put case-vectors
2297 at the beginning of the current section. */
2299 #ifdef HAVE_GAS_SUBSECTION_ORDERING
2301 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
2302 fprintf(FILE, "\t.subsection\t-1\n")
2304 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
2305 fprintf(FILE, "\t.previous\n")
2307 #endif
2309 /* This is how to output an assembler line
2310 that says to advance the location counter
2311 to a multiple of 2**LOG bytes. */
2313 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2314 if ((LOG) != 0) \
2315 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2317 /* This is how to output an assembler line that says to advance
2318 the location counter to a multiple of 2**LOG bytes using the
2319 "nop" instruction as padding. */
2320 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \
2321 if ((LOG) != 0) \
2322 fprintf (FILE, "\t.align %d,0x1000000\n", (1<<(LOG)))
2324 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2325 fprintf (FILE, "\t.skip "HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2327 /* This says how to output an assembler line
2328 to define a global common symbol. */
2330 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2331 ( fputs ("\t.common ", (FILE)), \
2332 assemble_name ((FILE), (NAME)), \
2333 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
2335 /* This says how to output an assembler line to define a local common
2336 symbol. */
2338 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2339 ( fputs ("\t.reserve ", (FILE)), \
2340 assemble_name ((FILE), (NAME)), \
2341 fprintf ((FILE), ","HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
2342 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2344 /* A C statement (sans semicolon) to output to the stdio stream
2345 FILE the assembler definition of uninitialized global DECL named
2346 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
2347 Try to use asm_output_aligned_bss to implement this macro. */
2349 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2350 do { \
2351 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
2352 } while (0)
2354 #define IDENT_ASM_OP "\t.ident\t"
2356 /* Output #ident as a .ident. */
2358 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2359 fprintf (FILE, "%s\"%s\"\n", IDENT_ASM_OP, NAME);
2361 /* Prettify the assembly. */
2363 extern int sparc_indent_opcode;
2365 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
2366 do { \
2367 if (sparc_indent_opcode) \
2369 putc (' ', FILE); \
2370 sparc_indent_opcode = 0; \
2372 } while (0)
2374 #define SPARC_SYMBOL_REF_TLS_P(RTX) \
2375 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
2377 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2378 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '(' \
2379 || (CHAR) == ')' || (CHAR) == '_' || (CHAR) == '&')
2381 /* Print operand X (an rtx) in assembler syntax to file FILE.
2382 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2383 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2385 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2387 /* Print a memory address as an operand to reference that memory location. */
2389 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2390 { register rtx base, index = 0; \
2391 int offset = 0; \
2392 register rtx addr = ADDR; \
2393 if (GET_CODE (addr) == REG) \
2394 fputs (reg_names[REGNO (addr)], FILE); \
2395 else if (GET_CODE (addr) == PLUS) \
2397 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2398 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2399 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2400 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2401 else \
2402 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2403 if (GET_CODE (base) == LO_SUM) \
2405 gcc_assert (USE_AS_OFFSETABLE_LO10 \
2406 && TARGET_ARCH64 \
2407 && ! TARGET_CM_MEDMID); \
2408 output_operand (XEXP (base, 0), 0); \
2409 fputs ("+%lo(", FILE); \
2410 output_address (XEXP (base, 1)); \
2411 fprintf (FILE, ")+%d", offset); \
2413 else \
2415 fputs (reg_names[REGNO (base)], FILE); \
2416 if (index == 0) \
2417 fprintf (FILE, "%+d", offset); \
2418 else if (GET_CODE (index) == REG) \
2419 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2420 else if (GET_CODE (index) == SYMBOL_REF \
2421 || GET_CODE (index) == CONST) \
2422 fputc ('+', FILE), output_addr_const (FILE, index); \
2423 else gcc_unreachable (); \
2426 else if (GET_CODE (addr) == MINUS \
2427 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2429 output_addr_const (FILE, XEXP (addr, 0)); \
2430 fputs ("-(", FILE); \
2431 output_addr_const (FILE, XEXP (addr, 1)); \
2432 fputs ("-.)", FILE); \
2434 else if (GET_CODE (addr) == LO_SUM) \
2436 output_operand (XEXP (addr, 0), 0); \
2437 if (TARGET_CM_MEDMID) \
2438 fputs ("+%l44(", FILE); \
2439 else \
2440 fputs ("+%lo(", FILE); \
2441 output_address (XEXP (addr, 1)); \
2442 fputc (')', FILE); \
2444 else if (flag_pic && GET_CODE (addr) == CONST \
2445 && GET_CODE (XEXP (addr, 0)) == MINUS \
2446 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2447 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2448 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2450 addr = XEXP (addr, 0); \
2451 output_addr_const (FILE, XEXP (addr, 0)); \
2452 /* Group the args of the second CONST in parenthesis. */ \
2453 fputs ("-(", FILE); \
2454 /* Skip past the second CONST--it does nothing for us. */\
2455 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2456 /* Close the parenthesis. */ \
2457 fputc (')', FILE); \
2459 else \
2461 output_addr_const (FILE, addr); \
2465 /* TLS support defaulting to original Sun flavor. GNU extensions
2466 must be activated in separate configuration files. */
2467 #ifdef HAVE_AS_TLS
2468 #define TARGET_TLS 1
2469 #else
2470 #define TARGET_TLS 0
2471 #endif
2473 #define TARGET_SUN_TLS TARGET_TLS
2474 #define TARGET_GNU_TLS 0
2476 /* The number of Pmode words for the setjmp buffer. */
2477 #define JMP_BUF_SIZE 12