testsuite/52641 - Fix more sloppy tests.
[official-gcc.git] / gcc / config / sparc / sparc.h
blob8612832a03ecb7fef72848e365da7bebd9ea5ebf
1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987-2024 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
5 at Cygnus Support.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
23 #include "config/vxworks-dummy.h"
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()
30 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
31 /* #define SPARC_BI_ARCH */
33 /* Macro used later in this file to determine default architecture. */
34 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
36 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
37 architectures to compile for. We allow targets to choose compile time or
38 runtime selection. */
39 #ifdef IN_LIBGCC2
40 #if defined(__sparcv9) || defined(__arch64__)
41 #define TARGET_ARCH32 0
42 #else
43 #define TARGET_ARCH32 1
44 #endif /* sparc64 */
45 #else
46 #ifdef SPARC_BI_ARCH
47 #define TARGET_ARCH32 (!TARGET_64BIT)
48 #else
49 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
50 #endif /* SPARC_BI_ARCH */
51 #endif /* IN_LIBGCC2 */
52 #define TARGET_ARCH64 (!TARGET_ARCH32)
54 /* Code model selection in 64-bit environment.
56 The machine mode used for addresses is 32-bit wide:
58 TARGET_CM_32: 32-bit address space.
59 It is the code model used when generating 32-bit code.
61 The machine mode used for addresses is 64-bit wide:
63 TARGET_CM_MEDLOW: 32-bit address space.
64 The executable must be in the low 32 bits of memory.
65 This avoids generating %uhi and %ulo terms. Programs
66 can be statically or dynamically linked.
68 TARGET_CM_MEDMID: 44-bit address space.
69 The executable must be in the low 44 bits of memory,
70 and the %[hml]44 terms are used. The text and data
71 segments have a maximum size of 2GB (31-bit span).
72 The maximum offset from any instruction to the label
73 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
75 TARGET_CM_MEDANY: 64-bit address space.
76 The text and data segments have a maximum size of 2GB
77 (31-bit span) and may be located anywhere in memory.
78 The maximum offset from any instruction to the label
79 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
81 TARGET_CM_EMBMEDANY: 64-bit address space.
82 The text and data segments have a maximum size of 2GB
83 (31-bit span) and may be located anywhere in memory.
84 The global register %g4 contains the start address of
85 the data segment. Programs are statically linked and
86 PIC is not supported.
88 Different code models are not supported in 32-bit environment. */
90 #define TARGET_CM_MEDLOW (sparc_code_model == CM_MEDLOW)
91 #define TARGET_CM_MEDMID (sparc_code_model == CM_MEDMID)
92 #define TARGET_CM_MEDANY (sparc_code_model == CM_MEDANY)
93 #define TARGET_CM_EMBMEDANY (sparc_code_model == CM_EMBMEDANY)
95 /* Default code model to be overridden in 64-bit environment. */
96 #define SPARC_DEFAULT_CMODEL CM_32
98 /* Do not use the .note.GNU-stack convention by default. */
99 #define NEED_INDICATE_EXEC_STACK 0
101 /* This is call-clobbered in the normal ABI, but is reserved in the
102 home grown (aka upward compatible) embedded ABI. */
103 #define EMBMEDANY_BASE_REG "%g4"
105 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
106 and specified by the user via --with-cpu=foo.
107 This specifies the cpu implementation, not the architecture size. */
108 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
109 capable cpu's. */
110 #define TARGET_CPU_sparc 0
111 #define TARGET_CPU_v7 0 /* alias */
112 #define TARGET_CPU_cypress 0 /* alias */
113 #define TARGET_CPU_v8 1 /* generic v8 implementation */
114 #define TARGET_CPU_supersparc 2
115 #define TARGET_CPU_hypersparc 3
116 #define TARGET_CPU_leon 4
117 #define TARGET_CPU_leon3 5
118 #define TARGET_CPU_leon3v7 6
119 #define TARGET_CPU_leon5 7
120 #define TARGET_CPU_sparclite 8
121 #define TARGET_CPU_f930 8 /* alias */
122 #define TARGET_CPU_f934 8 /* alias */
123 #define TARGET_CPU_sparclite86x 9
124 #define TARGET_CPU_sparclet 10
125 #define TARGET_CPU_tsc701 10 /* alias */
126 #define TARGET_CPU_v9 11 /* generic v9 implementation */
127 #define TARGET_CPU_sparcv9 11 /* alias */
128 #define TARGET_CPU_sparc64 11 /* alias */
129 #define TARGET_CPU_ultrasparc 12
130 #define TARGET_CPU_ultrasparc3 13
131 #define TARGET_CPU_niagara 14
132 #define TARGET_CPU_niagara2 15
133 #define TARGET_CPU_niagara3 16
134 #define TARGET_CPU_niagara4 17
135 #define TARGET_CPU_niagara7 19
136 #define TARGET_CPU_m8 20
138 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
139 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
140 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
141 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
142 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \
143 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \
144 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \
145 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 \
146 || TARGET_CPU_DEFAULT == TARGET_CPU_m8
148 #define CPP_CPU32_DEFAULT_SPEC ""
149 #define ASM_CPU32_DEFAULT_SPEC ""
151 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
152 /* ??? What does Sun's CC pass? */
153 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
154 /* ??? It's not clear how other assemblers will handle this, so by default
155 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
156 is handled in sol2.h. */
157 #define ASM_CPU64_DEFAULT_SPEC "-Av9"
158 #endif
159 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
160 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
161 #define ASM_CPU64_DEFAULT_SPEC "-Av9a"
162 #endif
163 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
164 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
165 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
166 #endif
167 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
168 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
169 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
170 #endif
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
172 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
173 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
174 #endif
175 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3
176 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
177 #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG
178 #endif
179 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4
180 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
181 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG
182 #endif
183 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7
184 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
185 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG
186 #endif
187 #if TARGET_CPU_DEFAULT == TARGET_CPU_m8
188 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
189 #define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG
190 #endif
192 #else
194 #define CPP_CPU64_DEFAULT_SPEC ""
195 #define ASM_CPU64_DEFAULT_SPEC ""
197 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
198 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
199 #define CPP_CPU32_DEFAULT_SPEC ""
200 #define ASM_CPU32_DEFAULT_SPEC ""
201 #endif
203 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
204 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__"
205 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet"
206 #endif
208 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
209 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__"
210 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
211 #endif
213 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
214 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__"
215 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite"
216 #endif
218 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
219 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__"
220 #define ASM_CPU32_DEFAULT_SPEC ""
221 #endif
223 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
224 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__"
225 #define ASM_CPU32_DEFAULT_SPEC ""
226 #endif
228 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \
229 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 \
230 || TARGET_CPU_DEFAULT == TARGET_CPU_leon5
231 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__"
232 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
233 #endif
235 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7
236 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__"
237 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG
238 #endif
240 #endif
242 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
243 #error Unrecognized value in TARGET_CPU_DEFAULT.
244 #endif
246 #ifdef SPARC_BI_ARCH
248 #define CPP_CPU_DEFAULT_SPEC \
249 (DEFAULT_ARCH32_P ? "\
250 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \
251 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \
252 " : "\
253 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \
254 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \
256 #define ASM_CPU_DEFAULT_SPEC \
257 (DEFAULT_ARCH32_P ? "\
258 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \
259 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \
260 " : "\
261 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \
262 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \
265 #else /* !SPARC_BI_ARCH */
267 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
268 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
270 #endif /* !SPARC_BI_ARCH */
272 /* Define macros to distinguish architectures. */
274 /* Common CPP definitions used by CPP_SPEC amongst the various targets
275 for handling -mcpu=xxx switches. */
276 #define CPP_CPU_SPEC "\
277 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
278 %{mcpu=sparclite:-D__sparclite__} \
279 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
280 %{mcpu=sparclite86x:-D__sparclite86x__} \
281 %{mcpu=v8:-D__sparc_v8__} \
282 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
283 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
284 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \
285 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
286 %{mcpu=leon5:-D__leon__ -D__sparc_v8__} \
287 %{mcpu=leon3v7:-D__leon__} \
288 %{mcpu=v9:-D__sparc_v9__} \
289 %{mcpu=ultrasparc:-D__sparc_v9__} \
290 %{mcpu=ultrasparc3:-D__sparc_v9__} \
291 %{mcpu=niagara:-D__sparc_v9__} \
292 %{mcpu=niagara2:-D__sparc_v9__} \
293 %{mcpu=niagara3:-D__sparc_v9__} \
294 %{mcpu=niagara4:-D__sparc_v9__} \
295 %{mcpu=niagara7:-D__sparc_v9__} \
296 %{mcpu=m8:-D__sparc_v9__} \
297 %{!mcpu*:%(cpp_cpu_default)} \
299 #define CPP_ARCH32_SPEC ""
300 #define CPP_ARCH64_SPEC "-D__arch64__"
302 #define CPP_ARCH_DEFAULT_SPEC \
303 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
305 #define CPP_ARCH_SPEC "\
306 %{m32:%(cpp_arch32)} \
307 %{m64:%(cpp_arch64)} \
308 %{!m32:%{!m64:%(cpp_arch_default)}} \
311 /* Macros to distinguish the endianness, window model and FP support. */
312 #define CPP_OTHER_SPEC "\
313 %{mflat:-D_FLAT} \
314 %{msoft-float:-D_SOFT_FLOAT} \
317 /* Macros to distinguish the particular subtarget. */
318 #define CPP_SUBTARGET_SPEC ""
320 #define CPP_SPEC \
321 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)"
323 /* This used to translate -dalign to -malign, but that is no good
324 because it can't turn off the usual meaning of making debugging dumps. */
326 #define CC1_SPEC ""
328 /* Override in target specific files. */
329 #define ASM_CPU_SPEC "\
330 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
331 %{mcpu=sparclite:-Asparclite} \
332 %{mcpu=sparclite86x:-Asparclite} \
333 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
334 %{mcpu=v8:-Av8} \
335 %{mcpu=supersparc:-Av8} \
336 %{mcpu=hypersparc:-Av8} \
337 %{mcpu=leon:" AS_LEON_FLAG "} \
338 %{mcpu=leon3:" AS_LEON_FLAG "} \
339 %{mcpu=leon5:" AS_LEON_FLAG "} \
340 %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \
341 %{mv8plus:-Av8plus} \
342 %{mcpu=v9:-Av9} \
343 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
344 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
345 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
346 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \
347 %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \
348 %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \
349 %{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \
350 %{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \
351 %{!mcpu*:%(asm_cpu_default)} \
354 /* Word size selection, among other things.
355 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
357 #define ASM_ARCH32_SPEC "-32"
358 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs"
359 #define ASM_ARCH_DEFAULT_SPEC \
360 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
362 #define ASM_ARCH_SPEC "\
363 %{m32:%(asm_arch32)} \
364 %{m64:%(asm_arch64)} \
365 %{!m32:%{!m64:%(asm_arch_default)}} \
368 #ifdef HAVE_AS_RELAX_OPTION
369 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}"
370 #else
371 #define ASM_RELAX_SPEC ""
372 #endif
374 /* Special flags to the Sun-4 assembler when using pipe for input. */
376 #define ASM_SPEC "\
377 %{!pg:%{!p:%{" FPIE_OR_FPIC_SPEC ":-k}}} %{keep-local-as-symbols:-L} \
378 %(asm_cpu) %(asm_relax)"
380 /* This macro defines names of additional specifications to put in the specs
381 that can be used in various specifications like CC1_SPEC. Its definition
382 is an initializer with a subgrouping for each command option.
384 Each subgrouping contains a string constant, that defines the
385 specification name, and a string constant that used by the GCC driver
386 program.
388 Do not define this macro if it does not need to do anything. */
390 #define EXTRA_SPECS \
391 { "cpp_cpu", CPP_CPU_SPEC }, \
392 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
393 { "cpp_arch32", CPP_ARCH32_SPEC }, \
394 { "cpp_arch64", CPP_ARCH64_SPEC }, \
395 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\
396 { "cpp_arch", CPP_ARCH_SPEC }, \
397 { "cpp_other", CPP_OTHER_SPEC }, \
398 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \
399 { "asm_cpu", ASM_CPU_SPEC }, \
400 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \
401 { "asm_arch32", ASM_ARCH32_SPEC }, \
402 { "asm_arch64", ASM_ARCH64_SPEC }, \
403 { "asm_relax", ASM_RELAX_SPEC }, \
404 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\
405 { "asm_arch", ASM_ARCH_SPEC }, \
406 SUBTARGET_EXTRA_SPECS
408 #define SUBTARGET_EXTRA_SPECS
410 /* Because libgcc can generate references back to libc (via .umul etc.) we have
411 to list libc again after the second libgcc. */
412 #define LINK_GCC_C_SEQUENCE_SPEC "%G %{!nolibc:%L} %G %{!nolibc:%L}"
415 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int")
416 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int")
418 /* ??? This should be 32 bits for v9 but what can we do? */
419 #define WCHAR_TYPE "short unsigned int"
420 #define WCHAR_TYPE_SIZE 16
422 /* Mask of all CPU selection flags. */
423 #define MASK_ISA \
424 (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \
425 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
427 /* Mask of all CPU feature flags. */
428 #define MASK_FEATURES \
429 (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \
430 + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \
431 + MASK_POPC + MASK_SUBXC)
433 /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */
434 #define TARGET_HARD_MUL \
435 (TARGET_SPARCLITE || TARGET_SPARCLET \
436 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
438 /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y
439 to get high 32 bits. False in 64-bit or V8+ because multiply stores
440 a 64-bit result in a register. */
441 #define TARGET_HARD_MUL32 \
442 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS)
444 /* MASK_APP_REGS must always be the default because that's what
445 FIXED_REGISTERS is set to and -ffixed- is processed before
446 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process
447 -mno-app-regs). */
448 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
450 /* Recast the cpu class to be the cpu attribute.
451 Every file includes us, but not every file includes insn-attr.h. */
452 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
454 /* Support for a compile-time default CPU, et cetera. The rules are:
455 --with-cpu is ignored if -mcpu is specified.
456 --with-tune is ignored if -mtune is specified.
457 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
458 are specified. */
459 #define OPTION_DEFAULT_SPECS \
460 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
461 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
462 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" }
464 /* target machine storage layout */
466 /* Define this if most significant bit is lowest numbered
467 in instructions that operate on numbered bit-fields. */
468 #define BITS_BIG_ENDIAN 1
470 /* Define this if most significant byte of a word is the lowest numbered. */
471 #define BYTES_BIG_ENDIAN 1
473 /* Define this if most significant word of a multiword number is the lowest
474 numbered. */
475 #define WORDS_BIG_ENDIAN 1
477 #define MAX_BITS_PER_WORD 64
479 /* Width of a word, in units (bytes). */
480 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
481 #ifdef IN_LIBGCC2
482 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
483 #else
484 #define MIN_UNITS_PER_WORD 4
485 #endif
487 /* Now define the sizes of the C data types. */
488 #define SHORT_TYPE_SIZE 16
489 #define INT_TYPE_SIZE 32
490 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
491 #define LONG_LONG_TYPE_SIZE 64
493 /* SPARC_LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
494 SPARC ABI says that it is 128-bit wide. LONG_DOUBLE_TYPE_SIZE
495 get poisoned, so add SPARC_ prefix. */
496 /* #define SPARC_LONG_DOUBLE_TYPE_SIZE 128 */
498 /* The widest floating-point format really supported by the hardware. */
499 #define WIDEST_HARDWARE_FP_SIZE 64
501 /* Width in bits of a pointer. This is the size of ptr_mode. */
502 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
504 /* This is the machine mode used for addresses. */
505 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
507 /* If we have to extend pointers (only when TARGET_ARCH64 and not
508 TARGET_PTR64), we want to do it unsigned. This macro does nothing
509 if ptr_mode and Pmode are the same. */
510 #define POINTERS_EXTEND_UNSIGNED 1
512 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
513 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
515 /* Boundary (in *bits*) on which stack pointer should be aligned. */
516 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
517 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */
518 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
520 /* Temporary hack until the FIXME above is fixed. */
521 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
523 /* ALIGN FRAMES on double word boundaries */
524 #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2)
526 /* Allocation boundary (in *bits*) for the code of a function. */
527 #define FUNCTION_BOUNDARY 32
529 /* Alignment of field after `int : 0' in a structure. */
530 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
532 /* Every structure's size must be a multiple of this. */
533 #define STRUCTURE_SIZE_BOUNDARY 8
535 /* A bit-field declared as `int' forces `int' alignment for the struct. */
536 #define PCC_BITFIELD_TYPE_MATTERS 1
538 /* No data type wants to be aligned rounder than this. */
539 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
541 /* The best alignment to use in cases where we have a choice. */
542 #define FASTEST_ALIGNMENT 64
544 /* Define this macro as an expression for the alignment of a structure
545 (given by STRUCT as a tree node) if the alignment computed in the
546 usual way is COMPUTED and the alignment explicitly specified was
547 SPECIFIED.
549 The default is to use SPECIFIED if it is larger; otherwise, use
550 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
551 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
552 (TARGET_FASTER_STRUCTS ? \
553 (RECORD_OR_UNION_TYPE_P (STRUCT) \
554 && TYPE_FIELDS (STRUCT) != 0 \
555 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
556 : MAX ((COMPUTED), (SPECIFIED))) \
557 : MAX ((COMPUTED), (SPECIFIED)))
559 /* An integer expression for the size in bits of the largest integer machine
560 mode that should actually be used. We allow pairs of registers. */
561 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode)
563 /* We need 2 words, so we can save the stack pointer and the return register
564 of the function containing a non-local goto target. */
565 #define STACK_SAVEAREA_MODE(LEVEL) \
566 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode)
568 /* Make arrays of chars word-aligned for the same reasons. */
569 #define DATA_ALIGNMENT(TYPE, ALIGN) \
570 (TREE_CODE (TYPE) == ARRAY_TYPE \
571 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
572 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
574 /* Make local arrays of chars word-aligned for the same reasons. */
575 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
577 /* Set this nonzero if move instructions will actually fail to work
578 when given unaligned data. */
579 #define STRICT_ALIGNMENT 1
581 /* Things that must be doubleword aligned cannot go in the text section,
582 because the linker fails to align the text section enough!
583 Put them in the data section. This macro is only used in this file. */
584 #define MAX_TEXT_ALIGN 32
586 /* Standard register usage. */
588 /* Number of actual hardware registers.
589 The hardware registers are assigned numbers for the compiler
590 from 0 to just below FIRST_PSEUDO_REGISTER.
591 All registers that the compiler knows about must be given numbers,
592 even those that are not normally considered general registers.
594 SPARC has 32 integer registers and 32 floating point registers.
595 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
596 accessible. We still account for them to simplify register computations
597 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
598 32+32+32+4 == 100.
599 Register 100 is used as the integer condition code register.
600 Register 101 is used as the soft frame pointer register.
601 Register 102 is used as the general status register by VIS instructions. */
603 #define FIRST_PSEUDO_REGISTER 103
605 #define SPARC_FIRST_INT_REG 0
606 #define SPARC_LAST_INT_REG 31
607 #define SPARC_FIRST_FP_REG 32
608 /* Additional V9 fp regs. */
609 #define SPARC_FIRST_V9_FP_REG 64
610 #define SPARC_LAST_V9_FP_REG 95
611 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
612 #define SPARC_FIRST_V9_FCC_REG 96
613 #define SPARC_LAST_V9_FCC_REG 99
614 /* V8 fcc reg. */
615 #define SPARC_FCC_REG 96
616 /* Integer CC reg. We don't distinguish %icc from %xcc. */
617 #define SPARC_ICC_REG 100
618 #define SPARC_GSR_REG 102
620 /* Nonzero if REGNO is an fp reg. */
621 #define SPARC_FP_REG_P(REGNO) \
622 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
624 /* Nonzero if REGNO is an int reg. */
625 #define SPARC_INT_REG_P(REGNO) \
626 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG)
628 /* Argument passing regs. */
629 #define SPARC_OUTGOING_INT_ARG_FIRST 8
630 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
631 #define SPARC_FP_ARG_FIRST 32
633 /* 1 for registers that have pervasive standard uses
634 and are not available for the register allocator.
636 On non-v9 systems:
637 g1 is free to use as temporary.
638 g2-g4 are reserved for applications. Gcc normally uses them as
639 temporaries, but this can be disabled via the -mno-app-regs option.
640 g5 through g7 are reserved for the operating system.
642 On v9 systems:
643 g1,g5 are free to use as temporaries, and are free to use between calls
644 if the call is to an external function via the PLT.
645 g4 is free to use as a temporary in the non-embedded case.
646 g4 is reserved in the embedded case.
647 g2-g3 are reserved for applications. Gcc normally uses them as
648 temporaries, but this can be disabled via the -mno-app-regs option.
649 g6-g7 are reserved for the operating system (or application in
650 embedded case).
651 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
652 currently be a fixed register until this pattern is rewritten.
653 Register 1 is also used when restoring call-preserved registers in large
654 stack frames.
656 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
657 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
660 #define FIXED_REGISTERS \
661 {1, 0, 2, 2, 2, 2, 1, 1, \
662 0, 0, 0, 0, 0, 0, 1, 0, \
663 0, 0, 0, 0, 0, 0, 0, 0, \
664 0, 0, 0, 0, 0, 0, 0, 1, \
666 0, 0, 0, 0, 0, 0, 0, 0, \
667 0, 0, 0, 0, 0, 0, 0, 0, \
668 0, 0, 0, 0, 0, 0, 0, 0, \
669 0, 0, 0, 0, 0, 0, 0, 0, \
671 0, 0, 0, 0, 0, 0, 0, 0, \
672 0, 0, 0, 0, 0, 0, 0, 0, \
673 0, 0, 0, 0, 0, 0, 0, 0, \
674 0, 0, 0, 0, 0, 0, 0, 0, \
676 0, 0, 0, 0, 1, 1, 1}
678 /* 1 for registers not available across function calls.
679 Unlike the above, this need not include the FIXED_REGISTERS, but any
680 registers that can be used without being saved.
681 The latter must include the registers where values are returned
682 and the register where structure-value addresses are passed.
683 Aside from that, you can include as many other registers as you like. */
685 #define CALL_REALLY_USED_REGISTERS \
686 {1, 1, 1, 1, 1, 1, 1, 1, \
687 1, 1, 1, 1, 1, 1, 1, 1, \
688 0, 0, 0, 0, 0, 0, 0, 0, \
689 0, 0, 0, 0, 0, 0, 0, 0, \
691 1, 1, 1, 1, 1, 1, 1, 1, \
692 1, 1, 1, 1, 1, 1, 1, 1, \
693 1, 1, 1, 1, 1, 1, 1, 1, \
694 1, 1, 1, 1, 1, 1, 1, 1, \
696 1, 1, 1, 1, 1, 1, 1, 1, \
697 1, 1, 1, 1, 1, 1, 1, 1, \
698 1, 1, 1, 1, 1, 1, 1, 1, \
699 1, 1, 1, 1, 1, 1, 1, 1, \
701 1, 1, 1, 1, 1, 1, 1}
703 /* Due to the ARCH64 discrepancy above we must override this next
704 macro too. */
705 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE)
707 /* Value is 1 if it is OK to rename a hard register FROM to another hard
708 register TO. We cannot rename %g1 as it may be used before the save
709 register window instruction in the prologue. */
710 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
712 /* Select a register mode required for caller save of hard regno REGNO.
713 Contrary to what is documented, the default is not the smallest suitable
714 mode but the largest suitable mode for the given (REGNO, NREGS) pair and
715 it quickly creates paradoxical subregs that can be problematic. */
716 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
717 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE))
719 /* Specify the registers used for certain standard purposes.
720 The values of these macros are register numbers. */
722 /* Register to use for pushing function arguments. */
723 #define STACK_POINTER_REGNUM 14
725 /* The stack bias (amount by which the hardware register is offset by). */
726 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
728 /* Actual top-of-stack address is 92/176 greater than the contents of the
729 stack pointer register for !v9/v9. That is:
730 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
731 address, and 6*4 bytes for the 6 register parameters.
732 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
733 parameter regs. */
734 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
736 /* Unbias the stack pointer if needed, and move past the register save area,
737 that is never in use while a function is active, so that it is regarded as a
738 callee save area rather than as part of the function's own stack area. This
739 enables __strub_leave() to do a better job of clearing the stack frame of a
740 previously-called sibling. */
741 #define STACK_ADDRESS_OFFSET STACK_POINTER_OFFSET
743 /* Base register for access to local variables of the function. */
744 #define HARD_FRAME_POINTER_REGNUM 30
746 /* The soft frame pointer does not have the stack bias applied. */
747 #define FRAME_POINTER_REGNUM 101
749 #define INIT_EXPANDERS \
750 do { \
751 if (crtl->emit.regno_pointer_align) \
753 /* The biased stack pointer is only aligned on BITS_PER_UNIT. */\
754 if (SPARC_STACK_BIAS) \
756 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) \
757 = BITS_PER_UNIT; \
758 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) \
759 = BITS_PER_UNIT; \
762 /* In 32-bit mode, not everything is double-word aligned. */ \
763 if (TARGET_ARCH32) \
765 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) \
766 = BITS_PER_WORD; \
767 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) \
768 = BITS_PER_WORD; \
769 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) \
770 = BITS_PER_WORD; \
773 } while (0)
775 /* Base register for access to arguments of the function. */
776 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
778 /* Register in which static-chain is passed to a function. This must
779 not be a register used by the prologue. */
780 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
782 /* Register which holds the global offset table, if any. */
783 #define GLOBAL_OFFSET_TABLE_REGNUM 23
785 /* Register which holds offset table for position-independent data references.
786 The original SPARC ABI imposes no requirement on the choice of the register
787 so we use a pseudo-register to make sure it is properly saved and restored
788 around calls to setjmp. Now the ABI of VxWorks RTP makes it live on entry
789 to PLT entries so we use the canonical GOT register in this case. */
790 #define PIC_OFFSET_TABLE_REGNUM \
791 (TARGET_VXWORKS_RTP && flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
793 /* Pick a default value we can notice from override_options:
794 !v9: Default is on.
795 v9: Default is off.
796 Originally it was -1, but later on the container of options changed to
797 unsigned byte, so we decided to pick 127 as default value, which does
798 reflect an undefined default value in case of 0/1. */
799 #define DEFAULT_PCC_STRUCT_RETURN 127
801 /* Functions which return large structures get the address
802 to place the wanted value at offset 64 from the frame.
803 Must reserve 64 bytes for the in and local registers.
804 v9: Functions which return large structures get the address to place the
805 wanted value from an invisible first argument. */
806 #define STRUCT_VALUE_OFFSET 64
808 /* Define the classes of registers for register constraints in the
809 machine description. Also define ranges of constants.
811 One of the classes must always be named ALL_REGS and include all hard regs.
812 If there is more than one class, another class must be named NO_REGS
813 and contain no registers.
815 The name GENERAL_REGS must be the name of a class (or an alias for
816 another name such as ALL_REGS). This is the class of registers
817 that is allowed by "g" or "r" in a register constraint.
818 Also, registers outside this class are allocated only when
819 instructions express preferences for them.
821 The classes must be numbered in nondecreasing order; that is,
822 a larger-numbered class must never be contained completely
823 in a smaller-numbered class.
825 For any two classes, it is very desirable that there be another
826 class that represents their union. */
828 /* The SPARC has various kinds of registers: general, floating point,
829 and condition codes [well, it has others as well, but none that we
830 care directly about].
832 For v9 we must distinguish between the upper and lower floating point
833 registers because the upper ones can't hold SFmode values.
834 TARGET_HARD_REGNO_MODE_OK won't help here because reload assumes that
835 register(s) satisfying a group need for a class will also satisfy a
836 single need for that class. EXTRA_FP_REGS is a bit of a misnomer as
837 it covers all 64 fp regs.
839 It is important that one class contains all the general and all the standard
840 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
841 because reg_class_record() will bias the selection in favor of fp regs,
842 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
843 because FP_REGS > GENERAL_REGS.
845 It is also important that one class contain all the general and all
846 the fp regs. Otherwise when spilling a DFmode reg, it may be from
847 EXTRA_FP_REGS but find_reloads() may use class
848 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
849 because the compiler thinks it doesn't have a spill reg when in
850 fact it does.
852 v9 also has 4 floating point condition code registers. Since we don't
853 have a class that is the union of FPCC_REGS with either of the others,
854 it is important that it appear first. Otherwise the compiler will die
855 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
856 constraints. */
858 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS,
859 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS,
860 ALL_REGS, LIM_REG_CLASSES };
862 #define N_REG_CLASSES (int) LIM_REG_CLASSES
864 /* Give names of register classes as strings for dump file. */
866 #define REG_CLASS_NAMES \
867 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \
868 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \
869 "ALL_REGS" }
871 /* Define which registers fit in which classes.
872 This is an initializer for a vector of HARD_REG_SET
873 of length N_REG_CLASSES. */
875 #define REG_CLASS_CONTENTS \
876 {{0, 0, 0, 0}, /* NO_REGS */ \
877 {0, 0, 0, 0xf}, /* FPCC_REGS */ \
878 {0xffff, 0, 0, 0}, /* I64_REGS */ \
879 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \
880 {0, -1, 0, 0}, /* FP_REGS */ \
881 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \
882 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \
883 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \
884 {-1, -1, -1, 0x7f}} /* ALL_REGS */
886 /* The same information, inverted:
887 Return the class number of the smallest class containing
888 reg number REGNO. This could be a conditional expression
889 or could index an array. */
891 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
893 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
895 /* This is the order in which to allocate registers normally.
897 We put %f0-%f7 last among the float registers, so as to make it more
898 likely that a pseudo-register which dies in the float return register
899 area will get allocated to the float return register, thus saving a move
900 instruction at the end of the function.
902 Similarly for integer return value registers.
904 We know in this case that we will not end up with a leaf function.
906 The register allocator is given the global and out registers first
907 because these registers are call clobbered and thus less useful to
908 global register allocation.
910 Next we list the local and in registers. They are not call clobbered
911 and thus very useful for global register allocation. We list the input
912 registers before the locals so that it is more likely the incoming
913 arguments received in those registers can just stay there and not be
914 reloaded. */
916 #define REG_ALLOC_ORDER \
917 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
918 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
919 15, /* %o7 */ \
920 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
921 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\
922 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
923 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
924 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
925 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
926 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
927 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
928 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
929 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
930 96, 97, 98, 99, /* %fcc0-3 */ \
931 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */
933 /* This is the order in which to allocate registers for
934 leaf functions. If all registers can fit in the global and
935 output registers, then we have the possibility of having a leaf
936 function.
938 The macro actually mentioned the input registers first,
939 because they get renumbered into the output registers once
940 we know really do have a leaf function.
942 To be more precise, this register allocation order is used
943 when %o7 is found to not be clobbered right before register
944 allocation. Normally, the reason %o7 would be clobbered is
945 due to a call which could not be transformed into a sibling
946 call.
948 As a consequence, it is possible to use the leaf register
949 allocation order and not end up with a leaf function. We will
950 not get suboptimal register allocation in that case because by
951 definition of being potentially leaf, there were no function
952 calls. Therefore, allocation order within the local register
953 window is not critical like it is when we do have function calls. */
955 #define REG_LEAF_ALLOC_ORDER \
956 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \
957 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \
958 15, /* %o7 */ \
959 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \
960 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \
961 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
962 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
963 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
964 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
965 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
966 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
967 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
968 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \
969 96, 97, 98, 99, /* %fcc0-3 */ \
970 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */
972 #define ADJUST_REG_ALLOC_ORDER sparc_order_regs_for_local_alloc ()
974 extern char sparc_leaf_regs[];
975 #define LEAF_REGISTERS sparc_leaf_regs
977 #define LEAF_REG_REMAP(REGNO) sparc_leaf_reg_remap (REGNO)
979 /* The class value for index registers, and the one for base regs. */
980 #define INDEX_REG_CLASS GENERAL_REGS
981 #define BASE_REG_CLASS GENERAL_REGS
983 /* Local macro to handle the two v9 classes of FP regs. */
984 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
986 /* Predicate for 2-bit and 5-bit unsigned constants. */
987 #define SPARC_IMM2_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x3) == 0)
988 #define SPARC_IMM5_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x1F) == 0)
990 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */
991 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20)
992 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
993 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
994 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
996 /* 10- and 11-bit immediates are only used for a few specific insns.
997 SMALL_INT is used throughout the port so we continue to use it. */
998 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1000 /* Predicate for constants that can be loaded with a sethi instruction.
1001 This is the general, 64-bit aware, bitwise version that ensures that
1002 only constants whose representation fits in the mask
1004 0x00000000fffffc00
1006 are accepted. It will reject, for example, negative SImode constants
1007 on 64-bit hosts, so correct handling is to mask the value beforehand
1008 according to the mode of the instruction. */
1009 #define SPARC_SETHI_P(X) \
1010 (((unsigned HOST_WIDE_INT) (X) \
1011 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1013 /* Version of the above predicate for SImode constants and below. */
1014 #define SPARC_SETHI32_P(X) \
1015 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1017 /* Return the maximum number of consecutive registers
1018 needed to represent mode MODE in a register of class CLASS. */
1019 /* On SPARC, this is the size of MODE in words. */
1020 #define CLASS_MAX_NREGS(CLASS, MODE) \
1021 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1022 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1024 /* Stack layout; function entry, exit and calling. */
1026 /* Define this if pushing a word on the stack
1027 makes the stack pointer a smaller address. */
1028 #define STACK_GROWS_DOWNWARD 1
1030 /* Define this to nonzero if the nominal address of the stack frame
1031 is at the high-address end of the local variables;
1032 that is, each additional local variable allocated
1033 goes at a more negative offset in the frame. */
1034 #define FRAME_GROWS_DOWNWARD 1
1036 /* Offset of first parameter from the argument pointer register value.
1037 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1038 even if this function isn't going to use it.
1039 v9: This is 128 for the ins and locals. */
1040 #define FIRST_PARM_OFFSET(FNDECL) \
1041 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1043 /* Offset from the argument pointer register value to the CFA.
1044 This is different from FIRST_PARM_OFFSET because the register window
1045 comes between the CFA and the arguments. */
1046 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1048 /* When a parameter is passed in a register, stack space is still
1049 allocated for it.
1050 !v9: All 6 possible integer registers have backing store allocated.
1051 v9: Only space for the arguments passed is allocated. */
1052 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1053 meaning to the backend. Further, we need to be able to detect if a
1054 varargs/unprototyped function is called, as they may want to spill more
1055 registers than we've provided space. Ugly, ugly. So for now we retain
1056 all 6 slots even for v9. */
1057 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1059 /* Definitions for register elimination. */
1061 #define ELIMINABLE_REGS \
1062 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1063 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1065 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1066 do \
1068 (OFFSET) = sparc_initial_elimination_offset ((TO)); \
1070 while (0)
1072 /* Keep the stack pointer constant throughout the function.
1073 This is both an optimization and a necessity: longjmp
1074 doesn't behave itself when the stack pointer moves within
1075 the function! */
1076 #define ACCUMULATE_OUTGOING_ARGS 1
1078 /* Define this macro if the target machine has "register windows". This
1079 C expression returns the register number as seen by the called function
1080 corresponding to register number OUT as seen by the calling function.
1081 Return OUT if register number OUT is not an outbound register. */
1083 #define INCOMING_REGNO(OUT) \
1084 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1086 /* Define this macro if the target machine has "register windows". This
1087 C expression returns the register number as seen by the calling function
1088 corresponding to register number IN as seen by the called function.
1089 Return IN if register number IN is not an inbound register. */
1091 #define OUTGOING_REGNO(IN) \
1092 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1094 /* Define this macro if the target machine has register windows. This
1095 C expression returns true if the register is call-saved but is in the
1096 register window. */
1098 #define LOCAL_REGNO(REGNO) \
1099 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31)
1101 /* Define the size of space to allocate for the return value of an
1102 untyped_call. */
1104 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1106 /* 1 if N is a possible register number for function argument passing.
1107 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1109 #define FUNCTION_ARG_REGNO_P(N) \
1110 (((N) >= 8 && (N) <= 13) \
1111 || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63))
1113 /* Define a data type for recording info about an argument list
1114 during the scan of that argument list. This data type should
1115 hold all necessary information about the function itself
1116 and about the args processed so far, enough to enable macros
1117 such as FUNCTION_ARG to determine where the next arg should go.
1119 On SPARC (!v9), this is a single integer, which is a number of words
1120 of arguments scanned so far (including the invisible argument,
1121 if any, which holds the structure-value-address).
1122 Thus 7 or more means all following args should go on the stack.
1124 For v9, we also need to know whether a prototype is present. */
1126 struct sparc_args {
1127 int words; /* number of words passed so far */
1128 int prototype_p; /* nonzero if a prototype is present */
1129 int libcall_p; /* nonzero if a library call */
1131 #define CUMULATIVE_ARGS struct sparc_args
1133 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1134 for a call to a function whose data type is FNTYPE.
1135 For a library call, FNTYPE is 0. */
1137 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1138 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1141 /* Generate the special assembly code needed to tell the assembler whatever
1142 it might need to know about the return value of a function.
1144 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1145 information to the assembler relating to peephole optimization (done in
1146 the assembler). */
1148 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1149 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT)))
1151 /* Output the special assembly code needed to tell the assembler some
1152 register is used as global register variable.
1154 SPARC 64bit psABI declares registers %g2 and %g3 as application
1155 registers and %g6 and %g7 as OS registers. Any object using them
1156 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1157 and how they are used (scratch or some global variable).
1158 Linker will then refuse to link together objects which use those
1159 registers incompatibly.
1161 Unless the registers are used for scratch, two different global
1162 registers cannot be declared to the same name, so in the unlikely
1163 case of a global register variable occupying more than one register
1164 we prefix the second and following registers with .gnu.part1. etc. */
1166 extern GTY(()) char sparc_hard_reg_printed[8];
1168 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1169 do { \
1170 if (TARGET_ARCH64) \
1172 int end = end_hard_regno (DECL_MODE (decl), REGNO); \
1173 int reg; \
1174 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1175 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1177 if (reg == (REGNO)) \
1178 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \
1179 else \
1180 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \
1181 reg, reg - (REGNO), (NAME)); \
1182 sparc_hard_reg_printed[reg] = 1; \
1185 } while (0)
1187 /* Emit rtl for profiling. */
1188 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1190 /* All the work done in PROFILE_HOOK, but still required. */
1191 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1193 /* Set the name of the mcount function for the system. */
1194 #define MCOUNT_FUNCTION "*mcount"
1196 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1197 the stack pointer does not matter. The value is tested only in
1198 functions that have frame pointers. */
1199 #define EXIT_IGNORE_STACK 1
1201 /* Length in units of the trampoline for entering a nested function. */
1202 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1204 /* Alignment required for trampolines, in bits. */
1205 #define TRAMPOLINE_ALIGNMENT 128
1207 /* Generate RTL to flush the register windows so as to make arbitrary frames
1208 available. */
1209 #define SETUP_FRAME_ADDRESSES() \
1210 do { \
1211 if (!TARGET_FLAT) \
1212 emit_insn (gen_flush_register_windows ());\
1213 } while (0)
1215 /* Given an rtx for the address of a frame,
1216 return an rtx for the address of the word in the frame
1217 that holds the dynamic chain--the previous frame's address. */
1218 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1219 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1221 /* Given an rtx for the frame pointer,
1222 return an rtx for the address of the frame. */
1223 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS)
1225 /* The return address isn't on the stack, it is in a register, so we can't
1226 access it from the current frame pointer. We can access it from the
1227 previous frame pointer though by reading a value from the register window
1228 save area. */
1229 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1
1231 /* This is the offset of the return address to the true next instruction to be
1232 executed for the current function. */
1233 #define RETURN_ADDR_OFFSET \
1234 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
1236 /* The current return address is in %i7. The return address of anything
1237 farther back is in the register window save area at [%fp+60]. */
1238 /* ??? This ignores the fact that the actual return address is +8 for normal
1239 returns, and +12 for structure returns. */
1240 #define RETURN_ADDR_REGNUM 31
1241 #define RETURN_ADDR_RTX(count, frame) \
1242 ((count == -1) \
1243 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \
1244 : gen_rtx_MEM (Pmode, \
1245 memory_address (Pmode, plus_constant (Pmode, frame, \
1246 15 * UNITS_PER_WORD \
1247 + SPARC_STACK_BIAS))))
1249 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1250 +12, but always using +8 is close enough for frame unwind purposes.
1251 Actually, just using %o7 is close enough for unwinding, but %o7+8
1252 is something you can return to. */
1253 #define INCOMING_RETURN_ADDR_REGNUM 15
1254 #define INCOMING_RETURN_ADDR_RTX \
1255 plus_constant (word_mode, \
1256 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8)
1257 #define DWARF_FRAME_RETURN_COLUMN \
1258 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM)
1260 /* The offset from the incoming value of %sp to the top of the stack frame
1261 for the current function. On sparc64, we have to account for the stack
1262 bias if present. */
1263 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1265 /* Describe how we implement __builtin_eh_return. */
1266 #define EH_RETURN_REGNUM 1
1267 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1268 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM)
1270 /* Define registers used by the epilogue and return instruction. */
1271 #define EPILOGUE_USES(REGNO) \
1272 ((REGNO) == RETURN_ADDR_REGNUM \
1273 || (TARGET_FLAT \
1274 && epilogue_completed \
1275 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \
1276 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM))
1278 /* Select a format to encode pointers in exception handling data. CODE
1279 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1280 true if the symbol may be affected by dynamic relocations.
1282 If assembler and linker properly support .uaword %r_disp32(foo),
1283 then use PC relative 32-bit relocations instead of absolute relocs
1284 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1285 for binaries, to save memory.
1287 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1288 symbol %r_disp32() is against was not local, but .hidden. In that
1289 case, we have to use DW_EH_PE_absptr for pic personality. */
1290 #ifdef HAVE_AS_SPARC_UA_PCREL
1291 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1292 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1293 (flag_pic \
1294 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1295 : ((TARGET_ARCH64 && ! GLOBAL) \
1296 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1297 : DW_EH_PE_absptr))
1298 #else
1299 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1300 (flag_pic \
1301 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1302 : ((TARGET_ARCH64 && ! GLOBAL) \
1303 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1304 : DW_EH_PE_absptr))
1305 #endif
1307 /* Emit a PC-relative relocation. */
1308 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1309 do { \
1310 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1311 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \
1312 assemble_name (FILE, LABEL); \
1313 fputc (')', FILE); \
1314 } while (0)
1315 #endif
1317 /* Addressing modes, and classification of registers for them. */
1319 /* Macros to check register numbers against specific register classes. */
1321 /* These assume that REGNO is a hard or pseudo reg number.
1322 They give nonzero only if REGNO is a hard reg of the suitable class
1323 or a pseudo reg currently allocated to a suitable hard reg.
1324 Since they use reg_renumber, they are safe only once reg_renumber
1325 has been allocated, which happens in reginfo.cc during register
1326 allocation. */
1328 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1329 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \
1330 || (REGNO) == FRAME_POINTER_REGNUM \
1331 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1333 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1335 #define REGNO_OK_FOR_FP_P(REGNO) \
1336 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1337 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1339 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1340 (TARGET_V9 \
1341 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1342 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1344 /* Maximum number of registers that can appear in a valid memory address. */
1346 #define MAX_REGS_PER_ADDRESS 2
1348 /* Recognize any constant value that is a valid address.
1349 When PIC, we do not accept an address that would require a scratch reg
1350 to load into a register. */
1352 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1354 /* Define this, so that when PIC, reload won't try to reload invalid
1355 addresses which require two reload registers. */
1357 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1359 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1361 #ifdef HAVE_AS_OFFSETABLE_LO10
1362 #define USE_AS_OFFSETABLE_LO10 1
1363 #else
1364 #define USE_AS_OFFSETABLE_LO10 0
1365 #endif
1367 /* Try a machine-dependent way of reloading an illegitimate address
1368 operand. If we find one, push the reload and jump to WIN. This
1369 macro is used in only one place: `find_reloads_address' in reload.cc. */
1370 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1371 do { \
1372 int win; \
1373 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \
1374 (int)(TYPE), (IND_LEVELS), &win); \
1375 if (win) \
1376 goto WIN; \
1377 } while (0)
1379 /* Specify the machine mode that this machine uses
1380 for the index in the tablejump instruction. */
1381 /* If we ever implement any of the full models (such as CM_FULLANY),
1382 this has to be DImode in that case */
1383 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1384 #define CASE_VECTOR_MODE \
1385 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
1386 #else
1387 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
1388 we have to sign extend which slows things down. */
1389 #define CASE_VECTOR_MODE \
1390 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
1391 #endif
1393 /* Define this as 1 if `char' should by default be signed; else as 0. */
1394 #define DEFAULT_SIGNED_CHAR 1
1396 /* Max number of bytes we can move from memory to memory
1397 in one reasonably fast instruction. */
1398 #define MOVE_MAX 8
1400 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1401 move-instruction pairs, we will do a cpymem or libcall instead. */
1403 #define MOVE_RATIO(speed) ((speed) ? 8 : 3)
1405 /* Define if operations between registers always perform the operation
1406 on the full register even if a narrower mode is specified. */
1407 #define WORD_REGISTER_OPERATIONS 1
1409 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1410 will either zero-extend or sign-extend. The value of this macro should
1411 be the code that says which one of the two operations is implicitly
1412 done, UNKNOWN if none. */
1413 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1415 /* Nonzero if access to memory by bytes is slow and undesirable.
1416 For RISC chips, it means that access to memory by bytes is no
1417 better than access by words when possible, so grab a whole word
1418 and maybe make use of that. */
1419 #define SLOW_BYTE_ACCESS 1
1421 /* Define this to be nonzero if shift instructions ignore all but the low-order
1422 few bits. */
1423 #define SHIFT_COUNT_TRUNCATED 1
1425 /* For SImode, we make sure the top 32-bits of the register are clear and
1426 then we subtract 32 from the lzd instruction result. */
1427 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1428 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
1430 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1431 return the mode to be used for the comparison. For floating-point,
1432 CCFP[E]mode is used. CCNZmode should be used when the first operand
1433 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1434 processing is needed. */
1435 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
1437 /* Return nonzero if MODE implies a floating point inequality can be
1438 reversed. For SPARC this is always true because we have a full
1439 compliment of ordered and unordered comparisons, but until generic
1440 code knows how to reverse it correctly we keep the old definition. */
1441 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
1443 /* A function address in a call instruction for indexing purposes. */
1444 #define FUNCTION_MODE Pmode
1446 /* Define this if addresses of constant functions
1447 shouldn't be put through pseudo regs where they can be cse'd.
1448 Desirable on machines where ordinary constants are expensive
1449 but a CALL with constant address is cheap. */
1450 #define NO_FUNCTION_CSE 1
1452 /* The _Q_* comparison libcalls return booleans. */
1453 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
1455 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
1456 that the inputs are fully consumed before the output memory is clobbered. */
1458 #define TARGET_BUGGY_QP_LIB 0
1460 /* Assume by default that we do not have the Solaris-specific conversion
1461 routines nor 64-bit integer multiply and divide routines. */
1463 #define SUN_CONVERSION_LIBFUNCS 0
1464 #define DITF_CONVERSION_LIBFUNCS 0
1465 #define SUN_INTEGER_MULTIPLY_64 0
1467 /* A C expression for the cost of a branch instruction. A value of 1
1468 is the default; other values are interpreted relative to that. */
1469 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
1470 (sparc_branch_cost (SPEED_P, PREDICTABLE_P))
1472 /* Control the assembler format that we output. */
1474 /* A C string constant describing how to begin a comment in the target
1475 assembler language. The compiler assumes that the comment will end at
1476 the end of the line. */
1478 #define ASM_COMMENT_START "!"
1480 /* Output to assembler file text saying following lines
1481 may contain character constants, extra white space, comments, etc. */
1483 #define ASM_APP_ON ""
1485 /* Output to assembler file text saying following lines
1486 no longer contain unusual constructs. */
1488 #define ASM_APP_OFF ""
1490 /* How to refer to registers in assembler output.
1491 This sequence is indexed by compiler's hard-register-number (see above). */
1493 #define REGISTER_NAMES \
1494 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1495 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1496 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1497 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1498 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1499 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1500 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1501 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
1502 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
1503 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
1504 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
1505 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
1506 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" }
1508 /* Define additional names for use in asm clobbers and asm declarations. */
1510 #define ADDITIONAL_REGISTER_NAMES \
1511 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}}
1513 /* This is how to output a command to make the user-level label named NAME
1514 defined for reference from other files. */
1516 /* Globalizing directive for a label. */
1517 #define GLOBAL_ASM_OP "\t.global "
1519 /* The prefix to add to user-visible assembler symbols. */
1521 #define USER_LABEL_PREFIX "_"
1523 /* This is how to store into the string LABEL
1524 the symbol_ref name of an internal numbered label where
1525 PREFIX is the class of label and NUM is the number within the class.
1526 This is suitable for output with `assemble_name'. */
1528 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1529 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM))
1531 /* This is how we hook in and defer the case-vector until the end of
1532 the function. */
1533 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
1534 sparc_defer_case_vector ((LAB),(VEC), 0)
1536 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
1537 sparc_defer_case_vector ((LAB),(VEC), 1)
1539 /* This is how to output an element of a case-vector that is absolute. */
1541 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1542 do { \
1543 char label[30]; \
1544 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1545 if (CASE_VECTOR_MODE == SImode) \
1546 fprintf (FILE, "\t.word\t"); \
1547 else \
1548 fprintf (FILE, "\t.xword\t"); \
1549 assemble_name (FILE, label); \
1550 fputc ('\n', FILE); \
1551 } while (0)
1553 /* This is how to output an element of a case-vector that is relative.
1554 (SPARC uses such vectors only when generating PIC.) */
1556 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1557 do { \
1558 char label[30]; \
1559 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \
1560 if (CASE_VECTOR_MODE == SImode) \
1561 fprintf (FILE, "\t.word\t"); \
1562 else \
1563 fprintf (FILE, "\t.xword\t"); \
1564 assemble_name (FILE, label); \
1565 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \
1566 fputc ('-', FILE); \
1567 assemble_name (FILE, label); \
1568 fputc ('\n', FILE); \
1569 } while (0)
1571 /* This is what to output before and after case-vector (both
1572 relative and absolute). If .subsection -1 works, we put case-vectors
1573 at the beginning of the current section. */
1575 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1577 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
1578 fprintf(FILE, "\t.subsection\t-1\n")
1580 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
1581 fprintf(FILE, "\t.previous\n")
1583 #endif
1585 /* This is how to output an assembler line
1586 that says to advance the location counter
1587 to a multiple of 2**LOG bytes. */
1589 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1590 if ((LOG) != 0) \
1591 fprintf (FILE, "\t.align %d\n", (1 << (LOG)))
1593 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1594 fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
1596 /* This says how to output an assembler line
1597 to define a global common symbol. */
1599 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1600 ( fputs ("\t.common ", (FILE)), \
1601 assemble_name ((FILE), (NAME)), \
1602 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE)))
1604 /* This says how to output an assembler line to define a local common
1605 symbol. */
1607 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1608 ( fputs ("\t.reserve ", (FILE)), \
1609 assemble_name ((FILE), (NAME)), \
1610 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \
1611 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
1613 /* A C statement (sans semicolon) to output to the stdio stream
1614 FILE the assembler definition of uninitialized global DECL named
1615 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
1616 Try to use asm_output_aligned_bss to implement this macro. */
1618 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1619 do { \
1620 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
1621 } while (0)
1623 /* Output #ident as a .ident. */
1625 #undef TARGET_ASM_OUTPUT_IDENT
1626 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
1628 /* Prettify the assembly. */
1630 extern int sparc_indent_opcode;
1632 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
1633 do { \
1634 if (sparc_indent_opcode) \
1636 putc (' ', FILE); \
1637 sparc_indent_opcode = 0; \
1639 } while (0)
1641 /* TLS support defaulting to original Sun flavor. GNU extensions
1642 must be activated in separate configuration files. */
1643 #ifdef HAVE_AS_TLS
1644 #define TARGET_TLS 1
1645 #else
1646 #define TARGET_TLS 0
1647 #endif
1649 #define TARGET_SUN_TLS TARGET_TLS
1650 #define TARGET_GNU_TLS 0
1652 #ifdef HAVE_AS_FMAF_HPC_VIS3
1653 #define AS_NIAGARA3_FLAG "d"
1654 #else
1655 #define AS_NIAGARA3_FLAG "b"
1656 #endif
1658 #ifdef HAVE_AS_SPARC4
1659 #define AS_NIAGARA4_FLAG "-xarch=sparc4"
1660 #else
1661 #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG
1662 #endif
1664 #ifdef HAVE_AS_SPARC5_VIS4
1665 #define AS_NIAGARA7_FLAG "-xarch=sparc5"
1666 #else
1667 #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG
1668 #endif
1670 #ifdef HAVE_AS_SPARC6
1671 #define AS_M8_FLAG "-xarch=sparc6"
1672 #else
1673 #define AS_M8_FLAG AS_NIAGARA7_FLAG
1674 #endif
1676 #ifdef HAVE_AS_LEON
1677 #define AS_LEON_FLAG "-Aleon"
1678 #define AS_LEONV7_FLAG "-Aleon"
1679 #else
1680 #define AS_LEON_FLAG "-Av8"
1681 #define AS_LEONV7_FLAG "-Av7"
1682 #endif
1684 /* We use gcc _mcount for profiling. */
1685 #define NO_PROFILE_COUNTERS 0
1687 /* Debug support */
1688 #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */
1689 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS
1691 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS)
1693 /* By default, use the weakest memory model for the cpu. */
1694 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL
1695 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT
1696 #endif
1698 /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */
1699 #define SPARC_LOW_FE_EXCEPT_VALUES 0
1701 #define TARGET_SUPPORTS_WIDE_INT 1
1703 /* Define this to 1 to accept ABI changes to match the vendor compiler. */
1704 #define SUN_V9_ABI_COMPATIBILITY 0