| blob | 508603cf6c8c8b6f480d8dfcc1879ba78776b181 |
1 ;; Unspec defintions.
2 ;; Copyright (C) 2012-2013 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; UNSPEC Usage:
22 ;; Note: sin and cos are no-longer used.
23 ;; Unspec enumerators for Neon are defined in neon.md.
24 ;; Unspec enumerators for iwmmxt2 are defined in iwmmxt2.md
26 (define_c_enum "unspec" [
27 UNSPEC_PUSH_MULT ; `push multiple' operation:
28 ; operand 0 is the first register,
29 ; subsequent registers are in parallel (use ...)
30 ; expressions.
31 UNSPEC_PIC_SYM ; A symbol that has been treated properly for pic
32 ; usage, that is, we will add the pic_register
33 ; value to it before trying to dereference it.
34 UNSPEC_PIC_BASE ; Add PC and all but the last operand together,
35 ; The last operand is the number of a PIC_LABEL
36 ; that points at the containing instruction.
37 UNSPEC_PRLG_STK ; A special barrier that prevents frame accesses
38 ; being scheduled before the stack adjustment insn.
39 UNSPEC_REGISTER_USE ; As USE insns are not meaningful after reload,
40 ; this unspec is used to prevent the deletion of
41 ; instructions setting registers for EH handling
42 ; and stack frame generation. Operand 0 is the
43 ; register to "use".
44 UNSPEC_CHECK_ARCH ; Set CCs to indicate 26-bit or 32-bit mode.
45 UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
46 UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction.
47 UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
48 UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction.
49 UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
50 UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction.
51 UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction.
52 UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
53 UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
54 UNSPEC_CLRDI ; Used by the intrinsic form of the iWMMXt CLRDI instruction.
55 UNSPEC_WALIGNI ; Used by the intrinsic form of the iWMMXt WALIGN instruction.
56 UNSPEC_TLS ; A symbol that has been treated properly for TLS usage.
57 UNSPEC_PIC_LABEL ; A label used for PIC access that does not appear in the
58 ; instruction stream.
59 UNSPEC_PIC_OFFSET ; A symbolic 12-bit OFFSET that has been treated
60 ; correctly for PIC usage.
61 UNSPEC_GOTSYM_OFF ; The offset of the start of the GOT from a
62 ; a given symbolic address.
63 UNSPEC_THUMB1_CASESI ; A Thumb1 compressed dispatch-table call.
64 UNSPEC_RBIT ; rbit operation.
65 UNSPEC_SYMBOL_OFFSET ; The offset of the start of the symbol from
66 ; another symbolic address.
67 UNSPEC_MEMORY_BARRIER ; Represent a memory barrier.
68 UNSPEC_UNALIGNED_LOAD ; Used to represent ldr/ldrh instructions that access
69 ; unaligned locations, on architectures which support
70 ; that.
71 UNSPEC_UNALIGNED_STORE ; Same for str/strh.
72 UNSPEC_PIC_UNIFIED ; Create a common pic addressing form.
73 UNSPEC_LL ; Represent an unpaired load-register-exclusive.
74 UNSPEC_VRINTZ ; Represent a float to integral float rounding
75 ; towards zero.
76 UNSPEC_VRINTP ; Represent a float to integral float rounding
77 ; towards +Inf.
78 UNSPEC_VRINTM ; Represent a float to integral float rounding
79 ; towards -Inf.
80 UNSPEC_VRINTR ; Represent a float to integral float rounding
81 ; FPSCR rounding mode.
82 UNSPEC_VRINTX ; Represent a float to integral float rounding
83 ; FPSCR rounding mode and signal inexactness.
84 UNSPEC_VRINTA ; Represent a float to integral float rounding
85 ; towards nearest, ties away from zero.
86 ])
88 (define_c_enum "unspec" [
89 UNSPEC_WADDC ; Used by the intrinsic form of the iWMMXt WADDC instruction.
90 UNSPEC_WABS ; Used by the intrinsic form of the iWMMXt WABS instruction.
91 UNSPEC_WQMULWMR ; Used by the intrinsic form of the iWMMXt WQMULWMR instruction.
92 UNSPEC_WQMULMR ; Used by the intrinsic form of the iWMMXt WQMULMR instruction.
93 UNSPEC_WQMULWM ; Used by the intrinsic form of the iWMMXt WQMULWM instruction.
94 UNSPEC_WQMULM ; Used by the intrinsic form of the iWMMXt WQMULM instruction.
95 UNSPEC_WQMIAxyn ; Used by the intrinsic form of the iWMMXt WMIAxyn instruction.
96 UNSPEC_WQMIAxy ; Used by the intrinsic form of the iWMMXt WMIAxy instruction.
97 UNSPEC_TANDC ; Used by the intrinsic form of the iWMMXt TANDC instruction.
98 UNSPEC_TORC ; Used by the intrinsic form of the iWMMXt TORC instruction.
99 UNSPEC_TORVSC ; Used by the intrinsic form of the iWMMXt TORVSC instruction.
100 UNSPEC_TEXTRC ; Used by the intrinsic form of the iWMMXt TEXTRC instruction.
101 ])
104 ;; UNSPEC_VOLATILE Usage:
106 (define_c_enum "unspecv" [
107 VUNSPEC_BLOCKAGE ; `blockage' insn to prevent scheduling across an
108 ; insn in the code.
109 VUNSPEC_EPILOGUE ; `epilogue' insn, used to represent any part of the
110 ; instruction epilogue sequence that isn't expanded
111 ; into normal RTL. Used for both normal and sibcall
112 ; epilogues.
113 VUNSPEC_THUMB1_INTERWORK ; `prologue_thumb1_interwork' insn, used to swap
114 ; modes from arm to thumb.
115 VUNSPEC_ALIGN ; `align' insn. Used at the head of a minipool table
116 ; for inlined constants.
117 VUNSPEC_POOL_END ; `end-of-table'. Used to mark the end of a minipool
118 ; table.
119 VUNSPEC_POOL_1 ; `pool-entry(1)'. An entry in the constant pool for
120 ; an 8-bit object.
121 VUNSPEC_POOL_2 ; `pool-entry(2)'. An entry in the constant pool for
122 ; a 16-bit object.
123 VUNSPEC_POOL_4 ; `pool-entry(4)'. An entry in the constant pool for
124 ; a 32-bit object.
125 VUNSPEC_POOL_8 ; `pool-entry(8)'. An entry in the constant pool for
126 ; a 64-bit object.
127 VUNSPEC_POOL_16 ; `pool-entry(16)'. An entry in the constant pool for
128 ; a 128-bit object.
129 VUNSPEC_TMRC ; Used by the iWMMXt TMRC instruction.
130 VUNSPEC_TMCR ; Used by the iWMMXt TMCR instruction.
131 VUNSPEC_ALIGN8 ; 8-byte alignment version of VUNSPEC_ALIGN
132 VUNSPEC_WCMP_EQ ; Used by the iWMMXt WCMPEQ instructions
133 VUNSPEC_WCMP_GTU ; Used by the iWMMXt WCMPGTU instructions
134 VUNSPEC_WCMP_GT ; Used by the iwMMXT WCMPGT instructions
135 VUNSPEC_EH_RETURN ; Use to override the return address for exception
136 ; handling.
137 VUNSPEC_ATOMIC_CAS ; Represent an atomic compare swap.
138 VUNSPEC_ATOMIC_XCHG ; Represent an atomic exchange.
139 VUNSPEC_ATOMIC_OP ; Represent an atomic operation.
140 VUNSPEC_LL ; Represent a load-register-exclusive.
141 VUNSPEC_SC ; Represent a store-register-exclusive.
142 VUNSPEC_LAX ; Represent a load-register-acquire-exclusive.
143 VUNSPEC_SLX ; Represent a store-register-release-exclusive.
144 VUNSPEC_LDA ; Represent a store-register-acquire.
145 VUNSPEC_STL ; Represent a store-register-release.
146 ])
148 ;; Enumerators for NEON unspecs.
149 (define_c_enum "unspec" [
150 UNSPEC_ASHIFT_SIGNED
151 UNSPEC_ASHIFT_UNSIGNED
152 UNSPEC_LOAD_COUNT
153 UNSPEC_VABD
154 UNSPEC_VABDL
155 UNSPEC_VADD
156 UNSPEC_VADDHN
157 UNSPEC_VADDL
158 UNSPEC_VADDW
159 UNSPEC_VBSL
160 UNSPEC_VCAGE
161 UNSPEC_VCAGT
162 UNSPEC_VCEQ
163 UNSPEC_VCGE
164 UNSPEC_VCGEU
165 UNSPEC_VCGT
166 UNSPEC_VCGTU
167 UNSPEC_VCLS
168 UNSPEC_VCONCAT
169 UNSPEC_VCVT
170 UNSPEC_VCVT_N
171 UNSPEC_VEXT
172 UNSPEC_VHADD
173 UNSPEC_VHSUB
174 UNSPEC_VLD1
175 UNSPEC_VLD1_LANE
176 UNSPEC_VLD2
177 UNSPEC_VLD2_DUP
178 UNSPEC_VLD2_LANE
179 UNSPEC_VLD3
180 UNSPEC_VLD3A
181 UNSPEC_VLD3B
182 UNSPEC_VLD3_DUP
183 UNSPEC_VLD3_LANE
184 UNSPEC_VLD4
185 UNSPEC_VLD4A
186 UNSPEC_VLD4B
187 UNSPEC_VLD4_DUP
188 UNSPEC_VLD4_LANE
189 UNSPEC_VMAX
190 UNSPEC_VMIN
191 UNSPEC_VMLA
192 UNSPEC_VMLAL
193 UNSPEC_VMLA_LANE
194 UNSPEC_VMLAL_LANE
195 UNSPEC_VMLS
196 UNSPEC_VMLSL
197 UNSPEC_VMLS_LANE
198 UNSPEC_VMLSL_LANE
199 UNSPEC_VMOVL
200 UNSPEC_VMOVN
201 UNSPEC_VMUL
202 UNSPEC_VMULL
203 UNSPEC_VMUL_LANE
204 UNSPEC_VMULL_LANE
205 UNSPEC_VPADAL
206 UNSPEC_VPADD
207 UNSPEC_VPADDL
208 UNSPEC_VPMAX
209 UNSPEC_VPMIN
210 UNSPEC_VPSMAX
211 UNSPEC_VPSMIN
212 UNSPEC_VPUMAX
213 UNSPEC_VPUMIN
214 UNSPEC_VQABS
215 UNSPEC_VQADD
216 UNSPEC_VQDMLAL
217 UNSPEC_VQDMLAL_LANE
218 UNSPEC_VQDMLSL
219 UNSPEC_VQDMLSL_LANE
220 UNSPEC_VQDMULH
221 UNSPEC_VQDMULH_LANE
222 UNSPEC_VQDMULL
223 UNSPEC_VQDMULL_LANE
224 UNSPEC_VQMOVN
225 UNSPEC_VQMOVUN
226 UNSPEC_VQNEG
227 UNSPEC_VQSHL
228 UNSPEC_VQSHL_N
229 UNSPEC_VQSHLU_N
230 UNSPEC_VQSHRN_N
231 UNSPEC_VQSHRUN_N
232 UNSPEC_VQSUB
233 UNSPEC_VRECPE
234 UNSPEC_VRECPS
235 UNSPEC_VREV16
236 UNSPEC_VREV32
237 UNSPEC_VREV64
238 UNSPEC_VRSQRTE
239 UNSPEC_VRSQRTS
240 UNSPEC_VSHL
241 UNSPEC_VSHLL_N
242 UNSPEC_VSHL_N
243 UNSPEC_VSHR_N
244 UNSPEC_VSHRN_N
245 UNSPEC_VSLI
246 UNSPEC_VSRA_N
247 UNSPEC_VSRI
248 UNSPEC_VST1
249 UNSPEC_VST1_LANE
250 UNSPEC_VST2
251 UNSPEC_VST2_LANE
252 UNSPEC_VST3
253 UNSPEC_VST3A
254 UNSPEC_VST3B
255 UNSPEC_VST3_LANE
256 UNSPEC_VST4
257 UNSPEC_VST4A
258 UNSPEC_VST4B
259 UNSPEC_VST4_LANE
260 UNSPEC_VSTRUCTDUMMY
261 UNSPEC_VSUB
262 UNSPEC_VSUBHN
263 UNSPEC_VSUBL
264 UNSPEC_VSUBW
265 UNSPEC_VTBL
266 UNSPEC_VTBX
267 UNSPEC_VTRN1
268 UNSPEC_VTRN2
269 UNSPEC_VTST
270 UNSPEC_VUZP1
271 UNSPEC_VUZP2
272 UNSPEC_VZIP1
273 UNSPEC_VZIP2
274 UNSPEC_MISALIGNED_ACCESS
275 UNSPEC_VCLE
276 UNSPEC_VCLT
277 UNSPEC_NVRINTZ
278 UNSPEC_NVRINTP
279 UNSPEC_NVRINTM
280 UNSPEC_NVRINTX
281 UNSPEC_NVRINTA
282 UNSPEC_NVRINTN
283 ])