1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2015 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
30 #include "config/rs6000/rs6000-opts.h"
33 /* Definitions for the object file format. These are set at
36 #define OBJECT_XCOFF 1
39 #define OBJECT_MACHO 4
41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
51 #define TARGET_AIX_OS 0
54 /* Control whether function entry points use a "dot" symbol when
58 /* Default string to use for cpu if not specified. */
59 #ifndef TARGET_CPU_DEFAULT
60 #define TARGET_CPU_DEFAULT ((char *)0)
63 /* If configured for PPC405, support PPC405CR Erratum77. */
64 #ifdef CONFIG_PPC405CR
65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
67 #define PPC405_ERRATUM77 0
70 #ifndef TARGET_PAIRED_FLOAT
71 #define TARGET_PAIRED_FLOAT 0
74 #ifdef HAVE_AS_POPCNTB
75 #define ASM_CPU_POWER5_SPEC "-mpower5"
77 #define ASM_CPU_POWER5_SPEC "-mpower4"
81 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
83 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
86 #ifdef HAVE_AS_POPCNTD
87 #define ASM_CPU_POWER7_SPEC "-mpower7"
89 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
93 #define ASM_CPU_POWER8_SPEC "-mpower8"
95 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC
99 #define ASM_CPU_476_SPEC "-m476"
101 #define ASM_CPU_476_SPEC "-mpower4"
104 /* Common ASM definitions used by ASM_SPEC among the various targets for
105 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
106 provide the default assembler options if the user uses -mcpu=native, so if
107 you make changes here, make them also there. */
108 #define ASM_CPU_SPEC \
110 %{mpowerpc64*: -mppc64} \
111 %{!mpowerpc64*: %(asm_default)}} \
112 %{mcpu=native: %(asm_cpu_native)} \
113 %{mcpu=cell: -mcell} \
114 %{mcpu=power3: -mppc64} \
115 %{mcpu=power4: -mpower4} \
116 %{mcpu=power5: %(asm_cpu_power5)} \
117 %{mcpu=power5+: %(asm_cpu_power5)} \
118 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
119 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
120 %{mcpu=power7: %(asm_cpu_power7)} \
121 %{mcpu=power8: %(asm_cpu_power8)} \
123 %{mcpu=powerpc: -mppc} \
124 %{mcpu=rs64a: -mppc64} \
128 %{mcpu=405fp: -m405} \
130 %{mcpu=440fp: -m440} \
132 %{mcpu=464fp: -m440} \
133 %{mcpu=476: %(asm_cpu_476)} \
134 %{mcpu=476fp: %(asm_cpu_476)} \
139 %{mcpu=603e: -mppc} \
140 %{mcpu=ec603e: -mppc} \
142 %{mcpu=604e: -mppc} \
143 %{mcpu=620: -mppc64} \
144 %{mcpu=630: -mppc64} \
148 %{mcpu=7400: -mppc -maltivec} \
149 %{mcpu=7450: -mppc -maltivec} \
150 %{mcpu=G4: -mppc -maltivec} \
155 %{mcpu=970: -mpower4 -maltivec} \
156 %{mcpu=G5: -mpower4 -maltivec} \
157 %{mcpu=8540: -me500} \
158 %{mcpu=8548: -me500} \
159 %{mcpu=e300c2: -me300} \
160 %{mcpu=e300c3: -me300} \
161 %{mcpu=e500mc: -me500mc} \
162 %{mcpu=e500mc64: -me500mc64} \
163 %{mcpu=e5500: -me5500} \
164 %{mcpu=e6500: -me6500} \
165 %{maltivec: -maltivec} \
166 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
167 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
170 #define CPP_DEFAULT_SPEC ""
172 #define ASM_DEFAULT_SPEC ""
174 /* This macro defines names of additional specifications to put in the specs
175 that can be used in various specifications like CC1_SPEC. Its definition
176 is an initializer with a subgrouping for each command option.
178 Each subgrouping contains a string constant, that defines the
179 specification name, and a string constant that used by the GCC driver
182 Do not define this macro if it does not need to do anything. */
184 #define SUBTARGET_EXTRA_SPECS
186 #define EXTRA_SPECS \
187 { "cpp_default", CPP_DEFAULT_SPEC }, \
188 { "asm_cpu", ASM_CPU_SPEC }, \
189 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
190 { "asm_default", ASM_DEFAULT_SPEC }, \
191 { "cc1_cpu", CC1_CPU_SPEC }, \
192 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
193 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
194 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
195 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \
196 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
197 SUBTARGET_EXTRA_SPECS
199 /* -mcpu=native handling only makes sense with compiler running on
200 an PowerPC chip. If changing this condition, also change
201 the condition in driver-rs6000.c. */
202 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
203 /* In driver-rs6000.c. */
204 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
205 #define EXTRA_SPEC_FUNCTIONS \
206 { "local_cpu_detect", host_detect_local_cpu },
207 #define HAVE_LOCAL_CPU_DETECT
208 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
211 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
215 #ifdef HAVE_LOCAL_CPU_DETECT
216 #define CC1_CPU_SPEC \
217 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
218 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
220 #define CC1_CPU_SPEC ""
224 /* Architecture type. */
226 /* Define TARGET_MFCRF if the target assembler does not support the
227 optional field operand for mfcr. */
229 #ifndef HAVE_AS_MFCRF
231 #define TARGET_MFCRF 0
234 /* Define TARGET_POPCNTB if the target assembler does not support the
235 popcount byte instruction. */
237 #ifndef HAVE_AS_POPCNTB
238 #undef TARGET_POPCNTB
239 #define TARGET_POPCNTB 0
242 /* Define TARGET_FPRND if the target assembler does not support the
243 fp rounding instructions. */
245 #ifndef HAVE_AS_FPRND
247 #define TARGET_FPRND 0
250 /* Define TARGET_CMPB if the target assembler does not support the
255 #define TARGET_CMPB 0
258 /* Define TARGET_MFPGPR if the target assembler does not support the
259 mffpr and mftgpr instructions. */
261 #ifndef HAVE_AS_MFPGPR
263 #define TARGET_MFPGPR 0
266 /* Define TARGET_DFP if the target assembler does not support decimal
267 floating point instructions. */
273 /* Define TARGET_POPCNTD if the target assembler does not support the
274 popcount word and double word instructions. */
276 #ifndef HAVE_AS_POPCNTD
277 #undef TARGET_POPCNTD
278 #define TARGET_POPCNTD 0
281 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the
282 waitasecond instruction. Allow -mpower8-fusion, since it does not add new
285 #ifndef HAVE_AS_POWER8
286 #undef TARGET_DIRECT_MOVE
289 #undef TARGET_P8_VECTOR
290 #define TARGET_DIRECT_MOVE 0
291 #define TARGET_CRYPTO 0
293 #define TARGET_P8_VECTOR 0
296 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
297 not, generate the lwsync code as an integer constant. */
298 #ifdef HAVE_AS_LWSYNC
299 #define TARGET_LWSYNC_INSTRUCTION 1
301 #define TARGET_LWSYNC_INSTRUCTION 0
304 /* Define TARGET_TLS_MARKERS if the target assembler does not support
305 arg markers for __tls_get_addr calls. */
306 #ifndef HAVE_AS_TLS_MARKERS
307 #undef TARGET_TLS_MARKERS
308 #define TARGET_TLS_MARKERS 0
310 #define TARGET_TLS_MARKERS tls_markers
313 #ifndef TARGET_SECURE_PLT
314 #define TARGET_SECURE_PLT 0
317 #ifndef TARGET_CMODEL
318 #define TARGET_CMODEL CMODEL_SMALL
321 #define TARGET_32BIT (! TARGET_64BIT)
324 #define HAVE_AS_TLS 0
327 #ifndef TARGET_LINK_STACK
328 #define TARGET_LINK_STACK 0
331 #ifndef SET_TARGET_LINK_STACK
332 #define SET_TARGET_LINK_STACK(X) do { } while (0)
335 /* Return 1 for a symbol ref for a thread-local storage symbol. */
336 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
337 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
340 /* For libgcc2 we make sure this is a compile time constant */
341 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
342 #undef TARGET_POWERPC64
343 #define TARGET_POWERPC64 1
345 #undef TARGET_POWERPC64
346 #define TARGET_POWERPC64 0
349 /* The option machinery will define this. */
352 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING)
354 /* FPU operations supported.
355 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
356 also test TARGET_HARD_FLOAT. */
357 #define TARGET_SINGLE_FLOAT 1
358 #define TARGET_DOUBLE_FLOAT 1
359 #define TARGET_SINGLE_FPU 0
360 #define TARGET_SIMPLE_FPU 0
361 #define TARGET_XILINX_FPU 0
363 /* Recast the processor type to the cpu attribute. */
364 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
366 /* Define generic processor types based upon current deployment. */
367 #define PROCESSOR_COMMON PROCESSOR_PPC601
368 #define PROCESSOR_POWERPC PROCESSOR_PPC604
369 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
371 /* Define the default processor. This is overridden by other tm.h files. */
372 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
373 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
375 /* Specify the dialect of assembler to use. Only new mnemonics are supported
376 starting with GCC 4.8, i.e. just one dialect, but for backwards
377 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
379 #define ASSEMBLER_DIALECT 1
382 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
383 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
384 #define MASK_DEBUG_REG 0x04 /* debug register handling */
385 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
386 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
387 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
388 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
389 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
394 | MASK_DEBUG_TARGET \
395 | MASK_DEBUG_BUILTIN)
397 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
398 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
399 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
400 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
401 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
402 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
403 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
405 /* Describe the vector unit used for arithmetic operations. */
406 extern enum rs6000_vector rs6000_vector_unit
[];
408 #define VECTOR_UNIT_NONE_P(MODE) \
409 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
411 #define VECTOR_UNIT_VSX_P(MODE) \
412 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
414 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
415 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
417 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
418 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
420 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
421 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
423 (int)VECTOR_P8_VECTOR))
425 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
426 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
427 compatible, so allow it as well, rather than changing all of the uses of the
429 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
430 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
431 (int)VECTOR_ALTIVEC, \
432 (int)VECTOR_P8_VECTOR))
434 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
435 same unit as the vector unit we are using, but we may want to migrate to
436 using VSX style loads even for types handled by altivec. */
437 extern enum rs6000_vector rs6000_vector_mem
[];
439 #define VECTOR_MEM_NONE_P(MODE) \
440 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
442 #define VECTOR_MEM_VSX_P(MODE) \
443 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
445 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
446 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
448 #define VECTOR_MEM_ALTIVEC_P(MODE) \
449 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
451 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
452 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
454 (int)VECTOR_P8_VECTOR))
456 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
457 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
458 (int)VECTOR_ALTIVEC, \
459 (int)VECTOR_P8_VECTOR))
461 /* Return the alignment of a given vector type, which is set based on the
462 vector unit use. VSX for instance can load 32 or 64 bit aligned words
463 without problems, while Altivec requires 128-bit aligned vectors. */
464 extern int rs6000_vector_align
[];
466 #define VECTOR_ALIGN(MODE) \
467 ((rs6000_vector_align[(MODE)] != 0) \
468 ? rs6000_vector_align[(MODE)] \
469 : (int)GET_MODE_BITSIZE ((MODE)))
471 /* Determine the element order to use for vector instructions. By
472 default we use big-endian element order when targeting big-endian,
473 and little-endian element order when targeting little-endian. For
474 programs being ported from BE Power to LE Power, it can sometimes
475 be useful to use big-endian element order when targeting little-endian.
476 This is set via -maltivec=be, for example. */
477 #define VECTOR_ELT_ORDER_BIG \
478 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
480 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
481 with scalar instructions. */
482 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
484 /* Alignment options for fields in structures for sub-targets following
486 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
487 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
489 Override the macro definitions when compiling libobjc to avoid undefined
490 reference to rs6000_alignment_flags due to library's use of GCC alignment
491 macros which use the macros below. */
493 #ifndef IN_TARGET_LIBS
494 #define MASK_ALIGN_POWER 0x00000000
495 #define MASK_ALIGN_NATURAL 0x00000001
496 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
498 #define TARGET_ALIGN_NATURAL 0
501 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
502 #define TARGET_IEEEQUAD rs6000_ieeequad
503 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
504 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
506 #define TARGET_SPE_ABI 0
508 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
509 #define TARGET_FPRS 1
510 #define TARGET_E500_SINGLE 0
511 #define TARGET_E500_DOUBLE 0
512 #define CHECK_E500_OPTIONS do { } while (0)
514 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
515 Enable 32-bit fcfid's on any of the switches for newer ISA machines or
517 #define TARGET_FCFID (TARGET_POWERPC64 \
518 || TARGET_PPC_GPOPT /* 970/power4 */ \
519 || TARGET_POPCNTB /* ISA 2.02 */ \
520 || TARGET_CMPB /* ISA 2.05 */ \
521 || TARGET_POPCNTD /* ISA 2.06 */ \
522 || TARGET_XILINX_FPU)
524 #define TARGET_FCTIDZ TARGET_FCFID
525 #define TARGET_STFIWX TARGET_PPC_GFXOPT
526 #define TARGET_LFIWAX TARGET_CMPB
527 #define TARGET_LFIWZX TARGET_POPCNTD
528 #define TARGET_FCFIDS TARGET_POPCNTD
529 #define TARGET_FCFIDU TARGET_POPCNTD
530 #define TARGET_FCFIDUS TARGET_POPCNTD
531 #define TARGET_FCTIDUZ TARGET_POPCNTD
532 #define TARGET_FCTIWUZ TARGET_POPCNTD
534 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
535 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
536 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
538 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
539 in power7, so conditionalize them on p8 features. TImode syncs need quad
541 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
542 || TARGET_QUAD_MEMORY_ATOMIC \
543 || TARGET_DIRECT_MOVE)
545 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
547 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
548 to allocate the SDmode stack slot to get the value into the proper location
550 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
552 /* In switching from using target_flags to using rs6000_isa_flags, the options
553 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
554 OPTION_MASK_<xxx> back into MASK_<xxx>. */
555 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
556 #define MASK_CMPB OPTION_MASK_CMPB
557 #define MASK_CRYPTO OPTION_MASK_CRYPTO
558 #define MASK_DFP OPTION_MASK_DFP
559 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
560 #define MASK_DLMZB OPTION_MASK_DLMZB
561 #define MASK_EABI OPTION_MASK_EABI
562 #define MASK_FPRND OPTION_MASK_FPRND
563 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
564 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
565 #define MASK_HTM OPTION_MASK_HTM
566 #define MASK_ISEL OPTION_MASK_ISEL
567 #define MASK_MFCRF OPTION_MASK_MFCRF
568 #define MASK_MFPGPR OPTION_MASK_MFPGPR
569 #define MASK_MULHW OPTION_MASK_MULHW
570 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
571 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
572 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
573 #define MASK_POPCNTB OPTION_MASK_POPCNTB
574 #define MASK_POPCNTD OPTION_MASK_POPCNTD
575 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
576 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
577 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
578 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
579 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
580 #define MASK_STRING OPTION_MASK_STRING
581 #define MASK_UPDATE OPTION_MASK_UPDATE
582 #define MASK_VSX OPTION_MASK_VSX
583 #define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE
586 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
590 #define MASK_64BIT OPTION_MASK_64BIT
593 #ifdef TARGET_RELOCATABLE
594 #define MASK_RELOCATABLE OPTION_MASK_RELOCATABLE
597 #ifdef TARGET_LITTLE_ENDIAN
598 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
601 #ifdef TARGET_MINIMAL_TOC
602 #define MASK_MINIMAL_TOC OPTION_MASK_MINIMAL_TOC
605 #ifdef TARGET_REGNAMES
606 #define MASK_REGNAMES OPTION_MASK_REGNAMES
609 #ifdef TARGET_PROTOTYPE
610 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
613 /* For power systems, we want to enable Altivec and VSX builtins even if the
614 user did not use -maltivec or -mvsx to allow the builtins to be used inside
615 of #pragma GCC target or the target attribute to change the code level for a
616 given system. The SPE and Paired builtins are only enabled if you configure
617 the compiler for those builtins, and those machines don't support altivec or
620 #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \
621 && ((TARGET_POWERPC64 \
622 || TARGET_PPC_GPOPT /* 970/power4 */ \
623 || TARGET_POPCNTB /* ISA 2.02 */ \
624 || TARGET_CMPB /* ISA 2.05 */ \
625 || TARGET_POPCNTD /* ISA 2.06 */ \
628 || TARGET_HARD_FLOAT)))
630 /* E500 cores only support plain "sync", not lwsync. */
631 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
632 || rs6000_cpu == PROCESSOR_PPC8548)
635 /* Whether SF/DF operations are supported on the E500. */
636 #define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \
639 #define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
640 && !TARGET_FPRS && TARGET_E500_DOUBLE)
642 /* Whether SF/DF operations are supported by by the normal floating point unit
643 (or the vector/scalar unit). */
644 #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
645 && TARGET_SINGLE_FLOAT)
647 #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
648 && TARGET_DOUBLE_FLOAT)
650 /* Whether SF/DF operations are supported by any hardware. */
651 #define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)
652 #define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)
654 /* Which machine supports the various reciprocal estimate instructions. */
655 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
656 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
658 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
659 && TARGET_DOUBLE_FLOAT \
660 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
662 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
663 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
665 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
666 && TARGET_DOUBLE_FLOAT \
667 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
669 /* Whether the various reciprocal divide/square root estimate instructions
670 exist, and whether we should automatically generate code for the instruction
672 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
673 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
674 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
675 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
677 extern unsigned char rs6000_recip_bits
[];
679 #define RS6000_RECIP_HAVE_RE_P(MODE) \
680 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
682 #define RS6000_RECIP_AUTO_RE_P(MODE) \
683 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
685 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
686 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
688 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
689 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
691 /* The default CPU for TARGET_OPTION_OVERRIDE. */
692 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
695 #define REGISTER_TARGET_PRAGMAS() do { \
696 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
697 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
698 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
699 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
702 /* Target #defines. */
703 #define TARGET_CPU_CPP_BUILTINS() \
704 rs6000_cpu_cpp_builtins (pfile)
706 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
707 we're compiling for. Some configurations may need to override it. */
708 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
711 if (BYTES_BIG_ENDIAN) \
713 builtin_define ("__BIG_ENDIAN__"); \
714 builtin_define ("_BIG_ENDIAN"); \
715 builtin_assert ("machine=bigendian"); \
719 builtin_define ("__LITTLE_ENDIAN__"); \
720 builtin_define ("_LITTLE_ENDIAN"); \
721 builtin_assert ("machine=littleendian"); \
726 /* Target machine storage layout. */
728 /* Define this macro if it is advisable to hold scalars in registers
729 in a wider mode than that declared by the program. In such cases,
730 the value is constrained to be within the bounds of the declared
731 type, but kept valid in the wider mode. The signedness of the
732 extension may differ from that of the type. */
734 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
735 if (GET_MODE_CLASS (MODE) == MODE_INT \
736 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
737 (MODE) = TARGET_32BIT ? SImode : DImode;
739 /* Define this if most significant bit is lowest numbered
740 in instructions that operate on numbered bit-fields. */
741 /* That is true on RS/6000. */
742 #define BITS_BIG_ENDIAN 1
744 /* Define this if most significant byte of a word is the lowest numbered. */
745 /* That is true on RS/6000. */
746 #define BYTES_BIG_ENDIAN 1
748 /* Define this if most significant word of a multiword number is lowest
751 For RS/6000 we can decide arbitrarily since there are no machine
752 instructions for them. Might as well be consistent with bits and bytes. */
753 #define WORDS_BIG_ENDIAN 1
755 /* This says that for the IBM long double the larger magnitude double
756 comes first. It's really a two element double array, and arrays
757 don't index differently between little- and big-endian. */
758 #define LONG_DOUBLE_LARGE_FIRST 1
760 #define MAX_BITS_PER_WORD 64
762 /* Width of a word, in units (bytes). */
763 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
765 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
767 #define MIN_UNITS_PER_WORD 4
769 #define UNITS_PER_FP_WORD 8
770 #define UNITS_PER_ALTIVEC_WORD 16
771 #define UNITS_PER_VSX_WORD 16
772 #define UNITS_PER_SPE_WORD 8
773 #define UNITS_PER_PAIRED_WORD 8
775 /* Type used for ptrdiff_t, as a string used in a declaration. */
776 #define PTRDIFF_TYPE "int"
778 /* Type used for size_t, as a string used in a declaration. */
779 #define SIZE_TYPE "long unsigned int"
781 /* Type used for wchar_t, as a string used in a declaration. */
782 #define WCHAR_TYPE "short unsigned int"
784 /* Width of wchar_t in bits. */
785 #define WCHAR_TYPE_SIZE 16
787 /* A C expression for the size in bits of the type `short' on the
788 target machine. If you don't define this, the default is half a
789 word. (If this would be less than one storage unit, it is
790 rounded up to one unit.) */
791 #define SHORT_TYPE_SIZE 16
793 /* A C expression for the size in bits of the type `int' on the
794 target machine. If you don't define this, the default is one
796 #define INT_TYPE_SIZE 32
798 /* A C expression for the size in bits of the type `long' on the
799 target machine. If you don't define this, the default is one
801 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
803 /* A C expression for the size in bits of the type `long long' on the
804 target machine. If you don't define this, the default is two
806 #define LONG_LONG_TYPE_SIZE 64
808 /* A C expression for the size in bits of the type `float' on the
809 target machine. If you don't define this, the default is one
811 #define FLOAT_TYPE_SIZE 32
813 /* A C expression for the size in bits of the type `double' on the
814 target machine. If you don't define this, the default is two
816 #define DOUBLE_TYPE_SIZE 64
818 /* A C expression for the size in bits of the type `long double' on
819 the target machine. If you don't define this, the default is two
821 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
823 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
824 #define WIDEST_HARDWARE_FP_SIZE 64
826 /* Width in bits of a pointer.
827 See also the macro `Pmode' defined below. */
828 extern unsigned rs6000_pointer_size
;
829 #define POINTER_SIZE rs6000_pointer_size
831 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
832 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
834 /* Boundary (in *bits*) on which stack pointer should be aligned. */
835 #define STACK_BOUNDARY \
836 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
839 /* Allocation boundary (in *bits*) for the code of a function. */
840 #define FUNCTION_BOUNDARY 32
842 /* No data type wants to be aligned rounder than this. */
843 #define BIGGEST_ALIGNMENT 128
845 /* Alignment of field after `int : 0' in a structure. */
846 #define EMPTY_FIELD_BOUNDARY 32
848 /* Every structure's size must be a multiple of this. */
849 #define STRUCTURE_SIZE_BOUNDARY 8
851 /* A bit-field declared as `int' forces `int' alignment for the struct. */
852 #define PCC_BITFIELD_TYPE_MATTERS 1
854 enum data_align
{ align_abi
, align_opt
, align_both
};
856 /* A C expression to compute the alignment for a variables in the
857 local store. TYPE is the data type, and ALIGN is the alignment
858 that the object would ordinarily have. */
859 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
860 rs6000_data_alignment (TYPE, ALIGN, align_both)
862 /* Make strings word-aligned so strcpy from constants will be faster. */
863 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
864 (TREE_CODE (EXP) == STRING_CST \
865 && (STRICT_ALIGNMENT || !optimize_size) \
866 && (ALIGN) < BITS_PER_WORD \
870 /* Make arrays of chars word-aligned for the same reasons. */
871 #define DATA_ALIGNMENT(TYPE, ALIGN) \
872 rs6000_data_alignment (TYPE, ALIGN, align_opt)
874 /* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
876 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
877 rs6000_data_alignment (TYPE, ALIGN, align_abi)
879 /* Nonzero if move instructions will actually fail to work
880 when given unaligned data. */
881 #define STRICT_ALIGNMENT 0
883 /* Define this macro to be the value 1 if unaligned accesses have a cost
884 many times greater than aligned accesses, for example if they are
885 emulated in a trap handler. */
886 /* Altivec vector memory instructions simply ignore the low bits; SPE vector
887 memory instructions trap on unaligned accesses; VSX memory instructions are
888 aligned to 4 or 8 bytes. */
889 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
891 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
892 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) \
894 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE))))
897 /* Standard register usage. */
899 /* Number of actual hardware registers.
900 The hardware registers are assigned numbers for the compiler
901 from 0 to just below FIRST_PSEUDO_REGISTER.
902 All registers that the compiler knows about must be given numbers,
903 even those that are not normally considered general registers.
905 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
906 a count register, a link register, and 8 condition register fields,
907 which we view here as separate registers. AltiVec adds 32 vector
908 registers and a VRsave register.
910 In addition, the difference between the frame and argument pointers is
911 a function of the number of registers saved, so we need to have a
912 register for AP that will later be eliminated in favor of SP or FP.
913 This is a normal register, but it is fixed.
915 We also create a pseudo register for float/int conversions, that will
916 really represent the memory location used. It is represented here as
917 a register, in order to work around problems in allocating stack storage
920 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
921 pointer, which is eventually eliminated in favor of SP or FP.
923 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
925 #define FIRST_PSEUDO_REGISTER 149
927 /* This must be included for pre gcc 3.0 glibc compatibility. */
928 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
930 /* True if register is an SPE High register. */
931 #define SPE_HIGH_REGNO_P(N) \
932 ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
934 /* SPE high registers added as hard regs.
935 The sfp register and 3 HTM registers
936 aren't included in DWARF_FRAME_REGISTERS. */
937 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
939 /* The SPE has an additional 32 synthetic registers, with DWARF debug
940 info numbering for these registers starting at 1200. While eh_frame
941 register numbering need not be the same as the debug info numbering,
942 we choose to number these regs for eh_frame at 1200 too.
944 We must map them here to avoid huge unwinder tables mostly consisting
946 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
947 ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
949 /* Use standard DWARF numbering for DWARF debugging information. */
950 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
952 /* Use gcc hard register numbering for eh_frame. */
953 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
955 /* Map register numbers held in the call frame info that gcc has
956 collected using DWARF_FRAME_REGNUM to those that should be output in
957 .debug_frame and .eh_frame. */
958 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
959 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1)
961 /* 1 for registers that have pervasive standard uses
962 and are not available for the register allocator.
964 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
965 as a local register; for all other OS's r2 is the TOC pointer.
967 On System V implementations, r13 is fixed and not available for use. */
969 #define FIXED_REGISTERS \
970 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
971 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
972 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
973 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
974 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
975 /* AltiVec registers. */ \
976 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
977 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
979 , 1, 1, 1, 1, 1, 1, \
980 /* SPE High registers. */ \
981 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
982 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
985 /* 1 for registers not available across function calls.
986 These must include the FIXED_REGISTERS and also any
987 registers that can be used without being saved.
988 The latter must include the registers where values are returned
989 and the register where structure-value addresses are passed.
990 Aside from that, you can include as many other registers as you like. */
992 #define CALL_USED_REGISTERS \
993 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
994 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
995 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
996 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
997 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
998 /* AltiVec registers. */ \
999 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1000 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1002 , 1, 1, 1, 1, 1, 1, \
1003 /* SPE High registers. */ \
1004 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1005 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1008 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
1009 the entire set of `FIXED_REGISTERS' be included.
1010 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
1011 This macro is optional. If not specified, it defaults to the value
1012 of `CALL_USED_REGISTERS'. */
1014 #define CALL_REALLY_USED_REGISTERS \
1015 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1016 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1017 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1018 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1019 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1020 /* AltiVec registers. */ \
1021 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1022 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1024 , 0, 0, 0, 0, 0, 0, \
1025 /* SPE High registers. */ \
1026 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1027 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1030 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
1032 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
1033 #define FIRST_SAVED_FP_REGNO (14+32)
1034 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
1036 /* List the order in which to allocate registers. Each register must be
1037 listed once, even those in FIXED_REGISTERS.
1039 We allocate in the following order:
1040 fp0 (not saved or used for anything)
1041 fp13 - fp2 (not saved; incoming fp arg registers)
1042 fp1 (not saved; return value)
1043 fp31 - fp14 (saved; order given to save least number)
1044 cr7, cr5 (not saved or special)
1045 cr6 (not saved, but used for vector operations)
1046 cr1 (not saved, but used for FP operations)
1047 cr0 (not saved, but used for arithmetic operations)
1048 cr4, cr3, cr2 (saved)
1049 r9 (not saved; best for TImode)
1050 r10, r8-r4 (not saved; highest first for less conflict with params)
1051 r3 (not saved; return value register)
1052 r11 (not saved; later alloc to help shrink-wrap)
1053 r0 (not saved; cannot be base reg)
1054 r31 - r13 (saved; order given to save least number)
1055 r12 (not saved; if used for DImode or DFmode would use r13)
1056 ctr (not saved; when we have the choice ctr is better)
1058 r1, r2, ap, ca (fixed)
1059 v0 - v1 (not saved or used for anything)
1060 v13 - v3 (not saved; incoming vector arg registers)
1061 v2 (not saved; incoming vector arg reg; return value)
1062 v19 - v14 (not saved or used for anything)
1063 v31 - v20 (saved; order given to save least number)
1064 vrsave, vscr (fixed)
1065 spe_acc, spefscr (fixed)
1073 #define MAYBE_R2_AVAILABLE
1074 #define MAYBE_R2_FIXED 2,
1076 #define MAYBE_R2_AVAILABLE 2,
1077 #define MAYBE_R2_FIXED
1081 #define EARLY_R12 12,
1085 #define LATE_R12 12,
1088 #define REG_ALLOC_ORDER \
1090 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
1091 /* not use fr14 which is a saved register. */ \
1092 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
1094 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1095 50, 49, 48, 47, 46, \
1096 75, 73, 74, 69, 68, 72, 71, 70, \
1097 MAYBE_R2_AVAILABLE \
1098 9, 10, 8, 7, 6, 5, 4, \
1099 3, EARLY_R12 11, 0, \
1100 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1101 18, 17, 16, 15, 14, 13, LATE_R12 \
1103 1, MAYBE_R2_FIXED 67, 76, \
1104 /* AltiVec registers. */ \
1106 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
1108 96, 95, 94, 93, 92, 91, \
1109 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1111 111, 112, 113, 114, 115, 116, \
1112 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
1113 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
1114 141, 142, 143, 144, 145, 146, 147, 148 \
1117 /* True if register is floating-point. */
1118 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1120 /* True if register is a condition register. */
1121 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
1123 /* True if register is a condition register, but not cr0. */
1124 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1126 /* True if register is an integer register. */
1127 #define INT_REGNO_P(N) \
1128 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1130 /* SPE SIMD registers are just the GPRs. */
1131 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1133 /* PAIRED SIMD registers are just the FPRs. */
1134 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1136 /* True if register is the CA register. */
1137 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1139 /* True if register is an AltiVec register. */
1140 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1142 /* True if register is a VSX register. */
1143 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1145 /* Alternate name for any vector register supporting floating point, no matter
1146 which instruction set(s) are available. */
1147 #define VFLOAT_REGNO_P(N) \
1148 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1150 /* Alternate name for any vector register supporting integer, no matter which
1151 instruction set(s) are available. */
1152 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1154 /* Alternate name for any vector register supporting logical operations, no
1155 matter which instruction set(s) are available. Allow GPRs as well as the
1156 vector registers. */
1157 #define VLOGICAL_REGNO_P(N) \
1158 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1159 || (TARGET_VSX && FP_REGNO_P (N))) \
1161 /* Return number of consecutive hard regs needed starting at reg REGNO
1162 to hold something of mode MODE. */
1164 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)]
1166 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1167 enough space to account for vectors in FP regs. However, TFmode/TDmode
1168 should not use VSX instructions to do a caller save. */
1169 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1171 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1172 && FP_REGNO_P (REGNO) \
1174 : TARGET_E500_DOUBLE && ((MODE) == VOIDmode || (MODE) == DFmode) \
1176 : !TARGET_E500_DOUBLE && (MODE) == TFmode && FP_REGNO_P (REGNO) \
1178 : !TARGET_E500_DOUBLE && (MODE) == TDmode && FP_REGNO_P (REGNO) \
1180 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1182 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
1183 (((TARGET_32BIT && TARGET_POWERPC64 \
1184 && (GET_MODE_SIZE (MODE) > 4) \
1185 && INT_REGNO_P (REGNO)) ? 1 : 0) \
1186 || (TARGET_VSX && FP_REGNO_P (REGNO) \
1187 && GET_MODE_SIZE (MODE) > 8 && ((MODE) != TDmode) \
1188 && ((MODE) != TFmode)))
1190 #define VSX_VECTOR_MODE(MODE) \
1191 ((MODE) == V4SFmode \
1192 || (MODE) == V2DFmode) \
1194 #define ALTIVEC_VECTOR_MODE(MODE) \
1195 ((MODE) == V16QImode \
1196 || (MODE) == V8HImode \
1197 || (MODE) == V4SFmode \
1198 || (MODE) == V4SImode)
1200 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1201 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1202 || (MODE) == V2DImode || (MODE) == V1TImode)
1204 #define SPE_VECTOR_MODE(MODE) \
1205 ((MODE) == V4HImode \
1206 || (MODE) == V2SFmode \
1207 || (MODE) == V1DImode \
1208 || (MODE) == V2SImode)
1210 #define PAIRED_VECTOR_MODE(MODE) \
1211 ((MODE) == V2SFmode)
1213 /* Value is TRUE if hard register REGNO can hold a value of
1214 machine-mode MODE. */
1215 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1216 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
1218 /* Value is 1 if it is a good idea to tie two pseudo registers
1219 when one has mode MODE1 and one has mode MODE2.
1220 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1221 for any hard reg, then this must be 0 for correct output.
1223 PTImode cannot tie with other modes because PTImode is restricted to even
1224 GPR registers, and TImode can go in any GPR as well as VSX registers (PR
1226 #define MODES_TIEABLE_P(MODE1, MODE2) \
1227 ((MODE1) == PTImode \
1228 ? (MODE2) == PTImode \
1229 : (MODE2) == PTImode \
1231 : SCALAR_FLOAT_MODE_P (MODE1) \
1232 ? SCALAR_FLOAT_MODE_P (MODE2) \
1233 : SCALAR_FLOAT_MODE_P (MODE2) \
1235 : GET_MODE_CLASS (MODE1) == MODE_CC \
1236 ? GET_MODE_CLASS (MODE2) == MODE_CC \
1237 : GET_MODE_CLASS (MODE2) == MODE_CC \
1239 : SPE_VECTOR_MODE (MODE1) \
1240 ? SPE_VECTOR_MODE (MODE2) \
1241 : SPE_VECTOR_MODE (MODE2) \
1243 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
1244 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
1245 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
1249 /* Post-reload, we can't use any new AltiVec registers, as we already
1250 emitted the vrsave mask. */
1252 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1253 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1255 /* Specify the cost of a branch insn; roughly the number of extra insns that
1256 should be added to avoid a branch.
1258 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1259 unscheduled conditional branch. */
1261 #define BRANCH_COST(speed_p, predictable_p) 3
1263 /* Override BRANCH_COST heuristic which empirically produces worse
1264 performance for removing short circuiting from the logical ops. */
1266 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1268 /* A fixed register used at epilogue generation to address SPE registers
1269 with negative offsets. The 64-bit load/store instructions on the SPE
1270 only take positive offsets (and small ones at that), so we need to
1271 reserve a register for consing up negative offsets. */
1273 #define FIXED_SCRATCH 0
1275 /* Specify the registers used for certain standard purposes.
1276 The values of these macros are register numbers. */
1278 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1279 /* #define PC_REGNUM */
1281 /* Register to use for pushing function arguments. */
1282 #define STACK_POINTER_REGNUM 1
1284 /* Base register for access to local variables of the function. */
1285 #define HARD_FRAME_POINTER_REGNUM 31
1287 /* Base register for access to local variables of the function. */
1288 #define FRAME_POINTER_REGNUM 113
1290 /* Base register for access to arguments of the function. */
1291 #define ARG_POINTER_REGNUM 67
1293 /* Place to put static chain when calling a function that requires it. */
1294 #define STATIC_CHAIN_REGNUM 11
1297 /* Define the classes of registers for register constraints in the
1298 machine description. Also define ranges of constants.
1300 One of the classes must always be named ALL_REGS and include all hard regs.
1301 If there is more than one class, another class must be named NO_REGS
1302 and contain no registers.
1304 The name GENERAL_REGS must be the name of a class (or an alias for
1305 another name such as ALL_REGS). This is the class of registers
1306 that is allowed by "g" or "r" in a register constraint.
1307 Also, registers outside this class are allocated only when
1308 instructions express preferences for them.
1310 The classes must be numbered in nondecreasing order; that is,
1311 a larger-numbered class must never be contained completely
1312 in a smaller-numbered class.
1314 For any two classes, it is very desirable that there be another
1315 class that represents their union. */
1317 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1318 condition registers, plus three special registers, CTR, and the link
1319 register. AltiVec adds a vector register class. VSX registers overlap the
1320 FPR registers and the Altivec registers.
1322 However, r0 is special in that it cannot be used as a base register.
1323 So make a class for registers valid as base registers.
1325 Also, cr0 is the only condition code register that can be used in
1326 arithmetic insns, so make a separate class for it. */
1356 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1358 /* Give names of register classes as strings for dump file. */
1360 #define REG_CLASS_NAMES \
1373 "NON_SPECIAL_REGS", \
1376 "LINK_OR_CTR_REGS", \
1378 "SPEC_OR_GEN_REGS", \
1387 /* Define which registers fit in which classes.
1388 This is an initializer for a vector of HARD_REG_SET
1389 of length N_REG_CLASSES. */
1391 #define REG_CLASS_CONTENTS \
1394 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1396 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
1397 /* GENERAL_REGS. */ \
1398 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
1400 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
1401 /* ALTIVEC_REGS. */ \
1402 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
1404 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
1405 /* VRSAVE_REGS. */ \
1406 { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
1408 { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
1409 /* SPE_ACC_REGS. */ \
1410 { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
1411 /* SPEFSCR_REGS. */ \
1412 { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
1414 { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
1415 /* NON_SPECIAL_REGS. */ \
1416 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
1418 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
1420 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
1421 /* LINK_OR_CTR_REGS. */ \
1422 { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
1423 /* SPECIAL_REGS. */ \
1424 { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
1425 /* SPEC_OR_GEN_REGS. */ \
1426 { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
1428 { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
1430 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
1431 /* NON_FLOAT_REGS. */ \
1432 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
1434 { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
1435 /* SPE_HIGH_REGS. */ \
1436 { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
1438 { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
1441 /* The same information, inverted:
1442 Return the class number of the smallest class containing
1443 reg number REGNO. This could be a conditional expression
1444 or could index an array. */
1446 extern enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
1449 #define REGNO_REG_CLASS(REGNO) \
1450 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \
1451 rs6000_regno_regclass[(REGNO)])
1454 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)]
1457 /* Register classes for various constraints that are based on the target
1459 enum r6000_reg_class_enum
{
1460 RS6000_CONSTRAINT_d
, /* fpr registers for double values */
1461 RS6000_CONSTRAINT_f
, /* fpr registers for single values */
1462 RS6000_CONSTRAINT_v
, /* Altivec registers */
1463 RS6000_CONSTRAINT_wa
, /* Any VSX register */
1464 RS6000_CONSTRAINT_wd
, /* VSX register for V2DF */
1465 RS6000_CONSTRAINT_wf
, /* VSX register for V4SF */
1466 RS6000_CONSTRAINT_wg
, /* FPR register for -mmfpgpr */
1467 RS6000_CONSTRAINT_wh
, /* FPR register for direct moves. */
1468 RS6000_CONSTRAINT_wi
, /* FPR/VSX register to hold DImode */
1469 RS6000_CONSTRAINT_wj
, /* FPR/VSX register for DImode direct moves. */
1470 RS6000_CONSTRAINT_wk
, /* FPR/VSX register for DFmode direct moves. */
1471 RS6000_CONSTRAINT_wl
, /* FPR register for LFIWAX */
1472 RS6000_CONSTRAINT_wm
, /* VSX register for direct move */
1473 RS6000_CONSTRAINT_wr
, /* GPR register if 64-bit */
1474 RS6000_CONSTRAINT_ws
, /* VSX register for DF */
1475 RS6000_CONSTRAINT_wt
, /* VSX register for TImode */
1476 RS6000_CONSTRAINT_wu
, /* Altivec register for float load/stores. */
1477 RS6000_CONSTRAINT_wv
, /* Altivec register for double load/stores. */
1478 RS6000_CONSTRAINT_ww
, /* FP or VSX register for vsx float ops. */
1479 RS6000_CONSTRAINT_wx
, /* FPR register for STFIWX */
1480 RS6000_CONSTRAINT_wy
, /* VSX register for SF */
1481 RS6000_CONSTRAINT_wz
, /* FPR register for LFIWZX */
1482 RS6000_CONSTRAINT_MAX
1485 extern enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
1487 /* The class value for index registers, and the one for base regs. */
1488 #define INDEX_REG_CLASS GENERAL_REGS
1489 #define BASE_REG_CLASS BASE_REGS
1491 /* Return whether a given register class can hold VSX objects. */
1492 #define VSX_REG_CLASS_P(CLASS) \
1493 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1495 /* Return whether a given register class targets general purpose registers. */
1496 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1498 /* Given an rtx X being reloaded into a reg required to be
1499 in class CLASS, return the class of reg to actually use.
1500 In general this is just CLASS; but on some machines
1501 in some cases it is preferable to use a more restrictive class.
1503 On the RS/6000, we have to return NO_REGS when we want to reload a
1504 floating-point CONST_DOUBLE to force it to be copied to memory.
1506 We also don't want to reload integer values into floating-point
1507 registers if we can at all help it. In fact, this can
1508 cause reload to die, if it tries to generate a reload of CTR
1509 into a FP register and discovers it doesn't have the memory location
1512 ??? Would it be a good idea to have reload do the converse, that is
1513 try to reload floating modes into FP registers if possible?
1516 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1517 rs6000_preferred_reload_class_ptr (X, CLASS)
1519 /* Return the register class of a scratch register needed to copy IN into
1520 or out of a register in CLASS in MODE. If it can be done directly,
1521 NO_REGS is returned. */
1523 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1524 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1526 /* If we are copying between FP or AltiVec registers and anything
1527 else, we need a memory location. The exception is when we are
1528 targeting ppc64 and the move to/from fpr to gpr instructions
1531 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1532 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE)
1534 /* For cpus that cannot load/store SDmode values from the 64-bit
1535 FP registers without using a full 64-bit load/store, we need
1536 to allocate a full 64-bit stack slot for them. */
1538 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1539 rs6000_secondary_memory_needed_rtx (MODE)
1541 /* Specify the mode to be used for memory when a secondary memory
1542 location is needed. For cpus that cannot load/store SDmode values
1543 from the 64-bit FP registers without using a full 64-bit
1544 load/store, we need a wider mode. */
1545 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1546 rs6000_secondary_memory_needed_mode (MODE)
1548 /* Return the maximum number of consecutive registers
1549 needed to represent mode MODE in a register of class CLASS.
1551 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1552 a single reg is enough for two words, unless we have VSX, where the FP
1553 registers can hold 128 bits. */
1554 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1556 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
1558 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1559 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS)
1561 /* Stack layout; function entry, exit and calling. */
1563 /* Define this if pushing a word on the stack
1564 makes the stack pointer a smaller address. */
1565 #define STACK_GROWS_DOWNWARD
1567 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1568 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1570 /* Define this to nonzero if the nominal address of the stack frame
1571 is at the high-address end of the local variables;
1572 that is, each additional local variable allocated
1573 goes at a more negative offset in the frame.
1575 On the RS/6000, we grow upwards, from the area after the outgoing
1577 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1578 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1580 /* Size of the fixed area on the stack */
1581 #define RS6000_SAVE_AREA \
1582 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1583 << (TARGET_64BIT ? 1 : 0))
1585 /* Stack offset for toc save slot. */
1586 #define RS6000_TOC_SAVE_SLOT \
1587 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1589 /* Align an address */
1590 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1592 /* Offset within stack frame to start allocating local variables at.
1593 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1594 first local allocated. Otherwise, it is the offset to the BEGINNING
1595 of the first local allocated.
1597 On the RS/6000, the frame pointer is the same as the stack pointer,
1598 except for dynamic allocations. So we start after the fixed area and
1599 outgoing parameter area. */
1601 #define STARTING_FRAME_OFFSET \
1602 (FRAME_GROWS_DOWNWARD \
1604 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1605 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1606 + RS6000_SAVE_AREA))
1608 /* Offset from the stack pointer register to an item dynamically
1609 allocated on the stack, e.g., by `alloca'.
1611 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1612 length of the outgoing arguments. The default is correct for most
1613 machines. See `function.c' for details. */
1614 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1615 (RS6000_ALIGN (crtl->outgoing_args_size, \
1616 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1617 + (STACK_POINTER_OFFSET))
1619 /* If we generate an insn to push BYTES bytes,
1620 this says how many the stack pointer really advances by.
1621 On RS/6000, don't define this because there are no push insns. */
1622 /* #define PUSH_ROUNDING(BYTES) */
1624 /* Offset of first parameter from the argument pointer register value.
1625 On the RS/6000, we define the argument pointer to the start of the fixed
1627 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1629 /* Offset from the argument pointer register value to the top of
1630 stack. This is different from FIRST_PARM_OFFSET because of the
1631 register save area. */
1632 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1634 /* Define this if stack space is still allocated for a parameter passed
1635 in a register. The value is the number of bytes allocated to this
1637 #define REG_PARM_STACK_SPACE(FNDECL) \
1638 rs6000_reg_parm_stack_space ((FNDECL), false)
1640 /* Define this macro if space guaranteed when compiling a function body
1641 is different to space required when making a call, a situation that
1642 can arise with K&R style function definitions. */
1643 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1644 rs6000_reg_parm_stack_space ((FNDECL), true)
1646 /* Define this if the above stack space is to be considered part of the
1647 space allocated by the caller. */
1648 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1650 /* This is the difference between the logical top of stack and the actual sp.
1652 For the RS/6000, sp points past the fixed area. */
1653 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1655 /* Define this if the maximum size of all the outgoing args is to be
1656 accumulated and pushed during the prologue. The amount can be
1657 found in the variable crtl->outgoing_args_size. */
1658 #define ACCUMULATE_OUTGOING_ARGS 1
1660 /* Define how to find the value returned by a library function
1661 assuming the value has mode MODE. */
1663 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1665 /* DRAFT_V4_STRUCT_RET defaults off. */
1666 #define DRAFT_V4_STRUCT_RET 0
1668 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1669 #define DEFAULT_PCC_STRUCT_RETURN 0
1671 /* Mode of stack savearea.
1672 FUNCTION is VOIDmode because calling convention maintains SP.
1673 BLOCK needs Pmode for SP.
1674 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1675 #define STACK_SAVEAREA_MODE(LEVEL) \
1676 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1677 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1679 /* Minimum and maximum general purpose registers used to hold arguments. */
1680 #define GP_ARG_MIN_REG 3
1681 #define GP_ARG_MAX_REG 10
1682 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1684 /* Minimum and maximum floating point registers used to hold arguments. */
1685 #define FP_ARG_MIN_REG 33
1686 #define FP_ARG_AIX_MAX_REG 45
1687 #define FP_ARG_V4_MAX_REG 40
1688 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1689 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1690 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1692 /* Minimum and maximum AltiVec registers used to hold arguments. */
1693 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1694 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1695 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1697 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1698 #define AGGR_ARG_NUM_REG 8
1700 /* Return registers */
1701 #define GP_ARG_RETURN GP_ARG_MIN_REG
1702 #define FP_ARG_RETURN FP_ARG_MIN_REG
1703 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1704 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1705 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1706 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \
1707 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1709 /* Flags for the call/call_value rtl operations set up by function_arg */
1710 #define CALL_NORMAL 0x00000000 /* no special processing */
1711 /* Bits in 0x00000001 are unused. */
1712 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1713 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1714 #define CALL_LONG 0x00000008 /* always call indirect */
1715 #define CALL_LIBCALL 0x00000010 /* libcall */
1717 /* We don't have prologue and epilogue functions to save/restore
1718 everything for most ABIs. */
1719 #define WORLD_SAVE_P(INFO) 0
1721 /* 1 if N is a possible register number for a function value
1722 as seen by the caller.
1724 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1725 #define FUNCTION_VALUE_REGNO_P(N) \
1726 ((N) == GP_ARG_RETURN \
1727 || ((N) >= FP_ARG_RETURN && (N) <= FP_ARG_MAX_RETURN \
1728 && TARGET_HARD_FLOAT && TARGET_FPRS) \
1729 || ((N) >= ALTIVEC_ARG_RETURN && (N) <= ALTIVEC_ARG_MAX_RETURN \
1730 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1732 /* 1 if N is a possible register number for function argument passing.
1733 On RS/6000, these are r3-r10 and fp1-fp13.
1734 On AltiVec, v2 - v13 are used for passing vectors. */
1735 #define FUNCTION_ARG_REGNO_P(N) \
1736 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1737 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1738 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1739 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1740 && TARGET_HARD_FLOAT && TARGET_FPRS))
1742 /* Define a data type for recording info about an argument list
1743 during the scan of that argument list. This data type should
1744 hold all necessary information about the function itself
1745 and about the args processed so far, enough to enable macros
1746 such as FUNCTION_ARG to determine where the next arg should go.
1748 On the RS/6000, this is a structure. The first element is the number of
1749 total argument words, the second is used to store the next
1750 floating-point register number, and the third says how many more args we
1751 have prototype types for.
1753 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1754 the next available GP register, `fregno' is the next available FP
1755 register, and `words' is the number of words used on the stack.
1757 The varargs/stdarg support requires that this structure's size
1758 be a multiple of sizeof(int). */
1760 typedef struct rs6000_args
1762 int words
; /* # words used for passing GP registers */
1763 int fregno
; /* next available FP register */
1764 int vregno
; /* next available AltiVec register */
1765 int nargs_prototype
; /* # args left in the current prototype */
1766 int prototype
; /* Whether a prototype was defined */
1767 int stdarg
; /* Whether function is a stdarg function. */
1768 int call_cookie
; /* Do special things for this call */
1769 int sysv_gregno
; /* next available GP register */
1770 int intoffset
; /* running offset in struct (darwin64) */
1771 int use_stack
; /* any part of struct on stack (darwin64) */
1772 int floats_in_gpr
; /* count of SFmode floats taking up
1773 GPR space (darwin64) */
1774 int named
; /* false for varargs params */
1775 int escapes
; /* if function visible outside tu */
1778 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1779 for a call to a function whose data type is FNTYPE.
1780 For a library call, FNTYPE is 0. */
1782 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1783 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1784 N_NAMED_ARGS, FNDECL, VOIDmode)
1786 /* Similar, but when scanning the definition of a procedure. We always
1787 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1789 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1790 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1791 1000, current_function_decl, VOIDmode)
1793 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1795 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1796 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1799 /* If defined, a C expression which determines whether, and in which
1800 direction, to pad out an argument with extra space. The value
1801 should be of type `enum direction': either `upward' to pad above
1802 the argument, `downward' to pad below, or `none' to inhibit
1805 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1807 #define PAD_VARARGS_DOWN \
1808 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1810 /* Output assembler code to FILE to increment profiler label # LABELNO
1811 for profiling a function entry. */
1813 #define FUNCTION_PROFILER(FILE, LABELNO) \
1814 output_function_profiler ((FILE), (LABELNO));
1816 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1817 the stack pointer does not matter. No definition is equivalent to
1820 On the RS/6000, this is nonzero because we can restore the stack from
1821 its backpointer, which we maintain. */
1822 #define EXIT_IGNORE_STACK 1
1824 /* Define this macro as a C expression that is nonzero for registers
1825 that are used by the epilogue or the return' pattern. The stack
1826 and frame pointer registers are already be assumed to be used as
1829 #define EPILOGUE_USES(REGNO) \
1830 ((reload_completed && (REGNO) == LR_REGNO) \
1831 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1832 || (crtl->calls_eh_return \
1837 /* Length in units of the trampoline for entering a nested function. */
1839 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1841 /* Definitions for __builtin_return_address and __builtin_frame_address.
1842 __builtin_return_address (0) should give link register (65), enable
1844 /* This should be uncommented, so that the link register is used, but
1845 currently this would result in unmatched insns and spilling fixed
1846 registers so we'll leave it for another day. When these problems are
1847 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1849 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1851 /* Number of bytes into the frame return addresses can be found. See
1852 rs6000_stack_info in rs6000.c for more information on how the different
1853 abi's store the return address. */
1854 #define RETURN_ADDRESS_OFFSET \
1855 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1857 /* The current return address is in link register (65). The return address
1858 of anything farther back is accessed normally at an offset of 8 from the
1860 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1861 (rs6000_return_addr (COUNT, FRAME))
1864 /* Definitions for register eliminations.
1866 We have two registers that can be eliminated on the RS/6000. First, the
1867 frame pointer register can often be eliminated in favor of the stack
1868 pointer register. Secondly, the argument pointer register can always be
1869 eliminated; it is replaced with either the stack or frame pointer.
1871 In addition, we use the elimination mechanism to see if r30 is needed
1872 Initially we assume that it isn't. If it is, we spill it. This is done
1873 by making it an eliminable register. We replace it with itself so that
1874 if it isn't needed, then existing uses won't be modified. */
1876 /* This is an array of structures. Each structure initializes one pair
1877 of eliminable registers. The "from" register number is given first,
1878 followed by "to". Eliminations of the same "from" register are listed
1879 in order of preference. */
1880 #define ELIMINABLE_REGS \
1881 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1882 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1883 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1884 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1885 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1886 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1888 /* Define the offset between two registers, one to be eliminated, and the other
1889 its replacement, at the start of a routine. */
1890 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1891 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1893 /* Addressing modes, and classification of registers for them. */
1895 #define HAVE_PRE_DECREMENT 1
1896 #define HAVE_PRE_INCREMENT 1
1897 #define HAVE_PRE_MODIFY_DISP 1
1898 #define HAVE_PRE_MODIFY_REG 1
1900 /* Macros to check register numbers against specific register classes. */
1902 /* These assume that REGNO is a hard or pseudo reg number.
1903 They give nonzero only if REGNO is a hard reg of the suitable class
1904 or a pseudo reg currently allocated to a suitable hard reg.
1905 Since they use reg_renumber, they are safe only once reg_renumber
1906 has been allocated, which happens in reginfo.c during register
1909 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1910 ((REGNO) < FIRST_PSEUDO_REGISTER \
1911 ? (REGNO) <= 31 || (REGNO) == 67 \
1912 || (REGNO) == FRAME_POINTER_REGNUM \
1913 : (reg_renumber[REGNO] >= 0 \
1914 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1915 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1917 #define REGNO_OK_FOR_BASE_P(REGNO) \
1918 ((REGNO) < FIRST_PSEUDO_REGISTER \
1919 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1920 || (REGNO) == FRAME_POINTER_REGNUM \
1921 : (reg_renumber[REGNO] > 0 \
1922 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1923 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1925 /* Nonzero if X is a hard reg that can be used as an index
1926 or if it is a pseudo reg in the non-strict case. */
1927 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1928 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1929 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1931 /* Nonzero if X is a hard reg that can be used as a base reg
1932 or if it is a pseudo reg in the non-strict case. */
1933 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1934 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1935 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1938 /* Maximum number of registers that can appear in a valid memory address. */
1940 #define MAX_REGS_PER_ADDRESS 2
1942 /* Recognize any constant value that is a valid address. */
1944 #define CONSTANT_ADDRESS_P(X) \
1945 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1946 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1947 || GET_CODE (X) == HIGH)
1949 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1950 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1951 && EASY_VECTOR_15((n) >> 1) \
1954 #define EASY_VECTOR_MSB(n,mode) \
1955 (((unsigned HOST_WIDE_INT)n) == \
1956 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1959 /* Try a machine-dependent way of reloading an illegitimate address
1960 operand. If we find one, push the reload and jump to WIN. This
1961 macro is used in only one place: `find_reloads_address' in reload.c.
1963 Implemented on rs6000 by rs6000_legitimize_reload_address.
1964 Note that (X) is evaluated twice; this is safe in current usage. */
1966 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1969 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
1970 (int)(TYPE), (IND_LEVELS), &win); \
1975 #define FIND_BASE_TERM rs6000_find_base_term
1977 /* The register number of the register used to address a table of
1978 static data addresses in memory. In some cases this register is
1979 defined by a processor's "application binary interface" (ABI).
1980 When this macro is defined, RTL is generated for this register
1981 once, as with the stack pointer and frame pointer registers. If
1982 this macro is not defined, it is up to the machine-dependent files
1983 to allocate such a register (if necessary). */
1985 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1986 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1988 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1990 /* Define this macro if the register defined by
1991 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1992 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1994 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1996 /* A C expression that is nonzero if X is a legitimate immediate
1997 operand on the target machine when generating position independent
1998 code. You can assume that X satisfies `CONSTANT_P', so you need
1999 not check this. You can also assume FLAG_PIC is true, so you need
2000 not check it either. You need not define this macro if all
2001 constants (including `SYMBOL_REF') can be immediate operands when
2002 generating position independent code. */
2004 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2006 /* Define this if some processing needs to be done immediately before
2007 emitting code for an insn. */
2009 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
2010 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
2012 /* Specify the machine mode that this machine uses
2013 for the index in the tablejump instruction. */
2014 #define CASE_VECTOR_MODE SImode
2016 /* Define as C expression which evaluates to nonzero if the tablejump
2017 instruction expects the table to contain offsets from the address of the
2019 Do not define this if the table should contain absolute addresses. */
2020 #define CASE_VECTOR_PC_RELATIVE 1
2022 /* Define this as 1 if `char' should by default be signed; else as 0. */
2023 #define DEFAULT_SIGNED_CHAR 0
2025 /* An integer expression for the size in bits of the largest integer machine
2026 mode that should actually be used. */
2028 /* Allow pairs of registers to be used, which is the intent of the default. */
2029 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
2031 /* Max number of bytes we can move from memory to memory
2032 in one reasonably fast instruction. */
2033 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2034 #define MAX_MOVE_MAX 8
2036 /* Nonzero if access to memory by bytes is no faster than for words.
2037 Also nonzero if doing byte operations (specifically shifts) in registers
2039 #define SLOW_BYTE_ACCESS 1
2041 /* Define if operations between registers always perform the operation
2042 on the full register even if a narrower mode is specified. */
2043 #define WORD_REGISTER_OPERATIONS
2045 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2046 will either zero-extend or sign-extend. The value of this macro should
2047 be the code that says which one of the two operations is implicitly
2048 done, UNKNOWN if none. */
2049 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2051 /* Define if loading short immediate values into registers sign extends. */
2052 #define SHORT_IMMEDIATES_SIGN_EXTEND
2054 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2055 is done just by pretending it is already truncated. */
2056 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2058 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2059 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2060 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
2062 /* The CTZ patterns return -1 for input of zero. */
2063 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
2065 /* Specify the machine mode that pointers have.
2066 After generation of rtl, the compiler makes no further distinction
2067 between pointers and any other objects of this machine mode. */
2068 extern unsigned rs6000_pmode
;
2069 #define Pmode ((machine_mode)rs6000_pmode)
2071 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2072 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2074 /* Mode of a function address in a call instruction (for indexing purposes).
2075 Doesn't matter on RS/6000. */
2076 #define FUNCTION_MODE SImode
2078 /* Define this if addresses of constant functions
2079 shouldn't be put through pseudo regs where they can be cse'd.
2080 Desirable on machines where ordinary constants are expensive
2081 but a CALL with constant address is cheap. */
2082 #define NO_FUNCTION_CSE
2084 /* Define this to be nonzero if shift instructions ignore all but the low-order
2087 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2088 have been dropped from the PowerPC architecture. */
2089 #define SHIFT_COUNT_TRUNCATED 0
2091 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2092 should be adjusted to reflect any required changes. This macro is used when
2093 there is some systematic length adjustment required that would be difficult
2094 to express in the length attribute. */
2096 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2098 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2099 COMPARE, return the mode to be used for the comparison. For
2100 floating-point, CCFPmode should be used. CCUNSmode should be used
2101 for unsigned comparisons. CCEQmode should be used when we are
2102 doing an inequality comparison on the result of a
2103 comparison. CCmode should be used in all other cases. */
2105 #define SELECT_CC_MODE(OP,X,Y) \
2106 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2107 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2108 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2109 ? CCEQmode : CCmode))
2111 /* Can the condition code MODE be safely reversed? This is safe in
2112 all cases on this port, because at present it doesn't use the
2113 trapping FP comparisons (fcmpo). */
2114 #define REVERSIBLE_CC_MODE(MODE) 1
2116 /* Given a condition code and a mode, return the inverse condition. */
2117 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2120 /* Control the assembler format that we output. */
2122 /* A C string constant describing how to begin a comment in the target
2123 assembler language. The compiler assumes that the comment will end at
2124 the end of the line. */
2125 #define ASM_COMMENT_START " #"
2127 /* Flag to say the TOC is initialized */
2128 extern int toc_initialized
;
2130 /* Macro to output a special constant pool entry. Go to WIN if we output
2131 it. Otherwise, it is written the usual way.
2133 On the RS/6000, toc entries are handled this way. */
2135 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2136 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2138 output_toc (FILE, X, LABELNO, MODE); \
2143 #ifdef HAVE_GAS_WEAK
2144 #define RS6000_WEAK 1
2146 #define RS6000_WEAK 0
2150 /* Used in lieu of ASM_WEAKEN_LABEL. */
2151 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2154 fputs ("\t.weak\t", (FILE)); \
2155 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2156 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2157 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2160 fputs ("[DS]", (FILE)); \
2161 fputs ("\n\t.weak\t.", (FILE)); \
2162 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2164 fputc ('\n', (FILE)); \
2167 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2168 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2169 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2171 fputs ("\t.set\t.", (FILE)); \
2172 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2173 fputs (",.", (FILE)); \
2174 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2175 fputc ('\n', (FILE)); \
2182 #if HAVE_GAS_WEAKREF
2183 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2186 fputs ("\t.weakref\t", (FILE)); \
2187 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2188 fputs (", ", (FILE)); \
2189 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2190 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2191 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2193 fputs ("\n\t.weakref\t.", (FILE)); \
2194 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2195 fputs (", .", (FILE)); \
2196 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2198 fputc ('\n', (FILE)); \
2202 /* This implements the `alias' attribute. */
2203 #undef ASM_OUTPUT_DEF_FROM_DECLS
2204 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2207 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2208 const char *name = IDENTIFIER_POINTER (TARGET); \
2209 if (TREE_CODE (DECL) == FUNCTION_DECL \
2210 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2212 if (TREE_PUBLIC (DECL)) \
2214 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2216 fputs ("\t.globl\t.", FILE); \
2217 RS6000_OUTPUT_BASENAME (FILE, alias); \
2218 putc ('\n', FILE); \
2221 else if (TARGET_XCOFF) \
2223 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2225 fputs ("\t.lglobl\t.", FILE); \
2226 RS6000_OUTPUT_BASENAME (FILE, alias); \
2227 putc ('\n', FILE); \
2228 fputs ("\t.lglobl\t", FILE); \
2229 RS6000_OUTPUT_BASENAME (FILE, alias); \
2230 putc ('\n', FILE); \
2233 fputs ("\t.set\t.", FILE); \
2234 RS6000_OUTPUT_BASENAME (FILE, alias); \
2235 fputs (",.", FILE); \
2236 RS6000_OUTPUT_BASENAME (FILE, name); \
2237 fputc ('\n', FILE); \
2239 ASM_OUTPUT_DEF (FILE, alias, name); \
2243 #define TARGET_ASM_FILE_START rs6000_file_start
2245 /* Output to assembler file text saying following lines
2246 may contain character constants, extra white space, comments, etc. */
2248 #define ASM_APP_ON ""
2250 /* Output to assembler file text saying following lines
2251 no longer contain unusual constructs. */
2253 #define ASM_APP_OFF ""
2255 /* How to refer to registers in assembler output.
2256 This sequence is indexed by compiler's hard-register-number (see above). */
2258 extern char rs6000_reg_names
[][8]; /* register names (0 vs. %r0). */
2260 #define REGISTER_NAMES \
2262 &rs6000_reg_names[ 0][0], /* r0 */ \
2263 &rs6000_reg_names[ 1][0], /* r1 */ \
2264 &rs6000_reg_names[ 2][0], /* r2 */ \
2265 &rs6000_reg_names[ 3][0], /* r3 */ \
2266 &rs6000_reg_names[ 4][0], /* r4 */ \
2267 &rs6000_reg_names[ 5][0], /* r5 */ \
2268 &rs6000_reg_names[ 6][0], /* r6 */ \
2269 &rs6000_reg_names[ 7][0], /* r7 */ \
2270 &rs6000_reg_names[ 8][0], /* r8 */ \
2271 &rs6000_reg_names[ 9][0], /* r9 */ \
2272 &rs6000_reg_names[10][0], /* r10 */ \
2273 &rs6000_reg_names[11][0], /* r11 */ \
2274 &rs6000_reg_names[12][0], /* r12 */ \
2275 &rs6000_reg_names[13][0], /* r13 */ \
2276 &rs6000_reg_names[14][0], /* r14 */ \
2277 &rs6000_reg_names[15][0], /* r15 */ \
2278 &rs6000_reg_names[16][0], /* r16 */ \
2279 &rs6000_reg_names[17][0], /* r17 */ \
2280 &rs6000_reg_names[18][0], /* r18 */ \
2281 &rs6000_reg_names[19][0], /* r19 */ \
2282 &rs6000_reg_names[20][0], /* r20 */ \
2283 &rs6000_reg_names[21][0], /* r21 */ \
2284 &rs6000_reg_names[22][0], /* r22 */ \
2285 &rs6000_reg_names[23][0], /* r23 */ \
2286 &rs6000_reg_names[24][0], /* r24 */ \
2287 &rs6000_reg_names[25][0], /* r25 */ \
2288 &rs6000_reg_names[26][0], /* r26 */ \
2289 &rs6000_reg_names[27][0], /* r27 */ \
2290 &rs6000_reg_names[28][0], /* r28 */ \
2291 &rs6000_reg_names[29][0], /* r29 */ \
2292 &rs6000_reg_names[30][0], /* r30 */ \
2293 &rs6000_reg_names[31][0], /* r31 */ \
2295 &rs6000_reg_names[32][0], /* fr0 */ \
2296 &rs6000_reg_names[33][0], /* fr1 */ \
2297 &rs6000_reg_names[34][0], /* fr2 */ \
2298 &rs6000_reg_names[35][0], /* fr3 */ \
2299 &rs6000_reg_names[36][0], /* fr4 */ \
2300 &rs6000_reg_names[37][0], /* fr5 */ \
2301 &rs6000_reg_names[38][0], /* fr6 */ \
2302 &rs6000_reg_names[39][0], /* fr7 */ \
2303 &rs6000_reg_names[40][0], /* fr8 */ \
2304 &rs6000_reg_names[41][0], /* fr9 */ \
2305 &rs6000_reg_names[42][0], /* fr10 */ \
2306 &rs6000_reg_names[43][0], /* fr11 */ \
2307 &rs6000_reg_names[44][0], /* fr12 */ \
2308 &rs6000_reg_names[45][0], /* fr13 */ \
2309 &rs6000_reg_names[46][0], /* fr14 */ \
2310 &rs6000_reg_names[47][0], /* fr15 */ \
2311 &rs6000_reg_names[48][0], /* fr16 */ \
2312 &rs6000_reg_names[49][0], /* fr17 */ \
2313 &rs6000_reg_names[50][0], /* fr18 */ \
2314 &rs6000_reg_names[51][0], /* fr19 */ \
2315 &rs6000_reg_names[52][0], /* fr20 */ \
2316 &rs6000_reg_names[53][0], /* fr21 */ \
2317 &rs6000_reg_names[54][0], /* fr22 */ \
2318 &rs6000_reg_names[55][0], /* fr23 */ \
2319 &rs6000_reg_names[56][0], /* fr24 */ \
2320 &rs6000_reg_names[57][0], /* fr25 */ \
2321 &rs6000_reg_names[58][0], /* fr26 */ \
2322 &rs6000_reg_names[59][0], /* fr27 */ \
2323 &rs6000_reg_names[60][0], /* fr28 */ \
2324 &rs6000_reg_names[61][0], /* fr29 */ \
2325 &rs6000_reg_names[62][0], /* fr30 */ \
2326 &rs6000_reg_names[63][0], /* fr31 */ \
2328 &rs6000_reg_names[64][0], /* was mq */ \
2329 &rs6000_reg_names[65][0], /* lr */ \
2330 &rs6000_reg_names[66][0], /* ctr */ \
2331 &rs6000_reg_names[67][0], /* ap */ \
2333 &rs6000_reg_names[68][0], /* cr0 */ \
2334 &rs6000_reg_names[69][0], /* cr1 */ \
2335 &rs6000_reg_names[70][0], /* cr2 */ \
2336 &rs6000_reg_names[71][0], /* cr3 */ \
2337 &rs6000_reg_names[72][0], /* cr4 */ \
2338 &rs6000_reg_names[73][0], /* cr5 */ \
2339 &rs6000_reg_names[74][0], /* cr6 */ \
2340 &rs6000_reg_names[75][0], /* cr7 */ \
2342 &rs6000_reg_names[76][0], /* ca */ \
2344 &rs6000_reg_names[77][0], /* v0 */ \
2345 &rs6000_reg_names[78][0], /* v1 */ \
2346 &rs6000_reg_names[79][0], /* v2 */ \
2347 &rs6000_reg_names[80][0], /* v3 */ \
2348 &rs6000_reg_names[81][0], /* v4 */ \
2349 &rs6000_reg_names[82][0], /* v5 */ \
2350 &rs6000_reg_names[83][0], /* v6 */ \
2351 &rs6000_reg_names[84][0], /* v7 */ \
2352 &rs6000_reg_names[85][0], /* v8 */ \
2353 &rs6000_reg_names[86][0], /* v9 */ \
2354 &rs6000_reg_names[87][0], /* v10 */ \
2355 &rs6000_reg_names[88][0], /* v11 */ \
2356 &rs6000_reg_names[89][0], /* v12 */ \
2357 &rs6000_reg_names[90][0], /* v13 */ \
2358 &rs6000_reg_names[91][0], /* v14 */ \
2359 &rs6000_reg_names[92][0], /* v15 */ \
2360 &rs6000_reg_names[93][0], /* v16 */ \
2361 &rs6000_reg_names[94][0], /* v17 */ \
2362 &rs6000_reg_names[95][0], /* v18 */ \
2363 &rs6000_reg_names[96][0], /* v19 */ \
2364 &rs6000_reg_names[97][0], /* v20 */ \
2365 &rs6000_reg_names[98][0], /* v21 */ \
2366 &rs6000_reg_names[99][0], /* v22 */ \
2367 &rs6000_reg_names[100][0], /* v23 */ \
2368 &rs6000_reg_names[101][0], /* v24 */ \
2369 &rs6000_reg_names[102][0], /* v25 */ \
2370 &rs6000_reg_names[103][0], /* v26 */ \
2371 &rs6000_reg_names[104][0], /* v27 */ \
2372 &rs6000_reg_names[105][0], /* v28 */ \
2373 &rs6000_reg_names[106][0], /* v29 */ \
2374 &rs6000_reg_names[107][0], /* v30 */ \
2375 &rs6000_reg_names[108][0], /* v31 */ \
2376 &rs6000_reg_names[109][0], /* vrsave */ \
2377 &rs6000_reg_names[110][0], /* vscr */ \
2378 &rs6000_reg_names[111][0], /* spe_acc */ \
2379 &rs6000_reg_names[112][0], /* spefscr */ \
2380 &rs6000_reg_names[113][0], /* sfp */ \
2381 &rs6000_reg_names[114][0], /* tfhar */ \
2382 &rs6000_reg_names[115][0], /* tfiar */ \
2383 &rs6000_reg_names[116][0], /* texasr */ \
2385 &rs6000_reg_names[117][0], /* SPE rh0. */ \
2386 &rs6000_reg_names[118][0], /* SPE rh1. */ \
2387 &rs6000_reg_names[119][0], /* SPE rh2. */ \
2388 &rs6000_reg_names[120][0], /* SPE rh3. */ \
2389 &rs6000_reg_names[121][0], /* SPE rh4. */ \
2390 &rs6000_reg_names[122][0], /* SPE rh5. */ \
2391 &rs6000_reg_names[123][0], /* SPE rh6. */ \
2392 &rs6000_reg_names[124][0], /* SPE rh7. */ \
2393 &rs6000_reg_names[125][0], /* SPE rh8. */ \
2394 &rs6000_reg_names[126][0], /* SPE rh9. */ \
2395 &rs6000_reg_names[127][0], /* SPE rh10. */ \
2396 &rs6000_reg_names[128][0], /* SPE rh11. */ \
2397 &rs6000_reg_names[129][0], /* SPE rh12. */ \
2398 &rs6000_reg_names[130][0], /* SPE rh13. */ \
2399 &rs6000_reg_names[131][0], /* SPE rh14. */ \
2400 &rs6000_reg_names[132][0], /* SPE rh15. */ \
2401 &rs6000_reg_names[133][0], /* SPE rh16. */ \
2402 &rs6000_reg_names[134][0], /* SPE rh17. */ \
2403 &rs6000_reg_names[135][0], /* SPE rh18. */ \
2404 &rs6000_reg_names[136][0], /* SPE rh19. */ \
2405 &rs6000_reg_names[137][0], /* SPE rh20. */ \
2406 &rs6000_reg_names[138][0], /* SPE rh21. */ \
2407 &rs6000_reg_names[139][0], /* SPE rh22. */ \
2408 &rs6000_reg_names[140][0], /* SPE rh22. */ \
2409 &rs6000_reg_names[141][0], /* SPE rh24. */ \
2410 &rs6000_reg_names[142][0], /* SPE rh25. */ \
2411 &rs6000_reg_names[143][0], /* SPE rh26. */ \
2412 &rs6000_reg_names[144][0], /* SPE rh27. */ \
2413 &rs6000_reg_names[145][0], /* SPE rh28. */ \
2414 &rs6000_reg_names[146][0], /* SPE rh29. */ \
2415 &rs6000_reg_names[147][0], /* SPE rh30. */ \
2416 &rs6000_reg_names[148][0], /* SPE rh31. */ \
2419 /* Table of additional register names to use in user input. */
2421 #define ADDITIONAL_REGISTER_NAMES \
2422 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2423 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2424 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2425 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2426 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2427 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2428 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2429 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2430 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2431 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2432 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2433 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2434 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2435 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2436 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2437 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2438 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2439 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2440 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2441 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2442 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2443 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2444 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2445 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2446 {"vrsave", 109}, {"vscr", 110}, \
2447 {"spe_acc", 111}, {"spefscr", 112}, \
2448 /* no additional names for: lr, ctr, ap */ \
2449 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2450 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2451 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2452 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2454 /* VSX registers overlaid on top of FR, Altivec registers */ \
2455 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2456 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2457 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2458 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2459 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2460 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2461 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2462 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2463 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2464 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2465 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2466 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2467 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2468 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2469 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2470 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
2471 /* Transactional Memory Facility (HTM) Registers. */ \
2472 {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
2473 /* SPE high registers. */ \
2474 {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \
2475 {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \
2476 {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \
2477 {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \
2478 {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \
2479 {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \
2480 {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \
2481 {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \
2484 /* This is how to output an element of a case-vector that is relative. */
2486 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2487 do { char buf[100]; \
2488 fputs ("\t.long ", FILE); \
2489 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2490 assemble_name (FILE, buf); \
2492 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2493 assemble_name (FILE, buf); \
2494 putc ('\n', FILE); \
2497 /* This is how to output an assembler line
2498 that says to advance the location counter
2499 to a multiple of 2**LOG bytes. */
2501 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2503 fprintf (FILE, "\t.align %d\n", (LOG))
2505 /* How to align the given loop. */
2506 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2508 /* Alignment guaranteed by __builtin_malloc. */
2509 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2510 However, specifying the stronger guarantee currently leads to
2511 a regression in SPEC CPU2006 437.leslie3d. The stronger
2512 guarantee should be implemented here once that's fixed. */
2513 #define MALLOC_ABI_ALIGNMENT (64)
2515 /* Pick up the return address upon entry to a procedure. Used for
2516 dwarf2 unwind information. This also enables the table driven
2519 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2520 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2522 /* Describe how we implement __builtin_eh_return. */
2523 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2524 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2526 /* Print operand X (an rtx) in assembler syntax to file FILE.
2527 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2528 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2530 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2532 /* Define which CODE values are valid. */
2534 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2536 /* Print a memory address as an operand to reference that memory location. */
2538 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2540 /* For switching between functions with different target attributes. */
2541 #define SWITCHABLE_TARGET 1
2543 /* uncomment for disabling the corresponding default options */
2544 /* #define MACHINE_no_sched_interblock */
2545 /* #define MACHINE_no_sched_speculative */
2546 /* #define MACHINE_no_sched_speculative_load */
2548 /* General flags. */
2549 extern int frame_pointer_needed
;
2551 /* Classification of the builtin functions as to which switches enable the
2552 builtin, and what attributes it should have. We used to use the target
2553 flags macros, but we've run out of bits, so we now map the options into new
2554 settings used here. */
2556 /* Builtin attributes. */
2557 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2558 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2559 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2560 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2561 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2562 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2563 #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */
2564 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2565 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2567 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2568 #define RS6000_BTC_CONST 0x00000100 /* uses no global state. */
2569 #define RS6000_BTC_PURE 0x00000200 /* reads global state/mem. */
2570 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2571 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2573 /* Miscellaneous information. */
2574 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
2575 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
2576 #define RS6000_BTC_OVERLOADED 0x04000000 /* function is overloaded. */
2577 #define RS6000_BTC_32BIT 0x08000000 /* function references SPRs. */
2578 #define RS6000_BTC_64BIT 0x10000000 /* function references SPRs. */
2579 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
2581 /* Convenience macros to document the instruction type. */
2582 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2583 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2585 /* Builtin targets. For now, we reuse the masks for those options that are in
2586 target flags, and pick three random bits for SPE, paired and ldbl128 which
2587 aren't in target_flags. */
2588 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2589 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2590 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2591 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2592 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2593 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2594 #define RS6000_BTM_SPE MASK_STRING /* E500 */
2595 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
2596 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2597 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2598 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2599 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2600 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2601 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2602 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2603 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2604 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2606 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2608 | RS6000_BTM_P8_VECTOR \
2609 | RS6000_BTM_CRYPTO \
2612 | RS6000_BTM_FRSQRTE \
2613 | RS6000_BTM_FRSQRTES \
2615 | RS6000_BTM_POPCNTD \
2618 | RS6000_BTM_HARD_FLOAT \
2619 | RS6000_BTM_LDBL128)
2621 /* Define builtin enum index. */
2623 #undef RS6000_BUILTIN_1
2624 #undef RS6000_BUILTIN_2
2625 #undef RS6000_BUILTIN_3
2626 #undef RS6000_BUILTIN_A
2627 #undef RS6000_BUILTIN_D
2628 #undef RS6000_BUILTIN_E
2629 #undef RS6000_BUILTIN_H
2630 #undef RS6000_BUILTIN_P
2631 #undef RS6000_BUILTIN_Q
2632 #undef RS6000_BUILTIN_S
2633 #undef RS6000_BUILTIN_X
2635 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2636 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2637 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2638 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2639 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2640 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2641 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2642 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2643 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2644 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2645 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2647 enum rs6000_builtins
2649 #include "rs6000-builtin.def"
2651 RS6000_BUILTIN_COUNT
2654 #undef RS6000_BUILTIN_1
2655 #undef RS6000_BUILTIN_2
2656 #undef RS6000_BUILTIN_3
2657 #undef RS6000_BUILTIN_A
2658 #undef RS6000_BUILTIN_D
2659 #undef RS6000_BUILTIN_E
2660 #undef RS6000_BUILTIN_H
2661 #undef RS6000_BUILTIN_P
2662 #undef RS6000_BUILTIN_Q
2663 #undef RS6000_BUILTIN_S
2664 #undef RS6000_BUILTIN_X
2666 enum rs6000_builtin_type_index
2668 RS6000_BTI_NOT_OPAQUE
,
2669 RS6000_BTI_opaque_V2SI
,
2670 RS6000_BTI_opaque_V2SF
,
2671 RS6000_BTI_opaque_p_V2SI
,
2672 RS6000_BTI_opaque_V4SI
,
2683 RS6000_BTI_unsigned_V16QI
,
2684 RS6000_BTI_unsigned_V1TI
,
2685 RS6000_BTI_unsigned_V8HI
,
2686 RS6000_BTI_unsigned_V4SI
,
2687 RS6000_BTI_unsigned_V2DI
,
2688 RS6000_BTI_bool_char
, /* __bool char */
2689 RS6000_BTI_bool_short
, /* __bool short */
2690 RS6000_BTI_bool_int
, /* __bool int */
2691 RS6000_BTI_bool_long
, /* __bool long */
2692 RS6000_BTI_pixel
, /* __pixel */
2693 RS6000_BTI_bool_V16QI
, /* __vector __bool char */
2694 RS6000_BTI_bool_V8HI
, /* __vector __bool short */
2695 RS6000_BTI_bool_V4SI
, /* __vector __bool int */
2696 RS6000_BTI_bool_V2DI
, /* __vector __bool long */
2697 RS6000_BTI_pixel_V8HI
, /* __vector __pixel */
2698 RS6000_BTI_long
, /* long_integer_type_node */
2699 RS6000_BTI_unsigned_long
, /* long_unsigned_type_node */
2700 RS6000_BTI_long_long
, /* long_long_integer_type_node */
2701 RS6000_BTI_unsigned_long_long
, /* long_long_unsigned_type_node */
2702 RS6000_BTI_INTQI
, /* intQI_type_node */
2703 RS6000_BTI_UINTQI
, /* unsigned_intQI_type_node */
2704 RS6000_BTI_INTHI
, /* intHI_type_node */
2705 RS6000_BTI_UINTHI
, /* unsigned_intHI_type_node */
2706 RS6000_BTI_INTSI
, /* intSI_type_node */
2707 RS6000_BTI_UINTSI
, /* unsigned_intSI_type_node */
2708 RS6000_BTI_INTDI
, /* intDI_type_node */
2709 RS6000_BTI_UINTDI
, /* unsigned_intDI_type_node */
2710 RS6000_BTI_INTTI
, /* intTI_type_node */
2711 RS6000_BTI_UINTTI
, /* unsigned_intTI_type_node */
2712 RS6000_BTI_float
, /* float_type_node */
2713 RS6000_BTI_double
, /* double_type_node */
2714 RS6000_BTI_long_double
, /* long_double_type_node */
2715 RS6000_BTI_dfloat64
, /* dfloat64_type_node */
2716 RS6000_BTI_dfloat128
, /* dfloat128_type_node */
2717 RS6000_BTI_void
, /* void_type_node */
2722 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2723 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2724 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2725 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2726 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2727 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2728 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2729 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2730 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2731 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2732 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2733 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2734 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2735 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2736 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2737 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2738 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2739 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2740 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2741 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2742 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2743 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2744 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
2745 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2746 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2747 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2748 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2749 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2750 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2752 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2753 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2754 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2755 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2756 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2757 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2758 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2759 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2760 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2761 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2762 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2763 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2764 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2765 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2766 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2767 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2768 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2769 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2770 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2771 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2773 extern GTY(()) tree rs6000_builtin_types
[RS6000_BTI_MAX
];
2774 extern GTY(()) tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
2776 #define TARGET_SUPPORTS_WIDE_INT 1