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* config/sh/sh.c (sh_scalar_mode_supported_p): New function.
[official-gcc.git] / gcc / config / sh / sh.h
blob7a1547932e516706a2c95752659c04dc3e412b3d
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #ifndef GCC_SH_H
24 #define GCC_SH_H
25
26 #include "config/vxworks-dummy.h"
27
28 #define TARGET_VERSION \
29 fputs (" (Hitachi SH)", stderr);
30
31 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
32 include it here, because bconfig.h is also included by gencodes.c . */
33 /* ??? No longer true. */
34 extern int code_for_indirect_jump_scratch;
35
36 #define TARGET_CPU_CPP_BUILTINS() \
37 do { \
38 builtin_define ("__sh__"); \
39 builtin_assert ("cpu=sh"); \
40 builtin_assert ("machine=sh"); \
41 switch ((int) sh_cpu) \
42 { \
43 case PROCESSOR_SH1: \
44 builtin_define ("__sh1__"); \
45 break; \
46 case PROCESSOR_SH2: \
47 builtin_define ("__sh2__"); \
48 break; \
49 case PROCESSOR_SH2E: \
50 builtin_define ("__SH2E__"); \
51 break; \
52 case PROCESSOR_SH2A: \
53 builtin_define ("__SH2A__"); \
54 builtin_define (TARGET_SH2A_DOUBLE \
55 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
56 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
57 : "__SH2A_NOFPU__"); \
58 break; \
59 case PROCESSOR_SH3: \
60 builtin_define ("__sh3__"); \
61 builtin_define ("__SH3__"); \
62 if (TARGET_HARD_SH4) \
63 builtin_define ("__SH4_NOFPU__"); \
64 break; \
65 case PROCESSOR_SH3E: \
66 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
67 break; \
68 case PROCESSOR_SH4: \
69 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
70 break; \
71 case PROCESSOR_SH4A: \
72 builtin_define ("__SH4A__"); \
73 builtin_define (TARGET_SH4 \
74 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
75 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
76 : "__SH4_NOFPU__"); \
77 break; \
78 case PROCESSOR_SH5: \
79 { \
80 builtin_define_with_value ("__SH5__", \
81 TARGET_SHMEDIA64 ? "64" : "32", 0); \
82 builtin_define_with_value ("__SHMEDIA__", \
83 TARGET_SHMEDIA ? "1" : "0", 0); \
84 if (! TARGET_FPU_DOUBLE) \
85 builtin_define ("__SH4_NOFPU__"); \
86 } \
87 } \
88 if (TARGET_FPU_ANY) \
89 builtin_define ("__SH_FPU_ANY__"); \
90 if (TARGET_FPU_DOUBLE) \
91 builtin_define ("__SH_FPU_DOUBLE__"); \
92 if (TARGET_HITACHI) \
93 builtin_define ("__HITACHI__"); \
94 builtin_define (TARGET_LITTLE_ENDIAN \
95 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
96 } while (0)
97
98 /* We can not debug without a frame pointer. */
99 /* #define CAN_DEBUG_WITHOUT_FP */
100
101 #define CONDITIONAL_REGISTER_USAGE do \
102 { \
103 int regno; \
104 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
105 if (! VALID_REGISTER_P (regno)) \
106 fixed_regs[regno] = call_used_regs[regno] = 1; \
107 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
108 if (TARGET_SH5) \
109 { \
110 call_used_regs[FIRST_GENERAL_REG + 8] \
111 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
112 call_really_used_regs[FIRST_GENERAL_REG + 8] \
113 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
114 } \
115 if (TARGET_SHMEDIA) \
116 { \
117 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
118 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
119 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
120 } \
121 if (flag_pic) \
122 { \
123 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
125 } \
126 /* Renesas saves and restores mac registers on call. */ \
127 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
128 { \
129 call_really_used_regs[MACH_REG] = 0; \
130 call_really_used_regs[MACL_REG] = 0; \
131 } \
132 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
133 regno <= LAST_FP_REG; regno += 2) \
134 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
135 if (TARGET_SHMEDIA) \
136 { \
137 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
138 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
139 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
140 } \
141 else \
142 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
143 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
144 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
145 } while (0)
146 \f
147 /* Nonzero if this is an ELF target - compile time only */
148 #define TARGET_ELF 0
149
150 /* Nonzero if we should generate code using type 2E insns. */
151 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
152
153 /* Nonzero if we should generate code using type 2A insns. */
154 #define TARGET_SH2A TARGET_HARD_SH2A
155 /* Nonzero if we should generate code using type 2A SF insns. */
156 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
157 /* Nonzero if we should generate code using type 2A DF insns. */
158 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
159
160 /* Nonzero if we should generate code using type 3E insns. */
161 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
162
163 /* Nonzero if the cache line size is 32. */
164 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
165
166 /* Nonzero if we schedule for a superscalar implementation. */
167 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
168
169 /* Nonzero if the target has separate instruction and data caches. */
170 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
171
172 /* Nonzero if a double-precision FPU is available. */
173 #define TARGET_FPU_DOUBLE \
174 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
175
176 /* Nonzero if an FPU is available. */
177 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
178
179 /* Nonzero if we should generate code using type 4 insns. */
180 #undef TARGET_SH4
181 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
182
183 /* Nonzero if we're generating code for the common subset of
184 instructions present on both SH4a and SH4al-dsp. */
185 #define TARGET_SH4A_ARCH TARGET_SH4A
186
187 /* Nonzero if we're generating code for SH4a, unless the use of the
188 FPU is disabled (which makes it compatible with SH4al-dsp). */
189 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
190
191 /* Nonzero if we should generate code using the SHcompact instruction
192 set and 32-bit ABI. */
193 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
194
195 /* Nonzero if we should generate code using the SHmedia instruction
196 set and ABI. */
197 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
198
199 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
200 ABI. */
201 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
202
203 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
204 ABI. */
205 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
206
207 /* Nonzero if we should generate code using SHmedia FPU instructions. */
208 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
209
210 /* This is not used by the SH2E calling convention */
211 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
212 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
213 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
214
215 #ifndef TARGET_CPU_DEFAULT
216 #define TARGET_CPU_DEFAULT SELECT_SH1
217 #define SUPPORT_SH1 1
218 #define SUPPORT_SH2E 1
219 #define SUPPORT_SH4 1
220 #define SUPPORT_SH4_SINGLE 1
221 #define SUPPORT_SH2A 1
222 #define SUPPORT_SH2A_SINGLE 1
223 #endif
224
225 #define TARGET_DIVIDE_INV \
226 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
227 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
228 || sh_div_strategy == SH_DIV_INV_CALL \
229 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
230 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
231 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
232 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
233 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
234 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
235 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
236 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
237 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
238 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
239 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
240 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
241
242 #define SELECT_SH1 (MASK_SH1)
243 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
244 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
245 | MASK_FPU_SINGLE)
246 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
247 | MASK_HARD_SH2A_DOUBLE \
248 | MASK_SH2 | MASK_SH1)
249 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
250 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
251 | MASK_SH1 | MASK_FPU_SINGLE)
252 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
253 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
254 | MASK_SH2 | MASK_SH1)
255 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
256 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
257 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
258 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
259 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
260 | SELECT_SH3)
261 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
262 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
263 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
264 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
265 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
266 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
267 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
268 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
269 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
270 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
271 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
272
273 #if SUPPORT_SH1
274 #define SUPPORT_SH2 1
275 #endif
276 #if SUPPORT_SH2
277 #define SUPPORT_SH3 1
278 #define SUPPORT_SH2A_NOFPU 1
279 #endif
280 #if SUPPORT_SH3
281 #define SUPPORT_SH4_NOFPU 1
282 #endif
283 #if SUPPORT_SH4_NOFPU
284 #define SUPPORT_SH4A_NOFPU 1
285 #define SUPPORT_SH4AL 1
286 #endif
287
288 #if SUPPORT_SH2E
289 #define SUPPORT_SH3E 1
290 #define SUPPORT_SH2A_SINGLE_ONLY 1
291 #endif
292 #if SUPPORT_SH3E
293 #define SUPPORT_SH4_SINGLE_ONLY 1
294 #endif
295 #if SUPPORT_SH4_SINGLE_ONLY
296 #define SUPPORT_SH4A_SINGLE_ONLY 1
297 #endif
298
299 #if SUPPORT_SH4
300 #define SUPPORT_SH4A 1
301 #endif
302
303 #if SUPPORT_SH4_SINGLE
304 #define SUPPORT_SH4A_SINGLE 1
305 #endif
306
307 #if SUPPORT_SH5_COMPAT
308 #define SUPPORT_SH5_32MEDIA 1
309 #endif
310
311 #if SUPPORT_SH5_COMPACT_NOFPU
312 #define SUPPORT_SH5_32MEDIA_NOFPU 1
313 #endif
314
315 #define SUPPORT_ANY_SH5_32MEDIA \
316 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
317 #define SUPPORT_ANY_SH5_64MEDIA \
318 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
319 #define SUPPORT_ANY_SH5 \
320 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
321
322 /* Reset all target-selection flags. */
323 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
324 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
325 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
326
327 /* This defaults us to big-endian. */
328 #ifndef TARGET_ENDIAN_DEFAULT
329 #define TARGET_ENDIAN_DEFAULT 0
330 #endif
331
332 #ifndef TARGET_OPT_DEFAULT
333 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
334 #endif
335
336 #define TARGET_DEFAULT \
337 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
338
339 #ifndef SH_MULTILIB_CPU_DEFAULT
340 #define SH_MULTILIB_CPU_DEFAULT "m1"
341 #endif
342
343 #if TARGET_ENDIAN_DEFAULT
344 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
345 #else
346 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
347 #endif
348
349 #define CPP_SPEC " %(subtarget_cpp_spec) "
350
351 #ifndef SUBTARGET_CPP_SPEC
352 #define SUBTARGET_CPP_SPEC ""
353 #endif
354
355 #ifndef SUBTARGET_EXTRA_SPECS
356 #define SUBTARGET_EXTRA_SPECS
357 #endif
358
359 #define EXTRA_SPECS \
360 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
361 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
362 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
363 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
364 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
365 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
366 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
367 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
368 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
369 SUBTARGET_EXTRA_SPECS
370
371 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
372 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
373 #else
374 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
375 #endif
376
377 #define SH_ASM_SPEC \
378 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
379 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
380 %{m2a:--isa=sh2a} \
381 %{m2a-single:--isa=sh2a} \
382 %{m2a-single-only:--isa=sh2a} \
383 %{m2a-nofpu:--isa=sh2a-nofpu} \
384 %{m5-compact*:--isa=SHcompact} \
385 %{m5-32media*:--isa=SHmedia --abi=32} \
386 %{m5-64media*:--isa=SHmedia --abi=64} \
387 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
388
389 #define ASM_SPEC SH_ASM_SPEC
390
391 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
392 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
393 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
394 #else
395 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
396 #endif
397 #endif
398
399 #if STRICT_NOFPU == 1
400 /* Strict nofpu means that the compiler should tell the assembler
401 to reject FPU instructions. E.g. from ASM inserts. */
402 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
403 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
404 #else
405 /* If there were an -isa option for sh5-nofpu then it would also go here. */
406 #define SUBTARGET_ASM_ISA_SPEC \
407 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
408 #endif
409 #else /* ! STRICT_NOFPU */
410 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
411 #endif
412
413 #ifndef SUBTARGET_ASM_SPEC
414 #define SUBTARGET_ASM_SPEC ""
415 #endif
416
417 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
418 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
419 #else
420 #define LINK_EMUL_PREFIX "sh%{ml:l}"
421 #endif
422
423 #if TARGET_CPU_DEFAULT & MASK_SH5
424 #if TARGET_CPU_DEFAULT & MASK_SH_E
425 #define LINK_DEFAULT_CPU_EMUL "32"
426 #if TARGET_CPU_DEFAULT & MASK_SH1
427 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
428 #else
429 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
430 #endif /* MASK_SH1 */
431 #else /* !MASK_SH_E */
432 #define LINK_DEFAULT_CPU_EMUL "64"
433 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
434 #endif /* MASK_SH_E */
435 #define ASM_ISA_DEFAULT_SPEC \
436 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
437 #else /* !MASK_SH5 */
438 #define LINK_DEFAULT_CPU_EMUL ""
439 #define ASM_ISA_DEFAULT_SPEC ""
440 #endif /* MASK_SH5 */
441
442 #define SUBTARGET_LINK_EMUL_SUFFIX ""
443 #define SUBTARGET_LINK_SPEC ""
444
445 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
446 so that we can undo the damage without code replication. */
447 #define LINK_SPEC SH_LINK_SPEC
448
449 #define SH_LINK_SPEC "\
450 -m %(link_emul_prefix)\
451 %{m5-compact*|m5-32media*:32}\
452 %{m5-64media*:64}\
453 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
454 %(subtarget_link_emul_suffix) \
455 %{mrelax:-relax} %(subtarget_link_spec)"
456
457 #ifndef SH_DIV_STR_FOR_SIZE
458 #define SH_DIV_STR_FOR_SIZE "call"
459 #endif
460
461 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
462 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
463 do { \
464 if (LEVEL) \
465 { \
466 flag_omit_frame_pointer = -1; \
467 if (! SIZE) \
468 sh_div_str = "inv:minlat"; \
469 } \
470 if (SIZE) \
471 { \
472 target_flags |= MASK_SMALLCODE; \
473 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
474 } \
475 else \
476 { \
477 TARGET_CBRANCHDI4 = 1; \
478 TARGET_EXPAND_CBRANCHDI4 = 1; \
479 } \
480 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
481 haven't been parsed yet, hence we'd read only the default. \
482 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
483 it's OK to always set flag_branch_target_load_optimize. */ \
484 if (LEVEL > 1) \
485 { \
486 flag_branch_target_load_optimize = 1; \
487 if (! (SIZE)) \
488 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
489 } \
490 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
491 here, so leave it to OVERRIDE_OPTIONS to set \
492 flag_finite_math_only. We set it to 2 here so we know if the user \
493 explicitly requested this to be on or off. */ \
494 flag_finite_math_only = 2; \
495 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
496 the user explicitly requested this to be on or off. */ \
497 if (flag_schedule_insns > 0) \
498 flag_schedule_insns = 2; \
499 \
500 set_param_value ("simultaneous-prefetches", 2); \
501 } while (0)
502
503 #define ASSEMBLER_DIALECT assembler_dialect
504
505 extern int assembler_dialect;
506
507 enum sh_divide_strategy_e {
508 /* SH5 strategies. */
509 SH_DIV_CALL,
510 SH_DIV_CALL2,
511 SH_DIV_FP, /* We could do this also for SH4. */
512 SH_DIV_INV,
513 SH_DIV_INV_MINLAT,
514 SH_DIV_INV20U,
515 SH_DIV_INV20L,
516 SH_DIV_INV_CALL,
517 SH_DIV_INV_CALL2,
518 SH_DIV_INV_FP,
519 /* SH1 .. SH4 strategies. Because of the small number of registers
520 available, the compiler uses knowledge of the actual set of registers
521 being clobbered by the different functions called. */
522 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
523 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
524 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
525 SH_DIV_INTRINSIC
526 };
527
528 extern enum sh_divide_strategy_e sh_div_strategy;
529
530 #ifndef SH_DIV_STRATEGY_DEFAULT
531 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
532 #endif
533
534 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
535
536 #define OVERRIDE_OPTIONS \
537 do { \
538 int regno; \
539 \
540 SUBTARGET_OVERRIDE_OPTIONS; \
541 if (flag_finite_math_only == 2) \
542 flag_finite_math_only \
543 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
544 if (TARGET_SH2E && !flag_finite_math_only) \
545 target_flags |= MASK_IEEE; \
546 sh_cpu = CPU_SH1; \
547 assembler_dialect = 0; \
548 if (TARGET_SH2) \
549 sh_cpu = CPU_SH2; \
550 if (TARGET_SH2E) \
551 sh_cpu = CPU_SH2E; \
552 if (TARGET_SH2A) \
553 { \
554 sh_cpu = CPU_SH2A; \
555 if (TARGET_SH2A_DOUBLE) \
556 target_flags |= MASK_FMOVD; \
557 } \
558 if (TARGET_SH3) \
559 sh_cpu = CPU_SH3; \
560 if (TARGET_SH3E) \
561 sh_cpu = CPU_SH3E; \
562 if (TARGET_SH4) \
563 { \
564 assembler_dialect = 1; \
565 sh_cpu = CPU_SH4; \
566 } \
567 if (TARGET_SH4A_ARCH) \
568 { \
569 assembler_dialect = 1; \
570 sh_cpu = CPU_SH4A; \
571 } \
572 if (TARGET_SH5) \
573 { \
574 sh_cpu = CPU_SH5; \
575 target_flags |= MASK_ALIGN_DOUBLE; \
576 if (TARGET_SHMEDIA_FPU) \
577 target_flags |= MASK_FMOVD; \
578 if (TARGET_SHMEDIA) \
579 { \
580 /* There are no delay slots on SHmedia. */ \
581 flag_delayed_branch = 0; \
582 /* Relaxation isn't yet supported for SHmedia */ \
583 target_flags &= ~MASK_RELAX; \
584 /* After reload, if conversion does little good but can cause \
585 ICEs: \
586 - find_if_block doesn't do anything for SH because we don't\
587 have conditional execution patterns. (We use conditional\
588 move patterns, which are handled differently, and only \
589 before reload). \
590 - find_cond_trap doesn't do anything for the SH because we \
591 don't have conditional traps. \
592 - find_if_case_1 uses redirect_edge_and_branch_force in \
593 the only path that does an optimization, and this causes \
594 an ICE when branch targets are in registers. \
595 - find_if_case_2 doesn't do anything for the SHmedia after \
596 reload except when it can redirect a tablejump - and \
597 that's rather rare. */ \
598 flag_if_conversion2 = 0; \
599 if (! strcmp (sh_div_str, "call")) \
600 sh_div_strategy = SH_DIV_CALL; \
601 else if (! strcmp (sh_div_str, "call2")) \
602 sh_div_strategy = SH_DIV_CALL2; \
603 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
604 sh_div_strategy = SH_DIV_FP; \
605 else if (! strcmp (sh_div_str, "inv")) \
606 sh_div_strategy = SH_DIV_INV; \
607 else if (! strcmp (sh_div_str, "inv:minlat")) \
608 sh_div_strategy = SH_DIV_INV_MINLAT; \
609 else if (! strcmp (sh_div_str, "inv20u")) \
610 sh_div_strategy = SH_DIV_INV20U; \
611 else if (! strcmp (sh_div_str, "inv20l")) \
612 sh_div_strategy = SH_DIV_INV20L; \
613 else if (! strcmp (sh_div_str, "inv:call2")) \
614 sh_div_strategy = SH_DIV_INV_CALL2; \
615 else if (! strcmp (sh_div_str, "inv:call")) \
616 sh_div_strategy = SH_DIV_INV_CALL; \
617 else if (! strcmp (sh_div_str, "inv:fp")) \
618 { \
619 if (TARGET_FPU_ANY) \
620 sh_div_strategy = SH_DIV_INV_FP; \
621 else \
622 sh_div_strategy = SH_DIV_INV; \
623 } \
624 TARGET_CBRANCHDI4 = 0; \
625 } \
626 } \
627 else \
628 { \
629 /* Only the sh64-elf assembler fully supports .quad properly. */\
630 targetm.asm_out.aligned_op.di = NULL; \
631 targetm.asm_out.unaligned_op.di = NULL; \
632 } \
633 if (TARGET_SH1) \
634 { \
635 if (! strcmp (sh_div_str, "call-div1")) \
636 sh_div_strategy = SH_DIV_CALL_DIV1; \
637 else if (! strcmp (sh_div_str, "call-fp") \
638 && (TARGET_FPU_DOUBLE \
639 || (TARGET_HARD_SH4 && TARGET_SH2E) \
640 || (TARGET_SHCOMPACT && TARGET_FPU_ANY))) \
641 sh_div_strategy = SH_DIV_CALL_FP; \
642 else if (! strcmp (sh_div_str, "call-table") && TARGET_SH2) \
643 sh_div_strategy = SH_DIV_CALL_TABLE; \
644 else \
645 /* Pick one that makes most sense for the target in general. \
646 It is not much good to use different functions depending \
647 on -Os, since then we'll end up with two different functions \
648 when some of the code is compiled for size, and some for \
649 speed. */ \
650 \
651 /* SH4 tends to emphasize speed. */ \
652 if (TARGET_HARD_SH4) \
653 sh_div_strategy = SH_DIV_CALL_TABLE; \
654 /* These have their own way of doing things. */ \
655 else if (TARGET_SH2A) \
656 sh_div_strategy = SH_DIV_INTRINSIC; \
657 /* ??? Should we use the integer SHmedia function instead? */ \
658 else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
659 sh_div_strategy = SH_DIV_CALL_FP; \
660 /* SH1 .. SH3 cores often go into small-footprint systems, so \
661 default to the smallest implementation available. */ \
662 else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
663 sh_div_strategy = SH_DIV_CALL_TABLE; \
664 else \
665 sh_div_strategy = SH_DIV_CALL_DIV1; \
666 } \
667 if (!TARGET_SH1) \
668 TARGET_PRETEND_CMOVE = 0; \
669 if (sh_divsi3_libfunc[0]) \
670 ; /* User supplied - leave it alone. */ \
671 else if (TARGET_DIVIDE_CALL_FP) \
672 sh_divsi3_libfunc = "__sdivsi3_i4"; \
673 else if (TARGET_DIVIDE_CALL_TABLE) \
674 sh_divsi3_libfunc = "__sdivsi3_i4i"; \
675 else if (TARGET_SH5) \
676 sh_divsi3_libfunc = "__sdivsi3_1"; \
677 else \
678 sh_divsi3_libfunc = "__sdivsi3"; \
679 if (sh_branch_cost == -1) \
680 sh_branch_cost \
681 = TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1; \
682 \
683 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
684 if (! VALID_REGISTER_P (regno)) \
685 sh_register_names[regno][0] = '\0'; \
686 \
687 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
688 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
689 sh_additional_register_names[regno][0] = '\0'; \
690 \
691 if (flag_omit_frame_pointer < 0) \
692 { \
693 /* The debugging information is sufficient, \
694 but gdb doesn't implement this yet */ \
695 if (0) \
696 flag_omit_frame_pointer \
697 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
698 else \
699 flag_omit_frame_pointer = 0; \
700 } \
701 \
702 if ((flag_pic && ! TARGET_PREFERGOT) \
703 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
704 flag_no_function_cse = 1; \
705 \
706 if (SMALL_REGISTER_CLASSES) \
707 { \
708 /* Never run scheduling before reload, since that can \
709 break global alloc, and generates slower code anyway due \
710 to the pressure on R0. */ \
711 /* Enable sched1 for SH4; ready queue will be reordered by \
712 the target hooks when pressure is high. We can not do this for \
713 SH3 and lower as they give spill failures for R0. */ \
714 if (!TARGET_HARD_SH4) \
715 flag_schedule_insns = 0; \
716 /* ??? Current exception handling places basic block boundaries \
717 after call_insns. It causes the high pressure on R0 and gives \
718 spill failures for R0 in reload. See PR 22553 and the thread \
719 on gcc-patches \
720 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
721 else if (flag_exceptions) \
722 { \
723 if (flag_schedule_insns == 1) \
724 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
725 flag_schedule_insns = 0; \
726 } \
727 } \
728 \
729 if (align_loops == 0) \
730 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
731 if (align_jumps == 0) \
732 align_jumps = 1 << CACHE_LOG; \
733 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
734 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
735 \
736 /* Allocation boundary (in *bytes*) for the code of a function. \
737 SH1: 32 bit alignment is faster, because instructions are always \
738 fetched as a pair from a longword boundary. \
739 SH2 .. SH5 : align to cache line start. */ \
740 if (align_functions == 0) \
741 align_functions \
742 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
743 /* The linker relaxation code breaks when a function contains \
744 alignments that are larger than that at the start of a \
745 compilation unit. */ \
746 if (TARGET_RELAX) \
747 { \
748 int min_align \
749 = align_loops > align_jumps ? align_loops : align_jumps; \
750 \
751 /* Also take possible .long constants / mova tables int account. */\
752 if (min_align < 4) \
753 min_align = 4; \
754 if (align_functions < min_align) \
755 align_functions = min_align; \
756 } \
757 } while (0)
758 \f
759 /* Target machine storage layout. */
760
761 /* Define this if most significant bit is lowest numbered
762 in instructions that operate on numbered bit-fields. */
763
764 #define BITS_BIG_ENDIAN 0
765
766 /* Define this if most significant byte of a word is the lowest numbered. */
767 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
768
769 /* Define this if most significant word of a multiword number is the lowest
770 numbered. */
771 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
772
773 /* Define this to set the endianness to use in libgcc2.c, which can
774 not depend on target_flags. */
775 #if defined(__LITTLE_ENDIAN__)
776 #define LIBGCC2_WORDS_BIG_ENDIAN 0
777 #else
778 #define LIBGCC2_WORDS_BIG_ENDIAN 1
779 #endif
780
781 #define MAX_BITS_PER_WORD 64
782
783 /* Width in bits of an `int'. We want just 32-bits, even if words are
784 longer. */
785 #define INT_TYPE_SIZE 32
786
787 /* Width in bits of a `long'. */
788 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
789
790 /* Width in bits of a `long long'. */
791 #define LONG_LONG_TYPE_SIZE 64
792
793 /* Width in bits of a `long double'. */
794 #define LONG_DOUBLE_TYPE_SIZE 64
795
796 /* Width of a word, in units (bytes). */
797 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
798 #define MIN_UNITS_PER_WORD 4
799
800 /* Scaling factor for Dwarf data offsets for CFI information.
801 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
802 SHmedia; however, since we do partial register saves for the registers
803 visible to SHcompact, and for target registers for SHMEDIA32, we have
804 to allow saves that are only 4-byte aligned. */
805 #define DWARF_CIE_DATA_ALIGNMENT -4
806
807 /* Width in bits of a pointer.
808 See also the macro `Pmode' defined below. */
809 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
810
811 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
812 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
813
814 /* Boundary (in *bits*) on which stack pointer should be aligned. */
815 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
816
817 /* The log (base 2) of the cache line size, in bytes. Processors prior to
818 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
819 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
820 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
821
822 /* ABI given & required minimum allocation boundary (in *bits*) for the
823 code of a function. */
824 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
825
826 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
827 the vbit must go into the delta field of
828 pointers-to-member-functions. */
829 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
830 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
831
832 /* Alignment of field after `int : 0' in a structure. */
833 #define EMPTY_FIELD_BOUNDARY 32
834
835 /* No data type wants to be aligned rounder than this. */
836 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
837
838 /* The best alignment to use in cases where we have a choice. */
839 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
840
841 /* Make strings word-aligned so strcpy from constants will be faster. */
842 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
843 ((TREE_CODE (EXP) == STRING_CST \
844 && (ALIGN) < FASTEST_ALIGNMENT) \
845 ? FASTEST_ALIGNMENT : (ALIGN))
846
847 /* get_mode_alignment assumes complex values are always held in multiple
848 registers, but that is not the case on the SH; CQImode and CHImode are
849 held in a single integer register. SH5 also holds CSImode and SCmode
850 values in integer registers. This is relevant for argument passing on
851 SHcompact as we use a stack temp in order to pass CSImode by reference. */
852 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
853 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
854 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
855 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
856 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
857
858 /* Make arrays of chars word-aligned for the same reasons. */
859 #define DATA_ALIGNMENT(TYPE, ALIGN) \
860 (TREE_CODE (TYPE) == ARRAY_TYPE \
861 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
862 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
863
864 /* Number of bits which any structure or union's size must be a
865 multiple of. Each structure or union's size is rounded up to a
866 multiple of this. */
867 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
868
869 /* Set this nonzero if move instructions will actually fail to work
870 when given unaligned data. */
871 #define STRICT_ALIGNMENT 1
872
873 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
874 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
875 barrier_align (LABEL_AFTER_BARRIER)
876
877 #define LOOP_ALIGN(A_LABEL) \
878 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
879 ? 0 : sh_loop_align (A_LABEL))
880
881 #define LABEL_ALIGN(A_LABEL) \
882 ( \
883 (PREV_INSN (A_LABEL) \
884 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
885 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
886 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
887 /* explicit alignment insn in constant tables. */ \
888 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
889 : 0)
890
891 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
892 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
893
894 /* The base two logarithm of the known minimum alignment of an insn length. */
895 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
896 (GET_CODE (A_INSN) == INSN \
897 ? 1 << TARGET_SHMEDIA \
898 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
899 ? 1 << TARGET_SHMEDIA \
900 : CACHE_LOG)
901 \f
902 /* Standard register usage. */
903
904 /* Register allocation for the Renesas calling convention:
905
906 r0 arg return
907 r1..r3 scratch
908 r4..r7 args in
909 r8..r13 call saved
910 r14 frame pointer/call saved
911 r15 stack pointer
912 ap arg pointer (doesn't really exist, always eliminated)
913 pr subroutine return address
914 t t bit
915 mach multiply/accumulate result, high part
916 macl multiply/accumulate result, low part.
917 fpul fp/int communication register
918 rap return address pointer register
919 fr0 fp arg return
920 fr1..fr3 scratch floating point registers
921 fr4..fr11 fp args in
922 fr12..fr15 call saved floating point registers */
923
924 #define MAX_REGISTER_NAME_LENGTH 5
925 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
926
927 #define SH_REGISTER_NAMES_INITIALIZER \
928 { \
929 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
930 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
931 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
932 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
933 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
934 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
935 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
936 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
937 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
938 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
939 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
940 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
941 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
942 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
943 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
944 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
945 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
946 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
947 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
948 "rap", "sfp" \
949 }
950
951 #define REGNAMES_ARR_INDEX_1(index) \
952 (sh_register_names[index])
953 #define REGNAMES_ARR_INDEX_2(index) \
954 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
955 #define REGNAMES_ARR_INDEX_4(index) \
956 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
957 #define REGNAMES_ARR_INDEX_8(index) \
958 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
959 #define REGNAMES_ARR_INDEX_16(index) \
960 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
961 #define REGNAMES_ARR_INDEX_32(index) \
962 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
963 #define REGNAMES_ARR_INDEX_64(index) \
964 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
965
966 #define REGISTER_NAMES \
967 { \
968 REGNAMES_ARR_INDEX_64 (0), \
969 REGNAMES_ARR_INDEX_64 (64), \
970 REGNAMES_ARR_INDEX_8 (128), \
971 REGNAMES_ARR_INDEX_8 (136), \
972 REGNAMES_ARR_INDEX_8 (144), \
973 REGNAMES_ARR_INDEX_2 (152) \
974 }
975
976 #define ADDREGNAMES_SIZE 32
977 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
978 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
979 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
980
981 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
982 { \
983 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
984 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
985 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
986 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
987 }
988
989 #define ADDREGNAMES_REGNO(index) \
990 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
991 : (-1))
992
993 #define ADDREGNAMES_ARR_INDEX_1(index) \
994 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
995 #define ADDREGNAMES_ARR_INDEX_2(index) \
996 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
997 #define ADDREGNAMES_ARR_INDEX_4(index) \
998 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
999 #define ADDREGNAMES_ARR_INDEX_8(index) \
1000 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
1001 #define ADDREGNAMES_ARR_INDEX_16(index) \
1002 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
1003 #define ADDREGNAMES_ARR_INDEX_32(index) \
1004 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
1005
1006 #define ADDITIONAL_REGISTER_NAMES \
1007 { \
1008 ADDREGNAMES_ARR_INDEX_32 (0) \
1009 }
1010
1011 /* Number of actual hardware registers.
1012 The hardware registers are assigned numbers for the compiler
1013 from 0 to just below FIRST_PSEUDO_REGISTER.
1014 All registers that the compiler knows about must be given numbers,
1015 even those that are not normally considered general registers. */
1016
1017 /* There are many other relevant definitions in sh.md's md_constants. */
1018
1019 #define FIRST_GENERAL_REG R0_REG
1020 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
1021 #define FIRST_FP_REG DR0_REG
1022 #define LAST_FP_REG (FIRST_FP_REG + \
1023 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
1024 #define FIRST_XD_REG XD0_REG
1025 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
1026 #define FIRST_TARGET_REG TR0_REG
1027 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
1028
1029 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
1030
1031 #define FIRST_BANKED_REG R0_REG
1032 #define LAST_BANKED_REG R7_REG
1033
1034 #define BANKED_REGISTER_P(REGNO) \
1035 IN_RANGE ((REGNO), \
1036 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
1037 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
1038
1039 #define GENERAL_REGISTER_P(REGNO) \
1040 IN_RANGE ((REGNO), \
1041 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
1042 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
1043
1044 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
1045 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
1046 || ((REGNO) == FRAME_POINTER_REGNUM))
1047
1048 #define FP_REGISTER_P(REGNO) \
1049 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
1050
1051 #define XD_REGISTER_P(REGNO) \
1052 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
1053
1054 #define FP_OR_XD_REGISTER_P(REGNO) \
1055 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
1056
1057 #define FP_ANY_REGISTER_P(REGNO) \
1058 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
1059
1060 #define SPECIAL_REGISTER_P(REGNO) \
1061 ((REGNO) == GBR_REG || (REGNO) == T_REG \
1062 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1063
1064 #define TARGET_REGISTER_P(REGNO) \
1065 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1066
1067 #define SHMEDIA_REGISTER_P(REGNO) \
1068 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1069 || TARGET_REGISTER_P (REGNO))
1070
1071 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1072 that should be fixed. */
1073 #define VALID_REGISTER_P(REGNO) \
1074 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1075 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1076 || (REGNO) == FRAME_POINTER_REGNUM \
1077 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1078 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1079
1080 /* The mode that should be generally used to store a register by
1081 itself in the stack, or to load it back. */
1082 #define REGISTER_NATURAL_MODE(REGNO) \
1083 (FP_REGISTER_P (REGNO) ? SFmode \
1084 : XD_REGISTER_P (REGNO) ? DFmode \
1085 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1086 ? DImode \
1087 : SImode)
1088
1089 #define FIRST_PSEUDO_REGISTER 154
1090
1091 /* Don't count soft frame pointer. */
1092 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1093
1094 /* 1 for registers that have pervasive standard uses
1095 and are not available for the register allocator.
1096
1097 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1098 It is 32 bits wide for SH2. */
1099
1100 #define FIXED_REGISTERS \
1101 { \
1102 /* Regular registers. */ \
1103 0, 0, 0, 0, 0, 0, 0, 0, \
1104 0, 0, 0, 0, 0, 0, 0, 1, \
1105 /* r16 is reserved, r18 is the former pr. */ \
1106 1, 0, 0, 0, 0, 0, 0, 0, \
1107 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1108 /* r26 is a global variable data pointer; r27 is for constants. */ \
1109 1, 1, 1, 1, 0, 0, 0, 0, \
1110 0, 0, 0, 0, 0, 0, 0, 0, \
1111 0, 0, 0, 0, 0, 0, 0, 0, \
1112 0, 0, 0, 0, 0, 0, 0, 0, \
1113 0, 0, 0, 0, 0, 0, 0, 1, \
1114 /* FP registers. */ \
1115 0, 0, 0, 0, 0, 0, 0, 0, \
1116 0, 0, 0, 0, 0, 0, 0, 0, \
1117 0, 0, 0, 0, 0, 0, 0, 0, \
1118 0, 0, 0, 0, 0, 0, 0, 0, \
1119 0, 0, 0, 0, 0, 0, 0, 0, \
1120 0, 0, 0, 0, 0, 0, 0, 0, \
1121 0, 0, 0, 0, 0, 0, 0, 0, \
1122 0, 0, 0, 0, 0, 0, 0, 0, \
1123 /* Branch target registers. */ \
1124 0, 0, 0, 0, 0, 0, 0, 0, \
1125 /* XD registers. */ \
1126 0, 0, 0, 0, 0, 0, 0, 0, \
1127 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1128 1, 1, 1, 1, 1, 1, 0, 1, \
1129 /*"rap", "sfp" */ \
1130 1, 1, \
1131 }
1132
1133 /* 1 for registers not available across function calls.
1134 These must include the FIXED_REGISTERS and also any
1135 registers that can be used without being saved.
1136 The latter must include the registers where values are returned
1137 and the register where structure-value addresses are passed.
1138 Aside from that, you can include as many other registers as you like. */
1139
1140 #define CALL_USED_REGISTERS \
1141 { \
1142 /* Regular registers. */ \
1143 1, 1, 1, 1, 1, 1, 1, 1, \
1144 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1145 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1146 across SH5 function calls. */ \
1147 0, 0, 0, 0, 0, 0, 0, 1, \
1148 1, 1, 1, 1, 1, 1, 1, 1, \
1149 1, 1, 1, 1, 0, 0, 0, 0, \
1150 0, 0, 0, 0, 1, 1, 1, 1, \
1151 1, 1, 1, 1, 0, 0, 0, 0, \
1152 0, 0, 0, 0, 0, 0, 0, 0, \
1153 0, 0, 0, 0, 1, 1, 1, 1, \
1154 /* FP registers. */ \
1155 1, 1, 1, 1, 1, 1, 1, 1, \
1156 1, 1, 1, 1, 0, 0, 0, 0, \
1157 1, 1, 1, 1, 1, 1, 1, 1, \
1158 1, 1, 1, 1, 1, 1, 1, 1, \
1159 1, 1, 1, 1, 0, 0, 0, 0, \
1160 0, 0, 0, 0, 0, 0, 0, 0, \
1161 0, 0, 0, 0, 0, 0, 0, 0, \
1162 0, 0, 0, 0, 0, 0, 0, 0, \
1163 /* Branch target registers. */ \
1164 1, 1, 1, 1, 1, 0, 0, 0, \
1165 /* XD registers. */ \
1166 1, 1, 1, 1, 1, 1, 0, 0, \
1167 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1168 1, 1, 1, 1, 1, 1, 1, 1, \
1169 /*"rap", "sfp" */ \
1170 1, 1, \
1171 }
1172
1173 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1174 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1175 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1176
1177 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1178 across SHcompact function calls. We can't tell whether a called
1179 function is SHmedia or SHcompact, so we assume it may be when
1180 compiling SHmedia code with the 32-bit ABI, since that's the only
1181 ABI that can be linked with SHcompact code. */
1182 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1183 (TARGET_SHMEDIA32 \
1184 && GET_MODE_SIZE (MODE) > 4 \
1185 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1186 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1187 || TARGET_REGISTER_P (REGNO) \
1188 || (REGNO) == PR_MEDIA_REG))
1189
1190 /* Return number of consecutive hard regs needed starting at reg REGNO
1191 to hold something of mode MODE.
1192 This is ordinarily the length in words of a value of mode MODE
1193 but can be less for certain modes in special long registers.
1194
1195 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1196
1197 #define HARD_REGNO_NREGS(REGNO, MODE) \
1198 (XD_REGISTER_P (REGNO) \
1199 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1200 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1201 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1202 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1203
1204 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1205 We can allow any mode in any general register. The special registers
1206 only allow SImode. Don't allow any mode in the PR. */
1207
1208 /* We cannot hold DCmode values in the XD registers because alter_reg
1209 handles subregs of them incorrectly. We could work around this by
1210 spacing the XD registers like the DR registers, but this would require
1211 additional memory in every compilation to hold larger register vectors.
1212 We could hold SFmode / SCmode values in XD registers, but that
1213 would require a tertiary reload when reloading from / to memory,
1214 and a secondary reload to reload from / to general regs; that
1215 seems to be a loosing proposition. */
1216 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1217 it won't be ferried through GP registers first. */
1218 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1219 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1220 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1221 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1222 ? 1 \
1223 : (MODE) == V2SFmode \
1224 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1225 || GENERAL_REGISTER_P (REGNO)) \
1226 : (MODE) == V4SFmode \
1227 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1228 || GENERAL_REGISTER_P (REGNO)) \
1229 : (MODE) == V16SFmode \
1230 ? (TARGET_SHMEDIA \
1231 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1232 : (REGNO) == FIRST_XD_REG) \
1233 : FP_REGISTER_P (REGNO) \
1234 ? ((MODE) == SFmode || (MODE) == SImode \
1235 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1236 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1237 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1238 || (MODE) == V2SFmode || (MODE) == TImode))) \
1239 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1240 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1241 && (MODE) == TImode \
1242 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1243 : XD_REGISTER_P (REGNO) \
1244 ? (MODE) == DFmode \
1245 : TARGET_REGISTER_P (REGNO) \
1246 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1247 : (REGNO) == PR_REG ? (MODE) == SImode \
1248 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1249 : 1)
1250
1251 /* Value is 1 if it is a good idea to tie two pseudo registers
1252 when one has mode MODE1 and one has mode MODE2.
1253 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1254 for any hard reg, then this must be 0 for correct output.
1255 That's the case for xd registers: we don't hold SFmode values in
1256 them, so we can't tie an SFmode pseudos with one in another
1257 floating-point mode. */
1258
1259 #define MODES_TIEABLE_P(MODE1, MODE2) \
1260 ((MODE1) == (MODE2) \
1261 || (TARGET_SHMEDIA \
1262 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1263 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1264 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1265 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1266 && (GET_MODE_SIZE (MODE2) <= 4)) \
1267 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1268
1269 /* A C expression that is nonzero if hard register NEW_REG can be
1270 considered for use as a rename register for OLD_REG register */
1271
1272 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1273 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1274
1275 /* Specify the registers used for certain standard purposes.
1276 The values of these macros are register numbers. */
1277
1278 /* Define this if the program counter is overloaded on a register. */
1279 /* #define PC_REGNUM 15*/
1280
1281 /* Register to use for pushing function arguments. */
1282 #define STACK_POINTER_REGNUM SP_REG
1283
1284 /* Base register for access to local variables of the function. */
1285 #define HARD_FRAME_POINTER_REGNUM FP_REG
1286
1287 /* Base register for access to local variables of the function. */
1288 #define FRAME_POINTER_REGNUM 153
1289
1290 /* Fake register that holds the address on the stack of the
1291 current function's return address. */
1292 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1293
1294 /* Register to hold the addressing base for position independent
1295 code access to data items. */
1296 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1297
1298 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1299
1300 /* Value should be nonzero if functions must have frame pointers.
1301 Zero means the frame pointer need not be set up (and parms may be accessed
1302 via the stack pointer) in functions that seem suitable. */
1303
1304 #define FRAME_POINTER_REQUIRED 0
1305
1306 /* Definitions for register eliminations.
1307
1308 We have three registers that can be eliminated on the SH. First, the
1309 frame pointer register can often be eliminated in favor of the stack
1310 pointer register. Secondly, the argument pointer register can always be
1311 eliminated; it is replaced with either the stack or frame pointer.
1312 Third, there is the return address pointer, which can also be replaced
1313 with either the stack or the frame pointer. */
1314
1315 /* This is an array of structures. Each structure initializes one pair
1316 of eliminable registers. The "from" register number is given first,
1317 followed by "to". Eliminations of the same "from" register are listed
1318 in order of preference. */
1319
1320 /* If you add any registers here that are not actually hard registers,
1321 and that have any alternative of elimination that doesn't always
1322 apply, you need to amend calc_live_regs to exclude it, because
1323 reload spills all eliminable registers where it sees an
1324 can_eliminate == 0 entry, thus making them 'live' .
1325 If you add any hard registers that can be eliminated in different
1326 ways, you have to patch reload to spill them only when all alternatives
1327 of elimination fail. */
1328
1329 #define ELIMINABLE_REGS \
1330 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1331 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1332 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1333 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1334 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1335 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1336 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1337
1338 /* Given FROM and TO register numbers, say whether this elimination
1339 is allowed. */
1340 #define CAN_ELIMINATE(FROM, TO) \
1341 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1342
1343 /* Define the offset between two registers, one to be eliminated, and the other
1344 its replacement, at the start of a routine. */
1345
1346 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1347 OFFSET = initial_elimination_offset ((FROM), (TO))
1348
1349 /* Base register for access to arguments of the function. */
1350 #define ARG_POINTER_REGNUM AP_REG
1351
1352 /* Register in which the static-chain is passed to a function. */
1353 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1354
1355 /* Don't default to pcc-struct-return, because we have already specified
1356 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1357 target hook. */
1358
1359 #define DEFAULT_PCC_STRUCT_RETURN 0
1360
1361 #define SHMEDIA_REGS_STACK_ADJUST() \
1362 (TARGET_SHCOMPACT && current_function_saves_all_registers \
1363 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1364 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1365 : 0)
1366
1367 \f
1368 /* Define the classes of registers for register constraints in the
1369 machine description. Also define ranges of constants.
1370
1371 One of the classes must always be named ALL_REGS and include all hard regs.
1372 If there is more than one class, another class must be named NO_REGS
1373 and contain no registers.
1374
1375 The name GENERAL_REGS must be the name of a class (or an alias for
1376 another name such as ALL_REGS). This is the class of registers
1377 that is allowed by "g" or "r" in a register constraint.
1378 Also, registers outside this class are allocated only when
1379 instructions express preferences for them.
1380
1381 The classes must be numbered in nondecreasing order; that is,
1382 a larger-numbered class must never be contained completely
1383 in a smaller-numbered class.
1384
1385 For any two classes, it is very desirable that there be another
1386 class that represents their union. */
1387
1388 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1389 be used as the destination of some of the arithmetic ops. There are
1390 also some special purpose registers; the T bit register, the
1391 Procedure Return Register and the Multiply Accumulate Registers. */
1392 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1393 reg_class_subunion. We don't want to have an actual union class
1394 of these, because it would only be used when both classes are calculated
1395 to give the same cost, but there is only one FPUL register.
1396 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1397 applying to the actual instruction alternative considered. E.g., the
1398 y/r alternative of movsi_ie is considered to have no more cost that
1399 the r/r alternative, which is patently untrue. */
1400
1401 enum reg_class
1402 {
1403 NO_REGS,
1404 R0_REGS,
1405 PR_REGS,
1406 T_REGS,
1407 MAC_REGS,
1408 FPUL_REGS,
1409 SIBCALL_REGS,
1410 GENERAL_REGS,
1411 FP0_REGS,
1412 FP_REGS,
1413 DF_HI_REGS,
1414 DF_REGS,
1415 FPSCR_REGS,
1416 GENERAL_FP_REGS,
1417 GENERAL_DF_REGS,
1418 TARGET_REGS,
1419 ALL_REGS,
1420 LIM_REG_CLASSES
1421 };
1422
1423 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1424
1425 /* Give names of register classes as strings for dump file. */
1426 #define REG_CLASS_NAMES \
1427 { \
1428 "NO_REGS", \
1429 "R0_REGS", \
1430 "PR_REGS", \
1431 "T_REGS", \
1432 "MAC_REGS", \
1433 "FPUL_REGS", \
1434 "SIBCALL_REGS", \
1435 "GENERAL_REGS", \
1436 "FP0_REGS", \
1437 "FP_REGS", \
1438 "DF_HI_REGS", \
1439 "DF_REGS", \
1440 "FPSCR_REGS", \
1441 "GENERAL_FP_REGS", \
1442 "GENERAL_DF_REGS", \
1443 "TARGET_REGS", \
1444 "ALL_REGS", \
1445 }
1446
1447 /* Define which registers fit in which classes.
1448 This is an initializer for a vector of HARD_REG_SET
1449 of length N_REG_CLASSES. */
1450
1451 #define REG_CLASS_CONTENTS \
1452 { \
1453 /* NO_REGS: */ \
1454 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1455 /* R0_REGS: */ \
1456 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1457 /* PR_REGS: */ \
1458 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1459 /* T_REGS: */ \
1460 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1461 /* MAC_REGS: */ \
1462 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1463 /* FPUL_REGS: */ \
1464 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1465 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1466 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1467 /* GENERAL_REGS: */ \
1468 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1469 /* FP0_REGS: */ \
1470 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1471 /* FP_REGS: */ \
1472 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1473 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1474 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1475 /* DF_REGS: */ \
1476 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1477 /* FPSCR_REGS: */ \
1478 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1479 /* GENERAL_FP_REGS: */ \
1480 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1481 /* GENERAL_DF_REGS: */ \
1482 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1483 /* TARGET_REGS: */ \
1484 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1485 /* ALL_REGS: */ \
1486 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1487 }
1488
1489 /* The same information, inverted:
1490 Return the class number of the smallest class containing
1491 reg number REGNO. This could be a conditional expression
1492 or could index an array. */
1493
1494 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1495 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1496
1497 /* When defined, the compiler allows registers explicitly used in the
1498 rtl to be used as spill registers but prevents the compiler from
1499 extending the lifetime of these registers. */
1500
1501 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1502
1503 /* The order in which register should be allocated. */
1504 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1505 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1506 spilled or used otherwise, we better have the FP_REGS allocated first. */
1507 #define REG_ALLOC_ORDER \
1508 {/* Caller-saved FPRs */ \
1509 65, 66, 67, 68, 69, 70, 71, 64, \
1510 72, 73, 74, 75, 80, 81, 82, 83, \
1511 84, 85, 86, 87, 88, 89, 90, 91, \
1512 92, 93, 94, 95, 96, 97, 98, 99, \
1513 /* Callee-saved FPRs */ \
1514 76, 77, 78, 79,100,101,102,103, \
1515 104,105,106,107,108,109,110,111, \
1516 112,113,114,115,116,117,118,119, \
1517 120,121,122,123,124,125,126,127, \
1518 136,137,138,139,140,141,142,143, \
1519 /* FPSCR */ 151, \
1520 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1521 1, 2, 3, 7, 6, 5, 4, 0, \
1522 8, 9, 17, 19, 20, 21, 22, 23, \
1523 36, 37, 38, 39, 40, 41, 42, 43, \
1524 60, 61, 62, \
1525 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1526 10, 11, 12, 13, 14, 18, \
1527 /* SH5 callee-saved GPRs */ \
1528 28, 29, 30, 31, 32, 33, 34, 35, \
1529 44, 45, 46, 47, 48, 49, 50, 51, \
1530 52, 53, 54, 55, 56, 57, 58, 59, \
1531 /* FPUL */ 150, \
1532 /* SH5 branch target registers */ \
1533 128,129,130,131,132,133,134,135, \
1534 /* Fixed registers */ \
1535 15, 16, 24, 25, 26, 27, 63,144, \
1536 145,146,147,148,149,152,153 }
1537
1538 /* The class value for index registers, and the one for base regs. */
1539 #define INDEX_REG_CLASS \
1540 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1541 #define BASE_REG_CLASS GENERAL_REGS
1542 \f
1543 /* Defines for sh.md and constraints.md. */
1544
1545 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1546 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1547 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1548 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1549 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1550 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1551 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1552 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1553
1554 #define CONST_OK_FOR_J16(VALUE) \
1555 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1556 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1557
1558 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1559 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1560
1561 /* Given an rtx X being reloaded into a reg required to be
1562 in class CLASS, return the class of reg to actually use.
1563 In general this is just CLASS; but on some machines
1564 in some cases it is preferable to use a more restrictive class. */
1565
1566 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1567 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1568 && (GET_CODE (X) == CONST_DOUBLE \
1569 || GET_CODE (X) == SYMBOL_REF \
1570 || PIC_DIRECT_ADDR_P (X)) \
1571 ? GENERAL_REGS \
1572 : (CLASS)) \
1573
1574 #if 0
1575 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1576 ((((REGCLASS_HAS_FP_REG (CLASS) \
1577 && (GET_CODE (X) == REG \
1578 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1579 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1580 && TARGET_FMOVD)))) \
1581 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1582 && GET_CODE (X) == REG \
1583 && FP_REGISTER_P (REGNO (X)))) \
1584 && ! TARGET_SHMEDIA \
1585 && ((MODE) == SFmode || (MODE) == SImode)) \
1586 ? FPUL_REGS \
1587 : (((CLASS) == FPUL_REGS \
1588 || (REGCLASS_HAS_FP_REG (CLASS) \
1589 && ! TARGET_SHMEDIA && MODE == SImode)) \
1590 && (GET_CODE (X) == MEM \
1591 || (GET_CODE (X) == REG \
1592 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1593 || REGNO (X) == T_REG \
1594 || system_reg_operand (X, VOIDmode))))) \
1595 ? GENERAL_REGS \
1596 : (((CLASS) == TARGET_REGS \
1597 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1598 && !satisfies_constraint_Csy (X) \
1599 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1600 ? GENERAL_REGS \
1601 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1602 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1603 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1604 ? GENERAL_REGS \
1605 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1606 && TARGET_REGISTER_P (REGNO (X))) \
1607 ? GENERAL_REGS : (ELSE))
1608
1609 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1610 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1611
1612 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1613 ((REGCLASS_HAS_FP_REG (CLASS) \
1614 && ! TARGET_SHMEDIA \
1615 && immediate_operand ((X), (MODE)) \
1616 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1617 && (MODE) == SFmode && fldi_ok ())) \
1618 ? R0_REGS \
1619 : ((CLASS) == FPUL_REGS \
1620 && ((GET_CODE (X) == REG \
1621 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1622 || REGNO (X) == T_REG)) \
1623 || GET_CODE (X) == PLUS)) \
1624 ? GENERAL_REGS \
1625 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1626 ? (satisfies_constraint_I08 (X) \
1627 ? GENERAL_REGS \
1628 : R0_REGS) \
1629 : ((CLASS) == FPSCR_REGS \
1630 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1631 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1632 ? GENERAL_REGS \
1633 : (REGCLASS_HAS_FP_REG (CLASS) \
1634 && TARGET_SHMEDIA \
1635 && immediate_operand ((X), (MODE)) \
1636 && (X) != CONST0_RTX (GET_MODE (X)) \
1637 && GET_MODE (X) != V4SFmode) \
1638 ? GENERAL_REGS \
1639 : (((MODE) == QImode || (MODE) == HImode) \
1640 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1641 ? GENERAL_REGS \
1642 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1643 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1644 ? TARGET_REGS \
1645 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1646 #endif
1647
1648 /* Return the maximum number of consecutive registers
1649 needed to represent mode MODE in a register of class CLASS.
1650
1651 If TARGET_SHMEDIA, we need two FP registers per word.
1652 Otherwise we will need at most one register per word. */
1653 #define CLASS_MAX_NREGS(CLASS, MODE) \
1654 (TARGET_SHMEDIA \
1655 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1656 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1657 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1658
1659 /* If defined, gives a class of registers that cannot be used as the
1660 operand of a SUBREG that changes the mode of the object illegally. */
1661 /* ??? We need to renumber the internal numbers for the frnn registers
1662 when in little endian in order to allow mode size changes. */
1663
1664 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1665 sh_cannot_change_mode_class (FROM, TO, CLASS)
1666 \f
1667 /* Stack layout; function entry, exit and calling. */
1668
1669 /* Define the number of registers that can hold parameters.
1670 These macros are used only in other macro definitions below. */
1671
1672 #define NPARM_REGS(MODE) \
1673 (TARGET_FPU_ANY && (MODE) == SFmode \
1674 ? (TARGET_SH5 ? 12 : 8) \
1675 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1676 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1677 ? (TARGET_SH5 ? 12 : 8) \
1678 : (TARGET_SH5 ? 8 : 4))
1679
1680 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1681 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1682
1683 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1684 #define FIRST_FP_RET_REG FIRST_FP_REG
1685
1686 /* Define this if pushing a word on the stack
1687 makes the stack pointer a smaller address. */
1688 #define STACK_GROWS_DOWNWARD
1689
1690 /* Define this macro to nonzero if the addresses of local variable slots
1691 are at negative offsets from the frame pointer. */
1692 #define FRAME_GROWS_DOWNWARD 1
1693
1694 /* Offset from the frame pointer to the first local variable slot to
1695 be allocated. */
1696 #define STARTING_FRAME_OFFSET 0
1697
1698 /* If we generate an insn to push BYTES bytes,
1699 this says how many the stack pointer really advances by. */
1700 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1701 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1702 do correct alignment. */
1703 #if 0
1704 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1705 #endif
1706
1707 /* Offset of first parameter from the argument pointer register value. */
1708 #define FIRST_PARM_OFFSET(FNDECL) 0
1709
1710 /* Value is the number of byte of arguments automatically
1711 popped when returning from a subroutine call.
1712 FUNDECL is the declaration node of the function (as a tree),
1713 FUNTYPE is the data type of the function (as a tree),
1714 or for a library call it is an identifier node for the subroutine name.
1715 SIZE is the number of bytes of arguments passed on the stack.
1716
1717 On the SH, the caller does not pop any of its arguments that were passed
1718 on the stack. */
1719 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1720
1721 /* Value is the number of bytes of arguments automatically popped when
1722 calling a subroutine.
1723 CUM is the accumulated argument list.
1724
1725 On SHcompact, the call trampoline pops arguments off the stack. */
1726 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1727
1728 /* Some subroutine macros specific to this machine. */
1729
1730 #define BASE_RETURN_VALUE_REG(MODE) \
1731 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1732 ? FIRST_FP_RET_REG \
1733 : TARGET_FPU_ANY && (MODE) == SCmode \
1734 ? FIRST_FP_RET_REG \
1735 : (TARGET_FPU_DOUBLE \
1736 && ((MODE) == DFmode || (MODE) == SFmode \
1737 || (MODE) == DCmode || (MODE) == SCmode )) \
1738 ? FIRST_FP_RET_REG \
1739 : FIRST_RET_REG)
1740
1741 #define BASE_ARG_REG(MODE) \
1742 ((TARGET_SH2E && ((MODE) == SFmode)) \
1743 ? FIRST_FP_PARM_REG \
1744 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1745 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1746 ? FIRST_FP_PARM_REG \
1747 : FIRST_PARM_REG)
1748
1749 /* Define how to find the value returned by a function.
1750 VALTYPE is the data type of the value (as a tree).
1751 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1752 otherwise, FUNC is 0.
1753 For the SH, this is like LIBCALL_VALUE, except that we must change the
1754 mode like PROMOTE_MODE does.
1755 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1756 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1757
1758 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1759 gen_rtx_REG ( \
1760 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1761 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1762 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1763 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1764 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1765 || TREE_CODE (VALTYPE) == REAL_TYPE \
1766 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1767 && sh_promote_prototypes (VALTYPE) \
1768 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1769 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1770
1771 /* Define how to find the value returned by a library function
1772 assuming the value has mode MODE. */
1773 #define LIBCALL_VALUE(MODE) \
1774 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1775
1776 /* 1 if N is a possible register number for a function value. */
1777 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1778 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1779 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1780
1781 /* 1 if N is a possible register number for function argument passing. */
1782 /* ??? There are some callers that pass REGNO as int, and others that pass
1783 it as unsigned. We get warnings unless we do casts everywhere. */
1784 #define FUNCTION_ARG_REGNO_P(REGNO) \
1785 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1786 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1787 || (TARGET_FPU_ANY \
1788 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1789 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1790 + NPARM_REGS (SFmode))))
1791 \f
1792 /* Define a data type for recording info about an argument list
1793 during the scan of that argument list. This data type should
1794 hold all necessary information about the function itself
1795 and about the args processed so far, enough to enable macros
1796 such as FUNCTION_ARG to determine where the next arg should go.
1797
1798 On SH, this is a single integer, which is a number of words
1799 of arguments scanned so far (including the invisible argument,
1800 if any, which holds the structure-value-address).
1801 Thus NARGREGS or more means all following args should go on the stack. */
1802
1803 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1804 struct sh_args {
1805 int arg_count[2];
1806 int force_mem;
1807 /* Nonzero if a prototype is available for the function. */
1808 int prototype_p;
1809 /* The number of an odd floating-point register, that should be used
1810 for the next argument of type float. */
1811 int free_single_fp_reg;
1812 /* Whether we're processing an outgoing function call. */
1813 int outgoing;
1814 /* The number of general-purpose registers that should have been
1815 used to pass partial arguments, that are passed totally on the
1816 stack. On SHcompact, a call trampoline will pop them off the
1817 stack before calling the actual function, and, if the called
1818 function is implemented in SHcompact mode, the incoming arguments
1819 decoder will push such arguments back onto the stack. For
1820 incoming arguments, STACK_REGS also takes into account other
1821 arguments passed by reference, that the decoder will also push
1822 onto the stack. */
1823 int stack_regs;
1824 /* The number of general-purpose registers that should have been
1825 used to pass arguments, if the arguments didn't have to be passed
1826 by reference. */
1827 int byref_regs;
1828 /* Set as by shcompact_byref if the current argument is to be passed
1829 by reference. */
1830 int byref;
1831
1832 /* call_cookie is a bitmask used by call expanders, as well as
1833 function prologue and epilogues, to allow SHcompact to comply
1834 with the SH5 32-bit ABI, that requires 64-bit registers to be
1835 used even though only the lower 32-bit half is visible in
1836 SHcompact mode. The strategy is to call SHmedia trampolines.
1837
1838 The alternatives for each of the argument-passing registers are
1839 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1840 contents from the address in it; (d) add 8 to it, storing the
1841 result in the next register, then (c); (e) copy it from some
1842 floating-point register,
1843
1844 Regarding copies from floating-point registers, r2 may only be
1845 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1846 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1847 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1848 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1849 dr10.
1850
1851 The bit mask is structured as follows:
1852
1853 - 1 bit to tell whether to set up a return trampoline.
1854
1855 - 3 bits to count the number consecutive registers to pop off the
1856 stack.
1857
1858 - 4 bits for each of r9, r8, r7 and r6.
1859
1860 - 3 bits for each of r5, r4, r3 and r2.
1861
1862 - 3 bits set to 0 (the most significant ones)
1863
1864 3 2 1 0
1865 1098 7654 3210 9876 5432 1098 7654 3210
1866 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1867 2223 3344 4555 6666 7777 8888 9999 SSS-
1868
1869 - If F is set, the register must be copied from an FP register,
1870 whose number is encoded in the remaining bits.
1871
1872 - Else, if L is set, the register must be loaded from the address
1873 contained in it. If the P bit is *not* set, the address of the
1874 following dword should be computed first, and stored in the
1875 following register.
1876
1877 - Else, if P is set, the register alone should be popped off the
1878 stack.
1879
1880 - After all this processing, the number of registers represented
1881 in SSS will be popped off the stack. This is an optimization
1882 for pushing/popping consecutive registers, typically used for
1883 varargs and large arguments partially passed in registers.
1884
1885 - If T is set, a return trampoline will be set up for 64-bit
1886 return values to be split into 2 32-bit registers. */
1887 long call_cookie;
1888
1889 /* This is set to nonzero when the call in question must use the Renesas ABI,
1890 even without the -mrenesas option. */
1891 int renesas_abi;
1892 };
1893
1894 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1895 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1896 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1897 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1898 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1899 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1900 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1901 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1902 #define CALL_COOKIE_INT_REG(REG, VAL) \
1903 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1904 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1905 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1906
1907 #define CUMULATIVE_ARGS struct sh_args
1908
1909 #define GET_SH_ARG_CLASS(MODE) \
1910 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1911 ? SH_ARG_FLOAT \
1912 /* There's no mention of complex float types in the SH5 ABI, so we
1913 should presumably handle them as aggregate types. */ \
1914 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1915 ? SH_ARG_INT \
1916 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1917 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1918 ? SH_ARG_FLOAT : SH_ARG_INT)
1919
1920 #define ROUND_ADVANCE(SIZE) \
1921 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1922
1923 /* Round a register number up to a proper boundary for an arg of mode
1924 MODE.
1925
1926 The SH doesn't care about double alignment, so we only
1927 round doubles to even regs when asked to explicitly. */
1928
1929 #define ROUND_REG(CUM, MODE) \
1930 (((TARGET_ALIGN_DOUBLE \
1931 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1932 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1933 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1934 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1935 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1936 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1937
1938 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1939 for a call to a function whose data type is FNTYPE.
1940 For a library call, FNTYPE is 0.
1941
1942 On SH, the offset always starts at 0: the first parm reg is always
1943 the same reg for a given argument class.
1944
1945 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1946
1947 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1948 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1949
1950 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1951 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1952
1953 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1954 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1955 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1956 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1957
1958 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1959 This macro is only used in this file. */
1960
1961 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1962 (((TYPE) == 0 \
1963 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1964 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1965 || ! (AGGREGATE_TYPE_P (TYPE) \
1966 || (!TARGET_FPU_ANY \
1967 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1968 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1969 && ! (CUM).force_mem \
1970 && (TARGET_SH2E \
1971 ? ((MODE) == BLKmode \
1972 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1973 + int_size_in_bytes (TYPE)) \
1974 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1975 : ((ROUND_REG((CUM), (MODE)) \
1976 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1977 <= NPARM_REGS (MODE))) \
1978 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1979
1980 /* By accident we got stuck with passing SCmode on SH4 little endian
1981 in two registers that are nominally successive - which is different from
1982 two single SFmode values, where we take endianness translation into
1983 account. That does not work at all if an odd number of registers is
1984 already in use, so that got fixed, but library functions are still more
1985 likely to use complex numbers without mixing them with SFmode arguments
1986 (which in C would have to be structures), so for the sake of ABI
1987 compatibility the way SCmode values are passed when an even number of
1988 FP registers is in use remains different from a pair of SFmode values for
1989 now.
1990 I.e.:
1991 foo (double); a: fr5,fr4
1992 foo (float a, float b); a: fr5 b: fr4
1993 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1994 this should be the other way round...
1995 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1996 #define FUNCTION_ARG_SCmode_WART 1
1997
1998 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1999 register in SHcompact mode, it must be padded in the most
2000 significant end. This means that passing it by reference wouldn't
2001 pad properly on a big-endian machine. In this particular case, we
2002 pass this argument on the stack, in a way that the call trampoline
2003 will load its value into the appropriate register. */
2004 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2005 ((MODE) == BLKmode \
2006 && TARGET_SHCOMPACT \
2007 && ! TARGET_LITTLE_ENDIAN \
2008 && int_size_in_bytes (TYPE) > 4 \
2009 && int_size_in_bytes (TYPE) < 8)
2010
2011 /* Minimum alignment for an argument to be passed by callee-copy
2012 reference. We need such arguments to be aligned to 8 byte
2013 boundaries, because they'll be loaded using quad loads. */
2014 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2015
2016 /* The SH5 ABI requires floating-point arguments to be passed to
2017 functions without a prototype in both an FP register and a regular
2018 register or the stack. When passing the argument in both FP and
2019 general-purpose registers, list the FP register first. */
2020 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2021 (gen_rtx_PARALLEL \
2022 ((MODE), \
2023 gen_rtvec (2, \
2024 gen_rtx_EXPR_LIST \
2025 (VOIDmode, \
2026 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2027 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2028 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2029 : NULL_RTX), \
2030 const0_rtx), \
2031 gen_rtx_EXPR_LIST \
2032 (VOIDmode, \
2033 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2034 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2035 + (CUM).arg_count[(int) SH_ARG_INT]) \
2036 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2037 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2038 const0_rtx))))
2039
2040 /* The SH5 ABI requires regular registers or stack slots to be
2041 reserved for floating-point arguments. Registers are taken care of
2042 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2043 Unfortunately, there's no way to just reserve a stack slot, so
2044 we'll end up needlessly storing a copy of the argument in the
2045 stack. For incoming arguments, however, the PARALLEL will be
2046 optimized to the register-only form, and the value in the stack
2047 slot won't be used at all. */
2048 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2049 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2050 ? gen_rtx_REG ((MODE), (REG)) \
2051 : gen_rtx_PARALLEL ((MODE), \
2052 gen_rtvec (2, \
2053 gen_rtx_EXPR_LIST \
2054 (VOIDmode, NULL_RTX, \
2055 const0_rtx), \
2056 gen_rtx_EXPR_LIST \
2057 (VOIDmode, gen_rtx_REG ((MODE), \
2058 (REG)), \
2059 const0_rtx))))
2060
2061 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2062 (TARGET_SH5 \
2063 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2064 || (MODE) == DCmode) \
2065 && ((CUM).arg_count[(int) SH_ARG_INT] \
2066 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
2067 : GET_MODE_SIZE (MODE)) \
2068 + 7) / 8) > NPARM_REGS (SImode))
2069
2070 /* Perform any needed actions needed for a function that is receiving a
2071 variable number of arguments. */
2072
2073 /* Call the function profiler with a given profile label.
2074 We use two .aligns, so as to make sure that both the .long is aligned
2075 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2076 from the trapa instruction. */
2077
2078 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2079 { \
2080 if (TARGET_SHMEDIA) \
2081 { \
2082 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2083 fprintf((STREAM), "\ttrapa\tr0\n"); \
2084 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2085 } \
2086 else \
2087 { \
2088 fprintf((STREAM), "\t.align\t2\n"); \
2089 fprintf((STREAM), "\ttrapa\t#33\n"); \
2090 fprintf((STREAM), "\t.align\t2\n"); \
2091 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2092 } \
2093 }
2094
2095 /* Define this macro if the code for function profiling should come
2096 before the function prologue. Normally, the profiling code comes
2097 after. */
2098
2099 #define PROFILE_BEFORE_PROLOGUE
2100
2101 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2102 the stack pointer does not matter. The value is tested only in
2103 functions that have frame pointers.
2104 No definition is equivalent to always zero. */
2105
2106 #define EXIT_IGNORE_STACK 1
2107
2108 /*
2109 On the SH, the trampoline looks like
2110 2 0002 D202 mov.l l2,r2
2111 1 0000 D301 mov.l l1,r3
2112 3 0004 422B jmp @r2
2113 4 0006 0009 nop
2114 5 0008 00000000 l1: .long area
2115 6 000c 00000000 l2: .long function */
2116
2117 /* Length in units of the trampoline for entering a nested function. */
2118 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2119
2120 /* Alignment required for a trampoline in bits . */
2121 #define TRAMPOLINE_ALIGNMENT \
2122 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2123 : TARGET_SHMEDIA ? 256 : 64)
2124
2125 /* Emit RTL insns to initialize the variable parts of a trampoline.
2126 FNADDR is an RTX for the address of the function's pure code.
2127 CXT is an RTX for the static chain value for the function. */
2128
2129 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2130 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2131
2132 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2133
2134 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2135 { \
2136 if (TARGET_SHMEDIA) \
2137 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2138 gen_reg_rtx (Pmode), 0, \
2139 OPTAB_LIB_WIDEN); \
2140 } while (0)
2141
2142 /* A C expression whose value is RTL representing the value of the return
2143 address for the frame COUNT steps up from the current frame.
2144 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2145 can ignore COUNT. */
2146
2147 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2148 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2149
2150 /* A C expression whose value is RTL representing the location of the
2151 incoming return address at the beginning of any function, before the
2152 prologue. This RTL is either a REG, indicating that the return
2153 value is saved in REG, or a MEM representing a location in
2154 the stack. */
2155 #define INCOMING_RETURN_ADDR_RTX \
2156 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2157 \f
2158 /* Addressing modes, and classification of registers for them. */
2159 #define HAVE_POST_INCREMENT TARGET_SH1
2160 #define HAVE_PRE_DECREMENT TARGET_SH1
2161
2162 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2163 ? 0 : TARGET_SH1)
2164 #define USE_LOAD_PRE_DECREMENT(mode) 0
2165 #define USE_STORE_POST_INCREMENT(mode) 0
2166 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2167 ? 0 : TARGET_SH1)
2168
2169 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2170 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2171 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2172
2173 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2174 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2175 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2176
2177 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
2178
2179 /* Macros to check register numbers against specific register classes. */
2180
2181 /* These assume that REGNO is a hard or pseudo reg number.
2182 They give nonzero only if REGNO is a hard reg of the suitable class
2183 or a pseudo reg currently allocated to a suitable hard reg.
2184 Since they use reg_renumber, they are safe only once reg_renumber
2185 has been allocated, which happens in local-alloc.c. */
2186
2187 #define REGNO_OK_FOR_BASE_P(REGNO) \
2188 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2189 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2190 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2191 (TARGET_SHMEDIA \
2192 ? (GENERAL_REGISTER_P (REGNO) \
2193 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2194 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2195
2196 /* Maximum number of registers that can appear in a valid memory
2197 address. */
2198
2199 #define MAX_REGS_PER_ADDRESS 2
2200
2201 /* Recognize any constant value that is a valid address. */
2202
2203 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2204
2205 /* Nonzero if the constant value X is a legitimate general operand. */
2206 /* can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
2207
2208 #define LEGITIMATE_CONSTANT_P(X) \
2209 (TARGET_SHMEDIA \
2210 ? ((GET_MODE (X) != DFmode \
2211 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2212 || (X) == CONST0_RTX (GET_MODE (X)) \
2213 || ! TARGET_SHMEDIA_FPU \
2214 || TARGET_SHMEDIA64) \
2215 : (GET_CODE (X) != CONST_DOUBLE \
2216 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2217 || GET_MODE (X) == DImode || GET_MODE (X) == VOIDmode))
2218
2219 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2220 and check its validity for a certain class.
2221 We have two alternate definitions for each of them.
2222 The usual definition accepts all pseudo regs; the other rejects
2223 them unless they have been allocated suitable hard regs.
2224 The symbol REG_OK_STRICT causes the latter definition to be used. */
2225
2226 #ifndef REG_OK_STRICT
2227
2228 /* Nonzero if X is a hard reg that can be used as a base reg
2229 or if it is a pseudo reg. */
2230 #define REG_OK_FOR_BASE_P(X) \
2231 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2232
2233 /* Nonzero if X is a hard reg that can be used as an index
2234 or if it is a pseudo reg. */
2235 #define REG_OK_FOR_INDEX_P(X) \
2236 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2237 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2238
2239 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2240 or if X is a pseudo reg. */
2241 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2242 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2243 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2244
2245 #else
2246
2247 /* Nonzero if X is a hard reg that can be used as a base reg. */
2248 #define REG_OK_FOR_BASE_P(X) \
2249 REGNO_OK_FOR_BASE_P (REGNO (X))
2250
2251 /* Nonzero if X is a hard reg that can be used as an index. */
2252 #define REG_OK_FOR_INDEX_P(X) \
2253 REGNO_OK_FOR_INDEX_P (REGNO (X))
2254
2255 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2256 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2257 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2258
2259 #endif
2260
2261 /* Macros for extra constraints. */
2262
2263 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
2264 ((GET_CODE ((OP)) == LABEL_REF) \
2265 || (GET_CODE ((OP)) == CONST \
2266 && GET_CODE (XEXP ((OP), 0)) == PLUS \
2267 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2268 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2269
2270 #define IS_LITERAL_OR_SYMBOLIC_S16_P(OP) \
2271 (GET_CODE ((OP)) == SIGN_EXTEND \
2272 && (GET_MODE ((OP)) == DImode \
2273 || GET_MODE ((OP)) == SImode) \
2274 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2275 && GET_MODE (XEXP ((OP), 0)) == HImode \
2276 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2277 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2278 && (MOVI_SHORI_BASE_OPERAND_P \
2279 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2280 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2281
2282 #define IS_LITERAL_OR_SYMBOLIC_U16_P(OP) \
2283 (GET_CODE ((OP)) == ZERO_EXTEND \
2284 && (GET_MODE ((OP)) == DImode \
2285 || GET_MODE ((OP)) == SImode) \
2286 && GET_CODE (XEXP ((OP), 0)) == TRUNCATE \
2287 && GET_MODE (XEXP ((OP), 0)) == HImode \
2288 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP ((OP), 0), 0)) \
2289 || (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == ASHIFTRT \
2290 && (MOVI_SHORI_BASE_OPERAND_P \
2291 (XEXP (XEXP (XEXP ((OP), 0), 0), 0))) \
2292 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2293
2294 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
2295 (CONSTANT_P (OP) \
2296 && GET_CODE (OP) != CONST_INT \
2297 && GET_CODE (OP) != CONST_DOUBLE \
2298 && (!flag_pic \
2299 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2300 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2301 && GET_CODE (OP) != LABEL_REF)))
2302
2303 /* Check whether OP is a datalabel unspec. */
2304 #define DATALABEL_REF_NO_CONST_P(OP) \
2305 (GET_CODE (OP) == UNSPEC \
2306 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2307 && XVECLEN ((OP), 0) == 1 \
2308 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2309
2310 #define GOT_ENTRY_P(OP) \
2311 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2312 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2313
2314 #define GOTPLT_ENTRY_P(OP) \
2315 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2316 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2317
2318 #define UNSPEC_GOTOFF_P(OP) \
2319 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2320
2321 #define GOTOFF_P(OP) \
2322 (GET_CODE (OP) == CONST \
2323 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2324 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2325 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2326 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2327
2328 #define PIC_ADDR_P(OP) \
2329 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2330 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2331
2332 #define PIC_OFFSET_P(OP) \
2333 (PIC_ADDR_P (OP) \
2334 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2335 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2336
2337 #define PIC_DIRECT_ADDR_P(OP) \
2338 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2339
2340 #define NON_PIC_REFERENCE_P(OP) \
2341 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2342 || (GET_CODE (OP) == CONST \
2343 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2344 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2345 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2346 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2347 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2348 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2349 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2350 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2351
2352 #define PIC_REFERENCE_P(OP) \
2353 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2354 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2355
2356 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2357 (flag_pic \
2358 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2359 || PIC_OFFSET_P (OP)) \
2360 : NON_PIC_REFERENCE_P (OP))
2361 \f
2362 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2363 that is a valid memory address for an instruction.
2364 The MODE argument is the machine mode for the MEM expression
2365 that wants to use this address. */
2366
2367 #define MODE_DISP_OK_4(X,MODE) \
2368 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2369 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2370
2371 #define MODE_DISP_OK_8(X,MODE) \
2372 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2373 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2374
2375 #undef MODE_DISP_OK_4
2376 #define MODE_DISP_OK_4(X,MODE) \
2377 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2378 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2379 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2380 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2381
2382 #undef MODE_DISP_OK_8
2383 #define MODE_DISP_OK_8(X,MODE) \
2384 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2385 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2386 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2387 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2388
2389 #define BASE_REGISTER_RTX_P(X) \
2390 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2391 || (GET_CODE (X) == SUBREG \
2392 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2393 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2394 && GET_CODE (SUBREG_REG (X)) == REG \
2395 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2396
2397 /* Since this must be r0, which is a single register class, we must check
2398 SUBREGs more carefully, to be sure that we don't accept one that extends
2399 outside the class. */
2400 #define INDEX_REGISTER_RTX_P(X) \
2401 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2402 || (GET_CODE (X) == SUBREG \
2403 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2404 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2405 && GET_CODE (SUBREG_REG (X)) == REG \
2406 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2407
2408 /* Jump to LABEL if X is a valid address RTX. This must also take
2409 REG_OK_STRICT into account when deciding about valid registers, but it uses
2410 the above macros so we are in luck.
2411
2412 Allow REG
2413 REG+disp
2414 REG+r0
2415 REG++
2416 --REG */
2417
2418 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2419 into the FRx registers. We implement this by setting the maximum offset
2420 to zero when the value is SFmode. This also restricts loading of SFmode
2421 values into the integer registers, but that can't be helped. */
2422
2423 /* The SH allows a displacement in a QI or HI amode, but only when the
2424 other operand is R0. GCC doesn't handle this very well, so we forgo
2425 all of that.
2426
2427 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2428 DI can be any number 0..60. */
2429
2430 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2431 do { \
2432 if (GET_CODE (OP) == CONST_INT) \
2433 { \
2434 if (TARGET_SHMEDIA) \
2435 { \
2436 int MODE_SIZE; \
2437 /* Check if this the address of an unaligned load / store. */\
2438 if ((MODE) == VOIDmode) \
2439 { \
2440 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2441 goto LABEL; \
2442 break; \
2443 } \
2444 MODE_SIZE = GET_MODE_SIZE (MODE); \
2445 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2446 && INTVAL (OP) >= -512 * MODE_SIZE \
2447 && INTVAL (OP) < 512 * MODE_SIZE) \
2448 goto LABEL; \
2449 else \
2450 break; \
2451 } \
2452 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2453 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2454 } \
2455 } while(0)
2456
2457 #define ALLOW_INDEXED_ADDRESS \
2458 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2459
2460 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2461 { \
2462 if (BASE_REGISTER_RTX_P (X)) \
2463 goto LABEL; \
2464 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2465 && ! TARGET_SHMEDIA \
2466 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2467 goto LABEL; \
2468 else if (GET_CODE (X) == PLUS \
2469 && ((MODE) != PSImode || reload_completed)) \
2470 { \
2471 rtx xop0 = XEXP ((X), 0); \
2472 rtx xop1 = XEXP ((X), 1); \
2473 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2474 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2475 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2476 || ((xop0 == stack_pointer_rtx \
2477 || xop0 == hard_frame_pointer_rtx) \
2478 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2479 || ((xop1 == stack_pointer_rtx \
2480 || xop1 == hard_frame_pointer_rtx) \
2481 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2482 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2483 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2484 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2485 && TARGET_FMOVD && MODE == DFmode))) \
2486 { \
2487 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2488 goto LABEL; \
2489 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2490 goto LABEL; \
2491 } \
2492 } \
2493 }
2494 \f
2495 /* Try machine-dependent ways of modifying an illegitimate address
2496 to be legitimate. If we find one, return the new, valid address.
2497 This macro is used in only one place: `memory_address' in explow.c.
2498
2499 OLDX is the address as it was before break_out_memory_refs was called.
2500 In some cases it is useful to look at this to decide what needs to be done.
2501
2502 MODE and WIN are passed so that this macro can use
2503 GO_IF_LEGITIMATE_ADDRESS.
2504
2505 It is always safe for this macro to do nothing. It exists to recognize
2506 opportunities to optimize the output.
2507
2508 For the SH, if X is almost suitable for indexing, but the offset is
2509 out of range, convert it into a normal form so that cse has a chance
2510 of reducing the number of address registers used. */
2511
2512 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2513 { \
2514 if (flag_pic) \
2515 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2516 if (GET_CODE (X) == PLUS \
2517 && (GET_MODE_SIZE (MODE) == 4 \
2518 || GET_MODE_SIZE (MODE) == 8) \
2519 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2520 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2521 && ! TARGET_SHMEDIA \
2522 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2523 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2524 { \
2525 rtx index_rtx = XEXP ((X), 1); \
2526 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2527 rtx sum; \
2528 \
2529 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2530 /* On rare occasions, we might get an unaligned pointer \
2531 that is indexed in a way to give an aligned address. \
2532 Therefore, keep the lower two bits in offset_base. */ \
2533 /* Instead of offset_base 128..131 use 124..127, so that \
2534 simple add suffices. */ \
2535 if (offset > 127) \
2536 { \
2537 offset_base = ((offset + 4) & ~60) - 4; \
2538 } \
2539 else \
2540 offset_base = offset & ~60; \
2541 /* Sometimes the normal form does not suit DImode. We \
2542 could avoid that by using smaller ranges, but that \
2543 would give less optimized code when SImode is \
2544 prevalent. */ \
2545 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2546 { \
2547 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2548 GEN_INT (offset_base), NULL_RTX, 0, \
2549 OPTAB_LIB_WIDEN); \
2550 \
2551 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2552 goto WIN; \
2553 } \
2554 } \
2555 }
2556
2557 /* A C compound statement that attempts to replace X, which is an address
2558 that needs reloading, with a valid memory address for an operand of
2559 mode MODE. WIN is a C statement label elsewhere in the code.
2560
2561 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2562 of the address. That will allow inheritance of the address reloads. */
2563
2564 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2565 { \
2566 if (GET_CODE (X) == PLUS \
2567 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2568 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2569 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2570 && ! TARGET_SHMEDIA \
2571 && ! (TARGET_SH4 && (MODE) == DFmode) \
2572 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2573 && (ALLOW_INDEXED_ADDRESS \
2574 || XEXP ((X), 0) == stack_pointer_rtx \
2575 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2576 { \
2577 rtx index_rtx = XEXP (X, 1); \
2578 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2579 rtx sum; \
2580 \
2581 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2582 { \
2583 push_reload (X, NULL_RTX, &X, NULL, \
2584 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2585 (TYPE)); \
2586 goto WIN; \
2587 } \
2588 if (TARGET_SH2E && MODE == SFmode) \
2589 { \
2590 X = copy_rtx (X); \
2591 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2592 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2593 (TYPE)); \
2594 goto WIN; \
2595 } \
2596 /* Instead of offset_base 128..131 use 124..127, so that \
2597 simple add suffices. */ \
2598 if (offset > 127) \
2599 { \
2600 offset_base = ((offset + 4) & ~60) - 4; \
2601 } \
2602 else \
2603 offset_base = offset & ~60; \
2604 /* Sometimes the normal form does not suit DImode. We \
2605 could avoid that by using smaller ranges, but that \
2606 would give less optimized code when SImode is \
2607 prevalent. */ \
2608 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2609 { \
2610 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2611 GEN_INT (offset_base)); \
2612 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2613 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2614 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2615 (TYPE)); \
2616 goto WIN; \
2617 } \
2618 } \
2619 /* We must re-recognize what we created before. */ \
2620 else if (GET_CODE (X) == PLUS \
2621 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2622 && GET_CODE (XEXP (X, 0)) == PLUS \
2623 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2624 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2625 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2626 && ! TARGET_SHMEDIA \
2627 && ! (TARGET_SH2E && MODE == SFmode)) \
2628 { \
2629 /* Because this address is so complex, we know it must have \
2630 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2631 it is already unshared, and needs no further unsharing. */ \
2632 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2633 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2634 goto WIN; \
2635 } \
2636 }
2637
2638 /* Go to LABEL if ADDR (a legitimate address expression)
2639 has an effect that depends on the machine mode it is used for.
2640
2641 ??? Strictly speaking, we should also include all indexed addressing,
2642 because the index scale factor is the length of the operand.
2643 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2644 high if we did that. So we rely on reload to fix things up.
2645
2646 Auto-increment addressing is now treated in recog.c. */
2647
2648 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
2649 \f
2650 /* Specify the machine mode that this machine uses
2651 for the index in the tablejump instruction. */
2652 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2653
2654 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2655 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2656 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2657 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2658 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2659 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2660 : SImode)
2661
2662 /* Define as C expression which evaluates to nonzero if the tablejump
2663 instruction expects the table to contain offsets from the address of the
2664 table.
2665 Do not define this if the table should contain absolute addresses. */
2666 #define CASE_VECTOR_PC_RELATIVE 1
2667
2668 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2669 #define FLOAT_TYPE_SIZE 32
2670
2671 /* Since the SH2e has only `float' support, it is desirable to make all
2672 floating point types equivalent to `float'. */
2673 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2674
2675 #if defined(__SH2E__) || defined(__SH3E__) || defined( __SH4_SINGLE_ONLY__)
2676 #define LIBGCC2_DOUBLE_TYPE_SIZE 32
2677 #else
2678 #define LIBGCC2_DOUBLE_TYPE_SIZE 64
2679 #endif
2680
2681 /* 'char' is signed by default. */
2682 #define DEFAULT_SIGNED_CHAR 1
2683
2684 /* The type of size_t unsigned int. */
2685 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2686
2687 #undef PTRDIFF_TYPE
2688 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2689
2690 #define WCHAR_TYPE "short unsigned int"
2691 #define WCHAR_TYPE_SIZE 16
2692
2693 #define SH_ELF_WCHAR_TYPE "long int"
2694
2695 /* Max number of bytes we can move from memory to memory
2696 in one reasonably fast instruction. */
2697 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2698
2699 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2700 MOVE_MAX is not a compile-time constant. */
2701 #define MAX_MOVE_MAX 8
2702
2703 /* Max number of bytes we want move_by_pieces to be able to copy
2704 efficiently. */
2705 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2706
2707 /* Define if operations between registers always perform the operation
2708 on the full register even if a narrower mode is specified. */
2709 #define WORD_REGISTER_OPERATIONS
2710
2711 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2712 will either zero-extend or sign-extend. The value of this macro should
2713 be the code that says which one of the two operations is implicitly
2714 done, UNKNOWN if none. */
2715 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2716 /* FP registers can load SImode values, but don't implicitly sign-extend
2717 them to DImode. */
2718 #define LOAD_EXTEND_OP(MODE) \
2719 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2720 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2721
2722 /* Define if loading short immediate values into registers sign extends. */
2723 #define SHORT_IMMEDIATES_SIGN_EXTEND
2724
2725 /* Nonzero if access to memory by bytes is no faster than for words. */
2726 #define SLOW_BYTE_ACCESS 1
2727
2728 /* Immediate shift counts are truncated by the output routines (or was it
2729 the assembler?). Shift counts in a register are truncated by SH. Note
2730 that the native compiler puts too large (> 32) immediate shift counts
2731 into a register and shifts by the register, letting the SH decide what
2732 to do instead of doing that itself. */
2733 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2734 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2735 expects - the sign bit is significant - so it appears that we need to
2736 leave this zero for correct SH3 code. */
2737 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2738
2739 /* All integers have the same format so truncation is easy. */
2740 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2741 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2742 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2743
2744 /* Define this if addresses of constant functions
2745 shouldn't be put through pseudo regs where they can be cse'd.
2746 Desirable on machines where ordinary constants are expensive
2747 but a CALL with constant address is cheap. */
2748 /*#define NO_FUNCTION_CSE 1*/
2749
2750 /* The machine modes of pointers and functions. */
2751 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2752 #define FUNCTION_MODE Pmode
2753
2754 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2755 are actually function calls with some special constraints on arguments
2756 and register usage.
2757
2758 These macros tell reorg that the references to arguments and
2759 register clobbers for insns of type sfunc do not appear to happen
2760 until after the millicode call. This allows reorg to put insns
2761 which set the argument registers into the delay slot of the millicode
2762 call -- thus they act more like traditional CALL_INSNs.
2763
2764 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2765 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2766 in particular. */
2767
2768 #define INSN_SETS_ARE_DELAYED(X) \
2769 ((GET_CODE (X) == INSN \
2770 && GET_CODE (PATTERN (X)) != SEQUENCE \
2771 && GET_CODE (PATTERN (X)) != USE \
2772 && GET_CODE (PATTERN (X)) != CLOBBER \
2773 && get_attr_is_sfunc (X)))
2774
2775 #define INSN_REFERENCES_ARE_DELAYED(X) \
2776 ((GET_CODE (X) == INSN \
2777 && GET_CODE (PATTERN (X)) != SEQUENCE \
2778 && GET_CODE (PATTERN (X)) != USE \
2779 && GET_CODE (PATTERN (X)) != CLOBBER \
2780 && get_attr_is_sfunc (X)))
2781
2782 \f
2783 /* Position Independent Code. */
2784
2785 /* We can't directly access anything that contains a symbol,
2786 nor can we indirect via the constant pool. */
2787 #define LEGITIMATE_PIC_OPERAND_P(X) \
2788 ((! nonpic_symbol_mentioned_p (X) \
2789 && (GET_CODE (X) != SYMBOL_REF \
2790 || ! CONSTANT_POOL_ADDRESS_P (X) \
2791 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2792 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2793
2794 #define SYMBOLIC_CONST_P(X) \
2795 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2796 && nonpic_symbol_mentioned_p (X))
2797 \f
2798 /* Compute extra cost of moving data between one register class
2799 and another. */
2800
2801 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2802 uses this information. Hence, the general register <-> floating point
2803 register information here is not used for SFmode. */
2804
2805 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2806 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2807 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2808
2809 #define REGCLASS_HAS_FP_REG(CLASS) \
2810 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2811 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2812
2813 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2814 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2815
2816 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2817 would be so that people with slow memory systems could generate
2818 different code that does fewer memory accesses. */
2819
2820 /* A C expression for the cost of a branch instruction. A value of 1
2821 is the default; other values are interpreted relative to that.
2822 The SH1 does not have delay slots, hence we get a pipeline stall
2823 at every branch. The SH4 is superscalar, so the single delay slot
2824 is not sufficient to keep both pipelines filled. */
2825 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2826 \f
2827 /* Assembler output control. */
2828
2829 /* A C string constant describing how to begin a comment in the target
2830 assembler language. The compiler assumes that the comment will end at
2831 the end of the line. */
2832 #define ASM_COMMENT_START "!"
2833
2834 #define ASM_APP_ON ""
2835 #define ASM_APP_OFF ""
2836 #define FILE_ASM_OP "\t.file\n"
2837 #define SET_ASM_OP "\t.set\t"
2838
2839 /* How to change between sections. */
2840
2841 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2842 #define DATA_SECTION_ASM_OP "\t.data"
2843
2844 #if defined CRT_BEGIN || defined CRT_END
2845 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2846 # undef TEXT_SECTION_ASM_OP
2847 # if __SHMEDIA__ == 1 && __SH5__ == 32
2848 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2849 # else
2850 # define TEXT_SECTION_ASM_OP "\t.text"
2851 # endif
2852 #endif
2853
2854
2855 /* If defined, a C expression whose value is a string containing the
2856 assembler operation to identify the following data as
2857 uninitialized global data. If not defined, and neither
2858 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2859 uninitialized global data will be output in the data section if
2860 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2861 used. */
2862 #ifndef BSS_SECTION_ASM_OP
2863 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2864 #endif
2865
2866 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2867 separate, explicit argument. If you define this macro, it is used
2868 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2869 handling the required alignment of the variable. The alignment is
2870 specified as the number of bits.
2871
2872 Try to use function `asm_output_aligned_bss' defined in file
2873 `varasm.c' when defining this macro. */
2874 #ifndef ASM_OUTPUT_ALIGNED_BSS
2875 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2876 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2877 #endif
2878
2879 /* Define this so that jump tables go in same section as the current function,
2880 which could be text or it could be a user defined section. */
2881 #define JUMP_TABLES_IN_TEXT_SECTION 1
2882
2883 #undef DO_GLOBAL_CTORS_BODY
2884 #define DO_GLOBAL_CTORS_BODY \
2885 { \
2886 typedef void (*pfunc) (void); \
2887 extern pfunc __ctors[]; \
2888 extern pfunc __ctors_end[]; \
2889 pfunc *p; \
2890 for (p = __ctors_end; p > __ctors; ) \
2891 { \
2892 (*--p)(); \
2893 } \
2894 }
2895
2896 #undef DO_GLOBAL_DTORS_BODY
2897 #define DO_GLOBAL_DTORS_BODY \
2898 { \
2899 typedef void (*pfunc) (void); \
2900 extern pfunc __dtors[]; \
2901 extern pfunc __dtors_end[]; \
2902 pfunc *p; \
2903 for (p = __dtors; p < __dtors_end; p++) \
2904 { \
2905 (*p)(); \
2906 } \
2907 }
2908
2909 #define ASM_OUTPUT_REG_PUSH(file, v) \
2910 { \
2911 if (TARGET_SHMEDIA) \
2912 { \
2913 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2914 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2915 } \
2916 else \
2917 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2918 }
2919
2920 #define ASM_OUTPUT_REG_POP(file, v) \
2921 { \
2922 if (TARGET_SHMEDIA) \
2923 { \
2924 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2925 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2926 } \
2927 else \
2928 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2929 }
2930
2931 /* DBX register number for a given compiler register number. */
2932 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2933 to match gdb. */
2934 /* svr4.h undefines this macro, yet we really want to use the same numbers
2935 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
2936 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2937 register exists, so we should return -1 for invalid register numbers. */
2938 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2939
2940 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2941 used to use the encodings 245..260, but that doesn't make sense:
2942 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2943 the FP registers stay the same when switching between compact and media
2944 mode. Hence, we also need to use the same dwarf frame columns.
2945 Likewise, we need to support unwind information for SHmedia registers
2946 even in compact code. */
2947 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2948 (IN_RANGE ((REGNO), \
2949 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2950 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2951 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2952 : ((int) (REGNO) >= FIRST_FP_REG \
2953 && ((int) (REGNO) \
2954 <= (FIRST_FP_REG + \
2955 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2956 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2957 + (TARGET_SH5 ? 77 : 25)) \
2958 : XD_REGISTER_P (REGNO) \
2959 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2960 : TARGET_REGISTER_P (REGNO) \
2961 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2962 : (REGNO) == PR_REG \
2963 ? (TARGET_SH5 ? 18 : 17) \
2964 : (REGNO) == PR_MEDIA_REG \
2965 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2966 : (REGNO) == GBR_REG \
2967 ? (TARGET_SH5 ? 238 : 18) \
2968 : (REGNO) == MACH_REG \
2969 ? (TARGET_SH5 ? 239 : 20) \
2970 : (REGNO) == MACL_REG \
2971 ? (TARGET_SH5 ? 240 : 21) \
2972 : (REGNO) == T_REG \
2973 ? (TARGET_SH5 ? 242 : 22) \
2974 : (REGNO) == FPUL_REG \
2975 ? (TARGET_SH5 ? 244 : 23) \
2976 : (REGNO) == FPSCR_REG \
2977 ? (TARGET_SH5 ? 243 : 24) \
2978 : (unsigned) -1)
2979
2980 /* This is how to output a reference to a symbol_ref. On SH5,
2981 references to non-code symbols must be preceded by `datalabel'. */
2982 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2983 do \
2984 { \
2985 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2986 fputs ("datalabel ", (FILE)); \
2987 assemble_name ((FILE), XSTR ((SYM), 0)); \
2988 } \
2989 while (0)
2990
2991 /* This is how to output an assembler line
2992 that says to advance the location counter
2993 to a multiple of 2**LOG bytes. */
2994
2995 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2996 if ((LOG) != 0) \
2997 fprintf ((FILE), "\t.align %d\n", (LOG))
2998
2999 /* Globalizing directive for a label. */
3000 #define GLOBAL_ASM_OP "\t.global\t"
3001
3002 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3003
3004 /* Output a relative address table. */
3005
3006 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3007 switch (GET_MODE (BODY)) \
3008 { \
3009 case SImode: \
3010 if (TARGET_SH5) \
3011 { \
3012 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3013 (VALUE), (REL)); \
3014 break; \
3015 } \
3016 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3017 break; \
3018 case HImode: \
3019 if (TARGET_SH5) \
3020 { \
3021 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3022 (VALUE), (REL)); \
3023 break; \
3024 } \
3025 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3026 break; \
3027 case QImode: \
3028 if (TARGET_SH5) \
3029 { \
3030 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3031 (VALUE), (REL)); \
3032 break; \
3033 } \
3034 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3035 break; \
3036 default: \
3037 break; \
3038 }
3039
3040 /* Output an absolute table element. */
3041
3042 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3043 if (! optimize || TARGET_BIGTABLE) \
3044 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3045 else \
3046 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3047
3048 \f
3049 /* A C statement to be executed just prior to the output of
3050 assembler code for INSN, to modify the extracted operands so
3051 they will be output differently.
3052
3053 Here the argument OPVEC is the vector containing the operands
3054 extracted from INSN, and NOPERANDS is the number of elements of
3055 the vector which contain meaningful data for this insn.
3056 The contents of this vector are what will be used to convert the insn
3057 template into assembler code, so you can change the assembler output
3058 by changing the contents of the vector. */
3059
3060 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3061 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3062
3063 /* Print operand X (an rtx) in assembler syntax to file FILE.
3064 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3065 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3066
3067 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3068
3069 /* Print a memory address as an operand to reference that memory location. */
3070
3071 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3072
3073 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3074 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3075 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3076
3077 /* Recognize machine-specific patterns that may appear within
3078 constants. Used for PIC-specific UNSPECs. */
3079 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3080 do \
3081 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3082 { \
3083 switch (XINT ((X), 1)) \
3084 { \
3085 case UNSPEC_DATALABEL: \
3086 fputs ("datalabel ", (STREAM)); \
3087 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3088 break; \
3089 case UNSPEC_PIC: \
3090 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3091 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3092 break; \
3093 case UNSPEC_GOT: \
3094 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3095 fputs ("@GOT", (STREAM)); \
3096 break; \
3097 case UNSPEC_GOTOFF: \
3098 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3099 fputs ("@GOTOFF", (STREAM)); \
3100 break; \
3101 case UNSPEC_PLT: \
3102 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3103 fputs ("@PLT", (STREAM)); \
3104 break; \
3105 case UNSPEC_GOTPLT: \
3106 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3107 fputs ("@GOTPLT", (STREAM)); \
3108 break; \
3109 case UNSPEC_DTPOFF: \
3110 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3111 fputs ("@DTPOFF", (STREAM)); \
3112 break; \
3113 case UNSPEC_GOTTPOFF: \
3114 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3115 fputs ("@GOTTPOFF", (STREAM)); \
3116 break; \
3117 case UNSPEC_TPOFF: \
3118 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3119 fputs ("@TPOFF", (STREAM)); \
3120 break; \
3121 case UNSPEC_CALLER: \
3122 { \
3123 char name[32]; \
3124 /* LPCS stands for Label for PIC Call Site. */ \
3125 ASM_GENERATE_INTERNAL_LABEL \
3126 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3127 assemble_name ((STREAM), name); \
3128 } \
3129 break; \
3130 default: \
3131 goto FAIL; \
3132 } \
3133 break; \
3134 } \
3135 else \
3136 goto FAIL; \
3137 while (0)
3138
3139 \f
3140 extern struct rtx_def *sh_compare_op0;
3141 extern struct rtx_def *sh_compare_op1;
3142
3143 /* Which processor to schedule for. The elements of the enumeration must
3144 match exactly the cpu attribute in the sh.md file. */
3145
3146 enum processor_type {
3147 PROCESSOR_SH1,
3148 PROCESSOR_SH2,
3149 PROCESSOR_SH2E,
3150 PROCESSOR_SH2A,
3151 PROCESSOR_SH3,
3152 PROCESSOR_SH3E,
3153 PROCESSOR_SH4,
3154 PROCESSOR_SH4A,
3155 PROCESSOR_SH5
3156 };
3157
3158 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3159 extern enum processor_type sh_cpu;
3160
3161 extern int optimize; /* needed for gen_casesi. */
3162
3163 enum mdep_reorg_phase_e
3164 {
3165 SH_BEFORE_MDEP_REORG,
3166 SH_INSERT_USES_LABELS,
3167 SH_SHORTEN_BRANCHES0,
3168 SH_FIXUP_PCLOAD,
3169 SH_SHORTEN_BRANCHES1,
3170 SH_AFTER_MDEP_REORG
3171 };
3172
3173 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3174
3175 /* Handle Renesas compiler's pragmas. */
3176 #define REGISTER_TARGET_PRAGMAS() do { \
3177 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3178 c_register_pragma (0, "trapa", sh_pr_trapa); \
3179 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3180 } while (0)
3181
3182 extern tree sh_deferred_function_attributes;
3183 extern tree *sh_deferred_function_attributes_tail;
3184
3185 /* Set when processing a function with interrupt attribute. */
3186
3187 extern int current_function_interrupt;
3188
3189 \f
3190 /* Instructions with unfilled delay slots take up an
3191 extra two bytes for the nop in the delay slot.
3192 sh-dsp parallel processing insns are four bytes long. */
3193
3194 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3195 (LENGTH) += sh_insn_length_adjustment (X);
3196 \f
3197 /* Define this macro if it is advisable to hold scalars in registers
3198 in a wider mode than that declared by the program. In such cases,
3199 the value is constrained to be within the bounds of the declared
3200 type, but kept valid in the wider mode. The signedness of the
3201 extension may differ from that of the type.
3202
3203 Leaving the unsignedp unchanged gives better code than always setting it
3204 to 0. This is despite the fact that we have only signed char and short
3205 load instructions. */
3206 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3207 if (GET_MODE_CLASS (MODE) == MODE_INT \
3208 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3209 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3210 (MODE) = (TARGET_SH1 ? SImode \
3211 : TARGET_SHMEDIA32 ? SImode : DImode);
3212
3213 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3214
3215 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3216
3217 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3218 and popping arguments. However, we do have push/pop instructions, and
3219 rather limited offsets (4 bits) in load/store instructions, so it isn't
3220 clear if this would give better code. If implemented, should check for
3221 compatibility problems. */
3222
3223 #define SH_DYNAMIC_SHIFT_COST \
3224 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3225
3226
3227 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3228
3229 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3230
3231 #define ACTUAL_NORMAL_MODE(ENTITY) \
3232 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3233
3234 #define NORMAL_MODE(ENTITY) \
3235 (sh_cfun_interrupt_handler_p () \
3236 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3237 : ACTUAL_NORMAL_MODE (ENTITY))
3238
3239 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3240
3241 #define MODE_EXIT(ENTITY) \
3242 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3243
3244 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3245 && (REGNO) == FPSCR_REG)
3246
3247 #define MODE_NEEDED(ENTITY, INSN) \
3248 (recog_memoized (INSN) >= 0 \
3249 ? get_attr_fp_mode (INSN) \
3250 : FP_MODE_NONE)
3251
3252 #define MODE_AFTER(MODE, INSN) \
3253 (TARGET_HITACHI \
3254 && recog_memoized (INSN) >= 0 \
3255 && get_attr_fp_set (INSN) != FP_SET_NONE \
3256 ? (int) get_attr_fp_set (INSN) \
3257 : (MODE))
3258
3259 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3260 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3261
3262 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3263 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3264
3265 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3266 sh_can_redirect_branch ((INSN), (SEQ))
3267
3268 #define DWARF_FRAME_RETURN_COLUMN \
3269 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3270
3271 #define EH_RETURN_DATA_REGNO(N) \
3272 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3273
3274 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3275 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3276
3277 /* We have to distinguish between code and data, so that we apply
3278 datalabel where and only where appropriate. Use sdataN for data. */
3279 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3280 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3281 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3282 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3283
3284 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3285 indirect are handled automatically. */
3286 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3287 do { \
3288 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3289 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3290 { \
3291 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3292 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3293 if (0) goto DONE; \
3294 } \
3295 } while (0)
3296
3297 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3298 /* SH constant pool breaks the devices in crtstuff.c to control section
3299 in where code resides. We have to write it as asm code. */
3300 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3301 asm (SECTION_OP "\n\
3302 mov.l 1f,r1\n\
3303 mova 2f,r0\n\
3304 braf r1\n\
3305 lds r0,pr\n\
3306 0: .p2align 2\n\
3307 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3308 2:\n" TEXT_SECTION_ASM_OP);
3309 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3310
3311 /* FIXME: middle-end support for highpart optimizations is missing. */
3312 #define high_life_started reload_in_progress
3313
3314 #endif /* ! GCC_SH_H */
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