| blob | b5667b9d1edef9e46b5c303de9787dc57684cbad |
1 ;; Machine description for RISC-V 'V' Extension for GNU compiler.
2 ;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
3 ;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; This file describes the RISC-V 'V' Extension, Version 1.0.
22 ;;
23 ;; This file include :
24 ;;
25 ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
26 ;; - Auto-vectorization (autovec.md)
27 ;; - Optimization (autovec-opt.md)
29 (include "vector-iterators.md")
31 (define_constants [
32 (INVALID_ATTRIBUTE 255)
33 (X0_REGNUM 0)
34 ])
36 ;; True if the type is RVV instructions that include VTYPE
37 ;; global status register in the use op list.
38 ;; We known VTYPE has 4 fields: SEW, LMUL, TA, MA.
39 ;; The instruction need any of VTYPE field is set as true
40 ;; in this attribute.
41 (define_attr "has_vtype_op" "false,true"
42 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
43 vldux,vldox,vstux,vstox,vldff,\
44 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
45 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
46 vsalu,vaalu,vsmul,vsshift,vnclip,\
47 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
48 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
49 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
50 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
51 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
52 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,\
53 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
54 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
55 vssegtux,vssegtox,vlsegdff")
56 (const_string "true")]
57 (const_string "false")))
59 ;; True if the type is RVV instructions that include VL
60 ;; global status register in the use op list.
61 ;; The instruction need vector length to be specified is set
62 ;; in this attribute.
63 (define_attr "has_vl_op" "false,true"
64 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
65 vldux,vldox,vstux,vstox,vldff,\
66 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
67 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
68 vsalu,vaalu,vsmul,vsshift,vnclip,\
69 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
70 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
71 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
72 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
73 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
74 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovxv,vfmovfv,\
75 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
76 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
77 vssegtux,vssegtox,vlsegdff")
78 (const_string "true")]
79 (const_string "false")))
81 ;; The default SEW of RVV instruction. This attribute doesn't mean the instruction
82 ;; is necessary to require SEW check for example vlm.v which require ratio to
83 ;; check. However, we need default value of SEW for vsetvl instruction since there
84 ;; is no field for ratio in the vsetvl instruction encoding.
85 (define_attr "sew" ""
86 (cond [(eq_attr "mode" "RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\
87 RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,\
88 RVVM1x8QI,RVVMF2x8QI,RVVMF4x8QI,RVVMF8x8QI,\
89 RVVM1x7QI,RVVMF2x7QI,RVVMF4x7QI,RVVMF8x7QI,\
90 RVVM1x6QI,RVVMF2x6QI,RVVMF4x6QI,RVVMF8x6QI,\
91 RVVM1x5QI,RVVMF2x5QI,RVVMF4x5QI,RVVMF8x5QI,\
92 RVVM2x4QI,RVVM1x4QI,RVVMF2x4QI,RVVMF4x4QI,RVVMF8x4QI,\
93 RVVM2x3QI,RVVM1x3QI,RVVMF2x3QI,RVVMF4x3QI,RVVMF8x3QI,\
94 RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4x2QI,RVVMF8x2QI,\
95 V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,\
96 V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI")
97 (const_int 8)
98 (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,\
99 RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\
100 RVVM1x7HI,RVVMF2x7HI,RVVMF4x7HI,\
101 RVVM1x6HI,RVVMF2x6HI,RVVMF4x6HI,\
102 RVVM1x5HI,RVVMF2x5HI,RVVMF4x5HI,\
103 RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,\
104 RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,\
105 RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,\
106 RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,\
107 RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,\
108 RVVM1x7HF,RVVMF2x7HF,RVVMF4x7HF,\
109 RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,\
110 RVVM1x5HF,RVVMF2x5HF,RVVMF4x5HF,\
111 RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF,RVVMF4x4HF,\
112 RVVM2x3HF,RVVM1x3HF,RVVMF2x3HF,RVVMF4x3HF,\
113 RVVM4x2HF,RVVM2x2HF,RVVM1x2HF,RVVMF2x2HF,RVVMF4x2HF,\
114 V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI,\
115 V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V2048HF")
116 (const_int 16)
117 (eq_attr "mode" "RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI,\
118 RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF,\
119 RVVM1x8SI,RVVMF2x8SI,\
120 RVVM1x7SI,RVVMF2x7SI,\
121 RVVM1x6SI,RVVMF2x6SI,\
122 RVVM1x5SI,RVVMF2x5SI,\
123 RVVMF2x4SI,RVVMF2x3SI,\
124 RVVM2x4SI,RVVM1x4SI,\
125 RVVM2x3SI,RVVM1x3SI,\
126 RVVM4x2SI,RVVM2x2SI,RVVM1x2SI,RVVMF2x2SI,\
127 RVVM1x8SF,RVVMF2x8SF,\
128 RVVM1x7SF,RVVMF2x7SF,\
129 RVVM1x6SF,RVVMF2x6SF,\
130 RVVM1x5SF,RVVMF2x5SF,\
131 RVVM2x4SF,RVVM1x4SF,RVVMF2x4SF,\
132 RVVM2x3SF,RVVM1x3SF,RVVMF2x3SF,\
133 RVVM4x2SF,RVVM2x2SF,RVVM1x2SF,RVVMF2x2SF,\
134 V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI,\
135 V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF")
136 (const_int 32)
137 (eq_attr "mode" "RVVM8DI,RVVM4DI,RVVM2DI,RVVM1DI,\
138 RVVM8DF,RVVM4DF,RVVM2DF,RVVM1DF,\
139 RVVM1x8DI,RVVM1x7DI,RVVM1x6DI,RVVM1x5DI,\
140 RVVM2x4DI,RVVM1x4DI,\
141 RVVM2x3DI,RVVM1x3DI,\
142 RVVM4x2DI,RVVM2x2DI,RVVM1x2DI,\
143 RVVM1x8DF,RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,\
144 RVVM2x4DF,RVVM1x4DF,\
145 RVVM2x3DF,RVVM1x3DF,\
146 RVVM4x2DF,RVVM2x2DF,RVVM1x2DF,\
147 V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,\
148 V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF")
149 (const_int 64)]
150 (const_int INVALID_ATTRIBUTE)))
152 ;; Ditto to LMUL.
153 (define_attr "vlmul" ""
154 (cond [(eq_attr "mode" "RVVM8QI,RVVM1BI") (symbol_ref "riscv_vector::LMUL_8")
155 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (symbol_ref "riscv_vector::LMUL_4")
156 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (symbol_ref "riscv_vector::LMUL_2")
157 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (symbol_ref "riscv_vector::LMUL_1")
158 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (symbol_ref "riscv_vector::LMUL_F2")
159 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (symbol_ref "riscv_vector::LMUL_F4")
160 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (symbol_ref "riscv_vector::LMUL_F8")
161 (eq_attr "mode" "RVVM8HI") (symbol_ref "riscv_vector::LMUL_8")
162 (eq_attr "mode" "RVVM4HI") (symbol_ref "riscv_vector::LMUL_4")
163 (eq_attr "mode" "RVVM2HI") (symbol_ref "riscv_vector::LMUL_2")
164 (eq_attr "mode" "RVVM1HI") (symbol_ref "riscv_vector::LMUL_1")
165 (eq_attr "mode" "RVVMF2HI") (symbol_ref "riscv_vector::LMUL_F2")
166 (eq_attr "mode" "RVVMF4HI") (symbol_ref "riscv_vector::LMUL_F4")
167 (eq_attr "mode" "RVVM8HF") (symbol_ref "riscv_vector::LMUL_8")
168 (eq_attr "mode" "RVVM4HF") (symbol_ref "riscv_vector::LMUL_4")
169 (eq_attr "mode" "RVVM2HF") (symbol_ref "riscv_vector::LMUL_2")
170 (eq_attr "mode" "RVVM1HF") (symbol_ref "riscv_vector::LMUL_1")
171 (eq_attr "mode" "RVVMF2HF") (symbol_ref "riscv_vector::LMUL_F2")
172 (eq_attr "mode" "RVVMF4HF") (symbol_ref "riscv_vector::LMUL_F4")
173 (eq_attr "mode" "RVVM8SI") (symbol_ref "riscv_vector::LMUL_8")
174 (eq_attr "mode" "RVVM4SI") (symbol_ref "riscv_vector::LMUL_4")
175 (eq_attr "mode" "RVVM2SI") (symbol_ref "riscv_vector::LMUL_2")
176 (eq_attr "mode" "RVVM1SI") (symbol_ref "riscv_vector::LMUL_1")
177 (eq_attr "mode" "RVVMF2SI") (symbol_ref "riscv_vector::LMUL_F2")
178 (eq_attr "mode" "RVVM8SF") (symbol_ref "riscv_vector::LMUL_8")
179 (eq_attr "mode" "RVVM4SF") (symbol_ref "riscv_vector::LMUL_4")
180 (eq_attr "mode" "RVVM2SF") (symbol_ref "riscv_vector::LMUL_2")
181 (eq_attr "mode" "RVVM1SF") (symbol_ref "riscv_vector::LMUL_1")
182 (eq_attr "mode" "RVVMF2SF") (symbol_ref "riscv_vector::LMUL_F2")
183 (eq_attr "mode" "RVVM8DI") (symbol_ref "riscv_vector::LMUL_8")
184 (eq_attr "mode" "RVVM4DI") (symbol_ref "riscv_vector::LMUL_4")
185 (eq_attr "mode" "RVVM2DI") (symbol_ref "riscv_vector::LMUL_2")
186 (eq_attr "mode" "RVVM1DI") (symbol_ref "riscv_vector::LMUL_1")
187 (eq_attr "mode" "RVVM8DF") (symbol_ref "riscv_vector::LMUL_8")
188 (eq_attr "mode" "RVVM4DF") (symbol_ref "riscv_vector::LMUL_4")
189 (eq_attr "mode" "RVVM2DF") (symbol_ref "riscv_vector::LMUL_2")
190 (eq_attr "mode" "RVVM1DF") (symbol_ref "riscv_vector::LMUL_1")
191 (eq_attr "mode" "RVVM1x8QI") (symbol_ref "riscv_vector::LMUL_1")
192 (eq_attr "mode" "RVVMF2x8QI") (symbol_ref "riscv_vector::LMUL_F2")
193 (eq_attr "mode" "RVVMF4x8QI") (symbol_ref "riscv_vector::LMUL_F4")
194 (eq_attr "mode" "RVVMF8x8QI") (symbol_ref "riscv_vector::LMUL_F8")
195 (eq_attr "mode" "RVVM1x7QI") (symbol_ref "riscv_vector::LMUL_1")
196 (eq_attr "mode" "RVVMF2x7QI") (symbol_ref "riscv_vector::LMUL_F2")
197 (eq_attr "mode" "RVVMF4x7QI") (symbol_ref "riscv_vector::LMUL_F4")
198 (eq_attr "mode" "RVVMF8x7QI") (symbol_ref "riscv_vector::LMUL_F8")
199 (eq_attr "mode" "RVVM1x6QI") (symbol_ref "riscv_vector::LMUL_1")
200 (eq_attr "mode" "RVVMF2x6QI") (symbol_ref "riscv_vector::LMUL_F2")
201 (eq_attr "mode" "RVVMF4x6QI") (symbol_ref "riscv_vector::LMUL_F4")
202 (eq_attr "mode" "RVVMF8x6QI") (symbol_ref "riscv_vector::LMUL_F8")
203 (eq_attr "mode" "RVVM1x5QI") (symbol_ref "riscv_vector::LMUL_1")
204 (eq_attr "mode" "RVVMF2x5QI") (symbol_ref "riscv_vector::LMUL_F2")
205 (eq_attr "mode" "RVVMF4x5QI") (symbol_ref "riscv_vector::LMUL_F4")
206 (eq_attr "mode" "RVVMF8x5QI") (symbol_ref "riscv_vector::LMUL_F8")
207 (eq_attr "mode" "RVVM2x4QI") (symbol_ref "riscv_vector::LMUL_2")
208 (eq_attr "mode" "RVVM1x4QI") (symbol_ref "riscv_vector::LMUL_1")
209 (eq_attr "mode" "RVVMF2x4QI") (symbol_ref "riscv_vector::LMUL_F2")
210 (eq_attr "mode" "RVVMF4x4QI") (symbol_ref "riscv_vector::LMUL_F4")
211 (eq_attr "mode" "RVVMF8x4QI") (symbol_ref "riscv_vector::LMUL_F8")
212 (eq_attr "mode" "RVVM2x3QI") (symbol_ref "riscv_vector::LMUL_2")
213 (eq_attr "mode" "RVVM1x3QI") (symbol_ref "riscv_vector::LMUL_1")
214 (eq_attr "mode" "RVVMF2x3QI") (symbol_ref "riscv_vector::LMUL_F2")
215 (eq_attr "mode" "RVVMF4x3QI") (symbol_ref "riscv_vector::LMUL_F4")
216 (eq_attr "mode" "RVVMF8x3QI") (symbol_ref "riscv_vector::LMUL_F8")
217 (eq_attr "mode" "RVVM4x2QI") (symbol_ref "riscv_vector::LMUL_4")
218 (eq_attr "mode" "RVVM2x2QI") (symbol_ref "riscv_vector::LMUL_2")
219 (eq_attr "mode" "RVVM1x2QI") (symbol_ref "riscv_vector::LMUL_1")
220 (eq_attr "mode" "RVVMF2x2QI") (symbol_ref "riscv_vector::LMUL_F2")
221 (eq_attr "mode" "RVVMF4x2QI") (symbol_ref "riscv_vector::LMUL_F4")
222 (eq_attr "mode" "RVVMF8x2QI") (symbol_ref "riscv_vector::LMUL_F8")
223 (eq_attr "mode" "RVVM1x8HI") (symbol_ref "riscv_vector::LMUL_1")
224 (eq_attr "mode" "RVVMF2x8HI") (symbol_ref "riscv_vector::LMUL_F2")
225 (eq_attr "mode" "RVVMF4x8HI") (symbol_ref "riscv_vector::LMUL_F4")
226 (eq_attr "mode" "RVVM1x7HI") (symbol_ref "riscv_vector::LMUL_1")
227 (eq_attr "mode" "RVVMF2x7HI") (symbol_ref "riscv_vector::LMUL_F2")
228 (eq_attr "mode" "RVVMF4x7HI") (symbol_ref "riscv_vector::LMUL_F4")
229 (eq_attr "mode" "RVVM1x6HI") (symbol_ref "riscv_vector::LMUL_1")
230 (eq_attr "mode" "RVVMF2x6HI") (symbol_ref "riscv_vector::LMUL_F2")
231 (eq_attr "mode" "RVVMF4x6HI") (symbol_ref "riscv_vector::LMUL_F4")
232 (eq_attr "mode" "RVVM1x5HI") (symbol_ref "riscv_vector::LMUL_1")
233 (eq_attr "mode" "RVVMF2x5HI") (symbol_ref "riscv_vector::LMUL_F2")
234 (eq_attr "mode" "RVVMF4x5HI") (symbol_ref "riscv_vector::LMUL_F4")
235 (eq_attr "mode" "RVVM2x4HI") (symbol_ref "riscv_vector::LMUL_2")
236 (eq_attr "mode" "RVVM1x4HI") (symbol_ref "riscv_vector::LMUL_1")
237 (eq_attr "mode" "RVVMF2x4HI") (symbol_ref "riscv_vector::LMUL_F2")
238 (eq_attr "mode" "RVVMF4x4HI") (symbol_ref "riscv_vector::LMUL_F4")
239 (eq_attr "mode" "RVVM2x3HI") (symbol_ref "riscv_vector::LMUL_2")
240 (eq_attr "mode" "RVVM1x3HI") (symbol_ref "riscv_vector::LMUL_1")
241 (eq_attr "mode" "RVVMF2x3HI") (symbol_ref "riscv_vector::LMUL_F2")
242 (eq_attr "mode" "RVVMF4x3HI") (symbol_ref "riscv_vector::LMUL_F4")
243 (eq_attr "mode" "RVVM4x2HI") (symbol_ref "riscv_vector::LMUL_4")
244 (eq_attr "mode" "RVVM2x2HI") (symbol_ref "riscv_vector::LMUL_2")
245 (eq_attr "mode" "RVVM1x2HI") (symbol_ref "riscv_vector::LMUL_1")
246 (eq_attr "mode" "RVVMF2x2HI") (symbol_ref "riscv_vector::LMUL_F2")
247 (eq_attr "mode" "RVVMF4x2HI") (symbol_ref "riscv_vector::LMUL_F4")
248 (eq_attr "mode" "RVVM1x8HF") (symbol_ref "riscv_vector::LMUL_1")
249 (eq_attr "mode" "RVVMF2x8HF") (symbol_ref "riscv_vector::LMUL_F2")
250 (eq_attr "mode" "RVVMF4x8HF") (symbol_ref "riscv_vector::LMUL_F4")
251 (eq_attr "mode" "RVVM1x7HF") (symbol_ref "riscv_vector::LMUL_1")
252 (eq_attr "mode" "RVVMF2x7HF") (symbol_ref "riscv_vector::LMUL_F2")
253 (eq_attr "mode" "RVVMF4x7HF") (symbol_ref "riscv_vector::LMUL_F4")
254 (eq_attr "mode" "RVVM1x6HF") (symbol_ref "riscv_vector::LMUL_1")
255 (eq_attr "mode" "RVVMF2x6HF") (symbol_ref "riscv_vector::LMUL_F2")
256 (eq_attr "mode" "RVVMF4x6HF") (symbol_ref "riscv_vector::LMUL_F4")
257 (eq_attr "mode" "RVVM1x5HF") (symbol_ref "riscv_vector::LMUL_1")
258 (eq_attr "mode" "RVVMF2x5HF") (symbol_ref "riscv_vector::LMUL_F2")
259 (eq_attr "mode" "RVVMF4x5HF") (symbol_ref "riscv_vector::LMUL_F4")
260 (eq_attr "mode" "RVVM2x4HF") (symbol_ref "riscv_vector::LMUL_2")
261 (eq_attr "mode" "RVVM1x4HF") (symbol_ref "riscv_vector::LMUL_1")
262 (eq_attr "mode" "RVVMF2x4HF") (symbol_ref "riscv_vector::LMUL_F2")
263 (eq_attr "mode" "RVVMF4x4HF") (symbol_ref "riscv_vector::LMUL_F4")
264 (eq_attr "mode" "RVVM2x3HF") (symbol_ref "riscv_vector::LMUL_2")
265 (eq_attr "mode" "RVVM1x3HF") (symbol_ref "riscv_vector::LMUL_1")
266 (eq_attr "mode" "RVVMF2x3HF") (symbol_ref "riscv_vector::LMUL_F2")
267 (eq_attr "mode" "RVVMF4x3HF") (symbol_ref "riscv_vector::LMUL_F4")
268 (eq_attr "mode" "RVVM4x2HF") (symbol_ref "riscv_vector::LMUL_4")
269 (eq_attr "mode" "RVVM2x2HF") (symbol_ref "riscv_vector::LMUL_2")
270 (eq_attr "mode" "RVVM1x2HF") (symbol_ref "riscv_vector::LMUL_1")
271 (eq_attr "mode" "RVVMF2x2HF") (symbol_ref "riscv_vector::LMUL_F2")
272 (eq_attr "mode" "RVVMF4x2HF") (symbol_ref "riscv_vector::LMUL_F4")
273 (eq_attr "mode" "RVVM1x8SI") (symbol_ref "riscv_vector::LMUL_1")
274 (eq_attr "mode" "RVVMF2x8SI") (symbol_ref "riscv_vector::LMUL_F2")
275 (eq_attr "mode" "RVVM1x7SI") (symbol_ref "riscv_vector::LMUL_1")
276 (eq_attr "mode" "RVVMF2x7SI") (symbol_ref "riscv_vector::LMUL_F2")
277 (eq_attr "mode" "RVVM1x6SI") (symbol_ref "riscv_vector::LMUL_1")
278 (eq_attr "mode" "RVVMF2x6SI") (symbol_ref "riscv_vector::LMUL_F2")
279 (eq_attr "mode" "RVVM1x5SI") (symbol_ref "riscv_vector::LMUL_1")
280 (eq_attr "mode" "RVVMF2x5SI") (symbol_ref "riscv_vector::LMUL_F2")
281 (eq_attr "mode" "RVVM2x4SI") (symbol_ref "riscv_vector::LMUL_2")
282 (eq_attr "mode" "RVVM1x4SI") (symbol_ref "riscv_vector::LMUL_1")
283 (eq_attr "mode" "RVVMF2x4SI") (symbol_ref "riscv_vector::LMUL_F2")
284 (eq_attr "mode" "RVVM2x3SI") (symbol_ref "riscv_vector::LMUL_2")
285 (eq_attr "mode" "RVVM1x3SI") (symbol_ref "riscv_vector::LMUL_1")
286 (eq_attr "mode" "RVVMF2x3SI") (symbol_ref "riscv_vector::LMUL_F2")
287 (eq_attr "mode" "RVVM4x2SI") (symbol_ref "riscv_vector::LMUL_4")
288 (eq_attr "mode" "RVVM2x2SI") (symbol_ref "riscv_vector::LMUL_2")
289 (eq_attr "mode" "RVVM1x2SI") (symbol_ref "riscv_vector::LMUL_1")
290 (eq_attr "mode" "RVVMF2x2SI") (symbol_ref "riscv_vector::LMUL_F2")
291 (eq_attr "mode" "RVVM1x8SF") (symbol_ref "riscv_vector::LMUL_1")
292 (eq_attr "mode" "RVVMF2x8SF") (symbol_ref "riscv_vector::LMUL_F2")
293 (eq_attr "mode" "RVVM1x7SF") (symbol_ref "riscv_vector::LMUL_1")
294 (eq_attr "mode" "RVVMF2x7SF") (symbol_ref "riscv_vector::LMUL_F2")
295 (eq_attr "mode" "RVVM1x6SF") (symbol_ref "riscv_vector::LMUL_1")
296 (eq_attr "mode" "RVVMF2x6SF") (symbol_ref "riscv_vector::LMUL_F2")
297 (eq_attr "mode" "RVVM1x5SF") (symbol_ref "riscv_vector::LMUL_1")
298 (eq_attr "mode" "RVVMF2x5SF") (symbol_ref "riscv_vector::LMUL_F2")
299 (eq_attr "mode" "RVVM2x4SF") (symbol_ref "riscv_vector::LMUL_2")
300 (eq_attr "mode" "RVVM1x4SF") (symbol_ref "riscv_vector::LMUL_1")
301 (eq_attr "mode" "RVVMF2x4SF") (symbol_ref "riscv_vector::LMUL_F2")
302 (eq_attr "mode" "RVVM2x3SF") (symbol_ref "riscv_vector::LMUL_2")
303 (eq_attr "mode" "RVVM1x3SF") (symbol_ref "riscv_vector::LMUL_1")
304 (eq_attr "mode" "RVVMF2x3SF") (symbol_ref "riscv_vector::LMUL_F2")
305 (eq_attr "mode" "RVVM4x2SF") (symbol_ref "riscv_vector::LMUL_4")
306 (eq_attr "mode" "RVVM2x2SF") (symbol_ref "riscv_vector::LMUL_2")
307 (eq_attr "mode" "RVVM1x2SF") (symbol_ref "riscv_vector::LMUL_1")
308 (eq_attr "mode" "RVVMF2x2SF") (symbol_ref "riscv_vector::LMUL_F2")
309 (eq_attr "mode" "RVVM1x8DI") (symbol_ref "riscv_vector::LMUL_1")
310 (eq_attr "mode" "RVVM1x7DI") (symbol_ref "riscv_vector::LMUL_1")
311 (eq_attr "mode" "RVVM1x6DI") (symbol_ref "riscv_vector::LMUL_1")
312 (eq_attr "mode" "RVVM1x5DI") (symbol_ref "riscv_vector::LMUL_1")
313 (eq_attr "mode" "RVVM2x4DI") (symbol_ref "riscv_vector::LMUL_2")
314 (eq_attr "mode" "RVVM1x4DI") (symbol_ref "riscv_vector::LMUL_1")
315 (eq_attr "mode" "RVVM2x3DI") (symbol_ref "riscv_vector::LMUL_2")
316 (eq_attr "mode" "RVVM1x3DI") (symbol_ref "riscv_vector::LMUL_1")
317 (eq_attr "mode" "RVVM4x2DI") (symbol_ref "riscv_vector::LMUL_4")
318 (eq_attr "mode" "RVVM2x2DI") (symbol_ref "riscv_vector::LMUL_2")
319 (eq_attr "mode" "RVVM1x2DI") (symbol_ref "riscv_vector::LMUL_1")
320 (eq_attr "mode" "RVVM1x8DF") (symbol_ref "riscv_vector::LMUL_1")
321 (eq_attr "mode" "RVVM1x7DF") (symbol_ref "riscv_vector::LMUL_1")
322 (eq_attr "mode" "RVVM1x6DF") (symbol_ref "riscv_vector::LMUL_1")
323 (eq_attr "mode" "RVVM1x5DF") (symbol_ref "riscv_vector::LMUL_1")
324 (eq_attr "mode" "RVVM2x4DF") (symbol_ref "riscv_vector::LMUL_2")
325 (eq_attr "mode" "RVVM1x4DF") (symbol_ref "riscv_vector::LMUL_1")
326 (eq_attr "mode" "RVVM2x3DF") (symbol_ref "riscv_vector::LMUL_2")
327 (eq_attr "mode" "RVVM1x3DF") (symbol_ref "riscv_vector::LMUL_1")
328 (eq_attr "mode" "RVVM4x2DF") (symbol_ref "riscv_vector::LMUL_4")
329 (eq_attr "mode" "RVVM2x2DF") (symbol_ref "riscv_vector::LMUL_2")
330 (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1")
332 ;; VLS modes.
333 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_vlmul(E_V1QImode)")
334 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_vlmul(E_V2QImode)")
335 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_vlmul(E_V4QImode)")
336 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_vlmul(E_V8QImode)")
337 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
338 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_vlmul(E_V32QImode)")
339 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_vlmul(E_V64QImode)")
340 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_vlmul(E_V128QImode)")
341 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_vlmul(E_V256QImode)")
342 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_vlmul(E_V512QImode)")
343 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_vlmul(E_V1024QImode)")
344 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_vlmul(E_V2048QImode)")
345 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_vlmul(E_V4096QImode)")
346 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_vlmul(E_V1HImode)")
347 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_vlmul(E_V2HImode)")
348 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_vlmul(E_V4HImode)")
349 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_vlmul(E_V8HImode)")
350 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_vlmul(E_V16HImode)")
351 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_vlmul(E_V32HImode)")
352 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_vlmul(E_V64HImode)")
353 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_vlmul(E_V128HImode)")
354 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_vlmul(E_V256HImode)")
355 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_vlmul(E_V512HImode)")
356 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_vlmul(E_V1024HImode)")
357 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_vlmul(E_V2048HImode)")
358 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_vlmul(E_V1SImode)")
359 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_vlmul(E_V2SImode)")
360 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_vlmul(E_V4SImode)")
361 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_vlmul(E_V8SImode)")
362 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_vlmul(E_V16SImode)")
363 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_vlmul(E_V32SImode)")
364 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_vlmul(E_V64SImode)")
365 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_vlmul(E_V128SImode)")
366 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_vlmul(E_V256SImode)")
367 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_vlmul(E_V512SImode)")
368 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_vlmul(E_V1024SImode)")
369 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_vlmul(E_V1DImode)")
370 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_vlmul(E_V2DImode)")
371 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_vlmul(E_V4DImode)")
372 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_vlmul(E_V8DImode)")
373 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_vlmul(E_V16DImode)")
374 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_vlmul(E_V32DImode)")
375 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_vlmul(E_V64DImode)")
376 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_vlmul(E_V128DImode)")
377 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_vlmul(E_V256DImode)")
378 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_vlmul(E_V512DImode)")
379 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_vlmul(E_V1HFmode)")
380 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_vlmul(E_V2HFmode)")
381 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_vlmul(E_V4HFmode)")
382 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_vlmul(E_V8HFmode)")
383 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_vlmul(E_V16HFmode)")
384 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_vlmul(E_V32HFmode)")
385 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_vlmul(E_V64HFmode)")
386 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_vlmul(E_V128HFmode)")
387 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_vlmul(E_V256HFmode)")
388 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_vlmul(E_V512HFmode)")
389 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_vlmul(E_V1024HFmode)")
390 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_vlmul(E_V2048HFmode)")
391 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_vlmul(E_V1SFmode)")
392 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_vlmul(E_V2SFmode)")
393 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_vlmul(E_V4SFmode)")
394 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_vlmul(E_V8SFmode)")
395 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_vlmul(E_V16SFmode)")
396 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_vlmul(E_V32SFmode)")
397 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_vlmul(E_V64SFmode)")
398 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_vlmul(E_V128SFmode)")
399 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_vlmul(E_V256SFmode)")
400 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_vlmul(E_V512SFmode)")
401 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_vlmul(E_V1024SFmode)")
402 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_vlmul(E_V1DFmode)")
403 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_vlmul(E_V2DFmode)")
404 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_vlmul(E_V4DFmode)")
405 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_vlmul(E_V8DFmode)")
406 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_vlmul(E_V16DFmode)")
407 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_vlmul(E_V32DFmode)")
408 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_vlmul(E_V64DFmode)")
409 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_vlmul(E_V128DFmode)")
410 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_vlmul(E_V256DFmode)")
411 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_vlmul(E_V512DFmode)")]
412 (const_int INVALID_ATTRIBUTE)))
414 ;; It is valid for instruction that require sew/lmul ratio.
415 (define_attr "ratio" ""
416 (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\
417 vialu,vshift,vicmp,vimul,vidiv,vsalu,\
418 vext,viwalu,viwmul,vicalu,vnshift,\
419 vimuladd,vimerge,vaalu,vsmul,vsshift,\
420 vnclip,viminmax,viwmuladd,vmffs,vmsfs,\
421 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\
422 vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\
423 vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
424 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
425 vfncvtftof,vfmuladd,vfwmuladd,vfclass,vired,\
426 viwred,vfredu,vfredo,vfwredu,vfwredo,vimovvx,\
427 vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\
428 vislide1up,vislide1down,vfslide1up,vfslide1down,\
429 vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox")
430 (const_int INVALID_ATTRIBUTE)
431 (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
432 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (const_int 2)
433 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (const_int 4)
434 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (const_int 8)
435 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (const_int 16)
436 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (const_int 32)
437 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (const_int 64)
438 (eq_attr "mode" "RVVM8HI") (const_int 2)
439 (eq_attr "mode" "RVVM4HI") (const_int 4)
440 (eq_attr "mode" "RVVM2HI") (const_int 8)
441 (eq_attr "mode" "RVVM1HI") (const_int 16)
442 (eq_attr "mode" "RVVMF2HI") (const_int 32)
443 (eq_attr "mode" "RVVMF4HI") (const_int 64)
444 (eq_attr "mode" "RVVM8HF") (const_int 2)
445 (eq_attr "mode" "RVVM4HF") (const_int 4)
446 (eq_attr "mode" "RVVM2HF") (const_int 8)
447 (eq_attr "mode" "RVVM1HF") (const_int 16)
448 (eq_attr "mode" "RVVMF2HF") (const_int 32)
449 (eq_attr "mode" "RVVMF4HF") (const_int 64)
450 (eq_attr "mode" "RVVM8SI") (const_int 4)
451 (eq_attr "mode" "RVVM4SI") (const_int 8)
452 (eq_attr "mode" "RVVM2SI") (const_int 16)
453 (eq_attr "mode" "RVVM1SI") (const_int 32)
454 (eq_attr "mode" "RVVMF2SI") (const_int 64)
455 (eq_attr "mode" "RVVM8SF") (const_int 4)
456 (eq_attr "mode" "RVVM4SF") (const_int 8)
457 (eq_attr "mode" "RVVM2SF") (const_int 16)
458 (eq_attr "mode" "RVVM1SF") (const_int 32)
459 (eq_attr "mode" "RVVMF2SF") (const_int 64)
460 (eq_attr "mode" "RVVM8DI") (const_int 8)
461 (eq_attr "mode" "RVVM4DI") (const_int 16)
462 (eq_attr "mode" "RVVM2DI") (const_int 32)
463 (eq_attr "mode" "RVVM1DI") (const_int 64)
464 (eq_attr "mode" "RVVM8DF") (const_int 8)
465 (eq_attr "mode" "RVVM4DF") (const_int 16)
466 (eq_attr "mode" "RVVM2DF") (const_int 32)
467 (eq_attr "mode" "RVVM1DF") (const_int 64)
468 (eq_attr "mode" "RVVM1x8QI") (const_int 8)
469 (eq_attr "mode" "RVVMF2x8QI") (const_int 16)
470 (eq_attr "mode" "RVVMF4x8QI") (const_int 32)
471 (eq_attr "mode" "RVVMF8x8QI") (const_int 64)
472 (eq_attr "mode" "RVVM1x7QI") (const_int 8)
473 (eq_attr "mode" "RVVMF2x7QI") (const_int 16)
474 (eq_attr "mode" "RVVMF4x7QI") (const_int 32)
475 (eq_attr "mode" "RVVMF8x7QI") (const_int 64)
476 (eq_attr "mode" "RVVM1x6QI") (const_int 8)
477 (eq_attr "mode" "RVVMF2x6QI") (const_int 16)
478 (eq_attr "mode" "RVVMF4x6QI") (const_int 32)
479 (eq_attr "mode" "RVVMF8x6QI") (const_int 64)
480 (eq_attr "mode" "RVVM1x5QI") (const_int 8)
481 (eq_attr "mode" "RVVMF2x5QI") (const_int 16)
482 (eq_attr "mode" "RVVMF4x5QI") (const_int 32)
483 (eq_attr "mode" "RVVMF8x5QI") (const_int 64)
484 (eq_attr "mode" "RVVM2x4QI") (const_int 4)
485 (eq_attr "mode" "RVVM1x4QI") (const_int 8)
486 (eq_attr "mode" "RVVMF2x4QI") (const_int 16)
487 (eq_attr "mode" "RVVMF4x4QI") (const_int 32)
488 (eq_attr "mode" "RVVMF8x4QI") (const_int 64)
489 (eq_attr "mode" "RVVM2x3QI") (const_int 4)
490 (eq_attr "mode" "RVVM1x3QI") (const_int 8)
491 (eq_attr "mode" "RVVMF2x3QI") (const_int 16)
492 (eq_attr "mode" "RVVMF4x3QI") (const_int 32)
493 (eq_attr "mode" "RVVMF8x3QI") (const_int 64)
494 (eq_attr "mode" "RVVM4x2QI") (const_int 2)
495 (eq_attr "mode" "RVVM2x2QI") (const_int 4)
496 (eq_attr "mode" "RVVM1x2QI") (const_int 8)
497 (eq_attr "mode" "RVVMF2x2QI") (const_int 16)
498 (eq_attr "mode" "RVVMF4x2QI") (const_int 32)
499 (eq_attr "mode" "RVVMF8x2QI") (const_int 64)
500 (eq_attr "mode" "RVVM1x8HI") (const_int 16)
501 (eq_attr "mode" "RVVMF2x8HI") (const_int 32)
502 (eq_attr "mode" "RVVMF4x8HI") (const_int 64)
503 (eq_attr "mode" "RVVM1x7HI") (const_int 16)
504 (eq_attr "mode" "RVVMF2x7HI") (const_int 32)
505 (eq_attr "mode" "RVVMF4x7HI") (const_int 64)
506 (eq_attr "mode" "RVVM1x6HI") (const_int 16)
507 (eq_attr "mode" "RVVMF2x6HI") (const_int 32)
508 (eq_attr "mode" "RVVMF4x6HI") (const_int 64)
509 (eq_attr "mode" "RVVM1x5HI") (const_int 16)
510 (eq_attr "mode" "RVVMF2x5HI") (const_int 32)
511 (eq_attr "mode" "RVVMF4x5HI") (const_int 64)
512 (eq_attr "mode" "RVVM2x4HI") (const_int 8)
513 (eq_attr "mode" "RVVM1x4HI") (const_int 16)
514 (eq_attr "mode" "RVVMF2x4HI") (const_int 32)
515 (eq_attr "mode" "RVVMF4x4HI") (const_int 64)
516 (eq_attr "mode" "RVVM2x3HI") (const_int 8)
517 (eq_attr "mode" "RVVM1x3HI") (const_int 16)
518 (eq_attr "mode" "RVVMF2x3HI") (const_int 32)
519 (eq_attr "mode" "RVVMF4x3HI") (const_int 64)
520 (eq_attr "mode" "RVVM4x2HI") (const_int 4)
521 (eq_attr "mode" "RVVM2x2HI") (const_int 8)
522 (eq_attr "mode" "RVVM1x2HI") (const_int 16)
523 (eq_attr "mode" "RVVMF2x2HI") (const_int 32)
524 (eq_attr "mode" "RVVMF4x2HI") (const_int 64)
525 (eq_attr "mode" "RVVM1x8HF") (const_int 16)
526 (eq_attr "mode" "RVVMF2x8HF") (const_int 32)
527 (eq_attr "mode" "RVVMF4x8HF") (const_int 64)
528 (eq_attr "mode" "RVVM1x7HF") (const_int 16)
529 (eq_attr "mode" "RVVMF2x7HF") (const_int 32)
530 (eq_attr "mode" "RVVMF4x7HF") (const_int 64)
531 (eq_attr "mode" "RVVM1x6HF") (const_int 16)
532 (eq_attr "mode" "RVVMF2x6HF") (const_int 32)
533 (eq_attr "mode" "RVVMF4x6HF") (const_int 64)
534 (eq_attr "mode" "RVVM1x5HF") (const_int 16)
535 (eq_attr "mode" "RVVMF2x5HF") (const_int 32)
536 (eq_attr "mode" "RVVMF4x5HF") (const_int 64)
537 (eq_attr "mode" "RVVM2x4HF") (const_int 8)
538 (eq_attr "mode" "RVVM1x4HF") (const_int 16)
539 (eq_attr "mode" "RVVMF2x4HF") (const_int 32)
540 (eq_attr "mode" "RVVMF4x4HF") (const_int 64)
541 (eq_attr "mode" "RVVM2x3HF") (const_int 8)
542 (eq_attr "mode" "RVVM1x3HF") (const_int 16)
543 (eq_attr "mode" "RVVMF2x3HF") (const_int 32)
544 (eq_attr "mode" "RVVMF4x3HF") (const_int 64)
545 (eq_attr "mode" "RVVM4x2HF") (const_int 4)
546 (eq_attr "mode" "RVVM2x2HF") (const_int 8)
547 (eq_attr "mode" "RVVM1x2HF") (const_int 16)
548 (eq_attr "mode" "RVVMF2x2HF") (const_int 32)
549 (eq_attr "mode" "RVVMF4x2HF") (const_int 64)
550 (eq_attr "mode" "RVVM1x8SI") (const_int 32)
551 (eq_attr "mode" "RVVMF2x8SI") (const_int 64)
552 (eq_attr "mode" "RVVM1x7SI") (const_int 32)
553 (eq_attr "mode" "RVVMF2x7SI") (const_int 64)
554 (eq_attr "mode" "RVVM1x6SI") (const_int 32)
555 (eq_attr "mode" "RVVMF2x6SI") (const_int 64)
556 (eq_attr "mode" "RVVM1x5SI") (const_int 32)
557 (eq_attr "mode" "RVVMF2x5SI") (const_int 64)
558 (eq_attr "mode" "RVVM2x4SI") (const_int 16)
559 (eq_attr "mode" "RVVM1x4SI") (const_int 32)
560 (eq_attr "mode" "RVVMF2x4SI") (const_int 64)
561 (eq_attr "mode" "RVVM2x3SI") (const_int 16)
562 (eq_attr "mode" "RVVM1x3SI") (const_int 32)
563 (eq_attr "mode" "RVVMF2x3SI") (const_int 64)
564 (eq_attr "mode" "RVVM4x2SI") (const_int 8)
565 (eq_attr "mode" "RVVM2x2SI") (const_int 16)
566 (eq_attr "mode" "RVVM1x2SI") (const_int 32)
567 (eq_attr "mode" "RVVMF2x2SI") (const_int 64)
568 (eq_attr "mode" "RVVM1x8SF") (const_int 32)
569 (eq_attr "mode" "RVVMF2x8SF") (const_int 64)
570 (eq_attr "mode" "RVVM1x7SF") (const_int 32)
571 (eq_attr "mode" "RVVMF2x7SF") (const_int 64)
572 (eq_attr "mode" "RVVM1x6SF") (const_int 32)
573 (eq_attr "mode" "RVVMF2x6SF") (const_int 64)
574 (eq_attr "mode" "RVVM1x5SF") (const_int 32)
575 (eq_attr "mode" "RVVMF2x5SF") (const_int 64)
576 (eq_attr "mode" "RVVM2x4SF") (const_int 16)
577 (eq_attr "mode" "RVVM1x4SF") (const_int 32)
578 (eq_attr "mode" "RVVMF2x4SF") (const_int 64)
579 (eq_attr "mode" "RVVM2x3SF") (const_int 16)
580 (eq_attr "mode" "RVVM1x3SF") (const_int 32)
581 (eq_attr "mode" "RVVMF2x3SF") (const_int 64)
582 (eq_attr "mode" "RVVM4x2SF") (const_int 8)
583 (eq_attr "mode" "RVVM2x2SF") (const_int 16)
584 (eq_attr "mode" "RVVM1x2SF") (const_int 32)
585 (eq_attr "mode" "RVVMF2x2SF") (const_int 64)
586 (eq_attr "mode" "RVVM1x8DI") (const_int 64)
587 (eq_attr "mode" "RVVM1x7DI") (const_int 64)
588 (eq_attr "mode" "RVVM1x6DI") (const_int 64)
589 (eq_attr "mode" "RVVM1x5DI") (const_int 64)
590 (eq_attr "mode" "RVVM2x4DI") (const_int 32)
591 (eq_attr "mode" "RVVM1x4DI") (const_int 64)
592 (eq_attr "mode" "RVVM2x3DI") (const_int 32)
593 (eq_attr "mode" "RVVM1x3DI") (const_int 64)
594 (eq_attr "mode" "RVVM4x2DI") (const_int 16)
595 (eq_attr "mode" "RVVM2x2DI") (const_int 32)
596 (eq_attr "mode" "RVVM1x2DI") (const_int 64)
597 (eq_attr "mode" "RVVM1x8DF") (const_int 64)
598 (eq_attr "mode" "RVVM1x7DF") (const_int 64)
599 (eq_attr "mode" "RVVM1x6DF") (const_int 64)
600 (eq_attr "mode" "RVVM1x5DF") (const_int 64)
601 (eq_attr "mode" "RVVM2x4DF") (const_int 32)
602 (eq_attr "mode" "RVVM1x4DF") (const_int 64)
603 (eq_attr "mode" "RVVM2x3DF") (const_int 32)
604 (eq_attr "mode" "RVVM1x3DF") (const_int 64)
605 (eq_attr "mode" "RVVM4x2DF") (const_int 16)
606 (eq_attr "mode" "RVVM2x2DF") (const_int 32)
607 (eq_attr "mode" "RVVM1x2DF") (const_int 64)
609 ;; VLS modes.
610 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_ratio(E_V1QImode)")
611 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_ratio(E_V2QImode)")
612 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_ratio(E_V4QImode)")
613 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_ratio(E_V8QImode)")
614 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_ratio(E_V16QImode)")
615 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_ratio(E_V32QImode)")
616 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_ratio(E_V64QImode)")
617 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_ratio(E_V128QImode)")
618 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_ratio(E_V256QImode)")
619 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_ratio(E_V512QImode)")
620 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_ratio(E_V1024QImode)")
621 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_ratio(E_V2048QImode)")
622 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_ratio(E_V4096QImode)")
623 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_ratio(E_V1HImode)")
624 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_ratio(E_V2HImode)")
625 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_ratio(E_V4HImode)")
626 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_ratio(E_V8HImode)")
627 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_ratio(E_V16HImode)")
628 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_ratio(E_V32HImode)")
629 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_ratio(E_V64HImode)")
630 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_ratio(E_V128HImode)")
631 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_ratio(E_V256HImode)")
632 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_ratio(E_V512HImode)")
633 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_ratio(E_V1024HImode)")
634 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_ratio(E_V2048HImode)")
635 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_ratio(E_V1SImode)")
636 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_ratio(E_V2SImode)")
637 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_ratio(E_V4SImode)")
638 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_ratio(E_V8SImode)")
639 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_ratio(E_V16SImode)")
640 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_ratio(E_V32SImode)")
641 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_ratio(E_V64SImode)")
642 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_ratio(E_V128SImode)")
643 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_ratio(E_V256SImode)")
644 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_ratio(E_V512SImode)")
645 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_ratio(E_V1024SImode)")
646 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_ratio(E_V1DImode)")
647 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_ratio(E_V2DImode)")
648 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_ratio(E_V4DImode)")
649 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_ratio(E_V8DImode)")
650 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_ratio(E_V16DImode)")
651 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_ratio(E_V32DImode)")
652 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_ratio(E_V64DImode)")
653 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_ratio(E_V128DImode)")
654 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_ratio(E_V256DImode)")
655 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_ratio(E_V512DImode)")
656 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_ratio(E_V1HFmode)")
657 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_ratio(E_V2HFmode)")
658 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_ratio(E_V4HFmode)")
659 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_ratio(E_V8HFmode)")
660 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_ratio(E_V16HFmode)")
661 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_ratio(E_V32HFmode)")
662 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_ratio(E_V64HFmode)")
663 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_ratio(E_V128HFmode)")
664 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_ratio(E_V256HFmode)")
665 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_ratio(E_V512HFmode)")
666 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_ratio(E_V1024HFmode)")
667 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_ratio(E_V2048HFmode)")
668 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_ratio(E_V1SFmode)")
669 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_ratio(E_V2SFmode)")
670 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_ratio(E_V4SFmode)")
671 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_ratio(E_V8SFmode)")
672 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_ratio(E_V16SFmode)")
673 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_ratio(E_V32SFmode)")
674 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_ratio(E_V64SFmode)")
675 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_ratio(E_V128SFmode)")
676 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_ratio(E_V256SFmode)")
677 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_ratio(E_V512SFmode)")
678 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_ratio(E_V1024SFmode)")
679 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_ratio(E_V1DFmode)")
680 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_ratio(E_V2DFmode)")
681 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_ratio(E_V4DFmode)")
682 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_ratio(E_V8DFmode)")
683 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_ratio(E_V16DFmode)")
684 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_ratio(E_V32DFmode)")
685 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_ratio(E_V64DFmode)")
686 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_ratio(E_V128DFmode)")
687 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_ratio(E_V256DFmode)")
688 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_ratio(E_V512DFmode)")]
689 (const_int INVALID_ATTRIBUTE)))
691 ;; The index of operand[] to get the merge op.
692 (define_attr "merge_op_idx" ""
693 (cond [(eq_attr "type" "vlde,vimov,vfmov,vldm,vlds,vmalu,vldux,vldox,vicmp,\
694 vialu,vshift,viminmax,vimul,vidiv,vsalu,vext,viwalu,\
695 viwmul,vnshift,vaalu,vsmul,vsshift,vnclip,vmsfs,\
696 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
697 vfsqrt,vfrecp,vfsgnj,vfcmp,vfcvtitof,vfcvtftoi,vfwcvtitof,\
698 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,\
699 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\
700 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
701 vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff")
702 (const_int 2)
704 (eq_attr "type" "vimerge,vfmerge,vcompress")
705 (const_int 1)
707 (eq_attr "type" "vimuladd,vfmuladd")
708 (const_int 5)]
709 (const_int INVALID_ATTRIBUTE)))
711 ;; The index of operand[] represents the machine mode of the instruction.
712 (define_attr "mode_idx" ""
713 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vldff,vldr,vstr,\
714 vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vialu,vext,vicalu,\
715 vshift,vicmp,viminmax,vimul,vidiv,vimuladd,vimerge,vimov,\
716 vsalu,vaalu,vsmul,vsshift,vfalu,vfmul,vfdiv,vfmuladd,vfsqrt,vfrecp,\
717 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
718 vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\
719 vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
720 vgather,vcompress,vmov,vnclip,vnshift")
721 (const_int 0)
723 (eq_attr "type" "vimovvx,vfmovvf")
724 (const_int 1)
726 (eq_attr "type" "vssegte,vmpop,vmffs")
727 (const_int 2)
729 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi,
730 vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo")
731 (const_int 3)
733 (eq_attr "type" "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd")
734 (const_int 4)]
735 (const_int INVALID_ATTRIBUTE)))
737 ;; The index of operand[] to get the avl op.
738 (define_attr "vl_op_idx" ""
739 (cond [(eq_attr "type" "vlde,vste,vimov,vfmov,vldm,vstm,vmalu,vsts,vstux,\
740 vstox,vext,vmsfs,vmiota,vfsqrt,vfrecp,vfcvtitof,vldff,\
741 vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
742 vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\
743 vlsegde,vssegts,vssegtux,vssegtox,vlsegdff")
744 (const_int 4)
746 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
747 ;; wheras it is pred_strided_load if operands[3] is vector mode.
748 (eq_attr "type" "vlds")
749 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
750 (const_int 5)
751 (const_int 4))
753 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
754 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
755 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
756 vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
757 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
758 vgather,viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox")
759 (const_int 5)
761 (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd")
762 (const_int 6)
764 (eq_attr "type" "vmpop,vmffs,vmidx,vssegte")
765 (const_int 3)]
766 (const_int INVALID_ATTRIBUTE)))
768 ;; The tail policy op value.
769 (define_attr "ta" ""
770 (cond [(eq_attr "type" "vlde,vimov,vfmov,vext,vmiota,vfsqrt,vfrecp,\
771 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\
772 vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\
773 vcompress,vldff,vlsegde,vlsegdff")
774 (symbol_ref "riscv_vector::get_ta(operands[5])")
776 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
777 ;; wheras it is pred_strided_load if operands[3] is vector mode.
778 (eq_attr "type" "vlds")
779 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
780 (symbol_ref "riscv_vector::get_ta(operands[6])")
781 (symbol_ref "riscv_vector::get_ta(operands[5])"))
783 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
784 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
785 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,\
786 vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\
787 vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
788 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
789 vlsegds,vlsegdux,vlsegdox")
790 (symbol_ref "riscv_vector::get_ta(operands[6])")
792 (eq_attr "type" "vimuladd,vfmuladd")
793 (symbol_ref "riscv_vector::get_ta(operands[7])")
795 (eq_attr "type" "vmidx")
796 (symbol_ref "riscv_vector::get_ta(operands[4])")]
797 (const_int INVALID_ATTRIBUTE)))
799 ;; The mask policy op value.
800 (define_attr "ma" ""
801 (cond [(eq_attr "type" "vlde,vext,vmiota,vfsqrt,vfrecp,vfcvtitof,vfcvtftoi,\
802 vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
803 vfncvtftof,vfclass,vldff,vlsegde,vlsegdff")
804 (symbol_ref "riscv_vector::get_ma(operands[6])")
806 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
807 ;; wheras it is pred_strided_load if operands[3] is vector mode.
808 (eq_attr "type" "vlds")
809 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
810 (symbol_ref "riscv_vector::get_ma(operands[7])")
811 (symbol_ref "riscv_vector::get_ma(operands[6])"))
813 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
814 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
815 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,\
816 vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
817 vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\
818 viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox")
819 (symbol_ref "riscv_vector::get_ma(operands[7])")
821 (eq_attr "type" "vimuladd,vfmuladd")
822 (symbol_ref "riscv_vector::get_ma(operands[8])")
824 (eq_attr "type" "vmsfs,vmidx")
825 (symbol_ref "riscv_vector::get_ma(operands[5])")]
826 (const_int INVALID_ATTRIBUTE)))
828 ;; The avl type value.
829 (define_attr "avl_type_idx" ""
830 (cond [(eq_attr "type" "vlde,vldff,vste,vimov,vfmov,vext,vimerge,\
831 vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
832 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
833 vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
834 vimovxv,vfmovfv,vlsegde,vlsegdff")
835 (const_int 7)
836 (eq_attr "type" "vldm,vstm,vmalu,vmalu")
837 (const_int 5)
839 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
840 ;; wheras it is pred_strided_load if operands[3] is vector mode.
841 (eq_attr "type" "vlds")
842 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
843 (const_int 8)
844 (const_int 7))
846 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
847 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
848 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
849 vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\
850 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
851 vlsegds,vlsegdux,vlsegdox")
852 (const_int 8)
853 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox")
854 (const_int 5)
856 (eq_attr "type" "vimuladd,vfmuladd")
857 (const_int 9)
859 (eq_attr "type" "vmsfs,vmidx,vcompress")
860 (const_int 6)
862 (eq_attr "type" "vmpop,vmffs,vssegte")
863 (const_int 4)]
864 (const_int INVALID_ATTRIBUTE)))
866 ;; Defines rounding mode of an fixed-point operation.
868 (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
869 (cond [(eq_attr "type" "vaalu,vsmul,vsshift,vnclip")
870 (cond
871 [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
872 (const_string "rnu")
874 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
875 (const_string "rne")
877 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
878 (const_string "rdn")
880 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
881 (const_string "rod")]
882 (const_string "none"))]
883 (const_string "none")))
885 ;; Defines rounding mode of an floating-point operation.
886 (define_attr "frm_mode" ""
887 (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
888 (symbol_ref "riscv_vector::FRM_DYN")]
889 (symbol_ref "riscv_vector::FRM_NONE")))
891 ;; -----------------------------------------------------------------
892 ;; ---- Miscellaneous Operations
893 ;; -----------------------------------------------------------------
895 (define_insn "@vundefined<mode>"
896 [(set (match_operand:V 0 "register_operand" "=vr")
897 (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
898 "TARGET_VECTOR"
899 ""
900 [(set_attr "type" "vector")])
902 (define_insn "@vundefined<mode>"
903 [(set (match_operand:VB 0 "register_operand" "=vr")
904 (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
905 "TARGET_VECTOR"
906 ""
907 [(set_attr "type" "vector")])
909 (define_insn "@vundefined<mode>"
910 [(set (match_operand:VT 0 "register_operand" "=vr")
911 (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
912 "TARGET_VECTOR"
913 ""
914 [(set_attr "type" "vector")])
916 (define_expand "@vreinterpret<mode>"
917 [(set (match_operand:V 0 "register_operand")
918 (match_operand 1 "vector_any_register_operand"))]
919 "TARGET_VECTOR"
920 {
921 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
922 DONE;
923 }
924 )
926 (define_expand "@vreinterpret<mode>"
927 [(set (match_operand:VB 0 "register_operand")
928 (match_operand 1 "vector_any_register_operand"))]
929 "TARGET_VECTOR"
930 {
931 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
932 DONE;
933 }
934 )
936 ;; This pattern is used to hold the AVL operand for
937 ;; RVV instructions that implicity use VLMAX AVL.
938 ;; RVV instruction implicitly use GPR that is ultimately
939 ;; defined by this pattern is safe for VSETVL pass emit
940 ;; a vsetvl instruction modify this register after RA.
941 ;; Case 1:
942 ;; vlmax_avl a5
943 ;; ... (across many blocks)
944 ;; vadd (implicit use a5) ====> emit: vsetvl a5,zero
945 ;; Case 2:
946 ;; vlmax_avl a5
947 ;; ... (across many blocks)
948 ;; mv a6,a5
949 ;; ... (across many blocks)
950 ;; vadd (implicit use a6) ====> emit: vsetvl a6,zero
951 ;; Case 3:
952 ;; vlmax_avl a5
953 ;; ... (across many blocks)
954 ;; store mem,a5 (spill)
955 ;; ... (across many blocks)
956 ;; load a7,mem (spill)
957 ;; ... (across many blocks)
958 ;; vadd (implicit use a7) ====> emit: vsetvl a7,zero
959 ;; Such cases are all safe for VSETVL PASS to emit a vsetvl
960 ;; instruction that modifies the AVL operand.
961 (define_insn "@vlmax_avl<mode>"
962 [(set (match_operand:P 0 "register_operand" "=r")
963 (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
964 "TARGET_VECTOR"
965 ""
966 [(set_attr "type" "vsetvl_pre")]
967 )
969 ;; Set VXRM
970 (define_insn "vxrmsi"
971 [(set (reg:SI VXRM_REGNUM)
972 (match_operand:SI 0 "const_int_operand" "i"))]
973 "TARGET_VECTOR"
974 "csrwi\tvxrm,%0"
975 [(set_attr "type" "wrvxrm")
976 (set_attr "mode" "SI")])
978 ;; Set FRM
979 (define_insn "fsrmsi_backup"
980 [(set (match_operand:SI 0 "register_operand" "=r,r")
981 (reg:SI FRM_REGNUM))
982 (set (reg:SI FRM_REGNUM)
983 (match_operand:SI 1 "reg_or_int_operand" "r,i"))]
984 "TARGET_VECTOR"
985 "@
986 fsrm\t%0,%1
987 fsrmi\t%0,%1"
988 [(set_attr "type" "wrfrm,wrfrm")
989 (set_attr "mode" "SI")]
990 )
992 (define_insn "fsrmsi_restore"
993 [(set (reg:SI FRM_REGNUM)
994 (match_operand:SI 0 "reg_or_int_operand" "r,i"))]
995 "TARGET_VECTOR"
996 "@
997 fsrm\t%0
998 fsrmi\t%0"
999 [(set_attr "type" "wrfrm,wrfrm")
1000 (set_attr "mode" "SI")]
1001 )
1003 ;; The volatile fsrmsi restore is used for the exit point for the
1004 ;; dynamic mode switching. It will generate one volatile fsrm a5
1005 ;; which won't be eliminated.
1006 (define_insn "fsrmsi_restore_volatile"
1007 [(set (reg:SI FRM_REGNUM)
1008 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1009 UNSPECV_FRM_RESTORE_EXIT))]
1010 "TARGET_VECTOR"
1011 "fsrm\t%0"
1012 [(set_attr "type" "wrfrm")
1013 (set_attr "mode" "SI")]
1014 )
1016 ;; Read FRM
1017 (define_insn "frrmsi"
1018 [(set (match_operand:SI 0 "register_operand" "=r")
1019 (reg:SI FRM_REGNUM))]
1020 "TARGET_VECTOR"
1021 "frrm\t%0"
1022 [(set_attr "type" "rdfrm")
1023 (set_attr "mode" "SI")]
1024 )
1026 ;; -----------------------------------------------------------------
1027 ;; ---- Moves Operations
1028 ;; -----------------------------------------------------------------
1030 (define_expand "mov<mode>"
1031 [(set (match_operand:V 0 "reg_or_mem_operand")
1032 (match_operand:V 1 "general_operand"))]
1033 "TARGET_VECTOR"
1034 {
1035 /* For whole register move, we transform the pattern into the format
1036 that excludes the clobber of scratch register.
1038 We include clobber of a scalar scratch register which is going to be
1039 used for emit of vsetvl instruction after reload_completed since we
1040 need vsetvl instruction to set VL/VTYPE global status for fractional
1041 vector load/store.
1043 For example:
1044 [(set (match_operand:RVVMF8QI v24)
1045 (match_operand:RVVMF8QI (mem: a4)))
1046 (clobber (scratch:SI a5))]
1047 ====>> vsetvl a5,zero,e8,mf8
1048 ====>> vle8.v v24,(a4)
1050 Philosophy:
1052 - Clobber a scalar scratch register for each mov<mode>.
1054 - Classify the machine_mode mode = <MODE>mode into 2 class:
1055 Whole register move and fractional register move.
1057 - Transform and remove scratch clobber register for whole
1058 register move so that we can avoid occupying the scalar
1059 registers.
1061 - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
1062 before spilling. The clobber scratch is used by spilling fractional
1063 registers in IRA/LRA so it's too early. */
1065 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1066 DONE;
1067 })
1069 ;; This pattern is used for code-gen for whole register load/stores.
1070 ;; Also applicable for all register moves.
1071 ;; Fractional vector modes load/store are not allowed to match this pattern.
1072 ;; Mask modes load/store are not allowed to match this pattern.
1073 ;; We seperate "*mov<mode>" into "*mov<mode>_whole" and "*mov<mode>_fract" because
1074 ;; we don't want to include fractional load/store in "*mov<mode>" which will
1075 ;; create unexpected patterns in LRA.
1076 ;; For example:
1077 ;; ira rtl:
1078 ;; (insn 20 19 9 2 (set (reg/v:RVVMF4QI 97 v1 [ v1 ])
1079 ;; (reg:RVVMF4QI 134 [ _1 ])) "rvv.c":9:22 571 {*movvnx2qi_fract}
1080 ;; (nil))
1081 ;; When the value of pseudo register 134 of the insn above is discovered already
1082 ;; spilled in the memory during LRA.
1083 ;; LRA will reload this pattern into a memory load instruction pattern.
1084 ;; Because RVVMF4QI is a fractional vector, we want LRA reload this pattern into
1085 ;; (insn 20 19 9 2 (parallel [
1086 ;; (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1087 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8]))
1088 ;; (clobber (reg:SI 14 a4 [149]))])
1089 ;; So that we could be able to emit vsetvl instruction using clobber sratch a4.
1090 ;; To let LRA generate the expected pattern, we should exclude fractional vector
1091 ;; load/store in "*mov<mode>_whole". Otherwise, it will reload this pattern into:
1092 ;; (insn 20 19 9 2 (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1093 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8])))
1094 ;; which is not the pattern we want.
1095 ;; According the facts above, we make "*mov<mode>_whole" includes load/store/move for whole
1096 ;; vector modes according to '-march' and "*mov<mode>_fract" only include fractional vector modes.
1097 (define_insn "*mov<mode>_whole"
1098 [(set (match_operand:V_WHOLE 0 "reg_or_mem_operand" "=vr, m,vr")
1099 (match_operand:V_WHOLE 1 "reg_or_mem_operand" " m,vr,vr"))]
1100 "TARGET_VECTOR"
1101 "@
1102 vl%m1re<sew>.v\t%0,%1
1103 vs%m1r.v\t%1,%0
1104 vmv%m1r.v\t%0,%1"
1105 [(set_attr "type" "vldr,vstr,vmov")
1106 (set_attr "mode" "<MODE>")])
1108 (define_insn "*mov<mode>_fract"
1109 [(set (match_operand:V_FRACT 0 "register_operand" "=vr")
1110 (match_operand:V_FRACT 1 "register_operand" " vr"))]
1111 "TARGET_VECTOR"
1112 "vmv1r.v\t%0,%1"
1113 [(set_attr "type" "vmov")
1114 (set_attr "mode" "<MODE>")])
1116 (define_expand "mov<mode>"
1117 [(set (match_operand:VB 0 "reg_or_mem_operand")
1118 (match_operand:VB 1 "general_operand"))]
1119 "TARGET_VECTOR"
1120 {
1121 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1122 DONE;
1123 })
1125 (define_insn "*mov<mode>"
1126 [(set (match_operand:VB 0 "register_operand" "=vr")
1127 (match_operand:VB 1 "register_operand" " vr"))]
1128 "TARGET_VECTOR"
1129 "vmv1r.v\t%0,%1"
1130 [(set_attr "type" "vmov")
1131 (set_attr "mode" "<MODE>")])
1133 (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
1134 [(parallel
1135 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
1136 (match_operand:V_FRACT 1 "reg_or_mem_operand"))
1137 (clobber (match_scratch:P 2))])]
1138 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1139 {})
1141 (define_expand "@mov<VB:mode><P:mode>_lra"
1142 [(parallel
1143 [(set (match_operand:VB 0 "reg_or_mem_operand")
1144 (match_operand:VB 1 "reg_or_mem_operand"))
1145 (clobber (match_scratch:P 2))])]
1146 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1147 {})
1149 (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
1150 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
1151 (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
1152 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1153 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1154 "#"
1155 "&& reload_completed"
1156 [(const_int 0)]
1157 {
1158 if (REG_P (operands[0]) && REG_P (operands[1]))
1159 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1160 else
1161 {
1162 riscv_vector::emit_vlmax_vsetvl (<V_FRACT:MODE>mode, operands[2]);
1163 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<V_FRACT:MODE>mode),
1164 riscv_vector::UNARY_OP, operands, operands[2]);
1165 }
1166 DONE;
1167 }
1168 [(set_attr "type" "vector")]
1169 )
1171 (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
1172 [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
1173 (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
1174 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1175 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1176 "#"
1177 "&& reload_completed"
1178 [(const_int 0)]
1179 {
1180 if (REG_P (operands[0]) && REG_P (operands[1]))
1181 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1182 else
1183 {
1184 riscv_vector::emit_vlmax_vsetvl (<VB:MODE>mode, operands[2]);
1185 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<VB:MODE>mode),
1186 riscv_vector::UNARY_MASK_OP, operands, operands[2]);
1187 }
1188 DONE;
1189 }
1190 [(set_attr "type" "vector")]
1191 )
1193 ;; Define tuple modes data movement.
1194 ;; operands[2] is used to save the offset of each subpart.
1195 ;; operands[3] is used to calculate the address for each subpart.
1196 ;; operands[4] is VL of vsevli instruction.
1197 (define_expand "mov<mode>"
1198 [(parallel [(set (match_operand:VT 0 "reg_or_mem_operand")
1199 (match_operand:VT 1 "general_operand"))
1200 (clobber (match_dup 2))
1201 (clobber (match_dup 3))
1202 (clobber (match_dup 4))])]
1203 "TARGET_VECTOR"
1204 {
1205 /* Need to force register if mem <- !reg. */
1206 if (MEM_P (operands[0]) && !REG_P (operands[1]))
1207 operands[1] = force_reg (<MODE>mode, operands[1]);
1209 if (GET_CODE (operands[1]) == CONST_VECTOR)
1210 {
1211 riscv_vector::expand_tuple_move (operands);
1212 DONE;
1213 }
1215 operands[2] = gen_rtx_SCRATCH (Pmode);
1216 operands[3] = gen_rtx_SCRATCH (Pmode);
1217 operands[4] = gen_rtx_SCRATCH (Pmode);
1218 })
1220 (define_insn_and_split "*mov<VT:mode>_<P:mode>"
1221 [(set (match_operand:VT 0 "reg_or_mem_operand" "=vr,vr, m")
1222 (match_operand:VT 1 "reg_or_mem_operand" " vr, m,vr"))
1223 (clobber (match_scratch:P 2 "=X,&r,&r"))
1224 (clobber (match_scratch:P 3 "=X,&r,&r"))
1225 (clobber (match_scratch:P 4 "=X,&r,&r"))]
1226 "TARGET_VECTOR"
1227 "#"
1228 "&& reload_completed"
1229 [(const_int 0)]
1230 {
1231 riscv_vector::expand_tuple_move (operands);
1232 DONE;
1233 }
1234 [(set_attr "type" "vmov,vlde,vste")
1235 (set_attr "mode" "<VT:MODE>")
1236 (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
1237 (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))])
1239 ;; -----------------------------------------------------------------
1240 ;; ---- VLS Moves Operations
1241 ;; -----------------------------------------------------------------
1243 (define_expand "mov<mode>"
1244 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
1245 (match_operand:VLS_AVL_IMM 1 "general_operand"))]
1246 "TARGET_VECTOR"
1247 {
1248 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1249 DONE;
1250 })
1252 (define_insn_and_split "*mov<mode>"
1253 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
1254 (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
1255 "TARGET_VECTOR
1256 && (register_operand (operands[0], <MODE>mode)
1257 || register_operand (operands[1], <MODE>mode))"
1258 "@
1259 #
1260 #
1261 vmv%m1r.v\t%0,%1"
1262 "&& reload_completed
1263 && (!register_operand (operands[0], <MODE>mode)
1264 || !register_operand (operands[1], <MODE>mode))"
1265 [(const_int 0)]
1266 {
1267 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1268 gcc_assert (ok_p);
1269 DONE;
1270 }
1271 [(set_attr "type" "vmov")]
1272 )
1274 (define_expand "mov<mode>"
1275 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1276 (match_operand:VLS_AVL_REG 1 "general_operand"))]
1277 "TARGET_VECTOR"
1278 {
1279 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1280 gcc_assert (ok_p);
1281 DONE;
1282 })
1284 (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
1285 [(parallel
1286 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1287 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
1288 (clobber (match_scratch:P 2))])]
1289 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1290 {})
1292 (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
1293 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
1294 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
1295 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1296 "TARGET_VECTOR && (lra_in_progress || reload_completed)
1297 && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
1298 || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
1299 "#"
1300 "&& reload_completed"
1301 [(const_int 0)]
1302 {
1303 if (REG_P (operands[0]) && REG_P (operands[1]))
1304 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1305 else
1306 {
1307 emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
1308 Pmode));
1309 unsigned insn_flags
1310 = GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
1311 ? riscv_vector::UNARY_MASK_OP
1312 : riscv_vector::UNARY_OP;
1313 riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
1314 insn_flags, operands, operands[2]);
1315 }
1316 DONE;
1317 }
1318 [(set_attr "type" "vmov")]
1319 )
1321 (define_insn "*mov<mode>_vls"
1322 [(set (match_operand:VLS 0 "register_operand" "=vr")
1323 (match_operand:VLS 1 "register_operand" " vr"))]
1324 "TARGET_VECTOR"
1325 "vmv%m1r.v\t%0,%1"
1326 [(set_attr "type" "vmov")
1327 (set_attr "mode" "<MODE>")])
1329 (define_insn "*mov<mode>_vls"
1330 [(set (match_operand:VLSB 0 "register_operand" "=vr")
1331 (match_operand:VLSB 1 "register_operand" " vr"))]
1332 "TARGET_VECTOR"
1333 "vmv1r.v\t%0,%1"
1334 [(set_attr "type" "vmov")
1335 (set_attr "mode" "<MODE>")])
1337 (define_expand "movmisalign<mode>"
1338 [(set (match_operand:VLS 0 "nonimmediate_operand")
1339 (match_operand:VLS 1 "general_operand"))]
1340 "TARGET_VECTOR"
1341 {
1342 /* To support misalign data movement, we should use
1343 minimum element alignment load/store. */
1344 unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode));
1345 poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode) * size;
1346 machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require ();
1347 operands[0] = gen_lowpart (mode, operands[0]);
1348 operands[1] = gen_lowpart (mode, operands[1]);
1349 if (MEM_P (operands[0]) && !register_operand (operands[1], mode))
1350 operands[1] = force_reg (mode, operands[1]);
1351 riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::UNARY_OP, operands);
1352 DONE;
1353 }
1354 )
1356 ;; According to RVV ISA:
1357 ;; If an element accessed by a vector memory instruction is not naturally aligned to the size of the element,
1358 ;; either the element is transferred successfully or an address misaligned exception is raised on that element.
1359 (define_expand "movmisalign<mode>"
1360 [(set (match_operand:V 0 "nonimmediate_operand")
1361 (match_operand:V 1 "general_operand"))]
1362 "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
1363 {
1364 emit_move_insn (operands[0], operands[1]);
1365 DONE;
1366 }
1367 )
1369 ;; -----------------------------------------------------------------
1370 ;; ---- Duplicate Operations
1371 ;; -----------------------------------------------------------------
1373 (define_expand "vec_duplicate<mode>"
1374 [(set (match_operand:V_VLS 0 "register_operand")
1375 (vec_duplicate:V_VLS
1376 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1377 "TARGET_VECTOR"
1378 {
1379 /* Early expand DImode broadcast in RV32 system to avoid RA reload
1380 generate (set (reg) (vec_duplicate:DI)). */
1381 if (maybe_gt (GET_MODE_SIZE (<VEL>mode), GET_MODE_SIZE (Pmode)))
1382 {
1383 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1384 riscv_vector::UNARY_OP, operands);
1385 DONE;
1386 }
1387 /* Otherwise, allow it fall into general vec_duplicate pattern
1388 which allow us to have vv->vx combine optimization in later pass. */
1389 })
1391 ;; According to GCC internal:
1392 ;; This pattern only handles duplicates of non-constant inputs.
1393 ;; Constant vectors go through the movm pattern instead.
1394 ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT.
1395 (define_insn_and_split "*vec_duplicate<mode>"
1396 [(set (match_operand:V_VLS 0 "register_operand")
1397 (vec_duplicate:V_VLS
1398 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1399 "TARGET_VECTOR && can_create_pseudo_p ()"
1400 "#"
1401 "&& 1"
1402 [(const_int 0)]
1403 {
1404 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1405 riscv_vector::UNARY_OP, operands);
1406 DONE;
1407 }
1408 [(set_attr "type" "vector")]
1409 )
1411 ;; -----------------------------------------------------------------
1412 ;; ---- 6. Configuration-Setting Instructions
1413 ;; -----------------------------------------------------------------
1414 ;; Includes:
1415 ;; - 6.1 vsetvli/vsetivl/vsetvl instructions
1416 ;; -----------------------------------------------------------------
1418 ;; we dont't define vsetvli as unspec_volatile which has side effects.
1419 ;; This instruction can be scheduled by the instruction scheduler.
1420 ;; This means these instructions will be deleted when
1421 ;; there is no instructions using vl or vtype in the following.
1422 ;; rd | rs1 | AVL value | Effect on vl
1423 ;; - | !x0 | x[rs1] | Normal stripmining
1424 ;; !x0 | x0 | ~0 | Set vl to VLMAX
1425 ;; operands[0]: VL.
1426 ;; operands[1]: AVL.
1427 ;; operands[2]: SEW
1428 ;; operands[3]: LMUL
1429 ;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)
1430 ;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)
1432 ;; We define 2 types of "vsetvl*" instruction patterns:
1434 ;; - "@vsetvl<mode>" is a parallel format which has side effects.
1436 ;; - "@vsetvl<mode>_no_side_effects" has no side effects.
1438 ;; - "@vsetvl<mode>" is used by "vsetvl" intrinsics and "insert-vsetvl" PASS.
1440 ;; - "@vsetvl<mode>_no_side_effects" is used by GCC standard patterns.
1442 ;; - "@vsetvl<mode>" includes VL/VTYPE global registers status (define set)
1443 ;; and each RVV instruction includes VL/VTYPE global registers status (use)
1444 ;; so that we can guarantee each RVV instruction can execute with correct
1445 ;; VL/VTYPE global registers status after "insert-vsetvl" PASS.
1447 ;; - "@vsetvl<mode>_no_side_effects" has no side effects and excludes VL/VTYPE
1448 ;; global registers status (define set). It's only used by GCC standard pattern
1449 ;; expansion. For example: "mov<mode>" pattern for fractional vector modes which
1450 ;; need to set VL/VTYPE. Then we could manually call this pattern to gain benefits
1451 ;; from the optimization of each GCC internal PASS.
1453 ;; 1. void foo (float *in, float *out)
1454 ;; {
1455 ;; vfloat32mf2_t v = *(vfloat32mf2_t*)in;
1456 ;; *(vfloat32mf2_t*)out = v;
1457 ;; }
1458 ;; We could eliminate the second "vsetvl" by calling "@vsetvl<mode>_no_side_effects".
1459 ;;
1460 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1461 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; vsetvli a4,zero,e32,mf2,ta,ma
1462 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1463 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; --
1464 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1465 ;; ret ;; ret
1467 ;; 2. void foo (int8_t *in, int8_t *out, int M)
1468 ;; {
1469 ;; for (int i = 0; i < M; i++){
1470 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1471 ;; *(vint8mf2_t*)(out + i) = v;
1472 ;; }
1473 ;; }
1474 ;;
1475 ;; Hoist "vsetvl" instruction in LICM:
1476 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1477 ;; - ;; vsetvli a4,zero,e32,mf2,ta,ma
1478 ;; LOOP: ;; LOOP:
1479 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1480 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1481 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1482 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1484 ;; However, it may produce wrong codegen if we exclude VL/VTYPE in "vsevl<mode>".
1485 ;; 3. void foo (int8_t *in, int8_t *out, int32_t *in2, int32_t *out2, int M)
1486 ;; {
1487 ;; for (int i = 0; i < M; i++){
1488 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1489 ;; vint32mf2_t v2 = *(vint32mf2_t*)(in + i + i);
1490 ;; *(vint8mf2_t*)(out + i) = v;
1491 ;; *(vint32mf2_t*)(out + i + i) = v2;
1492 ;; }
1493 ;; }
1494 ;;
1495 ;; vsetvli a6,zero,e8,mf2,ta,ma
1496 ;; vsetvli a2,zero,e32,mf2,ta,ma
1497 ;; LOOP:
1498 ;; vle8.v v25,(a0)
1499 ;; vle32.v v24,(a5)
1500 ;; addi a0,a0,1
1501 ;; vse8.v v25,(a1)
1502 ;; vse32.v v24,(a3)
1503 ;;
1504 ;; Both vle8.v and vle32.v are using the wrong VL/VTYPE status.
1505 ;; We leave it to "insert-vsetvl" PASS to correct this situation.
1507 ;; The "insert-vsetvl" PASS mechanism:
1508 ;; 1. Before "insert-vsetvl" PASS, only RVV instructions are generated
1509 ;; by GCC standard pattern expansion has the corresponding "vsetvl".
1510 ;; We exploit each GCC internal optimization pass to optimize the "vsetvl".
1511 ;; 2. Correct the VL/VTYPE status for each GCC standard pattern RVV instructions.
1512 ;; Insert vsetvl for each RVV instructions that has no VL/VTYPE status if necessary.
1513 ;; For example: RVV intrinsics.
1514 ;; 3. Optimize "vsetvl" instructions.
1516 (define_insn "@vsetvl<mode>"
1517 [(set (match_operand:P 0 "register_operand" "=r")
1518 (unspec:P [(match_operand:P 1 "csr_operand" "rK")
1519 (match_operand 2 "const_int_operand" "i")
1520 (match_operand 3 "const_int_operand" "i")
1521 (match_operand 4 "const_int_operand" "i")
1522 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
1523 (set (reg:SI VL_REGNUM)
1524 (unspec:SI [(match_dup 1)
1525 (match_dup 2)
1526 (match_dup 3)] UNSPEC_VSETVL))
1527 (set (reg:SI VTYPE_REGNUM)
1528 (unspec:SI [(match_dup 2)
1529 (match_dup 3)
1530 (match_dup 4)
1531 (match_dup 5)] UNSPEC_VSETVL))]
1532 "TARGET_VECTOR"
1533 "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
1534 [(set_attr "type" "vsetvl")
1535 (set_attr "mode" "<MODE>")
1536 (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
1537 (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
1538 (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
1539 (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
1541 ;; vsetvl zero,zero,vtype instruction.
1542 ;; This pattern has no side effects and does not set X0 register.
1543 (define_insn "vsetvl_vtype_change_only"
1544 [(set (reg:SI VTYPE_REGNUM)
1545 (unspec:SI
1546 [(match_operand 0 "const_int_operand" "i")
1547 (match_operand 1 "const_int_operand" "i")
1548 (match_operand 2 "const_int_operand" "i")
1549 (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
1550 "TARGET_VECTOR"
1551 "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
1552 [(set_attr "type" "vsetvl")
1553 (set_attr "mode" "SI")
1554 (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
1555 (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
1556 (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
1557 (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
1559 ;; vsetvl zero,rs1,vtype instruction.
1560 ;; The reason we need this pattern since we should avoid setting X0 register
1561 ;; in vsetvl instruction pattern.
1562 (define_insn "@vsetvl_discard_result<mode>"
1563 [(set (reg:SI VL_REGNUM)
1564 (unspec:SI [(match_operand:P 0 "csr_operand" "rK")
1565 (match_operand 1 "const_int_operand" "i")
1566 (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
1567 (set (reg:SI VTYPE_REGNUM)
1568 (unspec:SI [(match_dup 1)
1569 (match_dup 2)
1570 (match_operand 3 "const_int_operand" "i")
1571 (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
1572 "TARGET_VECTOR"
1573 "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
1574 [(set_attr "type" "vsetvl")
1575 (set_attr "mode" "<MODE>")
1576 (set (attr "sew") (symbol_ref "INTVAL (operands[1])"))
1577 (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])"))
1578 (set (attr "ta") (symbol_ref "INTVAL (operands[3])"))
1579 (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))])
1581 ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.
1582 ;; Since we have many optmization passes from "expand" to "reload_completed",
1583 ;; such pattern can allow us gain benefits of these optimizations.
1584 (define_insn_and_split "@vsetvl<mode>_no_side_effects"
1585 [(set (match_operand:P 0 "register_operand" "=r")
1586 (unspec:P [(match_operand:P 1 "csr_operand" "rK")
1587 (match_operand 2 "const_int_operand" "i")
1588 (match_operand 3 "const_int_operand" "i")
1589 (match_operand 4 "const_int_operand" "i")
1590 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
1591 "TARGET_VECTOR"
1592 "#"
1593 "&& epilogue_completed"
1594 [(parallel
1595 [(set (match_dup 0)
1596 (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
1597 (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
1598 (set (reg:SI VL_REGNUM)
1599 (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
1600 (set (reg:SI VTYPE_REGNUM)
1601 (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
1602 (match_dup 5)] UNSPEC_VSETVL))])]
1603 ""
1604 [(set_attr "type" "vsetvl")
1605 (set_attr "mode" "SI")])
1607 ;; This pattern use to combine bellow two insns and then further remove
1608 ;; unnecessary sign_extend operations:
1609 ;; (set (reg:DI 134 [ _1 ])
1610 ;; (unspec:DI [
1611 ;; (const_int 19 [0x13])
1612 ;; (const_int 8 [0x8])
1613 ;; (const_int 5 [0x5])
1614 ;; (const_int 2 [0x2]) repeated x2
1615 ;; ] UNSPEC_VSETVL))
1616 ;; (set (reg/v:DI 135 [ <retval> ])
1617 ;; (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0)))
1618 ;;
1619 ;; The reason we can remove signe_extend is because currently the vl value
1620 ;; returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and
1621 ;; bits 17 to 63 (including 31) are always 0, so there is no change after
1622 ;; sign_extend. Note that for HI and QI modes we cannot do this.
1623 ;; Of course, if the range of instructions returned by vsetvl later expands
1624 ;; to 32bits, then this combine pattern needs to be removed. But that could be
1625 ;; a long time from now.
1626 (define_insn_and_split "*vsetvldi_no_side_effects_si_extend"
1627 [(set (match_operand:DI 0 "register_operand")
1628 (sign_extend:DI
1629 (subreg:SI
1630 (unspec:DI [(match_operand:P 1 "csr_operand")
1631 (match_operand 2 "const_int_operand")
1632 (match_operand 3 "const_int_operand")
1633 (match_operand 4 "const_int_operand")
1634 (match_operand 5 "const_int_operand")] UNSPEC_VSETVL) 0)))]
1635 "TARGET_VECTOR && TARGET_64BIT"
1636 "#"
1637 "&& 1"
1638 [(set (match_dup 0)
1639 (unspec:DI [(match_dup 1)
1640 (match_dup 2)
1641 (match_dup 3)
1642 (match_dup 4)
1643 (match_dup 5)] UNSPEC_VSETVL))]
1644 ""
1645 [(set_attr "type" "vsetvl")
1646 (set_attr "mode" "SI")])
1648 ;; RVV machine description matching format
1649 ;; (define_insn ""
1650 ;; [(set (match_operand:MODE 0)
1651 ;; (if_then_else:MODE
1652 ;; (unspec:<MODE:VM>
1653 ;; [(match_operand:<VM> 1 "vector_mask_operand")
1654 ;; (match_operand N + 4 "vector_length_operand")
1655 ;; (match_operand N + 5 "const_int_operand")
1656 ;; (match_operand N + 6 "const_int_operand")
1657 ;; (reg:SI VL_REGNUM)
1658 ;; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1659 ;; (instruction operation:MODE
1660 ;; (match_operand 3
1661 ;; (match_operand 4
1662 ;; (match_operand 5
1663 ;; ................
1664 ;; (match_operand N + 3)
1665 ;; (match_operand:MODE 2 "vector_reg_or_const0_operand")))]
1666 ;;
1667 ;; (unspec:[........] UNSPEC_VPREDICATE) is a predicate wrapper.
1668 ;; Include mask predicate && length predicate && vector policy.
1670 ;; -------------------------------------------------------------------------------
1671 ;; ---- Predicated Mov
1672 ;; -------------------------------------------------------------------------------
1673 ;; Includes:
1674 ;; - 7.4. Vector Unit-Stride Instructions
1675 ;; - 11.15 Vector Integer Merge Instructions
1676 ;; - 11.16 Vector Integer Move Instructions
1677 ;; - 13.16 Vector Floating-Point Move Instruction
1678 ;; - 15.1 Vector Mask-Register Logical Instructions
1679 ;; -------------------------------------------------------------------------------
1681 ;; vle.v/vse.v/vmv.v.v.
1682 ;; For vle.v/vmv.v.v, we may need merge and mask operand.
1683 ;; For vse.v, we don't need merge operand, so it should always match "vu".
1684 ;; constraint alternative 0 ~ 1 match vle.v.
1685 ;; constraint alternative 2 match vse.v.
1686 ;; constraint alternative 3 match vmv.v.v.
1688 ;; If operand 3 is a const_vector, then it is left to pred_braordcast patterns.
1689 (define_expand "@pred_mov<mode>"
1690 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1691 (if_then_else:V_VLS
1692 (unspec:<VM>
1693 [(match_operand:<VM> 1 "vector_mask_operand")
1694 (match_operand 4 "vector_length_operand")
1695 (match_operand 5 "const_int_operand")
1696 (match_operand 6 "const_int_operand")
1697 (match_operand 7 "const_int_operand")
1698 (reg:SI VL_REGNUM)
1699 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1700 (match_operand:V_VLS 3 "vector_move_operand")
1701 (match_operand:V_VLS 2 "vector_merge_operand")))]
1702 "TARGET_VECTOR"
1703 {})
1705 ;; vle.v/vse.v,vmv.v.v
1706 (define_insn_and_split "*pred_mov<mode>"
1707 [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=vr, vr, vd, m, vr, vr")
1708 (if_then_else:V_VLS
1709 (unspec:<VM>
1710 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, Wc1")
1711 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
1712 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
1713 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
1714 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
1715 (reg:SI VL_REGNUM)
1716 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1717 (match_operand:V_VLS 3 "reg_or_mem_operand" " m, m, m, vr, vr, vr")
1718 (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, vu, vu, 0")))]
1719 "(TARGET_VECTOR
1720 && (register_operand (operands[0], <MODE>mode)
1721 || register_operand (operands[3], <MODE>mode)))"
1722 "@
1723 vle<sew>.v\t%0,%3%p1
1724 vle<sew>.v\t%0,%3
1725 vle<sew>.v\t%0,%3,%1.t
1726 vse<sew>.v\t%3,%0%p1
1727 vmv.v.v\t%0,%3
1728 vmv.v.v\t%0,%3"
1729 "&& register_operand (operands[0], <MODE>mode)
1730 && register_operand (operands[3], <MODE>mode)
1731 && satisfies_constraint_vu (operands[2])
1732 && INTVAL (operands[7]) == riscv_vector::VLMAX"
1733 [(set (match_dup 0) (match_dup 3))]
1734 ""
1735 [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
1736 (set_attr "mode" "<MODE>")])
1738 ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include
1739 ;; memory operand as input which will produce inferior codegen.
1740 (define_insn "@pred_store<mode>"
1741 [(set (match_operand:V 0 "memory_operand" "+m")
1742 (if_then_else:V
1743 (unspec:<VM>
1744 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
1745 (match_operand 3 "vector_length_operand" " rK")
1746 (match_operand 4 "const_int_operand" " i")
1747 (reg:SI VL_REGNUM)
1748 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1749 (match_operand:V 2 "register_operand" " vr")
1750 (match_dup 0)))]
1751 "TARGET_VECTOR"
1752 "vse<sew>.v\t%2,%0%p1"
1753 [(set_attr "type" "vste")
1754 (set_attr "mode" "<MODE>")
1755 (set (attr "avl_type_idx") (const_int 4))
1756 (set_attr "vl_op_idx" "3")])
1758 ;; vlm.v/vsm.v/vmclr.m/vmset.m.
1759 ;; constraint alternative 0 match vlm.v.
1760 ;; constraint alternative 1 match vsm.v.
1761 ;; constraint alternative 3 match vmclr.m.
1762 ;; constraint alternative 4 match vmset.m.
1763 (define_insn_and_split "@pred_mov<mode>"
1764 [(set (match_operand:VB_VLS 0 "nonimmediate_operand" "=vr, m, vr, vr, vr")
1765 (if_then_else:VB_VLS
1766 (unspec:VB_VLS
1767 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
1768 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
1769 (match_operand 5 "const_int_operand" " i, i, i, i, i")
1770 (reg:SI VL_REGNUM)
1771 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1772 (match_operand:VB_VLS 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
1773 (match_operand:VB_VLS 2 "vector_undef_operand" " vu, vu, vu, vu, vu")))]
1774 "TARGET_VECTOR"
1775 "@
1776 vlm.v\t%0,%3
1777 vsm.v\t%3,%0
1778 vmmv.m\t%0,%3
1779 vmclr.m\t%0
1780 vmset.m\t%0"
1781 "&& register_operand (operands[0], <MODE>mode)
1782 && register_operand (operands[3], <MODE>mode)
1783 && INTVAL (operands[5]) == riscv_vector::VLMAX"
1784 [(set (match_dup 0) (match_dup 3))]
1785 ""
1786 [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu")
1787 (set_attr "mode" "<MODE>")])
1789 ;; Dedicated pattern for vsm.v instruction since we can't reuse pred_mov pattern to include
1790 ;; memory operand as input which will produce inferior codegen.
1791 (define_insn "@pred_store<mode>"
1792 [(set (match_operand:VB 0 "memory_operand" "+m")
1793 (if_then_else:VB
1794 (unspec:VB
1795 [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
1796 (match_operand 3 "vector_length_operand" " rK")
1797 (match_operand 4 "const_int_operand" " i")
1798 (reg:SI VL_REGNUM)
1799 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1800 (match_operand:VB 2 "register_operand" " vr")
1801 (match_dup 0)))]
1802 "TARGET_VECTOR"
1803 "vsm.v\t%2,%0"
1804 [(set_attr "type" "vstm")
1805 (set_attr "mode" "<MODE>")
1806 (set (attr "avl_type_idx") (const_int 4))
1807 (set_attr "vl_op_idx" "3")])
1809 (define_insn "@pred_merge<mode>"
1810 [(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd")
1811 (if_then_else:V_VLS
1812 (unspec:<VM>
1813 [(match_operand 5 "vector_length_operand" " rK,rK,rK,rK")
1814 (match_operand 6 "const_int_operand" " i, i, i, i")
1815 (match_operand 7 "const_int_operand" " i, i, i, i")
1816 (reg:SI VL_REGNUM)
1817 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1818 (vec_merge:V_VLS
1819 (match_operand:V_VLS 3 "vector_arith_operand" " vr,vr,vi,vi")
1820 (match_operand:V_VLS 2 "register_operand" " vr,vr,vr,vr")
1821 (match_operand:<VM> 4 "register_operand" " vm,vm,vm,vm"))
1822 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0,vu, 0")))]
1823 "TARGET_VECTOR"
1824 "vmerge.v%o3m\t%0,%2,%v3,%4"
1825 [(set_attr "type" "vimerge")
1826 (set_attr "mode" "<MODE>")])
1828 (define_insn "@pred_merge<mode>_scalar"
1829 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd")
1830 (if_then_else:V_VLSI_QHS
1831 (unspec:<VM>
1832 [(match_operand 5 "vector_length_operand" " rK,rK")
1833 (match_operand 6 "const_int_operand" " i, i")
1834 (match_operand 7 "const_int_operand" " i, i")
1835 (reg:SI VL_REGNUM)
1836 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1837 (vec_merge:V_VLSI_QHS
1838 (vec_duplicate:V_VLSI_QHS
1839 (match_operand:<VEL> 3 "register_operand" " r, r"))
1840 (match_operand:V_VLSI_QHS 2 "register_operand" " vr,vr")
1841 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1842 (match_operand:V_VLSI_QHS 1 "vector_merge_operand" " vu, 0")))]
1843 "TARGET_VECTOR"
1844 "vmerge.vxm\t%0,%2,%3,%4"
1845 [(set_attr "type" "vimerge")
1846 (set_attr "mode" "<MODE>")])
1848 (define_expand "@pred_merge<mode>_scalar"
1849 [(set (match_operand:V_VLSI_D 0 "register_operand")
1850 (if_then_else:V_VLSI_D
1851 (unspec:<VM>
1852 [(match_operand 5 "vector_length_operand")
1853 (match_operand 6 "const_int_operand")
1854 (match_operand 7 "const_int_operand")
1855 (reg:SI VL_REGNUM)
1856 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1857 (vec_merge:V_VLSI_D
1858 (vec_duplicate:V_VLSI_D
1859 (match_operand:<VEL> 3 "reg_or_int_operand"))
1860 (match_operand:V_VLSI_D 2 "register_operand")
1861 (match_operand:<VM> 4 "register_operand"))
1862 (match_operand:V_VLSI_D 1 "vector_merge_operand")))]
1863 "TARGET_VECTOR"
1864 {
1865 if (riscv_vector::sew64_scalar_helper (
1866 operands,
1867 /* scalar op */&operands[3],
1868 /* vl */operands[5],
1869 <MODE>mode,
1870 riscv_vector::simm5_p (operands[3]),
1871 [] (rtx *operands, rtx boardcast_scalar) {
1872 emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
1873 operands[2], boardcast_scalar, operands[4], operands[5],
1874 operands[6], operands[7]));
1875 },
1876 (riscv_vector::avl_type) INTVAL (operands[7])))
1877 DONE;
1878 })
1880 (define_insn "*pred_merge<mode>_scalar"
1881 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1882 (if_then_else:V_VLSI_D
1883 (unspec:<VM>
1884 [(match_operand 5 "vector_length_operand" " rK,rK")
1885 (match_operand 6 "const_int_operand" " i, i")
1886 (match_operand 7 "const_int_operand" " i, i")
1887 (reg:SI VL_REGNUM)
1888 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1889 (vec_merge:V_VLSI_D
1890 (vec_duplicate:V_VLSI_D
1891 (match_operand:<VEL> 3 "register_operand" " r, r"))
1892 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1893 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1894 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1895 "TARGET_VECTOR"
1896 "vmerge.vxm\t%0,%2,%3,%4"
1897 [(set_attr "type" "vimerge")
1898 (set_attr "mode" "<MODE>")])
1900 (define_insn "*pred_merge<mode>_extended_scalar"
1901 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1902 (if_then_else:V_VLSI_D
1903 (unspec:<VM>
1904 [(match_operand 5 "vector_length_operand" " rK,rK")
1905 (match_operand 6 "const_int_operand" " i, i")
1906 (match_operand 7 "const_int_operand" " i, i")
1907 (reg:SI VL_REGNUM)
1908 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1909 (vec_merge:V_VLSI_D
1910 (vec_duplicate:V_VLSI_D
1911 (sign_extend:<VEL>
1912 (match_operand:<VSUBEL> 3 "register_operand" " r, r")))
1913 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1914 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1915 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1916 "TARGET_VECTOR"
1917 "vmerge.vxm\t%0,%2,%3,%4"
1918 [(set_attr "type" "vimerge")
1919 (set_attr "mode" "<MODE>")])
1921 ;; -------------------------------------------------------------------------------
1922 ;; ---- Predicated Broadcast
1923 ;; -------------------------------------------------------------------------------
1924 ;; Includes:
1925 ;; - 7.5. Vector Strided Instructions (zero stride)
1926 ;; - 11.16 Vector Integer Move Instructions (vmv.v.x)
1927 ;; - 13.16 Vector Floating-Point Move Instruction (vfmv.v.f)
1928 ;; - 16.1 Integer Scalar Move Instructions (vmv.s.x)
1929 ;; - 16.2 Floating-Point Scalar Move Instructions (vfmv.s.f)
1930 ;; -------------------------------------------------------------------------------
1932 ;; According to RVV ISA, vector-scalar instruction doesn't support
1933 ;; operand fetched from 2 consecutive registers, so we should use
1934 ;; vlse.v which is a memory access to broadcast a DImode scalar into a vector.
1935 ;;
1936 ;; Since the optimization flow in GCC is as follows:
1937 ;; expand --> LICM (Loop invariant) --> split.
1938 ;; To use LICM optimization, we postpone generation of vlse.v to split stage since
1939 ;; a memory access instruction can not be optimized by LICM (Loop invariant).
1940 (define_expand "@pred_broadcast<mode>"
1941 [(set (match_operand:V_VLS 0 "register_operand")
1942 (if_then_else:V_VLS
1943 (unspec:<VM>
1944 [(match_operand:<VM> 1 "vector_broadcast_mask_operand")
1945 (match_operand 4 "vector_length_operand")
1946 (match_operand 5 "const_int_operand")
1947 (match_operand 6 "const_int_operand")
1948 (match_operand 7 "const_int_operand")
1949 (reg:SI VL_REGNUM)
1950 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1951 (vec_duplicate:V_VLS
1952 (match_operand:<VEL> 3 "direct_broadcast_operand"))
1953 (match_operand:V_VLS 2 "vector_merge_operand")))]
1954 "TARGET_VECTOR"
1955 {
1956 /* Handle vmv.s.x instruction (Wb1 mask) which has memory scalar. */
1957 if (satisfies_constraint_Wdm (operands[3]))
1958 {
1959 if (satisfies_constraint_Wb1 (operands[1]))
1960 {
1961 /* Case 1: vmv.s.x (TA, x == memory) ==> vlse.v (TA) */
1962 if (satisfies_constraint_vu (operands[2]))
1963 operands[1] = CONSTM1_RTX (<VM>mode);
1964 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
1965 {
1966 /* Case 2: vmv.s.x (TU, x == memory) ==>
1967 vl = 0 or 1; + vlse.v (TU) in RV32 system */
1968 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
1969 operands[1] = CONSTM1_RTX (<VM>mode);
1970 }
1971 else
1972 /* Case 3: load x (memory) to register. */
1973 operands[3] = force_reg (<VEL>mode, operands[3]);
1974 }
1975 }
1976 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)
1977 && (immediate_operand (operands[3], Pmode)
1978 || (CONST_POLY_INT_P (operands[3])
1979 && known_ge (rtx_to_poly_int64 (operands[3]), 0U)
1980 && known_le (rtx_to_poly_int64 (operands[3]), GET_MODE_SIZE (<MODE>mode)))))
1981 {
1982 rtx tmp = gen_reg_rtx (Pmode);
1983 poly_int64 value = rtx_to_poly_int64 (operands[3]);
1984 emit_move_insn (tmp, gen_int_mode (value, Pmode));
1985 operands[3] = gen_rtx_SIGN_EXTEND (<VEL>mode, tmp);
1986 }
1987 else
1988 operands[3] = force_reg (<VEL>mode, operands[3]);
1989 })
1991 (define_insn_and_split "*pred_broadcast<mode>"
1992 [(set (match_operand:V_VLSI 0 "register_operand" "=vr, vr, vd, vd, vr, vr, vr, vr")
1993 (if_then_else:V_VLSI
1994 (unspec:<VM>
1995 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
1996 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
1997 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
1998 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
1999 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2000 (reg:SI VL_REGNUM)
2001 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2002 (vec_duplicate:V_VLSI
2003 (match_operand:<VEL> 3 "direct_broadcast_operand" " r, r,Wdm,Wdm,Wdm,Wdm, r, r"))
2004 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2005 "TARGET_VECTOR"
2006 "@
2007 vmv.v.x\t%0,%3
2008 vmv.v.x\t%0,%3
2009 vlse<sew>.v\t%0,%3,zero,%1.t
2010 vlse<sew>.v\t%0,%3,zero,%1.t
2011 vlse<sew>.v\t%0,%3,zero
2012 vlse<sew>.v\t%0,%3,zero
2013 vmv.s.x\t%0,%3
2014 vmv.s.x\t%0,%3"
2015 "(register_operand (operands[3], <VEL>mode)
2016 || CONST_POLY_INT_P (operands[3]))
2017 && GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)"
2018 [(set (match_dup 0)
2019 (if_then_else:V_VLSI (unspec:<VM> [(match_dup 1) (match_dup 4)
2020 (match_dup 5) (match_dup 6) (match_dup 7)
2021 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2022 (vec_duplicate:V_VLSI (match_dup 3))
2023 (match_dup 2)))]
2024 {
2025 gcc_assert (can_create_pseudo_p ());
2026 if (CONST_POLY_INT_P (operands[3]))
2027 {
2028 rtx tmp = gen_reg_rtx (<VEL>mode);
2029 emit_move_insn (tmp, operands[3]);
2030 operands[3] = tmp;
2031 }
2032 rtx m = assign_stack_local (<VEL>mode, GET_MODE_SIZE (<VEL>mode),
2033 GET_MODE_ALIGNMENT (<VEL>mode));
2034 m = validize_mem (m);
2035 emit_move_insn (m, operands[3]);
2036 m = gen_rtx_MEM (<VEL>mode, force_reg (Pmode, XEXP (m, 0)));
2037 operands[3] = m;
2039 /* For SEW = 64 in RV32 system, we expand vmv.s.x:
2040 andi a2,a2,1
2041 vsetvl zero,a2,e64
2042 vlse64.v */
2043 if (satisfies_constraint_Wb1 (operands[1]))
2044 {
2045 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2046 operands[1] = CONSTM1_RTX (<VM>mode);
2047 }
2048 }
2049 [(set_attr "type" "vimov,vimov,vlds,vlds,vlds,vlds,vimovxv,vimovxv")
2050 (set_attr "mode" "<MODE>")])
2052 (define_insn "*pred_broadcast<mode>"
2053 [(set (match_operand:V_VLSF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, vr, vr")
2054 (if_then_else:V_VLSF_ZVFHMIN
2055 (unspec:<VM>
2056 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
2057 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
2058 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
2059 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2060 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2061 (reg:SI VL_REGNUM)
2062 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2063 (vec_duplicate:V_VLSF_ZVFHMIN
2064 (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
2065 (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2066 "TARGET_VECTOR"
2067 "@
2068 vfmv.v.f\t%0,%3
2069 vfmv.v.f\t%0,%3
2070 vlse<sew>.v\t%0,%3,zero,%1.t
2071 vlse<sew>.v\t%0,%3,zero,%1.t
2072 vlse<sew>.v\t%0,%3,zero
2073 vlse<sew>.v\t%0,%3,zero
2074 vfmv.s.f\t%0,%3
2075 vfmv.s.f\t%0,%3"
2076 [(set_attr "type" "vfmov,vfmov,vlds,vlds,vlds,vlds,vfmovfv,vfmovfv")
2077 (set_attr "mode" "<MODE>")])
2079 (define_insn "*pred_broadcast<mode>_extended_scalar"
2080 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vr, vr, vr, vr")
2081 (if_then_else:V_VLSI_D
2082 (unspec:<VM>
2083 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,Wb1,Wb1")
2084 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
2085 (match_operand 5 "const_int_operand" " i, i, i, i")
2086 (match_operand 6 "const_int_operand" " i, i, i, i")
2087 (match_operand 7 "const_int_operand" " i, i, i, i")
2088 (reg:SI VL_REGNUM)
2089 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2090 (vec_duplicate:V_VLSI_D
2091 (sign_extend:<VEL>
2092 (match_operand:<VSUBEL> 3 "register_operand" " r, r, r, r")))
2093 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2094 "TARGET_VECTOR"
2095 "@
2096 vmv.v.x\t%0,%3
2097 vmv.v.x\t%0,%3
2098 vmv.s.x\t%0,%3
2099 vmv.s.x\t%0,%3"
2100 [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
2101 (set_attr "mode" "<MODE>")])
2103 (define_insn "*pred_broadcast<mode>_zero"
2104 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2105 (if_then_else:V_VLS
2106 (unspec:<VM>
2107 [(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1, Wb1")
2108 (match_operand 4 "vector_length_operand" " rK, rK")
2109 (match_operand 5 "const_int_operand" " i, i")
2110 (match_operand 6 "const_int_operand" " i, i")
2111 (match_operand 7 "const_int_operand" " i, i")
2112 (reg:SI VL_REGNUM)
2113 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2114 (match_operand:V_VLS 3 "vector_const_0_operand" "Wc0, Wc0")
2115 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2116 "TARGET_VECTOR"
2117 "vmv.s.x\t%0,zero"
2118 [(set_attr "type" "vimovxv,vimovxv")
2119 (set_attr "mode" "<MODE>")])
2121 ;; Because (vec_duplicate imm) will be converted to (const_vector imm),
2122 ;; This pattern is used to handle this case.
2123 (define_insn "*pred_broadcast<mode>_imm"
2124 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2125 (if_then_else:V_VLS
2126 (unspec:<VM>
2127 [(match_operand:<VM> 1 "vector_all_trues_mask_operand" " Wc1, Wc1")
2128 (match_operand 4 "vector_length_operand" " rK, rK")
2129 (match_operand 5 "const_int_operand" " i, i")
2130 (match_operand 6 "const_int_operand" " i, i")
2131 (match_operand 7 "const_int_operand" " i, i")
2132 (reg:SI VL_REGNUM)
2133 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2134 (match_operand:V_VLS 3 "vector_const_int_or_double_0_operand" "viWc0, viWc0")
2135 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2136 "TARGET_VECTOR"
2137 "vmv.v.i\t%0,%v3"
2138 [(set_attr "type" "vimov,vimov")
2139 (set_attr "mode" "<MODE>")])
2141 ;; -------------------------------------------------------------------------------
2142 ;; ---- Predicated Strided loads/stores
2143 ;; -------------------------------------------------------------------------------
2144 ;; Includes:
2145 ;; - 7.5. Vector Strided Instructions
2146 ;; -------------------------------------------------------------------------------
2148 (define_insn "@pred_strided_load<mode>"
2149 [(set (match_operand:V 0 "register_operand" "=vr, vr, vd, vr, vr, vd")
2150 (if_then_else:V
2151 (unspec:<VM>
2152 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, vm")
2153 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2154 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2155 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2156 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2157 (reg:SI VL_REGNUM)
2158 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2159 (unspec:V
2160 [(match_operand:V 3 "memory_operand" " m, m, m, m, m, m")
2161 (match_operand 4 "<V:stride_predicate>" "<V:stride_load_constraint>")] UNSPEC_STRIDED)
2162 (match_operand:V 2 "vector_merge_operand" " 0, vu, vu, 0, vu, vu")))]
2163 "TARGET_VECTOR"
2164 "@
2165 vlse<sew>.v\t%0,%3,%z4%p1
2166 vlse<sew>.v\t%0,%3,%z4
2167 vlse<sew>.v\t%0,%3,%z4,%1.t
2168 vle<sew>.v\t%0,%3%p1
2169 vle<sew>.v\t%0,%3
2170 vle<sew>.v\t%0,%3,%1.t"
2171 [(set_attr "type" "vlds")
2172 (set_attr "mode" "<MODE>")])
2174 (define_insn "@pred_strided_store<mode>"
2175 [(set (match_operand:V 0 "memory_operand" "+m, m")
2176 (if_then_else:V
2177 (unspec:<VM>
2178 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
2179 (match_operand 4 "vector_length_operand" " rK, rK")
2180 (match_operand 5 "const_int_operand" " i, i")
2181 (reg:SI VL_REGNUM)
2182 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2183 (unspec:V
2184 [(match_operand 2 "<V:stride_predicate>" "<V:stride_store_constraint>")
2185 (match_operand:V 3 "register_operand" " vr, vr")] UNSPEC_STRIDED)
2186 (match_dup 0)))]
2187 "TARGET_VECTOR"
2188 "@
2189 vsse<sew>.v\t%3,%0,%z2%p1
2190 vse<sew>.v\t%3,%0%p1"
2191 [(set_attr "type" "vsts")
2192 (set_attr "mode" "<MODE>")
2193 (set (attr "avl_type_idx") (const_int 5))])
2195 ;; -------------------------------------------------------------------------------
2196 ;; ---- Predicated indexed loads/stores
2197 ;; -------------------------------------------------------------------------------
2198 ;; Includes:
2199 ;; - 7.6. Vector Indexed Instructions
2200 ;; -------------------------------------------------------------------------------
2202 ;; DEST eew is same as SOURCE eew, DEST register can overlap SOURCE.
2203 (define_insn "@pred_indexed_<order>load<mode>_same_eew"
2204 [(set (match_operand:VINDEXED 0 "register_operand" "=vd, vr,vd, vr")
2205 (if_then_else:VINDEXED
2206 (unspec:<VM>
2207 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
2208 (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
2209 (match_operand 6 "const_int_operand" " i, i, i, i")
2210 (match_operand 7 "const_int_operand" " i, i, i, i")
2211 (match_operand 8 "const_int_operand" " i, i, i, i")
2212 (reg:SI VL_REGNUM)
2213 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2214 (unspec:VINDEXED
2215 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ")
2216 (mem:BLK (scratch))
2217 (match_operand:<VINDEX> 4 "register_operand" " vr, vr,vr, vr")] ORDER)
2218 (match_operand:VINDEXED 2 "vector_merge_operand" " vu, vu, 0, 0")))]
2219 "TARGET_VECTOR"
2220 "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"
2221 [(set_attr "type" "vld<order>x")
2222 (set_attr "mode" "<MODE>")])
2224 ;; DEST eew is greater than SOURCE eew.
2225 (define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew"
2226 [(set (match_operand:VEEWEXT2 0 "register_operand" "=&vr, &vr")
2227 (if_then_else:VEEWEXT2
2228 (unspec:<VM>
2229 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2230 (match_operand 5 "vector_length_operand" " rK, rK")
2231 (match_operand 6 "const_int_operand" " i, i")
2232 (match_operand 7 "const_int_operand" " i, i")
2233 (match_operand 8 "const_int_operand" " i, i")
2234 (reg:SI VL_REGNUM)
2235 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2236 (unspec:VEEWEXT2
2237 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2238 (mem:BLK (scratch))
2239 (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2240 (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, 0")))]
2241 "TARGET_VECTOR"
2242 "vl<order>xei<double_trunc_sew>.v\t%0,(%z3),%4%p1"
2243 [(set_attr "type" "vld<order>x")
2244 (set_attr "mode" "<MODE>")])
2246 (define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew"
2247 [(set (match_operand:VEEWEXT4 0 "register_operand" "=&vr, &vr")
2248 (if_then_else:VEEWEXT4
2249 (unspec:<VM>
2250 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2251 (match_operand 5 "vector_length_operand" " rK, rK")
2252 (match_operand 6 "const_int_operand" " i, i")
2253 (match_operand 7 "const_int_operand" " i, i")
2254 (match_operand 8 "const_int_operand" " i, i")
2255 (reg:SI VL_REGNUM)
2256 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2257 (unspec:VEEWEXT4
2258 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2259 (mem:BLK (scratch))
2260 (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2261 (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, 0")))]
2262 "TARGET_VECTOR"
2263 "vl<order>xei<quad_trunc_sew>.v\t%0,(%z3),%4%p1"
2264 [(set_attr "type" "vld<order>x")
2265 (set_attr "mode" "<MODE>")])
2267 (define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew"
2268 [(set (match_operand:VEEWEXT8 0 "register_operand" "=&vr, &vr")
2269 (if_then_else:VEEWEXT8
2270 (unspec:<VM>
2271 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
2272 (match_operand 5 "vector_length_operand" " rK, rK")
2273 (match_operand 6 "const_int_operand" " i, i")
2274 (match_operand 7 "const_int_operand" " i, i")
2275 (match_operand 8 "const_int_operand" " i, i")
2276 (reg:SI VL_REGNUM)
2277 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2278 (unspec:VEEWEXT8
2279 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
2280 (mem:BLK (scratch))
2281 (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" " vr, vr")] ORDER)
2282 (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, 0")))]
2283 "TARGET_VECTOR"
2284 "vl<order>xei<oct_trunc_sew>.v\t%0,(%z3),%4%p1"
2285 [(set_attr "type" "vld<order>x")
2286 (set_attr "mode" "<MODE>")])
2288 ;; DEST eew is smaller than SOURCE eew.
2289 (define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew"
2290 [(set (match_operand:VEEWTRUNC2 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2291 (if_then_else:VEEWTRUNC2
2292 (unspec:<VM>
2293 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2294 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2295 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2296 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2297 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2298 (reg:SI VL_REGNUM)
2299 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2300 (unspec:VEEWTRUNC2
2301 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2302 (mem:BLK (scratch))
2303 (match_operand:<VINDEX_DOUBLE_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2304 (match_operand:VEEWTRUNC2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2305 "TARGET_VECTOR"
2306 "vl<order>xei<double_ext_sew>.v\t%0,(%z3),%4%p1"
2307 [(set_attr "type" "vld<order>x")
2308 (set_attr "mode" "<MODE>")])
2310 (define_insn "@pred_indexed_<order>load<mode>_x4_smaller_eew"
2311 [(set (match_operand:VEEWTRUNC4 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2312 (if_then_else:VEEWTRUNC4
2313 (unspec:<VM>
2314 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2315 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2316 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2317 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2318 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2319 (reg:SI VL_REGNUM)
2320 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2321 (unspec:VEEWTRUNC4
2322 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2323 (mem:BLK (scratch))
2324 (match_operand:<VINDEX_QUAD_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2325 (match_operand:VEEWTRUNC4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2326 "TARGET_VECTOR"
2327 "vl<order>xei<quad_ext_sew>.v\t%0,(%z3),%4%p1"
2328 [(set_attr "type" "vld<order>x")
2329 (set_attr "mode" "<MODE>")])
2331 (define_insn "@pred_indexed_<order>load<mode>_x8_smaller_eew"
2332 [(set (match_operand:VEEWTRUNC8 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2333 (if_then_else:VEEWTRUNC8
2334 (unspec:<VM>
2335 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2336 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2337 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2338 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2339 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2340 (reg:SI VL_REGNUM)
2341 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2342 (unspec:VEEWTRUNC8
2343 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2344 (mem:BLK (scratch))
2345 (match_operand:<VINDEX_OCT_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2346 (match_operand:VEEWTRUNC8 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2347 "TARGET_VECTOR"
2348 "vl<order>xei<oct_ext_sew>.v\t%0,(%z3),%4%p1"
2349 [(set_attr "type" "vld<order>x")
2350 (set_attr "mode" "<MODE>")])
2352 (define_insn "@pred_indexed_<order>store<RATIO64:mode><RATIO64I:mode>"
2353 [(set (mem:BLK (scratch))
2354 (unspec:BLK
2355 [(unspec:<VM>
2356 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2357 (match_operand 4 "vector_length_operand" " rK")
2358 (match_operand 5 "const_int_operand" " i")
2359 (reg:SI VL_REGNUM)
2360 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2361 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2362 (match_operand:RATIO64I 2 "register_operand" " vr")
2363 (match_operand:RATIO64 3 "register_operand" " vr")] ORDER))]
2364 "TARGET_VECTOR"
2365 "vs<order>xei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
2366 [(set_attr "type" "vst<order>x")
2367 (set_attr "mode" "<RATIO64:MODE>")])
2369 (define_insn "@pred_indexed_<order>store<RATIO32:mode><RATIO32I:mode>"
2370 [(set (mem:BLK (scratch))
2371 (unspec:BLK
2372 [(unspec:<VM>
2373 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2374 (match_operand 4 "vector_length_operand" " rK")
2375 (match_operand 5 "const_int_operand" " i")
2376 (reg:SI VL_REGNUM)
2377 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2378 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2379 (match_operand:RATIO32I 2 "register_operand" " vr")
2380 (match_operand:RATIO32 3 "register_operand" " vr")] ORDER))]
2381 "TARGET_VECTOR"
2382 "vs<order>xei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
2383 [(set_attr "type" "vst<order>x")
2384 (set_attr "mode" "<RATIO32:MODE>")])
2386 (define_insn "@pred_indexed_<order>store<RATIO16:mode><RATIO16I:mode>"
2387 [(set (mem:BLK (scratch))
2388 (unspec:BLK
2389 [(unspec:<VM>
2390 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2391 (match_operand 4 "vector_length_operand" " rK")
2392 (match_operand 5 "const_int_operand" " i")
2393 (reg:SI VL_REGNUM)
2394 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2395 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2396 (match_operand:RATIO16I 2 "register_operand" " vr")
2397 (match_operand:RATIO16 3 "register_operand" " vr")] ORDER))]
2398 "TARGET_VECTOR"
2399 "vs<order>xei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
2400 [(set_attr "type" "vst<order>x")
2401 (set_attr "mode" "<RATIO16:MODE>")])
2403 (define_insn "@pred_indexed_<order>store<RATIO8:mode><RATIO8I:mode>"
2404 [(set (mem:BLK (scratch))
2405 (unspec:BLK
2406 [(unspec:<VM>
2407 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2408 (match_operand 4 "vector_length_operand" " rK")
2409 (match_operand 5 "const_int_operand" " i")
2410 (reg:SI VL_REGNUM)
2411 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2412 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2413 (match_operand:RATIO8I 2 "register_operand" " vr")
2414 (match_operand:RATIO8 3 "register_operand" " vr")] ORDER))]
2415 "TARGET_VECTOR"
2416 "vs<order>xei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
2417 [(set_attr "type" "vst<order>x")
2418 (set_attr "mode" "<RATIO8:MODE>")])
2420 (define_insn "@pred_indexed_<order>store<RATIO4:mode><RATIO4I:mode>"
2421 [(set (mem:BLK (scratch))
2422 (unspec:BLK
2423 [(unspec:<VM>
2424 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2425 (match_operand 4 "vector_length_operand" " rK")
2426 (match_operand 5 "const_int_operand" " i")
2427 (reg:SI VL_REGNUM)
2428 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2429 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2430 (match_operand:RATIO4I 2 "register_operand" " vr")
2431 (match_operand:RATIO4 3 "register_operand" " vr")] ORDER))]
2432 "TARGET_VECTOR"
2433 "vs<order>xei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
2434 [(set_attr "type" "vst<order>x")
2435 (set_attr "mode" "<RATIO4:MODE>")])
2437 (define_insn "@pred_indexed_<order>store<RATIO2:mode><RATIO2I:mode>"
2438 [(set (mem:BLK (scratch))
2439 (unspec:BLK
2440 [(unspec:<VM>
2441 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2442 (match_operand 4 "vector_length_operand" " rK")
2443 (match_operand 5 "const_int_operand" " i")
2444 (reg:SI VL_REGNUM)
2445 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2446 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2447 (match_operand:RATIO2I 2 "register_operand" " vr")
2448 (match_operand:RATIO2 3 "register_operand" " vr")] ORDER))]
2449 "TARGET_VECTOR"
2450 "vs<order>xei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
2451 [(set_attr "type" "vst<order>x")
2452 (set_attr "mode" "<RATIO2:MODE>")])
2454 (define_insn "@pred_indexed_<order>store<RATIO1:mode><RATIO1:mode>"
2455 [(set (mem:BLK (scratch))
2456 (unspec:BLK
2457 [(unspec:<VM>
2458 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2459 (match_operand 4 "vector_length_operand" " rK")
2460 (match_operand 5 "const_int_operand" " i")
2461 (reg:SI VL_REGNUM)
2462 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2463 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2464 (match_operand:RATIO1 2 "register_operand" " vr")
2465 (match_operand:RATIO1 3 "register_operand" " vr")] ORDER))]
2466 "TARGET_VECTOR"
2467 "vs<order>xei<RATIO1:sew>.v\t%3,(%z1),%2%p0"
2468 [(set_attr "type" "vst<order>x")
2469 (set_attr "mode" "<RATIO1:MODE>")])
2471 ;; -------------------------------------------------------------------------------
2472 ;; ---- Predicated integer binary operations
2473 ;; -------------------------------------------------------------------------------
2474 ;; Includes:
2475 ;; - 11.1 Vector Single-Width Integer Add and Subtract
2476 ;; - 11.4 Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions
2477 ;; - 11.5 Vector Bitwise Logical Instructions
2478 ;; - 11.6 Vector Single-Width Bit Shift Instructions
2479 ;; - 11.9 Vector Integer Min/Max Instructions
2480 ;; - 11.10 Vector Single-Width Integer Multiply Instructions
2481 ;; - 11.11 Vector Integer Divide Instructions
2482 ;; -------------------------------------------------------------------------------
2484 (define_insn "@pred_<optab><mode>"
2485 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
2486 (if_then_else:V_VLSI
2487 (unspec:<VM>
2488 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
2489 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2490 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2491 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2492 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2493 (reg:SI VL_REGNUM)
2494 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2495 (any_int_binop:V_VLSI
2496 (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
2497 (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
2498 (match_operand:V_VLSI 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
2499 "TARGET_VECTOR"
2500 "@
2501 v<insn>.vv\t%0,%3,%4%p1
2502 v<insn>.vv\t%0,%3,%4%p1
2503 v<insn>.vv\t%0,%3,%4%p1
2504 v<insn>.vv\t%0,%3,%4%p1
2505 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2506 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2507 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2508 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2509 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2510 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2511 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2512 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
2513 [(set_attr "type" "<int_binop_insn_type>")
2514 (set_attr "mode" "<MODE>")])
2516 ;; vx instructions patterns.
2517 ;; Note: Unlike vv patterns, we should split them since they are variant.
2518 ;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the
2519 ;; scalar mode is inner mode of the RVV mode for other vx patterns.
2520 (define_insn "@pred_<optab><mode>_scalar"
2521 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr,vd,vd, vr, vr")
2522 (if_then_else:V_VLSI
2523 (unspec:<VM>
2524 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
2525 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK,rK,rK, rK, rK")
2526 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2527 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2528 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
2529 (reg:SI VL_REGNUM)
2530 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2531 (any_shift:V_VLSI
2532 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr,vr,vr, vr, vr")
2533 (match_operand 4 "pmode_reg_or_uimm5_operand" " r, r, r, r, K, K, K, K"))
2534 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0,vu, 0, vu, 0")))]
2535 "TARGET_VECTOR"
2536 "v<insn>.v%o4\t%0,%3,%4%p1"
2537 [(set_attr "type" "vshift")
2538 (set_attr "mode" "<MODE>")])
2540 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
2541 (define_insn "@pred_<optab><mode>_scalar"
2542 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2543 (if_then_else:V_VLSI_QHS
2544 (unspec:<VM>
2545 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2546 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2547 (match_operand 6 "const_int_operand" " i, i, i, i")
2548 (match_operand 7 "const_int_operand" " i, i, i, i")
2549 (match_operand 8 "const_int_operand" " i, i, i, i")
2550 (reg:SI VL_REGNUM)
2551 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2552 (any_commutative_binop:V_VLSI_QHS
2553 (vec_duplicate:V_VLSI_QHS
2554 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2555 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2556 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2557 "TARGET_VECTOR"
2558 "v<insn>.vx\t%0,%3,%z4%p1"
2559 [(set_attr "type" "<int_binop_insn_type>")
2560 (set_attr "mode" "<MODE>")])
2562 (define_insn "@pred_<optab><mode>_scalar"
2563 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2564 (if_then_else:V_VLSI_QHS
2565 (unspec:<VM>
2566 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2567 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2568 (match_operand 6 "const_int_operand" " i, i, i, i")
2569 (match_operand 7 "const_int_operand" " i, i, i, i")
2570 (match_operand 8 "const_int_operand" " i, i, i, i")
2571 (reg:SI VL_REGNUM)
2572 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2573 (any_non_commutative_binop:V_VLSI_QHS
2574 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr")
2575 (vec_duplicate:V_VLSI_QHS
2576 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2577 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2578 "TARGET_VECTOR"
2579 "v<insn>.vx\t%0,%3,%z4%p1"
2580 [(set_attr "type" "<int_binop_insn_type>")
2581 (set_attr "mode" "<MODE>")])
2583 (define_insn "@pred_sub<mode>_reverse_scalar"
2584 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2585 (if_then_else:V_VLSI_QHS
2586 (unspec:<VM>
2587 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2588 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2589 (match_operand 6 "const_int_operand" " i, i, i, i")
2590 (match_operand 7 "const_int_operand" " i, i, i, i")
2591 (match_operand 8 "const_int_operand" " i, i, i, i")
2592 (reg:SI VL_REGNUM)
2593 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2594 (minus:V_VLSI_QHS
2595 (vec_duplicate:V_VLSI_QHS
2596 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2597 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2598 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2599 "TARGET_VECTOR"
2600 "vrsub.vx\t%0,%3,%z4%p1"
2601 [(set_attr "type" "vialu")
2602 (set_attr "mode" "<MODE>")])
2604 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
2605 ;; we need to deal with SEW = 64 in RV32 system.
2606 (define_expand "@pred_<optab><mode>_scalar"
2607 [(set (match_operand:V_VLSI_D 0 "register_operand")
2608 (if_then_else:V_VLSI_D
2609 (unspec:<VM>
2610 [(match_operand:<VM> 1 "vector_mask_operand")
2611 (match_operand 5 "vector_length_operand")
2612 (match_operand 6 "const_int_operand")
2613 (match_operand 7 "const_int_operand")
2614 (match_operand 8 "const_int_operand")
2615 (reg:SI VL_REGNUM)
2616 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2617 (any_commutative_binop:V_VLSI_D
2618 (vec_duplicate:V_VLSI_D
2619 (match_operand:<VEL> 4 "reg_or_int_operand"))
2620 (match_operand:V_VLSI_D 3 "register_operand"))
2621 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2622 "TARGET_VECTOR"
2623 {
2624 if (riscv_vector::sew64_scalar_helper (
2625 operands,
2626 /* scalar op */&operands[4],
2627 /* vl */operands[5],
2628 <MODE>mode,
2629 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2630 [] (rtx *operands, rtx boardcast_scalar) {
2631 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2632 operands[2], operands[3], boardcast_scalar, operands[5],
2633 operands[6], operands[7], operands[8]));
2634 },
2635 (riscv_vector::avl_type) INTVAL (operands[8])))
2636 DONE;
2637 })
2639 (define_insn "*pred_<optab><mode>_scalar"
2640 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2641 (if_then_else:V_VLSI_D
2642 (unspec:<VM>
2643 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2644 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2645 (match_operand 6 "const_int_operand" " i, i, i, i")
2646 (match_operand 7 "const_int_operand" " i, i, i, i")
2647 (match_operand 8 "const_int_operand" " i, i, i, i")
2648 (reg:SI VL_REGNUM)
2649 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2650 (any_commutative_binop:V_VLSI_D
2651 (vec_duplicate:V_VLSI_D
2652 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2653 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2654 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2655 "TARGET_VECTOR"
2656 "v<insn>.vx\t%0,%3,%z4%p1"
2657 [(set_attr "type" "<int_binop_insn_type>")
2658 (set_attr "mode" "<MODE>")])
2660 (define_insn "*pred_<optab><mode>_extended_scalar"
2661 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2662 (if_then_else:V_VLSI_D
2663 (unspec:<VM>
2664 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2665 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2666 (match_operand 6 "const_int_operand" " i, i, i, i")
2667 (match_operand 7 "const_int_operand" " i, i, i, i")
2668 (match_operand 8 "const_int_operand" " i, i, i, i")
2669 (reg:SI VL_REGNUM)
2670 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2671 (any_commutative_binop:V_VLSI_D
2672 (vec_duplicate:V_VLSI_D
2673 (sign_extend:<VEL>
2674 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2675 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2676 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2677 "TARGET_VECTOR"
2678 "v<insn>.vx\t%0,%3,%z4%p1"
2679 [(set_attr "type" "<int_binop_insn_type>")
2680 (set_attr "mode" "<MODE>")])
2682 (define_expand "@pred_<optab><mode>_scalar"
2683 [(set (match_operand:V_VLSI_D 0 "register_operand")
2684 (if_then_else:V_VLSI_D
2685 (unspec:<VM>
2686 [(match_operand:<VM> 1 "vector_mask_operand")
2687 (match_operand 5 "vector_length_operand")
2688 (match_operand 6 "const_int_operand")
2689 (match_operand 7 "const_int_operand")
2690 (match_operand 8 "const_int_operand")
2691 (reg:SI VL_REGNUM)
2692 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2693 (any_non_commutative_binop:V_VLSI_D
2694 (match_operand:V_VLSI_D 3 "register_operand")
2695 (vec_duplicate:V_VLSI_D
2696 (match_operand:<VEL> 4 "reg_or_int_operand")))
2697 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2698 "TARGET_VECTOR"
2699 {
2700 if (riscv_vector::sew64_scalar_helper (
2701 operands,
2702 /* scalar op */&operands[4],
2703 /* vl */operands[5],
2704 <MODE>mode,
2705 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2706 [] (rtx *operands, rtx boardcast_scalar) {
2707 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2708 operands[2], operands[3], boardcast_scalar, operands[5],
2709 operands[6], operands[7], operands[8]));
2710 },
2711 (riscv_vector::avl_type) INTVAL (operands[8])))
2712 DONE;
2713 })
2715 (define_insn "*pred_<optab><mode>_scalar"
2716 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2717 (if_then_else:V_VLSI_D
2718 (unspec:<VM>
2719 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2720 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2721 (match_operand 6 "const_int_operand" " i, i, i, i")
2722 (match_operand 7 "const_int_operand" " i, i, i, i")
2723 (match_operand 8 "const_int_operand" " i, i, i, i")
2724 (reg:SI VL_REGNUM)
2725 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2726 (any_non_commutative_binop:V_VLSI_D
2727 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2728 (vec_duplicate:V_VLSI_D
2729 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2730 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2731 "TARGET_VECTOR"
2732 "v<insn>.vx\t%0,%3,%z4%p1"
2733 [(set_attr "type" "<int_binop_insn_type>")
2734 (set_attr "mode" "<MODE>")])
2736 (define_insn "*pred_<optab><mode>_extended_scalar"
2737 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2738 (if_then_else:V_VLSI_D
2739 (unspec:<VM>
2740 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2741 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2742 (match_operand 6 "const_int_operand" " i, i, i, i")
2743 (match_operand 7 "const_int_operand" " i, i, i, i")
2744 (match_operand 8 "const_int_operand" " i, i, i, i")
2745 (reg:SI VL_REGNUM)
2746 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2747 (any_non_commutative_binop:V_VLSI_D
2748 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2749 (vec_duplicate:V_VLSI_D
2750 (sign_extend:<VEL>
2751 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
2752 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2753 "TARGET_VECTOR"
2754 "v<insn>.vx\t%0,%3,%z4%p1"
2755 [(set_attr "type" "<int_binop_insn_type>")
2756 (set_attr "mode" "<MODE>")])
2758 (define_expand "@pred_sub<mode>_reverse_scalar"
2759 [(set (match_operand:V_VLSI_D 0 "register_operand")
2760 (if_then_else:V_VLSI_D
2761 (unspec:<VM>
2762 [(match_operand:<VM> 1 "vector_mask_operand")
2763 (match_operand 5 "vector_length_operand")
2764 (match_operand 6 "const_int_operand")
2765 (match_operand 7 "const_int_operand")
2766 (match_operand 8 "const_int_operand")
2767 (reg:SI VL_REGNUM)
2768 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2769 (minus:V_VLSI_D
2770 (vec_duplicate:V_VLSI_D
2771 (match_operand:<VEL> 4 "reg_or_int_operand"))
2772 (match_operand:V_VLSI_D 3 "register_operand"))
2773 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2774 "TARGET_VECTOR"
2775 {
2776 if (riscv_vector::sew64_scalar_helper (
2777 operands,
2778 /* scalar op */&operands[4],
2779 /* vl */operands[5],
2780 <MODE>mode,
2781 riscv_vector::neg_simm5_p (operands[4]),
2782 [] (rtx *operands, rtx boardcast_scalar) {
2783 emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
2784 operands[2], boardcast_scalar, operands[3], operands[5],
2785 operands[6], operands[7], operands[8]));
2786 },
2787 (riscv_vector::avl_type) INTVAL (operands[8])))
2788 DONE;
2789 })
2791 (define_insn "*pred_sub<mode>_reverse_scalar"
2792 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2793 (if_then_else:V_VLSI_D
2794 (unspec:<VM>
2795 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2796 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2797 (match_operand 6 "const_int_operand" " i, i, i, i")
2798 (match_operand 7 "const_int_operand" " i, i, i, i")
2799 (match_operand 8 "const_int_operand" " i, i, i, i")
2800 (reg:SI VL_REGNUM)
2801 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2802 (minus:V_VLSI_D
2803 (vec_duplicate:V_VLSI_D
2804 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2805 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2806 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2807 "TARGET_VECTOR"
2808 "vrsub.vx\t%0,%3,%z4%p1"
2809 [(set_attr "type" "vialu")
2810 (set_attr "mode" "<MODE>")])
2812 (define_insn "*pred_sub<mode>_extended_reverse_scalar"
2813 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2814 (if_then_else:V_VLSI_D
2815 (unspec:<VM>
2816 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2817 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2818 (match_operand 6 "const_int_operand" " i, i, i, i")
2819 (match_operand 7 "const_int_operand" " i, i, i, i")
2820 (match_operand 8 "const_int_operand" " i, i, i, i")
2821 (reg:SI VL_REGNUM)
2822 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2823 (minus:V_VLSI_D
2824 (vec_duplicate:V_VLSI_D
2825 (sign_extend:<VEL>
2826 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2827 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2828 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2829 "TARGET_VECTOR"
2830 "vrsub.vx\t%0,%3,%z4%p1"
2831 [(set_attr "type" "vialu")
2832 (set_attr "mode" "<MODE>")])
2834 ;; Multiply High instructions.
2835 (define_insn "@pred_mulh<v_su><mode>"
2836 [(set (match_operand:VFULLI 0 "register_operand" "=vd,vd, vr, vr")
2837 (if_then_else:VFULLI
2838 (unspec:<VM>
2839 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2840 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2841 (match_operand 6 "const_int_operand" " i, i, i, i")
2842 (match_operand 7 "const_int_operand" " i, i, i, i")
2843 (match_operand 8 "const_int_operand" " i, i, i, i")
2844 (reg:SI VL_REGNUM)
2845 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2846 (unspec:VFULLI
2847 [(match_operand:VFULLI 3 "register_operand" "vr,vr, vr, vr")
2848 (match_operand:VFULLI 4 "register_operand" "vr,vr, vr, vr")] VMULH)
2849 (match_operand:VFULLI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2850 "TARGET_VECTOR"
2851 "vmulh<v_su>.vv\t%0,%3,%4%p1"
2852 [(set_attr "type" "vimul")
2853 (set_attr "mode" "<MODE>")])
2855 (define_insn "@pred_mulh<v_su><mode>_scalar"
2856 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2857 (if_then_else:VI_QHS
2858 (unspec:<VM>
2859 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2860 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2861 (match_operand 6 "const_int_operand" " i, i, i, i")
2862 (match_operand 7 "const_int_operand" " i, i, i, i")
2863 (match_operand 8 "const_int_operand" " i, i, i, i")
2864 (reg:SI VL_REGNUM)
2865 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2866 (unspec:VI_QHS
2867 [(vec_duplicate:VI_QHS
2868 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2869 (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2870 (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2871 "TARGET_VECTOR"
2872 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2873 [(set_attr "type" "vimul")
2874 (set_attr "mode" "<MODE>")])
2876 (define_expand "@pred_mulh<v_su><mode>_scalar"
2877 [(set (match_operand:VFULLI_D 0 "register_operand")
2878 (if_then_else:VFULLI_D
2879 (unspec:<VM>
2880 [(match_operand:<VM> 1 "vector_mask_operand")
2881 (match_operand 5 "vector_length_operand")
2882 (match_operand 6 "const_int_operand")
2883 (match_operand 7 "const_int_operand")
2884 (match_operand 8 "const_int_operand")
2885 (reg:SI VL_REGNUM)
2886 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2887 (unspec:VFULLI_D
2888 [(vec_duplicate:VFULLI_D
2889 (match_operand:<VEL> 4 "reg_or_int_operand"))
2890 (match_operand:VFULLI_D 3 "register_operand")] VMULH)
2891 (match_operand:VFULLI_D 2 "vector_merge_operand")))]
2892 "TARGET_VECTOR"
2893 {
2894 if (riscv_vector::sew64_scalar_helper (
2895 operands,
2896 /* scalar op */&operands[4],
2897 /* vl */operands[5],
2898 <MODE>mode,
2899 false,
2900 [] (rtx *operands, rtx boardcast_scalar) {
2901 emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
2902 operands[2], operands[3], boardcast_scalar, operands[5],
2903 operands[6], operands[7], operands[8]));
2904 },
2905 (riscv_vector::avl_type) INTVAL (operands[8])))
2906 DONE;
2907 })
2909 (define_insn "*pred_mulh<v_su><mode>_scalar"
2910 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
2911 (if_then_else:VFULLI_D
2912 (unspec:<VM>
2913 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2914 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2915 (match_operand 6 "const_int_operand" " i, i, i, i")
2916 (match_operand 7 "const_int_operand" " i, i, i, i")
2917 (match_operand 8 "const_int_operand" " i, i, i, i")
2918 (reg:SI VL_REGNUM)
2919 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2920 (unspec:VFULLI_D
2921 [(vec_duplicate:VFULLI_D
2922 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2923 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2924 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2925 "TARGET_VECTOR"
2926 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2927 [(set_attr "type" "vimul")
2928 (set_attr "mode" "<MODE>")])
2930 (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
2931 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
2932 (if_then_else:VFULLI_D
2933 (unspec:<VM>
2934 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2935 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2936 (match_operand 6 "const_int_operand" " i, i, i, i")
2937 (match_operand 7 "const_int_operand" " i, i, i, i")
2938 (match_operand 8 "const_int_operand" " i, i, i, i")
2939 (reg:SI VL_REGNUM)
2940 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2941 (unspec:VFULLI_D
2942 [(vec_duplicate:VFULLI_D
2943 (sign_extend:<VEL>
2944 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2945 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2946 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2947 "TARGET_VECTOR"
2948 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2949 [(set_attr "type" "vimul")
2950 (set_attr "mode" "<MODE>")])
2952 ;; Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
2953 (define_insn "@pred_adc<mode>"
2954 [(set (match_operand:VI 0 "register_operand" "=vd,vd,vd,vd")
2955 (if_then_else:VI
2956 (unspec:<VM>
2957 [(match_operand 5 "vector_length_operand" "rK,rK,rK,rK")
2958 (match_operand 6 "const_int_operand" " i, i, i, i")
2959 (match_operand 7 "const_int_operand" " i, i, i, i")
2960 (reg:SI VL_REGNUM)
2961 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2962 (unspec:VI
2963 [(plus:VI
2964 (match_operand:VI 2 "register_operand" "vr,vr,vr,vr")
2965 (match_operand:VI 3 "vector_arith_operand" "vr,vr,vi,vi"))
2966 (match_operand:<VM> 4 "register_operand" "vm,vm,vm,vm")] UNSPEC_VADC)
2967 (match_operand:VI 1 "vector_merge_operand" "vu, 0,vu, 0")))]
2968 "TARGET_VECTOR"
2969 "vadc.v%o3m\t%0,%2,%v3,%4"
2970 [(set_attr "type" "vicalu")
2971 (set_attr "mode" "<MODE>")
2972 (set_attr "merge_op_idx" "1")
2973 (set_attr "vl_op_idx" "5")
2974 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
2975 (set (attr "avl_type_idx") (const_int 7))])
2977 (define_insn "@pred_sbc<mode>"
2978 [(set (match_operand:VI 0 "register_operand" "=vd,vd")
2979 (if_then_else:VI
2980 (unspec:<VM>
2981 [(match_operand 5 "vector_length_operand" "rK,rK")
2982 (match_operand 6 "const_int_operand" " i, i")
2983 (match_operand 7 "const_int_operand" " i, i")
2984 (reg:SI VL_REGNUM)
2985 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2986 (unspec:VI
2987 [(minus:VI
2988 (match_operand:VI 2 "register_operand" "vr,vr")
2989 (match_operand:VI 3 "register_operand" "vr,vr"))
2990 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
2991 (match_operand:VI 1 "vector_merge_operand" "vu, 0")))]
2992 "TARGET_VECTOR"
2993 "vsbc.vvm\t%0,%2,%3,%4"
2994 [(set_attr "type" "vicalu")
2995 (set_attr "mode" "<MODE>")
2996 (set_attr "merge_op_idx" "1")
2997 (set_attr "vl_op_idx" "5")
2998 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
2999 (set (attr "avl_type_idx") (const_int 7))])
3001 (define_insn "@pred_adc<mode>_scalar"
3002 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3003 (if_then_else:VI_QHS
3004 (unspec:<VM>
3005 [(match_operand 5 "vector_length_operand" "rK,rK")
3006 (match_operand 6 "const_int_operand" " i, i")
3007 (match_operand 7 "const_int_operand" " i, i")
3008 (reg:SI VL_REGNUM)
3009 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3010 (unspec:VI_QHS
3011 [(plus:VI_QHS
3012 (vec_duplicate:VI_QHS
3013 (match_operand:<VEL> 3 "register_operand" " r, r"))
3014 (match_operand:VI_QHS 2 "register_operand" "vr,vr"))
3015 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3016 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3017 "TARGET_VECTOR"
3018 "vadc.vxm\t%0,%2,%3,%4"
3019 [(set_attr "type" "vicalu")
3020 (set_attr "mode" "<MODE>")
3021 (set_attr "merge_op_idx" "1")
3022 (set_attr "vl_op_idx" "5")
3023 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3024 (set (attr "avl_type_idx") (const_int 7))])
3026 (define_insn "@pred_sbc<mode>_scalar"
3027 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3028 (if_then_else:VI_QHS
3029 (unspec:<VM>
3030 [(match_operand 5 "vector_length_operand" "rK,rK")
3031 (match_operand 6 "const_int_operand" " i, i")
3032 (match_operand 7 "const_int_operand" " i, i")
3033 (reg:SI VL_REGNUM)
3034 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3035 (unspec:VI_QHS
3036 [(minus:VI_QHS
3037 (match_operand:VI_QHS 2 "register_operand" "vr,vr")
3038 (vec_duplicate:VI_QHS
3039 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3040 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3041 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3042 "TARGET_VECTOR"
3043 "vsbc.vxm\t%0,%2,%z3,%4"
3044 [(set_attr "type" "vicalu")
3045 (set_attr "mode" "<MODE>")
3046 (set_attr "merge_op_idx" "1")
3047 (set_attr "vl_op_idx" "5")
3048 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3049 (set (attr "avl_type_idx") (const_int 7))])
3051 (define_expand "@pred_adc<mode>_scalar"
3052 [(set (match_operand:VI_D 0 "register_operand")
3053 (if_then_else:VI_D
3054 (unspec:<VM>
3055 [(match_operand 5 "vector_length_operand")
3056 (match_operand 6 "const_int_operand")
3057 (match_operand 7 "const_int_operand")
3058 (reg:SI VL_REGNUM)
3059 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3060 (unspec:VI_D
3061 [(plus:VI_D
3062 (vec_duplicate:VI_D
3063 (match_operand:<VEL> 3 "reg_or_int_operand"))
3064 (match_operand:VI_D 2 "register_operand"))
3065 (match_operand:<VM> 4 "register_operand")] UNSPEC_VADC)
3066 (match_operand:VI_D 1 "vector_merge_operand")))]
3067 "TARGET_VECTOR"
3068 {
3069 if (riscv_vector::sew64_scalar_helper (
3070 operands,
3071 /* scalar op */&operands[3],
3072 /* vl */operands[5],
3073 <MODE>mode,
3074 riscv_vector::simm5_p (operands[3]),
3075 [] (rtx *operands, rtx boardcast_scalar) {
3076 emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
3077 operands[2], boardcast_scalar, operands[4], operands[5],
3078 operands[6], operands[7]));
3079 },
3080 (riscv_vector::avl_type) INTVAL (operands[7])))
3081 DONE;
3082 })
3084 (define_insn "*pred_adc<mode>_scalar"
3085 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3086 (if_then_else:VI_D
3087 (unspec:<VM>
3088 [(match_operand 5 "vector_length_operand" "rK,rK")
3089 (match_operand 6 "const_int_operand" " i, i")
3090 (match_operand 7 "const_int_operand" " i, i")
3091 (reg:SI VL_REGNUM)
3092 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3093 (unspec:VI_D
3094 [(plus:VI_D
3095 (vec_duplicate:VI_D
3096 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ"))
3097 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3098 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3099 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3100 "TARGET_VECTOR"
3101 "vadc.vxm\t%0,%2,%z3,%4"
3102 [(set_attr "type" "vicalu")
3103 (set_attr "mode" "<MODE>")
3104 (set_attr "merge_op_idx" "1")
3105 (set_attr "vl_op_idx" "5")
3106 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3107 (set (attr "avl_type_idx") (const_int 7))])
3109 (define_insn "*pred_adc<mode>_extended_scalar"
3110 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3111 (if_then_else:VI_D
3112 (unspec:<VM>
3113 [(match_operand 5 "vector_length_operand" "rK,rK")
3114 (match_operand 6 "const_int_operand" " i, i")
3115 (match_operand 7 "const_int_operand" " i, i")
3116 (reg:SI VL_REGNUM)
3117 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3118 (unspec:VI_D
3119 [(plus:VI_D
3120 (vec_duplicate:VI_D
3121 (sign_extend:<VEL>
3122 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ")))
3123 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3124 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3125 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3126 "TARGET_VECTOR"
3127 "vadc.vxm\t%0,%2,%z3,%4"
3128 [(set_attr "type" "vicalu")
3129 (set_attr "mode" "<MODE>")
3130 (set_attr "merge_op_idx" "1")
3131 (set_attr "vl_op_idx" "5")
3132 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3133 (set (attr "avl_type_idx") (const_int 7))])
3135 (define_expand "@pred_sbc<mode>_scalar"
3136 [(set (match_operand:VI_D 0 "register_operand")
3137 (if_then_else:VI_D
3138 (unspec:<VM>
3139 [(match_operand 5 "vector_length_operand")
3140 (match_operand 6 "const_int_operand")
3141 (match_operand 7 "const_int_operand")
3142 (reg:SI VL_REGNUM)
3143 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3144 (unspec:VI_D
3145 [(minus:VI_D
3146 (match_operand:VI_D 2 "register_operand")
3147 (vec_duplicate:VI_D
3148 (match_operand:<VEL> 3 "reg_or_int_operand")))
3149 (match_operand:<VM> 4 "register_operand")] UNSPEC_VSBC)
3150 (match_operand:VI_D 1 "vector_merge_operand")))]
3151 "TARGET_VECTOR"
3152 {
3153 if (riscv_vector::sew64_scalar_helper (
3154 operands,
3155 /* scalar op */&operands[3],
3156 /* vl */operands[5],
3157 <MODE>mode,
3158 false,
3159 [] (rtx *operands, rtx boardcast_scalar) {
3160 emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
3161 operands[2], boardcast_scalar, operands[4], operands[5],
3162 operands[6], operands[7]));
3163 },
3164 (riscv_vector::avl_type) INTVAL (operands[7])))
3165 DONE;
3166 })
3168 (define_insn "*pred_sbc<mode>_scalar"
3169 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3170 (if_then_else:VI_D
3171 (unspec:<VM>
3172 [(match_operand 5 "vector_length_operand" "rK,rK")
3173 (match_operand 6 "const_int_operand" " i, i")
3174 (match_operand 7 "const_int_operand" " i, i")
3175 (reg:SI VL_REGNUM)
3176 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3177 (unspec:VI_D
3178 [(minus:VI_D
3179 (match_operand:VI_D 2 "register_operand" "vr,vr")
3180 (vec_duplicate:VI_D
3181 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3182 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3183 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3184 "TARGET_VECTOR"
3185 "vsbc.vxm\t%0,%2,%z3,%4"
3186 [(set_attr "type" "vicalu")
3187 (set_attr "mode" "<MODE>")
3188 (set_attr "merge_op_idx" "1")
3189 (set_attr "vl_op_idx" "5")
3190 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3191 (set (attr "avl_type_idx") (const_int 7))])
3193 (define_insn "*pred_sbc<mode>_extended_scalar"
3194 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3195 (if_then_else:VI_D
3196 (unspec:<VM>
3197 [(match_operand 5 "vector_length_operand" "rK,rK")
3198 (match_operand 6 "const_int_operand" " i, i")
3199 (match_operand 7 "const_int_operand" " i, i")
3200 (reg:SI VL_REGNUM)
3201 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3202 (unspec:VI_D
3203 [(minus:VI_D
3204 (match_operand:VI_D 2 "register_operand" "vr,vr")
3205 (vec_duplicate:VI_D
3206 (sign_extend:<VEL>
3207 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ"))))
3208 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3209 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3210 "TARGET_VECTOR"
3211 "vsbc.vxm\t%0,%2,%z3,%4"
3212 [(set_attr "type" "vicalu")
3213 (set_attr "mode" "<MODE>")
3214 (set_attr "merge_op_idx" "1")
3215 (set_attr "vl_op_idx" "5")
3216 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3217 (set (attr "avl_type_idx") (const_int 7))])
3219 (define_insn "@pred_madc<mode>"
3220 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3221 (unspec:<VM>
3222 [(plus:VI
3223 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3224 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3225 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3226 (unspec:<VM>
3227 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3228 (match_operand 5 "const_int_operand" " i, i, i")
3229 (reg:SI VL_REGNUM)
3230 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3231 "TARGET_VECTOR"
3232 "vmadc.v%o2m\t%0,%1,%v2,%3"
3233 [(set_attr "type" "vicalu")
3234 (set_attr "mode" "<MODE>")
3235 (set_attr "vl_op_idx" "4")
3236 (set (attr "avl_type_idx") (const_int 5))])
3238 (define_insn "@pred_msbc<mode>"
3239 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
3240 (unspec:<VM>
3241 [(minus:VI
3242 (match_operand:VI 1 "register_operand" " 0, vr, vr")
3243 (match_operand:VI 2 "register_operand" " vr, 0, vr"))
3244 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3245 (unspec:<VM>
3246 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3247 (match_operand 5 "const_int_operand" " i, i, i")
3248 (reg:SI VL_REGNUM)
3249 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3250 "TARGET_VECTOR"
3251 "vmsbc.vvm\t%0,%1,%2,%3"
3252 [(set_attr "type" "vicalu")
3253 (set_attr "mode" "<MODE>")
3254 (set_attr "vl_op_idx" "4")
3255 (set (attr "avl_type_idx") (const_int 5))])
3257 (define_insn "@pred_madc<mode>_scalar"
3258 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3259 (unspec:<VM>
3260 [(plus:VI_QHS
3261 (vec_duplicate:VI_QHS
3262 (match_operand:<VEL> 2 "register_operand" " r, r"))
3263 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3264 (match_operand:<VM> 3 "register_operand" " vm, vm")
3265 (unspec:<VM>
3266 [(match_operand 4 "vector_length_operand" " rK, rK")
3267 (match_operand 5 "const_int_operand" " i, i")
3268 (reg:SI VL_REGNUM)
3269 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3270 "TARGET_VECTOR"
3271 "vmadc.vxm\t%0,%1,%2,%3"
3272 [(set_attr "type" "vicalu")
3273 (set_attr "mode" "<MODE>")
3274 (set_attr "vl_op_idx" "4")
3275 (set (attr "avl_type_idx") (const_int 5))])
3277 (define_insn "@pred_msbc<mode>_scalar"
3278 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3279 (unspec:<VM>
3280 [(minus:VI_QHS
3281 (vec_duplicate:VI_QHS
3282 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3283 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3284 (match_operand:<VM> 3 "register_operand" " vm, vm")
3285 (unspec:<VM>
3286 [(match_operand 4 "vector_length_operand" " rK, rK")
3287 (match_operand 5 "const_int_operand" " i, i")
3288 (reg:SI VL_REGNUM)
3289 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3290 "TARGET_VECTOR"
3291 "vmsbc.vxm\t%0,%1,%z2,%3"
3292 [(set_attr "type" "vicalu")
3293 (set_attr "mode" "<MODE>")
3294 (set_attr "vl_op_idx" "4")
3295 (set (attr "avl_type_idx") (const_int 5))])
3297 (define_expand "@pred_madc<mode>_scalar"
3298 [(set (match_operand:<VM> 0 "register_operand")
3299 (unspec:<VM>
3300 [(plus:VI_D
3301 (vec_duplicate:VI_D
3302 (match_operand:<VEL> 2 "reg_or_int_operand"))
3303 (match_operand:VI_D 1 "register_operand"))
3304 (match_operand:<VM> 3 "register_operand")
3305 (unspec:<VM>
3306 [(match_operand 4 "vector_length_operand")
3307 (match_operand 5 "const_int_operand")
3308 (reg:SI VL_REGNUM)
3309 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3310 "TARGET_VECTOR"
3311 {
3312 if (riscv_vector::sew64_scalar_helper (
3313 operands,
3314 /* scalar op */&operands[2],
3315 /* vl */operands[4],
3316 <MODE>mode,
3317 riscv_vector::simm5_p (operands[2]),
3318 [] (rtx *operands, rtx boardcast_scalar) {
3319 emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
3320 boardcast_scalar, operands[3], operands[4], operands[5]));
3321 },
3322 (riscv_vector::avl_type) INTVAL (operands[5])))
3323 DONE;
3324 })
3326 (define_insn "*pred_madc<mode>_scalar"
3327 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3328 (unspec:<VM>
3329 [(plus:VI_D
3330 (vec_duplicate:VI_D
3331 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3332 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3333 (match_operand:<VM> 3 "register_operand" " vm, vm")
3334 (unspec:<VM>
3335 [(match_operand 4 "vector_length_operand" " rK, rK")
3336 (match_operand 5 "const_int_operand" " i, i")
3337 (reg:SI VL_REGNUM)
3338 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3339 "TARGET_VECTOR"
3340 "vmadc.vxm\t%0,%1,%z2,%3"
3341 [(set_attr "type" "vicalu")
3342 (set_attr "mode" "<MODE>")
3343 (set_attr "vl_op_idx" "4")
3344 (set (attr "avl_type_idx") (const_int 5))])
3346 (define_insn "*pred_madc<mode>_extended_scalar"
3347 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3348 (unspec:<VM>
3349 [(plus:VI_D
3350 (vec_duplicate:VI_D
3351 (sign_extend:<VEL>
3352 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3353 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3354 (match_operand:<VM> 3 "register_operand" " vm, vm")
3355 (unspec:<VM>
3356 [(match_operand 4 "vector_length_operand" " rK, rK")
3357 (match_operand 5 "const_int_operand" " i, i")
3358 (reg:SI VL_REGNUM)
3359 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3360 "TARGET_VECTOR"
3361 "vmadc.vxm\t%0,%1,%z2,%3"
3362 [(set_attr "type" "vicalu")
3363 (set_attr "mode" "<MODE>")
3364 (set_attr "vl_op_idx" "4")
3365 (set (attr "avl_type_idx") (const_int 5))])
3367 (define_expand "@pred_msbc<mode>_scalar"
3368 [(set (match_operand:<VM> 0 "register_operand")
3369 (unspec:<VM>
3370 [(minus:VI_D
3371 (vec_duplicate:VI_D
3372 (match_operand:<VEL> 2 "reg_or_int_operand"))
3373 (match_operand:VI_D 1 "register_operand"))
3374 (match_operand:<VM> 3 "register_operand")
3375 (unspec:<VM>
3376 [(match_operand 4 "vector_length_operand")
3377 (match_operand 5 "const_int_operand")
3378 (reg:SI VL_REGNUM)
3379 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3380 "TARGET_VECTOR"
3381 {
3382 if (riscv_vector::sew64_scalar_helper (
3383 operands,
3384 /* scalar op */&operands[2],
3385 /* vl */operands[4],
3386 <MODE>mode,
3387 false,
3388 [] (rtx *operands, rtx boardcast_scalar) {
3389 emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
3390 boardcast_scalar, operands[3], operands[4], operands[5]));
3391 },
3392 (riscv_vector::avl_type) INTVAL (operands[5])))
3393 DONE;
3394 })
3396 (define_insn "*pred_msbc<mode>_scalar"
3397 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3398 (unspec:<VM>
3399 [(minus:VI_D
3400 (vec_duplicate:VI_D
3401 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3402 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3403 (match_operand:<VM> 3 "register_operand" " vm, vm")
3404 (unspec:<VM>
3405 [(match_operand 4 "vector_length_operand" " rK, rK")
3406 (match_operand 5 "const_int_operand" " i, i")
3407 (reg:SI VL_REGNUM)
3408 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3409 "TARGET_VECTOR"
3410 "vmsbc.vxm\t%0,%1,%z2,%3"
3411 [(set_attr "type" "vicalu")
3412 (set_attr "mode" "<MODE>")
3413 (set_attr "vl_op_idx" "4")
3414 (set (attr "avl_type_idx") (const_int 5))])
3416 (define_insn "*pred_msbc<mode>_extended_scalar"
3417 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3418 (unspec:<VM>
3419 [(minus:VI_D
3420 (vec_duplicate:VI_D
3421 (sign_extend:<VEL>
3422 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3423 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3424 (match_operand:<VM> 3 "register_operand" " vm, vm")
3425 (unspec:<VM>
3426 [(match_operand 4 "vector_length_operand" " rK, rK")
3427 (match_operand 5 "const_int_operand" " i, i")
3428 (reg:SI VL_REGNUM)
3429 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3430 "TARGET_VECTOR"
3431 "vmsbc.vxm\t%0,%1,%z2,%3"
3432 [(set_attr "type" "vicalu")
3433 (set_attr "mode" "<MODE>")
3434 (set_attr "vl_op_idx" "4")
3435 (set (attr "avl_type_idx") (const_int 5))])
3437 (define_insn "@pred_madc<mode>_overflow"
3438 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3439 (unspec:<VM>
3440 [(plus:VI
3441 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3442 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3443 (unspec:<VM>
3444 [(match_operand 3 "vector_length_operand" " rK, rK, rK")
3445 (match_operand 4 "const_int_operand" " i, i, i")
3446 (reg:SI VL_REGNUM)
3447 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3448 "TARGET_VECTOR"
3449 "vmadc.v%o2\t%0,%1,%v2"
3450 [(set_attr "type" "vicalu")
3451 (set_attr "mode" "<MODE>")
3452 (set_attr "vl_op_idx" "3")
3453 (set (attr "avl_type_idx") (const_int 4))])
3455 (define_insn "@pred_msbc<mode>_overflow"
3456 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
3457 (unspec:<VM>
3458 [(minus:VI
3459 (match_operand:VI 1 "register_operand" " 0, vr, vr, vr")
3460 (match_operand:VI 2 "register_operand" " vr, 0, vr, vi"))
3461 (unspec:<VM>
3462 [(match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
3463 (match_operand 4 "const_int_operand" " i, i, i, i")
3464 (reg:SI VL_REGNUM)
3465 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3466 "TARGET_VECTOR"
3467 "vmsbc.vv\t%0,%1,%2"
3468 [(set_attr "type" "vicalu")
3469 (set_attr "mode" "<MODE>")
3470 (set_attr "vl_op_idx" "3")
3471 (set (attr "avl_type_idx") (const_int 4))])
3473 (define_insn "@pred_madc<mode>_overflow_scalar"
3474 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3475 (unspec:<VM>
3476 [(plus:VI_QHS
3477 (vec_duplicate:VI_QHS
3478 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3479 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3480 (unspec:<VM>
3481 [(match_operand 3 "vector_length_operand" " rK, rK")
3482 (match_operand 4 "const_int_operand" " i, i")
3483 (reg:SI VL_REGNUM)
3484 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3485 "TARGET_VECTOR"
3486 "vmadc.vx\t%0,%1,%z2"
3487 [(set_attr "type" "vicalu")
3488 (set_attr "mode" "<MODE>")
3489 (set_attr "vl_op_idx" "3")
3490 (set (attr "avl_type_idx") (const_int 4))])
3492 (define_insn "@pred_msbc<mode>_overflow_scalar"
3493 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3494 (unspec:<VM>
3495 [(minus:VI_QHS
3496 (vec_duplicate:VI_QHS
3497 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3498 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3499 (unspec:<VM>
3500 [(match_operand 3 "vector_length_operand" " rK, rK")
3501 (match_operand 4 "const_int_operand" " i, i")
3502 (reg:SI VL_REGNUM)
3503 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3504 "TARGET_VECTOR"
3505 "vmsbc.vx\t%0,%1,%z2"
3506 [(set_attr "type" "vicalu")
3507 (set_attr "mode" "<MODE>")
3508 (set_attr "vl_op_idx" "3")
3509 (set (attr "avl_type_idx") (const_int 4))])
3511 (define_expand "@pred_madc<mode>_overflow_scalar"
3512 [(set (match_operand:<VM> 0 "register_operand")
3513 (unspec:<VM>
3514 [(plus:VI_D
3515 (vec_duplicate:VI_D
3516 (match_operand:<VEL> 2 "reg_or_int_operand"))
3517 (match_operand:VI_D 1 "register_operand"))
3518 (unspec:<VM>
3519 [(match_operand 3 "vector_length_operand")
3520 (match_operand 4 "const_int_operand")
3521 (reg:SI VL_REGNUM)
3522 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3523 "TARGET_VECTOR"
3524 {
3525 if (riscv_vector::sew64_scalar_helper (
3526 operands,
3527 /* scalar op */&operands[2],
3528 /* vl */operands[3],
3529 <MODE>mode,
3530 riscv_vector::simm5_p (operands[2]),
3531 [] (rtx *operands, rtx boardcast_scalar) {
3532 emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
3533 boardcast_scalar, operands[3], operands[4]));
3534 },
3535 (riscv_vector::avl_type) INTVAL (operands[4])))
3536 DONE;
3537 })
3539 (define_insn "*pred_madc<mode>_overflow_scalar"
3540 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3541 (unspec:<VM>
3542 [(plus:VI_D
3543 (vec_duplicate:VI_D
3544 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3545 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3546 (unspec:<VM>
3547 [(match_operand 3 "vector_length_operand" " rK, rK")
3548 (match_operand 4 "const_int_operand" " i, i")
3549 (reg:SI VL_REGNUM)
3550 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3551 "TARGET_VECTOR"
3552 "vmadc.vx\t%0,%1,%z2"
3553 [(set_attr "type" "vicalu")
3554 (set_attr "mode" "<MODE>")
3555 (set_attr "vl_op_idx" "3")
3556 (set (attr "avl_type_idx") (const_int 4))])
3558 (define_insn "*pred_madc<mode>_overflow_extended_scalar"
3559 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3560 (unspec:<VM>
3561 [(plus:VI_D
3562 (vec_duplicate:VI_D
3563 (sign_extend:<VEL>
3564 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3565 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3566 (unspec:<VM>
3567 [(match_operand 3 "vector_length_operand" " rK, rK")
3568 (match_operand 4 "const_int_operand" " i, i")
3569 (reg:SI VL_REGNUM)
3570 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3571 "TARGET_VECTOR"
3572 "vmadc.vx\t%0,%1,%z2"
3573 [(set_attr "type" "vicalu")
3574 (set_attr "mode" "<MODE>")
3575 (set_attr "vl_op_idx" "3")
3576 (set (attr "avl_type_idx") (const_int 4))])
3578 (define_expand "@pred_msbc<mode>_overflow_scalar"
3579 [(set (match_operand:<VM> 0 "register_operand")
3580 (unspec:<VM>
3581 [(minus:VI_D
3582 (vec_duplicate:VI_D
3583 (match_operand:<VEL> 2 "reg_or_int_operand"))
3584 (match_operand:VI_D 1 "register_operand"))
3585 (unspec:<VM>
3586 [(match_operand 3 "vector_length_operand")
3587 (match_operand 4 "const_int_operand")
3588 (reg:SI VL_REGNUM)
3589 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3590 "TARGET_VECTOR"
3591 {
3592 if (riscv_vector::sew64_scalar_helper (
3593 operands,
3594 /* scalar op */&operands[2],
3595 /* vl */operands[3],
3596 <MODE>mode,
3597 false,
3598 [] (rtx *operands, rtx boardcast_scalar) {
3599 emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
3600 boardcast_scalar, operands[3], operands[4]));
3601 },
3602 (riscv_vector::avl_type) INTVAL (operands[4])))
3603 DONE;
3604 })
3606 (define_insn "*pred_msbc<mode>_overflow_scalar"
3607 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3608 (unspec:<VM>
3609 [(minus:VI_D
3610 (vec_duplicate:VI_D
3611 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3612 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3613 (unspec:<VM>
3614 [(match_operand 3 "vector_length_operand" " rK, rK")
3615 (match_operand 4 "const_int_operand" " i, i")
3616 (reg:SI VL_REGNUM)
3617 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3618 "TARGET_VECTOR"
3619 "vmsbc.vx\t%0,%1,%z2"
3620 [(set_attr "type" "vicalu")
3621 (set_attr "mode" "<MODE>")
3622 (set_attr "vl_op_idx" "3")
3623 (set (attr "avl_type_idx") (const_int 4))])
3625 (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
3626 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3627 (unspec:<VM>
3628 [(minus:VI_D
3629 (vec_duplicate:VI_D
3630 (sign_extend:<VEL>
3631 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3632 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3633 (unspec:<VM>
3634 [(match_operand 3 "vector_length_operand" " rK, rK")
3635 (match_operand 4 "const_int_operand" " i, i")
3636 (reg:SI VL_REGNUM)
3637 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3638 "TARGET_VECTOR"
3639 "vmsbc.vx\t%0,%1,%z2"
3640 [(set_attr "type" "vicalu")
3641 (set_attr "mode" "<MODE>")
3642 (set_attr "vl_op_idx" "3")
3643 (set (attr "avl_type_idx") (const_int 4))])
3645 ;; -------------------------------------------------------------------------------
3646 ;; ---- Predicated integer unary operations
3647 ;; -------------------------------------------------------------------------------
3648 ;; Includes:
3649 ;; - vneg.v/vnot.v
3650 ;; -------------------------------------------------------------------------------
3652 (define_insn "@pred_<optab><mode>"
3653 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
3654 (if_then_else:V_VLSI
3655 (unspec:<VM>
3656 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3657 (match_operand 4 "vector_length_operand" "rK,rK, rK, rK")
3658 (match_operand 5 "const_int_operand" " i, i, i, i")
3659 (match_operand 6 "const_int_operand" " i, i, i, i")
3660 (match_operand 7 "const_int_operand" " i, i, i, i")
3661 (reg:SI VL_REGNUM)
3662 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3663 (any_int_unop:V_VLSI
3664 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr"))
3665 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3666 "TARGET_VECTOR"
3667 "v<insn>.v\t%0,%3%p1"
3668 [(set_attr "type" "vialu")
3669 (set_attr "mode" "<MODE>")
3670 (set_attr "vl_op_idx" "4")
3671 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3672 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3673 (set (attr "avl_type_idx") (const_int 7))])
3675 ;; -------------------------------------------------------------------------------
3676 ;; ---- Predicated integer widening binary operations
3677 ;; -------------------------------------------------------------------------------
3678 ;; Includes:
3679 ;; - 11.2 Vector Widening Integer Add/Subtract
3680 ;; - 11.3 Vector Integer Extension
3681 ;; - 11.12 Vector Widening Integer Multiply Instructions
3682 ;; -------------------------------------------------------------------------------
3684 ;; Vector Double-Widening Sign-extend and Zero-extend.
3685 (define_insn "@pred_<optab><mode>_vf2"
3686 [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
3687 (if_then_else:VWEXTI
3688 (unspec:<VM>
3689 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
3690 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
3691 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
3692 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
3693 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
3694 (reg:SI VL_REGNUM)
3695 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3696 (any_extend:VWEXTI
3697 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
3698 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
3699 "TARGET_VECTOR"
3700 "v<sz>ext.vf2\t%0,%3%p1"
3701 [(set_attr "type" "vext")
3702 (set_attr "mode" "<MODE>")
3703 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
3705 ;; Vector Quad-Widening Sign-extend and Zero-extend.
3706 (define_insn "@pred_<optab><mode>_vf4"
3707 [(set (match_operand:VQEXTI 0 "register_operand" "=&vr,&vr")
3708 (if_then_else:VQEXTI
3709 (unspec:<VM>
3710 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3711 (match_operand 4 "vector_length_operand" " rK, rK")
3712 (match_operand 5 "const_int_operand" " i, i")
3713 (match_operand 6 "const_int_operand" " i, i")
3714 (match_operand 7 "const_int_operand" " i, i")
3715 (reg:SI VL_REGNUM)
3716 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3717 (any_extend:VQEXTI
3718 (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " vr, vr"))
3719 (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0")))]
3720 "TARGET_VECTOR"
3721 "v<sz>ext.vf4\t%0,%3%p1"
3722 [(set_attr "type" "vext")
3723 (set_attr "mode" "<MODE>")])
3725 ;; Vector Oct-Widening Sign-extend and Zero-extend.
3726 (define_insn "@pred_<optab><mode>_vf8"
3727 [(set (match_operand:VOEXTI 0 "register_operand" "=&vr,&vr")
3728 (if_then_else:VOEXTI
3729 (unspec:<VM>
3730 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3731 (match_operand 4 "vector_length_operand" " rK, rK")
3732 (match_operand 5 "const_int_operand" " i, i")
3733 (match_operand 6 "const_int_operand" " i, i")
3734 (match_operand 7 "const_int_operand" " i, i")
3735 (reg:SI VL_REGNUM)
3736 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3737 (any_extend:VOEXTI
3738 (match_operand:<V_OCT_TRUNC> 3 "register_operand" " vr, vr"))
3739 (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0")))]
3740 "TARGET_VECTOR"
3741 "v<sz>ext.vf8\t%0,%3%p1"
3742 [(set_attr "type" "vext")
3743 (set_attr "mode" "<MODE>")])
3745 ;; Vector Widening Add/Subtract/Multiply.
3746 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
3747 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3748 (if_then_else:VWEXTI
3749 (unspec:<VM>
3750 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3751 (match_operand 5 "vector_length_operand" " rK, rK")
3752 (match_operand 6 "const_int_operand" " i, i")
3753 (match_operand 7 "const_int_operand" " i, i")
3754 (match_operand 8 "const_int_operand" " i, i")
3755 (reg:SI VL_REGNUM)
3756 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3757 (any_widen_binop:VWEXTI
3758 (any_extend:VWEXTI
3759 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3760 (any_extend:VWEXTI
3761 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3762 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3763 "TARGET_VECTOR"
3764 "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
3765 [(set_attr "type" "vi<widen_binop_insn_type>")
3766 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3768 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
3769 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3770 (if_then_else:VWEXTI
3771 (unspec:<VM>
3772 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3773 (match_operand 5 "vector_length_operand" " rK, rK")
3774 (match_operand 6 "const_int_operand" " i, i")
3775 (match_operand 7 "const_int_operand" " i, i")
3776 (match_operand 8 "const_int_operand" " i, i")
3777 (reg:SI VL_REGNUM)
3778 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3779 (any_widen_binop:VWEXTI
3780 (any_extend:VWEXTI
3781 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3782 (any_extend:VWEXTI
3783 (vec_duplicate:<V_DOUBLE_TRUNC>
3784 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3785 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3786 "TARGET_VECTOR"
3787 "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
3788 [(set_attr "type" "vi<widen_binop_insn_type>")
3789 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3791 (define_insn "@pred_single_widen_sub<any_extend:su><mode>"
3792 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3793 (if_then_else:VWEXTI
3794 (unspec:<VM>
3795 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3796 (match_operand 5 "vector_length_operand" " rK, rK")
3797 (match_operand 6 "const_int_operand" " i, i")
3798 (match_operand 7 "const_int_operand" " i, i")
3799 (match_operand 8 "const_int_operand" " i, i")
3800 (reg:SI VL_REGNUM)
3801 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3802 (minus:VWEXTI
3803 (match_operand:VWEXTI 3 "register_operand" " vr, vr")
3804 (any_extend:VWEXTI
3805 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3806 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3807 "TARGET_VECTOR"
3808 "vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
3809 [(set_attr "type" "viwalu")
3810 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3812 (define_insn "@pred_single_widen_add<any_extend:su><mode>"
3813 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3814 (if_then_else:VWEXTI
3815 (unspec:<VM>
3816 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3817 (match_operand 5 "vector_length_operand" " rK, rK")
3818 (match_operand 6 "const_int_operand" " i, i")
3819 (match_operand 7 "const_int_operand" " i, i")
3820 (match_operand 8 "const_int_operand" " i, i")
3821 (reg:SI VL_REGNUM)
3822 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3823 (plus:VWEXTI
3824 (any_extend:VWEXTI
3825 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
3826 (match_operand:VWEXTI 3 "register_operand" " vr, vr"))
3827 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3828 "TARGET_VECTOR"
3829 "vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
3830 [(set_attr "type" "viwalu")
3831 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3833 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
3834 [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
3835 (if_then_else:VWEXTI
3836 (unspec:<VM>
3837 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3838 (match_operand 5 "vector_length_operand" " rK, rK")
3839 (match_operand 6 "const_int_operand" " i, i")
3840 (match_operand 7 "const_int_operand" " i, i")
3841 (match_operand 8 "const_int_operand" " i, i")
3842 (reg:SI VL_REGNUM)
3843 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3844 (plus_minus:VWEXTI
3845 (match_operand:VWEXTI 3 "register_operand" " vr, vr")
3846 (any_extend:VWEXTI
3847 (vec_duplicate:<V_DOUBLE_TRUNC>
3848 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3849 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3850 "TARGET_VECTOR"
3851 "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
3852 [(set_attr "type" "vi<widen_binop_insn_type>")
3853 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3855 (define_insn "@pred_widen_mulsu<mode>"
3856 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3857 (if_then_else:VWEXTI
3858 (unspec:<VM>
3859 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3860 (match_operand 5 "vector_length_operand" " rK, rK")
3861 (match_operand 6 "const_int_operand" " i, i")
3862 (match_operand 7 "const_int_operand" " i, i")
3863 (match_operand 8 "const_int_operand" " i, i")
3864 (reg:SI VL_REGNUM)
3865 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3866 (mult:VWEXTI
3867 (sign_extend:VWEXTI
3868 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3869 (zero_extend:VWEXTI
3870 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3871 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3872 "TARGET_VECTOR"
3873 "vwmulsu.vv\t%0,%3,%4%p1"
3874 [(set_attr "type" "viwmul")
3875 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3877 (define_insn "@pred_widen_mulsu<mode>_scalar"
3878 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3879 (if_then_else:VWEXTI
3880 (unspec:<VM>
3881 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3882 (match_operand 5 "vector_length_operand" " rK, rK")
3883 (match_operand 6 "const_int_operand" " i, i")
3884 (match_operand 7 "const_int_operand" " i, i")
3885 (match_operand 8 "const_int_operand" " i, i")
3886 (reg:SI VL_REGNUM)
3887 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3888 (mult:VWEXTI
3889 (sign_extend:VWEXTI
3890 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3891 (zero_extend:VWEXTI
3892 (vec_duplicate:<V_DOUBLE_TRUNC>
3893 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3894 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3895 "TARGET_VECTOR"
3896 "vwmulsu.vx\t%0,%3,%z4%p1"
3897 [(set_attr "type" "viwmul")
3898 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3900 ;; vwcvt<u>.x.x.v
3901 (define_insn "@pred_<optab><mode>"
3902 [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
3903 (if_then_else:VWEXTI
3904 (unspec:<VM>
3905 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
3906 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
3907 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
3908 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
3909 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
3910 (reg:SI VL_REGNUM)
3911 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3912 (plus:VWEXTI
3913 (any_extend:VWEXTI
3914 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
3915 (vec_duplicate:VWEXTI
3916 (reg:<VEL> X0_REGNUM)))
3917 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
3918 "TARGET_VECTOR"
3919 "vwcvt<u>.x.x.v\t%0,%3%p1"
3920 [(set_attr "type" "viwalu")
3921 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3922 (set_attr "vl_op_idx" "4")
3923 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3924 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3925 (set (attr "avl_type_idx") (const_int 7))
3926 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
3928 ;; -------------------------------------------------------------------------------
3929 ;; ---- Predicated integer Narrowing operations
3930 ;; -------------------------------------------------------------------------------
3931 ;; Includes:
3932 ;; - 11.7 Vector Narrowing Integer Right Shift Instructions
3933 ;; -------------------------------------------------------------------------------
3935 ;; The destination EEW is smaller than the source EEW and the overlap is in the
3936 ;; lowest-numbered part of the source register group
3937 ;; e.g, when LMUL = 1, vnsrl.wi v0,v0,3 is legal but a destination of v1 is not.
3938 (define_insn "@pred_narrow_<optab><mode>"
3939 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
3940 (if_then_else:<V_DOUBLE_TRUNC>
3941 (unspec:<VM>
3942 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
3943 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
3944 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3945 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3946 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3947 (reg:SI VL_REGNUM)
3948 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3949 (truncate:<V_DOUBLE_TRUNC>
3950 (any_shiftrt:VWEXTI
3951 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
3952 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")))
3953 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
3954 "TARGET_VECTOR"
3955 "vn<insn>.w%o4\t%0,%3,%v4%p1"
3956 [(set_attr "type" "vnshift")
3957 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3959 (define_insn "@pred_narrow_<optab><mode>_scalar"
3960 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
3961 (if_then_else:<V_DOUBLE_TRUNC>
3962 (unspec:<VM>
3963 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
3964 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3965 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3966 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3967 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
3968 (reg:SI VL_REGNUM)
3969 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3970 (truncate:<V_DOUBLE_TRUNC>
3971 (any_shiftrt:VWEXTI
3972 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
3973 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")))
3974 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
3975 "TARGET_VECTOR"
3976 "vn<insn>.w%o4\t%0,%3,%4%p1"
3977 [(set_attr "type" "vnshift")
3978 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3980 ;; vncvt.x.x.w
3981 (define_insn "@pred_trunc<mode>"
3982 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
3983 (if_then_else:<V_DOUBLE_TRUNC>
3984 (unspec:<VM>
3985 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
3986 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3987 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
3988 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3989 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3990 (reg:SI VL_REGNUM)
3991 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3992 (truncate:<V_DOUBLE_TRUNC>
3993 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
3994 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
3995 "TARGET_VECTOR"
3996 "vncvt.x.x.w\t%0,%3%p1"
3997 [(set_attr "type" "vnshift")
3998 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3999 (set_attr "vl_op_idx" "4")
4000 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
4001 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4002 (set (attr "avl_type_idx") (const_int 7))])
4004 ;; -------------------------------------------------------------------------------
4005 ;; ---- Predicated fixed-point operations
4006 ;; -------------------------------------------------------------------------------
4007 ;; Includes:
4008 ;; - 12.1 Vector Single-Width Saturating Add and Subtract
4009 ;; - 12.2 Vector Single-Width Aaveraging Add and Subtract
4010 ;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation
4011 ;; - 12.4 Vector Single-Width Scaling Shift Instructions
4012 ;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions
4013 ;; -------------------------------------------------------------------------------
4015 ;; Saturating Add and Subtract
4016 (define_insn "@pred_<optab><mode>"
4017 [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr")
4018 (if_then_else:VI
4019 (unspec:<VM>
4020 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
4021 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4022 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
4023 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4024 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4025 (reg:SI VL_REGNUM)
4026 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4027 (any_sat_int_binop:VI
4028 (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
4029 (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
4030 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4031 "TARGET_VECTOR"
4032 "@
4033 v<insn>.vv\t%0,%3,%4%p1
4034 v<insn>.vv\t%0,%3,%4%p1
4035 v<insn>.vv\t%0,%3,%4%p1
4036 v<insn>.vv\t%0,%3,%4%p1
4037 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4038 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4039 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4040 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
4041 [(set_attr "type" "<int_binop_insn_type>")
4042 (set_attr "mode" "<MODE>")])
4044 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4045 (define_insn "@pred_<optab><mode>_scalar"
4046 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4047 (if_then_else:VI_QHS
4048 (unspec:<VM>
4049 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4050 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4051 (match_operand 6 "const_int_operand" " i, i, i, i")
4052 (match_operand 7 "const_int_operand" " i, i, i, i")
4053 (match_operand 8 "const_int_operand" " i, i, i, i")
4054 (reg:SI VL_REGNUM)
4055 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4056 (sat_int_plus_binop:VI_QHS
4057 (vec_duplicate:VI_QHS
4058 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4059 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr"))
4060 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4061 "TARGET_VECTOR"
4062 "v<insn>.vx\t%0,%3,%4%p1"
4063 [(set_attr "type" "<int_binop_insn_type>")
4064 (set_attr "mode" "<MODE>")])
4066 (define_insn "@pred_<optab><mode>_scalar"
4067 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4068 (if_then_else:VI_QHS
4069 (unspec:<VM>
4070 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4071 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4072 (match_operand 6 "const_int_operand" " i, i, i, i")
4073 (match_operand 7 "const_int_operand" " i, i, i, i")
4074 (match_operand 8 "const_int_operand" " i, i, i, i")
4075 (reg:SI VL_REGNUM)
4076 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4077 (sat_int_minus_binop:VI_QHS
4078 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4079 (vec_duplicate:VI_QHS
4080 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4081 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4082 "TARGET_VECTOR"
4083 "v<insn>.vx\t%0,%3,%4%p1"
4084 [(set_attr "type" "<int_binop_insn_type>")
4085 (set_attr "mode" "<MODE>")])
4087 (define_expand "@pred_<optab><mode>_scalar"
4088 [(set (match_operand:VI_D 0 "register_operand")
4089 (if_then_else:VI_D
4090 (unspec:<VM>
4091 [(match_operand:<VM> 1 "vector_mask_operand")
4092 (match_operand 5 "vector_length_operand")
4093 (match_operand 6 "const_int_operand")
4094 (match_operand 7 "const_int_operand")
4095 (match_operand 8 "const_int_operand")
4096 (reg:SI VL_REGNUM)
4097 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4098 (sat_int_plus_binop:VI_D
4099 (vec_duplicate:VI_D
4100 (match_operand:<VEL> 4 "reg_or_int_operand"))
4101 (match_operand:VI_D 3 "register_operand"))
4102 (match_operand:VI_D 2 "vector_merge_operand")))]
4103 "TARGET_VECTOR"
4104 {
4105 if (riscv_vector::sew64_scalar_helper (
4106 operands,
4107 /* scalar op */&operands[4],
4108 /* vl */operands[5],
4109 <MODE>mode,
4110 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4111 [] (rtx *operands, rtx boardcast_scalar) {
4112 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4113 operands[2], operands[3], boardcast_scalar, operands[5],
4114 operands[6], operands[7], operands[8]));
4115 },
4116 (riscv_vector::avl_type) INTVAL (operands[8])))
4117 DONE;
4118 })
4120 (define_insn "*pred_<optab><mode>_scalar"
4121 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4122 (if_then_else:VI_D
4123 (unspec:<VM>
4124 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4125 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4126 (match_operand 6 "const_int_operand" " i, i, i, i")
4127 (match_operand 7 "const_int_operand" " i, i, i, i")
4128 (match_operand 8 "const_int_operand" " i, i, i, i")
4129 (reg:SI VL_REGNUM)
4130 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4131 (sat_int_plus_binop:VI_D
4132 (vec_duplicate:VI_D
4133 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4134 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4135 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4136 "TARGET_VECTOR"
4137 "v<insn>.vx\t%0,%3,%4%p1"
4138 [(set_attr "type" "<int_binop_insn_type>")
4139 (set_attr "mode" "<MODE>")])
4141 (define_insn "*pred_<optab><mode>_extended_scalar"
4142 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4143 (if_then_else:VI_D
4144 (unspec:<VM>
4145 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4146 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4147 (match_operand 6 "const_int_operand" " i, i, i, i")
4148 (match_operand 7 "const_int_operand" " i, i, i, i")
4149 (match_operand 8 "const_int_operand" " i, i, i, i")
4150 (reg:SI VL_REGNUM)
4151 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4152 (sat_int_plus_binop:VI_D
4153 (vec_duplicate:VI_D
4154 (sign_extend:<VEL>
4155 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r")))
4156 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4157 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4158 "TARGET_VECTOR"
4159 "v<insn>.vx\t%0,%3,%4%p1"
4160 [(set_attr "type" "<int_binop_insn_type>")
4161 (set_attr "mode" "<MODE>")])
4163 (define_expand "@pred_<optab><mode>_scalar"
4164 [(set (match_operand:VI_D 0 "register_operand")
4165 (if_then_else:VI_D
4166 (unspec:<VM>
4167 [(match_operand:<VM> 1 "vector_mask_operand")
4168 (match_operand 5 "vector_length_operand")
4169 (match_operand 6 "const_int_operand")
4170 (match_operand 7 "const_int_operand")
4171 (match_operand 8 "const_int_operand")
4172 (reg:SI VL_REGNUM)
4173 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4174 (sat_int_minus_binop:VI_D
4175 (match_operand:VI_D 3 "register_operand")
4176 (vec_duplicate:VI_D
4177 (match_operand:<VEL> 4 "reg_or_int_operand")))
4178 (match_operand:VI_D 2 "vector_merge_operand")))]
4179 "TARGET_VECTOR"
4180 {
4181 if (riscv_vector::sew64_scalar_helper (
4182 operands,
4183 /* scalar op */&operands[4],
4184 /* vl */operands[5],
4185 <MODE>mode,
4186 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4187 [] (rtx *operands, rtx boardcast_scalar) {
4188 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4189 operands[2], operands[3], boardcast_scalar, operands[5],
4190 operands[6], operands[7], operands[8]));
4191 },
4192 (riscv_vector::avl_type) INTVAL (operands[8])))
4193 DONE;
4194 })
4196 (define_insn "*pred_<optab><mode>_scalar"
4197 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4198 (if_then_else:VI_D
4199 (unspec:<VM>
4200 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4201 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4202 (match_operand 6 "const_int_operand" " i, i, i, i")
4203 (match_operand 7 "const_int_operand" " i, i, i, i")
4204 (match_operand 8 "const_int_operand" " i, i, i, i")
4205 (reg:SI VL_REGNUM)
4206 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4207 (sat_int_minus_binop:VI_D
4208 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4209 (vec_duplicate:VI_D
4210 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4211 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4212 "TARGET_VECTOR"
4213 "v<insn>.vx\t%0,%3,%4%p1"
4214 [(set_attr "type" "<int_binop_insn_type>")
4215 (set_attr "mode" "<MODE>")])
4217 (define_insn "*pred_<optab><mode>_extended_scalar"
4218 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4219 (if_then_else:VI_D
4220 (unspec:<VM>
4221 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4222 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4223 (match_operand 6 "const_int_operand" " i, i, i, i")
4224 (match_operand 7 "const_int_operand" " i, i, i, i")
4225 (match_operand 8 "const_int_operand" " i, i, i, i")
4226 (reg:SI VL_REGNUM)
4227 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4228 (sat_int_minus_binop:VI_D
4229 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4230 (vec_duplicate:VI_D
4231 (sign_extend:<VEL>
4232 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r"))))
4233 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4234 "TARGET_VECTOR"
4235 "v<insn>.vx\t%0,%3,%4%p1"
4236 [(set_attr "type" "<int_binop_insn_type>")
4237 (set_attr "mode" "<MODE>")])
4239 (define_insn "@pred_<sat_op><mode>"
4240 [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr")
4241 (if_then_else:VI
4242 (unspec:<VM>
4243 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4244 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4245 (match_operand 6 "const_int_operand" " i, i, i, i")
4246 (match_operand 7 "const_int_operand" " i, i, i, i")
4247 (match_operand 8 "const_int_operand" " i, i, i, i")
4248 (match_operand 9 "const_int_operand" " i, i, i, i")
4249 (reg:SI VL_REGNUM)
4250 (reg:SI VTYPE_REGNUM)
4251 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4252 (unspec:VI
4253 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4254 (match_operand:VI 4 "register_operand" " vr, vr, vr, vr")] VSAT_OP)
4255 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4256 "TARGET_VECTOR"
4257 "v<sat_op>.vv\t%0,%3,%4%p1"
4258 [(set_attr "type" "<sat_insn_type>")
4259 (set_attr "mode" "<MODE>")])
4261 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4262 (define_insn "@pred_<sat_op><mode>_scalar"
4263 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr, vd, vr")
4264 (if_then_else:VI_QHS
4265 (unspec:<VM>
4266 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4267 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4268 (match_operand 6 "const_int_operand" " i, i, i, i")
4269 (match_operand 7 "const_int_operand" " i, i, i, i")
4270 (match_operand 8 "const_int_operand" " i, i, i, i")
4271 (match_operand 9 "const_int_operand" " i, i, i, i")
4272 (reg:SI VL_REGNUM)
4273 (reg:SI VTYPE_REGNUM)
4274 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4275 (unspec:VI_QHS
4276 [(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4277 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4278 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4279 "TARGET_VECTOR"
4280 "v<sat_op>.vx\t%0,%3,%z4%p1"
4281 [(set_attr "type" "<sat_insn_type>")
4282 (set_attr "mode" "<MODE>")])
4284 (define_insn "@pred_<sat_op><mode>_scalar"
4285 [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
4286 (if_then_else:VI
4287 (unspec:<VM>
4288 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4289 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4290 (match_operand 6 "const_int_operand" " i, i, i, i")
4291 (match_operand 7 "const_int_operand" " i, i, i, i")
4292 (match_operand 8 "const_int_operand" " i, i, i, i")
4293 (match_operand 9 "const_int_operand" " i, i, i, i")
4294 (reg:SI VL_REGNUM)
4295 (reg:SI VTYPE_REGNUM)
4296 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4297 (unspec:VI
4298 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4299 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
4300 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4301 "TARGET_VECTOR"
4302 "v<sat_op>.v%o4\t%0,%3,%4%p1"
4303 [(set_attr "type" "<sat_insn_type>")
4304 (set_attr "mode" "<MODE>")])
4306 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4307 ;; we need to deal with SEW = 64 in RV32 system.
4308 (define_expand "@pred_<sat_op><mode>_scalar"
4309 [(set (match_operand:VI_D 0 "register_operand")
4310 (if_then_else:VI_D
4311 (unspec:<VM>
4312 [(match_operand:<VM> 1 "vector_mask_operand")
4313 (match_operand 5 "vector_length_operand")
4314 (match_operand 6 "const_int_operand")
4315 (match_operand 7 "const_int_operand")
4316 (match_operand 8 "const_int_operand")
4317 (match_operand 9 "const_int_operand")
4318 (reg:SI VL_REGNUM)
4319 (reg:SI VTYPE_REGNUM)
4320 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4321 (unspec:VI_D
4322 [(match_operand:VI_D 3 "register_operand")
4323 (match_operand:<VEL> 4 "reg_or_int_operand")] VSAT_ARITH_OP)
4324 (match_operand:VI_D 2 "vector_merge_operand")))]
4325 "TARGET_VECTOR"
4326 {
4327 if (riscv_vector::sew64_scalar_helper (
4328 operands,
4329 /* scalar op */&operands[4],
4330 /* vl */operands[5],
4331 <MODE>mode,
4332 false,
4333 [] (rtx *operands, rtx boardcast_scalar) {
4334 emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
4335 operands[2], operands[3], boardcast_scalar, operands[5],
4336 operands[6], operands[7], operands[8], operands[9]));
4337 },
4338 (riscv_vector::avl_type) INTVAL (operands[8])))
4339 DONE;
4340 })
4342 (define_insn "*pred_<sat_op><mode>_scalar"
4343 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4344 (if_then_else:VI_D
4345 (unspec:<VM>
4346 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4347 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4348 (match_operand 6 "const_int_operand" " i, i, i, i")
4349 (match_operand 7 "const_int_operand" " i, i, i, i")
4350 (match_operand 8 "const_int_operand" " i, i, i, i")
4351 (match_operand 9 "const_int_operand" " i, i, i, i")
4352 (reg:SI VL_REGNUM)
4353 (reg:SI VTYPE_REGNUM)
4354 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4355 (unspec:VI_D
4356 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4357 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4358 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4359 "TARGET_VECTOR"
4360 "v<sat_op>.vx\t%0,%3,%z4%p1"
4361 [(set_attr "type" "<sat_insn_type>")
4362 (set_attr "mode" "<MODE>")])
4364 (define_insn "*pred_<sat_op><mode>_extended_scalar"
4365 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4366 (if_then_else:VI_D
4367 (unspec:<VM>
4368 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4369 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4370 (match_operand 6 "const_int_operand" " i, i, i, i")
4371 (match_operand 7 "const_int_operand" " i, i, i, i")
4372 (match_operand 8 "const_int_operand" " i, i, i, i")
4373 (match_operand 9 "const_int_operand" " i, i, i, i")
4374 (reg:SI VL_REGNUM)
4375 (reg:SI VTYPE_REGNUM)
4376 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4377 (unspec:VI_D
4378 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4379 (sign_extend:<VEL>
4380 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP)
4381 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4382 "TARGET_VECTOR"
4383 "v<sat_op>.vx\t%0,%3,%z4%p1"
4384 [(set_attr "type" "<sat_insn_type>")
4385 (set_attr "mode" "<MODE>")])
4387 ;; CLIP
4388 (define_insn "@pred_narrow_clip<v_su><mode>"
4389 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
4390 (if_then_else:<V_DOUBLE_TRUNC>
4391 (unspec:<VM>
4392 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
4393 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
4394 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4395 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4396 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4397 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4398 (reg:SI VL_REGNUM)
4399 (reg:SI VTYPE_REGNUM)
4400 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4401 (unspec:<V_DOUBLE_TRUNC>
4402 [(match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4403 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")] VNCLIP)
4404 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4405 "TARGET_VECTOR"
4406 "vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
4407 [(set_attr "type" "vnclip")
4408 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4410 (define_insn "@pred_narrow_clip<v_su><mode>_scalar"
4411 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4412 (if_then_else:<V_DOUBLE_TRUNC>
4413 (unspec:<VM>
4414 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4415 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4416 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4417 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4418 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4419 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
4420 (reg:SI VL_REGNUM)
4421 (reg:SI VTYPE_REGNUM)
4422 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4423 (unspec:<V_DOUBLE_TRUNC>
4424 [(match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4425 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")] VNCLIP)
4426 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4427 "TARGET_VECTOR"
4428 "vnclip<v_su>.w%o4\t%0,%3,%4%p1"
4429 [(set_attr "type" "vnclip")
4430 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4432 ;; -------------------------------------------------------------------------------
4433 ;; ---- Predicated integer comparison operations
4434 ;; -------------------------------------------------------------------------------
4435 ;; Includes:
4436 ;; - 11.8 Vector Integer Comparision Instructions
4437 ;; -------------------------------------------------------------------------------
4439 (define_expand "@pred_cmp<mode>"
4440 [(set (match_operand:<VM> 0 "register_operand")
4441 (if_then_else:<VM>
4442 (unspec:<VM>
4443 [(match_operand:<VM> 1 "vector_mask_operand")
4444 (match_operand 6 "vector_length_operand")
4445 (match_operand 7 "const_int_operand")
4446 (match_operand 8 "const_int_operand")
4447 (reg:SI VL_REGNUM)
4448 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4449 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4450 [(match_operand:V_VLSI 4 "register_operand")
4451 (match_operand:V_VLSI 5 "vector_arith_operand")])
4452 (match_operand:<VM> 2 "vector_merge_operand")))]
4453 "TARGET_VECTOR"
4454 {})
4456 (define_insn "*pred_cmp<mode>_merge_tie_mask"
4457 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4458 (if_then_else:<VM>
4459 (unspec:<VM>
4460 [(match_operand:<VM> 1 "register_operand" " 0")
4461 (match_operand 5 "vector_length_operand" " rK")
4462 (match_operand 6 "const_int_operand" " i")
4463 (match_operand 7 "const_int_operand" " i")
4464 (reg:SI VL_REGNUM)
4465 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4466 (match_operator:<VM> 2 "comparison_except_ltge_operator"
4467 [(match_operand:V_VLSI 3 "register_operand" " vr")
4468 (match_operand:V_VLSI 4 "vector_arith_operand" "vrvi")])
4469 (match_dup 1)))]
4470 "TARGET_VECTOR"
4471 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4472 [(set_attr "type" "vicmp")
4473 (set_attr "mode" "<MODE>")
4474 (set_attr "merge_op_idx" "1")
4475 (set_attr "vl_op_idx" "5")
4476 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4477 (set (attr "avl_type_idx") (const_int 7))])
4479 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4480 (define_insn "*pred_cmp<mode>"
4481 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr")
4482 (if_then_else:<VM>
4483 (unspec:<VM>
4484 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4485 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4486 (match_operand 7 "const_int_operand" " i, i, i, i")
4487 (match_operand 8 "const_int_operand" " i, i, i, i")
4488 (reg:SI VL_REGNUM)
4489 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4490 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4491 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
4492 (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi")])
4493 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4494 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4495 "vms%B3.v%o5\t%0,%4,%v5%p1"
4496 [(set_attr "type" "vicmp")
4497 (set_attr "mode" "<MODE>")])
4499 ;; We use early-clobber for source LMUL > dest LMUL.
4500 (define_insn "*pred_cmp<mode>_narrow"
4501 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4502 (if_then_else:<VM>
4503 (unspec:<VM>
4504 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4505 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4506 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4507 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4508 (reg:SI VL_REGNUM)
4509 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4510 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4511 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4512 (match_operand:V_VLSI 5 "vector_arith_operand" " vrvi, vrvi, 0, 0, vrvi, 0, 0, vrvi, vrvi")])
4513 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4514 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4515 "vms%B3.v%o5\t%0,%4,%v5%p1"
4516 [(set_attr "type" "vicmp")
4517 (set_attr "mode" "<MODE>")])
4519 (define_expand "@pred_ltge<mode>"
4520 [(set (match_operand:<VM> 0 "register_operand")
4521 (if_then_else:<VM>
4522 (unspec:<VM>
4523 [(match_operand:<VM> 1 "vector_mask_operand")
4524 (match_operand 6 "vector_length_operand")
4525 (match_operand 7 "const_int_operand")
4526 (match_operand 8 "const_int_operand")
4527 (reg:SI VL_REGNUM)
4528 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4529 (match_operator:<VM> 3 "ltge_operator"
4530 [(match_operand:V_VLSI 4 "register_operand")
4531 (match_operand:V_VLSI 5 "vector_neg_arith_operand")])
4532 (match_operand:<VM> 2 "vector_merge_operand")))]
4533 "TARGET_VECTOR"
4534 {})
4536 (define_insn "*pred_ltge<mode>_merge_tie_mask"
4537 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4538 (if_then_else:<VM>
4539 (unspec:<VM>
4540 [(match_operand:<VM> 1 "register_operand" " 0")
4541 (match_operand 5 "vector_length_operand" " rK")
4542 (match_operand 6 "const_int_operand" " i")
4543 (match_operand 7 "const_int_operand" " i")
4544 (reg:SI VL_REGNUM)
4545 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4546 (match_operator:<VM> 2 "ltge_operator"
4547 [(match_operand:V_VLSI 3 "register_operand" " vr")
4548 (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")])
4549 (match_dup 1)))]
4550 "TARGET_VECTOR"
4551 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4552 [(set_attr "type" "vicmp")
4553 (set_attr "mode" "<MODE>")
4554 (set_attr "merge_op_idx" "1")
4555 (set_attr "vl_op_idx" "5")
4556 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4557 (set (attr "avl_type_idx") (const_int 7))])
4559 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4560 (define_insn "*pred_ltge<mode>"
4561 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr")
4562 (if_then_else:<VM>
4563 (unspec:<VM>
4564 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4565 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4566 (match_operand 7 "const_int_operand" " i, i, i, i")
4567 (match_operand 8 "const_int_operand" " i, i, i, i")
4568 (reg:SI VL_REGNUM)
4569 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4570 (match_operator:<VM> 3 "ltge_operator"
4571 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
4572 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj")])
4573 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4574 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4575 "vms%B3.v%o5\t%0,%4,%v5%p1"
4576 [(set_attr "type" "vicmp")
4577 (set_attr "mode" "<MODE>")])
4579 ;; We use early-clobber for source LMUL > dest LMUL.
4580 (define_insn "*pred_ltge<mode>_narrow"
4581 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4582 (if_then_else:<VM>
4583 (unspec:<VM>
4584 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4585 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4586 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4587 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4588 (reg:SI VL_REGNUM)
4589 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4590 (match_operator:<VM> 3 "ltge_operator"
4591 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4592 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vrvj, vrvj, 0, 0, vrvj, 0, 0, vrvj, vrvj")])
4593 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4594 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4595 "vms%B3.v%o5\t%0,%4,%v5%p1"
4596 [(set_attr "type" "vicmp")
4597 (set_attr "mode" "<MODE>")])
4599 (define_expand "@pred_cmp<mode>_scalar"
4600 [(set (match_operand:<VM> 0 "register_operand")
4601 (if_then_else:<VM>
4602 (unspec:<VM>
4603 [(match_operand:<VM> 1 "vector_mask_operand")
4604 (match_operand 6 "vector_length_operand")
4605 (match_operand 7 "const_int_operand")
4606 (match_operand 8 "const_int_operand")
4607 (reg:SI VL_REGNUM)
4608 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4609 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4610 [(match_operand:V_VLSI_QHS 4 "register_operand")
4611 (vec_duplicate:V_VLSI_QHS
4612 (match_operand:<VEL> 5 "register_operand"))])
4613 (match_operand:<VM> 2 "vector_merge_operand")))]
4614 "TARGET_VECTOR"
4615 {})
4617 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4618 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4619 (if_then_else:<VM>
4620 (unspec:<VM>
4621 [(match_operand:<VM> 1 "register_operand" " 0")
4622 (match_operand 5 "vector_length_operand" " rK")
4623 (match_operand 6 "const_int_operand" " i")
4624 (match_operand 7 "const_int_operand" " i")
4625 (reg:SI VL_REGNUM)
4626 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4627 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4628 [(match_operand:V_VLSI_QHS 3 "register_operand" " vr")
4629 (vec_duplicate:V_VLSI_QHS
4630 (match_operand:<VEL> 4 "register_operand" " r"))])
4631 (match_dup 1)))]
4632 "TARGET_VECTOR"
4633 "vms%B2.vx\t%0,%3,%4,v0.t"
4634 [(set_attr "type" "vicmp")
4635 (set_attr "mode" "<MODE>")
4636 (set_attr "merge_op_idx" "1")
4637 (set_attr "vl_op_idx" "5")
4638 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4639 (set (attr "avl_type_idx") (const_int 7))])
4641 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4642 (define_insn "*pred_cmp<mode>_scalar"
4643 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4644 (if_then_else:<VM>
4645 (unspec:<VM>
4646 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4647 (match_operand 6 "vector_length_operand" " rK, rK")
4648 (match_operand 7 "const_int_operand" " i, i")
4649 (match_operand 8 "const_int_operand" " i, i")
4650 (reg:SI VL_REGNUM)
4651 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4652 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4653 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")
4654 (vec_duplicate:V_VLSI_QHS
4655 (match_operand:<VEL> 5 "register_operand" " r, r"))])
4656 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4657 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4658 "vms%B3.vx\t%0,%4,%5%p1"
4659 [(set_attr "type" "vicmp")
4660 (set_attr "mode" "<MODE>")])
4662 ;; We use early-clobber for source LMUL > dest LMUL.
4663 (define_insn "*pred_cmp<mode>_scalar_narrow"
4664 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4665 (if_then_else:<VM>
4666 (unspec:<VM>
4667 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4668 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4669 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4670 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4671 (reg:SI VL_REGNUM)
4672 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4673 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4674 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")
4675 (vec_duplicate:V_VLSI_QHS
4676 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4677 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4678 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4679 "vms%B3.vx\t%0,%4,%5%p1"
4680 [(set_attr "type" "vicmp")
4681 (set_attr "mode" "<MODE>")])
4683 (define_expand "@pred_eqne<mode>_scalar"
4684 [(set (match_operand:<VM> 0 "register_operand")
4685 (if_then_else:<VM>
4686 (unspec:<VM>
4687 [(match_operand:<VM> 1 "vector_mask_operand")
4688 (match_operand 6 "vector_length_operand")
4689 (match_operand 7 "const_int_operand")
4690 (match_operand 8 "const_int_operand")
4691 (reg:SI VL_REGNUM)
4692 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4693 (match_operator:<VM> 3 "equality_operator"
4694 [(vec_duplicate:V_VLSI_QHS
4695 (match_operand:<VEL> 5 "register_operand"))
4696 (match_operand:V_VLSI_QHS 4 "register_operand")])
4697 (match_operand:<VM> 2 "vector_merge_operand")))]
4698 "TARGET_VECTOR"
4699 {})
4701 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
4702 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4703 (if_then_else:<VM>
4704 (unspec:<VM>
4705 [(match_operand:<VM> 1 "register_operand" " 0")
4706 (match_operand 5 "vector_length_operand" " rK")
4707 (match_operand 6 "const_int_operand" " i")
4708 (match_operand 7 "const_int_operand" " i")
4709 (reg:SI VL_REGNUM)
4710 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4711 (match_operator:<VM> 2 "equality_operator"
4712 [(vec_duplicate:V_VLSI_QHS
4713 (match_operand:<VEL> 4 "register_operand" " r"))
4714 (match_operand:V_VLSI_QHS 3 "register_operand" " vr")])
4715 (match_dup 1)))]
4716 "TARGET_VECTOR"
4717 "vms%B2.vx\t%0,%3,%4,v0.t"
4718 [(set_attr "type" "vicmp")
4719 (set_attr "mode" "<MODE>")
4720 (set_attr "merge_op_idx" "1")
4721 (set_attr "vl_op_idx" "5")
4722 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4723 (set (attr "avl_type_idx") (const_int 7))])
4725 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4726 (define_insn "*pred_eqne<mode>_scalar"
4727 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4728 (if_then_else:<VM>
4729 (unspec:<VM>
4730 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4731 (match_operand 6 "vector_length_operand" " rK, rK")
4732 (match_operand 7 "const_int_operand" " i, i")
4733 (match_operand 8 "const_int_operand" " i, i")
4734 (reg:SI VL_REGNUM)
4735 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4736 (match_operator:<VM> 3 "equality_operator"
4737 [(vec_duplicate:V_VLSI_QHS
4738 (match_operand:<VEL> 5 "register_operand" " r, r"))
4739 (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")])
4740 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4741 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4742 "vms%B3.vx\t%0,%4,%5%p1"
4743 [(set_attr "type" "vicmp")
4744 (set_attr "mode" "<MODE>")])
4746 ;; We use early-clobber for source LMUL > dest LMUL.
4747 (define_insn "*pred_eqne<mode>_scalar_narrow"
4748 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4749 (if_then_else:<VM>
4750 (unspec:<VM>
4751 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4752 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4753 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4754 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4755 (reg:SI VL_REGNUM)
4756 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4757 (match_operator:<VM> 3 "equality_operator"
4758 [(vec_duplicate:V_VLSI_QHS
4759 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
4760 (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")])
4761 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4762 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4763 "vms%B3.vx\t%0,%4,%5%p1"
4764 [(set_attr "type" "vicmp")
4765 (set_attr "mode" "<MODE>")])
4767 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4768 ;; we need to deal with SEW = 64 in RV32 system.
4769 (define_expand "@pred_cmp<mode>_scalar"
4770 [(set (match_operand:<VM> 0 "register_operand")
4771 (if_then_else:<VM>
4772 (unspec:<VM>
4773 [(match_operand:<VM> 1 "vector_mask_operand")
4774 (match_operand 6 "vector_length_operand")
4775 (match_operand 7 "const_int_operand")
4776 (match_operand 8 "const_int_operand")
4777 (reg:SI VL_REGNUM)
4778 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4779 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4780 [(match_operand:V_VLSI_D 4 "register_operand")
4781 (vec_duplicate:V_VLSI_D
4782 (match_operand:<VEL> 5 "reg_or_int_operand"))])
4783 (match_operand:<VM> 2 "vector_merge_operand")))]
4784 "TARGET_VECTOR"
4785 {
4786 enum rtx_code code = GET_CODE (operands[3]);
4787 if (riscv_vector::sew64_scalar_helper (
4788 operands,
4789 /* scalar op */&operands[5],
4790 /* vl */operands[6],
4791 <MODE>mode,
4792 riscv_vector::has_vi_variant_p (code, operands[5]),
4793 code == LT || code == LTU ?
4794 [] (rtx *operands, rtx boardcast_scalar) {
4795 emit_insn (gen_pred_ltge<mode> (operands[0], operands[1],
4796 operands[2], operands[3], operands[4], boardcast_scalar,
4797 operands[6], operands[7], operands[8]));
4798 }
4799 :
4800 [] (rtx *operands, rtx boardcast_scalar) {
4801 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4802 operands[2], operands[3], operands[4], boardcast_scalar,
4803 operands[6], operands[7], operands[8]));
4804 },
4805 (riscv_vector::avl_type) INTVAL (operands[8])))
4806 DONE;
4807 })
4809 (define_expand "@pred_eqne<mode>_scalar"
4810 [(set (match_operand:<VM> 0 "register_operand")
4811 (if_then_else:<VM>
4812 (unspec:<VM>
4813 [(match_operand:<VM> 1 "vector_mask_operand")
4814 (match_operand 6 "vector_length_operand")
4815 (match_operand 7 "const_int_operand")
4816 (match_operand 8 "const_int_operand")
4817 (reg:SI VL_REGNUM)
4818 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4819 (match_operator:<VM> 3 "equality_operator"
4820 [(vec_duplicate:V_VLSI_D
4821 (match_operand:<VEL> 5 "reg_or_int_operand"))
4822 (match_operand:V_VLSI_D 4 "register_operand")])
4823 (match_operand:<VM> 2 "vector_merge_operand")))]
4824 "TARGET_VECTOR"
4825 {
4826 enum rtx_code code = GET_CODE (operands[3]);
4827 if (riscv_vector::sew64_scalar_helper (
4828 operands,
4829 /* scalar op */&operands[5],
4830 /* vl */operands[6],
4831 <MODE>mode,
4832 riscv_vector::has_vi_variant_p (code, operands[5]),
4833 [] (rtx *operands, rtx boardcast_scalar) {
4834 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4835 operands[2], operands[3], operands[4], boardcast_scalar,
4836 operands[6], operands[7], operands[8]));
4837 },
4838 (riscv_vector::avl_type) INTVAL (operands[8])))
4839 DONE;
4840 })
4842 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4843 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4844 (if_then_else:<VM>
4845 (unspec:<VM>
4846 [(match_operand:<VM> 1 "register_operand" " 0")
4847 (match_operand 5 "vector_length_operand" " rK")
4848 (match_operand 6 "const_int_operand" " i")
4849 (match_operand 7 "const_int_operand" " i")
4850 (reg:SI VL_REGNUM)
4851 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4852 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4853 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
4854 (vec_duplicate:V_VLSI_D
4855 (match_operand:<VEL> 4 "register_operand" " r"))])
4856 (match_dup 1)))]
4857 "TARGET_VECTOR"
4858 "vms%B2.vx\t%0,%3,%4,v0.t"
4859 [(set_attr "type" "vicmp")
4860 (set_attr "mode" "<MODE>")
4861 (set_attr "merge_op_idx" "1")
4862 (set_attr "vl_op_idx" "5")
4863 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4864 (set (attr "avl_type_idx") (const_int 7))])
4866 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
4867 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4868 (if_then_else:<VM>
4869 (unspec:<VM>
4870 [(match_operand:<VM> 1 "register_operand" " 0")
4871 (match_operand 5 "vector_length_operand" " rK")
4872 (match_operand 6 "const_int_operand" " i")
4873 (match_operand 7 "const_int_operand" " i")
4874 (reg:SI VL_REGNUM)
4875 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4876 (match_operator:<VM> 2 "equality_operator"
4877 [(vec_duplicate:V_VLSI_D
4878 (match_operand:<VEL> 4 "register_operand" " r"))
4879 (match_operand:V_VLSI_D 3 "register_operand" " vr")])
4880 (match_dup 1)))]
4881 "TARGET_VECTOR"
4882 "vms%B2.vx\t%0,%3,%4,v0.t"
4883 [(set_attr "type" "vicmp")
4884 (set_attr "mode" "<MODE>")
4885 (set_attr "merge_op_idx" "1")
4886 (set_attr "vl_op_idx" "5")
4887 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4888 (set (attr "avl_type_idx") (const_int 7))])
4890 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4891 (define_insn "*pred_cmp<mode>_scalar"
4892 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4893 (if_then_else:<VM>
4894 (unspec:<VM>
4895 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4896 (match_operand 6 "vector_length_operand" " rK, rK")
4897 (match_operand 7 "const_int_operand" " i, i")
4898 (match_operand 8 "const_int_operand" " i, i")
4899 (reg:SI VL_REGNUM)
4900 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4901 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4902 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
4903 (vec_duplicate:V_VLSI_D
4904 (match_operand:<VEL> 5 "register_operand" " r, r"))])
4905 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4906 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4907 "vms%B3.vx\t%0,%4,%5%p1"
4908 [(set_attr "type" "vicmp")
4909 (set_attr "mode" "<MODE>")])
4911 ;; We use early-clobber for source LMUL > dest LMUL.
4912 (define_insn "*pred_cmp<mode>_scalar_narrow"
4913 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4914 (if_then_else:<VM>
4915 (unspec:<VM>
4916 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4917 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4918 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4919 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4920 (reg:SI VL_REGNUM)
4921 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4922 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4923 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
4924 (vec_duplicate:V_VLSI_D
4925 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4926 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4927 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4928 "vms%B3.vx\t%0,%4,%5%p1"
4929 [(set_attr "type" "vicmp")
4930 (set_attr "mode" "<MODE>")])
4932 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4933 (define_insn "*pred_eqne<mode>_scalar"
4934 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4935 (if_then_else:<VM>
4936 (unspec:<VM>
4937 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4938 (match_operand 6 "vector_length_operand" " rK, rK")
4939 (match_operand 7 "const_int_operand" " i, i")
4940 (match_operand 8 "const_int_operand" " i, i")
4941 (reg:SI VL_REGNUM)
4942 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4943 (match_operator:<VM> 3 "equality_operator"
4944 [(vec_duplicate:V_VLSI_D
4945 (match_operand:<VEL> 5 "register_operand" " r, r"))
4946 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")])
4947 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4948 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4949 "vms%B3.vx\t%0,%4,%5%p1"
4950 [(set_attr "type" "vicmp")
4951 (set_attr "mode" "<MODE>")])
4953 ;; We use early-clobber for source LMUL > dest LMUL.
4954 (define_insn "*pred_eqne<mode>_scalar_narrow"
4955 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4956 (if_then_else:<VM>
4957 (unspec:<VM>
4958 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4959 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4960 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4961 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4962 (reg:SI VL_REGNUM)
4963 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4964 (match_operator:<VM> 3 "equality_operator"
4965 [(vec_duplicate:V_VLSI_D
4966 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
4967 (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
4968 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4969 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4970 "vms%B3.vx\t%0,%4,%5%p1"
4971 [(set_attr "type" "vicmp")
4972 (set_attr "mode" "<MODE>")])
4974 (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
4975 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4976 (if_then_else:<VM>
4977 (unspec:<VM>
4978 [(match_operand:<VM> 1 "register_operand" " 0")
4979 (match_operand 5 "vector_length_operand" " rK")
4980 (match_operand 6 "const_int_operand" " i")
4981 (match_operand 7 "const_int_operand" " i")
4982 (reg:SI VL_REGNUM)
4983 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4984 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4985 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
4986 (vec_duplicate:V_VLSI_D
4987 (sign_extend:<VEL>
4988 (match_operand:<VSUBEL> 4 "register_operand" " r")))])
4989 (match_dup 1)))]
4990 "TARGET_VECTOR"
4991 "vms%B2.vx\t%0,%3,%4,v0.t"
4992 [(set_attr "type" "vicmp")
4993 (set_attr "mode" "<MODE>")
4994 (set_attr "merge_op_idx" "1")
4995 (set_attr "vl_op_idx" "5")
4996 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4997 (set (attr "avl_type_idx") (const_int 7))])
4999 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5000 (define_insn "*pred_cmp<mode>_extended_scalar"
5001 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
5002 (if_then_else:<VM>
5003 (unspec:<VM>
5004 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
5005 (match_operand 6 "vector_length_operand" " rK, rK")
5006 (match_operand 7 "const_int_operand" " i, i")
5007 (match_operand 8 "const_int_operand" " i, i")
5008 (reg:SI VL_REGNUM)
5009 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5010 (match_operator:<VM> 3 "comparison_except_eqge_operator"
5011 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
5012 (vec_duplicate:V_VLSI_D
5013 (sign_extend:<VEL>
5014 (match_operand:<VSUBEL> 5 "register_operand" " r, r")))])
5015 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
5016 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
5017 "vms%B3.vx\t%0,%4,%5%p1"
5018 [(set_attr "type" "vicmp")
5019 (set_attr "mode" "<MODE>")])
5021 (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
5022 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5023 (if_then_else:<VM>
5024 (unspec:<VM>
5025 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5026 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5027 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5028 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5029 (reg:SI VL_REGNUM)
5030 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5031 (match_operator:<VM> 3 "comparison_except_eqge_operator"
5032 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
5033 (vec_duplicate:V_VLSI_D
5034 (sign_extend:<VEL>
5035 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))])
5036 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5037 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
5038 "vms%B3.vx\t%0,%4,%5%p1"
5039 [(set_attr "type" "vicmp")
5040 (set_attr "mode" "<MODE>")])
5042 (define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
5043 [(set (match_operand:<VM> 0 "register_operand" "=vm")
5044 (if_then_else:<VM>
5045 (unspec:<VM>
5046 [(match_operand:<VM> 1 "register_operand" " 0")
5047 (match_operand 5 "vector_length_operand" " rK")
5048 (match_operand 6 "const_int_operand" " i")
5049 (match_operand 7 "const_int_operand" " i")
5050 (reg:SI VL_REGNUM)
5051 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5052 (match_operator:<VM> 2 "equality_operator"
5053 [(vec_duplicate:V_VLSI_D
5054 (sign_extend:<VEL>
5055 (match_operand:<VSUBEL> 4 "register_operand" " r")))
5056 (match_operand:V_VLSI_D 3 "register_operand" " vr")])
5057 (match_dup 1)))]
5058 "TARGET_VECTOR"
5059 "vms%B2.vx\t%0,%3,%4,v0.t"
5060 [(set_attr "type" "vicmp")
5061 (set_attr "mode" "<MODE>")
5062 (set_attr "merge_op_idx" "1")
5063 (set_attr "vl_op_idx" "5")
5064 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5065 (set (attr "avl_type_idx") (const_int 7))])
5067 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5068 (define_insn "*pred_eqne<mode>_extended_scalar"
5069 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
5070 (if_then_else:<VM>
5071 (unspec:<VM>
5072 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
5073 (match_operand 6 "vector_length_operand" " rK, rK")
5074 (match_operand 7 "const_int_operand" " i, i")
5075 (match_operand 8 "const_int_operand" " i, i")
5076 (reg:SI VL_REGNUM)
5077 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5078 (match_operator:<VM> 3 "equality_operator"
5079 [(vec_duplicate:V_VLSI_D
5080 (sign_extend:<VEL>
5081 (match_operand:<VSUBEL> 5 "register_operand" " r, r")))
5082 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")])
5083 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
5084 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
5085 "vms%B3.vx\t%0,%4,%5%p1"
5086 [(set_attr "type" "vicmp")
5087 (set_attr "mode" "<MODE>")])
5089 (define_insn "*pred_eqne<mode>_extended_scalar_narrow"
5090 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5091 (if_then_else:<VM>
5092 (unspec:<VM>
5093 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5094 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5095 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5096 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5097 (reg:SI VL_REGNUM)
5098 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5099 (match_operator:<VM> 3 "equality_operator"
5100 [(vec_duplicate:V_VLSI_D
5101 (sign_extend:<VEL>
5102 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))
5103 (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
5104 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5105 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
5106 "vms%B3.vx\t%0,%4,%5%p1"
5107 [(set_attr "type" "vicmp")
5108 (set_attr "mode" "<MODE>")])
5110 ;; GE, vmsge.vx/vmsgeu.vx
5111 ;;
5112 ;; unmasked va >= x
5113 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x
5114 ;; - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
5115 ;;
5116 ;; masked va >= x, vd != v0
5117 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5118 ;; - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
5119 ;;
5120 ;; masked va >= x, vd == v0
5121 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5122 ;; - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
5123 (define_expand "@pred_ge<mode>_scalar"
5124 [(set (match_operand:<VM> 0 "register_operand")
5125 (if_then_else:<VM>
5126 (unspec:<VM>
5127 [(match_operand:<VM> 1 "vector_mask_operand")
5128 (match_operand 6 "vector_length_operand")
5129 (match_operand 7 "const_int_operand")
5130 (match_operand 8 "const_int_operand")
5131 (reg:SI VL_REGNUM)
5132 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5133 (match_operator:<VM> 3 "ge_operator"
5134 [(match_operand:V_VLSI 4 "register_operand")
5135 (vec_duplicate:V_VLSI
5136 (match_operand:<VEL> 5 "reg_or_int_operand"))])
5137 (match_operand:<VM> 2 "vector_merge_operand")))]
5138 "TARGET_VECTOR"
5139 {
5140 enum rtx_code code = GET_CODE (operands[3]);
5141 rtx undef = RVV_VUNDEF (<VM>mode);
5142 rtx tmp = gen_reg_rtx (<VM>mode);
5143 if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
5144 {
5145 /* If vmsgeu with 0 immediate, expand it to vmset. */
5146 if (satisfies_constraint_Wc1 (operands[1]))
5147 emit_insn (
5148 gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
5149 CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
5150 else
5151 {
5152 /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
5153 */
5154 if (rtx_equal_p (operands[1], operands[2]))
5155 emit_move_insn (operands[0], operands[1]);
5156 else if (register_operand (operands[2], <VM>mode))
5157 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5158 CONSTM1_RTX (<VM>mode), undef, operands[1],
5159 operands[2], operands[6], operands[8]));
5160 else
5161 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5162 CONSTM1_RTX (<VM>mode), undef, operands[1],
5163 operands[1], operands[6], operands[8]));
5164 }
5165 }
5166 else if (riscv_vector::neg_simm5_p (operands[5]))
5167 emit_insn (
5168 gen_pred_ltge<mode> (operands[0], operands[1], operands[2], operands[3],
5169 operands[4],
5170 gen_const_vec_duplicate (<MODE>mode, operands[5]),
5171 operands[6], operands[7], operands[8]));
5172 else
5173 {
5174 if (code == GE)
5175 operands[3] = gen_rtx_fmt_ee (LT, <VM>mode, XEXP (operands[3], 0),
5176 XEXP (operands[3], 1));
5177 else
5178 operands[3] = gen_rtx_fmt_ee (LTU, <VM>mode, XEXP (operands[3], 0),
5179 XEXP (operands[3], 1));
5180 if (GET_MODE_BITSIZE (<VEL>mode) <= GET_MODE_BITSIZE (Pmode))
5181 operands[5] = force_reg (<VEL>mode, operands[5]);
5183 if (satisfies_constraint_Wc1 (operands[1]))
5184 {
5185 /* unmasked va >= x
5186 - pseudoinstruction: vmsge{u}.vx vd, va, x
5187 - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */
5188 emit_insn (
5189 gen_pred_cmp<mode>_scalar (tmp, operands[1], operands[2],
5190 operands[3], operands[4], operands[5],
5191 operands[6], operands[7], operands[8]));
5192 emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
5193 undef, tmp, tmp, operands[6], operands[8]));
5194 }
5195 else
5196 {
5197 if (rtx_equal_p (operands[1], operands[2]))
5198 {
5199 /* masked va >= x, vd == v0
5200 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5201 - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt. */
5202 emit_insn (gen_pred_cmp<mode>_scalar (
5203 tmp, CONSTM1_RTX (<VM>mode), undef, operands[3], operands[4],
5204 operands[5], operands[6], operands[7], operands[8]));
5205 emit_insn (
5206 gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
5207 operands[1], tmp, operands[6], operands[8]));
5208 }
5209 else
5210 {
5211 /* masked va >= x, vd != v0
5212 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5213 - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
5214 */
5215 emit_insn (gen_pred_cmp<mode>_scalar (
5216 tmp, operands[1], operands[2], operands[3], operands[4],
5217 operands[5], operands[6], operands[7], operands[8]));
5218 emit_insn (gen_pred (XOR, <VM>mode, operands[0],
5219 CONSTM1_RTX (<VM>mode), undef, tmp,
5220 operands[1], operands[6], operands[8]));
5221 }
5222 }
5223 }
5224 DONE;
5225 })
5227 ;; -------------------------------------------------------------------------------
5228 ;; ---- Predicated integer ternary operations
5229 ;; -------------------------------------------------------------------------------
5230 ;; Includes:
5231 ;; - 11.13 Vector Single-Width Integer Multiply-Add Instructions
5232 ;; -------------------------------------------------------------------------------
5234 (define_expand "@pred_mul_plus<mode>"
5235 [(set (match_operand:V_VLSI 0 "register_operand")
5236 (if_then_else:V_VLSI
5237 (unspec:<VM>
5238 [(match_operand:<VM> 1 "vector_mask_operand")
5239 (match_operand 6 "vector_length_operand")
5240 (match_operand 7 "const_int_operand")
5241 (match_operand 8 "const_int_operand")
5242 (match_operand 9 "const_int_operand")
5243 (reg:SI VL_REGNUM)
5244 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5245 (plus:V_VLSI
5246 (mult:V_VLSI
5247 (match_operand:V_VLSI 2 "register_operand")
5248 (match_operand:V_VLSI 3 "register_operand"))
5249 (match_operand:V_VLSI 4 "register_operand"))
5250 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5251 "TARGET_VECTOR"
5252 {
5253 riscv_vector::prepare_ternary_operands (operands);
5254 })
5256 (define_insn "*pred_mul_plus<mode>_undef"
5257 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5258 (if_then_else:V_VLSI
5259 (unspec:<VM>
5260 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5261 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5262 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5263 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5264 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5265 (reg:SI VL_REGNUM)
5266 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5267 (plus:V_VLSI
5268 (mult:V_VLSI
5269 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5270 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))
5271 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
5272 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5273 "TARGET_VECTOR"
5274 "@
5275 vmadd.vv\t%0,%4,%5%p1
5276 vmacc.vv\t%0,%3,%4%p1
5277 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1
5278 vmadd.vv\t%0,%4,%5%p1
5279 vmacc.vv\t%0,%3,%4%p1
5280 vmv.v.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1"
5281 [(set_attr "type" "vimuladd")
5282 (set_attr "mode" "<MODE>")])
5284 (define_insn "*pred_madd<mode>"
5285 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5286 (if_then_else:V_VLSI
5287 (unspec:<VM>
5288 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5289 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5290 (match_operand 6 "const_int_operand" " i, i, i, i")
5291 (match_operand 7 "const_int_operand" " i, i, i, i")
5292 (match_operand 8 "const_int_operand" " i, i, i, i")
5293 (reg:SI VL_REGNUM)
5294 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5295 (plus:V_VLSI
5296 (mult:V_VLSI
5297 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5298 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5299 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5300 (match_dup 2)))]
5301 "TARGET_VECTOR"
5302 "@
5303 vmadd.vv\t%0,%3,%4%p1
5304 vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1
5305 vmadd.vv\t%0,%3,%4%p1
5306 vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1"
5307 [(set_attr "type" "vimuladd")
5308 (set_attr "mode" "<MODE>")
5309 (set_attr "merge_op_idx" "4")
5310 (set_attr "vl_op_idx" "5")
5311 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5312 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5313 (set (attr "avl_type_idx") (const_int 8))])
5315 (define_insn "*pred_macc<mode>"
5316 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5317 (if_then_else:V_VLSI
5318 (unspec:<VM>
5319 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5320 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5321 (match_operand 6 "const_int_operand" " i, i, i, i")
5322 (match_operand 7 "const_int_operand" " i, i, i, i")
5323 (match_operand 8 "const_int_operand" " i, i, i, i")
5324 (reg:SI VL_REGNUM)
5325 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5326 (plus:V_VLSI
5327 (mult:V_VLSI
5328 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5329 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5330 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5331 (match_dup 4)))]
5332 "TARGET_VECTOR"
5333 "@
5334 vmacc.vv\t%0,%2,%3%p1
5335 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1
5336 vmacc.vv\t%0,%2,%3%p1
5337 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1"
5338 [(set_attr "type" "vimuladd")
5339 (set_attr "mode" "<MODE>")
5340 (set_attr "merge_op_idx" "2")
5341 (set_attr "vl_op_idx" "5")
5342 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5343 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5344 (set (attr "avl_type_idx") (const_int 8))])
5346 (define_expand "@pred_mul_plus<mode>_scalar"
5347 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5348 (if_then_else:V_VLSI_QHS
5349 (unspec:<VM>
5350 [(match_operand:<VM> 1 "vector_mask_operand")
5351 (match_operand 6 "vector_length_operand")
5352 (match_operand 7 "const_int_operand")
5353 (match_operand 8 "const_int_operand")
5354 (match_operand 9 "const_int_operand")
5355 (reg:SI VL_REGNUM)
5356 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5357 (plus:V_VLSI_QHS
5358 (mult:V_VLSI_QHS
5359 (vec_duplicate:V_VLSI_QHS
5360 (match_operand:<VEL> 2 "register_operand"))
5361 (match_operand:V_VLSI_QHS 3 "register_operand"))
5362 (match_operand:V_VLSI_QHS 4 "register_operand"))
5363 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5364 "TARGET_VECTOR"
5365 {})
5367 (define_insn "*pred_madd<mode>_scalar"
5368 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5369 (if_then_else:V_VLSI
5370 (unspec:<VM>
5371 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5372 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5373 (match_operand 6 "const_int_operand" " i, i, i, i")
5374 (match_operand 7 "const_int_operand" " i, i, i, i")
5375 (match_operand 8 "const_int_operand" " i, i, i, i")
5376 (reg:SI VL_REGNUM)
5377 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5378 (plus:V_VLSI
5379 (mult:V_VLSI
5380 (vec_duplicate:V_VLSI
5381 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5382 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))
5383 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5384 (match_dup 3)))]
5385 "TARGET_VECTOR"
5386 "@
5387 vmadd.vx\t%0,%2,%4%p1
5388 vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1
5389 vmadd.vx\t%0,%2,%4%p1
5390 vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1"
5391 [(set_attr "type" "vimuladd")
5392 (set_attr "mode" "<MODE>")
5393 (set_attr "merge_op_idx" "4")
5394 (set_attr "vl_op_idx" "5")
5395 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5396 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5397 (set (attr "avl_type_idx") (const_int 8))])
5399 (define_insn "*pred_macc<mode>_scalar"
5400 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5401 (if_then_else:V_VLSI
5402 (unspec:<VM>
5403 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5404 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5405 (match_operand 6 "const_int_operand" " i, i, i, i")
5406 (match_operand 7 "const_int_operand" " i, i, i, i")
5407 (match_operand 8 "const_int_operand" " i, i, i, i")
5408 (reg:SI VL_REGNUM)
5409 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5410 (plus:V_VLSI
5411 (mult:V_VLSI
5412 (vec_duplicate:V_VLSI
5413 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5414 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5415 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5416 (match_dup 4)))]
5417 "TARGET_VECTOR"
5418 "@
5419 vmacc.vx\t%0,%2,%3%p1
5420 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5421 vmacc.vx\t%0,%2,%3%p1
5422 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5423 [(set_attr "type" "vimuladd")
5424 (set_attr "mode" "<MODE>")
5425 (set_attr "merge_op_idx" "2")
5426 (set_attr "vl_op_idx" "5")
5427 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5428 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5429 (set (attr "avl_type_idx") (const_int 8))])
5431 (define_expand "@pred_mul_plus<mode>_scalar"
5432 [(set (match_operand:V_VLSI_D 0 "register_operand")
5433 (if_then_else:V_VLSI_D
5434 (unspec:<VM>
5435 [(match_operand:<VM> 1 "vector_mask_operand")
5436 (match_operand 6 "vector_length_operand")
5437 (match_operand 7 "const_int_operand")
5438 (match_operand 8 "const_int_operand")
5439 (match_operand 9 "const_int_operand")
5440 (reg:SI VL_REGNUM)
5441 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5442 (plus:V_VLSI_D
5443 (mult:V_VLSI_D
5444 (vec_duplicate:V_VLSI_D
5445 (match_operand:<VEL> 2 "reg_or_int_operand"))
5446 (match_operand:V_VLSI_D 3 "register_operand"))
5447 (match_operand:V_VLSI_D 4 "register_operand"))
5448 (match_operand:V_VLSI_D 5 "register_operand")))]
5449 "TARGET_VECTOR"
5450 {
5451 if (riscv_vector::sew64_scalar_helper (
5452 operands,
5453 /* scalar op */&operands[2],
5454 /* vl */operands[6],
5455 <MODE>mode,
5456 false,
5457 [] (rtx *operands, rtx boardcast_scalar) {
5458 emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
5459 boardcast_scalar, operands[3], operands[4], operands[5],
5460 operands[6], operands[7], operands[8], operands[9]));
5461 },
5462 (riscv_vector::avl_type) INTVAL (operands[9])))
5463 DONE;
5464 })
5466 (define_insn "*pred_madd<mode>_extended_scalar"
5467 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5468 (if_then_else:V_VLSI_D
5469 (unspec:<VM>
5470 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5471 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5472 (match_operand 6 "const_int_operand" " i, i, i, i")
5473 (match_operand 7 "const_int_operand" " i, i, i, i")
5474 (match_operand 8 "const_int_operand" " i, i, i, i")
5475 (reg:SI VL_REGNUM)
5476 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5477 (plus:V_VLSI_D
5478 (mult:V_VLSI_D
5479 (vec_duplicate:V_VLSI_D
5480 (sign_extend:<VEL>
5481 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5482 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))
5483 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr"))
5484 (match_dup 3)))]
5485 "TARGET_VECTOR"
5486 "@
5487 vmadd.vx\t%0,%2,%4%p1
5488 vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1
5489 vmadd.vx\t%0,%2,%4%p1
5490 vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1"
5491 [(set_attr "type" "vimuladd")
5492 (set_attr "mode" "<MODE>")
5493 (set_attr "merge_op_idx" "4")
5494 (set_attr "vl_op_idx" "5")
5495 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5496 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5497 (set (attr "avl_type_idx") (const_int 8))])
5499 (define_insn "*pred_macc<mode>_extended_scalar"
5500 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5501 (if_then_else:V_VLSI_D
5502 (unspec:<VM>
5503 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5504 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5505 (match_operand 6 "const_int_operand" " i, i, i, i")
5506 (match_operand 7 "const_int_operand" " i, i, i, i")
5507 (match_operand 8 "const_int_operand" " i, i, i, i")
5508 (reg:SI VL_REGNUM)
5509 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5510 (plus:V_VLSI_D
5511 (mult:V_VLSI_D
5512 (vec_duplicate:V_VLSI_D
5513 (sign_extend:<VEL>
5514 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5515 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))
5516 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr"))
5517 (match_dup 4)))]
5518 "TARGET_VECTOR"
5519 "@
5520 vmacc.vx\t%0,%2,%3%p1
5521 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5522 vmacc.vx\t%0,%2,%3%p1
5523 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5524 [(set_attr "type" "vimuladd")
5525 (set_attr "mode" "<MODE>")
5526 (set_attr "merge_op_idx" "2")
5527 (set_attr "vl_op_idx" "5")
5528 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5529 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5530 (set (attr "avl_type_idx") (const_int 8))])
5532 (define_expand "@pred_minus_mul<mode>"
5533 [(set (match_operand:V_VLSI 0 "register_operand")
5534 (if_then_else:V_VLSI
5535 (unspec:<VM>
5536 [(match_operand:<VM> 1 "vector_mask_operand")
5537 (match_operand 6 "vector_length_operand")
5538 (match_operand 7 "const_int_operand")
5539 (match_operand 8 "const_int_operand")
5540 (match_operand 9 "const_int_operand")
5541 (reg:SI VL_REGNUM)
5542 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5543 (minus:V_VLSI
5544 (match_operand:V_VLSI 4 "register_operand")
5545 (mult:V_VLSI
5546 (match_operand:V_VLSI 2 "register_operand")
5547 (match_operand:V_VLSI 3 "register_operand")))
5548 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5549 "TARGET_VECTOR"
5550 {
5551 riscv_vector::prepare_ternary_operands (operands);
5552 })
5554 (define_insn "*pred_minus_mul<mode>_undef"
5555 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5556 (if_then_else:V_VLSI
5557 (unspec:<VM>
5558 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5559 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5560 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5561 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5562 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5563 (reg:SI VL_REGNUM)
5564 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5565 (minus:V_VLSI
5566 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr")
5567 (mult:V_VLSI
5568 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5569 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr")))
5570 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5571 "TARGET_VECTOR"
5572 "@
5573 vnmsub.vv\t%0,%4,%5%p1
5574 vnmsac.vv\t%0,%3,%4%p1
5575 vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1
5576 vnmsub.vv\t%0,%4,%5%p1
5577 vnmsac.vv\t%0,%3,%4%p1
5578 vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1"
5579 [(set_attr "type" "vimuladd")
5580 (set_attr "mode" "<MODE>")])
5582 (define_insn "*pred_nmsub<mode>"
5583 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5584 (if_then_else:V_VLSI
5585 (unspec:<VM>
5586 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5587 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5588 (match_operand 6 "const_int_operand" " i, i, i, i")
5589 (match_operand 7 "const_int_operand" " i, i, i, i")
5590 (match_operand 8 "const_int_operand" " i, i, i, i")
5591 (reg:SI VL_REGNUM)
5592 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5593 (minus:V_VLSI
5594 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5595 (mult:V_VLSI
5596 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5597 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5598 (match_dup 2)))]
5599 "TARGET_VECTOR"
5600 "@
5601 vnmsub.vv\t%0,%3,%4%p1
5602 vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1
5603 vnmsub.vv\t%0,%3,%4%p1
5604 vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1"
5605 [(set_attr "type" "vimuladd")
5606 (set_attr "mode" "<MODE>")
5607 (set_attr "merge_op_idx" "4")
5608 (set_attr "vl_op_idx" "5")
5609 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5610 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5611 (set (attr "avl_type_idx") (const_int 8))])
5613 (define_insn "*pred_nmsac<mode>"
5614 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5615 (if_then_else:V_VLSI
5616 (unspec:<VM>
5617 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5618 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5619 (match_operand 6 "const_int_operand" " i, i, i, i")
5620 (match_operand 7 "const_int_operand" " i, i, i, i")
5621 (match_operand 8 "const_int_operand" " i, i, i, i")
5622 (reg:SI VL_REGNUM)
5623 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5624 (minus:V_VLSI
5625 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5626 (mult:V_VLSI
5627 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5628 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5629 (match_dup 4)))]
5630 "TARGET_VECTOR"
5631 "@
5632 vnmsac.vv\t%0,%2,%3%p1
5633 vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1
5634 vnmsac.vv\t%0,%2,%3%p1
5635 vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1"
5636 [(set_attr "type" "vimuladd")
5637 (set_attr "mode" "<MODE>")
5638 (set_attr "merge_op_idx" "2")
5639 (set_attr "vl_op_idx" "5")
5640 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5641 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5642 (set (attr "avl_type_idx") (const_int 8))])
5644 (define_expand "@pred_minus_mul<mode>_scalar"
5645 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5646 (if_then_else:V_VLSI_QHS
5647 (unspec:<VM>
5648 [(match_operand:<VM> 1 "vector_mask_operand")
5649 (match_operand 6 "vector_length_operand")
5650 (match_operand 7 "const_int_operand")
5651 (match_operand 8 "const_int_operand")
5652 (match_operand 9 "const_int_operand")
5653 (reg:SI VL_REGNUM)
5654 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5655 (minus:V_VLSI_QHS
5656 (match_operand:V_VLSI_QHS 4 "register_operand")
5657 (mult:V_VLSI_QHS
5658 (vec_duplicate:V_VLSI_QHS
5659 (match_operand:<VEL> 2 "register_operand"))
5660 (match_operand:V_VLSI_QHS 3 "register_operand")))
5661 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5662 "TARGET_VECTOR"
5663 {})
5665 (define_insn "*pred_nmsub<mode>_scalar"
5666 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5667 (if_then_else:V_VLSI
5668 (unspec:<VM>
5669 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5670 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5671 (match_operand 6 "const_int_operand" " i, i, i, i")
5672 (match_operand 7 "const_int_operand" " i, i, i, i")
5673 (match_operand 8 "const_int_operand" " i, i, i, i")
5674 (reg:SI VL_REGNUM)
5675 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5676 (minus:V_VLSI
5677 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5678 (mult:V_VLSI
5679 (vec_duplicate:V_VLSI
5680 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5681 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")))
5682 (match_dup 3)))]
5683 "TARGET_VECTOR"
5684 "@
5685 vnmsub.vx\t%0,%2,%4%p1
5686 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5687 vnmsub.vx\t%0,%2,%4%p1
5688 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5689 [(set_attr "type" "vimuladd")
5690 (set_attr "mode" "<MODE>")
5691 (set_attr "merge_op_idx" "4")
5692 (set_attr "vl_op_idx" "5")
5693 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5694 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5695 (set (attr "avl_type_idx") (const_int 8))])
5697 (define_insn "*pred_nmsac<mode>_scalar"
5698 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5699 (if_then_else:V_VLSI
5700 (unspec:<VM>
5701 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5702 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5703 (match_operand 6 "const_int_operand" " i, i, i, i")
5704 (match_operand 7 "const_int_operand" " i, i, i, i")
5705 (match_operand 8 "const_int_operand" " i, i, i, i")
5706 (reg:SI VL_REGNUM)
5707 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5708 (minus:V_VLSI
5709 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5710 (mult:V_VLSI
5711 (vec_duplicate:V_VLSI
5712 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5713 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5714 (match_dup 4)))]
5715 "TARGET_VECTOR"
5716 "@
5717 vnmsac.vx\t%0,%2,%3%p1
5718 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5719 vnmsac.vx\t%0,%2,%3%p1
5720 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5721 [(set_attr "type" "vimuladd")
5722 (set_attr "mode" "<MODE>")
5723 (set_attr "merge_op_idx" "2")
5724 (set_attr "vl_op_idx" "5")
5725 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5726 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5727 (set (attr "avl_type_idx") (const_int 8))])
5729 (define_expand "@pred_minus_mul<mode>_scalar"
5730 [(set (match_operand:V_VLSI_D 0 "register_operand")
5731 (if_then_else:V_VLSI_D
5732 (unspec:<VM>
5733 [(match_operand:<VM> 1 "vector_mask_operand")
5734 (match_operand 6 "vector_length_operand")
5735 (match_operand 7 "const_int_operand")
5736 (match_operand 8 "const_int_operand")
5737 (match_operand 9 "const_int_operand")
5738 (reg:SI VL_REGNUM)
5739 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5740 (minus:V_VLSI_D
5741 (match_operand:V_VLSI_D 4 "register_operand")
5742 (mult:V_VLSI_D
5743 (vec_duplicate:V_VLSI_D
5744 (match_operand:<VEL> 2 "reg_or_int_operand"))
5745 (match_operand:V_VLSI_D 3 "register_operand")))
5746 (match_operand:V_VLSI_D 5 "register_operand")))]
5747 "TARGET_VECTOR"
5748 {
5749 if (riscv_vector::sew64_scalar_helper (
5750 operands,
5751 /* scalar op */&operands[2],
5752 /* vl */operands[6],
5753 <MODE>mode,
5754 false,
5755 [] (rtx *operands, rtx boardcast_scalar) {
5756 emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
5757 boardcast_scalar, operands[3], operands[4], operands[5],
5758 operands[6], operands[7], operands[8], operands[9]));
5759 },
5760 (riscv_vector::avl_type) INTVAL (operands[9])))
5761 DONE;
5762 })
5764 (define_insn "*pred_nmsub<mode>_extended_scalar"
5765 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5766 (if_then_else:V_VLSI_D
5767 (unspec:<VM>
5768 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5769 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5770 (match_operand 6 "const_int_operand" " i, i, i, i")
5771 (match_operand 7 "const_int_operand" " i, i, i, i")
5772 (match_operand 8 "const_int_operand" " i, i, i, i")
5773 (reg:SI VL_REGNUM)
5774 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5775 (minus:V_VLSI_D
5776 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5777 (mult:V_VLSI_D
5778 (vec_duplicate:V_VLSI_D
5779 (sign_extend:<VEL>
5780 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5781 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")))
5782 (match_dup 3)))]
5783 "TARGET_VECTOR"
5784 "@
5785 vnmsub.vx\t%0,%2,%4%p1
5786 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5787 vnmsub.vx\t%0,%2,%4%p1
5788 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5789 [(set_attr "type" "vimuladd")
5790 (set_attr "mode" "<MODE>")
5791 (set_attr "merge_op_idx" "4")
5792 (set_attr "vl_op_idx" "5")
5793 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5794 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5795 (set (attr "avl_type_idx") (const_int 8))])
5797 (define_insn "*pred_nmsac<mode>_extended_scalar"
5798 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5799 (if_then_else:V_VLSI_D
5800 (unspec:<VM>
5801 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5802 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5803 (match_operand 6 "const_int_operand" " i, i, i, i")
5804 (match_operand 7 "const_int_operand" " i, i, i, i")
5805 (match_operand 8 "const_int_operand" " i, i, i, i")
5806 (reg:SI VL_REGNUM)
5807 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5808 (minus:V_VLSI_D
5809 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")
5810 (mult:V_VLSI_D
5811 (vec_duplicate:V_VLSI_D
5812 (sign_extend:<VEL>
5813 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5814 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")))
5815 (match_dup 4)))]
5816 "TARGET_VECTOR"
5817 "@
5818 vnmsac.vx\t%0,%2,%3%p1
5819 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5820 vnmsac.vx\t%0,%2,%3%p1
5821 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5822 [(set_attr "type" "vimuladd")
5823 (set_attr "mode" "<MODE>")
5824 (set_attr "merge_op_idx" "2")
5825 (set_attr "vl_op_idx" "5")
5826 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5827 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5828 (set (attr "avl_type_idx") (const_int 8))])
5830 ;; -------------------------------------------------------------------------------
5831 ;; ---- Predicated widen integer ternary operations
5832 ;; -------------------------------------------------------------------------------
5833 ;; Includes:
5834 ;; - 11.14 Vector Widening Integer Multiply-Add Instructions
5835 ;; -------------------------------------------------------------------------------
5837 (define_insn "@pred_widen_mul_plus<su><mode>"
5838 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5839 (if_then_else:VWEXTI
5840 (unspec:<VM>
5841 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5842 (match_operand 5 "vector_length_operand" " rK")
5843 (match_operand 6 "const_int_operand" " i")
5844 (match_operand 7 "const_int_operand" " i")
5845 (match_operand 8 "const_int_operand" " i")
5846 (reg:SI VL_REGNUM)
5847 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5848 (plus:VWEXTI
5849 (mult:VWEXTI
5850 (any_extend:VWEXTI
5851 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5852 (any_extend:VWEXTI
5853 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5854 (match_operand:VWEXTI 2 "register_operand" " 0"))
5855 (match_dup 2)))]
5856 "TARGET_VECTOR"
5857 "vwmacc<u>.vv\t%0,%3,%4%p1"
5858 [(set_attr "type" "viwmuladd")
5859 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5861 (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
5862 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5863 (if_then_else:VWEXTI
5864 (unspec:<VM>
5865 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5866 (match_operand 5 "vector_length_operand" " rK")
5867 (match_operand 6 "const_int_operand" " i")
5868 (match_operand 7 "const_int_operand" " i")
5869 (match_operand 8 "const_int_operand" " i")
5870 (reg:SI VL_REGNUM)
5871 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5872 (plus:VWEXTI
5873 (mult:VWEXTI
5874 (any_extend:VWEXTI
5875 (vec_duplicate:<V_DOUBLE_TRUNC>
5876 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5877 (any_extend:VWEXTI
5878 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5879 (match_operand:VWEXTI 2 "register_operand" " 0"))
5880 (match_dup 2)))]
5881 "TARGET_VECTOR"
5882 "vwmacc<u>.vx\t%0,%3,%4%p1"
5883 [(set_attr "type" "viwmuladd")
5884 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5886 (define_insn "@pred_widen_mul_plussu<mode>"
5887 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5888 (if_then_else:VWEXTI
5889 (unspec:<VM>
5890 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5891 (match_operand 5 "vector_length_operand" " rK")
5892 (match_operand 6 "const_int_operand" " i")
5893 (match_operand 7 "const_int_operand" " i")
5894 (match_operand 8 "const_int_operand" " i")
5895 (reg:SI VL_REGNUM)
5896 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5897 (plus:VWEXTI
5898 (mult:VWEXTI
5899 (sign_extend:VWEXTI
5900 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5901 (zero_extend:VWEXTI
5902 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5903 (match_operand:VWEXTI 2 "register_operand" " 0"))
5904 (match_dup 2)))]
5905 "TARGET_VECTOR"
5906 "vwmaccsu.vv\t%0,%3,%4%p1"
5907 [(set_attr "type" "viwmuladd")
5908 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5910 (define_insn "@pred_widen_mul_plussu<mode>_scalar"
5911 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5912 (if_then_else:VWEXTI
5913 (unspec:<VM>
5914 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5915 (match_operand 5 "vector_length_operand" " rK")
5916 (match_operand 6 "const_int_operand" " i")
5917 (match_operand 7 "const_int_operand" " i")
5918 (match_operand 8 "const_int_operand" " i")
5919 (reg:SI VL_REGNUM)
5920 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5921 (plus:VWEXTI
5922 (mult:VWEXTI
5923 (sign_extend:VWEXTI
5924 (vec_duplicate:<V_DOUBLE_TRUNC>
5925 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5926 (zero_extend:VWEXTI
5927 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5928 (match_operand:VWEXTI 2 "register_operand" " 0"))
5929 (match_dup 2)))]
5930 "TARGET_VECTOR"
5931 "vwmaccsu.vx\t%0,%3,%4%p1"
5932 [(set_attr "type" "viwmuladd")
5933 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5935 (define_insn "@pred_widen_mul_plusus<mode>_scalar"
5936 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5937 (if_then_else:VWEXTI
5938 (unspec:<VM>
5939 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5940 (match_operand 5 "vector_length_operand" " rK")
5941 (match_operand 6 "const_int_operand" " i")
5942 (match_operand 7 "const_int_operand" " i")
5943 (match_operand 8 "const_int_operand" " i")
5944 (reg:SI VL_REGNUM)
5945 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5946 (plus:VWEXTI
5947 (mult:VWEXTI
5948 (zero_extend:VWEXTI
5949 (vec_duplicate:<V_DOUBLE_TRUNC>
5950 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5951 (sign_extend:VWEXTI
5952 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5953 (match_operand:VWEXTI 2 "register_operand" " 0"))
5954 (match_dup 2)))]
5955 "TARGET_VECTOR"
5956 "vwmaccus.vx\t%0,%3,%4%p1"
5957 [(set_attr "type" "viwmuladd")
5958 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5960 ;; -------------------------------------------------------------------------------
5961 ;; ---- Predicated BOOL mask operations
5962 ;; -------------------------------------------------------------------------------
5963 ;; Includes:
5964 ;; - 15.1 Vector Mask-Register Logical Instructions
5965 ;; - 15.2 Vector count population in mask vcpop.m
5966 ;; - 15.3 vfirst find-first-set mask bit
5967 ;; - 15.4 vmsbf.m set-before-first mask bit
5968 ;; - 15.5 vmsif.m set-including-first mask bit
5969 ;; - 15.6 vmsof.m set-only-first mask bit
5970 ;; - 15.8 Vector Iota Instruction
5971 ;; - 15.9 Vector Element Index Instruction
5972 ;; -------------------------------------------------------------------------------
5974 ;; We keep this pattern same as pred_mov so that we can gain more optimizations.
5975 ;; For example, if we have vmxor.mm v1,v1,v1. It will be optmized as vmclr.m which
5976 ;; is generated by pred_mov.
5977 (define_insn "@pred_<optab><mode>"
5978 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5979 (if_then_else:VB_VLS
5980 (unspec:VB_VLS
5981 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
5982 (match_operand 5 "vector_length_operand" " rK")
5983 (match_operand 6 "const_int_operand" " i")
5984 (reg:SI VL_REGNUM)
5985 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5986 (any_bitwise:VB_VLS
5987 (match_operand:VB_VLS 3 "register_operand" " vr")
5988 (match_operand:VB_VLS 4 "register_operand" " vr"))
5989 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
5990 "TARGET_VECTOR"
5991 "vm<insn>.mm\t%0,%3,%4"
5992 [(set_attr "type" "vmalu")
5993 (set_attr "mode" "<MODE>")
5994 (set_attr "vl_op_idx" "5")
5995 (set (attr "avl_type_idx") (const_int 6))])
5997 (define_insn "@pred_n<optab><mode>"
5998 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5999 (if_then_else:VB_VLS
6000 (unspec:VB_VLS
6001 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6002 (match_operand 5 "vector_length_operand" " rK")
6003 (match_operand 6 "const_int_operand" " i")
6004 (reg:SI VL_REGNUM)
6005 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6006 (not:VB_VLS
6007 (any_bitwise:VB_VLS
6008 (match_operand:VB_VLS 3 "register_operand" " vr")
6009 (match_operand:VB_VLS 4 "register_operand" " vr")))
6010 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6011 "TARGET_VECTOR"
6012 "vm<ninsn>.mm\t%0,%3,%4"
6013 [(set_attr "type" "vmalu")
6014 (set_attr "mode" "<MODE>")
6015 (set_attr "vl_op_idx" "5")
6016 (set (attr "avl_type_idx") (const_int 6))])
6018 (define_insn "@pred_<optab>not<mode>"
6019 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6020 (if_then_else:VB_VLS
6021 (unspec:VB_VLS
6022 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6023 (match_operand 5 "vector_length_operand" " rK")
6024 (match_operand 6 "const_int_operand" " i")
6025 (reg:SI VL_REGNUM)
6026 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6027 (and_ior:VB_VLS
6028 (match_operand:VB_VLS 3 "register_operand" " vr")
6029 (not:VB_VLS
6030 (match_operand:VB_VLS 4 "register_operand" " vr")))
6031 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6032 "TARGET_VECTOR"
6033 "vm<insn>n.mm\t%0,%3,%4"
6034 [(set_attr "type" "vmalu")
6035 (set_attr "mode" "<MODE>")
6036 (set_attr "vl_op_idx" "5")
6037 (set (attr "avl_type_idx") (const_int 6))])
6039 (define_insn "@pred_not<mode>"
6040 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6041 (if_then_else:VB_VLS
6042 (unspec:VB_VLS
6043 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6044 (match_operand 4 "vector_length_operand" " rK")
6045 (match_operand 5 "const_int_operand" " i")
6046 (reg:SI VL_REGNUM)
6047 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6048 (not:VB_VLS
6049 (match_operand:VB_VLS 3 "register_operand" " vr"))
6050 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6051 "TARGET_VECTOR"
6052 "vmnot.m\t%0,%3"
6053 [(set_attr "type" "vmalu")
6054 (set_attr "mode" "<MODE>")
6055 (set_attr "vl_op_idx" "4")
6056 (set (attr "avl_type_idx") (const_int 5))])
6058 (define_insn "@pred_popcount<VB:mode><P:mode>"
6059 [(set (match_operand:P 0 "register_operand" "=r")
6060 (popcount:P
6061 (unspec:VB
6062 [(and:VB
6063 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6064 (match_operand:VB 2 "register_operand" " vr"))
6065 (match_operand 3 "vector_length_operand" " rK")
6066 (match_operand 4 "const_int_operand" " i")
6067 (reg:SI VL_REGNUM)
6068 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
6069 "TARGET_VECTOR"
6070 "vcpop.m\t%0,%2%p1"
6071 [(set_attr "type" "vmpop")
6072 (set_attr "mode" "<VB:MODE>")])
6074 (define_insn "@pred_ffs<VB:mode><P:mode>"
6075 [(set (match_operand:P 0 "register_operand" "=r")
6076 (plus:P
6077 (ffs:P
6078 (unspec:VB
6079 [(and:VB
6080 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6081 (match_operand:VB 2 "register_operand" " vr"))
6082 (match_operand 3 "vector_length_operand" " rK")
6083 (match_operand 4 "const_int_operand" " i")
6084 (reg:SI VL_REGNUM)
6085 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))
6086 (const_int -1)))]
6087 "TARGET_VECTOR"
6088 "vfirst.m\t%0,%2%p1"
6089 [(set_attr "type" "vmffs")
6090 (set_attr "mode" "<VB:MODE>")])
6092 (define_insn "@pred_<misc_op><mode>"
6093 [(set (match_operand:VB 0 "register_operand" "=&vr, &vr")
6094 (if_then_else:VB
6095 (unspec:VB
6096 [(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
6097 (match_operand 4 "vector_length_operand" " rK, rK")
6098 (match_operand 5 "const_int_operand" " i, i")
6099 (match_operand 6 "const_int_operand" " i, i")
6100 (reg:SI VL_REGNUM)
6101 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6102 (unspec:VB
6103 [(match_operand:VB 3 "register_operand" " vr, vr")] VMISC)
6104 (match_operand:VB 2 "vector_merge_operand" " vu, 0")))]
6105 "TARGET_VECTOR"
6106 "vm<misc_op>.m\t%0,%3%p1"
6107 [(set_attr "type" "vmsfs")
6108 (set_attr "mode" "<MODE>")])
6110 (define_insn "@pred_iota<mode>"
6111 [(set (match_operand:VI 0 "register_operand" "=&vr, &vr")
6112 (if_then_else:VI
6113 (unspec:<VM>
6114 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
6115 (match_operand 4 "vector_length_operand" " rK, rK")
6116 (match_operand 5 "const_int_operand" " i, i")
6117 (match_operand 6 "const_int_operand" " i, i")
6118 (match_operand 7 "const_int_operand" " i, i")
6119 (reg:SI VL_REGNUM)
6120 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6121 (unspec:VI
6122 [(match_operand:<VM> 3 "register_operand" " vr, vr")] UNSPEC_VIOTA)
6123 (match_operand:VI 2 "vector_merge_operand" " vu, 0")))]
6124 "TARGET_VECTOR"
6125 "viota.m\t%0,%3%p1"
6126 [(set_attr "type" "vmiota")
6127 (set_attr "mode" "<MODE>")])
6129 (define_insn "@pred_series<mode>"
6130 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
6131 (if_then_else:V_VLSI
6132 (unspec:<VM>
6133 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6134 (match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
6135 (match_operand 4 "const_int_operand" " i, i, i, i")
6136 (match_operand 5 "const_int_operand" " i, i, i, i")
6137 (match_operand 6 "const_int_operand" " i, i, i, i")
6138 (reg:SI VL_REGNUM)
6139 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6140 (vec_series:V_VLSI (const_int 0) (const_int 1))
6141 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6142 "TARGET_VECTOR"
6143 "vid.v\t%0%p1"
6144 [(set_attr "type" "vmidx")
6145 (set_attr "mode" "<MODE>")])
6147 ;; -------------------------------------------------------------------------------
6148 ;; ---- Predicated floating-point binary operations
6149 ;; -------------------------------------------------------------------------------
6150 ;; Includes:
6151 ;; - 13.2 Vector Single-Width Floating-Point Add/Subtract Instructions
6152 ;; - 13.4 Vector Single-Width Floating-Point Multiply/Divide Instructions
6153 ;; - 13.11 Vector Floating-Point MIN/MAX Instructions
6154 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions
6155 ;; -------------------------------------------------------------------------------
6157 (define_insn "@pred_<optab><mode>"
6158 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6159 (if_then_else:V_VLSF
6160 (unspec:<VM>
6161 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6162 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6163 (match_operand 6 "const_int_operand" " i, i, i, i")
6164 (match_operand 7 "const_int_operand" " i, i, i, i")
6165 (match_operand 8 "const_int_operand" " i, i, i, i")
6166 (match_operand 9 "const_int_operand" " i, i, i, i")
6167 (reg:SI VL_REGNUM)
6168 (reg:SI VTYPE_REGNUM)
6169 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6170 (any_float_binop:V_VLSF
6171 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6172 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6173 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6174 "TARGET_VECTOR"
6175 "vf<insn>.vv\t%0,%3,%4%p1"
6176 [(set_attr "type" "<float_insn_type>")
6177 (set_attr "mode" "<MODE>")
6178 (set (attr "frm_mode")
6179 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6181 (define_insn "@pred_<optab><mode>"
6182 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6183 (if_then_else:V_VLSF
6184 (unspec:<VM>
6185 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6186 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6187 (match_operand 6 "const_int_operand" " i, i, i, i")
6188 (match_operand 7 "const_int_operand" " i, i, i, i")
6189 (match_operand 8 "const_int_operand" " i, i, i, i")
6190 (reg:SI VL_REGNUM)
6191 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6192 (any_float_binop_nofrm:V_VLSF
6193 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6194 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6195 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6196 "TARGET_VECTOR"
6197 "vf<insn>.vv\t%0,%3,%4%p1"
6198 [(set_attr "type" "<float_insn_type>")
6199 (set_attr "mode" "<MODE>")])
6201 (define_insn "@pred_<ieee_fmaxmin_op><mode>"
6202 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6203 (if_then_else:V_VLSF
6204 (unspec:<VM>
6205 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6206 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6207 (match_operand 6 "const_int_operand" " i, i, i, i")
6208 (match_operand 7 "const_int_operand" " i, i, i, i")
6209 (match_operand 8 "const_int_operand" " i, i, i, i")
6210 (reg:SI VL_REGNUM)
6211 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6212 (unspec:V_VLSF
6213 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6214 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]
6215 UNSPEC_VFMAXMIN)
6216 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6217 "TARGET_VECTOR"
6218 "v<ieee_fmaxmin_op>.vv\t%0,%3,%4%p1"
6219 [(set_attr "type" "vfminmax")
6220 (set_attr "mode" "<MODE>")])
6222 (define_insn "@pred_<optab><mode>_scalar"
6223 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6224 (if_then_else:VF
6225 (unspec:<VM>
6226 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6227 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6228 (match_operand 6 "const_int_operand" " i, i, i, i")
6229 (match_operand 7 "const_int_operand" " i, i, i, i")
6230 (match_operand 8 "const_int_operand" " i, i, i, i")
6231 (match_operand 9 "const_int_operand" " i, i, i, i")
6232 (reg:SI VL_REGNUM)
6233 (reg:SI VTYPE_REGNUM)
6234 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6235 (commutative_float_binop:VF
6236 (vec_duplicate:VF
6237 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6238 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6239 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6240 "TARGET_VECTOR"
6241 "vf<insn>.vf\t%0,%3,%4%p1"
6242 [(set_attr "type" "<float_insn_type>")
6243 (set_attr "mode" "<MODE>")
6244 (set (attr "frm_mode")
6245 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6247 (define_insn "@pred_<optab><mode>_scalar"
6248 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6249 (if_then_else:VF
6250 (unspec:<VM>
6251 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6252 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6253 (match_operand 6 "const_int_operand" " i, i, i, i")
6254 (match_operand 7 "const_int_operand" " i, i, i, i")
6255 (match_operand 8 "const_int_operand" " i, i, i, i")
6256 (reg:SI VL_REGNUM)
6257 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6258 (commutative_float_binop_nofrm:VF
6259 (vec_duplicate:VF
6260 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6261 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6262 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6263 "TARGET_VECTOR"
6264 "vf<insn>.vf\t%0,%3,%4%p1"
6265 [(set_attr "type" "<float_insn_type>")
6266 (set_attr "mode" "<MODE>")])
6268 (define_insn "@pred_<ieee_fmaxmin_op><mode>_scalar"
6269 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6270 (if_then_else:VF
6271 (unspec:<VM>
6272 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6273 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6274 (match_operand 6 "const_int_operand" " i, i, i, i")
6275 (match_operand 7 "const_int_operand" " i, i, i, i")
6276 (match_operand 8 "const_int_operand" " i, i, i, i")
6277 (reg:SI VL_REGNUM)
6278 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6279 (unspec:VF
6280 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6281 (vec_duplicate:VF
6282 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))]
6283 UNSPEC_VFMAXMIN)
6284 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6285 "TARGET_VECTOR"
6286 "v<ieee_fmaxmin_op>.vf\t%0,%3,%4%p1"
6287 [(set_attr "type" "vfminmax")
6288 (set_attr "mode" "<MODE>")])
6290 (define_insn "@pred_<optab><mode>_scalar"
6291 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6292 (if_then_else:VF
6293 (unspec:<VM>
6294 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6295 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6296 (match_operand 6 "const_int_operand" " i, i, i, i")
6297 (match_operand 7 "const_int_operand" " i, i, i, i")
6298 (match_operand 8 "const_int_operand" " i, i, i, i")
6299 (match_operand 9 "const_int_operand" " i, i, i, i")
6300 (reg:SI VL_REGNUM)
6301 (reg:SI VTYPE_REGNUM)
6302 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6303 (non_commutative_float_binop:VF
6304 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6305 (vec_duplicate:VF
6306 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
6307 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6308 "TARGET_VECTOR"
6309 "vf<insn>.vf\t%0,%3,%4%p1"
6310 [(set_attr "type" "<float_insn_type>")
6311 (set_attr "mode" "<MODE>")
6312 (set (attr "frm_mode")
6313 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6315 (define_insn "@pred_<optab><mode>_reverse_scalar"
6316 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6317 (if_then_else:VF
6318 (unspec:<VM>
6319 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6320 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6321 (match_operand 6 "const_int_operand" " i, i, i, i")
6322 (match_operand 7 "const_int_operand" " i, i, i, i")
6323 (match_operand 8 "const_int_operand" " i, i, i, i")
6324 (match_operand 9 "const_int_operand" " i, i, i, i")
6325 (reg:SI VL_REGNUM)
6326 (reg:SI VTYPE_REGNUM)
6327 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6328 (non_commutative_float_binop:VF
6329 (vec_duplicate:VF
6330 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6331 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6332 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6333 "TARGET_VECTOR"
6334 "vfr<insn>.vf\t%0,%3,%4%p1"
6335 [(set_attr "type" "<float_insn_type>")
6336 (set_attr "mode" "<MODE>")
6337 (set (attr "frm_mode")
6338 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6340 (define_insn "@pred_<copysign><mode>"
6341 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6342 (if_then_else:V_VLSF
6343 (unspec:<VM>
6344 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6345 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6346 (match_operand 6 "const_int_operand" " i, i, i, i")
6347 (match_operand 7 "const_int_operand" " i, i, i, i")
6348 (match_operand 8 "const_int_operand" " i, i, i, i")
6349 (reg:SI VL_REGNUM)
6350 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6351 (unspec:V_VLSF
6352 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6353 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
6354 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6355 "TARGET_VECTOR"
6356 "vfsgnj<nx>.vv\t%0,%3,%4%p1"
6357 [(set_attr "type" "vfsgnj")
6358 (set_attr "mode" "<MODE>")])
6360 (define_insn "@pred_ncopysign<mode>"
6361 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6362 (if_then_else:VF
6363 (unspec:<VM>
6364 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6365 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6366 (match_operand 6 "const_int_operand" " i, i, i, i")
6367 (match_operand 7 "const_int_operand" " i, i, i, i")
6368 (match_operand 8 "const_int_operand" " i, i, i, i")
6369 (reg:SI VL_REGNUM)
6370 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6371 (neg:VF
6372 (unspec:VF
6373 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6374 (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))
6375 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6376 "TARGET_VECTOR"
6377 "vfsgnjn.vv\t%0,%3,%4%p1"
6378 [(set_attr "type" "vfsgnj")
6379 (set_attr "mode" "<MODE>")])
6381 (define_insn "@pred_<copysign><mode>_scalar"
6382 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6383 (if_then_else:V_VLSF
6384 (unspec:<VM>
6385 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6386 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6387 (match_operand 6 "const_int_operand" " i, i, i, i")
6388 (match_operand 7 "const_int_operand" " i, i, i, i")
6389 (match_operand 8 "const_int_operand" " i, i, i, i")
6390 (reg:SI VL_REGNUM)
6391 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6392 (unspec:V_VLSF
6393 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6394 (vec_duplicate:V_VLSF
6395 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
6396 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6397 "TARGET_VECTOR"
6398 "vfsgnj<nx>.vf\t%0,%3,%4%p1"
6399 [(set_attr "type" "vfsgnj")
6400 (set_attr "mode" "<MODE>")])
6402 (define_insn "@pred_ncopysign<mode>_scalar"
6403 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6404 (if_then_else:VF
6405 (unspec:<VM>
6406 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6407 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6408 (match_operand 6 "const_int_operand" " i, i, i, i")
6409 (match_operand 7 "const_int_operand" " i, i, i, i")
6410 (match_operand 8 "const_int_operand" " i, i, i, i")
6411 (reg:SI VL_REGNUM)
6412 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6413 (neg:VF
6414 (unspec:VF
6415 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6416 (vec_duplicate:VF
6417 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] UNSPEC_VCOPYSIGN))
6418 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6419 "TARGET_VECTOR"
6420 "vfsgnjn.vf\t%0,%3,%4%p1"
6421 [(set_attr "type" "vfsgnj")
6422 (set_attr "mode" "<MODE>")])
6424 ;; -------------------------------------------------------------------------------
6425 ;; ---- Predicated floating-point ternary operations
6426 ;; -------------------------------------------------------------------------------
6427 ;; Includes:
6428 ;; - 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions
6429 ;; -------------------------------------------------------------------------------
6431 (define_expand "@pred_mul_<optab><mode>"
6432 [(set (match_operand:V_VLSF 0 "register_operand")
6433 (if_then_else:V_VLSF
6434 (unspec:<VM>
6435 [(match_operand:<VM> 1 "vector_mask_operand")
6436 (match_operand 6 "vector_length_operand")
6437 (match_operand 7 "const_int_operand")
6438 (match_operand 8 "const_int_operand")
6439 (match_operand 9 "const_int_operand")
6440 (match_operand 10 "const_int_operand")
6441 (reg:SI VL_REGNUM)
6442 (reg:SI VTYPE_REGNUM)
6443 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6444 (plus_minus:V_VLSF
6445 (mult:V_VLSF
6446 (match_operand:V_VLSF 2 "register_operand")
6447 (match_operand:V_VLSF 3 "register_operand"))
6448 (match_operand:V_VLSF 4 "register_operand"))
6449 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6450 "TARGET_VECTOR"
6451 {
6452 riscv_vector::prepare_ternary_operands (operands);
6453 })
6455 (define_insn "*pred_mul_<optab><mode>_undef"
6456 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6457 (if_then_else:V_VLSF
6458 (unspec:<VM>
6459 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6460 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6461 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6462 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6463 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6464 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6465 (reg:SI VL_REGNUM)
6466 (reg:SI VTYPE_REGNUM)
6467 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6468 (plus_minus:V_VLSF
6469 (mult:V_VLSF
6470 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6471 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr"))
6472 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6473 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6474 "TARGET_VECTOR"
6475 "@
6476 vf<madd_msub>.vv\t%0,%4,%5%p1
6477 vf<macc_msac>.vv\t%0,%3,%4%p1
6478 vmv.v.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1
6479 vf<madd_msub>.vv\t%0,%4,%5%p1
6480 vf<macc_msac>.vv\t%0,%3,%4%p1
6481 vmv.v.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1"
6482 [(set_attr "type" "vfmuladd")
6483 (set_attr "mode" "<MODE>")
6484 (set (attr "frm_mode")
6485 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6487 (define_insn "*pred_<madd_msub><mode>"
6488 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6489 (if_then_else:V_VLSF
6490 (unspec:<VM>
6491 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6492 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6493 (match_operand 6 "const_int_operand" " i, i, i, i")
6494 (match_operand 7 "const_int_operand" " i, i, i, i")
6495 (match_operand 8 "const_int_operand" " i, i, i, i")
6496 (match_operand 9 "const_int_operand" " i, i, i, i")
6497 (reg:SI VL_REGNUM)
6498 (reg:SI VTYPE_REGNUM)
6499 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6500 (plus_minus:V_VLSF
6501 (mult:V_VLSF
6502 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6503 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6504 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6505 (match_dup 2)))]
6506 "TARGET_VECTOR"
6507 "@
6508 vf<madd_msub>.vv\t%0,%3,%4%p1
6509 vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
6510 vf<madd_msub>.vv\t%0,%3,%4%p1
6511 vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1"
6512 [(set_attr "type" "vfmuladd")
6513 (set_attr "mode" "<MODE>")
6514 (set_attr "merge_op_idx" "4")
6515 (set_attr "vl_op_idx" "5")
6516 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6517 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6518 (set (attr "avl_type_idx") (const_int 8))
6519 (set (attr "frm_mode")
6520 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6522 (define_insn "*pred_<macc_msac><mode>"
6523 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6524 (if_then_else:V_VLSF
6525 (unspec:<VM>
6526 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6527 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6528 (match_operand 6 "const_int_operand" " i, i, i, i")
6529 (match_operand 7 "const_int_operand" " i, i, i, i")
6530 (match_operand 8 "const_int_operand" " i, i, i, i")
6531 (match_operand 9 "const_int_operand" " i, i, i, i")
6532 (reg:SI VL_REGNUM)
6533 (reg:SI VTYPE_REGNUM)
6534 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6535 (plus_minus:V_VLSF
6536 (mult:V_VLSF
6537 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6538 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6539 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6540 (match_dup 4)))]
6541 "TARGET_VECTOR"
6542 "@
6543 vf<macc_msac>.vv\t%0,%2,%3%p1
6544 vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
6545 vf<macc_msac>.vv\t%0,%2,%3%p1
6546 vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1"
6547 [(set_attr "type" "vfmuladd")
6548 (set_attr "mode" "<MODE>")
6549 (set_attr "merge_op_idx" "2")
6550 (set_attr "vl_op_idx" "5")
6551 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6552 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6553 (set (attr "avl_type_idx") (const_int 8))
6554 (set (attr "frm_mode")
6555 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6557 (define_expand "@pred_mul_<optab><mode>_scalar"
6558 [(set (match_operand:V_VLSF 0 "register_operand")
6559 (if_then_else:V_VLSF
6560 (unspec:<VM>
6561 [(match_operand:<VM> 1 "vector_mask_operand")
6562 (match_operand 6 "vector_length_operand")
6563 (match_operand 7 "const_int_operand")
6564 (match_operand 8 "const_int_operand")
6565 (match_operand 9 "const_int_operand")
6566 (match_operand 10 "const_int_operand")
6567 (reg:SI VL_REGNUM)
6568 (reg:SI VTYPE_REGNUM)
6569 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6570 (plus_minus:V_VLSF
6571 (mult:V_VLSF
6572 (vec_duplicate:V_VLSF
6573 (match_operand:<VEL> 2 "register_operand"))
6574 (match_operand:V_VLSF 3 "register_operand"))
6575 (match_operand:V_VLSF 4 "register_operand"))
6576 (match_operand:V_VLSF 5 "register_operand")))]
6577 "TARGET_VECTOR"
6578 {})
6580 (define_insn "*pred_<madd_msub><mode>_scalar"
6581 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6582 (if_then_else:V_VLSF
6583 (unspec:<VM>
6584 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6585 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6586 (match_operand 6 "const_int_operand" " i, i, i, i")
6587 (match_operand 7 "const_int_operand" " i, i, i, i")
6588 (match_operand 8 "const_int_operand" " i, i, i, i")
6589 (match_operand 9 "const_int_operand" " i, i, i, i")
6590 (reg:SI VL_REGNUM)
6591 (reg:SI VTYPE_REGNUM)
6592 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6593 (plus_minus:V_VLSF
6594 (mult:V_VLSF
6595 (vec_duplicate:V_VLSF
6596 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6597 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr"))
6598 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6599 (match_dup 3)))]
6600 "TARGET_VECTOR"
6601 "@
6602 vf<madd_msub>.vf\t%0,%2,%4%p1
6603 vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
6604 vf<madd_msub>.vf\t%0,%2,%4%p1
6605 vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1"
6606 [(set_attr "type" "vfmuladd")
6607 (set_attr "mode" "<MODE>")
6608 (set_attr "merge_op_idx" "4")
6609 (set_attr "vl_op_idx" "5")
6610 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6611 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6612 (set (attr "avl_type_idx") (const_int 8))
6613 (set (attr "frm_mode")
6614 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6616 (define_insn "*pred_<macc_msac><mode>_scalar"
6617 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6618 (if_then_else:V_VLSF
6619 (unspec:<VM>
6620 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6621 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6622 (match_operand 6 "const_int_operand" " i, i, i, i")
6623 (match_operand 7 "const_int_operand" " i, i, i, i")
6624 (match_operand 8 "const_int_operand" " i, i, i, i")
6625 (match_operand 9 "const_int_operand" " i, i, i, i")
6626 (reg:SI VL_REGNUM)
6627 (reg:SI VTYPE_REGNUM)
6628 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6629 (plus_minus:V_VLSF
6630 (mult:V_VLSF
6631 (vec_duplicate:V_VLSF
6632 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6633 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6634 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6635 (match_dup 4)))]
6636 "TARGET_VECTOR"
6637 "@
6638 vf<macc_msac>.vf\t%0,%2,%3%p1
6639 vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
6640 vf<macc_msac>.vf\t%0,%2,%3%p1
6641 vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1"
6642 [(set_attr "type" "vfmuladd")
6643 (set_attr "mode" "<MODE>")
6644 (set_attr "merge_op_idx" "2")
6645 (set_attr "vl_op_idx" "5")
6646 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6647 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6648 (set (attr "avl_type_idx") (const_int 8))
6649 (set (attr "frm_mode")
6650 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6652 (define_expand "@pred_mul_neg_<optab><mode>"
6653 [(set (match_operand:V_VLSF 0 "register_operand")
6654 (if_then_else:V_VLSF
6655 (unspec:<VM>
6656 [(match_operand:<VM> 1 "vector_mask_operand")
6657 (match_operand 6 "vector_length_operand")
6658 (match_operand 7 "const_int_operand")
6659 (match_operand 8 "const_int_operand")
6660 (match_operand 9 "const_int_operand")
6661 (match_operand 10 "const_int_operand")
6662 (reg:SI VL_REGNUM)
6663 (reg:SI VTYPE_REGNUM)
6664 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6665 (plus_minus:V_VLSF
6666 (neg:V_VLSF
6667 (mult:V_VLSF
6668 (match_operand:V_VLSF 2 "register_operand")
6669 (match_operand:V_VLSF 3 "register_operand")))
6670 (match_operand:V_VLSF 4 "register_operand"))
6671 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6672 "TARGET_VECTOR"
6673 {
6674 riscv_vector::prepare_ternary_operands (operands);
6675 })
6677 (define_insn "*pred_mul_neg_<optab><mode>_undef"
6678 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6679 (if_then_else:V_VLSF
6680 (unspec:<VM>
6681 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6682 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6683 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6684 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6685 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6686 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6687 (reg:SI VL_REGNUM)
6688 (reg:SI VTYPE_REGNUM)
6689 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6690 (plus_minus:V_VLSF
6691 (neg:V_VLSF
6692 (mult:V_VLSF
6693 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6694 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr")))
6695 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6696 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6697 "TARGET_VECTOR"
6698 "@
6699 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6700 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6701 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6702 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6703 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6704 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1"
6705 [(set_attr "type" "vfmuladd")
6706 (set_attr "mode" "<MODE>")
6707 (set (attr "frm_mode")
6708 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6710 (define_insn "*pred_<nmsub_nmadd><mode>"
6711 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6712 (if_then_else:V_VLSF
6713 (unspec:<VM>
6714 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6715 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6716 (match_operand 6 "const_int_operand" " i, i, i, i")
6717 (match_operand 7 "const_int_operand" " i, i, i, i")
6718 (match_operand 8 "const_int_operand" " i, i, i, i")
6719 (match_operand 9 "const_int_operand" " i, i, i, i")
6720 (reg:SI VL_REGNUM)
6721 (reg:SI VTYPE_REGNUM)
6722 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6723 (plus_minus:V_VLSF
6724 (neg:V_VLSF
6725 (mult:V_VLSF
6726 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6727 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6728 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6729 (match_dup 2)))]
6730 "TARGET_VECTOR"
6731 "@
6732 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6733 vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6734 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6735 vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
6736 [(set_attr "type" "vfmuladd")
6737 (set_attr "mode" "<MODE>")
6738 (set_attr "merge_op_idx" "4")
6739 (set_attr "vl_op_idx" "5")
6740 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6741 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6742 (set (attr "avl_type_idx") (const_int 8))
6743 (set (attr "frm_mode")
6744 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6746 (define_insn "*pred_<nmsac_nmacc><mode>"
6747 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6748 (if_then_else:V_VLSF
6749 (unspec:<VM>
6750 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6751 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6752 (match_operand 6 "const_int_operand" " i, i, i, i")
6753 (match_operand 7 "const_int_operand" " i, i, i, i")
6754 (match_operand 8 "const_int_operand" " i, i, i, i")
6755 (match_operand 9 "const_int_operand" " i, i, i, i")
6756 (reg:SI VL_REGNUM)
6757 (reg:SI VTYPE_REGNUM)
6758 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6759 (plus_minus:V_VLSF
6760 (neg:V_VLSF
6761 (mult:V_VLSF
6762 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6763 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6764 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6765 (match_dup 4)))]
6766 "TARGET_VECTOR"
6767 "@
6768 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6769 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6770 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6771 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
6772 [(set_attr "type" "vfmuladd")
6773 (set_attr "mode" "<MODE>")
6774 (set_attr "merge_op_idx" "2")
6775 (set_attr "vl_op_idx" "5")
6776 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6777 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6778 (set (attr "avl_type_idx") (const_int 8))
6779 (set (attr "frm_mode")
6780 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6782 (define_expand "@pred_mul_neg_<optab><mode>_scalar"
6783 [(set (match_operand:V_VLSF 0 "register_operand")
6784 (if_then_else:V_VLSF
6785 (unspec:<VM>
6786 [(match_operand:<VM> 1 "vector_mask_operand")
6787 (match_operand 6 "vector_length_operand")
6788 (match_operand 7 "const_int_operand")
6789 (match_operand 8 "const_int_operand")
6790 (match_operand 9 "const_int_operand")
6791 (match_operand 10 "const_int_operand")
6792 (reg:SI VL_REGNUM)
6793 (reg:SI VTYPE_REGNUM)
6794 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6795 (plus_minus:V_VLSF
6796 (neg:V_VLSF
6797 (mult:V_VLSF
6798 (vec_duplicate:V_VLSF
6799 (match_operand:<VEL> 2 "register_operand"))
6800 (match_operand:V_VLSF 3 "register_operand")))
6801 (match_operand:V_VLSF 4 "register_operand"))
6802 (match_operand:V_VLSF 5 "register_operand")))]
6803 "TARGET_VECTOR"
6804 {})
6806 (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
6807 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6808 (if_then_else:V_VLSF
6809 (unspec:<VM>
6810 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6811 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6812 (match_operand 6 "const_int_operand" " i, i, i, i")
6813 (match_operand 7 "const_int_operand" " i, i, i, i")
6814 (match_operand 8 "const_int_operand" " i, i, i, i")
6815 (match_operand 9 "const_int_operand" " i, i, i, i")
6816 (reg:SI VL_REGNUM)
6817 (reg:SI VTYPE_REGNUM)
6818 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6819 (plus_minus:V_VLSF
6820 (neg:V_VLSF
6821 (mult:V_VLSF
6822 (vec_duplicate:V_VLSF
6823 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6824 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr")))
6825 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6826 (match_dup 3)))]
6827 "TARGET_VECTOR"
6828 "@
6829 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6830 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6831 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6832 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
6833 [(set_attr "type" "vfmuladd")
6834 (set_attr "mode" "<MODE>")
6835 (set_attr "merge_op_idx" "4")
6836 (set_attr "vl_op_idx" "5")
6837 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6838 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6839 (set (attr "avl_type_idx") (const_int 8))
6840 (set (attr "frm_mode")
6841 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6843 (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
6844 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6845 (if_then_else:V_VLSF
6846 (unspec:<VM>
6847 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6848 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6849 (match_operand 6 "const_int_operand" " i, i, i, i")
6850 (match_operand 7 "const_int_operand" " i, i, i, i")
6851 (match_operand 8 "const_int_operand" " i, i, i, i")
6852 (match_operand 9 "const_int_operand" " i, i, i, i")
6853 (reg:SI VL_REGNUM)
6854 (reg:SI VTYPE_REGNUM)
6855 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6856 (plus_minus:V_VLSF
6857 (neg:V_VLSF
6858 (mult:V_VLSF
6859 (vec_duplicate:V_VLSF
6860 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6861 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6862 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6863 (match_dup 4)))]
6864 "TARGET_VECTOR"
6865 "@
6866 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6867 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6868 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6869 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
6870 [(set_attr "type" "vfmuladd")
6871 (set_attr "mode" "<MODE>")
6872 (set_attr "merge_op_idx" "2")
6873 (set_attr "vl_op_idx" "5")
6874 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6875 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6876 (set (attr "avl_type_idx") (const_int 8))
6877 (set (attr "frm_mode")
6878 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6880 ;; -------------------------------------------------------------------------------
6881 ;; ---- Predicated floating-point unary operations
6882 ;; -------------------------------------------------------------------------------
6883 ;; Includes:
6884 ;; - 13.8 Vector Floating-Point Square-Root Instruction
6885 ;; - 13.9 Vector Floating-Point Reciprocal Square-Root Estimate Instruction
6886 ;; - 13.10 Vector Floating-Point Reciprocal Estimate Instruction
6887 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions (vfneg.v/vfabs.v)
6888 ;; - 13.14 Vector Floating-Point Classify Instruction
6889 ;; -------------------------------------------------------------------------------
6891 (define_insn "@pred_<optab><mode>"
6892 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6893 (if_then_else:V_VLSF
6894 (unspec:<VM>
6895 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6896 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6897 (match_operand 5 "const_int_operand" " i, i, i, i")
6898 (match_operand 6 "const_int_operand" " i, i, i, i")
6899 (match_operand 7 "const_int_operand" " i, i, i, i")
6900 (match_operand 8 "const_int_operand" " i, i, i, i")
6901 (reg:SI VL_REGNUM)
6902 (reg:SI VTYPE_REGNUM)
6903 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6904 (any_float_unop:V_VLSF
6905 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6906 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6907 "TARGET_VECTOR"
6908 "vf<insn>.v\t%0,%3%p1"
6909 [(set_attr "type" "<float_insn_type>")
6910 (set_attr "mode" "<MODE>")
6911 (set_attr "vl_op_idx" "4")
6912 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6913 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6914 (set (attr "avl_type_idx") (const_int 7))
6915 (set (attr "frm_mode")
6916 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6918 (define_insn "@pred_<optab><mode>"
6919 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6920 (if_then_else:V_VLSF
6921 (unspec:<VM>
6922 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6923 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6924 (match_operand 5 "const_int_operand" " i, i, i, i")
6925 (match_operand 6 "const_int_operand" " i, i, i, i")
6926 (match_operand 7 "const_int_operand" " i, i, i, i")
6927 (reg:SI VL_REGNUM)
6928 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6929 (any_float_unop_nofrm:V_VLSF
6930 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6931 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6932 "TARGET_VECTOR"
6933 "vf<insn>.v\t%0,%3%p1"
6934 [(set_attr "type" "<float_insn_type>")
6935 (set_attr "mode" "<MODE>")
6936 (set_attr "vl_op_idx" "4")
6937 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6938 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6939 (set (attr "avl_type_idx") (const_int 7))])
6941 (define_insn "@pred_<misc_op><mode>"
6942 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6943 (if_then_else:VF
6944 (unspec:<VM>
6945 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6946 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6947 (match_operand 5 "const_int_operand" " i, i, i, i")
6948 (match_operand 6 "const_int_operand" " i, i, i, i")
6949 (match_operand 7 "const_int_operand" " i, i, i, i")
6950 (reg:SI VL_REGNUM)
6951 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6952 (unspec:VF
6953 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
6954 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6955 "TARGET_VECTOR"
6956 "vf<misc_op>.v\t%0,%3%p1"
6957 [(set_attr "type" "<float_insn_type>")
6958 (set_attr "mode" "<MODE>")])
6960 (define_insn "@pred_<misc_frm_op><mode>"
6961 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6962 (if_then_else:VF
6963 (unspec:<VM>
6964 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6965 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6966 (match_operand 5 "const_int_operand" " i, i, i, i")
6967 (match_operand 6 "const_int_operand" " i, i, i, i")
6968 (match_operand 7 "const_int_operand" " i, i, i, i")
6969 (match_operand 8 "const_int_operand" " i, i, i, i")
6970 (reg:SI VL_REGNUM)
6971 (reg:SI VTYPE_REGNUM)
6972 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6973 (unspec:VF
6974 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM)
6975 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6976 "TARGET_VECTOR"
6977 "vf<misc_frm_op>.v\t%0,%3%p1"
6978 [(set_attr "type" "<float_frm_insn_type>")
6979 (set_attr "mode" "<MODE>")
6980 (set (attr "frm_mode")
6981 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6983 (define_insn "@pred_class<mode>"
6984 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
6985 (if_then_else:<VCONVERT>
6986 (unspec:<VM>
6987 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6988 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6989 (match_operand 5 "const_int_operand" " i, i, i, i")
6990 (match_operand 6 "const_int_operand" " i, i, i, i")
6991 (match_operand 7 "const_int_operand" " i, i, i, i")
6992 (reg:SI VL_REGNUM)
6993 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6994 (unspec:<VCONVERT>
6995 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
6996 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6997 "TARGET_VECTOR"
6998 "vfclass.v\t%0,%3%p1"
6999 [(set_attr "type" "vfclass")
7000 (set_attr "mode" "<MODE>")])
7002 ;; -------------------------------------------------------------------------------
7003 ;; ---- Predicated floating-point widen binary operations
7004 ;; -------------------------------------------------------------------------------
7005 ;; Includes:
7006 ;; - 13.3 Vector Widening Floating-Point Add/Subtract Instructions
7007 ;; - 13.5 Vector Widening Floating-Point Multiply
7008 ;; -------------------------------------------------------------------------------
7010 ;; Vector Widening Add/Subtract/Multiply.
7011 (define_insn "@pred_dual_widen_<optab><mode>"
7012 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7013 (if_then_else:VWEXTF
7014 (unspec:<VM>
7015 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7016 (match_operand 5 "vector_length_operand" " rK, rK")
7017 (match_operand 6 "const_int_operand" " i, i")
7018 (match_operand 7 "const_int_operand" " i, i")
7019 (match_operand 8 "const_int_operand" " i, i")
7020 (match_operand 9 "const_int_operand" " i, i")
7021 (reg:SI VL_REGNUM)
7022 (reg:SI VTYPE_REGNUM)
7023 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7024 (any_widen_binop:VWEXTF
7025 (float_extend:VWEXTF
7026 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7027 (float_extend:VWEXTF
7028 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7029 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7030 "TARGET_VECTOR"
7031 "vfw<insn>.vv\t%0,%3,%4%p1"
7032 [(set_attr "type" "vf<widen_binop_insn_type>")
7033 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7034 (set (attr "frm_mode")
7035 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7037 (define_insn "@pred_dual_widen_<optab><mode>_scalar"
7038 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7039 (if_then_else:VWEXTF
7040 (unspec:<VM>
7041 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7042 (match_operand 5 "vector_length_operand" " rK, rK")
7043 (match_operand 6 "const_int_operand" " i, i")
7044 (match_operand 7 "const_int_operand" " i, i")
7045 (match_operand 8 "const_int_operand" " i, i")
7046 (match_operand 9 "const_int_operand" " i, i")
7047 (reg:SI VL_REGNUM)
7048 (reg:SI VTYPE_REGNUM)
7049 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7050 (any_widen_binop:VWEXTF
7051 (float_extend:VWEXTF
7052 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7053 (float_extend:VWEXTF
7054 (vec_duplicate:<V_DOUBLE_TRUNC>
7055 (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
7056 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7057 "TARGET_VECTOR"
7058 "vfw<insn>.vf\t%0,%3,%4%p1"
7059 [(set_attr "type" "vf<widen_binop_insn_type>")
7060 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7061 (set (attr "frm_mode")
7062 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7064 (define_insn "@pred_single_widen_add<mode>"
7065 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7066 (if_then_else:VWEXTF
7067 (unspec:<VM>
7068 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7069 (match_operand 5 "vector_length_operand" " rK, rK")
7070 (match_operand 6 "const_int_operand" " i, i")
7071 (match_operand 7 "const_int_operand" " i, i")
7072 (match_operand 8 "const_int_operand" " i, i")
7073 (match_operand 9 "const_int_operand" " i, i")
7074 (reg:SI VL_REGNUM)
7075 (reg:SI VTYPE_REGNUM)
7076 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7077 (plus:VWEXTF
7078 (float_extend:VWEXTF
7079 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
7080 (match_operand:VWEXTF 3 "register_operand" " vr, vr"))
7081 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7082 "TARGET_VECTOR"
7083 "vfwadd.wv\t%0,%3,%4%p1"
7084 [(set_attr "type" "vfwalu")
7085 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7086 (set (attr "frm_mode")
7087 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7089 (define_insn "@pred_single_widen_sub<mode>"
7090 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7091 (if_then_else:VWEXTF
7092 (unspec:<VM>
7093 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7094 (match_operand 5 "vector_length_operand" " rK, rK")
7095 (match_operand 6 "const_int_operand" " i, i")
7096 (match_operand 7 "const_int_operand" " i, i")
7097 (match_operand 8 "const_int_operand" " i, i")
7098 (match_operand 9 "const_int_operand" " i, i")
7099 (reg:SI VL_REGNUM)
7100 (reg:SI VTYPE_REGNUM)
7101 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7102 (minus:VWEXTF
7103 (match_operand:VWEXTF 3 "register_operand" " vr, vr")
7104 (float_extend:VWEXTF
7105 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7106 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7107 "TARGET_VECTOR"
7108 "vfwsub.wv\t%0,%3,%4%p1"
7109 [(set_attr "type" "vfwalu")
7110 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7111 (set (attr "frm_mode")
7112 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7114 (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
7115 [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr")
7116 (if_then_else:VWEXTF
7117 (unspec:<VM>
7118 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7119 (match_operand 5 "vector_length_operand" " rK, rK")
7120 (match_operand 6 "const_int_operand" " i, i")
7121 (match_operand 7 "const_int_operand" " i, i")
7122 (match_operand 8 "const_int_operand" " i, i")
7123 (match_operand 9 "const_int_operand" " i, i")
7124 (reg:SI VL_REGNUM)
7125 (reg:SI VTYPE_REGNUM)
7126 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7127 (plus_minus:VWEXTF
7128 (match_operand:VWEXTF 3 "register_operand" " vr, vr")
7129 (float_extend:VWEXTF
7130 (vec_duplicate:<V_DOUBLE_TRUNC>
7131 (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
7132 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7133 "TARGET_VECTOR"
7134 "vfw<insn>.wf\t%0,%3,%4%p1"
7135 [(set_attr "type" "vf<widen_binop_insn_type>")
7136 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7137 (set (attr "frm_mode")
7138 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7140 ;; -------------------------------------------------------------------------------
7141 ;; ---- Predicated widen floating-point ternary operations
7142 ;; -------------------------------------------------------------------------------
7143 ;; Includes:
7144 ;; - 13.7 Vector Widening Floating-Point Fused Multiply-Add Instructions
7145 ;; -------------------------------------------------------------------------------
7147 (define_insn "@pred_widen_mul_<optab><mode>"
7148 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7149 (if_then_else:VWEXTF
7150 (unspec:<VM>
7151 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7152 (match_operand 5 "vector_length_operand" " rK")
7153 (match_operand 6 "const_int_operand" " i")
7154 (match_operand 7 "const_int_operand" " i")
7155 (match_operand 8 "const_int_operand" " i")
7156 (match_operand 9 "const_int_operand" " i")
7157 (reg:SI VL_REGNUM)
7158 (reg:SI VTYPE_REGNUM)
7159 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7160 (plus_minus:VWEXTF
7161 (mult:VWEXTF
7162 (float_extend:VWEXTF
7163 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7164 (float_extend:VWEXTF
7165 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7166 (match_operand:VWEXTF 2 "register_operand" " 0"))
7167 (match_dup 2)))]
7168 "TARGET_VECTOR"
7169 "vfw<macc_msac>.vv\t%0,%3,%4%p1"
7170 [(set_attr "type" "vfwmuladd")
7171 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7172 (set (attr "frm_mode")
7173 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7175 (define_insn "@pred_widen_mul_<optab><mode>_scalar"
7176 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7177 (if_then_else:VWEXTF
7178 (unspec:<VM>
7179 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7180 (match_operand 5 "vector_length_operand" " rK")
7181 (match_operand 6 "const_int_operand" " i")
7182 (match_operand 7 "const_int_operand" " i")
7183 (match_operand 8 "const_int_operand" " i")
7184 (match_operand 9 "const_int_operand" " i")
7185 (reg:SI VL_REGNUM)
7186 (reg:SI VTYPE_REGNUM)
7187 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7188 (plus_minus:VWEXTF
7189 (mult:VWEXTF
7190 (float_extend:VWEXTF
7191 (vec_duplicate:<V_DOUBLE_TRUNC>
7192 (match_operand:<VSUBEL> 3 "register_operand" " f")))
7193 (float_extend:VWEXTF
7194 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7195 (match_operand:VWEXTF 2 "register_operand" " 0"))
7196 (match_dup 2)))]
7197 "TARGET_VECTOR"
7198 "vfw<macc_msac>.vf\t%0,%3,%4%p1"
7199 [(set_attr "type" "vfwmuladd")
7200 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7201 (set (attr "frm_mode")
7202 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7204 (define_insn "@pred_widen_mul_neg_<optab><mode>"
7205 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7206 (if_then_else:VWEXTF
7207 (unspec:<VM>
7208 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7209 (match_operand 5 "vector_length_operand" " rK")
7210 (match_operand 6 "const_int_operand" " i")
7211 (match_operand 7 "const_int_operand" " i")
7212 (match_operand 8 "const_int_operand" " i")
7213 (match_operand 9 "const_int_operand" " i")
7214 (reg:SI VL_REGNUM)
7215 (reg:SI VTYPE_REGNUM)
7216 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7217 (plus_minus:VWEXTF
7218 (neg:VWEXTF
7219 (mult:VWEXTF
7220 (float_extend:VWEXTF
7221 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7222 (float_extend:VWEXTF
7223 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7224 (match_operand:VWEXTF 2 "register_operand" " 0"))
7225 (match_dup 2)))]
7226 "TARGET_VECTOR"
7227 "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
7228 [(set_attr "type" "vfwmuladd")
7229 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7230 (set (attr "frm_mode")
7231 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7233 (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
7234 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7235 (if_then_else:VWEXTF
7236 (unspec:<VM>
7237 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7238 (match_operand 5 "vector_length_operand" " rK")
7239 (match_operand 6 "const_int_operand" " i")
7240 (match_operand 7 "const_int_operand" " i")
7241 (match_operand 8 "const_int_operand" " i")
7242 (match_operand 9 "const_int_operand" " i")
7243 (reg:SI VL_REGNUM)
7244 (reg:SI VTYPE_REGNUM)
7245 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7246 (plus_minus:VWEXTF
7247 (neg:VWEXTF
7248 (mult:VWEXTF
7249 (float_extend:VWEXTF
7250 (vec_duplicate:<V_DOUBLE_TRUNC>
7251 (match_operand:<VSUBEL> 3 "register_operand" " f")))
7252 (float_extend:VWEXTF
7253 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7254 (match_operand:VWEXTF 2 "register_operand" " 0"))
7255 (match_dup 2)))]
7256 "TARGET_VECTOR"
7257 "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
7258 [(set_attr "type" "vfwmuladd")
7259 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7260 (set (attr "frm_mode")
7261 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7263 ;; -------------------------------------------------------------------------------
7264 ;; ---- Predicated floating-point comparison operations
7265 ;; -------------------------------------------------------------------------------
7266 ;; Includes:
7267 ;; - 13.13 Vector Floating-Point Compare Instructions
7268 ;; -------------------------------------------------------------------------------
7270 (define_expand "@pred_cmp<mode>"
7271 [(set (match_operand:<VM> 0 "register_operand")
7272 (if_then_else:<VM>
7273 (unspec:<VM>
7274 [(match_operand:<VM> 1 "vector_mask_operand")
7275 (match_operand 6 "vector_length_operand")
7276 (match_operand 7 "const_int_operand")
7277 (match_operand 8 "const_int_operand")
7278 (reg:SI VL_REGNUM)
7279 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7280 (match_operator:<VM> 3 "signed_order_operator"
7281 [(match_operand:V_VLSF 4 "register_operand")
7282 (match_operand:V_VLSF 5 "register_operand")])
7283 (match_operand:<VM> 2 "vector_merge_operand")))]
7284 "TARGET_VECTOR"
7285 {})
7287 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7288 (define_insn "*pred_cmp<mode>"
7289 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7290 (if_then_else:<VM>
7291 (unspec:<VM>
7292 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7293 (match_operand 6 "vector_length_operand" " rK, rK")
7294 (match_operand 7 "const_int_operand" " i, i")
7295 (match_operand 8 "const_int_operand" " i, i")
7296 (reg:SI VL_REGNUM)
7297 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7298 (match_operator:<VM> 3 "signed_order_operator"
7299 [(match_operand:V_VLSF 4 "register_operand" " vr, vr")
7300 (match_operand:V_VLSF 5 "register_operand" " vr, vr")])
7301 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7302 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7303 "vmf%B3.vv\t%0,%4,%5%p1"
7304 [(set_attr "type" "vfcmp")
7305 (set_attr "mode" "<MODE>")])
7307 (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
7308 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7309 (if_then_else:<VM>
7310 (unspec:<VM>
7311 [(match_operand:<VM> 1 "register_operand" " 0")
7312 (match_operand 5 "vector_length_operand" " rK")
7313 (match_operand 6 "const_int_operand" " i")
7314 (match_operand 7 "const_int_operand" " i")
7315 (reg:SI VL_REGNUM)
7316 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7317 (match_operator:<VM> 2 "signed_order_operator"
7318 [(match_operand:V_VLSF 3 "register_operand" " vr")
7319 (match_operand:V_VLSF 4 "register_operand" " vr")])
7320 (match_dup 1)))]
7321 "TARGET_VECTOR"
7322 "vmf%B2.vv\t%0,%3,%4,v0.t"
7323 [(set_attr "type" "vfcmp")
7324 (set_attr "mode" "<MODE>")
7325 (set_attr "merge_op_idx" "1")
7326 (set_attr "vl_op_idx" "5")
7327 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7328 (set (attr "avl_type_idx") (const_int 7))])
7330 ;; We use early-clobber for source LMUL > dest LMUL.
7331 (define_insn "*pred_cmp<mode>_narrow"
7332 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
7333 (if_then_else:<VM>
7334 (unspec:<VM>
7335 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7336 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
7337 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7338 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7339 (reg:SI VL_REGNUM)
7340 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7341 (match_operator:<VM> 3 "signed_order_operator"
7342 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
7343 (match_operand:V_VLSF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
7344 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
7345 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7346 "vmf%B3.vv\t%0,%4,%5%p1"
7347 [(set_attr "type" "vfcmp")
7348 (set_attr "mode" "<MODE>")])
7350 (define_expand "@pred_cmp<mode>_scalar"
7351 [(set (match_operand:<VM> 0 "register_operand")
7352 (if_then_else:<VM>
7353 (unspec:<VM>
7354 [(match_operand:<VM> 1 "vector_mask_operand")
7355 (match_operand 6 "vector_length_operand")
7356 (match_operand 7 "const_int_operand")
7357 (match_operand 8 "const_int_operand")
7358 (reg:SI VL_REGNUM)
7359 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7360 (match_operator:<VM> 3 "signed_order_operator"
7361 [(match_operand:V_VLSF 4 "register_operand")
7362 (vec_duplicate:V_VLSF
7363 (match_operand:<VEL> 5 "register_operand"))])
7364 (match_operand:<VM> 2 "vector_merge_operand")))]
7365 "TARGET_VECTOR"
7366 {})
7368 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
7369 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7370 (if_then_else:<VM>
7371 (unspec:<VM>
7372 [(match_operand:<VM> 1 "register_operand" " 0")
7373 (match_operand 5 "vector_length_operand" " rK")
7374 (match_operand 6 "const_int_operand" " i")
7375 (match_operand 7 "const_int_operand" " i")
7376 (reg:SI VL_REGNUM)
7377 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7378 (match_operator:<VM> 2 "signed_order_operator"
7379 [(match_operand:V_VLSF 3 "register_operand" " vr")
7380 (vec_duplicate:V_VLSF
7381 (match_operand:<VEL> 4 "register_operand" " f"))])
7382 (match_dup 1)))]
7383 "TARGET_VECTOR"
7384 "vmf%B2.vf\t%0,%3,%4,v0.t"
7385 [(set_attr "type" "vfcmp")
7386 (set_attr "mode" "<MODE>")
7387 (set_attr "merge_op_idx" "1")
7388 (set_attr "vl_op_idx" "5")
7389 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7390 (set (attr "avl_type_idx") (const_int 7))])
7392 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7393 (define_insn "*pred_cmp<mode>_scalar"
7394 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7395 (if_then_else:<VM>
7396 (unspec:<VM>
7397 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7398 (match_operand 6 "vector_length_operand" " rK, rK")
7399 (match_operand 7 "const_int_operand" " i, i")
7400 (match_operand 8 "const_int_operand" " i, i")
7401 (reg:SI VL_REGNUM)
7402 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7403 (match_operator:<VM> 3 "signed_order_operator"
7404 [(match_operand:V_VLSF 4 "register_operand" " vr, vr")
7405 (vec_duplicate:V_VLSF
7406 (match_operand:<VEL> 5 "register_operand" " f, f"))])
7407 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7408 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7409 "vmf%B3.vf\t%0,%4,%5%p1"
7410 [(set_attr "type" "vfcmp")
7411 (set_attr "mode" "<MODE>")])
7413 ;; We use early-clobber for source LMUL > dest LMUL.
7414 (define_insn "*pred_cmp<mode>_scalar_narrow"
7415 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7416 (if_then_else:<VM>
7417 (unspec:<VM>
7418 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7419 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7420 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7421 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7422 (reg:SI VL_REGNUM)
7423 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7424 (match_operator:<VM> 3 "signed_order_operator"
7425 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")
7426 (vec_duplicate:V_VLSF
7427 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
7428 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7429 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7430 "vmf%B3.vf\t%0,%4,%5%p1"
7431 [(set_attr "type" "vfcmp")
7432 (set_attr "mode" "<MODE>")])
7434 (define_expand "@pred_eqne<mode>_scalar"
7435 [(set (match_operand:<VM> 0 "register_operand")
7436 (if_then_else:<VM>
7437 (unspec:<VM>
7438 [(match_operand:<VM> 1 "vector_mask_operand")
7439 (match_operand 6 "vector_length_operand")
7440 (match_operand 7 "const_int_operand")
7441 (match_operand 8 "const_int_operand")
7442 (reg:SI VL_REGNUM)
7443 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7444 (match_operator:<VM> 3 "equality_operator"
7445 [(vec_duplicate:V_VLSF
7446 (match_operand:<VEL> 5 "register_operand"))
7447 (match_operand:V_VLSF 4 "register_operand")])
7448 (match_operand:<VM> 2 "vector_merge_operand")))]
7449 "TARGET_VECTOR"
7450 {})
7452 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
7453 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7454 (if_then_else:<VM>
7455 (unspec:<VM>
7456 [(match_operand:<VM> 1 "register_operand" " 0")
7457 (match_operand 5 "vector_length_operand" " rK")
7458 (match_operand 6 "const_int_operand" " i")
7459 (match_operand 7 "const_int_operand" " i")
7460 (reg:SI VL_REGNUM)
7461 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7462 (match_operator:<VM> 2 "equality_operator"
7463 [(vec_duplicate:V_VLSF
7464 (match_operand:<VEL> 4 "register_operand" " f"))
7465 (match_operand:V_VLSF 3 "register_operand" " vr")])
7466 (match_dup 1)))]
7467 "TARGET_VECTOR"
7468 "vmf%B2.vf\t%0,%3,%4,v0.t"
7469 [(set_attr "type" "vfcmp")
7470 (set_attr "mode" "<MODE>")
7471 (set_attr "merge_op_idx" "1")
7472 (set_attr "vl_op_idx" "5")
7473 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7474 (set (attr "avl_type_idx") (const_int 7))])
7476 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7477 (define_insn "*pred_eqne<mode>_scalar"
7478 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7479 (if_then_else:<VM>
7480 (unspec:<VM>
7481 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7482 (match_operand 6 "vector_length_operand" " rK, rK")
7483 (match_operand 7 "const_int_operand" " i, i")
7484 (match_operand 8 "const_int_operand" " i, i")
7485 (reg:SI VL_REGNUM)
7486 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7487 (match_operator:<VM> 3 "equality_operator"
7488 [(vec_duplicate:V_VLSF
7489 (match_operand:<VEL> 5 "register_operand" " f, f"))
7490 (match_operand:V_VLSF 4 "register_operand" " vr, vr")])
7491 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7492 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7493 "vmf%B3.vf\t%0,%4,%5%p1"
7494 [(set_attr "type" "vfcmp")
7495 (set_attr "mode" "<MODE>")])
7497 ;; We use early-clobber for source LMUL > dest LMUL.
7498 (define_insn "*pred_eqne<mode>_scalar_narrow"
7499 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7500 (if_then_else:<VM>
7501 (unspec:<VM>
7502 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7503 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7504 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7505 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7506 (reg:SI VL_REGNUM)
7507 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7508 (match_operator:<VM> 3 "equality_operator"
7509 [(vec_duplicate:V_VLSF
7510 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
7511 (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")])
7512 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7513 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7514 "vmf%B3.vf\t%0,%4,%5%p1"
7515 [(set_attr "type" "vfcmp")
7516 (set_attr "mode" "<MODE>")])
7518 ;; -------------------------------------------------------------------------------
7519 ;; ---- Predicated floating-point merge
7520 ;; -------------------------------------------------------------------------------
7521 ;; Includes:
7522 ;; - 13.15 Vector Floating-Point Merge Instruction
7523 ;; -------------------------------------------------------------------------------
7525 (define_insn "@pred_merge<mode>_scalar"
7526 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd")
7527 (if_then_else:V_VLSF
7528 (unspec:<VM>
7529 [(match_operand 5 "vector_length_operand" " rK,rK")
7530 (match_operand 6 "const_int_operand" " i, i")
7531 (match_operand 7 "const_int_operand" " i, i")
7532 (reg:SI VL_REGNUM)
7533 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7534 (vec_merge:V_VLSF
7535 (vec_duplicate:V_VLSF
7536 (match_operand:<VEL> 3 "register_operand" " f, f"))
7537 (match_operand:V_VLSF 2 "register_operand" " vr,vr")
7538 (match_operand:<VM> 4 "register_operand" " vm,vm"))
7539 (match_operand:V_VLSF 1 "vector_merge_operand" " vu, 0")))]
7540 "TARGET_VECTOR"
7541 "vfmerge.vfm\t%0,%2,%3,%4"
7542 [(set_attr "type" "vfmerge")
7543 (set_attr "mode" "<MODE>")])
7545 ;; -------------------------------------------------------------------------------
7546 ;; ---- Predicated floating-point conversions
7547 ;; -------------------------------------------------------------------------------
7548 ;; Includes:
7549 ;; - 13.17 Single-Width Floating-Point/Integer Type-Convert Instructions
7550 ;; -------------------------------------------------------------------------------
7552 (define_insn "@pred_fcvt_x<v_su>_f<mode>"
7553 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7554 (if_then_else:<VCONVERT>
7555 (unspec:<VM>
7556 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7557 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7558 (match_operand 5 "const_int_operand" " i, i, i, i")
7559 (match_operand 6 "const_int_operand" " i, i, i, i")
7560 (match_operand 7 "const_int_operand" " i, i, i, i")
7561 (match_operand 8 "const_int_operand" " i, i, i, i")
7562 (reg:SI VL_REGNUM)
7563 (reg:SI VTYPE_REGNUM)
7564 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7565 (unspec:<VCONVERT>
7566 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
7567 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7568 "TARGET_VECTOR"
7569 "vfcvt.x<v_su>.f.v\t%0,%3%p1"
7570 [(set_attr "type" "vfcvtftoi")
7571 (set_attr "mode" "<MODE>")
7572 (set (attr "frm_mode")
7573 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7575 (define_insn "@pred_<fix_cvt><mode>"
7576 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7577 (if_then_else:<VCONVERT>
7578 (unspec:<VM>
7579 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7580 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7581 (match_operand 5 "const_int_operand" " i, i, i, i")
7582 (match_operand 6 "const_int_operand" " i, i, i, i")
7583 (match_operand 7 "const_int_operand" " i, i, i, i")
7584 (reg:SI VL_REGNUM)
7585 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7586 (any_fix:<VCONVERT>
7587 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
7588 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7589 "TARGET_VECTOR"
7590 "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
7591 [(set_attr "type" "vfcvtftoi")
7592 (set_attr "mode" "<MODE>")])
7594 (define_insn "@pred_<float_cvt><mode>"
7595 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
7596 (if_then_else:V_VLSF
7597 (unspec:<VM>
7598 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7599 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7600 (match_operand 5 "const_int_operand" " i, i, i, i")
7601 (match_operand 6 "const_int_operand" " i, i, i, i")
7602 (match_operand 7 "const_int_operand" " i, i, i, i")
7603 (match_operand 8 "const_int_operand" " i, i, i, i")
7604 (reg:SI VL_REGNUM)
7605 (reg:SI VTYPE_REGNUM)
7606 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7607 (any_float:V_VLSF
7608 (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
7609 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7610 "TARGET_VECTOR"
7611 "vfcvt.f.x<u>.v\t%0,%3%p1"
7612 [(set_attr "type" "vfcvtitof")
7613 (set_attr "mode" "<MODE>")
7614 (set (attr "frm_mode")
7615 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7617 ;; -------------------------------------------------------------------------------
7618 ;; ---- Predicated floating-point widen conversions
7619 ;; -------------------------------------------------------------------------------
7620 ;; Includes:
7621 ;; - 13.18 Widening Floating-Point/Integer Type-Convert Instructions
7622 ;; -------------------------------------------------------------------------------
7624 (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
7625 [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
7626 (if_then_else:VWCONVERTI
7627 (unspec:<VM>
7628 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7629 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
7630 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
7631 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
7632 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
7633 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
7634 (reg:SI VL_REGNUM)
7635 (reg:SI VTYPE_REGNUM)
7636 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7637 (unspec:VWCONVERTI
7638 [(match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")] VFCVTS)
7639 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
7640 "TARGET_VECTOR"
7641 "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
7642 [(set_attr "type" "vfwcvtftoi")
7643 (set_attr "mode" "<VNCONVERT>")
7644 (set (attr "frm_mode")
7645 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7646 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
7648 (define_insn "@pred_widen_<fix_cvt><mode>"
7649 [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
7650 (if_then_else:VWCONVERTI
7651 (unspec:<VM>
7652 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7653 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
7654 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
7655 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
7656 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
7657 (reg:SI VL_REGNUM)
7658 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7659 (any_fix:VWCONVERTI
7660 (match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
7661 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
7662 "TARGET_VECTOR"
7663 "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
7664 [(set_attr "type" "vfwcvtftoi")
7665 (set_attr "mode" "<VNCONVERT>")
7666 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
7668 (define_insn "@pred_widen_<float_cvt><mode>"
7669 [(set (match_operand:V_VLSF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
7670 (if_then_else:V_VLSF
7671 (unspec:<VM>
7672 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7673 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
7674 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
7675 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
7676 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
7677 (reg:SI VL_REGNUM)
7678 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7679 (any_float:V_VLSF
7680 (match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
7681 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
7682 "TARGET_VECTOR"
7683 "vfwcvt.f.x<u>.v\t%0,%3%p1"
7684 [(set_attr "type" "vfwcvtitof")
7685 (set_attr "mode" "<VNCONVERT>")
7686 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
7688 (define_insn "@pred_extend<mode>"
7689 [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
7690 (if_then_else:VWEXTF_ZVFHMIN
7691 (unspec:<VM>
7692 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7693 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
7694 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
7695 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
7696 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
7697 (reg:SI VL_REGNUM)
7698 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7699 (float_extend:VWEXTF_ZVFHMIN
7700 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
7701 (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
7702 "TARGET_VECTOR"
7703 "vfwcvt.f.f.v\t%0,%3%p1"
7704 [(set_attr "type" "vfwcvtftof")
7705 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7706 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
7708 ;; -------------------------------------------------------------------------------
7709 ;; ---- Predicated floating-point narrow conversions
7710 ;; -------------------------------------------------------------------------------
7711 ;; Includes:
7712 ;; - 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
7713 ;; -------------------------------------------------------------------------------
7715 (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
7716 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7717 (if_then_else:<VNCONVERT>
7718 (unspec:<VM>
7719 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7720 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7721 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7722 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7723 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7724 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7725 (reg:SI VL_REGNUM)
7726 (reg:SI VTYPE_REGNUM)
7727 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7728 (unspec:<VNCONVERT>
7729 [(match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
7730 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7731 "TARGET_VECTOR"
7732 "vfncvt.x<v_su>.f.w\t%0,%3%p1"
7733 [(set_attr "type" "vfncvtftoi")
7734 (set_attr "mode" "<VNCONVERT>")
7735 (set (attr "frm_mode")
7736 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7738 (define_insn "@pred_narrow_<fix_cvt><mode>"
7739 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7740 (if_then_else:<VNCONVERT>
7741 (unspec:<VM>
7742 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7743 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7744 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7745 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7746 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7747 (reg:SI VL_REGNUM)
7748 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7749 (any_fix:<VNCONVERT>
7750 (match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7751 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7752 "TARGET_VECTOR"
7753 "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
7754 [(set_attr "type" "vfncvtftoi")
7755 (set_attr "mode" "<VNCONVERT>")])
7757 (define_insn "@pred_narrow_<float_cvt><mode>"
7758 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7759 (if_then_else:<VNCONVERT>
7760 (unspec:<VM>
7761 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7762 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7763 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7764 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7765 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7766 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7767 (reg:SI VL_REGNUM)
7768 (reg:SI VTYPE_REGNUM)
7769 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7770 (any_float:<VNCONVERT>
7771 (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7772 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7773 "TARGET_VECTOR"
7774 "vfncvt.f.x<u>.w\t%0,%3%p1"
7775 [(set_attr "type" "vfncvtitof")
7776 (set_attr "mode" "<VNCONVERT>")
7777 (set (attr "frm_mode")
7778 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7780 (define_insn "@pred_trunc<mode>"
7781 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7782 (if_then_else:<V_DOUBLE_TRUNC>
7783 (unspec:<VM>
7784 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7785 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7786 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7787 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7788 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7789 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7790 (reg:SI VL_REGNUM)
7791 (reg:SI VTYPE_REGNUM)
7792 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7793 (float_truncate:<V_DOUBLE_TRUNC>
7794 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7795 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7796 "TARGET_VECTOR"
7797 "vfncvt.f.f.w\t%0,%3%p1"
7798 [(set_attr "type" "vfncvtftof")
7799 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7800 (set (attr "frm_mode")
7801 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7803 (define_insn "@pred_rod_trunc<mode>"
7804 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7805 (if_then_else:<V_DOUBLE_TRUNC>
7806 (unspec:<VM>
7807 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7808 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7809 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7810 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7811 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7812 (reg:SI VL_REGNUM)
7813 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7814 (unspec:<V_DOUBLE_TRUNC>
7815 [(float_truncate:<V_DOUBLE_TRUNC>
7816 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
7817 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7818 "TARGET_VECTOR"
7819 "vfncvt.rod.f.f.w\t%0,%3%p1"
7820 [(set_attr "type" "vfncvtftof")
7821 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
7823 ;; -------------------------------------------------------------------------------
7824 ;; ---- Predicated reduction operations
7825 ;; -------------------------------------------------------------------------------
7826 ;; Includes:
7827 ;; - 14.1 Vector Single-Width Integer Reduction Instructions
7828 ;; - 14.2 Vector Widening Integer Reduction Instructions
7829 ;; - 14.3 Vector Single-Width Floating-Point Reduction Instructions
7830 ;; - 14.4 Vector Widening Floating-Point Reduction Instructions
7831 ;; -------------------------------------------------------------------------------
7833 ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
7834 (define_insn "@pred_<reduc_op><mode>"
7835 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7836 (unspec:<V_LMUL1>
7837 [(unspec:<VM>
7838 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7839 (match_operand 5 "vector_length_operand" " rK, rK")
7840 (match_operand 6 "const_int_operand" " i, i")
7841 (match_operand 7 "const_int_operand" " i, i")
7842 (reg:SI VL_REGNUM)
7843 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7844 (unspec:<V_LMUL1> [
7845 (match_operand:V_VLSI 3 "register_operand" " vr, vr")
7846 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7847 ] ANY_REDUC)
7848 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7849 "TARGET_VECTOR"
7850 "v<reduc_op>.vs\t%0,%3,%4%p1"
7851 [(set_attr "type" "vired")
7852 (set_attr "mode" "<MODE>")])
7854 ;; Integer Widen Reduction Sum (vwredsum[u].vs)
7855 (define_insn "@pred_<reduc_op><mode>"
7856 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
7857 (unspec:<V_EXT_LMUL1>
7858 [(unspec:<VM>
7859 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7860 (match_operand 5 "vector_length_operand" " rK, rK")
7861 (match_operand 6 "const_int_operand" " i, i")
7862 (match_operand 7 "const_int_operand" " i, i")
7863 (reg:SI VL_REGNUM)
7864 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7865 (unspec:<V_EXT_LMUL1> [
7866 (match_operand:VI_QHS 3 "register_operand" " vr, vr")
7867 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr0, vr0")
7868 ] ANY_WREDUC)
7869 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7870 "TARGET_VECTOR"
7871 "v<reduc_op>.vs\t%0,%3,%4%p1"
7872 [(set_attr "type" "viwred")
7873 (set_attr "mode" "<MODE>")])
7875 ;; Float Reduction (vfred(max|min).vs)
7876 (define_insn "@pred_<reduc_op><mode>"
7877 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7878 (unspec:<V_LMUL1>
7879 [(unspec:<VM>
7880 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7881 (match_operand 5 "vector_length_operand" " rK, rK")
7882 (match_operand 6 "const_int_operand" " i, i")
7883 (match_operand 7 "const_int_operand" " i, i")
7884 (reg:SI VL_REGNUM)
7885 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7886 (unspec:<V_LMUL1> [
7887 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7888 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7889 ] ANY_FREDUC)
7890 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7891 "TARGET_VECTOR"
7892 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7893 [(set_attr "type" "vfredu")
7894 (set_attr "mode" "<MODE>")])
7896 ;; Float Reduction Sum (vfred[ou]sum.vs)
7897 (define_insn "@pred_<reduc_op><mode>"
7898 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
7899 (unspec:<V_LMUL1>
7900 [(unspec:<VM>
7901 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7902 (match_operand 5 "vector_length_operand" " rK, rK")
7903 (match_operand 6 "const_int_operand" " i, i")
7904 (match_operand 7 "const_int_operand" " i, i")
7905 (match_operand 8 "const_int_operand" " i, i")
7906 (reg:SI VL_REGNUM)
7907 (reg:SI VTYPE_REGNUM)
7908 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7909 (unspec:<V_LMUL1> [
7910 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7911 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7912 ] ANY_FREDUC_SUM)
7913 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7914 "TARGET_VECTOR"
7915 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7916 [(set_attr "type" "vfred<order>")
7917 (set_attr "mode" "<MODE>")
7918 (set (attr "frm_mode")
7919 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7921 ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
7922 (define_insn "@pred_<reduc_op><mode>"
7923 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
7924 (unspec:<V_EXT_LMUL1>
7925 [(unspec:<VM>
7926 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7927 (match_operand 5 "vector_length_operand" " rK, rK")
7928 (match_operand 6 "const_int_operand" " i, i")
7929 (match_operand 7 "const_int_operand" " i, i")
7930 (match_operand 8 "const_int_operand" " i, i")
7931 (reg:SI VL_REGNUM)
7932 (reg:SI VTYPE_REGNUM)
7933 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7934 (unspec:<V_EXT_LMUL1> [
7935 (match_operand:VF_HS 3 "register_operand" " vr, vr")
7936 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr0, vr0")
7937 ] ANY_FWREDUC_SUM)
7938 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7939 "TARGET_VECTOR"
7940 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7941 [(set_attr "type" "vfwred<order>")
7942 (set_attr "mode" "<MODE>")
7943 (set (attr "frm_mode")
7944 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7946 ;; -------------------------------------------------------------------------------
7947 ;; ---- Predicated permutation operations
7948 ;; -------------------------------------------------------------------------------
7949 ;; Includes:
7950 ;; - 16.1 Integer Scalar Move Instructions
7951 ;; - 16.2 Floating-Point Scalar Move Instructions
7952 ;; - 16.3 Vector Slide Instructions
7953 ;; - 16.4 Vector Register Gather Instructions
7954 ;; - 16.5 Vector Compress Instruction
7955 ;; -------------------------------------------------------------------------------
7957 (define_expand "@pred_extract_first<mode>"
7958 [(set (match_operand:<VEL> 0 "register_operand")
7959 (unspec:<VEL>
7960 [(vec_select:<VEL>
7961 (match_operand:V_VLSI 1 "reg_or_mem_operand")
7962 (parallel [(const_int 0)]))
7963 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7964 "TARGET_VECTOR"
7965 {
7966 if (MEM_P (operands[1]))
7967 {
7968 /* Combine vle.v + vmv.x.s ==> lw. */
7969 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
7970 DONE;
7971 }
7972 })
7974 (define_insn_and_split "*pred_extract_first<mode>"
7975 [(set (match_operand:<VEL> 0 "register_operand" "=r")
7976 (unspec:<VEL>
7977 [(vec_select:<VEL>
7978 (match_operand:V_VLSI 1 "register_operand" "vr")
7979 (parallel [(const_int 0)]))
7980 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7981 "TARGET_VECTOR"
7982 "vmv.x.s\t%0,%1"
7983 "known_gt (GET_MODE_BITSIZE (<VEL>mode), GET_MODE_BITSIZE (Pmode))"
7984 [(const_int 0)]
7985 {
7986 /* In rv32 system, we can't use vmv.x.s directly.
7987 Instead, we should generate this following code sequence:
7988 vsrl.vx v16,v8,a0
7989 vmv.x.s a1,v16
7990 vmv.x.s a0,v8 */
7991 rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
7992 rtx high_bits = gen_reg_rtx (<MODE>mode);
7993 emit_insn (gen_pred_scalar (LSHIFTRT, <MODE>mode, high_bits, CONSTM1_RTX (<VM>mode),
7994 RVV_VUNDEF (<MODE>mode), operands[1], nbits, /* vl */ const1_rtx,
7995 gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
7996 gen_int_mode (riscv_vector::MASK_ANY, Pmode),
7997 gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
7998 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
7999 gen_highpart (SImode, operands[0]), high_bits));
8000 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8001 gen_lowpart (SImode, operands[0]), operands[1]));
8002 DONE;
8003 }
8004 [(set_attr "type" "vimovvx")
8005 (set_attr "mode" "<MODE>")])
8007 (define_insn "@pred_extract_first_trunc<mode>"
8008 [(set (match_operand:SI 0 "register_operand" "=r")
8009 (truncate:SI
8010 (unspec:<VEL>
8011 [(vec_select:<VEL>
8012 (match_operand:V_VLSI_D 1 "register_operand" "vr")
8013 (parallel [(const_int 0)]))
8014 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
8015 "TARGET_VECTOR"
8016 "vmv.x.s\t%0,%1"
8017 [(set_attr "type" "vimovvx")
8018 (set_attr "mode" "<MODE>")])
8020 (define_expand "@pred_extract_first<mode>"
8021 [(set (match_operand:<VEL> 0 "register_operand")
8022 (unspec:<VEL>
8023 [(vec_select:<VEL>
8024 (match_operand:V_VLSF 1 "reg_or_mem_operand")
8025 (parallel [(const_int 0)]))
8026 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8027 "TARGET_VECTOR"
8028 {
8029 if (MEM_P (operands[1]))
8030 {
8031 /* Combine vle.v + vmv.f.s ==> flw. */
8032 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
8033 DONE;
8034 }
8035 })
8037 (define_insn "*pred_extract_first<mode>"
8038 [(set (match_operand:<VEL> 0 "register_operand" "=f")
8039 (unspec:<VEL>
8040 [(vec_select:<VEL>
8041 (match_operand:V_VLSF 1 "register_operand" "vr")
8042 (parallel [(const_int 0)]))
8043 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8044 "TARGET_VECTOR"
8045 "vfmv.f.s\t%0,%1"
8046 [(set_attr "type" "vfmovvf")
8047 (set_attr "mode" "<MODE>")])
8049 ;; vslide instructions
8050 (define_insn "@pred_slide<ud><mode>"
8051 [(set (match_operand:V_VLS 0 "register_operand" "<ud_constraint>")
8052 (unspec:V_VLS
8053 [(unspec:<VM>
8054 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8055 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8056 (match_operand 6 "const_int_operand" " i, i, i, i")
8057 (match_operand 7 "const_int_operand" " i, i, i, i")
8058 (match_operand 8 "const_int_operand" " i, i, i, i")
8059 (reg:SI VL_REGNUM)
8060 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8061 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0, vu, 0")
8062 (match_operand:V_VLS 3 "register_operand" " vr, vr, vr, vr")
8063 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSLIDES))]
8064 "TARGET_VECTOR"
8065 "vslide<ud>.v%o4\t%0,%3,%4%p1"
8066 [(set_attr "type" "vslide<ud>")
8067 (set_attr "mode" "<MODE>")])
8069 ;; vslide1 instructions
8070 (define_insn "@pred_slide<ud><mode>"
8071 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "<ud_constraint>")
8072 (unspec:V_VLSI_QHS
8073 [(unspec:<VM>
8074 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8075 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8076 (match_operand 6 "const_int_operand" " i, i, i, i")
8077 (match_operand 7 "const_int_operand" " i, i, i, i")
8078 (match_operand 8 "const_int_operand" " i, i, i, i")
8079 (reg:SI VL_REGNUM)
8080 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8081 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")
8082 (match_operand:V_VLSI_QHS 3 "register_operand" " vr, vr, vr, vr")
8083 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8084 "TARGET_VECTOR"
8085 "vslide<ud>.vx\t%0,%3,%z4%p1"
8086 [(set_attr "type" "vislide<ud>")
8087 (set_attr "mode" "<MODE>")])
8089 (define_expand "@pred_slide<ud><mode>"
8090 [(set (match_operand:V_VLSI_D 0 "register_operand")
8091 (unspec:V_VLSI_D
8092 [(unspec:<VM>
8093 [(match_operand:<VM> 1 "vector_mask_operand")
8094 (match_operand 5 "reg_or_int_operand")
8095 (match_operand 6 "const_int_operand")
8096 (match_operand 7 "const_int_operand")
8097 (match_operand 8 "const_int_operand")
8098 (reg:SI VL_REGNUM)
8099 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8100 (match_operand:V_VLSI_D 2 "vector_merge_operand")
8101 (match_operand:V_VLSI_D 3 "register_operand")
8102 (match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
8103 "TARGET_VECTOR"
8104 {
8105 poly_uint64 nunits = GET_MODE_NUNITS (<MODE>mode) * 2;
8106 machine_mode vsimode = riscv_vector::get_vector_mode (SImode, nunits).require ();
8107 machine_mode vbimode = riscv_vector::get_vector_mode (BImode, nunits).require ();
8108 if (riscv_vector::slide1_sew64_helper (<UNSPEC>, <MODE>mode,
8109 vsimode, vbimode,
8110 operands))
8111 DONE;
8112 })
8114 (define_insn "*pred_slide<ud><mode>"
8115 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8116 (unspec:V_VLSI_D
8117 [(unspec:<VM>
8118 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8119 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8120 (match_operand 6 "const_int_operand" " i, i, i, i")
8121 (match_operand 7 "const_int_operand" " i, i, i, i")
8122 (match_operand 8 "const_int_operand" " i, i, i, i")
8123 (reg:SI VL_REGNUM)
8124 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8125 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8126 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8127 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8128 "TARGET_VECTOR"
8129 "vslide<ud>.vx\t%0,%3,%z4%p1"
8130 [(set_attr "type" "vislide<ud>")
8131 (set_attr "mode" "<MODE>")])
8133 (define_insn "*pred_slide<ud><mode>_extended"
8134 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8135 (unspec:V_VLSI_D
8136 [(unspec:<VM>
8137 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8138 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8139 (match_operand 6 "const_int_operand" " i, i, i, i")
8140 (match_operand 7 "const_int_operand" " i, i, i, i")
8141 (match_operand 8 "const_int_operand" " i, i, i, i")
8142 (reg:SI VL_REGNUM)
8143 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8144 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8145 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8146 (sign_extend:<VEL>
8147 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))]
8148 "TARGET_VECTOR"
8149 "vslide<ud>.vx\t%0,%3,%z4%p1"
8150 [(set_attr "type" "vislide<ud>")
8151 (set_attr "mode" "<MODE>")])
8153 ;; vfslide1 instructions
8154 (define_insn "@pred_slide<ud><mode>"
8155 [(set (match_operand:V_VLSF 0 "register_operand" "<ud_constraint>")
8156 (unspec:V_VLSF
8157 [(unspec:<VM>
8158 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8159 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8160 (match_operand 6 "const_int_operand" " i, i, i, i")
8161 (match_operand 7 "const_int_operand" " i, i, i, i")
8162 (match_operand 8 "const_int_operand" " i, i, i, i")
8163 (reg:SI VL_REGNUM)
8164 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8165 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")
8166 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
8167 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
8168 "TARGET_VECTOR"
8169 "vfslide<ud>.vf\t%0,%3,%4%p1"
8170 [(set_attr "type" "vfslide<ud>")
8171 (set_attr "mode" "<MODE>")])
8173 ;; vrgather
8174 (define_insn "@pred_gather<mode>"
8175 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8176 (if_then_else:V_VLS
8177 (unspec:<VM>
8178 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8179 (match_operand 5 "vector_length_operand" " rK, rK")
8180 (match_operand 6 "const_int_operand" " i, i")
8181 (match_operand 7 "const_int_operand" " i, i")
8182 (match_operand 8 "const_int_operand" " i, i")
8183 (reg:SI VL_REGNUM)
8184 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8185 (unspec:V_VLS
8186 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8187 (match_operand:<VINDEX> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHER)
8188 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8189 "TARGET_VECTOR"
8190 "vrgather.vv\t%0,%3,%4%p1"
8191 [(set_attr "type" "vgather")
8192 (set_attr "mode" "<MODE>")])
8194 (define_insn "@pred_gather<mode>_scalar"
8195 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8196 (if_then_else:V_VLS
8197 (unspec:<VM>
8198 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8199 (match_operand 5 "vector_length_operand" " rK, rK")
8200 (match_operand 6 "const_int_operand" " i, i")
8201 (match_operand 7 "const_int_operand" " i, i")
8202 (match_operand 8 "const_int_operand" " i, i")
8203 (reg:SI VL_REGNUM)
8204 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8205 (unspec:V_VLS
8206 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8207 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] UNSPEC_VRGATHER)
8208 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8209 "TARGET_VECTOR"
8210 "vrgather.v%o4\t%0,%3,%4%p1"
8211 [(set_attr "type" "vgather")
8212 (set_attr "mode" "<MODE>")])
8214 ;; vrgatherei16
8215 (define_insn "@pred_gatherei16<mode>"
8216 [(set (match_operand:VEI16 0 "register_operand" "=&vr, &vr")
8217 (if_then_else:VEI16
8218 (unspec:<VM>
8219 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8220 (match_operand 5 "vector_length_operand" " rK, rK")
8221 (match_operand 6 "const_int_operand" " i, i")
8222 (match_operand 7 "const_int_operand" " i, i")
8223 (match_operand 8 "const_int_operand" " i, i")
8224 (reg:SI VL_REGNUM)
8225 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8226 (unspec:VEI16
8227 [(match_operand:VEI16 3 "register_operand" " vr, vr")
8228 (match_operand:<VINDEXEI16> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHEREI16)
8229 (match_operand:VEI16 2 "vector_merge_operand" " vu, 0")))]
8230 "TARGET_VECTOR"
8231 "vrgatherei16.vv\t%0,%3,%4%p1"
8232 [(set_attr "type" "vgather")
8233 (set_attr "mode" "<MODE>")])
8235 ;; vcompress
8236 (define_insn "@pred_compress<mode>"
8237 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8238 (unspec:V_VLS
8239 [(unspec:<VM>
8240 [(match_operand:<VM> 3 "register_operand" " vm, vm")
8241 (match_operand 4 "vector_length_operand" " rK, rK")
8242 (match_operand 5 "const_int_operand" " i, i")
8243 (match_operand 6 "const_int_operand" " i, i")
8244 (reg:SI VL_REGNUM)
8245 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8246 (match_operand:V_VLS 2 "register_operand" " vr, vr")
8247 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))]
8248 "TARGET_VECTOR"
8249 "vcompress.vm\t%0,%2,%3"
8250 [(set_attr "type" "vcompress")
8251 (set_attr "mode" "<MODE>")])
8253 ;; -------------------------------------------------------------------------------
8254 ;; ---- Predicated Fault-Only-First loads
8255 ;; -------------------------------------------------------------------------------
8256 ;; Includes:
8257 ;; - 7.7. Unit-stride Fault-Only-First Loads
8258 ;; -------------------------------------------------------------------------------
8260 (define_insn "read_vlsi"
8261 [(set (match_operand:SI 0 "register_operand" "=r")
8262 (reg:SI VL_REGNUM))]
8263 "TARGET_VECTOR"
8264 "csrr\t%0,vl"
8265 [(set_attr "type" "rdvl")
8266 (set_attr "mode" "SI")])
8268 (define_insn "read_vldi_zero_extend"
8269 [(set (match_operand:DI 0 "register_operand" "=r")
8270 (zero_extend:DI (reg:SI VL_REGNUM)))]
8271 "TARGET_VECTOR && TARGET_64BIT"
8272 "csrr\t%0,vl"
8273 [(set_attr "type" "rdvl")
8274 (set_attr "mode" "DI")])
8276 (define_insn "@pred_fault_load<mode>"
8277 [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr")
8278 (if_then_else:V
8279 (unspec:<VM>
8280 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1, Wc1")
8281 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
8282 (match_operand 5 "const_int_operand" " i, i, i, i")
8283 (match_operand 6 "const_int_operand" " i, i, i, i")
8284 (match_operand 7 "const_int_operand" " i, i, i, i")
8285 (reg:SI VL_REGNUM)
8286 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8287 (unspec:V
8288 [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF)
8289 (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0")))
8290 (set (reg:SI VL_REGNUM)
8291 (unspec:SI
8292 [(if_then_else:V
8293 (unspec:<VM>
8294 [(match_dup 1) (match_dup 4) (match_dup 5)
8295 (match_dup 6) (match_dup 7)
8296 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8297 (unspec:V [(match_dup 3)] UNSPEC_VLEFF)
8298 (match_dup 2))] UNSPEC_MODIFY_VL))]
8299 "TARGET_VECTOR"
8300 "vle<sew>ff.v\t%0,%3%p1"
8301 [(set_attr "type" "vldff")
8302 (set_attr "mode" "<MODE>")])
8305 ;; -------------------------------------------------------------------------------
8306 ;; ---- Predicated Segment loads/stores
8307 ;; -------------------------------------------------------------------------------
8308 ;; Includes:
8309 ;; - 7.8.1. Vector Unit-Stride Segment Loads and Stores
8310 ;; - 7.8.2. Vector Strided Segment Loads and Stores
8311 ;; - 7.8.3. Vector Indexed Segment Loads and Stores
8312 ;; -------------------------------------------------------------------------------
8314 (define_insn "@pred_unit_strided_load<mode>"
8315 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8316 (if_then_else:VT
8317 (unspec:<VM>
8318 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8319 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8320 (match_operand 5 "const_int_operand" " i, i, i")
8321 (match_operand 6 "const_int_operand" " i, i, i")
8322 (match_operand 7 "const_int_operand" " i, i, i")
8323 (reg:SI VL_REGNUM)
8324 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8325 (unspec:VT
8326 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8327 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED)
8328 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8329 "TARGET_VECTOR"
8330 "vlseg<nf>e<sew>.v\t%0,(%z3)%p1"
8331 [(set_attr "type" "vlsegde")
8332 (set_attr "mode" "<MODE>")])
8334 (define_insn "@pred_unit_strided_store<mode>"
8335 [(set (mem:BLK (scratch))
8336 (unspec:BLK
8337 [(unspec:<VM>
8338 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8339 (match_operand 3 "vector_length_operand" " rK")
8340 (match_operand 4 "const_int_operand" " i")
8341 (reg:SI VL_REGNUM)
8342 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8343 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8344 (match_operand:VT 2 "register_operand" " vr")
8345 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED))]
8346 "TARGET_VECTOR"
8347 "vsseg<nf>e<sew>.v\t%2,(%z1)%p0"
8348 [(set_attr "type" "vssegte")
8349 (set_attr "mode" "<MODE>")])
8351 (define_insn "@pred_strided_load<mode>"
8352 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8353 (if_then_else:VT
8354 (unspec:<VM>
8355 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8356 (match_operand 5 "vector_length_operand" " rK, rK, rK")
8357 (match_operand 6 "const_int_operand" " i, i, i")
8358 (match_operand 7 "const_int_operand" " i, i, i")
8359 (match_operand 8 "const_int_operand" " i, i, i")
8360 (reg:SI VL_REGNUM)
8361 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8362 (unspec:VT
8363 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8364 (match_operand 4 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8365 (mem:BLK (scratch))] UNSPEC_STRIDED)
8366 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8367 "TARGET_VECTOR"
8368 "vlsseg<nf>e<sew>.v\t%0,(%z3),%z4%p1"
8369 [(set_attr "type" "vlsegds")
8370 (set_attr "mode" "<MODE>")])
8372 (define_insn "@pred_strided_store<mode>"
8373 [(set (mem:BLK (scratch))
8374 (unspec:BLK
8375 [(unspec:<VM>
8376 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8377 (match_operand 4 "vector_length_operand" " rK")
8378 (match_operand 5 "const_int_operand" " i")
8379 (reg:SI VL_REGNUM)
8380 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8381 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8382 (match_operand 2 "pmode_reg_or_0_operand" " rJ")
8383 (match_operand:VT 3 "register_operand" " vr")
8384 (mem:BLK (scratch))] UNSPEC_STRIDED))]
8385 "TARGET_VECTOR"
8386 "vssseg<nf>e<sew>.v\t%3,(%z1),%z2%p0"
8387 [(set_attr "type" "vssegts")
8388 (set_attr "mode" "<MODE>")])
8390 (define_insn "@pred_fault_load<mode>"
8391 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8392 (if_then_else:VT
8393 (unspec:<VM>
8394 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8395 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8396 (match_operand 5 "const_int_operand" " i, i, i")
8397 (match_operand 6 "const_int_operand" " i, i, i")
8398 (match_operand 7 "const_int_operand" " i, i, i")
8399 (reg:SI VL_REGNUM)
8400 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8401 (unspec:VT
8402 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8403 (mem:BLK (scratch))] UNSPEC_VLEFF)
8404 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))
8405 (set (reg:SI VL_REGNUM)
8406 (unspec:SI
8407 [(if_then_else:VT
8408 (unspec:<VM>
8409 [(match_dup 1) (match_dup 4) (match_dup 5)
8410 (match_dup 6) (match_dup 7)
8411 (reg:SI VL_REGNUM)
8412 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8413 (unspec:VT
8414 [(match_dup 3) (mem:BLK (scratch))] UNSPEC_VLEFF)
8415 (match_dup 2))] UNSPEC_MODIFY_VL))]
8416 "TARGET_VECTOR"
8417 "vlseg<nf>e<sew>ff.v\t%0,(%z3)%p1"
8418 [(set_attr "type" "vlsegdff")
8419 (set_attr "mode" "<MODE>")])
8421 (define_insn "@pred_indexed_<order>load<V1T:mode><RATIO64I:mode>"
8422 [(set (match_operand:V1T 0 "register_operand" "=&vr, &vr")
8423 (if_then_else:V1T
8424 (unspec:<VM>
8425 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8426 (match_operand 5 "vector_length_operand" " rK, rK")
8427 (match_operand 6 "const_int_operand" " i, i")
8428 (match_operand 7 "const_int_operand" " i, i")
8429 (match_operand 8 "const_int_operand" " i, i")
8430 (reg:SI VL_REGNUM)
8431 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8432 (unspec:V1T
8433 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8434 (mem:BLK (scratch))
8435 (match_operand:RATIO64I 4 "register_operand" " vr, vr")] ORDER)
8436 (match_operand:V1T 2 "vector_merge_operand" " vu, 0")))]
8437 "TARGET_VECTOR"
8438 "vl<order>xseg<nf>ei<RATIO64I:sew>.v\t%0,(%z3),%4%p1"
8439 [(set_attr "type" "vlsegd<order>x")
8440 (set_attr "mode" "<V1T:MODE>")])
8442 (define_insn "@pred_indexed_<order>load<V2T:mode><RATIO32I:mode>"
8443 [(set (match_operand:V2T 0 "register_operand" "=&vr, &vr")
8444 (if_then_else:V2T
8445 (unspec:<VM>
8446 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8447 (match_operand 5 "vector_length_operand" " rK, rK")
8448 (match_operand 6 "const_int_operand" " i, i")
8449 (match_operand 7 "const_int_operand" " i, i")
8450 (match_operand 8 "const_int_operand" " i, i")
8451 (reg:SI VL_REGNUM)
8452 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8453 (unspec:V2T
8454 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8455 (mem:BLK (scratch))
8456 (match_operand:RATIO32I 4 "register_operand" " vr, vr")] ORDER)
8457 (match_operand:V2T 2 "vector_merge_operand" " vu, 0")))]
8458 "TARGET_VECTOR"
8459 "vl<order>xseg<nf>ei<RATIO32I:sew>.v\t%0,(%z3),%4%p1"
8460 [(set_attr "type" "vlsegd<order>x")
8461 (set_attr "mode" "<V2T:MODE>")])
8463 (define_insn "@pred_indexed_<order>load<V4T:mode><RATIO16I:mode>"
8464 [(set (match_operand:V4T 0 "register_operand" "=&vr, &vr")
8465 (if_then_else:V4T
8466 (unspec:<VM>
8467 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8468 (match_operand 5 "vector_length_operand" " rK, rK")
8469 (match_operand 6 "const_int_operand" " i, i")
8470 (match_operand 7 "const_int_operand" " i, i")
8471 (match_operand 8 "const_int_operand" " i, i")
8472 (reg:SI VL_REGNUM)
8473 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8474 (unspec:V4T
8475 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8476 (mem:BLK (scratch))
8477 (match_operand:RATIO16I 4 "register_operand" " vr, vr")] ORDER)
8478 (match_operand:V4T 2 "vector_merge_operand" " vu, 0")))]
8479 "TARGET_VECTOR"
8480 "vl<order>xseg<nf>ei<RATIO16I:sew>.v\t%0,(%z3),%4%p1"
8481 [(set_attr "type" "vlsegd<order>x")
8482 (set_attr "mode" "<V4T:MODE>")])
8484 (define_insn "@pred_indexed_<order>load<V8T:mode><RATIO8I:mode>"
8485 [(set (match_operand:V8T 0 "register_operand" "=&vr, &vr")
8486 (if_then_else:V8T
8487 (unspec:<VM>
8488 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8489 (match_operand 5 "vector_length_operand" " rK, rK")
8490 (match_operand 6 "const_int_operand" " i, i")
8491 (match_operand 7 "const_int_operand" " i, i")
8492 (match_operand 8 "const_int_operand" " i, i")
8493 (reg:SI VL_REGNUM)
8494 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8495 (unspec:V8T
8496 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8497 (mem:BLK (scratch))
8498 (match_operand:RATIO8I 4 "register_operand" " vr, vr")] ORDER)
8499 (match_operand:V8T 2 "vector_merge_operand" " vu, 0")))]
8500 "TARGET_VECTOR"
8501 "vl<order>xseg<nf>ei<RATIO8I:sew>.v\t%0,(%z3),%4%p1"
8502 [(set_attr "type" "vlsegd<order>x")
8503 (set_attr "mode" "<V8T:MODE>")])
8505 (define_insn "@pred_indexed_<order>load<V16T:mode><RATIO4I:mode>"
8506 [(set (match_operand:V16T 0 "register_operand" "=&vr, &vr")
8507 (if_then_else:V16T
8508 (unspec:<VM>
8509 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8510 (match_operand 5 "vector_length_operand" " rK, rK")
8511 (match_operand 6 "const_int_operand" " i, i")
8512 (match_operand 7 "const_int_operand" " i, i")
8513 (match_operand 8 "const_int_operand" " i, i")
8514 (reg:SI VL_REGNUM)
8515 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8516 (unspec:V16T
8517 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8518 (mem:BLK (scratch))
8519 (match_operand:RATIO4I 4 "register_operand" " vr, vr")] ORDER)
8520 (match_operand:V16T 2 "vector_merge_operand" " vu, 0")))]
8521 "TARGET_VECTOR"
8522 "vl<order>xseg<nf>ei<RATIO4I:sew>.v\t%0,(%z3),%4%p1"
8523 [(set_attr "type" "vlsegd<order>x")
8524 (set_attr "mode" "<V16T:MODE>")])
8526 (define_insn "@pred_indexed_<order>load<V32T:mode><RATIO2I:mode>"
8527 [(set (match_operand:V32T 0 "register_operand" "=&vr, &vr")
8528 (if_then_else:V32T
8529 (unspec:<VM>
8530 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8531 (match_operand 5 "vector_length_operand" " rK, rK")
8532 (match_operand 6 "const_int_operand" " i, i")
8533 (match_operand 7 "const_int_operand" " i, i")
8534 (match_operand 8 "const_int_operand" " i, i")
8535 (reg:SI VL_REGNUM)
8536 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8537 (unspec:V32T
8538 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8539 (mem:BLK (scratch))
8540 (match_operand:RATIO2I 4 "register_operand" " vr, vr")] ORDER)
8541 (match_operand:V32T 2 "vector_merge_operand" " vu, 0")))]
8542 "TARGET_VECTOR"
8543 "vl<order>xseg<nf>ei<RATIO2I:sew>.v\t%0,(%z3),%4%p1"
8544 [(set_attr "type" "vlsegd<order>x")
8545 (set_attr "mode" "<V32T:MODE>")])
8547 (define_insn "@pred_indexed_<order>store<V1T:mode><RATIO64I:mode>"
8548 [(set (mem:BLK (scratch))
8549 (unspec:BLK
8550 [(unspec:<VM>
8551 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8552 (match_operand 4 "vector_length_operand" " rK")
8553 (match_operand 5 "const_int_operand" " i")
8554 (reg:SI VL_REGNUM)
8555 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8556 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8557 (match_operand:RATIO64I 2 "register_operand" " vr")
8558 (match_operand:V1T 3 "register_operand" " vr")] ORDER))]
8559 "TARGET_VECTOR"
8560 "vs<order>xseg<nf>ei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
8561 [(set_attr "type" "vssegt<order>x")
8562 (set_attr "mode" "<V1T:MODE>")])
8564 (define_insn "@pred_indexed_<order>store<V2T:mode><RATIO32I:mode>"
8565 [(set (mem:BLK (scratch))
8566 (unspec:BLK
8567 [(unspec:<VM>
8568 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8569 (match_operand 4 "vector_length_operand" " rK")
8570 (match_operand 5 "const_int_operand" " i")
8571 (reg:SI VL_REGNUM)
8572 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8573 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8574 (match_operand:RATIO32I 2 "register_operand" " vr")
8575 (match_operand:V2T 3 "register_operand" " vr")] ORDER))]
8576 "TARGET_VECTOR"
8577 "vs<order>xseg<nf>ei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
8578 [(set_attr "type" "vssegt<order>x")
8579 (set_attr "mode" "<V2T:MODE>")])
8581 (define_insn "@pred_indexed_<order>store<V4T:mode><RATIO16I:mode>"
8582 [(set (mem:BLK (scratch))
8583 (unspec:BLK
8584 [(unspec:<VM>
8585 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8586 (match_operand 4 "vector_length_operand" " rK")
8587 (match_operand 5 "const_int_operand" " i")
8588 (reg:SI VL_REGNUM)
8589 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8590 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8591 (match_operand:RATIO16I 2 "register_operand" " vr")
8592 (match_operand:V4T 3 "register_operand" " vr")] ORDER))]
8593 "TARGET_VECTOR"
8594 "vs<order>xseg<nf>ei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
8595 [(set_attr "type" "vssegt<order>x")
8596 (set_attr "mode" "<V4T:MODE>")])
8598 (define_insn "@pred_indexed_<order>store<V8T:mode><RATIO8I:mode>"
8599 [(set (mem:BLK (scratch))
8600 (unspec:BLK
8601 [(unspec:<VM>
8602 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8603 (match_operand 4 "vector_length_operand" " rK")
8604 (match_operand 5 "const_int_operand" " i")
8605 (reg:SI VL_REGNUM)
8606 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8607 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8608 (match_operand:RATIO8I 2 "register_operand" " vr")
8609 (match_operand:V8T 3 "register_operand" " vr")] ORDER))]
8610 "TARGET_VECTOR"
8611 "vs<order>xseg<nf>ei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
8612 [(set_attr "type" "vssegt<order>x")
8613 (set_attr "mode" "<V8T:MODE>")])
8615 (define_insn "@pred_indexed_<order>store<V16T:mode><RATIO4I:mode>"
8616 [(set (mem:BLK (scratch))
8617 (unspec:BLK
8618 [(unspec:<VM>
8619 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8620 (match_operand 4 "vector_length_operand" " rK")
8621 (match_operand 5 "const_int_operand" " i")
8622 (reg:SI VL_REGNUM)
8623 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8624 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8625 (match_operand:RATIO4I 2 "register_operand" " vr")
8626 (match_operand:V16T 3 "register_operand" " vr")] ORDER))]
8627 "TARGET_VECTOR"
8628 "vs<order>xseg<nf>ei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
8629 [(set_attr "type" "vssegt<order>x")
8630 (set_attr "mode" "<V16T:MODE>")])
8632 (define_insn "@pred_indexed_<order>store<V32T:mode><RATIO2I:mode>"
8633 [(set (mem:BLK (scratch))
8634 (unspec:BLK
8635 [(unspec:<VM>
8636 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8637 (match_operand 4 "vector_length_operand" " rK")
8638 (match_operand 5 "const_int_operand" " i")
8639 (reg:SI VL_REGNUM)
8640 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8641 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8642 (match_operand:RATIO2I 2 "register_operand" " vr")
8643 (match_operand:V32T 3 "register_operand" " vr")] ORDER))]
8644 "TARGET_VECTOR"
8645 "vs<order>xseg<nf>ei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
8646 [(set_attr "type" "vssegt<order>x")
8647 (set_attr "mode" "<V32T:MODE>")])
8649 (include "autovec.md")
8650 (include "autovec-opt.md")