1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions. */
26 /* Definitions for the object file format. These are set at
29 #define OBJECT_XCOFF 1
32 #define OBJECT_MACHO 4
34 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
35 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
36 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
37 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
43 /* Control whether function entry points use a "dot" symbol when
47 /* Default string to use for cpu if not specified. */
48 #ifndef TARGET_CPU_DEFAULT
49 #define TARGET_CPU_DEFAULT ((char *)0)
52 /* If configured for PPC405, support PPC405CR Erratum77. */
53 #ifdef CONFIG_PPC405CR
54 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
56 #define PPC405_ERRATUM77 0
59 /* Common ASM definitions used by ASM_SPEC among the various targets
60 for handling -mcpu=xxx switches. */
61 #define ASM_CPU_SPEC \
63 %{mpower: %{!mpower2: -mpwr}} \
65 %{mpowerpc64*: -mppc64} \
66 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \
67 %{mno-power: %{!mpowerpc*: -mcom}} \
68 %{!mno-power: %{!mpower*: %(asm_default)}}} \
69 %{mcpu=common: -mcom} \
70 %{mcpu=power: -mpwr} \
71 %{mcpu=power2: -mpwrx} \
72 %{mcpu=power3: -mppc64} \
73 %{mcpu=power4: -mpower4} \
74 %{mcpu=power5: -mpower4} \
75 %{mcpu=power5+: -mpower4} \
76 %{mcpu=powerpc: -mppc} \
78 %{mcpu=rios1: -mpwr} \
79 %{mcpu=rios2: -mpwrx} \
82 %{mcpu=rs64a: -mppc64} \
86 %{mcpu=405fp: -m405} \
88 %{mcpu=440fp: -m440} \
94 %{mcpu=ec603e: -mppc} \
97 %{mcpu=620: -mppc64} \
98 %{mcpu=630: -mppc64} \
102 %{mcpu=7400: -mppc -maltivec} \
103 %{mcpu=7450: -mppc -maltivec} \
104 %{mcpu=G4: -mppc -maltivec} \
109 %{mcpu=970: -mpower4 -maltivec} \
110 %{mcpu=G5: -mpower4 -maltivec} \
111 %{mcpu=8540: -me500} \
112 %{maltivec: -maltivec} \
115 #define CPP_DEFAULT_SPEC ""
117 #define ASM_DEFAULT_SPEC ""
119 /* This macro defines names of additional specifications to put in the specs
120 that can be used in various specifications like CC1_SPEC. Its definition
121 is an initializer with a subgrouping for each command option.
123 Each subgrouping contains a string constant, that defines the
124 specification name, and a string constant that used by the GCC driver
127 Do not define this macro if it does not need to do anything. */
129 #define SUBTARGET_EXTRA_SPECS
131 #define EXTRA_SPECS \
132 { "cpp_default", CPP_DEFAULT_SPEC }, \
133 { "asm_cpu", ASM_CPU_SPEC }, \
134 { "asm_default", ASM_DEFAULT_SPEC }, \
135 SUBTARGET_EXTRA_SPECS
137 /* Architecture type. */
139 /* Define TARGET_MFCRF if the target assembler does not support the
140 optional field operand for mfcr. */
142 #ifndef HAVE_AS_MFCRF
144 #define TARGET_MFCRF 0
147 /* Define TARGET_POPCNTB if the target assembler does not support the
148 popcount byte instruction. */
150 #ifndef HAVE_AS_POPCNTB
151 #undef TARGET_POPCNTB
152 #define TARGET_POPCNTB 0
155 /* Define TARGET_FPRND if the target assembler does not support the
156 fp rounding instructions. */
158 #ifndef HAVE_AS_FPRND
160 #define TARGET_FPRND 0
163 #ifndef TARGET_SECURE_PLT
164 #define TARGET_SECURE_PLT 0
167 #define TARGET_32BIT (! TARGET_64BIT)
170 #define HAVE_AS_TLS 0
173 /* Return 1 for a symbol ref for a thread-local storage symbol. */
174 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
175 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
178 /* For libgcc2 we make sure this is a compile time constant */
179 #if defined (__64BIT__) || defined (__powerpc64__)
180 #undef TARGET_POWERPC64
181 #define TARGET_POWERPC64 1
183 #undef TARGET_POWERPC64
184 #define TARGET_POWERPC64 0
187 /* The option machinery will define this. */
190 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
192 /* Processor type. Order must match cpu attribute in MD file. */
216 extern enum processor_type rs6000_cpu
;
218 /* Recast the processor type to the cpu attribute. */
219 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
221 /* Define generic processor types based upon current deployment. */
222 #define PROCESSOR_COMMON PROCESSOR_PPC601
223 #define PROCESSOR_POWER PROCESSOR_RIOS1
224 #define PROCESSOR_POWERPC PROCESSOR_PPC604
225 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
227 /* Define the default processor. This is overridden by other tm.h files. */
228 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
229 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
231 /* Specify the dialect of assembler to use. New mnemonics is dialect one
232 and the old mnemonics are dialect zero. */
233 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
235 /* Types of costly dependences. */
236 enum rs6000_dependence_cost
238 max_dep_latency
= 1000,
241 true_store_to_load_dep_costly
,
242 store_to_load_dep_costly
245 /* Types of nop insertion schemes in sched target hook sched_finish. */
246 enum rs6000_nop_insertion
248 sched_finish_regroup_exact
= 1000,
249 sched_finish_pad_groups
,
253 /* Dispatch group termination caused by an insn. */
254 enum group_termination
260 /* Support for a compile-time default CPU, et cetera. The rules are:
261 --with-cpu is ignored if -mcpu is specified.
262 --with-tune is ignored if -mtune is specified.
263 --with-float is ignored if -mhard-float or -msoft-float are
265 #define OPTION_DEFAULT_SPECS \
266 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
267 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
268 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
270 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
271 struct rs6000_cpu_select
279 extern struct rs6000_cpu_select rs6000_select
[];
282 extern const char *rs6000_debug_name
; /* Name for -mdebug-xxxx option */
283 extern int rs6000_debug_stack
; /* debug stack applications */
284 extern int rs6000_debug_arg
; /* debug argument handling */
286 #define TARGET_DEBUG_STACK rs6000_debug_stack
287 #define TARGET_DEBUG_ARG rs6000_debug_arg
289 extern const char *rs6000_traceback_name
; /* Type of traceback table. */
291 /* These are separate from target_flags because we've run out of bits
293 extern int rs6000_long_double_type_size
;
294 extern int rs6000_altivec_abi
;
295 extern int rs6000_spe_abi
;
296 extern int rs6000_float_gprs
;
297 extern int rs6000_alignment_flags
;
298 extern const char *rs6000_sched_insert_nops_str
;
299 extern enum rs6000_nop_insertion rs6000_sched_insert_nops
;
301 /* Alignment options for fields in structures for sub-targets following
303 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
304 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
306 Override the macro definitions when compiling libobjc to avoid undefined
307 reference to rs6000_alignment_flags due to library's use of GCC alignment
308 macros which use the macros below. */
310 #ifndef IN_TARGET_LIBS
311 #define MASK_ALIGN_POWER 0x00000000
312 #define MASK_ALIGN_NATURAL 0x00000001
313 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
315 #define TARGET_ALIGN_NATURAL 0
318 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
319 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
321 #define TARGET_SPE_ABI 0
323 #define TARGET_E500 0
324 #define TARGET_ISEL 0
325 #define TARGET_FPRS 1
326 #define TARGET_E500_SINGLE 0
327 #define TARGET_E500_DOUBLE 0
329 /* Sometimes certain combinations of command options do not make sense
330 on a particular target machine. You can define a macro
331 `OVERRIDE_OPTIONS' to take account of this. This macro, if
332 defined, is executed once just after all the command options have
335 Do not use this macro to turn on various extra optimizations for
336 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
338 On the RS/6000 this is used to define the target cpu type. */
340 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
342 /* Define this to change the optimizations performed by default. */
343 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
345 /* Show we can debug even without a frame pointer. */
346 #define CAN_DEBUG_WITHOUT_FP
349 #define REGISTER_TARGET_PRAGMAS() do { \
350 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
351 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
354 /* Target #defines. */
355 #define TARGET_CPU_CPP_BUILTINS() \
356 rs6000_cpu_cpp_builtins (pfile)
358 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
359 we're compiling for. Some configurations may need to override it. */
360 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
363 if (BYTES_BIG_ENDIAN) \
365 builtin_define ("__BIG_ENDIAN__"); \
366 builtin_define ("_BIG_ENDIAN"); \
367 builtin_assert ("machine=bigendian"); \
371 builtin_define ("__LITTLE_ENDIAN__"); \
372 builtin_define ("_LITTLE_ENDIAN"); \
373 builtin_assert ("machine=littleendian"); \
378 /* Target machine storage layout. */
380 /* Define this macro if it is advisable to hold scalars in registers
381 in a wider mode than that declared by the program. In such cases,
382 the value is constrained to be within the bounds of the declared
383 type, but kept valid in the wider mode. The signedness of the
384 extension may differ from that of the type. */
386 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
387 if (GET_MODE_CLASS (MODE) == MODE_INT \
388 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
389 (MODE) = TARGET_32BIT ? SImode : DImode;
391 /* Define this if most significant bit is lowest numbered
392 in instructions that operate on numbered bit-fields. */
393 /* That is true on RS/6000. */
394 #define BITS_BIG_ENDIAN 1
396 /* Define this if most significant byte of a word is the lowest numbered. */
397 /* That is true on RS/6000. */
398 #define BYTES_BIG_ENDIAN 1
400 /* Define this if most significant word of a multiword number is lowest
403 For RS/6000 we can decide arbitrarily since there are no machine
404 instructions for them. Might as well be consistent with bits and bytes. */
405 #define WORDS_BIG_ENDIAN 1
407 #define MAX_BITS_PER_WORD 64
409 /* Width of a word, in units (bytes). */
410 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
412 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
414 #define MIN_UNITS_PER_WORD 4
416 #define UNITS_PER_FP_WORD 8
417 #define UNITS_PER_ALTIVEC_WORD 16
418 #define UNITS_PER_SPE_WORD 8
420 /* Type used for ptrdiff_t, as a string used in a declaration. */
421 #define PTRDIFF_TYPE "int"
423 /* Type used for size_t, as a string used in a declaration. */
424 #define SIZE_TYPE "long unsigned int"
426 /* Type used for wchar_t, as a string used in a declaration. */
427 #define WCHAR_TYPE "short unsigned int"
429 /* Width of wchar_t in bits. */
430 #define WCHAR_TYPE_SIZE 16
432 /* A C expression for the size in bits of the type `short' on the
433 target machine. If you don't define this, the default is half a
434 word. (If this would be less than one storage unit, it is
435 rounded up to one unit.) */
436 #define SHORT_TYPE_SIZE 16
438 /* A C expression for the size in bits of the type `int' on the
439 target machine. If you don't define this, the default is one
441 #define INT_TYPE_SIZE 32
443 /* A C expression for the size in bits of the type `long' on the
444 target machine. If you don't define this, the default is one
446 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
448 /* A C expression for the size in bits of the type `long long' on the
449 target machine. If you don't define this, the default is two
451 #define LONG_LONG_TYPE_SIZE 64
453 /* A C expression for the size in bits of the type `float' on the
454 target machine. If you don't define this, the default is one
456 #define FLOAT_TYPE_SIZE 32
458 /* A C expression for the size in bits of the type `double' on the
459 target machine. If you don't define this, the default is two
461 #define DOUBLE_TYPE_SIZE 64
463 /* A C expression for the size in bits of the type `long double' on
464 the target machine. If you don't define this, the default is two
466 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
468 /* Define this to set long double type size to use in libgcc2.c, which can
469 not depend on target_flags. */
470 #ifdef __LONG_DOUBLE_128__
471 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
473 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
476 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
477 #define WIDEST_HARDWARE_FP_SIZE 64
479 /* Width in bits of a pointer.
480 See also the macro `Pmode' defined below. */
481 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
483 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
484 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
486 /* Boundary (in *bits*) on which stack pointer should be aligned. */
487 #define STACK_BOUNDARY \
488 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI) ? 64 : 128)
490 /* Allocation boundary (in *bits*) for the code of a function. */
491 #define FUNCTION_BOUNDARY 32
493 /* No data type wants to be aligned rounder than this. */
494 #define BIGGEST_ALIGNMENT 128
496 /* A C expression to compute the alignment for a variables in the
497 local store. TYPE is the data type, and ALIGN is the alignment
498 that the object would ordinarily have. */
499 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
500 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \
501 (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 : \
502 (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN)
504 /* Alignment of field after `int : 0' in a structure. */
505 #define EMPTY_FIELD_BOUNDARY 32
507 /* Every structure's size must be a multiple of this. */
508 #define STRUCTURE_SIZE_BOUNDARY 8
510 /* Return 1 if a structure or array containing FIELD should be
511 accessed using `BLKMODE'.
513 For the SPE, simd types are V2SI, and gcc can be tempted to put the
514 entire thing in a DI and use subregs to access the internals.
515 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
516 back-end. Because a single GPR can hold a V2SI, but not a DI, the
517 best thing to do is set structs to BLKmode and avoid Severe Tire
520 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
521 fit into 1, whereas DI still needs two. */
522 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
523 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \
524 || (TARGET_E500_DOUBLE && (MODE) == DFmode))
526 /* A bit-field declared as `int' forces `int' alignment for the struct. */
527 #define PCC_BITFIELD_TYPE_MATTERS 1
529 /* Make strings word-aligned so strcpy from constants will be faster.
530 Make vector constants quadword aligned. */
531 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
532 (TREE_CODE (EXP) == STRING_CST \
533 && (ALIGN) < BITS_PER_WORD \
537 /* Make arrays of chars word-aligned for the same reasons.
538 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
540 #define DATA_ALIGNMENT(TYPE, ALIGN) \
541 (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \
542 : (TARGET_E500_DOUBLE && TYPE_MODE (TYPE) == DFmode) ? 64 \
543 : TREE_CODE (TYPE) == ARRAY_TYPE \
544 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
545 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
547 /* Nonzero if move instructions will actually fail to work
548 when given unaligned data. */
549 #define STRICT_ALIGNMENT 0
551 /* Define this macro to be the value 1 if unaligned accesses have a cost
552 many times greater than aligned accesses, for example if they are
553 emulated in a trap handler. */
554 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
556 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \
557 || (MODE) == DImode) \
560 /* Standard register usage. */
562 /* Number of actual hardware registers.
563 The hardware registers are assigned numbers for the compiler
564 from 0 to just below FIRST_PSEUDO_REGISTER.
565 All registers that the compiler knows about must be given numbers,
566 even those that are not normally considered general registers.
568 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
569 an MQ register, a count register, a link register, and 8 condition
570 register fields, which we view here as separate registers. AltiVec
571 adds 32 vector registers and a VRsave register.
573 In addition, the difference between the frame and argument pointers is
574 a function of the number of registers saved, so we need to have a
575 register for AP that will later be eliminated in favor of SP or FP.
576 This is a normal register, but it is fixed.
578 We also create a pseudo register for float/int conversions, that will
579 really represent the memory location used. It is represented here as
580 a register, in order to work around problems in allocating stack storage
583 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
584 pointer, which is eventually eliminated in favor of SP or FP. */
586 #define FIRST_PSEUDO_REGISTER 114
588 /* This must be included for pre gcc 3.0 glibc compatibility. */
589 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
591 /* Add 32 dwarf columns for synthetic SPE registers. */
592 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32)
594 /* The SPE has an additional 32 synthetic registers, with DWARF debug
595 info numbering for these registers starting at 1200. While eh_frame
596 register numbering need not be the same as the debug info numbering,
597 we choose to number these regs for eh_frame at 1200 too. This allows
598 future versions of the rs6000 backend to add hard registers and
599 continue to use the gcc hard register numbering for eh_frame. If the
600 extra SPE registers in eh_frame were numbered starting from the
601 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER
602 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to
603 avoid invalidating older SPE eh_frame info.
605 We must map them here to avoid huge unwinder tables mostly consisting
607 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
608 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r))
610 /* Use gcc hard register numbering for eh_frame. */
611 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
613 /* 1 for registers that have pervasive standard uses
614 and are not available for the register allocator.
616 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
617 as a local register; for all other OS's r2 is the TOC pointer.
619 cr5 is not supposed to be used.
621 On System V implementations, r13 is fixed and not available for use. */
623 #define FIXED_REGISTERS \
624 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
625 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
626 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
627 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
628 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
629 /* AltiVec registers. */ \
630 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
636 /* 1 for registers not available across function calls.
637 These must include the FIXED_REGISTERS and also any
638 registers that can be used without being saved.
639 The latter must include the registers where values are returned
640 and the register where structure-value addresses are passed.
641 Aside from that, you can include as many other registers as you like. */
643 #define CALL_USED_REGISTERS \
644 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
645 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
646 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
647 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
648 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
649 /* AltiVec registers. */ \
650 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
651 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
656 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
657 the entire set of `FIXED_REGISTERS' be included.
658 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
659 This macro is optional. If not specified, it defaults to the value
660 of `CALL_USED_REGISTERS'. */
662 #define CALL_REALLY_USED_REGISTERS \
663 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
664 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
665 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
666 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
667 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
668 /* AltiVec registers. */ \
669 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
670 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
681 #define MAX_CR_REGNO 75
683 #define FIRST_ALTIVEC_REGNO 77
684 #define LAST_ALTIVEC_REGNO 108
685 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
686 #define VRSAVE_REGNO 109
687 #define VSCR_REGNO 110
688 #define SPE_ACC_REGNO 111
689 #define SPEFSCR_REGNO 112
691 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
692 #define FIRST_SAVED_FP_REGNO (14+32)
693 #define FIRST_SAVED_GP_REGNO 13
695 /* List the order in which to allocate registers. Each register must be
696 listed once, even those in FIXED_REGISTERS.
698 We allocate in the following order:
699 fp0 (not saved or used for anything)
700 fp13 - fp2 (not saved; incoming fp arg registers)
701 fp1 (not saved; return value)
702 fp31 - fp14 (saved; order given to save least number)
703 cr7, cr6 (not saved or special)
704 cr1 (not saved, but used for FP operations)
705 cr0 (not saved, but used for arithmetic operations)
706 cr4, cr3, cr2 (saved)
707 r0 (not saved; cannot be base reg)
708 r9 (not saved; best for TImode)
709 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
710 r3 (not saved; return value register)
711 r31 - r13 (saved; order given to save least number)
712 r12 (not saved; if used for DImode or DFmode would use r13)
713 mq (not saved; best to use it if we can)
714 ctr (not saved; when we have the choice ctr is better)
716 cr5, r1, r2, ap, xer (fixed)
717 v0 - v1 (not saved or used for anything)
718 v13 - v3 (not saved; incoming vector arg registers)
719 v2 (not saved; incoming vector arg reg; return value)
720 v19 - v14 (not saved or used for anything)
721 v31 - v20 (saved; order given to save least number)
723 spe_acc, spefscr (fixed)
728 #define MAYBE_R2_AVAILABLE
729 #define MAYBE_R2_FIXED 2,
731 #define MAYBE_R2_AVAILABLE 2,
732 #define MAYBE_R2_FIXED
735 #define REG_ALLOC_ORDER \
737 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
739 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
740 50, 49, 48, 47, 46, \
741 75, 74, 69, 68, 72, 71, 70, \
742 0, MAYBE_R2_AVAILABLE \
743 9, 11, 10, 8, 7, 6, 5, 4, \
745 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
746 18, 17, 16, 15, 14, 13, 12, \
748 73, 1, MAYBE_R2_FIXED 67, 76, \
749 /* AltiVec registers. */ \
751 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
753 96, 95, 94, 93, 92, 91, \
754 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
759 /* True if register is floating-point. */
760 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
762 /* True if register is a condition register. */
763 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
765 /* True if register is a condition register, but not cr0. */
766 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
768 /* True if register is an integer register. */
769 #define INT_REGNO_P(N) \
770 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
772 /* SPE SIMD registers are just the GPRs. */
773 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
775 /* True if register is the XER register. */
776 #define XER_REGNO_P(N) ((N) == XER_REGNO)
778 /* True if register is an AltiVec register. */
779 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
781 /* Return number of consecutive hard regs needed starting at reg REGNO
782 to hold something of mode MODE. */
784 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs ((REGNO), (MODE))
786 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
787 ((TARGET_32BIT && TARGET_POWERPC64 \
788 && (GET_MODE_SIZE (MODE) > 4) \
789 && INT_REGNO_P (REGNO)) ? 1 : 0)
791 #define ALTIVEC_VECTOR_MODE(MODE) \
792 ((MODE) == V16QImode \
793 || (MODE) == V8HImode \
794 || (MODE) == V4SFmode \
795 || (MODE) == V4SImode)
797 #define SPE_VECTOR_MODE(MODE) \
798 ((MODE) == V4HImode \
799 || (MODE) == V2SFmode \
800 || (MODE) == V1DImode \
801 || (MODE) == V2SImode)
803 #define UNITS_PER_SIMD_WORD \
804 (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \
805 : (TARGET_SPE ? UNITS_PER_SPE_WORD : UNITS_PER_WORD))
807 /* Value is TRUE if hard register REGNO can hold a value of
808 machine-mode MODE. */
809 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
810 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO]
812 /* Value is 1 if it is a good idea to tie two pseudo registers
813 when one has mode MODE1 and one has mode MODE2.
814 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
815 for any hard reg, then this must be 0 for correct output. */
816 #define MODES_TIEABLE_P(MODE1, MODE2) \
817 (SCALAR_FLOAT_MODE_P (MODE1) \
818 ? SCALAR_FLOAT_MODE_P (MODE2) \
819 : SCALAR_FLOAT_MODE_P (MODE2) \
820 ? SCALAR_FLOAT_MODE_P (MODE1) \
821 : GET_MODE_CLASS (MODE1) == MODE_CC \
822 ? GET_MODE_CLASS (MODE2) == MODE_CC \
823 : GET_MODE_CLASS (MODE2) == MODE_CC \
824 ? GET_MODE_CLASS (MODE1) == MODE_CC \
825 : SPE_VECTOR_MODE (MODE1) \
826 ? SPE_VECTOR_MODE (MODE2) \
827 : SPE_VECTOR_MODE (MODE2) \
828 ? SPE_VECTOR_MODE (MODE1) \
829 : ALTIVEC_VECTOR_MODE (MODE1) \
830 ? ALTIVEC_VECTOR_MODE (MODE2) \
831 : ALTIVEC_VECTOR_MODE (MODE2) \
832 ? ALTIVEC_VECTOR_MODE (MODE1) \
835 /* Post-reload, we can't use any new AltiVec registers, as we already
836 emitted the vrsave mask. */
838 #define HARD_REGNO_RENAME_OK(SRC, DST) \
839 (! ALTIVEC_REGNO_P (DST) || regs_ever_live[DST])
841 /* A C expression returning the cost of moving data from a register of class
842 CLASS1 to one of CLASS2. */
844 #define REGISTER_MOVE_COST rs6000_register_move_cost
846 /* A C expressions returning the cost of moving data of MODE from a register to
849 #define MEMORY_MOVE_COST rs6000_memory_move_cost
851 /* Specify the cost of a branch insn; roughly the number of extra insns that
852 should be added to avoid a branch.
854 Set this to 3 on the RS/6000 since that is roughly the average cost of an
855 unscheduled conditional branch. */
857 #define BRANCH_COST 3
859 /* Override BRANCH_COST heuristic which empirically produces worse
860 performance for removing short circuiting from the logical ops. */
862 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
864 /* A fixed register used at prologue and epilogue generation to fix
865 addressing modes. The SPE needs heavy addressing fixes at the last
866 minute, and it's best to save a register for it.
868 AltiVec also needs fixes, but we've gotten around using r11, which
869 is actually wrong because when use_backchain_to_restore_sp is true,
870 we end up clobbering r11.
872 The AltiVec case needs to be fixed. Dunno if we should break ABI
873 compatibility and reserve a register for it as well.. */
875 #define FIXED_SCRATCH (TARGET_SPE ? 14 : 11)
877 /* Define this macro to change register usage conditional on target
880 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage ()
882 /* Specify the registers used for certain standard purposes.
883 The values of these macros are register numbers. */
885 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
886 /* #define PC_REGNUM */
888 /* Register to use for pushing function arguments. */
889 #define STACK_POINTER_REGNUM 1
891 /* Base register for access to local variables of the function. */
892 #define HARD_FRAME_POINTER_REGNUM 31
894 /* Base register for access to local variables of the function. */
895 #define FRAME_POINTER_REGNUM 113
897 /* Value should be nonzero if functions must have frame pointers.
898 Zero means the frame pointer need not be set up (and parms
899 may be accessed via the stack pointer) in functions that seem suitable.
900 This is computed in `reload', in reload1.c. */
901 #define FRAME_POINTER_REQUIRED 0
903 /* Base register for access to arguments of the function. */
904 #define ARG_POINTER_REGNUM 67
906 /* Place to put static chain when calling a function that requires it. */
907 #define STATIC_CHAIN_REGNUM 11
909 /* Link register number. */
910 #define LINK_REGISTER_REGNUM 65
912 /* Count register number. */
913 #define COUNT_REGISTER_REGNUM 66
915 /* Define the classes of registers for register constraints in the
916 machine description. Also define ranges of constants.
918 One of the classes must always be named ALL_REGS and include all hard regs.
919 If there is more than one class, another class must be named NO_REGS
920 and contain no registers.
922 The name GENERAL_REGS must be the name of a class (or an alias for
923 another name such as ALL_REGS). This is the class of registers
924 that is allowed by "g" or "r" in a register constraint.
925 Also, registers outside this class are allocated only when
926 instructions express preferences for them.
928 The classes must be numbered in nondecreasing order; that is,
929 a larger-numbered class must never be contained completely
930 in a smaller-numbered class.
932 For any two classes, it is very desirable that there be another
933 class that represents their union. */
935 /* The RS/6000 has three types of registers, fixed-point, floating-point,
936 and condition registers, plus three special registers, MQ, CTR, and the
937 link register. AltiVec adds a vector register class.
939 However, r0 is special in that it cannot be used as a base register.
940 So make a class for registers valid as base registers.
942 Also, cr0 is the only condition code register that can be used in
943 arithmetic insns, so make a separate class for it. */
971 #define N_REG_CLASSES (int) LIM_REG_CLASSES
973 /* Give names of register classes as strings for dump file. */
975 #define REG_CLASS_NAMES \
986 "NON_SPECIAL_REGS", \
990 "LINK_OR_CTR_REGS", \
992 "SPEC_OR_GEN_REGS", \
1000 /* Define which registers fit in which classes.
1001 This is an initializer for a vector of HARD_REG_SET
1002 of length N_REG_CLASSES. */
1004 #define REG_CLASS_CONTENTS \
1006 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1007 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \
1008 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \
1009 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1010 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1011 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1012 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1013 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \
1014 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \
1015 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \
1016 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1017 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1018 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1019 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1020 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1021 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \
1022 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1023 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1024 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1025 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1026 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \
1029 /* The same information, inverted:
1030 Return the class number of the smallest class containing
1031 reg number REGNO. This could be a conditional expression
1032 or could index an array. */
1034 #define REGNO_REG_CLASS(REGNO) \
1035 ((REGNO) == 0 ? GENERAL_REGS \
1036 : (REGNO) < 32 ? BASE_REGS \
1037 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1038 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1039 : (REGNO) == CR0_REGNO ? CR0_REGS \
1040 : CR_REGNO_P (REGNO) ? CR_REGS \
1041 : (REGNO) == MQ_REGNO ? MQ_REGS \
1042 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1043 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1044 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1045 : (REGNO) == XER_REGNO ? XER_REGS \
1046 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1047 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1048 : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \
1049 : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \
1050 : (REGNO) == FRAME_POINTER_REGNUM ? BASE_REGS \
1053 /* The class value for index registers, and the one for base regs. */
1054 #define INDEX_REG_CLASS GENERAL_REGS
1055 #define BASE_REG_CLASS BASE_REGS
1057 /* Get reg_class from a letter such as appears in the machine description. */
1059 #define REG_CLASS_FROM_LETTER(C) \
1060 ((C) == 'f' ? ((TARGET_HARD_FLOAT && TARGET_FPRS) ? FLOAT_REGS : NO_REGS) \
1061 : (C) == 'b' ? BASE_REGS \
1062 : (C) == 'h' ? SPECIAL_REGS \
1063 : (C) == 'q' ? MQ_REGS \
1064 : (C) == 'c' ? CTR_REGS \
1065 : (C) == 'l' ? LINK_REGS \
1066 : (C) == 'v' ? ALTIVEC_REGS \
1067 : (C) == 'x' ? CR0_REGS \
1068 : (C) == 'y' ? CR_REGS \
1069 : (C) == 'z' ? XER_REGS \
1072 /* The letters I, J, K, L, M, N, and P in a register constraint string
1073 can be used to stand for particular ranges of immediate operands.
1074 This macro defines what the ranges are.
1075 C is the letter, and VALUE is a constant value.
1076 Return 1 if VALUE is in the range specified by C.
1078 `I' is a signed 16-bit constant
1079 `J' is a constant with only the high-order 16 bits nonzero
1080 `K' is a constant with only the low-order 16 bits nonzero
1081 `L' is a signed 16-bit constant shifted left 16 bits
1082 `M' is a constant that is greater than 31
1083 `N' is a positive constant that is an exact power of two
1084 `O' is the constant zero
1085 `P' is a constant whose negation is a signed 16-bit constant */
1087 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1088 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1089 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1090 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1091 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1092 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1093 : (C) == 'M' ? (VALUE) > 31 \
1094 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1095 : (C) == 'O' ? (VALUE) == 0 \
1096 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1099 /* Similar, but for floating constants, and defining letters G and H.
1100 Here VALUE is the CONST_DOUBLE rtx itself.
1102 We flag for special constants when we can copy the constant into
1103 a general register in two insns for DF/DI and one insn for SF.
1105 'H' is used for DI/DF constants that take 3 insns. */
1107 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1108 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1109 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1110 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1113 /* Optional extra constraints for this machine.
1115 'Q' means that is a memory operand that is just an offset from a reg.
1116 'R' is for AIX TOC entries.
1117 'S' is a constant that can be placed into a 64-bit mask operand.
1118 'T' is a constant that can be placed into a 32-bit mask operand.
1119 'U' is for V.4 small data references.
1120 'W' is a vector constant that can be easily generated (no mem refs).
1121 'Y' is an indexed or word-aligned displacement memory operand.
1122 'Z' is an indexed or indirect memory operand.
1123 'a' is an indexed or indirect address operand.
1124 't' is for AND masks that can be performed by two rldic{l,r} insns
1125 (but excluding those that could match other constraints of anddi3.) */
1127 #define EXTRA_CONSTRAINT(OP, C) \
1128 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1129 : (C) == 'R' ? legitimate_constant_pool_address_p (OP) \
1130 : (C) == 'S' ? mask64_operand (OP, DImode) \
1131 : (C) == 'T' ? mask_operand (OP, GET_MODE (OP)) \
1132 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1133 && small_data_operand (OP, GET_MODE (OP))) \
1134 : (C) == 't' ? (mask64_2_operand (OP, DImode) \
1135 && (fixed_regs[CR0_REGNO] \
1136 || !logical_operand (OP, DImode)) \
1137 && !mask_operand (OP, DImode) \
1138 && !mask64_operand (OP, DImode)) \
1139 : (C) == 'W' ? (easy_vector_constant (OP, GET_MODE (OP))) \
1140 : (C) == 'Y' ? (word_offset_memref_operand (OP, GET_MODE (OP))) \
1141 : (C) == 'Z' ? (indexed_or_indirect_operand (OP, GET_MODE (OP))) \
1142 : (C) == 'a' ? (indexed_or_indirect_address (OP, GET_MODE (OP))) \
1145 /* Define which constraints are memory constraints. Tell reload
1146 that any memory address can be reloaded by copying the
1147 memory address into a base register if required. */
1149 #define EXTRA_MEMORY_CONSTRAINT(C, STR) \
1150 ((C) == 'Q' || (C) == 'Y' || (C) == 'Z')
1152 /* Define which constraints should be treated like address constraints
1153 by the reload pass. */
1155 #define EXTRA_ADDRESS_CONSTRAINT(C, STR) \
1158 /* Given an rtx X being reloaded into a reg required to be
1159 in class CLASS, return the class of reg to actually use.
1160 In general this is just CLASS; but on some machines
1161 in some cases it is preferable to use a more restrictive class.
1163 On the RS/6000, we have to return NO_REGS when we want to reload a
1164 floating-point CONST_DOUBLE to force it to be copied to memory.
1166 We also don't want to reload integer values into floating-point
1167 registers if we can at all help it. In fact, this can
1168 cause reload to die, if it tries to generate a reload of CTR
1169 into a FP register and discovers it doesn't have the memory location
1172 ??? Would it be a good idea to have reload do the converse, that is
1173 try to reload floating modes into FP registers if possible?
1176 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1178 && reg_classes_intersect_p ((CLASS), FLOAT_REGS)) \
1180 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1181 && (CLASS) == NON_SPECIAL_REGS) \
1185 /* Return the register class of a scratch register needed to copy IN into
1186 or out of a register in CLASS in MODE. If it can be done directly,
1187 NO_REGS is returned. */
1189 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1190 rs6000_secondary_reload_class (CLASS, MODE, IN)
1192 /* If we are copying between FP or AltiVec registers and anything
1193 else, we need a memory location. */
1195 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1196 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1197 || (CLASS2) == FLOAT_REGS \
1198 || (CLASS1) == ALTIVEC_REGS \
1199 || (CLASS2) == ALTIVEC_REGS))
1201 /* Return the maximum number of consecutive registers
1202 needed to represent mode MODE in a register of class CLASS.
1204 On RS/6000, this is the size of MODE in words,
1205 except in the FP regs, where a single reg is enough for two words. */
1206 #define CLASS_MAX_NREGS(CLASS, MODE) \
1207 (((CLASS) == FLOAT_REGS) \
1208 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1209 : (TARGET_E500_DOUBLE && (CLASS) == GENERAL_REGS && (MODE) == DFmode) \
1211 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1214 /* Return a class of registers that cannot change FROM mode to TO mode. */
1216 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1217 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) \
1218 && GET_MODE_SIZE (FROM) >= 8 && GET_MODE_SIZE (TO) >= 8) \
1220 : GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
1221 ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \
1222 : (TARGET_E500_DOUBLE && (((TO) == DFmode) + ((FROM) == DFmode)) == 1) \
1223 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1224 : (TARGET_E500_DOUBLE && (((TO) == DImode) + ((FROM) == DImode)) == 1) \
1225 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1226 : (TARGET_SPE && (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1) \
1227 ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \
1230 /* Stack layout; function entry, exit and calling. */
1232 /* Enumeration to give which calling sequence to use. */
1235 ABI_AIX
, /* IBM's AIX */
1236 ABI_V4
, /* System V.4/eabi */
1237 ABI_DARWIN
/* Apple's Darwin (OS X kernel) */
1240 extern enum rs6000_abi rs6000_current_abi
; /* available for use by subtarget */
1242 /* Define this if pushing a word on the stack
1243 makes the stack pointer a smaller address. */
1244 #define STACK_GROWS_DOWNWARD
1246 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1247 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1249 /* Define this to nonzero if the nominal address of the stack frame
1250 is at the high-address end of the local variables;
1251 that is, each additional local variable allocated
1252 goes at a more negative offset in the frame.
1254 On the RS/6000, we grow upwards, from the area after the outgoing
1256 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0)
1258 /* Size of the outgoing register save area */
1259 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1260 || DEFAULT_ABI == ABI_DARWIN) \
1261 ? (TARGET_64BIT ? 64 : 32) \
1264 /* Size of the fixed area on the stack */
1265 #define RS6000_SAVE_AREA \
1266 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1267 << (TARGET_64BIT ? 1 : 0))
1269 /* MEM representing address to save the TOC register */
1270 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1271 plus_constant (stack_pointer_rtx, \
1272 (TARGET_32BIT ? 20 : 40)))
1274 /* Align an address */
1275 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1277 /* Offset within stack frame to start allocating local variables at.
1278 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1279 first local allocated. Otherwise, it is the offset to the BEGINNING
1280 of the first local allocated.
1282 On the RS/6000, the frame pointer is the same as the stack pointer,
1283 except for dynamic allocations. So we start after the fixed area and
1284 outgoing parameter area. */
1286 #define STARTING_FRAME_OFFSET \
1287 (FRAME_GROWS_DOWNWARD \
1289 : (RS6000_ALIGN (current_function_outgoing_args_size, \
1290 TARGET_ALTIVEC ? 16 : 8) \
1291 + RS6000_SAVE_AREA))
1293 /* Offset from the stack pointer register to an item dynamically
1294 allocated on the stack, e.g., by `alloca'.
1296 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1297 length of the outgoing arguments. The default is correct for most
1298 machines. See `function.c' for details. */
1299 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1300 (RS6000_ALIGN (current_function_outgoing_args_size, \
1301 TARGET_ALTIVEC ? 16 : 8) \
1302 + (STACK_POINTER_OFFSET))
1304 /* If we generate an insn to push BYTES bytes,
1305 this says how many the stack pointer really advances by.
1306 On RS/6000, don't define this because there are no push insns. */
1307 /* #define PUSH_ROUNDING(BYTES) */
1309 /* Offset of first parameter from the argument pointer register value.
1310 On the RS/6000, we define the argument pointer to the start of the fixed
1312 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1314 /* Offset from the argument pointer register value to the top of
1315 stack. This is different from FIRST_PARM_OFFSET because of the
1316 register save area. */
1317 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1319 /* Define this if stack space is still allocated for a parameter passed
1320 in a register. The value is the number of bytes allocated to this
1322 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1324 /* Define this if the above stack space is to be considered part of the
1325 space allocated by the caller. */
1326 #define OUTGOING_REG_PARM_STACK_SPACE
1328 /* This is the difference between the logical top of stack and the actual sp.
1330 For the RS/6000, sp points past the fixed area. */
1331 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1333 /* Define this if the maximum size of all the outgoing args is to be
1334 accumulated and pushed during the prologue. The amount can be
1335 found in the variable current_function_outgoing_args_size. */
1336 #define ACCUMULATE_OUTGOING_ARGS 1
1338 /* Value is the number of bytes of arguments automatically
1339 popped when returning from a subroutine call.
1340 FUNDECL is the declaration node of the function (as a tree),
1341 FUNTYPE is the data type of the function (as a tree),
1342 or for a library call it is an identifier node for the subroutine name.
1343 SIZE is the number of bytes of arguments passed on the stack. */
1345 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1347 /* Define how to find the value returned by a function.
1348 VALTYPE is the data type of the value (as a tree).
1349 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1350 otherwise, FUNC is 0. */
1352 #define FUNCTION_VALUE(VALTYPE, FUNC) rs6000_function_value ((VALTYPE), (FUNC))
1354 /* Define how to find the value returned by a library function
1355 assuming the value has mode MODE. */
1357 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1359 /* DRAFT_V4_STRUCT_RET defaults off. */
1360 #define DRAFT_V4_STRUCT_RET 0
1362 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1363 #define DEFAULT_PCC_STRUCT_RETURN 0
1365 /* Mode of stack savearea.
1366 FUNCTION is VOIDmode because calling convention maintains SP.
1367 BLOCK needs Pmode for SP.
1368 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1369 #define STACK_SAVEAREA_MODE(LEVEL) \
1370 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1371 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1373 /* Minimum and maximum general purpose registers used to hold arguments. */
1374 #define GP_ARG_MIN_REG 3
1375 #define GP_ARG_MAX_REG 10
1376 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1378 /* Minimum and maximum floating point registers used to hold arguments. */
1379 #define FP_ARG_MIN_REG 33
1380 #define FP_ARG_AIX_MAX_REG 45
1381 #define FP_ARG_V4_MAX_REG 40
1382 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1383 || DEFAULT_ABI == ABI_DARWIN) \
1384 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1385 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1387 /* Minimum and maximum AltiVec registers used to hold arguments. */
1388 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1389 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1390 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1392 /* Return registers */
1393 #define GP_ARG_RETURN GP_ARG_MIN_REG
1394 #define FP_ARG_RETURN FP_ARG_MIN_REG
1395 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1397 /* Flags for the call/call_value rtl operations set up by function_arg */
1398 #define CALL_NORMAL 0x00000000 /* no special processing */
1399 /* Bits in 0x00000001 are unused. */
1400 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1401 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1402 #define CALL_LONG 0x00000008 /* always call indirect */
1403 #define CALL_LIBCALL 0x00000010 /* libcall */
1405 /* We don't have prologue and epilogue functions to save/restore
1406 everything for most ABIs. */
1407 #define WORLD_SAVE_P(INFO) 0
1409 /* 1 if N is a possible register number for a function value
1410 as seen by the caller.
1412 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1413 #define FUNCTION_VALUE_REGNO_P(N) \
1414 ((N) == GP_ARG_RETURN \
1415 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \
1416 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1418 /* 1 if N is a possible register number for function argument passing.
1419 On RS/6000, these are r3-r10 and fp1-fp13.
1420 On AltiVec, v2 - v13 are used for passing vectors. */
1421 #define FUNCTION_ARG_REGNO_P(N) \
1422 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \
1423 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \
1424 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1425 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \
1426 && TARGET_HARD_FLOAT && TARGET_FPRS))
1428 /* Define a data type for recording info about an argument list
1429 during the scan of that argument list. This data type should
1430 hold all necessary information about the function itself
1431 and about the args processed so far, enough to enable macros
1432 such as FUNCTION_ARG to determine where the next arg should go.
1434 On the RS/6000, this is a structure. The first element is the number of
1435 total argument words, the second is used to store the next
1436 floating-point register number, and the third says how many more args we
1437 have prototype types for.
1439 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1440 the next available GP register, `fregno' is the next available FP
1441 register, and `words' is the number of words used on the stack.
1443 The varargs/stdarg support requires that this structure's size
1444 be a multiple of sizeof(int). */
1446 typedef struct rs6000_args
1448 int words
; /* # words used for passing GP registers */
1449 int fregno
; /* next available FP register */
1450 int vregno
; /* next available AltiVec register */
1451 int nargs_prototype
; /* # args left in the current prototype */
1452 int prototype
; /* Whether a prototype was defined */
1453 int stdarg
; /* Whether function is a stdarg function. */
1454 int call_cookie
; /* Do special things for this call */
1455 int sysv_gregno
; /* next available GP register */
1456 int intoffset
; /* running offset in struct (darwin64) */
1457 int use_stack
; /* any part of struct on stack (darwin64) */
1458 int named
; /* false for varargs params */
1461 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1462 for a call to a function whose data type is FNTYPE.
1463 For a library call, FNTYPE is 0. */
1465 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
1466 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS)
1468 /* Similar, but when scanning the definition of a procedure. We always
1469 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1471 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1472 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000)
1474 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1476 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1477 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0)
1479 /* Update the data in CUM to advance over an argument
1480 of mode MODE and data type TYPE.
1481 (TYPE is null for libcalls where that information may not be available.) */
1483 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1484 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0)
1486 /* Determine where to put an argument to a function.
1487 Value is zero to push the argument on the stack,
1488 or a hard register in which to store the argument.
1490 MODE is the argument's machine mode.
1491 TYPE is the data type of the argument (as a tree).
1492 This is null for libcalls where that information may
1494 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1495 the preceding args and about the function being called.
1496 NAMED is nonzero if this argument is a named parameter
1497 (otherwise it is an extra parameter matching an ellipsis).
1499 On RS/6000 the first eight words of non-FP are normally in registers
1500 and the rest are pushed. The first 13 FP args are in registers.
1502 If this is floating-point and no prototype is specified, we use
1503 both an FP and integer register (or possibly FP reg and stack). Library
1504 functions (when TYPE is zero) always have the proper types for args,
1505 so we can pass the FP value just in one register. emit_library_function
1506 doesn't support EXPR_LIST anyway. */
1508 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1509 function_arg (&CUM, MODE, TYPE, NAMED)
1511 /* If defined, a C expression which determines whether, and in which
1512 direction, to pad out an argument with extra space. The value
1513 should be of type `enum direction': either `upward' to pad above
1514 the argument, `downward' to pad below, or `none' to inhibit
1517 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1519 /* If defined, a C expression that gives the alignment boundary, in bits,
1520 of an argument with the specified mode and type. If it is not defined,
1521 PARM_BOUNDARY is used for all arguments. */
1523 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1524 function_arg_boundary (MODE, TYPE)
1526 /* Implement `va_start' for varargs and stdarg. */
1527 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1528 rs6000_va_start (valist, nextarg)
1530 #define PAD_VARARGS_DOWN \
1531 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1533 /* Output assembler code to FILE to increment profiler label # LABELNO
1534 for profiling a function entry. */
1536 #define FUNCTION_PROFILER(FILE, LABELNO) \
1537 output_function_profiler ((FILE), (LABELNO));
1539 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1540 the stack pointer does not matter. No definition is equivalent to
1543 On the RS/6000, this is nonzero because we can restore the stack from
1544 its backpointer, which we maintain. */
1545 #define EXIT_IGNORE_STACK 1
1547 /* Define this macro as a C expression that is nonzero for registers
1548 that are used by the epilogue or the return' pattern. The stack
1549 and frame pointer registers are already be assumed to be used as
1552 #define EPILOGUE_USES(REGNO) \
1553 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1554 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1555 || (current_function_calls_eh_return \
1560 /* TRAMPOLINE_TEMPLATE deleted */
1562 /* Length in units of the trampoline for entering a nested function. */
1564 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1566 /* Emit RTL insns to initialize the variable parts of a trampoline.
1567 FNADDR is an RTX for the address of the function's pure code.
1568 CXT is an RTX for the static chain value for the function. */
1570 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1571 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1573 /* Definitions for __builtin_return_address and __builtin_frame_address.
1574 __builtin_return_address (0) should give link register (65), enable
1576 /* This should be uncommented, so that the link register is used, but
1577 currently this would result in unmatched insns and spilling fixed
1578 registers so we'll leave it for another day. When these problems are
1579 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1581 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1583 /* Number of bytes into the frame return addresses can be found. See
1584 rs6000_stack_info in rs6000.c for more information on how the different
1585 abi's store the return address. */
1586 #define RETURN_ADDRESS_OFFSET \
1587 ((DEFAULT_ABI == ABI_AIX \
1588 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \
1589 (DEFAULT_ABI == ABI_V4) ? 4 : \
1590 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1592 /* The current return address is in link register (65). The return address
1593 of anything farther back is accessed normally at an offset of 8 from the
1595 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1596 (rs6000_return_addr (COUNT, FRAME))
1599 /* Definitions for register eliminations.
1601 We have two registers that can be eliminated on the RS/6000. First, the
1602 frame pointer register can often be eliminated in favor of the stack
1603 pointer register. Secondly, the argument pointer register can always be
1604 eliminated; it is replaced with either the stack or frame pointer.
1606 In addition, we use the elimination mechanism to see if r30 is needed
1607 Initially we assume that it isn't. If it is, we spill it. This is done
1608 by making it an eliminable register. We replace it with itself so that
1609 if it isn't needed, then existing uses won't be modified. */
1611 /* This is an array of structures. Each structure initializes one pair
1612 of eliminable registers. The "from" register number is given first,
1613 followed by "to". Eliminations of the same "from" register are listed
1614 in order of preference. */
1615 #define ELIMINABLE_REGS \
1616 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1617 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1618 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1619 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1620 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1621 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1623 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1624 Frame pointer elimination is automatically handled.
1626 For the RS/6000, if frame pointer elimination is being done, we would like
1627 to convert ap into fp, not sp.
1629 We need r30 if -mminimal-toc was specified, and there are constant pool
1632 #define CAN_ELIMINATE(FROM, TO) \
1633 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1634 ? ! frame_pointer_needed \
1635 : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \
1636 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1639 /* Define the offset between two registers, one to be eliminated, and the other
1640 its replacement, at the start of a routine. */
1641 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1642 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1644 /* Addressing modes, and classification of registers for them. */
1646 #define HAVE_PRE_DECREMENT 1
1647 #define HAVE_PRE_INCREMENT 1
1649 /* Macros to check register numbers against specific register classes. */
1651 /* These assume that REGNO is a hard or pseudo reg number.
1652 They give nonzero only if REGNO is a hard reg of the suitable class
1653 or a pseudo reg currently allocated to a suitable hard reg.
1654 Since they use reg_renumber, they are safe only once reg_renumber
1655 has been allocated, which happens in local-alloc.c. */
1657 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1658 ((REGNO) < FIRST_PSEUDO_REGISTER \
1659 ? (REGNO) <= 31 || (REGNO) == 67 \
1660 || (REGNO) == FRAME_POINTER_REGNUM \
1661 : (reg_renumber[REGNO] >= 0 \
1662 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1663 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1665 #define REGNO_OK_FOR_BASE_P(REGNO) \
1666 ((REGNO) < FIRST_PSEUDO_REGISTER \
1667 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1668 || (REGNO) == FRAME_POINTER_REGNUM \
1669 : (reg_renumber[REGNO] > 0 \
1670 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1671 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1673 /* Maximum number of registers that can appear in a valid memory address. */
1675 #define MAX_REGS_PER_ADDRESS 2
1677 /* Recognize any constant value that is a valid address. */
1679 #define CONSTANT_ADDRESS_P(X) \
1680 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1681 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1682 || GET_CODE (X) == HIGH)
1684 /* Nonzero if the constant value X is a legitimate general operand.
1685 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1687 On the RS/6000, all integer constants are acceptable, most won't be valid
1688 for particular insns, though. Only easy FP constants are
1691 #define LEGITIMATE_CONSTANT_P(X) \
1692 (((GET_CODE (X) != CONST_DOUBLE \
1693 && GET_CODE (X) != CONST_VECTOR) \
1694 || GET_MODE (X) == VOIDmode \
1695 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1696 || easy_fp_constant (X, GET_MODE (X)) \
1697 || easy_vector_constant (X, GET_MODE (X))) \
1698 && !rs6000_tls_referenced_p (X))
1700 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1701 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1702 && EASY_VECTOR_15((n) >> 1))
1704 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1705 and check its validity for a certain class.
1706 We have two alternate definitions for each of them.
1707 The usual definition accepts all pseudo regs; the other rejects
1708 them unless they have been allocated suitable hard regs.
1709 The symbol REG_OK_STRICT causes the latter definition to be used.
1711 Most source files want to accept pseudo regs in the hope that
1712 they will get allocated to the class that the insn wants them to be in.
1713 Source files for reload pass need to be strict.
1714 After reload, it makes no difference, since pseudo regs have
1715 been eliminated by then. */
1717 #ifdef REG_OK_STRICT
1718 # define REG_OK_STRICT_FLAG 1
1720 # define REG_OK_STRICT_FLAG 0
1723 /* Nonzero if X is a hard reg that can be used as an index
1724 or if it is a pseudo reg in the non-strict case. */
1725 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1727 && (REGNO (X) <= 31 \
1728 || REGNO (X) == ARG_POINTER_REGNUM \
1729 || REGNO (X) == FRAME_POINTER_REGNUM \
1730 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1731 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1733 /* Nonzero if X is a hard reg that can be used as a base reg
1734 or if it is a pseudo reg in the non-strict case. */
1735 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1736 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1738 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1739 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1741 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1742 that is a valid memory address for an instruction.
1743 The MODE argument is the machine mode for the MEM expression
1744 that wants to use this address.
1746 On the RS/6000, there are four valid address: a SYMBOL_REF that
1747 refers to a constant pool entry of an address (or the sum of it
1748 plus a constant), a short (16-bit signed) constant plus a register,
1749 the sum of two registers, or a register indirect, possibly with an
1750 auto-increment. For DFmode and DImode with a constant plus register,
1751 we must ensure that both words are addressable or PowerPC64 with offset
1754 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1755 32-bit DImode, TImode), indexed addressing cannot be used because
1756 adjacent memory cells are accessed by adding word-sized offsets
1757 during assembly output. */
1759 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1760 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
1764 /* Try machine-dependent ways of modifying an illegitimate address
1765 to be legitimate. If we find one, return the new, valid address.
1766 This macro is used in only one place: `memory_address' in explow.c.
1768 OLDX is the address as it was before break_out_memory_refs was called.
1769 In some cases it is useful to look at this to decide what needs to be done.
1771 MODE and WIN are passed so that this macro can use
1772 GO_IF_LEGITIMATE_ADDRESS.
1774 It is always safe for this macro to do nothing. It exists to recognize
1775 opportunities to optimize the output.
1777 On RS/6000, first check for the sum of a register with a constant
1778 integer that is out of range. If so, generate code to add the
1779 constant with the low-order 16 bits masked to the register and force
1780 this result into another register (this can be done with `cau').
1781 Then generate an address of REG+(CONST&0xffff), allowing for the
1782 possibility of bit 16 being a one.
1784 Then check for the sum of a register and something not constant, try to
1785 load the other things into a register and return the sum. */
1787 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1788 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
1789 if (result != NULL_RTX) \
1796 /* Try a machine-dependent way of reloading an illegitimate address
1797 operand. If we find one, push the reload and jump to WIN. This
1798 macro is used in only one place: `find_reloads_address' in reload.c.
1800 Implemented on rs6000 by rs6000_legitimize_reload_address.
1801 Note that (X) is evaluated twice; this is safe in current usage. */
1803 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1806 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
1807 (int)(TYPE), (IND_LEVELS), &win); \
1812 /* Go to LABEL if ADDR (a legitimate address expression)
1813 has an effect that depends on the machine mode it is used for. */
1815 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1817 if (rs6000_mode_dependent_address (ADDR)) \
1821 /* The register number of the register used to address a table of
1822 static data addresses in memory. In some cases this register is
1823 defined by a processor's "application binary interface" (ABI).
1824 When this macro is defined, RTL is generated for this register
1825 once, as with the stack pointer and frame pointer registers. If
1826 this macro is not defined, it is up to the machine-dependent files
1827 to allocate such a register (if necessary). */
1829 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1830 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
1832 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1834 /* Define this macro if the register defined by
1835 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1836 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1838 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1840 /* A C expression that is nonzero if X is a legitimate immediate
1841 operand on the target machine when generating position independent
1842 code. You can assume that X satisfies `CONSTANT_P', so you need
1843 not check this. You can also assume FLAG_PIC is true, so you need
1844 not check it either. You need not define this macro if all
1845 constants (including `SYMBOL_REF') can be immediate operands when
1846 generating position independent code. */
1848 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1850 /* Define this if some processing needs to be done immediately before
1851 emitting code for an insn. */
1853 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
1855 /* Specify the machine mode that this machine uses
1856 for the index in the tablejump instruction. */
1857 #define CASE_VECTOR_MODE SImode
1859 /* Define as C expression which evaluates to nonzero if the tablejump
1860 instruction expects the table to contain offsets from the address of the
1862 Do not define this if the table should contain absolute addresses. */
1863 #define CASE_VECTOR_PC_RELATIVE 1
1865 /* Define this as 1 if `char' should by default be signed; else as 0. */
1866 #define DEFAULT_SIGNED_CHAR 0
1868 /* This flag, if defined, says the same insns that convert to a signed fixnum
1869 also convert validly to an unsigned one. */
1871 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
1873 /* An integer expression for the size in bits of the largest integer machine
1874 mode that should actually be used. */
1876 /* Allow pairs of registers to be used, which is the intent of the default. */
1877 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1879 /* Max number of bytes we can move from memory to memory
1880 in one reasonably fast instruction. */
1881 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1882 #define MAX_MOVE_MAX 8
1884 /* Nonzero if access to memory by bytes is no faster than for words.
1885 Also nonzero if doing byte operations (specifically shifts) in registers
1887 #define SLOW_BYTE_ACCESS 1
1889 /* Define if operations between registers always perform the operation
1890 on the full register even if a narrower mode is specified. */
1891 #define WORD_REGISTER_OPERATIONS
1893 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1894 will either zero-extend or sign-extend. The value of this macro should
1895 be the code that says which one of the two operations is implicitly
1896 done, UNKNOWN if none. */
1897 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1899 /* Define if loading short immediate values into registers sign extends. */
1900 #define SHORT_IMMEDIATES_SIGN_EXTEND
1902 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1903 is done just by pretending it is already truncated. */
1904 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1906 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1907 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1908 ((VALUE) = ((MODE) == SImode ? 32 : 64))
1910 /* The CTZ patterns return -1 for input of zero. */
1911 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1)
1913 /* Specify the machine mode that pointers have.
1914 After generation of rtl, the compiler makes no further distinction
1915 between pointers and any other objects of this machine mode. */
1916 #define Pmode (TARGET_32BIT ? SImode : DImode)
1918 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1919 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1921 /* Mode of a function address in a call instruction (for indexing purposes).
1922 Doesn't matter on RS/6000. */
1923 #define FUNCTION_MODE SImode
1925 /* Define this if addresses of constant functions
1926 shouldn't be put through pseudo regs where they can be cse'd.
1927 Desirable on machines where ordinary constants are expensive
1928 but a CALL with constant address is cheap. */
1929 #define NO_FUNCTION_CSE
1931 /* Define this to be nonzero if shift instructions ignore all but the low-order
1934 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1935 have been dropped from the PowerPC architecture. */
1937 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
1939 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1940 should be adjusted to reflect any required changes. This macro is used when
1941 there is some systematic length adjustment required that would be difficult
1942 to express in the length attribute. */
1944 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1946 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1947 COMPARE, return the mode to be used for the comparison. For
1948 floating-point, CCFPmode should be used. CCUNSmode should be used
1949 for unsigned comparisons. CCEQmode should be used when we are
1950 doing an inequality comparison on the result of a
1951 comparison. CCmode should be used in all other cases. */
1953 #define SELECT_CC_MODE(OP,X,Y) \
1954 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1955 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1956 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1957 ? CCEQmode : CCmode))
1959 /* Can the condition code MODE be safely reversed? This is safe in
1960 all cases on this port, because at present it doesn't use the
1961 trapping FP comparisons (fcmpo). */
1962 #define REVERSIBLE_CC_MODE(MODE) 1
1964 /* Given a condition code and a mode, return the inverse condition. */
1965 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1967 /* Define the information needed to generate branch and scc insns. This is
1968 stored from the compare operation. */
1970 extern GTY(()) rtx rs6000_compare_op0
;
1971 extern GTY(()) rtx rs6000_compare_op1
;
1972 extern int rs6000_compare_fp_p
;
1974 /* Control the assembler format that we output. */
1976 /* A C string constant describing how to begin a comment in the target
1977 assembler language. The compiler assumes that the comment will end at
1978 the end of the line. */
1979 #define ASM_COMMENT_START " #"
1981 /* Flag to say the TOC is initialized */
1982 extern int toc_initialized
;
1984 /* Macro to output a special constant pool entry. Go to WIN if we output
1985 it. Otherwise, it is written the usual way.
1987 On the RS/6000, toc entries are handled this way. */
1989 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1990 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1992 output_toc (FILE, X, LABELNO, MODE); \
1997 #ifdef HAVE_GAS_WEAK
1998 #define RS6000_WEAK 1
2000 #define RS6000_WEAK 0
2004 /* Used in lieu of ASM_WEAKEN_LABEL. */
2005 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2008 fputs ("\t.weak\t", (FILE)); \
2009 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2010 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2011 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2014 fputs ("[DS]", (FILE)); \
2015 fputs ("\n\t.weak\t.", (FILE)); \
2016 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2018 fputc ('\n', (FILE)); \
2021 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2022 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2023 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2025 fputs ("\t.set\t.", (FILE)); \
2026 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2027 fputs (",.", (FILE)); \
2028 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2029 fputc ('\n', (FILE)); \
2036 #if HAVE_GAS_WEAKREF
2037 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2040 fputs ("\t.weakref\t", (FILE)); \
2041 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2042 fputs (", ", (FILE)); \
2043 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2044 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2045 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2047 fputs ("\n\t.weakref\t.", (FILE)); \
2048 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2049 fputs (", .", (FILE)); \
2050 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2052 fputc ('\n', (FILE)); \
2056 /* This implements the `alias' attribute. */
2057 #undef ASM_OUTPUT_DEF_FROM_DECLS
2058 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2061 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2062 const char *name = IDENTIFIER_POINTER (TARGET); \
2063 if (TREE_CODE (DECL) == FUNCTION_DECL \
2064 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2066 if (TREE_PUBLIC (DECL)) \
2068 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2070 fputs ("\t.globl\t.", FILE); \
2071 RS6000_OUTPUT_BASENAME (FILE, alias); \
2072 putc ('\n', FILE); \
2075 else if (TARGET_XCOFF) \
2077 fputs ("\t.lglobl\t.", FILE); \
2078 RS6000_OUTPUT_BASENAME (FILE, alias); \
2079 putc ('\n', FILE); \
2081 fputs ("\t.set\t.", FILE); \
2082 RS6000_OUTPUT_BASENAME (FILE, alias); \
2083 fputs (",.", FILE); \
2084 RS6000_OUTPUT_BASENAME (FILE, name); \
2085 fputc ('\n', FILE); \
2087 ASM_OUTPUT_DEF (FILE, alias, name); \
2091 #define TARGET_ASM_FILE_START rs6000_file_start
2093 /* Output to assembler file text saying following lines
2094 may contain character constants, extra white space, comments, etc. */
2096 #define ASM_APP_ON ""
2098 /* Output to assembler file text saying following lines
2099 no longer contain unusual constructs. */
2101 #define ASM_APP_OFF ""
2103 /* How to refer to registers in assembler output.
2104 This sequence is indexed by compiler's hard-register-number (see above). */
2106 extern char rs6000_reg_names
[][8]; /* register names (0 vs. %r0). */
2108 #define REGISTER_NAMES \
2110 &rs6000_reg_names[ 0][0], /* r0 */ \
2111 &rs6000_reg_names[ 1][0], /* r1 */ \
2112 &rs6000_reg_names[ 2][0], /* r2 */ \
2113 &rs6000_reg_names[ 3][0], /* r3 */ \
2114 &rs6000_reg_names[ 4][0], /* r4 */ \
2115 &rs6000_reg_names[ 5][0], /* r5 */ \
2116 &rs6000_reg_names[ 6][0], /* r6 */ \
2117 &rs6000_reg_names[ 7][0], /* r7 */ \
2118 &rs6000_reg_names[ 8][0], /* r8 */ \
2119 &rs6000_reg_names[ 9][0], /* r9 */ \
2120 &rs6000_reg_names[10][0], /* r10 */ \
2121 &rs6000_reg_names[11][0], /* r11 */ \
2122 &rs6000_reg_names[12][0], /* r12 */ \
2123 &rs6000_reg_names[13][0], /* r13 */ \
2124 &rs6000_reg_names[14][0], /* r14 */ \
2125 &rs6000_reg_names[15][0], /* r15 */ \
2126 &rs6000_reg_names[16][0], /* r16 */ \
2127 &rs6000_reg_names[17][0], /* r17 */ \
2128 &rs6000_reg_names[18][0], /* r18 */ \
2129 &rs6000_reg_names[19][0], /* r19 */ \
2130 &rs6000_reg_names[20][0], /* r20 */ \
2131 &rs6000_reg_names[21][0], /* r21 */ \
2132 &rs6000_reg_names[22][0], /* r22 */ \
2133 &rs6000_reg_names[23][0], /* r23 */ \
2134 &rs6000_reg_names[24][0], /* r24 */ \
2135 &rs6000_reg_names[25][0], /* r25 */ \
2136 &rs6000_reg_names[26][0], /* r26 */ \
2137 &rs6000_reg_names[27][0], /* r27 */ \
2138 &rs6000_reg_names[28][0], /* r28 */ \
2139 &rs6000_reg_names[29][0], /* r29 */ \
2140 &rs6000_reg_names[30][0], /* r30 */ \
2141 &rs6000_reg_names[31][0], /* r31 */ \
2143 &rs6000_reg_names[32][0], /* fr0 */ \
2144 &rs6000_reg_names[33][0], /* fr1 */ \
2145 &rs6000_reg_names[34][0], /* fr2 */ \
2146 &rs6000_reg_names[35][0], /* fr3 */ \
2147 &rs6000_reg_names[36][0], /* fr4 */ \
2148 &rs6000_reg_names[37][0], /* fr5 */ \
2149 &rs6000_reg_names[38][0], /* fr6 */ \
2150 &rs6000_reg_names[39][0], /* fr7 */ \
2151 &rs6000_reg_names[40][0], /* fr8 */ \
2152 &rs6000_reg_names[41][0], /* fr9 */ \
2153 &rs6000_reg_names[42][0], /* fr10 */ \
2154 &rs6000_reg_names[43][0], /* fr11 */ \
2155 &rs6000_reg_names[44][0], /* fr12 */ \
2156 &rs6000_reg_names[45][0], /* fr13 */ \
2157 &rs6000_reg_names[46][0], /* fr14 */ \
2158 &rs6000_reg_names[47][0], /* fr15 */ \
2159 &rs6000_reg_names[48][0], /* fr16 */ \
2160 &rs6000_reg_names[49][0], /* fr17 */ \
2161 &rs6000_reg_names[50][0], /* fr18 */ \
2162 &rs6000_reg_names[51][0], /* fr19 */ \
2163 &rs6000_reg_names[52][0], /* fr20 */ \
2164 &rs6000_reg_names[53][0], /* fr21 */ \
2165 &rs6000_reg_names[54][0], /* fr22 */ \
2166 &rs6000_reg_names[55][0], /* fr23 */ \
2167 &rs6000_reg_names[56][0], /* fr24 */ \
2168 &rs6000_reg_names[57][0], /* fr25 */ \
2169 &rs6000_reg_names[58][0], /* fr26 */ \
2170 &rs6000_reg_names[59][0], /* fr27 */ \
2171 &rs6000_reg_names[60][0], /* fr28 */ \
2172 &rs6000_reg_names[61][0], /* fr29 */ \
2173 &rs6000_reg_names[62][0], /* fr30 */ \
2174 &rs6000_reg_names[63][0], /* fr31 */ \
2176 &rs6000_reg_names[64][0], /* mq */ \
2177 &rs6000_reg_names[65][0], /* lr */ \
2178 &rs6000_reg_names[66][0], /* ctr */ \
2179 &rs6000_reg_names[67][0], /* ap */ \
2181 &rs6000_reg_names[68][0], /* cr0 */ \
2182 &rs6000_reg_names[69][0], /* cr1 */ \
2183 &rs6000_reg_names[70][0], /* cr2 */ \
2184 &rs6000_reg_names[71][0], /* cr3 */ \
2185 &rs6000_reg_names[72][0], /* cr4 */ \
2186 &rs6000_reg_names[73][0], /* cr5 */ \
2187 &rs6000_reg_names[74][0], /* cr6 */ \
2188 &rs6000_reg_names[75][0], /* cr7 */ \
2190 &rs6000_reg_names[76][0], /* xer */ \
2192 &rs6000_reg_names[77][0], /* v0 */ \
2193 &rs6000_reg_names[78][0], /* v1 */ \
2194 &rs6000_reg_names[79][0], /* v2 */ \
2195 &rs6000_reg_names[80][0], /* v3 */ \
2196 &rs6000_reg_names[81][0], /* v4 */ \
2197 &rs6000_reg_names[82][0], /* v5 */ \
2198 &rs6000_reg_names[83][0], /* v6 */ \
2199 &rs6000_reg_names[84][0], /* v7 */ \
2200 &rs6000_reg_names[85][0], /* v8 */ \
2201 &rs6000_reg_names[86][0], /* v9 */ \
2202 &rs6000_reg_names[87][0], /* v10 */ \
2203 &rs6000_reg_names[88][0], /* v11 */ \
2204 &rs6000_reg_names[89][0], /* v12 */ \
2205 &rs6000_reg_names[90][0], /* v13 */ \
2206 &rs6000_reg_names[91][0], /* v14 */ \
2207 &rs6000_reg_names[92][0], /* v15 */ \
2208 &rs6000_reg_names[93][0], /* v16 */ \
2209 &rs6000_reg_names[94][0], /* v17 */ \
2210 &rs6000_reg_names[95][0], /* v18 */ \
2211 &rs6000_reg_names[96][0], /* v19 */ \
2212 &rs6000_reg_names[97][0], /* v20 */ \
2213 &rs6000_reg_names[98][0], /* v21 */ \
2214 &rs6000_reg_names[99][0], /* v22 */ \
2215 &rs6000_reg_names[100][0], /* v23 */ \
2216 &rs6000_reg_names[101][0], /* v24 */ \
2217 &rs6000_reg_names[102][0], /* v25 */ \
2218 &rs6000_reg_names[103][0], /* v26 */ \
2219 &rs6000_reg_names[104][0], /* v27 */ \
2220 &rs6000_reg_names[105][0], /* v28 */ \
2221 &rs6000_reg_names[106][0], /* v29 */ \
2222 &rs6000_reg_names[107][0], /* v30 */ \
2223 &rs6000_reg_names[108][0], /* v31 */ \
2224 &rs6000_reg_names[109][0], /* vrsave */ \
2225 &rs6000_reg_names[110][0], /* vscr */ \
2226 &rs6000_reg_names[111][0], /* spe_acc */ \
2227 &rs6000_reg_names[112][0], /* spefscr */ \
2228 &rs6000_reg_names[113][0], /* sfp */ \
2231 /* Table of additional register names to use in user input. */
2233 #define ADDITIONAL_REGISTER_NAMES \
2234 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2235 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2236 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2237 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2238 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2239 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2240 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2241 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2242 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2243 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2244 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2245 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2246 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2247 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2248 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2249 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2250 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2251 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2252 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2253 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2254 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2255 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2256 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2257 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2258 {"vrsave", 109}, {"vscr", 110}, \
2259 {"spe_acc", 111}, {"spefscr", 112}, \
2260 /* no additional names for: mq, lr, ctr, ap */ \
2261 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2262 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2263 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2265 /* Text to write out after a CALL that may be replaced by glue code by
2266 the loader. This depends on the AIX version. */
2267 #define RS6000_CALL_GLUE "cror 31,31,31"
2269 /* This is how to output an element of a case-vector that is relative. */
2271 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2272 do { char buf[100]; \
2273 fputs ("\t.long ", FILE); \
2274 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2275 assemble_name (FILE, buf); \
2277 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2278 assemble_name (FILE, buf); \
2279 putc ('\n', FILE); \
2282 /* This is how to output an assembler line
2283 that says to advance the location counter
2284 to a multiple of 2**LOG bytes. */
2286 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2288 fprintf (FILE, "\t.align %d\n", (LOG))
2290 /* Pick up the return address upon entry to a procedure. Used for
2291 dwarf2 unwind information. This also enables the table driven
2294 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2295 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2297 /* Describe how we implement __builtin_eh_return. */
2298 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2299 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2301 /* Print operand X (an rtx) in assembler syntax to file FILE.
2302 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2303 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2305 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2307 /* Define which CODE values are valid. */
2309 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2310 ((CODE) == '.' || (CODE) == '&')
2312 /* Print a memory address as an operand to reference that memory location. */
2314 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2316 /* uncomment for disabling the corresponding default options */
2317 /* #define MACHINE_no_sched_interblock */
2318 /* #define MACHINE_no_sched_speculative */
2319 /* #define MACHINE_no_sched_speculative_load */
2321 /* General flags. */
2322 extern int flag_pic
;
2323 extern int optimize
;
2324 extern int flag_expensive_optimizations
;
2325 extern int frame_pointer_needed
;
2327 enum rs6000_builtins
2329 /* AltiVec builtins. */
2330 ALTIVEC_BUILTIN_ST_INTERNAL_4si
,
2331 ALTIVEC_BUILTIN_LD_INTERNAL_4si
,
2332 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
,
2333 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
,
2334 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
,
2335 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
,
2336 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
,
2337 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
,
2338 ALTIVEC_BUILTIN_VADDUBM
,
2339 ALTIVEC_BUILTIN_VADDUHM
,
2340 ALTIVEC_BUILTIN_VADDUWM
,
2341 ALTIVEC_BUILTIN_VADDFP
,
2342 ALTIVEC_BUILTIN_VADDCUW
,
2343 ALTIVEC_BUILTIN_VADDUBS
,
2344 ALTIVEC_BUILTIN_VADDSBS
,
2345 ALTIVEC_BUILTIN_VADDUHS
,
2346 ALTIVEC_BUILTIN_VADDSHS
,
2347 ALTIVEC_BUILTIN_VADDUWS
,
2348 ALTIVEC_BUILTIN_VADDSWS
,
2349 ALTIVEC_BUILTIN_VAND
,
2350 ALTIVEC_BUILTIN_VANDC
,
2351 ALTIVEC_BUILTIN_VAVGUB
,
2352 ALTIVEC_BUILTIN_VAVGSB
,
2353 ALTIVEC_BUILTIN_VAVGUH
,
2354 ALTIVEC_BUILTIN_VAVGSH
,
2355 ALTIVEC_BUILTIN_VAVGUW
,
2356 ALTIVEC_BUILTIN_VAVGSW
,
2357 ALTIVEC_BUILTIN_VCFUX
,
2358 ALTIVEC_BUILTIN_VCFSX
,
2359 ALTIVEC_BUILTIN_VCTSXS
,
2360 ALTIVEC_BUILTIN_VCTUXS
,
2361 ALTIVEC_BUILTIN_VCMPBFP
,
2362 ALTIVEC_BUILTIN_VCMPEQUB
,
2363 ALTIVEC_BUILTIN_VCMPEQUH
,
2364 ALTIVEC_BUILTIN_VCMPEQUW
,
2365 ALTIVEC_BUILTIN_VCMPEQFP
,
2366 ALTIVEC_BUILTIN_VCMPGEFP
,
2367 ALTIVEC_BUILTIN_VCMPGTUB
,
2368 ALTIVEC_BUILTIN_VCMPGTSB
,
2369 ALTIVEC_BUILTIN_VCMPGTUH
,
2370 ALTIVEC_BUILTIN_VCMPGTSH
,
2371 ALTIVEC_BUILTIN_VCMPGTUW
,
2372 ALTIVEC_BUILTIN_VCMPGTSW
,
2373 ALTIVEC_BUILTIN_VCMPGTFP
,
2374 ALTIVEC_BUILTIN_VEXPTEFP
,
2375 ALTIVEC_BUILTIN_VLOGEFP
,
2376 ALTIVEC_BUILTIN_VMADDFP
,
2377 ALTIVEC_BUILTIN_VMAXUB
,
2378 ALTIVEC_BUILTIN_VMAXSB
,
2379 ALTIVEC_BUILTIN_VMAXUH
,
2380 ALTIVEC_BUILTIN_VMAXSH
,
2381 ALTIVEC_BUILTIN_VMAXUW
,
2382 ALTIVEC_BUILTIN_VMAXSW
,
2383 ALTIVEC_BUILTIN_VMAXFP
,
2384 ALTIVEC_BUILTIN_VMHADDSHS
,
2385 ALTIVEC_BUILTIN_VMHRADDSHS
,
2386 ALTIVEC_BUILTIN_VMLADDUHM
,
2387 ALTIVEC_BUILTIN_VMRGHB
,
2388 ALTIVEC_BUILTIN_VMRGHH
,
2389 ALTIVEC_BUILTIN_VMRGHW
,
2390 ALTIVEC_BUILTIN_VMRGLB
,
2391 ALTIVEC_BUILTIN_VMRGLH
,
2392 ALTIVEC_BUILTIN_VMRGLW
,
2393 ALTIVEC_BUILTIN_VMSUMUBM
,
2394 ALTIVEC_BUILTIN_VMSUMMBM
,
2395 ALTIVEC_BUILTIN_VMSUMUHM
,
2396 ALTIVEC_BUILTIN_VMSUMSHM
,
2397 ALTIVEC_BUILTIN_VMSUMUHS
,
2398 ALTIVEC_BUILTIN_VMSUMSHS
,
2399 ALTIVEC_BUILTIN_VMINUB
,
2400 ALTIVEC_BUILTIN_VMINSB
,
2401 ALTIVEC_BUILTIN_VMINUH
,
2402 ALTIVEC_BUILTIN_VMINSH
,
2403 ALTIVEC_BUILTIN_VMINUW
,
2404 ALTIVEC_BUILTIN_VMINSW
,
2405 ALTIVEC_BUILTIN_VMINFP
,
2406 ALTIVEC_BUILTIN_VMULEUB
,
2407 ALTIVEC_BUILTIN_VMULESB
,
2408 ALTIVEC_BUILTIN_VMULEUH
,
2409 ALTIVEC_BUILTIN_VMULESH
,
2410 ALTIVEC_BUILTIN_VMULOUB
,
2411 ALTIVEC_BUILTIN_VMULOSB
,
2412 ALTIVEC_BUILTIN_VMULOUH
,
2413 ALTIVEC_BUILTIN_VMULOSH
,
2414 ALTIVEC_BUILTIN_VNMSUBFP
,
2415 ALTIVEC_BUILTIN_VNOR
,
2416 ALTIVEC_BUILTIN_VOR
,
2417 ALTIVEC_BUILTIN_VSEL_4SI
,
2418 ALTIVEC_BUILTIN_VSEL_4SF
,
2419 ALTIVEC_BUILTIN_VSEL_8HI
,
2420 ALTIVEC_BUILTIN_VSEL_16QI
,
2421 ALTIVEC_BUILTIN_VPERM_4SI
,
2422 ALTIVEC_BUILTIN_VPERM_4SF
,
2423 ALTIVEC_BUILTIN_VPERM_8HI
,
2424 ALTIVEC_BUILTIN_VPERM_16QI
,
2425 ALTIVEC_BUILTIN_VPKUHUM
,
2426 ALTIVEC_BUILTIN_VPKUWUM
,
2427 ALTIVEC_BUILTIN_VPKPX
,
2428 ALTIVEC_BUILTIN_VPKUHSS
,
2429 ALTIVEC_BUILTIN_VPKSHSS
,
2430 ALTIVEC_BUILTIN_VPKUWSS
,
2431 ALTIVEC_BUILTIN_VPKSWSS
,
2432 ALTIVEC_BUILTIN_VPKUHUS
,
2433 ALTIVEC_BUILTIN_VPKSHUS
,
2434 ALTIVEC_BUILTIN_VPKUWUS
,
2435 ALTIVEC_BUILTIN_VPKSWUS
,
2436 ALTIVEC_BUILTIN_VREFP
,
2437 ALTIVEC_BUILTIN_VRFIM
,
2438 ALTIVEC_BUILTIN_VRFIN
,
2439 ALTIVEC_BUILTIN_VRFIP
,
2440 ALTIVEC_BUILTIN_VRFIZ
,
2441 ALTIVEC_BUILTIN_VRLB
,
2442 ALTIVEC_BUILTIN_VRLH
,
2443 ALTIVEC_BUILTIN_VRLW
,
2444 ALTIVEC_BUILTIN_VRSQRTEFP
,
2445 ALTIVEC_BUILTIN_VSLB
,
2446 ALTIVEC_BUILTIN_VSLH
,
2447 ALTIVEC_BUILTIN_VSLW
,
2448 ALTIVEC_BUILTIN_VSL
,
2449 ALTIVEC_BUILTIN_VSLO
,
2450 ALTIVEC_BUILTIN_VSPLTB
,
2451 ALTIVEC_BUILTIN_VSPLTH
,
2452 ALTIVEC_BUILTIN_VSPLTW
,
2453 ALTIVEC_BUILTIN_VSPLTISB
,
2454 ALTIVEC_BUILTIN_VSPLTISH
,
2455 ALTIVEC_BUILTIN_VSPLTISW
,
2456 ALTIVEC_BUILTIN_VSRB
,
2457 ALTIVEC_BUILTIN_VSRH
,
2458 ALTIVEC_BUILTIN_VSRW
,
2459 ALTIVEC_BUILTIN_VSRAB
,
2460 ALTIVEC_BUILTIN_VSRAH
,
2461 ALTIVEC_BUILTIN_VSRAW
,
2462 ALTIVEC_BUILTIN_VSR
,
2463 ALTIVEC_BUILTIN_VSRO
,
2464 ALTIVEC_BUILTIN_VSUBUBM
,
2465 ALTIVEC_BUILTIN_VSUBUHM
,
2466 ALTIVEC_BUILTIN_VSUBUWM
,
2467 ALTIVEC_BUILTIN_VSUBFP
,
2468 ALTIVEC_BUILTIN_VSUBCUW
,
2469 ALTIVEC_BUILTIN_VSUBUBS
,
2470 ALTIVEC_BUILTIN_VSUBSBS
,
2471 ALTIVEC_BUILTIN_VSUBUHS
,
2472 ALTIVEC_BUILTIN_VSUBSHS
,
2473 ALTIVEC_BUILTIN_VSUBUWS
,
2474 ALTIVEC_BUILTIN_VSUBSWS
,
2475 ALTIVEC_BUILTIN_VSUM4UBS
,
2476 ALTIVEC_BUILTIN_VSUM4SBS
,
2477 ALTIVEC_BUILTIN_VSUM4SHS
,
2478 ALTIVEC_BUILTIN_VSUM2SWS
,
2479 ALTIVEC_BUILTIN_VSUMSWS
,
2480 ALTIVEC_BUILTIN_VXOR
,
2481 ALTIVEC_BUILTIN_VSLDOI_16QI
,
2482 ALTIVEC_BUILTIN_VSLDOI_8HI
,
2483 ALTIVEC_BUILTIN_VSLDOI_4SI
,
2484 ALTIVEC_BUILTIN_VSLDOI_4SF
,
2485 ALTIVEC_BUILTIN_VUPKHSB
,
2486 ALTIVEC_BUILTIN_VUPKHPX
,
2487 ALTIVEC_BUILTIN_VUPKHSH
,
2488 ALTIVEC_BUILTIN_VUPKLSB
,
2489 ALTIVEC_BUILTIN_VUPKLPX
,
2490 ALTIVEC_BUILTIN_VUPKLSH
,
2491 ALTIVEC_BUILTIN_MTVSCR
,
2492 ALTIVEC_BUILTIN_MFVSCR
,
2493 ALTIVEC_BUILTIN_DSSALL
,
2494 ALTIVEC_BUILTIN_DSS
,
2495 ALTIVEC_BUILTIN_LVSL
,
2496 ALTIVEC_BUILTIN_LVSR
,
2497 ALTIVEC_BUILTIN_DSTT
,
2498 ALTIVEC_BUILTIN_DSTST
,
2499 ALTIVEC_BUILTIN_DSTSTT
,
2500 ALTIVEC_BUILTIN_DST
,
2501 ALTIVEC_BUILTIN_LVEBX
,
2502 ALTIVEC_BUILTIN_LVEHX
,
2503 ALTIVEC_BUILTIN_LVEWX
,
2504 ALTIVEC_BUILTIN_LVXL
,
2505 ALTIVEC_BUILTIN_LVX
,
2506 ALTIVEC_BUILTIN_STVX
,
2507 ALTIVEC_BUILTIN_STVEBX
,
2508 ALTIVEC_BUILTIN_STVEHX
,
2509 ALTIVEC_BUILTIN_STVEWX
,
2510 ALTIVEC_BUILTIN_STVXL
,
2511 ALTIVEC_BUILTIN_VCMPBFP_P
,
2512 ALTIVEC_BUILTIN_VCMPEQFP_P
,
2513 ALTIVEC_BUILTIN_VCMPEQUB_P
,
2514 ALTIVEC_BUILTIN_VCMPEQUH_P
,
2515 ALTIVEC_BUILTIN_VCMPEQUW_P
,
2516 ALTIVEC_BUILTIN_VCMPGEFP_P
,
2517 ALTIVEC_BUILTIN_VCMPGTFP_P
,
2518 ALTIVEC_BUILTIN_VCMPGTSB_P
,
2519 ALTIVEC_BUILTIN_VCMPGTSH_P
,
2520 ALTIVEC_BUILTIN_VCMPGTSW_P
,
2521 ALTIVEC_BUILTIN_VCMPGTUB_P
,
2522 ALTIVEC_BUILTIN_VCMPGTUH_P
,
2523 ALTIVEC_BUILTIN_VCMPGTUW_P
,
2524 ALTIVEC_BUILTIN_ABSS_V4SI
,
2525 ALTIVEC_BUILTIN_ABSS_V8HI
,
2526 ALTIVEC_BUILTIN_ABSS_V16QI
,
2527 ALTIVEC_BUILTIN_ABS_V4SI
,
2528 ALTIVEC_BUILTIN_ABS_V4SF
,
2529 ALTIVEC_BUILTIN_ABS_V8HI
,
2530 ALTIVEC_BUILTIN_ABS_V16QI
,
2531 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
2532 ALTIVEC_BUILTIN_MASK_FOR_STORE
,
2533 ALTIVEC_BUILTIN_VEC_INIT_V4SI
,
2534 ALTIVEC_BUILTIN_VEC_INIT_V8HI
,
2535 ALTIVEC_BUILTIN_VEC_INIT_V16QI
,
2536 ALTIVEC_BUILTIN_VEC_INIT_V4SF
,
2537 ALTIVEC_BUILTIN_VEC_SET_V4SI
,
2538 ALTIVEC_BUILTIN_VEC_SET_V8HI
,
2539 ALTIVEC_BUILTIN_VEC_SET_V16QI
,
2540 ALTIVEC_BUILTIN_VEC_SET_V4SF
,
2541 ALTIVEC_BUILTIN_VEC_EXT_V4SI
,
2542 ALTIVEC_BUILTIN_VEC_EXT_V8HI
,
2543 ALTIVEC_BUILTIN_VEC_EXT_V16QI
,
2544 ALTIVEC_BUILTIN_VEC_EXT_V4SF
,
2546 /* Altivec overloaded builtins. */
2547 ALTIVEC_BUILTIN_VCMPEQ_P
,
2548 ALTIVEC_BUILTIN_OVERLOADED_FIRST
= ALTIVEC_BUILTIN_VCMPEQ_P
,
2549 ALTIVEC_BUILTIN_VCMPGT_P
,
2550 ALTIVEC_BUILTIN_VCMPGE_P
,
2551 ALTIVEC_BUILTIN_VEC_ABS
,
2552 ALTIVEC_BUILTIN_VEC_ABSS
,
2553 ALTIVEC_BUILTIN_VEC_ADD
,
2554 ALTIVEC_BUILTIN_VEC_ADDC
,
2555 ALTIVEC_BUILTIN_VEC_ADDS
,
2556 ALTIVEC_BUILTIN_VEC_AND
,
2557 ALTIVEC_BUILTIN_VEC_ANDC
,
2558 ALTIVEC_BUILTIN_VEC_AVG
,
2559 ALTIVEC_BUILTIN_VEC_CEIL
,
2560 ALTIVEC_BUILTIN_VEC_CMPB
,
2561 ALTIVEC_BUILTIN_VEC_CMPEQ
,
2562 ALTIVEC_BUILTIN_VEC_CMPEQUB
,
2563 ALTIVEC_BUILTIN_VEC_CMPEQUH
,
2564 ALTIVEC_BUILTIN_VEC_CMPEQUW
,
2565 ALTIVEC_BUILTIN_VEC_CMPGE
,
2566 ALTIVEC_BUILTIN_VEC_CMPGT
,
2567 ALTIVEC_BUILTIN_VEC_CMPLE
,
2568 ALTIVEC_BUILTIN_VEC_CMPLT
,
2569 ALTIVEC_BUILTIN_VEC_CTF
,
2570 ALTIVEC_BUILTIN_VEC_CTS
,
2571 ALTIVEC_BUILTIN_VEC_CTU
,
2572 ALTIVEC_BUILTIN_VEC_DST
,
2573 ALTIVEC_BUILTIN_VEC_DSTST
,
2574 ALTIVEC_BUILTIN_VEC_DSTSTT
,
2575 ALTIVEC_BUILTIN_VEC_DSTT
,
2576 ALTIVEC_BUILTIN_VEC_EXPTE
,
2577 ALTIVEC_BUILTIN_VEC_FLOOR
,
2578 ALTIVEC_BUILTIN_VEC_LD
,
2579 ALTIVEC_BUILTIN_VEC_LDE
,
2580 ALTIVEC_BUILTIN_VEC_LDL
,
2581 ALTIVEC_BUILTIN_VEC_LOGE
,
2582 ALTIVEC_BUILTIN_VEC_LVEBX
,
2583 ALTIVEC_BUILTIN_VEC_LVEHX
,
2584 ALTIVEC_BUILTIN_VEC_LVEWX
,
2585 ALTIVEC_BUILTIN_VEC_LVSL
,
2586 ALTIVEC_BUILTIN_VEC_LVSR
,
2587 ALTIVEC_BUILTIN_VEC_MADD
,
2588 ALTIVEC_BUILTIN_VEC_MADDS
,
2589 ALTIVEC_BUILTIN_VEC_MAX
,
2590 ALTIVEC_BUILTIN_VEC_MERGEH
,
2591 ALTIVEC_BUILTIN_VEC_MERGEL
,
2592 ALTIVEC_BUILTIN_VEC_MIN
,
2593 ALTIVEC_BUILTIN_VEC_MLADD
,
2594 ALTIVEC_BUILTIN_VEC_MPERM
,
2595 ALTIVEC_BUILTIN_VEC_MRADDS
,
2596 ALTIVEC_BUILTIN_VEC_MRGHB
,
2597 ALTIVEC_BUILTIN_VEC_MRGHH
,
2598 ALTIVEC_BUILTIN_VEC_MRGHW
,
2599 ALTIVEC_BUILTIN_VEC_MRGLB
,
2600 ALTIVEC_BUILTIN_VEC_MRGLH
,
2601 ALTIVEC_BUILTIN_VEC_MRGLW
,
2602 ALTIVEC_BUILTIN_VEC_MSUM
,
2603 ALTIVEC_BUILTIN_VEC_MSUMS
,
2604 ALTIVEC_BUILTIN_VEC_MTVSCR
,
2605 ALTIVEC_BUILTIN_VEC_MULE
,
2606 ALTIVEC_BUILTIN_VEC_MULO
,
2607 ALTIVEC_BUILTIN_VEC_NMSUB
,
2608 ALTIVEC_BUILTIN_VEC_NOR
,
2609 ALTIVEC_BUILTIN_VEC_OR
,
2610 ALTIVEC_BUILTIN_VEC_PACK
,
2611 ALTIVEC_BUILTIN_VEC_PACKPX
,
2612 ALTIVEC_BUILTIN_VEC_PACKS
,
2613 ALTIVEC_BUILTIN_VEC_PACKSU
,
2614 ALTIVEC_BUILTIN_VEC_PERM
,
2615 ALTIVEC_BUILTIN_VEC_RE
,
2616 ALTIVEC_BUILTIN_VEC_RL
,
2617 ALTIVEC_BUILTIN_VEC_ROUND
,
2618 ALTIVEC_BUILTIN_VEC_RSQRTE
,
2619 ALTIVEC_BUILTIN_VEC_SEL
,
2620 ALTIVEC_BUILTIN_VEC_SL
,
2621 ALTIVEC_BUILTIN_VEC_SLD
,
2622 ALTIVEC_BUILTIN_VEC_SLL
,
2623 ALTIVEC_BUILTIN_VEC_SLO
,
2624 ALTIVEC_BUILTIN_VEC_SPLAT
,
2625 ALTIVEC_BUILTIN_VEC_SPLAT_S16
,
2626 ALTIVEC_BUILTIN_VEC_SPLAT_S32
,
2627 ALTIVEC_BUILTIN_VEC_SPLAT_S8
,
2628 ALTIVEC_BUILTIN_VEC_SPLAT_U16
,
2629 ALTIVEC_BUILTIN_VEC_SPLAT_U32
,
2630 ALTIVEC_BUILTIN_VEC_SPLAT_U8
,
2631 ALTIVEC_BUILTIN_VEC_SPLTB
,
2632 ALTIVEC_BUILTIN_VEC_SPLTH
,
2633 ALTIVEC_BUILTIN_VEC_SPLTW
,
2634 ALTIVEC_BUILTIN_VEC_SR
,
2635 ALTIVEC_BUILTIN_VEC_SRA
,
2636 ALTIVEC_BUILTIN_VEC_SRL
,
2637 ALTIVEC_BUILTIN_VEC_SRO
,
2638 ALTIVEC_BUILTIN_VEC_ST
,
2639 ALTIVEC_BUILTIN_VEC_STE
,
2640 ALTIVEC_BUILTIN_VEC_STL
,
2641 ALTIVEC_BUILTIN_VEC_STVEBX
,
2642 ALTIVEC_BUILTIN_VEC_STVEHX
,
2643 ALTIVEC_BUILTIN_VEC_STVEWX
,
2644 ALTIVEC_BUILTIN_VEC_SUB
,
2645 ALTIVEC_BUILTIN_VEC_SUBC
,
2646 ALTIVEC_BUILTIN_VEC_SUBS
,
2647 ALTIVEC_BUILTIN_VEC_SUM2S
,
2648 ALTIVEC_BUILTIN_VEC_SUM4S
,
2649 ALTIVEC_BUILTIN_VEC_SUMS
,
2650 ALTIVEC_BUILTIN_VEC_TRUNC
,
2651 ALTIVEC_BUILTIN_VEC_UNPACKH
,
2652 ALTIVEC_BUILTIN_VEC_UNPACKL
,
2653 ALTIVEC_BUILTIN_VEC_VADDFP
,
2654 ALTIVEC_BUILTIN_VEC_VADDSBS
,
2655 ALTIVEC_BUILTIN_VEC_VADDSHS
,
2656 ALTIVEC_BUILTIN_VEC_VADDSWS
,
2657 ALTIVEC_BUILTIN_VEC_VADDUBM
,
2658 ALTIVEC_BUILTIN_VEC_VADDUBS
,
2659 ALTIVEC_BUILTIN_VEC_VADDUHM
,
2660 ALTIVEC_BUILTIN_VEC_VADDUHS
,
2661 ALTIVEC_BUILTIN_VEC_VADDUWM
,
2662 ALTIVEC_BUILTIN_VEC_VADDUWS
,
2663 ALTIVEC_BUILTIN_VEC_VAVGSB
,
2664 ALTIVEC_BUILTIN_VEC_VAVGSH
,
2665 ALTIVEC_BUILTIN_VEC_VAVGSW
,
2666 ALTIVEC_BUILTIN_VEC_VAVGUB
,
2667 ALTIVEC_BUILTIN_VEC_VAVGUH
,
2668 ALTIVEC_BUILTIN_VEC_VAVGUW
,
2669 ALTIVEC_BUILTIN_VEC_VCFSX
,
2670 ALTIVEC_BUILTIN_VEC_VCFUX
,
2671 ALTIVEC_BUILTIN_VEC_VCMPEQFP
,
2672 ALTIVEC_BUILTIN_VEC_VCMPEQUB
,
2673 ALTIVEC_BUILTIN_VEC_VCMPEQUH
,
2674 ALTIVEC_BUILTIN_VEC_VCMPEQUW
,
2675 ALTIVEC_BUILTIN_VEC_VCMPGTFP
,
2676 ALTIVEC_BUILTIN_VEC_VCMPGTSB
,
2677 ALTIVEC_BUILTIN_VEC_VCMPGTSH
,
2678 ALTIVEC_BUILTIN_VEC_VCMPGTSW
,
2679 ALTIVEC_BUILTIN_VEC_VCMPGTUB
,
2680 ALTIVEC_BUILTIN_VEC_VCMPGTUH
,
2681 ALTIVEC_BUILTIN_VEC_VCMPGTUW
,
2682 ALTIVEC_BUILTIN_VEC_VMAXFP
,
2683 ALTIVEC_BUILTIN_VEC_VMAXSB
,
2684 ALTIVEC_BUILTIN_VEC_VMAXSH
,
2685 ALTIVEC_BUILTIN_VEC_VMAXSW
,
2686 ALTIVEC_BUILTIN_VEC_VMAXUB
,
2687 ALTIVEC_BUILTIN_VEC_VMAXUH
,
2688 ALTIVEC_BUILTIN_VEC_VMAXUW
,
2689 ALTIVEC_BUILTIN_VEC_VMINFP
,
2690 ALTIVEC_BUILTIN_VEC_VMINSB
,
2691 ALTIVEC_BUILTIN_VEC_VMINSH
,
2692 ALTIVEC_BUILTIN_VEC_VMINSW
,
2693 ALTIVEC_BUILTIN_VEC_VMINUB
,
2694 ALTIVEC_BUILTIN_VEC_VMINUH
,
2695 ALTIVEC_BUILTIN_VEC_VMINUW
,
2696 ALTIVEC_BUILTIN_VEC_VMRGHB
,
2697 ALTIVEC_BUILTIN_VEC_VMRGHH
,
2698 ALTIVEC_BUILTIN_VEC_VMRGHW
,
2699 ALTIVEC_BUILTIN_VEC_VMRGLB
,
2700 ALTIVEC_BUILTIN_VEC_VMRGLH
,
2701 ALTIVEC_BUILTIN_VEC_VMRGLW
,
2702 ALTIVEC_BUILTIN_VEC_VMSUMMBM
,
2703 ALTIVEC_BUILTIN_VEC_VMSUMSHM
,
2704 ALTIVEC_BUILTIN_VEC_VMSUMSHS
,
2705 ALTIVEC_BUILTIN_VEC_VMSUMUBM
,
2706 ALTIVEC_BUILTIN_VEC_VMSUMUHM
,
2707 ALTIVEC_BUILTIN_VEC_VMSUMUHS
,
2708 ALTIVEC_BUILTIN_VEC_VMULESB
,
2709 ALTIVEC_BUILTIN_VEC_VMULESH
,
2710 ALTIVEC_BUILTIN_VEC_VMULEUB
,
2711 ALTIVEC_BUILTIN_VEC_VMULEUH
,
2712 ALTIVEC_BUILTIN_VEC_VMULOSB
,
2713 ALTIVEC_BUILTIN_VEC_VMULOSH
,
2714 ALTIVEC_BUILTIN_VEC_VMULOUB
,
2715 ALTIVEC_BUILTIN_VEC_VMULOUH
,
2716 ALTIVEC_BUILTIN_VEC_VPKSHSS
,
2717 ALTIVEC_BUILTIN_VEC_VPKSHUS
,
2718 ALTIVEC_BUILTIN_VEC_VPKSWSS
,
2719 ALTIVEC_BUILTIN_VEC_VPKSWUS
,
2720 ALTIVEC_BUILTIN_VEC_VPKUHUM
,
2721 ALTIVEC_BUILTIN_VEC_VPKUHUS
,
2722 ALTIVEC_BUILTIN_VEC_VPKUWUM
,
2723 ALTIVEC_BUILTIN_VEC_VPKUWUS
,
2724 ALTIVEC_BUILTIN_VEC_VRLB
,
2725 ALTIVEC_BUILTIN_VEC_VRLH
,
2726 ALTIVEC_BUILTIN_VEC_VRLW
,
2727 ALTIVEC_BUILTIN_VEC_VSLB
,
2728 ALTIVEC_BUILTIN_VEC_VSLH
,
2729 ALTIVEC_BUILTIN_VEC_VSLW
,
2730 ALTIVEC_BUILTIN_VEC_VSPLTB
,
2731 ALTIVEC_BUILTIN_VEC_VSPLTH
,
2732 ALTIVEC_BUILTIN_VEC_VSPLTW
,
2733 ALTIVEC_BUILTIN_VEC_VSRAB
,
2734 ALTIVEC_BUILTIN_VEC_VSRAH
,
2735 ALTIVEC_BUILTIN_VEC_VSRAW
,
2736 ALTIVEC_BUILTIN_VEC_VSRB
,
2737 ALTIVEC_BUILTIN_VEC_VSRH
,
2738 ALTIVEC_BUILTIN_VEC_VSRW
,
2739 ALTIVEC_BUILTIN_VEC_VSUBFP
,
2740 ALTIVEC_BUILTIN_VEC_VSUBSBS
,
2741 ALTIVEC_BUILTIN_VEC_VSUBSHS
,
2742 ALTIVEC_BUILTIN_VEC_VSUBSWS
,
2743 ALTIVEC_BUILTIN_VEC_VSUBUBM
,
2744 ALTIVEC_BUILTIN_VEC_VSUBUBS
,
2745 ALTIVEC_BUILTIN_VEC_VSUBUHM
,
2746 ALTIVEC_BUILTIN_VEC_VSUBUHS
,
2747 ALTIVEC_BUILTIN_VEC_VSUBUWM
,
2748 ALTIVEC_BUILTIN_VEC_VSUBUWS
,
2749 ALTIVEC_BUILTIN_VEC_VSUM4SBS
,
2750 ALTIVEC_BUILTIN_VEC_VSUM4SHS
,
2751 ALTIVEC_BUILTIN_VEC_VSUM4UBS
,
2752 ALTIVEC_BUILTIN_VEC_VUPKHPX
,
2753 ALTIVEC_BUILTIN_VEC_VUPKHSB
,
2754 ALTIVEC_BUILTIN_VEC_VUPKHSH
,
2755 ALTIVEC_BUILTIN_VEC_VUPKLPX
,
2756 ALTIVEC_BUILTIN_VEC_VUPKLSB
,
2757 ALTIVEC_BUILTIN_VEC_VUPKLSH
,
2758 ALTIVEC_BUILTIN_VEC_XOR
,
2759 ALTIVEC_BUILTIN_VEC_STEP
,
2760 ALTIVEC_BUILTIN_OVERLOADED_LAST
= ALTIVEC_BUILTIN_VEC_STEP
,
2766 SPE_BUILTIN_EVDIVWS
,
2767 SPE_BUILTIN_EVDIVWU
,
2769 SPE_BUILTIN_EVFSADD
,
2770 SPE_BUILTIN_EVFSDIV
,
2771 SPE_BUILTIN_EVFSMUL
,
2772 SPE_BUILTIN_EVFSSUB
,
2776 SPE_BUILTIN_EVLHHESPLATX
,
2777 SPE_BUILTIN_EVLHHOSSPLATX
,
2778 SPE_BUILTIN_EVLHHOUSPLATX
,
2779 SPE_BUILTIN_EVLWHEX
,
2780 SPE_BUILTIN_EVLWHOSX
,
2781 SPE_BUILTIN_EVLWHOUX
,
2782 SPE_BUILTIN_EVLWHSPLATX
,
2783 SPE_BUILTIN_EVLWWSPLATX
,
2784 SPE_BUILTIN_EVMERGEHI
,
2785 SPE_BUILTIN_EVMERGEHILO
,
2786 SPE_BUILTIN_EVMERGELO
,
2787 SPE_BUILTIN_EVMERGELOHI
,
2788 SPE_BUILTIN_EVMHEGSMFAA
,
2789 SPE_BUILTIN_EVMHEGSMFAN
,
2790 SPE_BUILTIN_EVMHEGSMIAA
,
2791 SPE_BUILTIN_EVMHEGSMIAN
,
2792 SPE_BUILTIN_EVMHEGUMIAA
,
2793 SPE_BUILTIN_EVMHEGUMIAN
,
2794 SPE_BUILTIN_EVMHESMF
,
2795 SPE_BUILTIN_EVMHESMFA
,
2796 SPE_BUILTIN_EVMHESMFAAW
,
2797 SPE_BUILTIN_EVMHESMFANW
,
2798 SPE_BUILTIN_EVMHESMI
,
2799 SPE_BUILTIN_EVMHESMIA
,
2800 SPE_BUILTIN_EVMHESMIAAW
,
2801 SPE_BUILTIN_EVMHESMIANW
,
2802 SPE_BUILTIN_EVMHESSF
,
2803 SPE_BUILTIN_EVMHESSFA
,
2804 SPE_BUILTIN_EVMHESSFAAW
,
2805 SPE_BUILTIN_EVMHESSFANW
,
2806 SPE_BUILTIN_EVMHESSIAAW
,
2807 SPE_BUILTIN_EVMHESSIANW
,
2808 SPE_BUILTIN_EVMHEUMI
,
2809 SPE_BUILTIN_EVMHEUMIA
,
2810 SPE_BUILTIN_EVMHEUMIAAW
,
2811 SPE_BUILTIN_EVMHEUMIANW
,
2812 SPE_BUILTIN_EVMHEUSIAAW
,
2813 SPE_BUILTIN_EVMHEUSIANW
,
2814 SPE_BUILTIN_EVMHOGSMFAA
,
2815 SPE_BUILTIN_EVMHOGSMFAN
,
2816 SPE_BUILTIN_EVMHOGSMIAA
,
2817 SPE_BUILTIN_EVMHOGSMIAN
,
2818 SPE_BUILTIN_EVMHOGUMIAA
,
2819 SPE_BUILTIN_EVMHOGUMIAN
,
2820 SPE_BUILTIN_EVMHOSMF
,
2821 SPE_BUILTIN_EVMHOSMFA
,
2822 SPE_BUILTIN_EVMHOSMFAAW
,
2823 SPE_BUILTIN_EVMHOSMFANW
,
2824 SPE_BUILTIN_EVMHOSMI
,
2825 SPE_BUILTIN_EVMHOSMIA
,
2826 SPE_BUILTIN_EVMHOSMIAAW
,
2827 SPE_BUILTIN_EVMHOSMIANW
,
2828 SPE_BUILTIN_EVMHOSSF
,
2829 SPE_BUILTIN_EVMHOSSFA
,
2830 SPE_BUILTIN_EVMHOSSFAAW
,
2831 SPE_BUILTIN_EVMHOSSFANW
,
2832 SPE_BUILTIN_EVMHOSSIAAW
,
2833 SPE_BUILTIN_EVMHOSSIANW
,
2834 SPE_BUILTIN_EVMHOUMI
,
2835 SPE_BUILTIN_EVMHOUMIA
,
2836 SPE_BUILTIN_EVMHOUMIAAW
,
2837 SPE_BUILTIN_EVMHOUMIANW
,
2838 SPE_BUILTIN_EVMHOUSIAAW
,
2839 SPE_BUILTIN_EVMHOUSIANW
,
2840 SPE_BUILTIN_EVMWHSMF
,
2841 SPE_BUILTIN_EVMWHSMFA
,
2842 SPE_BUILTIN_EVMWHSMI
,
2843 SPE_BUILTIN_EVMWHSMIA
,
2844 SPE_BUILTIN_EVMWHSSF
,
2845 SPE_BUILTIN_EVMWHSSFA
,
2846 SPE_BUILTIN_EVMWHUMI
,
2847 SPE_BUILTIN_EVMWHUMIA
,
2848 SPE_BUILTIN_EVMWLSMIAAW
,
2849 SPE_BUILTIN_EVMWLSMIANW
,
2850 SPE_BUILTIN_EVMWLSSIAAW
,
2851 SPE_BUILTIN_EVMWLSSIANW
,
2852 SPE_BUILTIN_EVMWLUMI
,
2853 SPE_BUILTIN_EVMWLUMIA
,
2854 SPE_BUILTIN_EVMWLUMIAAW
,
2855 SPE_BUILTIN_EVMWLUMIANW
,
2856 SPE_BUILTIN_EVMWLUSIAAW
,
2857 SPE_BUILTIN_EVMWLUSIANW
,
2858 SPE_BUILTIN_EVMWSMF
,
2859 SPE_BUILTIN_EVMWSMFA
,
2860 SPE_BUILTIN_EVMWSMFAA
,
2861 SPE_BUILTIN_EVMWSMFAN
,
2862 SPE_BUILTIN_EVMWSMI
,
2863 SPE_BUILTIN_EVMWSMIA
,
2864 SPE_BUILTIN_EVMWSMIAA
,
2865 SPE_BUILTIN_EVMWSMIAN
,
2866 SPE_BUILTIN_EVMWHSSFAA
,
2867 SPE_BUILTIN_EVMWSSF
,
2868 SPE_BUILTIN_EVMWSSFA
,
2869 SPE_BUILTIN_EVMWSSFAA
,
2870 SPE_BUILTIN_EVMWSSFAN
,
2871 SPE_BUILTIN_EVMWUMI
,
2872 SPE_BUILTIN_EVMWUMIA
,
2873 SPE_BUILTIN_EVMWUMIAA
,
2874 SPE_BUILTIN_EVMWUMIAN
,
2883 SPE_BUILTIN_EVSTDDX
,
2884 SPE_BUILTIN_EVSTDHX
,
2885 SPE_BUILTIN_EVSTDWX
,
2886 SPE_BUILTIN_EVSTWHEX
,
2887 SPE_BUILTIN_EVSTWHOX
,
2888 SPE_BUILTIN_EVSTWWEX
,
2889 SPE_BUILTIN_EVSTWWOX
,
2890 SPE_BUILTIN_EVSUBFW
,
2893 SPE_BUILTIN_EVADDSMIAAW
,
2894 SPE_BUILTIN_EVADDSSIAAW
,
2895 SPE_BUILTIN_EVADDUMIAAW
,
2896 SPE_BUILTIN_EVADDUSIAAW
,
2897 SPE_BUILTIN_EVCNTLSW
,
2898 SPE_BUILTIN_EVCNTLZW
,
2899 SPE_BUILTIN_EVEXTSB
,
2900 SPE_BUILTIN_EVEXTSH
,
2901 SPE_BUILTIN_EVFSABS
,
2902 SPE_BUILTIN_EVFSCFSF
,
2903 SPE_BUILTIN_EVFSCFSI
,
2904 SPE_BUILTIN_EVFSCFUF
,
2905 SPE_BUILTIN_EVFSCFUI
,
2906 SPE_BUILTIN_EVFSCTSF
,
2907 SPE_BUILTIN_EVFSCTSI
,
2908 SPE_BUILTIN_EVFSCTSIZ
,
2909 SPE_BUILTIN_EVFSCTUF
,
2910 SPE_BUILTIN_EVFSCTUI
,
2911 SPE_BUILTIN_EVFSCTUIZ
,
2912 SPE_BUILTIN_EVFSNABS
,
2913 SPE_BUILTIN_EVFSNEG
,
2917 SPE_BUILTIN_EVSUBFSMIAAW
,
2918 SPE_BUILTIN_EVSUBFSSIAAW
,
2919 SPE_BUILTIN_EVSUBFUMIAAW
,
2920 SPE_BUILTIN_EVSUBFUSIAAW
,
2921 SPE_BUILTIN_EVADDIW
,
2925 SPE_BUILTIN_EVLHHESPLAT
,
2926 SPE_BUILTIN_EVLHHOSSPLAT
,
2927 SPE_BUILTIN_EVLHHOUSPLAT
,
2929 SPE_BUILTIN_EVLWHOS
,
2930 SPE_BUILTIN_EVLWHOU
,
2931 SPE_BUILTIN_EVLWHSPLAT
,
2932 SPE_BUILTIN_EVLWWSPLAT
,
2935 SPE_BUILTIN_EVSRWIS
,
2936 SPE_BUILTIN_EVSRWIU
,
2940 SPE_BUILTIN_EVSTWHE
,
2941 SPE_BUILTIN_EVSTWHO
,
2942 SPE_BUILTIN_EVSTWWE
,
2943 SPE_BUILTIN_EVSTWWO
,
2944 SPE_BUILTIN_EVSUBIFW
,
2947 SPE_BUILTIN_EVCMPEQ
,
2948 SPE_BUILTIN_EVCMPGTS
,
2949 SPE_BUILTIN_EVCMPGTU
,
2950 SPE_BUILTIN_EVCMPLTS
,
2951 SPE_BUILTIN_EVCMPLTU
,
2952 SPE_BUILTIN_EVFSCMPEQ
,
2953 SPE_BUILTIN_EVFSCMPGT
,
2954 SPE_BUILTIN_EVFSCMPLT
,
2955 SPE_BUILTIN_EVFSTSTEQ
,
2956 SPE_BUILTIN_EVFSTSTGT
,
2957 SPE_BUILTIN_EVFSTSTLT
,
2959 /* EVSEL compares. */
2960 SPE_BUILTIN_EVSEL_CMPEQ
,
2961 SPE_BUILTIN_EVSEL_CMPGTS
,
2962 SPE_BUILTIN_EVSEL_CMPGTU
,
2963 SPE_BUILTIN_EVSEL_CMPLTS
,
2964 SPE_BUILTIN_EVSEL_CMPLTU
,
2965 SPE_BUILTIN_EVSEL_FSCMPEQ
,
2966 SPE_BUILTIN_EVSEL_FSCMPGT
,
2967 SPE_BUILTIN_EVSEL_FSCMPLT
,
2968 SPE_BUILTIN_EVSEL_FSTSTEQ
,
2969 SPE_BUILTIN_EVSEL_FSTSTGT
,
2970 SPE_BUILTIN_EVSEL_FSTSTLT
,
2972 SPE_BUILTIN_EVSPLATFI
,
2973 SPE_BUILTIN_EVSPLATI
,
2974 SPE_BUILTIN_EVMWHSSMAA
,
2975 SPE_BUILTIN_EVMWHSMFAA
,
2976 SPE_BUILTIN_EVMWHSMIAA
,
2977 SPE_BUILTIN_EVMWHUSIAA
,
2978 SPE_BUILTIN_EVMWHUMIAA
,
2979 SPE_BUILTIN_EVMWHSSFAN
,
2980 SPE_BUILTIN_EVMWHSSIAN
,
2981 SPE_BUILTIN_EVMWHSMFAN
,
2982 SPE_BUILTIN_EVMWHSMIAN
,
2983 SPE_BUILTIN_EVMWHUSIAN
,
2984 SPE_BUILTIN_EVMWHUMIAN
,
2985 SPE_BUILTIN_EVMWHGSSFAA
,
2986 SPE_BUILTIN_EVMWHGSMFAA
,
2987 SPE_BUILTIN_EVMWHGSMIAA
,
2988 SPE_BUILTIN_EVMWHGUMIAA
,
2989 SPE_BUILTIN_EVMWHGSSFAN
,
2990 SPE_BUILTIN_EVMWHGSMFAN
,
2991 SPE_BUILTIN_EVMWHGSMIAN
,
2992 SPE_BUILTIN_EVMWHGUMIAN
,
2993 SPE_BUILTIN_MTSPEFSCR
,
2994 SPE_BUILTIN_MFSPEFSCR
,
2997 RS6000_BUILTIN_COUNT
3000 enum rs6000_builtin_type_index
3002 RS6000_BTI_NOT_OPAQUE
,
3003 RS6000_BTI_opaque_V2SI
,
3004 RS6000_BTI_opaque_V2SF
,
3005 RS6000_BTI_opaque_p_V2SI
,
3006 RS6000_BTI_opaque_V4SI
,
3014 RS6000_BTI_unsigned_V16QI
,
3015 RS6000_BTI_unsigned_V8HI
,
3016 RS6000_BTI_unsigned_V4SI
,
3017 RS6000_BTI_bool_char
, /* __bool char */
3018 RS6000_BTI_bool_short
, /* __bool short */
3019 RS6000_BTI_bool_int
, /* __bool int */
3020 RS6000_BTI_pixel
, /* __pixel */
3021 RS6000_BTI_bool_V16QI
, /* __vector __bool char */
3022 RS6000_BTI_bool_V8HI
, /* __vector __bool short */
3023 RS6000_BTI_bool_V4SI
, /* __vector __bool int */
3024 RS6000_BTI_pixel_V8HI
, /* __vector __pixel */
3025 RS6000_BTI_long
, /* long_integer_type_node */
3026 RS6000_BTI_unsigned_long
, /* long_unsigned_type_node */
3027 RS6000_BTI_INTQI
, /* intQI_type_node */
3028 RS6000_BTI_UINTQI
, /* unsigned_intQI_type_node */
3029 RS6000_BTI_INTHI
, /* intHI_type_node */
3030 RS6000_BTI_UINTHI
, /* unsigned_intHI_type_node */
3031 RS6000_BTI_INTSI
, /* intSI_type_node */
3032 RS6000_BTI_UINTSI
, /* unsigned_intSI_type_node */
3033 RS6000_BTI_float
, /* float_type_node */
3034 RS6000_BTI_void
, /* void_type_node */
3039 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
3040 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
3041 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
3042 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
3043 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
3044 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
3045 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
3046 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
3047 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
3048 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
3049 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
3050 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
3051 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
3052 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
3053 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
3054 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
3055 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
3056 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
3057 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
3058 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
3059 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
3060 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
3062 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
3063 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
3064 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
3065 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
3066 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
3067 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
3068 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
3069 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
3070 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
3071 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
3073 extern GTY(()) tree rs6000_builtin_types
[RS6000_BTI_MAX
];
3074 extern GTY(()) tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];