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tm.texi (LEGITIMIZE_ADDRESS): Revise documentation.
[official-gcc.git] / gcc / config / mips / mips.h
blob5c68688cccee6df104fa4fc221235ffee25e1376
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
52 PROCESSOR_M4K,
53 PROCESSOR_OCTEON,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4130,
61 PROCESSOR_R4300,
62 PROCESSOR_R4600,
63 PROCESSOR_R4650,
64 PROCESSOR_R5000,
65 PROCESSOR_R5400,
66 PROCESSOR_R5500,
67 PROCESSOR_R7000,
68 PROCESSOR_R8000,
69 PROCESSOR_R9000,
70 PROCESSOR_R10000,
71 PROCESSOR_SB1,
72 PROCESSOR_SB1A,
73 PROCESSOR_SR71000,
74 PROCESSOR_XLR,
75 PROCESSOR_MAX
76 };
77
78 /* Costs of various operations on the different architectures. */
79
80 struct mips_rtx_cost_data
81 {
82 unsigned short fp_add;
83 unsigned short fp_mult_sf;
84 unsigned short fp_mult_df;
85 unsigned short fp_div_sf;
86 unsigned short fp_div_df;
87 unsigned short int_mult_si;
88 unsigned short int_mult_di;
89 unsigned short int_div_si;
90 unsigned short int_div_di;
91 unsigned short branch_cost;
92 unsigned short memory_latency;
93 };
94
95 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
96 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
97 to work on a 64-bit machine. */
98
99 #define ABI_32 0
100 #define ABI_N32 1
101 #define ABI_64 2
102 #define ABI_EABI 3
103 #define ABI_O64 4
104
105 /* Masks that affect tuning.
106
107 PTF_AVOID_BRANCHLIKELY
108 Set if it is usually not profitable to use branch-likely instructions
109 for this target, typically because the branches are always predicted
110 taken and so incur a large overhead when not taken. */
111 #define PTF_AVOID_BRANCHLIKELY 0x1
112
113 /* Information about one recognized processor. Defined here for the
114 benefit of TARGET_CPU_CPP_BUILTINS. */
115 struct mips_cpu_info {
116 /* The 'canonical' name of the processor as far as GCC is concerned.
117 It's typically a manufacturer's prefix followed by a numerical
118 designation. It should be lowercase. */
119 const char *name;
120
121 /* The internal processor number that most closely matches this
122 entry. Several processors can have the same value, if there's no
123 difference between them from GCC's point of view. */
124 enum processor_type cpu;
125
126 /* The ISA level that the processor implements. */
127 int isa;
128
129 /* A mask of PTF_* values. */
130 unsigned int tune_flags;
131 };
132
133 /* Enumerates the setting of the -mcode-readable option. */
134 enum mips_code_readable_setting {
135 CODE_READABLE_NO,
136 CODE_READABLE_PCREL,
137 CODE_READABLE_YES
138 };
139
140 /* Macros to silence warnings about numbers being signed in traditional
141 C and unsigned in ISO C when compiled on 32-bit hosts. */
142
143 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
144 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
145 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
146
147 \f
148 /* Run-time compilation parameters selecting different hardware subsets. */
149
150 /* True if we are generating position-independent VxWorks RTP code. */
151 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
152
153 /* True if the output file is marked as ".abicalls; .option pic0"
154 (-call_nonpic). */
155 #define TARGET_ABICALLS_PIC0 \
156 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
157
158 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
159 #define TARGET_ABICALLS_PIC2 \
160 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
161
162 /* True if the call patterns should be split into a jalr followed by
163 an instruction to restore $gp. It is only safe to split the load
164 from the call when every use of $gp is explicit. */
165
166 #define TARGET_SPLIT_CALLS \
167 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
168
169 /* True if we're generating a form of -mabicalls in which we can use
170 operators like %hi and %lo to refer to locally-binding symbols.
171 We can only do this for -mno-shared, and only then if we can use
172 relocation operations instead of assembly macros. It isn't really
173 worth using absolute sequences for 64-bit symbols because GOT
174 accesses are so much shorter. */
175
176 #define TARGET_ABSOLUTE_ABICALLS \
177 (TARGET_ABICALLS \
178 && !TARGET_SHARED \
179 && TARGET_EXPLICIT_RELOCS \
180 && !ABI_HAS_64BIT_SYMBOLS)
181
182 /* True if we can optimize sibling calls. For simplicity, we only
183 handle cases in which call_insn_operand will reject invalid
184 sibcall addresses. There are two cases in which this isn't true:
185
186 - TARGET_MIPS16. call_insn_operand accepts constant addresses
187 but there is no direct jump instruction. It isn't worth
188 using sibling calls in this case anyway; they would usually
189 be longer than normal calls.
190
191 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
192 accepts global constants, but all sibcalls must be indirect. */
193 #define TARGET_SIBCALLS \
194 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
195
196 /* True if we need to use a global offset table to access some symbols. */
197 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
198
199 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
200 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
201
202 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
203 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
204
205 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
206 This is true for both the PIC and non-PIC VxWorks RTP modes. */
207 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
208
209 /* True if .gpword or .gpdword should be used for switch tables.
210
211 Although GAS does understand .gpdword, the SGI linker mishandles
212 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
213 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
214 #define TARGET_GPWORD \
215 (TARGET_ABICALLS \
216 && !TARGET_ABSOLUTE_ABICALLS \
217 && !(mips_abi == ABI_64 && TARGET_IRIX))
218
219 /* Generate mips16 code */
220 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
221 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
222 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
223 /* Generate mips16e register save/restore sequences. */
224 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
225
226 /* True if we're generating a form of MIPS16 code in which general
227 text loads are allowed. */
228 #define TARGET_MIPS16_TEXT_LOADS \
229 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
230
231 /* True if we're generating a form of MIPS16 code in which PC-relative
232 loads are allowed. */
233 #define TARGET_MIPS16_PCREL_LOADS \
234 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
235
236 /* Generic ISA defines. */
237 #define ISA_MIPS1 (mips_isa == 1)
238 #define ISA_MIPS2 (mips_isa == 2)
239 #define ISA_MIPS3 (mips_isa == 3)
240 #define ISA_MIPS4 (mips_isa == 4)
241 #define ISA_MIPS32 (mips_isa == 32)
242 #define ISA_MIPS32R2 (mips_isa == 33)
243 #define ISA_MIPS64 (mips_isa == 64)
244 #define ISA_MIPS64R2 (mips_isa == 65)
245
246 /* Architecture target defines. */
247 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
248 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
249 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
250 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
251 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
252 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
253 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
254 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
255 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
256 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
257 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
258 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
259 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
260 || mips_arch == PROCESSOR_SB1A)
261 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
262
263 /* Scheduling target defines. */
264 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
265 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
266 || mips_tune == PROCESSOR_24KF2_1 \
267 || mips_tune == PROCESSOR_24KF1_1)
268 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
269 || mips_tune == PROCESSOR_74KF2_1 \
270 || mips_tune == PROCESSOR_74KF1_1 \
271 || mips_tune == PROCESSOR_74KF3_2)
272 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
273 || mips_tune == PROCESSOR_LOONGSON_2F)
274 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
275 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
276 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
277 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
278 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
279 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
280 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
281 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
282 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
283 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
284 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
285 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON)
286 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
287 || mips_tune == PROCESSOR_SB1A)
288
289 /* Whether vector modes and intrinsics for ST Microelectronics
290 Loongson-2E/2F processors should be enabled. In o32 pairs of
291 floating-point registers provide 64-bit values. */
292 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
293 && TARGET_LOONGSON_2EF)
294
295 /* True if the pre-reload scheduler should try to create chains of
296 multiply-add or multiply-subtract instructions. For example,
297 suppose we have:
298
299 t1 = a * b
300 t2 = t1 + c * d
301 t3 = e * f
302 t4 = t3 - g * h
303
304 t1 will have a higher priority than t2 and t3 will have a higher
305 priority than t4. However, before reload, there is no dependence
306 between t1 and t3, and they can often have similar priorities.
307 The scheduler will then tend to prefer:
308
309 t1 = a * b
310 t3 = e * f
311 t2 = t1 + c * d
312 t4 = t3 - g * h
313
314 which stops us from making full use of macc/madd-style instructions.
315 This sort of situation occurs frequently in Fourier transforms and
316 in unrolled loops.
317
318 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
319 queue so that chained multiply-add and multiply-subtract instructions
320 appear ahead of any other instruction that is likely to clobber lo.
321 In the example above, if t2 and t3 become ready at the same time,
322 the code ensures that t2 is scheduled first.
323
324 Multiply-accumulate instructions are a bigger win for some targets
325 than others, so this macro is defined on an opt-in basis. */
326 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
327 || TUNE_MIPS4120 \
328 || TUNE_MIPS4130 \
329 || TUNE_24K)
330
331 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
332 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
333
334 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
335 directly accessible, while the command-line options select
336 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
337 in use. */
338 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
339 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
340
341 /* IRIX specific stuff. */
342 #define TARGET_IRIX 0
343 #define TARGET_IRIX6 0
344
345 /* Define preprocessor macros for the -march and -mtune options.
346 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
347 processor. If INFO's canonical name is "foo", define PREFIX to
348 be "foo", and define an additional macro PREFIX_FOO. */
349 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
350 do \
351 { \
352 char *macro, *p; \
353 \
354 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
355 for (p = macro; *p != 0; p++) \
356 *p = TOUPPER (*p); \
357 \
358 builtin_define (macro); \
359 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
360 free (macro); \
361 } \
362 while (0)
363
364 /* Target CPU builtins. */
365 #define TARGET_CPU_CPP_BUILTINS() \
366 do \
367 { \
368 /* Everyone but IRIX defines this to mips. */ \
369 if (!TARGET_IRIX) \
370 builtin_assert ("machine=mips"); \
371 \
372 builtin_assert ("cpu=mips"); \
373 builtin_define ("__mips__"); \
374 builtin_define ("_mips"); \
375 \
376 /* We do this here because __mips is defined below and so we \
377 can't use builtin_define_std. We don't ever want to define \
378 "mips" for VxWorks because some of the VxWorks headers \
379 construct include filenames from a root directory macro, \
380 an architecture macro and a filename, where the architecture \
381 macro expands to 'mips'. If we define 'mips' to 1, the \
382 architecture macro expands to 1 as well. */ \
383 if (!flag_iso && !TARGET_VXWORKS) \
384 builtin_define ("mips"); \
385 \
386 if (TARGET_64BIT) \
387 builtin_define ("__mips64"); \
388 \
389 if (!TARGET_IRIX) \
390 { \
391 /* Treat _R3000 and _R4000 like register-size \
392 defines, which is how they've historically \
393 been used. */ \
394 if (TARGET_64BIT) \
395 { \
396 builtin_define_std ("R4000"); \
397 builtin_define ("_R4000"); \
398 } \
399 else \
400 { \
401 builtin_define_std ("R3000"); \
402 builtin_define ("_R3000"); \
403 } \
404 } \
405 if (TARGET_FLOAT64) \
406 builtin_define ("__mips_fpr=64"); \
407 else \
408 builtin_define ("__mips_fpr=32"); \
409 \
410 if (mips_base_mips16) \
411 builtin_define ("__mips16"); \
412 \
413 if (TARGET_MIPS3D) \
414 builtin_define ("__mips3d"); \
415 \
416 if (TARGET_SMARTMIPS) \
417 builtin_define ("__mips_smartmips"); \
418 \
419 if (TARGET_DSP) \
420 { \
421 builtin_define ("__mips_dsp"); \
422 if (TARGET_DSPR2) \
423 { \
424 builtin_define ("__mips_dspr2"); \
425 builtin_define ("__mips_dsp_rev=2"); \
426 } \
427 else \
428 builtin_define ("__mips_dsp_rev=1"); \
429 } \
430 \
431 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
432 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
433 \
434 if (ISA_MIPS1) \
435 { \
436 builtin_define ("__mips=1"); \
437 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
438 } \
439 else if (ISA_MIPS2) \
440 { \
441 builtin_define ("__mips=2"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
443 } \
444 else if (ISA_MIPS3) \
445 { \
446 builtin_define ("__mips=3"); \
447 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
448 } \
449 else if (ISA_MIPS4) \
450 { \
451 builtin_define ("__mips=4"); \
452 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
453 } \
454 else if (ISA_MIPS32) \
455 { \
456 builtin_define ("__mips=32"); \
457 builtin_define ("__mips_isa_rev=1"); \
458 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
459 } \
460 else if (ISA_MIPS32R2) \
461 { \
462 builtin_define ("__mips=32"); \
463 builtin_define ("__mips_isa_rev=2"); \
464 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
465 } \
466 else if (ISA_MIPS64) \
467 { \
468 builtin_define ("__mips=64"); \
469 builtin_define ("__mips_isa_rev=1"); \
470 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
471 } \
472 else if (ISA_MIPS64R2) \
473 { \
474 builtin_define ("__mips=64"); \
475 builtin_define ("__mips_isa_rev=2"); \
476 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
477 } \
478 \
479 switch (mips_abi) \
480 { \
481 case ABI_32: \
482 builtin_define ("_ABIO32=1"); \
483 builtin_define ("_MIPS_SIM=_ABIO32"); \
484 break; \
485 \
486 case ABI_N32: \
487 builtin_define ("_ABIN32=2"); \
488 builtin_define ("_MIPS_SIM=_ABIN32"); \
489 break; \
490 \
491 case ABI_64: \
492 builtin_define ("_ABI64=3"); \
493 builtin_define ("_MIPS_SIM=_ABI64"); \
494 break; \
495 \
496 case ABI_O64: \
497 builtin_define ("_ABIO64=4"); \
498 builtin_define ("_MIPS_SIM=_ABIO64"); \
499 break; \
500 } \
501 \
502 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
503 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
504 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
505 builtin_define_with_int_value ("_MIPS_FPSET", \
506 32 / MAX_FPRS_PER_FMT); \
507 \
508 /* These defines reflect the ABI in use, not whether the \
509 FPU is directly accessible. */ \
510 if (TARGET_HARD_FLOAT_ABI) \
511 builtin_define ("__mips_hard_float"); \
512 else \
513 builtin_define ("__mips_soft_float"); \
514 \
515 if (TARGET_SINGLE_FLOAT) \
516 builtin_define ("__mips_single_float"); \
517 \
518 if (TARGET_PAIRED_SINGLE_FLOAT) \
519 builtin_define ("__mips_paired_single_float"); \
520 \
521 if (TARGET_BIG_ENDIAN) \
522 { \
523 builtin_define_std ("MIPSEB"); \
524 builtin_define ("_MIPSEB"); \
525 } \
526 else \
527 { \
528 builtin_define_std ("MIPSEL"); \
529 builtin_define ("_MIPSEL"); \
530 } \
531 \
532 /* Whether calls should go through $25. The separate __PIC__ \
533 macro indicates whether abicalls code might use a GOT. */ \
534 if (TARGET_ABICALLS) \
535 builtin_define ("__mips_abicalls"); \
536 \
537 /* Whether Loongson vector modes are enabled. */ \
538 if (TARGET_LOONGSON_VECTORS) \
539 builtin_define ("__mips_loongson_vector_rev"); \
540 \
541 /* Historical Octeon macro. */ \
542 if (TARGET_OCTEON) \
543 builtin_define ("__OCTEON__"); \
544 \
545 /* Macros dependent on the C dialect. */ \
546 if (preprocessing_asm_p ()) \
547 { \
548 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
549 builtin_define ("_LANGUAGE_ASSEMBLY"); \
550 } \
551 else if (c_dialect_cxx ()) \
552 { \
553 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
554 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
555 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
556 } \
557 else \
558 { \
559 builtin_define_std ("LANGUAGE_C"); \
560 builtin_define ("_LANGUAGE_C"); \
561 } \
562 if (c_dialect_objc ()) \
563 { \
564 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
565 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
566 /* Bizarre, but needed at least for Irix. */ \
567 builtin_define_std ("LANGUAGE_C"); \
568 builtin_define ("_LANGUAGE_C"); \
569 } \
570 \
571 if (mips_abi == ABI_EABI) \
572 builtin_define ("__mips_eabi"); \
573 \
574 if (TARGET_CACHE_BUILTIN) \
575 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
576 } \
577 while (0)
578
579 /* Default target_flags if no switches are specified */
580
581 #ifndef TARGET_DEFAULT
582 #define TARGET_DEFAULT 0
583 #endif
584
585 #ifndef TARGET_CPU_DEFAULT
586 #define TARGET_CPU_DEFAULT 0
587 #endif
588
589 #ifndef TARGET_ENDIAN_DEFAULT
590 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
591 #endif
592
593 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
594 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
595 #endif
596
597 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
598 #ifndef MIPS_ISA_DEFAULT
599 #ifndef MIPS_CPU_STRING_DEFAULT
600 #define MIPS_CPU_STRING_DEFAULT "from-abi"
601 #endif
602 #endif
603
604 #ifdef IN_LIBGCC2
605 #undef TARGET_64BIT
606 /* Make this compile time constant for libgcc2 */
607 #ifdef __mips64
608 #define TARGET_64BIT 1
609 #else
610 #define TARGET_64BIT 0
611 #endif
612 #endif /* IN_LIBGCC2 */
613
614 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
615 when compiled with hardware floating point. This is because MIPS16
616 code cannot save and restore the floating-point registers, which is
617 important if in a mixed MIPS16/non-MIPS16 environment. */
618
619 #ifdef IN_LIBGCC2
620 #if __mips_hard_float
621 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
622 #endif
623 #endif /* IN_LIBGCC2 */
624
625 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
626
627 #ifndef MULTILIB_ENDIAN_DEFAULT
628 #if TARGET_ENDIAN_DEFAULT == 0
629 #define MULTILIB_ENDIAN_DEFAULT "EL"
630 #else
631 #define MULTILIB_ENDIAN_DEFAULT "EB"
632 #endif
633 #endif
634
635 #ifndef MULTILIB_ISA_DEFAULT
636 # if MIPS_ISA_DEFAULT == 1
637 # define MULTILIB_ISA_DEFAULT "mips1"
638 # else
639 # if MIPS_ISA_DEFAULT == 2
640 # define MULTILIB_ISA_DEFAULT "mips2"
641 # else
642 # if MIPS_ISA_DEFAULT == 3
643 # define MULTILIB_ISA_DEFAULT "mips3"
644 # else
645 # if MIPS_ISA_DEFAULT == 4
646 # define MULTILIB_ISA_DEFAULT "mips4"
647 # else
648 # if MIPS_ISA_DEFAULT == 32
649 # define MULTILIB_ISA_DEFAULT "mips32"
650 # else
651 # if MIPS_ISA_DEFAULT == 33
652 # define MULTILIB_ISA_DEFAULT "mips32r2"
653 # else
654 # if MIPS_ISA_DEFAULT == 64
655 # define MULTILIB_ISA_DEFAULT "mips64"
656 # else
657 # if MIPS_ISA_DEFAULT == 65
658 # define MULTILIB_ISA_DEFAULT "mips64r2"
659 # else
660 # define MULTILIB_ISA_DEFAULT "mips1"
661 # endif
662 # endif
663 # endif
664 # endif
665 # endif
666 # endif
667 # endif
668 # endif
669 #endif
670
671 #ifndef MULTILIB_DEFAULTS
672 #define MULTILIB_DEFAULTS \
673 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
674 #endif
675
676 /* We must pass -EL to the linker by default for little endian embedded
677 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
678 linker will default to using big-endian output files. The OUTPUT_FORMAT
679 line must be in the linker script, otherwise -EB/-EL will not work. */
680
681 #ifndef ENDIAN_SPEC
682 #if TARGET_ENDIAN_DEFAULT == 0
683 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
684 #else
685 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
686 #endif
687 #endif
688
689 /* A spec condition that matches all non-mips16 -mips arguments. */
690
691 #define MIPS_ISA_LEVEL_OPTION_SPEC \
692 "mips1|mips2|mips3|mips4|mips32*|mips64*"
693
694 /* A spec condition that matches all non-mips16 architecture arguments. */
695
696 #define MIPS_ARCH_OPTION_SPEC \
697 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
698
699 /* A spec that infers a -mips argument from an -march argument,
700 or injects the default if no architecture is specified. */
701
702 #define MIPS_ISA_LEVEL_SPEC \
703 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
704 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
705 %{march=mips2|march=r6000:-mips2} \
706 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
707 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
708 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
709 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
710 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
711 |march=34k*|march=74k*: -mips32r2} \
712 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
713 |march=xlr: -mips64} \
714 %{march=mips64r2|march=octeon: -mips64r2} \
715 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
716
717 /* A spec that infers a -mhard-float or -msoft-float setting from an
718 -march argument. Note that soft-float and hard-float code are not
719 link-compatible. */
720
721 #define MIPS_ARCH_FLOAT_SPEC \
722 "%{mhard-float|msoft-float|march=mips*:; \
723 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
724 |march=34kc|march=74kc|march=5kc|march=octeon|march=xlr: -msoft-float; \
725 march=*: -mhard-float}"
726
727 /* A spec condition that matches 32-bit options. It only works if
728 MIPS_ISA_LEVEL_SPEC has been applied. */
729
730 #define MIPS_32BIT_OPTION_SPEC \
731 "mips1|mips2|mips32*|mgp32"
732
733 /* Support for a compile-time default CPU, et cetera. The rules are:
734 --with-arch is ignored if -march is specified or a -mips is specified
735 (other than -mips16).
736 --with-tune is ignored if -mtune is specified.
737 --with-abi is ignored if -mabi is specified.
738 --with-float is ignored if -mhard-float or -msoft-float are
739 specified.
740 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
741 specified. */
742 #define OPTION_DEFAULT_SPECS \
743 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
744 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
745 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
746 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
747 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
748 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
749 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }
750
751
752 /* A spec that infers the -mdsp setting from an -march argument. */
753 #define BASE_DRIVER_SELF_SPECS \
754 "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*: -mdsp}}"
755
756 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
757
758 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
759 && ISA_HAS_COND_TRAP)
760
761 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
762
763 /* True if the ABI can only work with 64-bit integer registers. We
764 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
765 otherwise floating-point registers must also be 64-bit. */
766 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
767
768 /* Likewise for 32-bit regs. */
769 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
770
771 /* True if the file format uses 64-bit symbols. At present, this is
772 only true for n64, which uses 64-bit ELF. */
773 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
774
775 /* True if symbols are 64 bits wide. This is usually determined by
776 the ABI's file format, but it can be overridden by -msym32. Note that
777 overriding the size with -msym32 changes the ABI of relocatable objects,
778 although it doesn't change the ABI of a fully-linked object. */
779 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS && !TARGET_SYM32)
780
781 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
782 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
783 || ISA_MIPS4 \
784 || ISA_MIPS64 \
785 || ISA_MIPS64R2)
786
787 /* ISA has branch likely instructions (e.g. mips2). */
788 /* Disable branchlikely for tx39 until compare rewrite. They haven't
789 been generated up to this point. */
790 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
791
792 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
793 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
794 || TARGET_MIPS5400 \
795 || TARGET_MIPS5500 \
796 || TARGET_MIPS7000 \
797 || TARGET_MIPS9000 \
798 || TARGET_MAD \
799 || ISA_MIPS32 \
800 || ISA_MIPS32R2 \
801 || ISA_MIPS64 \
802 || ISA_MIPS64R2) \
803 && !TARGET_MIPS16)
804
805 /* ISA has a three-operand multiplication instruction. */
806 #define ISA_HAS_DMUL3 (TARGET_64BIT \
807 && TARGET_OCTEON \
808 && !TARGET_MIPS16)
809
810 /* ISA has the floating-point conditional move instructions introduced
811 in mips4. */
812 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
813 || ISA_MIPS32 \
814 || ISA_MIPS32R2 \
815 || ISA_MIPS64 \
816 || ISA_MIPS64R2) \
817 && !TARGET_MIPS5500 \
818 && !TARGET_MIPS16)
819
820 /* ISA has the integer conditional move instructions introduced in mips4 and
821 ST Loongson 2E/2F. */
822 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
823
824 /* ISA has LDC1 and SDC1. */
825 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
826
827 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
828 branch on CC, and move (both FP and non-FP) on CC. */
829 #define ISA_HAS_8CC (ISA_MIPS4 \
830 || ISA_MIPS32 \
831 || ISA_MIPS32R2 \
832 || ISA_MIPS64 \
833 || ISA_MIPS64R2)
834
835 /* This is a catch all for other mips4 instructions: indexed load, the
836 FP madd and msub instructions, and the FP recip and recip sqrt
837 instructions. */
838 #define ISA_HAS_FP4 ((ISA_MIPS4 \
839 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
840 || ISA_MIPS64 \
841 || ISA_MIPS64R2) \
842 && !TARGET_MIPS16)
843
844 /* ISA has paired-single instructions. */
845 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
846
847 /* ISA has conditional trap instructions. */
848 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
849 && !TARGET_MIPS16)
850
851 /* ISA has integer multiply-accumulate instructions, madd and msub. */
852 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
853 || ISA_MIPS32R2 \
854 || ISA_MIPS64 \
855 || ISA_MIPS64R2) \
856 && !TARGET_MIPS16)
857
858 /* Integer multiply-accumulate instructions should be generated. */
859 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
860
861 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
862 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
863
864 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
865 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
866
867 /* ISA has floating-point nmadd and nmsub instructions
868 'd = -((a * b) [+-] c)'. */
869 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
870 ((ISA_MIPS4 \
871 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
872 || ISA_MIPS64 \
873 || ISA_MIPS64R2) \
874 && (!TARGET_MIPS5400 || TARGET_MAD) \
875 && !TARGET_MIPS16)
876
877 /* ISA has floating-point nmadd and nmsub instructions
878 'c = -((a * b) [+-] c)'. */
879 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
880 TARGET_LOONGSON_2EF
881
882 /* ISA has count leading zeroes/ones instruction (not implemented). */
883 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
884 || ISA_MIPS32R2 \
885 || ISA_MIPS64 \
886 || ISA_MIPS64R2) \
887 && !TARGET_MIPS16)
888
889 /* ISA has three operand multiply instructions that put
890 the high part in an accumulator: mulhi or mulhiu. */
891 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
892 || TARGET_MIPS5500 \
893 || TARGET_SR71K) \
894 && !TARGET_MIPS16)
895
896 /* ISA has three operand multiply instructions that
897 negates the result and puts the result in an accumulator. */
898 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
899 || TARGET_MIPS5500 \
900 || TARGET_SR71K) \
901 && !TARGET_MIPS16)
902
903 /* ISA has three operand multiply instructions that subtracts the
904 result from a 4th operand and puts the result in an accumulator. */
905 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
906 || TARGET_MIPS5500 \
907 || TARGET_SR71K) \
908 && !TARGET_MIPS16)
909
910 /* ISA has three operand multiply instructions that the result
911 from a 4th operand and puts the result in an accumulator. */
912 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
913 || TARGET_MIPS4130 \
914 || TARGET_MIPS5400 \
915 || TARGET_MIPS5500 \
916 || TARGET_SR71K) \
917 && !TARGET_MIPS16)
918
919 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
920 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
921 || TARGET_MIPS4130) \
922 && !TARGET_MIPS16)
923
924 /* ISA has the "ror" (rotate right) instructions. */
925 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
926 || ISA_MIPS64R2 \
927 || TARGET_MIPS5400 \
928 || TARGET_MIPS5500 \
929 || TARGET_SR71K \
930 || TARGET_SMARTMIPS) \
931 && !TARGET_MIPS16)
932
933 /* ISA has data prefetch instructions. This controls use of 'pref'. */
934 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
935 || TARGET_LOONGSON_2EF \
936 || ISA_MIPS32 \
937 || ISA_MIPS32R2 \
938 || ISA_MIPS64 \
939 || ISA_MIPS64R2) \
940 && !TARGET_MIPS16)
941
942 /* ISA has data indexed prefetch instructions. This controls use of
943 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
944 (prefx is a cop1x instruction, so can only be used if FP is
945 enabled.) */
946 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
947 || ISA_MIPS32R2 \
948 || ISA_MIPS64 \
949 || ISA_MIPS64R2) \
950 && !TARGET_MIPS16)
951
952 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
953 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
954 also requires TARGET_DOUBLE_FLOAT. */
955 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
956
957 /* ISA includes the MIPS32r2 seb and seh instructions. */
958 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
959 || ISA_MIPS64R2) \
960 && !TARGET_MIPS16)
961
962 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
963 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
964 || ISA_MIPS64R2) \
965 && !TARGET_MIPS16)
966
967 /* ISA has instructions for accessing top part of 64-bit fp regs. */
968 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
969 && (ISA_MIPS32R2 \
970 || ISA_MIPS64R2))
971
972 /* ISA has lwxs instruction (load w/scaled index address. */
973 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
974
975 /* The DSP ASE is available. */
976 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
977
978 /* Revision 2 of the DSP ASE is available. */
979 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
980
981 /* True if the result of a load is not available to the next instruction.
982 A nop will then be needed between instructions like "lw $4,..."
983 and "addiu $4,$4,1". */
984 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
985 && !TARGET_MIPS3900 \
986 && !TARGET_MIPS16)
987
988 /* Likewise mtc1 and mfc1. */
989 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
990 && !TARGET_LOONGSON_2EF)
991
992 /* Likewise floating-point comparisons. */
993 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
994 && !TARGET_LOONGSON_2EF)
995
996 /* True if mflo and mfhi can be immediately followed by instructions
997 which write to the HI and LO registers.
998
999 According to MIPS specifications, MIPS ISAs I, II, and III need
1000 (at least) two instructions between the reads of HI/LO and
1001 instructions which write them, and later ISAs do not. Contradicting
1002 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1003 the UM for the NEC Vr5000) document needing the instructions between
1004 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1005 MIPS64 and later ISAs to have the interlocks, plus any specific
1006 earlier-ISA CPUs for which CPU documentation declares that the
1007 instructions are really interlocked. */
1008 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1009 || ISA_MIPS32R2 \
1010 || ISA_MIPS64 \
1011 || ISA_MIPS64R2 \
1012 || TARGET_MIPS5500 \
1013 || TARGET_LOONGSON_2EF)
1014
1015 /* ISA includes synci, jr.hb and jalr.hb. */
1016 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
1017 || ISA_MIPS64R2) \
1018 && !TARGET_MIPS16)
1019
1020 /* ISA includes sync. */
1021 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1022 #define GENERATE_SYNC \
1023 (target_flags_explicit & MASK_LLSC \
1024 ? TARGET_LLSC && !TARGET_MIPS16 \
1025 : ISA_HAS_SYNC)
1026
1027 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1028 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1029 instructions. */
1030 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1031 #define GENERATE_LL_SC \
1032 (target_flags_explicit & MASK_LLSC \
1033 ? TARGET_LLSC && !TARGET_MIPS16 \
1034 : ISA_HAS_LL_SC)
1035
1036 /* ISA includes the baddu instruction. */
1037 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1038
1039 /* ISA includes the bbit* instructions. */
1040 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1041
1042 /* ISA includes the cins instruction. */
1043 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1044
1045 /* ISA includes the exts instruction. */
1046 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1047
1048 /* ISA includes the seq and sne instructions. */
1049 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1050
1051 /* ISA includes the pop instruction. */
1052 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1053
1054 /* The CACHE instruction is available in non-MIPS16 code. */
1055 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1056
1057 /* The CACHE instruction is available. */
1058 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1059 \f
1060 /* Add -G xx support. */
1061
1062 #undef SWITCH_TAKES_ARG
1063 #define SWITCH_TAKES_ARG(CHAR) \
1064 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1065
1066 #define OVERRIDE_OPTIONS mips_override_options ()
1067
1068 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1069
1070 /* Show we can debug even without a frame pointer. */
1071 #define CAN_DEBUG_WITHOUT_FP
1072 \f
1073 /* Tell collect what flags to pass to nm. */
1074 #ifndef NM_FLAGS
1075 #define NM_FLAGS "-Bn"
1076 #endif
1077
1078 \f
1079 #ifndef MIPS_ABI_DEFAULT
1080 #define MIPS_ABI_DEFAULT ABI_32
1081 #endif
1082
1083 /* Use the most portable ABI flag for the ASM specs. */
1084
1085 #if MIPS_ABI_DEFAULT == ABI_32
1086 #define MULTILIB_ABI_DEFAULT "mabi=32"
1087 #endif
1088
1089 #if MIPS_ABI_DEFAULT == ABI_O64
1090 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1091 #endif
1092
1093 #if MIPS_ABI_DEFAULT == ABI_N32
1094 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1095 #endif
1096
1097 #if MIPS_ABI_DEFAULT == ABI_64
1098 #define MULTILIB_ABI_DEFAULT "mabi=64"
1099 #endif
1100
1101 #if MIPS_ABI_DEFAULT == ABI_EABI
1102 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1103 #endif
1104
1105 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1106 to the assembler. It may be overridden by subtargets. */
1107 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1108 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1109 %{noasmopt:-O0} \
1110 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1111 #endif
1112
1113 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1114 the assembler. It may be overridden by subtargets.
1115
1116 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1117 COFF debugging info. */
1118
1119 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1120 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1121 %{g} %{g0} %{g1} %{g2} %{g3} \
1122 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1123 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1124 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1125 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1126 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1127 #endif
1128
1129 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1130 overridden by subtargets. */
1131
1132 #ifndef SUBTARGET_ASM_SPEC
1133 #define SUBTARGET_ASM_SPEC ""
1134 #endif
1135
1136 #undef ASM_SPEC
1137 #define ASM_SPEC "\
1138 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1139 %{mips32*} %{mips64*} \
1140 %{mips16} %{mno-mips16:-no-mips16} \
1141 %{mips3d} %{mno-mips3d:-no-mips3d} \
1142 %{mdmx} %{mno-mdmx:-no-mdmx} \
1143 %{mdsp} %{mno-dsp} \
1144 %{mdspr2} %{mno-dspr2} \
1145 %{msmartmips} %{mno-smartmips} \
1146 %{mmt} %{mno-mt} \
1147 %{mfix-vr4120} %{mfix-vr4130} \
1148 %(subtarget_asm_optimizing_spec) \
1149 %(subtarget_asm_debugging_spec) \
1150 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1151 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1152 %{mfp32} %{mfp64} \
1153 %{mshared} %{mno-shared} \
1154 %{msym32} %{mno-sym32} \
1155 %{mtune=*} %{v} \
1156 %(subtarget_asm_spec)"
1157
1158 /* Extra switches sometimes passed to the linker. */
1159 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1160 will interpret it as a -b option. */
1161
1162 #ifndef LINK_SPEC
1163 #define LINK_SPEC "\
1164 %(endian_spec) \
1165 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1166 %{bestGnum} %{shared} %{non_shared}"
1167 #endif /* LINK_SPEC defined */
1168
1169
1170 /* Specs for the compiler proper */
1171
1172 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1173 overridden by subtargets. */
1174 #ifndef SUBTARGET_CC1_SPEC
1175 #define SUBTARGET_CC1_SPEC ""
1176 #endif
1177
1178 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1179
1180 #undef CC1_SPEC
1181 #define CC1_SPEC "\
1182 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1183 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1184 %{save-temps: } \
1185 %(subtarget_cc1_spec)"
1186
1187 /* Preprocessor specs. */
1188
1189 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1190 overridden by subtargets. */
1191 #ifndef SUBTARGET_CPP_SPEC
1192 #define SUBTARGET_CPP_SPEC ""
1193 #endif
1194
1195 #define CPP_SPEC "%(subtarget_cpp_spec)"
1196
1197 /* This macro defines names of additional specifications to put in the specs
1198 that can be used in various specifications like CC1_SPEC. Its definition
1199 is an initializer with a subgrouping for each command option.
1200
1201 Each subgrouping contains a string constant, that defines the
1202 specification name, and a string constant that used by the GCC driver
1203 program.
1204
1205 Do not define this macro if it does not need to do anything. */
1206
1207 #define EXTRA_SPECS \
1208 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1209 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1210 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1211 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1212 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1213 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1214 { "endian_spec", ENDIAN_SPEC }, \
1215 SUBTARGET_EXTRA_SPECS
1216
1217 #ifndef SUBTARGET_EXTRA_SPECS
1218 #define SUBTARGET_EXTRA_SPECS
1219 #endif
1220 \f
1221 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1222 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1223
1224 #ifndef PREFERRED_DEBUGGING_TYPE
1225 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1226 #endif
1227
1228 /* The size of DWARF addresses should be the same as the size of symbols
1229 in the target file format. They shouldn't depend on things like -msym32,
1230 because many DWARF consumers do not allow the mixture of address sizes
1231 that one would then get from linking -msym32 code with -msym64 code.
1232
1233 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1234 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1235 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1236
1237 /* By default, turn on GDB extensions. */
1238 #define DEFAULT_GDB_EXTENSIONS 1
1239
1240 /* Local compiler-generated symbols must have a prefix that the assembler
1241 understands. By default, this is $, although some targets (e.g.,
1242 NetBSD-ELF) need to override this. */
1243
1244 #ifndef LOCAL_LABEL_PREFIX
1245 #define LOCAL_LABEL_PREFIX "$"
1246 #endif
1247
1248 /* By default on the mips, external symbols do not have an underscore
1249 prepended, but some targets (e.g., NetBSD) require this. */
1250
1251 #ifndef USER_LABEL_PREFIX
1252 #define USER_LABEL_PREFIX ""
1253 #endif
1254
1255 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1256 since the length can run past this up to a continuation point. */
1257 #undef DBX_CONTIN_LENGTH
1258 #define DBX_CONTIN_LENGTH 1500
1259
1260 /* How to renumber registers for dbx and gdb. */
1261 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1262
1263 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1264 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1265
1266 /* The DWARF 2 CFA column which tracks the return address. */
1267 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1268
1269 /* Before the prologue, RA lives in r31. */
1270 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1271
1272 /* Describe how we implement __builtin_eh_return. */
1273 #define EH_RETURN_DATA_REGNO(N) \
1274 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1275
1276 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1277
1278 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1279 The default for this in 64-bit mode is 8, which causes problems with
1280 SFmode register saves. */
1281 #define DWARF_CIE_DATA_ALIGNMENT -4
1282
1283 /* Correct the offset of automatic variables and arguments. Note that
1284 the MIPS debug format wants all automatic variables and arguments
1285 to be in terms of the virtual frame pointer (stack pointer before
1286 any adjustment in the function), while the MIPS 3.0 linker wants
1287 the frame pointer to be the stack pointer after the initial
1288 adjustment. */
1289
1290 #define DEBUGGER_AUTO_OFFSET(X) \
1291 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1292 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1293 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1294 \f
1295 /* Target machine storage layout */
1296
1297 #define BITS_BIG_ENDIAN 0
1298 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1299 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1300
1301 /* Define this to set the endianness to use in libgcc2.c, which can
1302 not depend on target_flags. */
1303 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1304 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1305 #else
1306 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1307 #endif
1308
1309 #define MAX_BITS_PER_WORD 64
1310
1311 /* Width of a word, in units (bytes). */
1312 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1313 #ifndef IN_LIBGCC2
1314 #define MIN_UNITS_PER_WORD 4
1315 #endif
1316
1317 /* For MIPS, width of a floating point register. */
1318 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1319
1320 /* The number of consecutive floating-point registers needed to store the
1321 largest format supported by the FPU. */
1322 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1323
1324 /* The number of consecutive floating-point registers needed to store the
1325 smallest format supported by the FPU. */
1326 #define MIN_FPRS_PER_FMT \
1327 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1328 ? 1 : MAX_FPRS_PER_FMT)
1329
1330 /* The largest size of value that can be held in floating-point
1331 registers and moved with a single instruction. */
1332 #define UNITS_PER_HWFPVALUE \
1333 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1334
1335 /* The largest size of value that can be held in floating-point
1336 registers. */
1337 #define UNITS_PER_FPVALUE \
1338 (TARGET_SOFT_FLOAT_ABI ? 0 \
1339 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1340 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1341
1342 /* The number of bytes in a double. */
1343 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1344
1345 #define UNITS_PER_SIMD_WORD(MODE) \
1346 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1347
1348 /* Set the sizes of the core types. */
1349 #define SHORT_TYPE_SIZE 16
1350 #define INT_TYPE_SIZE 32
1351 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1352 #define LONG_LONG_TYPE_SIZE 64
1353
1354 #define FLOAT_TYPE_SIZE 32
1355 #define DOUBLE_TYPE_SIZE 64
1356 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1357
1358 /* Define the sizes of fixed-point types. */
1359 #define SHORT_FRACT_TYPE_SIZE 8
1360 #define FRACT_TYPE_SIZE 16
1361 #define LONG_FRACT_TYPE_SIZE 32
1362 #define LONG_LONG_FRACT_TYPE_SIZE 64
1363
1364 #define SHORT_ACCUM_TYPE_SIZE 16
1365 #define ACCUM_TYPE_SIZE 32
1366 #define LONG_ACCUM_TYPE_SIZE 64
1367 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1368 doesn't support 128-bit integers for MIPS32 currently. */
1369 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1370
1371 /* long double is not a fixed mode, but the idea is that, if we
1372 support long double, we also want a 128-bit integer type. */
1373 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1374
1375 #ifdef IN_LIBGCC2
1376 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1377 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1378 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1379 # else
1380 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1381 # endif
1382 #endif
1383
1384 /* Width in bits of a pointer. */
1385 #ifndef POINTER_SIZE
1386 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1387 #endif
1388
1389 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1390 #define PARM_BOUNDARY BITS_PER_WORD
1391
1392 /* Allocation boundary (in *bits*) for the code of a function. */
1393 #define FUNCTION_BOUNDARY 32
1394
1395 /* Alignment of field after `int : 0' in a structure. */
1396 #define EMPTY_FIELD_BOUNDARY 32
1397
1398 /* Every structure's size must be a multiple of this. */
1399 /* 8 is observed right on a DECstation and on riscos 4.02. */
1400 #define STRUCTURE_SIZE_BOUNDARY 8
1401
1402 /* There is no point aligning anything to a rounder boundary than this. */
1403 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1404
1405 /* All accesses must be aligned. */
1406 #define STRICT_ALIGNMENT 1
1407
1408 /* Define this if you wish to imitate the way many other C compilers
1409 handle alignment of bitfields and the structures that contain
1410 them.
1411
1412 The behavior is that the type written for a bit-field (`int',
1413 `short', or other integer type) imposes an alignment for the
1414 entire structure, as if the structure really did contain an
1415 ordinary field of that type. In addition, the bit-field is placed
1416 within the structure so that it would fit within such a field,
1417 not crossing a boundary for it.
1418
1419 Thus, on most machines, a bit-field whose type is written as `int'
1420 would not cross a four-byte boundary, and would force four-byte
1421 alignment for the whole structure. (The alignment used may not
1422 be four bytes; it is controlled by the other alignment
1423 parameters.)
1424
1425 If the macro is defined, its definition should be a C expression;
1426 a nonzero value for the expression enables this behavior. */
1427
1428 #define PCC_BITFIELD_TYPE_MATTERS 1
1429
1430 /* If defined, a C expression to compute the alignment given to a
1431 constant that is being placed in memory. CONSTANT is the constant
1432 and ALIGN is the alignment that the object would ordinarily have.
1433 The value of this macro is used instead of that alignment to align
1434 the object.
1435
1436 If this macro is not defined, then ALIGN is used.
1437
1438 The typical use of this macro is to increase alignment for string
1439 constants to be word aligned so that `strcpy' calls that copy
1440 constants can be done inline. */
1441
1442 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1443 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1444 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1445
1446 /* If defined, a C expression to compute the alignment for a static
1447 variable. TYPE is the data type, and ALIGN is the alignment that
1448 the object would ordinarily have. The value of this macro is used
1449 instead of that alignment to align the object.
1450
1451 If this macro is not defined, then ALIGN is used.
1452
1453 One use of this macro is to increase alignment of medium-size
1454 data to make it all fit in fewer cache lines. Another is to
1455 cause character arrays to be word-aligned so that `strcpy' calls
1456 that copy constants to character arrays can be done inline. */
1457
1458 #undef DATA_ALIGNMENT
1459 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1460 ((((ALIGN) < BITS_PER_WORD) \
1461 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1462 || TREE_CODE (TYPE) == UNION_TYPE \
1463 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1464
1465 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1466 character arrays to be word-aligned so that `strcpy' calls that copy
1467 constants to character arrays can be done inline, and 'strcmp' can be
1468 optimised to use word loads. */
1469 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1470 DATA_ALIGNMENT (TYPE, ALIGN)
1471
1472 #define PAD_VARARGS_DOWN \
1473 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1474
1475 /* Define if operations between registers always perform the operation
1476 on the full register even if a narrower mode is specified. */
1477 #define WORD_REGISTER_OPERATIONS
1478
1479 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1480 moves. All other references are zero extended. */
1481 #define LOAD_EXTEND_OP(MODE) \
1482 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1483 ? SIGN_EXTEND : ZERO_EXTEND)
1484
1485 /* Define this macro if it is advisable to hold scalars in registers
1486 in a wider mode than that declared by the program. In such cases,
1487 the value is constrained to be within the bounds of the declared
1488 type, but kept valid in the wider mode. The signedness of the
1489 extension may differ from that of the type. */
1490
1491 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1492 if (GET_MODE_CLASS (MODE) == MODE_INT \
1493 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1494 { \
1495 if ((MODE) == SImode) \
1496 (UNSIGNEDP) = 0; \
1497 (MODE) = Pmode; \
1498 }
1499
1500 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1501 Extensions of pointers to word_mode must be signed. */
1502 #define POINTERS_EXTEND_UNSIGNED false
1503
1504 /* Define if loading short immediate values into registers sign extends. */
1505 #define SHORT_IMMEDIATES_SIGN_EXTEND
1506
1507 /* The [d]clz instructions have the natural values at 0. */
1508
1509 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1510 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1511 \f
1512 /* Standard register usage. */
1513
1514 /* Number of hardware registers. We have:
1515
1516 - 32 integer registers
1517 - 32 floating point registers
1518 - 8 condition code registers
1519 - 2 accumulator registers (hi and lo)
1520 - 32 registers each for coprocessors 0, 2 and 3
1521 - 3 fake registers:
1522 - ARG_POINTER_REGNUM
1523 - FRAME_POINTER_REGNUM
1524 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1525 - 3 dummy entries that were used at various times in the past.
1526 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1527 - 6 DSP control registers */
1528
1529 #define FIRST_PSEUDO_REGISTER 188
1530
1531 /* By default, fix the kernel registers ($26 and $27), the global
1532 pointer ($28) and the stack pointer ($29). This can change
1533 depending on the command-line options.
1534
1535 Regarding coprocessor registers: without evidence to the contrary,
1536 it's best to assume that each coprocessor register has a unique
1537 use. This can be overridden, in, e.g., mips_override_options or
1538 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1539 for a particular target. */
1540
1541 #define FIXED_REGISTERS \
1542 { \
1543 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1544 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1545 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1546 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1547 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1548 /* COP0 registers */ \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1551 /* COP2 registers */ \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1554 /* COP3 registers */ \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1557 /* 6 DSP accumulator registers & 6 control registers */ \
1558 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1559 }
1560
1561
1562 /* Set up this array for o32 by default.
1563
1564 Note that we don't mark $31 as a call-clobbered register. The idea is
1565 that it's really the call instructions themselves which clobber $31.
1566 We don't care what the called function does with it afterwards.
1567
1568 This approach makes it easier to implement sibcalls. Unlike normal
1569 calls, sibcalls don't clobber $31, so the register reaches the
1570 called function in tact. EPILOGUE_USES says that $31 is useful
1571 to the called function. */
1572
1573 #define CALL_USED_REGISTERS \
1574 { \
1575 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1576 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1577 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1578 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1579 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1580 /* COP0 registers */ \
1581 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1582 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1583 /* COP2 registers */ \
1584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1585 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1586 /* COP3 registers */ \
1587 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1588 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1589 /* 6 DSP accumulator registers & 6 control registers */ \
1590 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1591 }
1592
1593
1594 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1595
1596 #define CALL_REALLY_USED_REGISTERS \
1597 { /* General registers. */ \
1598 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1599 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1600 /* Floating-point registers. */ \
1601 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1602 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1603 /* Others. */ \
1604 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1605 /* COP0 registers */ \
1606 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1607 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1608 /* COP2 registers */ \
1609 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1610 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1611 /* COP3 registers */ \
1612 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1613 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1614 /* 6 DSP accumulator registers & 6 control registers */ \
1615 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1616 }
1617
1618 /* Internal macros to classify a register number as to whether it's a
1619 general purpose register, a floating point register, a
1620 multiply/divide register, or a status register. */
1621
1622 #define GP_REG_FIRST 0
1623 #define GP_REG_LAST 31
1624 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1625 #define GP_DBX_FIRST 0
1626 #define K0_REG_NUM (GP_REG_FIRST + 26)
1627 #define K1_REG_NUM (GP_REG_FIRST + 27)
1628 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1629
1630 #define FP_REG_FIRST 32
1631 #define FP_REG_LAST 63
1632 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1633 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1634
1635 #define MD_REG_FIRST 64
1636 #define MD_REG_LAST 65
1637 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1638 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1639
1640 /* The DWARF 2 CFA column which tracks the return address from a
1641 signal handler context. This means that to maintain backwards
1642 compatibility, no hard register can be assigned this column if it
1643 would need to be handled by the DWARF unwinder. */
1644 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1645
1646 #define ST_REG_FIRST 67
1647 #define ST_REG_LAST 74
1648 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1649
1650
1651 /* FIXME: renumber. */
1652 #define COP0_REG_FIRST 80
1653 #define COP0_REG_LAST 111
1654 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1655
1656 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1657 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1658 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1659
1660 #define COP2_REG_FIRST 112
1661 #define COP2_REG_LAST 143
1662 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1663
1664 #define COP3_REG_FIRST 144
1665 #define COP3_REG_LAST 175
1666 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1667 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1668 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1669
1670 #define DSP_ACC_REG_FIRST 176
1671 #define DSP_ACC_REG_LAST 181
1672 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1673
1674 #define AT_REGNUM (GP_REG_FIRST + 1)
1675 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1676 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1677
1678 /* A few bitfield locations for the coprocessor registers. */
1679 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1680 the cause register for the EIC interrupt mode. */
1681 #define CAUSE_IPL 10
1682 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1683 #define SR_IPL 10
1684 /* Exception Level is at bit 1 of the status register. */
1685 #define SR_EXL 1
1686 /* Interrupt Enable is at bit 0 of the status register. */
1687 #define SR_IE 0
1688
1689 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1690 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1691 should be used instead. */
1692 #define FPSW_REGNUM ST_REG_FIRST
1693
1694 #define GP_REG_P(REGNO) \
1695 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1696 #define M16_REG_P(REGNO) \
1697 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1698 #define FP_REG_P(REGNO) \
1699 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1700 #define MD_REG_P(REGNO) \
1701 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1702 #define ST_REG_P(REGNO) \
1703 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1704 #define COP0_REG_P(REGNO) \
1705 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1706 #define COP2_REG_P(REGNO) \
1707 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1708 #define COP3_REG_P(REGNO) \
1709 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1710 #define ALL_COP_REG_P(REGNO) \
1711 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1712 /* Test if REGNO is one of the 6 new DSP accumulators. */
1713 #define DSP_ACC_REG_P(REGNO) \
1714 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1715 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1716 #define ACC_REG_P(REGNO) \
1717 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1718
1719 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1720
1721 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1722 to initialize the mips16 gp pseudo register. */
1723 #define CONST_GP_P(X) \
1724 (GET_CODE (X) == CONST \
1725 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1726 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1727
1728 /* Return coprocessor number from register number. */
1729
1730 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1731 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1732 : COP3_REG_P (REGNO) ? '3' : '?')
1733
1734
1735 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1736
1737 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1738 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1739
1740 #define MODES_TIEABLE_P mips_modes_tieable_p
1741
1742 /* Register to use for pushing function arguments. */
1743 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1744
1745 /* These two registers don't really exist: they get eliminated to either
1746 the stack or hard frame pointer. */
1747 #define ARG_POINTER_REGNUM 77
1748 #define FRAME_POINTER_REGNUM 78
1749
1750 /* $30 is not available on the mips16, so we use $17 as the frame
1751 pointer. */
1752 #define HARD_FRAME_POINTER_REGNUM \
1753 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1754
1755 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1756
1757 /* Register in which static-chain is passed to a function. */
1758 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1759
1760 /* Registers used as temporaries in prologue/epilogue code:
1761
1762 - If a MIPS16 PIC function needs access to _gp, it first loads
1763 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1764
1765 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1766 register. The register must not conflict with MIPS16_PIC_TEMP.
1767
1768 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1769 register.
1770
1771 If we're generating MIPS16 code, these registers must come from the
1772 core set of 8. The prologue registers mustn't conflict with any
1773 incoming arguments, the static chain pointer, or the frame pointer.
1774 The epilogue temporary mustn't conflict with the return registers,
1775 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1776 or the EH data registers.
1777
1778 If we're generating interrupt handlers, we use K0 as a temporary register
1779 in prologue/epilogue code. */
1780
1781 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1782 #define MIPS_PROLOGUE_TEMP_REGNUM \
1783 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1784 #define MIPS_EPILOGUE_TEMP_REGNUM \
1785 (cfun->machine->interrupt_handler_p \
1786 ? K0_REG_NUM \
1787 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1788
1789 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1790 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1791 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1792
1793 /* Define this macro if it is as good or better to call a constant
1794 function address than to call an address kept in a register. */
1795 #define NO_FUNCTION_CSE 1
1796
1797 /* The ABI-defined global pointer. Sometimes we use a different
1798 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1799 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1800
1801 /* We normally use $28 as the global pointer. However, when generating
1802 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1803 register instead. They can then avoid saving and restoring $28
1804 and perhaps avoid using a frame at all.
1805
1806 When a leaf function uses something other than $28, mips_expand_prologue
1807 will modify pic_offset_table_rtx in place. Take the register number
1808 from there after reload. */
1809 #define PIC_OFFSET_TABLE_REGNUM \
1810 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1811
1812 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1813 \f
1814 /* Define the classes of registers for register constraints in the
1815 machine description. Also define ranges of constants.
1816
1817 One of the classes must always be named ALL_REGS and include all hard regs.
1818 If there is more than one class, another class must be named NO_REGS
1819 and contain no registers.
1820
1821 The name GENERAL_REGS must be the name of a class (or an alias for
1822 another name such as ALL_REGS). This is the class of registers
1823 that is allowed by "g" or "r" in a register constraint.
1824 Also, registers outside this class are allocated only when
1825 instructions express preferences for them.
1826
1827 The classes must be numbered in nondecreasing order; that is,
1828 a larger-numbered class must never be contained completely
1829 in a smaller-numbered class.
1830
1831 For any two classes, it is very desirable that there be another
1832 class that represents their union. */
1833
1834 enum reg_class
1835 {
1836 NO_REGS, /* no registers in set */
1837 M16_REGS, /* mips16 directly accessible registers */
1838 T_REG, /* mips16 T register ($24) */
1839 M16_T_REGS, /* mips16 registers plus T register */
1840 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1841 V1_REG, /* Register $v1 ($3) used for TLS access. */
1842 LEA_REGS, /* Every GPR except $25 */
1843 GR_REGS, /* integer registers */
1844 FP_REGS, /* floating point registers */
1845 MD0_REG, /* first multiply/divide register */
1846 MD1_REG, /* second multiply/divide register */
1847 MD_REGS, /* multiply/divide registers (hi/lo) */
1848 COP0_REGS, /* generic coprocessor classes */
1849 COP2_REGS,
1850 COP3_REGS,
1851 ST_REGS, /* status registers (fp status) */
1852 DSP_ACC_REGS, /* DSP accumulator registers */
1853 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1854 FRAME_REGS, /* $arg and $frame */
1855 GR_AND_MD0_REGS, /* union classes */
1856 GR_AND_MD1_REGS,
1857 GR_AND_MD_REGS,
1858 GR_AND_ACC_REGS,
1859 ALL_REGS, /* all registers */
1860 LIM_REG_CLASSES /* max value + 1 */
1861 };
1862
1863 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1864
1865 #define GENERAL_REGS GR_REGS
1866
1867 /* An initializer containing the names of the register classes as C
1868 string constants. These names are used in writing some of the
1869 debugging dumps. */
1870
1871 #define REG_CLASS_NAMES \
1872 { \
1873 "NO_REGS", \
1874 "M16_REGS", \
1875 "T_REG", \
1876 "M16_T_REGS", \
1877 "PIC_FN_ADDR_REG", \
1878 "V1_REG", \
1879 "LEA_REGS", \
1880 "GR_REGS", \
1881 "FP_REGS", \
1882 "MD0_REG", \
1883 "MD1_REG", \
1884 "MD_REGS", \
1885 /* coprocessor registers */ \
1886 "COP0_REGS", \
1887 "COP2_REGS", \
1888 "COP3_REGS", \
1889 "ST_REGS", \
1890 "DSP_ACC_REGS", \
1891 "ACC_REGS", \
1892 "FRAME_REGS", \
1893 "GR_AND_MD0_REGS", \
1894 "GR_AND_MD1_REGS", \
1895 "GR_AND_MD_REGS", \
1896 "GR_AND_ACC_REGS", \
1897 "ALL_REGS" \
1898 }
1899
1900 /* An initializer containing the contents of the register classes,
1901 as integers which are bit masks. The Nth integer specifies the
1902 contents of class N. The way the integer MASK is interpreted is
1903 that register R is in the class if `MASK & (1 << R)' is 1.
1904
1905 When the machine has more than 32 registers, an integer does not
1906 suffice. Then the integers are replaced by sub-initializers,
1907 braced groupings containing several integers. Each
1908 sub-initializer must be suitable as an initializer for the type
1909 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1910
1911 #define REG_CLASS_CONTENTS \
1912 { \
1913 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1914 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
1915 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
1916 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
1917 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
1918 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
1919 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
1920 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
1921 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
1922 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
1923 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
1924 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
1925 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
1926 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
1927 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
1928 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
1929 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
1930 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
1931 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
1932 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
1933 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
1934 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
1935 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
1936 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
1937 }
1938
1939
1940 /* A C expression whose value is a register class containing hard
1941 register REGNO. In general there is more that one such class;
1942 choose a class which is "minimal", meaning that no smaller class
1943 also contains the register. */
1944
1945 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1946
1947 /* A macro whose definition is the name of the class to which a
1948 valid base register must belong. A base register is one used in
1949 an address which is the register value plus a displacement. */
1950
1951 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1952
1953 /* A macro whose definition is the name of the class to which a
1954 valid index register must belong. An index register is one used
1955 in an address where its value is either multiplied by a scale
1956 factor or added to another register (as well as added to a
1957 displacement). */
1958
1959 #define INDEX_REG_CLASS NO_REGS
1960
1961 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1962 registers explicitly used in the rtl to be used as spill registers
1963 but prevents the compiler from extending the lifetime of these
1964 registers. */
1965
1966 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1967
1968 /* We generally want to put call-clobbered registers ahead of
1969 call-saved ones. (IRA expects this.) */
1970
1971 #define REG_ALLOC_ORDER \
1972 { /* Accumulator registers. When GPRs and accumulators have equal \
1973 cost, we generally prefer to use accumulators. For example, \
1974 a division of multiplication result is better allocated to LO, \
1975 so that we put the MFLO at the point of use instead of at the \
1976 point of definition. It's also needed if we're to take advantage \
1977 of the extra accumulators available with -mdspr2. In some cases, \
1978 it can also help to reduce register pressure. */ \
1979 64, 65,176,177,178,179,180,181, \
1980 /* Call-clobbered GPRs. */ \
1981 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1982 24, 25, 31, \
1983 /* The global pointer. This is call-clobbered for o32 and o64 \
1984 abicalls, call-saved for n32 and n64 abicalls, and a program \
1985 invariant otherwise. Putting it between the call-clobbered \
1986 and call-saved registers should cope with all eventualities. */ \
1987 28, \
1988 /* Call-saved GPRs. */ \
1989 16, 17, 18, 19, 20, 21, 22, 23, 30, \
1990 /* GPRs that can never be exposed to the register allocator. */ \
1991 0, 26, 27, 29, \
1992 /* Call-clobbered FPRs. */ \
1993 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1994 48, 49, 50, 51, \
1995 /* FPRs that are usually call-saved. The odd ones are actually \
1996 call-clobbered for n32, but listing them ahead of the even \
1997 registers might encourage the register allocator to fragment \
1998 the available FPR pairs. We need paired FPRs to store long \
1999 doubles, so it isn't clear that using a different order \
2000 for n32 would be a win. */ \
2001 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2002 /* None of the remaining classes have defined call-saved \
2003 registers. */ \
2004 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2005 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2006 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2007 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2008 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2009 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2010 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2011 182,183,184,185,186,187 \
2012 }
2013
2014 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2015 to be rearranged based on a particular function. On the mips16, we
2016 want to allocate $24 (T_REG) before other registers for
2017 instructions for which it is possible. */
2018
2019 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2020
2021 /* True if VALUE is an unsigned 6-bit number. */
2022
2023 #define UIMM6_OPERAND(VALUE) \
2024 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2025
2026 /* True if VALUE is a signed 10-bit number. */
2027
2028 #define IMM10_OPERAND(VALUE) \
2029 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2030
2031 /* True if VALUE is a signed 16-bit number. */
2032
2033 #define SMALL_OPERAND(VALUE) \
2034 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2035
2036 /* True if VALUE is an unsigned 16-bit number. */
2037
2038 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2039 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2040
2041 /* True if VALUE can be loaded into a register using LUI. */
2042
2043 #define LUI_OPERAND(VALUE) \
2044 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2045 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2046
2047 /* Return a value X with the low 16 bits clear, and such that
2048 VALUE - X is a signed 16-bit value. */
2049
2050 #define CONST_HIGH_PART(VALUE) \
2051 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2052
2053 #define CONST_LOW_PART(VALUE) \
2054 ((VALUE) - CONST_HIGH_PART (VALUE))
2055
2056 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2057 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2058 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2059
2060 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2061 mips_preferred_reload_class (X, CLASS)
2062
2063 /* The HI and LO registers can only be reloaded via the general
2064 registers. Condition code registers can only be loaded to the
2065 general registers, and from the floating point registers. */
2066
2067 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2068 mips_secondary_reload_class (CLASS, MODE, X, true)
2069 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2070 mips_secondary_reload_class (CLASS, MODE, X, false)
2071
2072 /* Return the maximum number of consecutive registers
2073 needed to represent mode MODE in a register of class CLASS. */
2074
2075 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2076
2077 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2078 mips_cannot_change_mode_class (FROM, TO, CLASS)
2079 \f
2080 /* Stack layout; function entry, exit and calling. */
2081
2082 #define STACK_GROWS_DOWNWARD
2083
2084 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2085
2086 /* Size of the area allocated in the frame to save the GP. */
2087
2088 #define MIPS_GP_SAVE_AREA_SIZE \
2089 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2090
2091 /* The offset of the first local variable from the frame pointer. See
2092 mips_compute_frame_info for details about the frame layout. */
2093
2094 #define STARTING_FRAME_OFFSET \
2095 (FRAME_GROWS_DOWNWARD \
2096 ? 0 \
2097 : crtl->outgoing_args_size + MIPS_GP_SAVE_AREA_SIZE)
2098
2099 #define RETURN_ADDR_RTX mips_return_addr
2100
2101 /* Mask off the MIPS16 ISA bit in unwind addresses.
2102
2103 The reason for this is a little subtle. When unwinding a call,
2104 we are given the call's return address, which on most targets
2105 is the address of the following instruction. However, what we
2106 actually want to find is the EH region for the call itself.
2107 The target-independent unwind code therefore searches for "RA - 1".
2108
2109 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2110 RA - 1 is therefore the real (even-valued) start of the return
2111 instruction. EH region labels are usually odd-valued MIPS16 symbols
2112 too, so a search for an even address within a MIPS16 region would
2113 usually work.
2114
2115 However, there is an exception. If the end of an EH region is also
2116 the end of a function, the end label is allowed to be even. This is
2117 necessary because a following non-MIPS16 function may also need EH
2118 information for its first instruction.
2119
2120 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2121 non-ISA-encoded address. This probably isn't ideal, but it is
2122 the traditional (legacy) behavior. It is therefore only safe
2123 to search MIPS EH regions for an _odd-valued_ address.
2124
2125 Masking off the ISA bit means that the target-independent code
2126 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2127 #define MASK_RETURN_ADDR GEN_INT (-2)
2128
2129
2130 /* Similarly, don't use the least-significant bit to tell pointers to
2131 code from vtable index. */
2132
2133 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2134
2135 /* The eliminations to $17 are only used for mips16 code. See the
2136 definition of HARD_FRAME_POINTER_REGNUM. */
2137
2138 #define ELIMINABLE_REGS \
2139 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2140 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2141 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2142 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2143 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2144 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2145
2146 /* Make sure that we're not trying to eliminate to the wrong hard frame
2147 pointer. */
2148 #define CAN_ELIMINATE(FROM, TO) \
2149 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
2150
2151 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2152 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2153
2154 /* Allocate stack space for arguments at the beginning of each function. */
2155 #define ACCUMULATE_OUTGOING_ARGS 1
2156
2157 /* The argument pointer always points to the first argument. */
2158 #define FIRST_PARM_OFFSET(FNDECL) 0
2159
2160 /* o32 and o64 reserve stack space for all argument registers. */
2161 #define REG_PARM_STACK_SPACE(FNDECL) \
2162 (TARGET_OLDABI \
2163 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2164 : 0)
2165
2166 /* Define this if it is the responsibility of the caller to
2167 allocate the area reserved for arguments passed in registers.
2168 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2169 of this macro is to determine whether the space is included in
2170 `crtl->outgoing_args_size'. */
2171 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2172
2173 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2174 \f
2175 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2176
2177 /* Symbolic macros for the registers used to return integer and floating
2178 point values. */
2179
2180 #define GP_RETURN (GP_REG_FIRST + 2)
2181 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2182
2183 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2184
2185 /* Symbolic macros for the first/last argument registers. */
2186
2187 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2188 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2189 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2190 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2191
2192 #define LIBCALL_VALUE(MODE) \
2193 mips_function_value (NULL_TREE, MODE)
2194
2195 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2196 mips_function_value (VALTYPE, VOIDmode)
2197
2198 /* 1 if N is a possible register number for a function value.
2199 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2200 Currently, R2 and F0 are only implemented here (C has no complex type) */
2201
2202 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2203 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2204 && (N) == FP_RETURN + 2))
2205
2206 /* 1 if N is a possible register number for function argument passing.
2207 We have no FP argument registers when soft-float. When FP registers
2208 are 32 bits, we can't directly reference the odd numbered ones. */
2209
2210 #define FUNCTION_ARG_REGNO_P(N) \
2211 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2212 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2213 && !fixed_regs[N])
2214 \f
2215 /* This structure has to cope with two different argument allocation
2216 schemes. Most MIPS ABIs view the arguments as a structure, of which
2217 the first N words go in registers and the rest go on the stack. If I
2218 < N, the Ith word might go in Ith integer argument register or in a
2219 floating-point register. For these ABIs, we only need to remember
2220 the offset of the current argument into the structure.
2221
2222 The EABI instead allocates the integer and floating-point arguments
2223 separately. The first N words of FP arguments go in FP registers,
2224 the rest go on the stack. Likewise, the first N words of the other
2225 arguments go in integer registers, and the rest go on the stack. We
2226 need to maintain three counts: the number of integer registers used,
2227 the number of floating-point registers used, and the number of words
2228 passed on the stack.
2229
2230 We could keep separate information for the two ABIs (a word count for
2231 the standard ABIs, and three separate counts for the EABI). But it
2232 seems simpler to view the standard ABIs as forms of EABI that do not
2233 allocate floating-point registers.
2234
2235 So for the standard ABIs, the first N words are allocated to integer
2236 registers, and mips_function_arg decides on an argument-by-argument
2237 basis whether that argument should really go in an integer register,
2238 or in a floating-point one. */
2239
2240 typedef struct mips_args {
2241 /* Always true for varargs functions. Otherwise true if at least
2242 one argument has been passed in an integer register. */
2243 int gp_reg_found;
2244
2245 /* The number of arguments seen so far. */
2246 unsigned int arg_number;
2247
2248 /* The number of integer registers used so far. For all ABIs except
2249 EABI, this is the number of words that have been added to the
2250 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2251 unsigned int num_gprs;
2252
2253 /* For EABI, the number of floating-point registers used so far. */
2254 unsigned int num_fprs;
2255
2256 /* The number of words passed on the stack. */
2257 unsigned int stack_words;
2258
2259 /* On the mips16, we need to keep track of which floating point
2260 arguments were passed in general registers, but would have been
2261 passed in the FP regs if this were a 32-bit function, so that we
2262 can move them to the FP regs if we wind up calling a 32-bit
2263 function. We record this information in fp_code, encoded in base
2264 four. A zero digit means no floating point argument, a one digit
2265 means an SFmode argument, and a two digit means a DFmode argument,
2266 and a three digit is not used. The low order digit is the first
2267 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2268 an SFmode argument. ??? A more sophisticated approach will be
2269 needed if MIPS_ABI != ABI_32. */
2270 int fp_code;
2271
2272 /* True if the function has a prototype. */
2273 int prototype;
2274 } CUMULATIVE_ARGS;
2275
2276 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2277 for a call to a function whose data type is FNTYPE.
2278 For a library call, FNTYPE is 0. */
2279
2280 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2281 mips_init_cumulative_args (&CUM, FNTYPE)
2282
2283 /* Update the data in CUM to advance over an argument
2284 of mode MODE and data type TYPE.
2285 (TYPE is null for libcalls where that information may not be available.) */
2286
2287 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2288 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2289
2290 /* Determine where to put an argument to a function.
2291 Value is zero to push the argument on the stack,
2292 or a hard register in which to store the argument.
2293
2294 MODE is the argument's machine mode.
2295 TYPE is the data type of the argument (as a tree).
2296 This is null for libcalls where that information may
2297 not be available.
2298 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2299 the preceding args and about the function being called.
2300 NAMED is nonzero if this argument is a named parameter
2301 (otherwise it is an extra parameter matching an ellipsis). */
2302
2303 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2304 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2305
2306 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2307
2308 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2309 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2310
2311 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2312 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2313
2314 /* True if using EABI and varargs can be passed in floating-point
2315 registers. Under these conditions, we need a more complex form
2316 of va_list, which tracks GPR, FPR and stack arguments separately. */
2317 #define EABI_FLOAT_VARARGS_P \
2318 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2319
2320 \f
2321 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2322
2323 /* Treat LOC as a byte offset from the stack pointer and round it up
2324 to the next fully-aligned offset. */
2325 #define MIPS_STACK_ALIGN(LOC) \
2326 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2327
2328 \f
2329 /* Output assembler code to FILE to increment profiler label # LABELNO
2330 for profiling a function entry. */
2331
2332 #define FUNCTION_PROFILER(FILE, LABELNO) \
2333 { \
2334 if (TARGET_MIPS16) \
2335 sorry ("mips16 function profiling"); \
2336 if (TARGET_LONG_CALLS) \
2337 { \
2338 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */ \
2339 if (Pmode == DImode) \
2340 fprintf (FILE, "\tdla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2341 else \
2342 fprintf (FILE, "\tla\t%s,_mcount\n", reg_names[GP_REG_FIRST + 3]); \
2343 } \
2344 fprintf (FILE, "\t.set\tnoat\n"); \
2345 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2346 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2347 /* _mcount treats $2 as the static chain register. */ \
2348 if (cfun->static_chain_decl != NULL) \
2349 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[2], \
2350 reg_names[STATIC_CHAIN_REGNUM]); \
2351 if (!TARGET_NEWABI) \
2352 { \
2353 fprintf (FILE, \
2354 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2355 TARGET_64BIT ? "dsubu" : "subu", \
2356 reg_names[STACK_POINTER_REGNUM], \
2357 reg_names[STACK_POINTER_REGNUM], \
2358 Pmode == DImode ? 16 : 8); \
2359 } \
2360 if (TARGET_LONG_CALLS) \
2361 fprintf (FILE, "\tjalr\t%s\n", reg_names[GP_REG_FIRST + 3]); \
2362 else \
2363 fprintf (FILE, "\tjal\t_mcount\n"); \
2364 fprintf (FILE, "\t.set\tat\n"); \
2365 /* _mcount treats $2 as the static chain register. */ \
2366 if (cfun->static_chain_decl != NULL) \
2367 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], \
2368 reg_names[2]); \
2369 }
2370
2371 /* The profiler preserves all interesting registers, including $31. */
2372 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2373
2374 /* No mips port has ever used the profiler counter word, so don't emit it
2375 or the label for it. */
2376
2377 #define NO_PROFILE_COUNTERS 1
2378
2379 /* Define this macro if the code for function profiling should come
2380 before the function prologue. Normally, the profiling code comes
2381 after. */
2382
2383 /* #define PROFILE_BEFORE_PROLOGUE */
2384
2385 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2386 the stack pointer does not matter. The value is tested only in
2387 functions that have frame pointers.
2388 No definition is equivalent to always zero. */
2389
2390 #define EXIT_IGNORE_STACK 1
2391
2392 \f
2393 /* A C statement to output, on the stream FILE, assembler code for a
2394 block of data that contains the constant parts of a trampoline.
2395 This code should not include a label--the label is taken care of
2396 automatically. */
2397
2398 #define TRAMPOLINE_TEMPLATE(STREAM) \
2399 { \
2400 if (ptr_mode == DImode) \
2401 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2402 else \
2403 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2404 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2405 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2406 if (ptr_mode == DImode) \
2407 { \
2408 fprintf (STREAM, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n"); \
2409 fprintf (STREAM, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n"); \
2410 } \
2411 else \
2412 { \
2413 fprintf (STREAM, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n"); \
2414 fprintf (STREAM, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n"); \
2415 } \
2416 fprintf (STREAM, "\t.word\t0x03200008\t\t# jr $25\n"); \
2417 if (ptr_mode == DImode) \
2418 { \
2419 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2420 fprintf (STREAM, "\t.word\t0x00000000\t\t# <padding>\n"); \
2421 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2422 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2423 } \
2424 else \
2425 { \
2426 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2427 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2428 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2429 } \
2430 }
2431
2432 /* A C expression for the size in bytes of the trampoline, as an
2433 integer. */
2434
2435 #define TRAMPOLINE_SIZE (ptr_mode == DImode ? 48 : 36)
2436
2437 /* Alignment required for trampolines, in bits. */
2438
2439 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2440
2441 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2442 program and data caches. */
2443
2444 #ifndef CACHE_FLUSH_FUNC
2445 #define CACHE_FLUSH_FUNC "_flush_cache"
2446 #endif
2447
2448 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2449 /* Flush both caches. We need to flush the data cache in case \
2450 the system has a write-back cache. */ \
2451 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2452 LCT_NORMAL, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2453 GEN_INT (3), TYPE_MODE (integer_type_node))
2454
2455 /* A C statement to initialize the variable parts of a trampoline.
2456 ADDR is an RTX for the address of the trampoline; FNADDR is an
2457 RTX for the address of the nested function; STATIC_CHAIN is an
2458 RTX for the static chain value that should be passed to the
2459 function when it is called. */
2460
2461 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2462 { \
2463 rtx func_addr, chain_addr, end_addr; \
2464 \
2465 func_addr = plus_constant (ADDR, ptr_mode == DImode ? 32 : 28); \
2466 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2467 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2468 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2469 end_addr = gen_reg_rtx (Pmode); \
2470 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2471 GEN_INT (TRAMPOLINE_SIZE))); \
2472 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2473 }
2474 \f
2475 /* Addressing modes, and classification of registers for them. */
2476
2477 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2478 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2479 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2480
2481 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2482 and check its validity for a certain class.
2483 We have two alternate definitions for each of them.
2484 The usual definition accepts all pseudo regs; the other rejects them all.
2485 The symbol REG_OK_STRICT causes the latter definition to be used.
2486
2487 Most source files want to accept pseudo regs in the hope that
2488 they will get allocated to the class that the insn wants them to be in.
2489 Some source files that are used after register allocation
2490 need to be strict. */
2491
2492 #ifndef REG_OK_STRICT
2493 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2494 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2495 #else
2496 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2497 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2498 #endif
2499
2500 #define REG_OK_FOR_INDEX_P(X) 0
2501
2502 \f
2503 /* Maximum number of registers that can appear in a valid memory address. */
2504
2505 #define MAX_REGS_PER_ADDRESS 1
2506
2507 #ifdef REG_OK_STRICT
2508 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2509 { \
2510 if (mips_legitimate_address_p (MODE, X, 1)) \
2511 goto ADDR; \
2512 }
2513 #else
2514 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2515 { \
2516 if (mips_legitimate_address_p (MODE, X, 0)) \
2517 goto ADDR; \
2518 }
2519 #endif
2520
2521 /* Check for constness inline but use mips_legitimate_address_p
2522 to check whether a constant really is an address. */
2523
2524 #define CONSTANT_ADDRESS_P(X) \
2525 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2526
2527 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2528
2529 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2530 'the start of the function that this code is output in'. */
2531
2532 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2533 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2534 asm_fprintf ((FILE), "%U%s", \
2535 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2536 else \
2537 asm_fprintf ((FILE), "%U%s", (NAME))
2538 \f
2539 /* Flag to mark a function decl symbol that requires a long call. */
2540 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2541 #define SYMBOL_REF_LONG_CALL_P(X) \
2542 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2543
2544 /* This flag marks functions that cannot be lazily bound. */
2545 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2546 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2547 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2548
2549 /* True if we're generating a form of MIPS16 code in which jump tables
2550 are stored in the text section and encoded as 16-bit PC-relative
2551 offsets. This is only possible when general text loads are allowed,
2552 since the table access itself will be an "lh" instruction. */
2553 /* ??? 16-bit offsets can overflow in large functions. */
2554 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2555
2556 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2557
2558 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2559
2560 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2561
2562 /* Define this as 1 if `char' should by default be signed; else as 0. */
2563 #ifndef DEFAULT_SIGNED_CHAR
2564 #define DEFAULT_SIGNED_CHAR 1
2565 #endif
2566
2567 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2568 we generally don't want to use them for copying arbitrary data.
2569 A single N-word move is usually the same cost as N single-word moves. */
2570 #define MOVE_MAX UNITS_PER_WORD
2571 #define MAX_MOVE_MAX 8
2572
2573 /* Define this macro as a C expression which is nonzero if
2574 accessing less than a word of memory (i.e. a `char' or a
2575 `short') is no faster than accessing a word of memory, i.e., if
2576 such access require more than one instruction or if there is no
2577 difference in cost between byte and (aligned) word loads.
2578
2579 On RISC machines, it tends to generate better code to define
2580 this as 1, since it avoids making a QI or HI mode register.
2581
2582 But, generating word accesses for -mips16 is generally bad as shifts
2583 (often extended) would be needed for byte accesses. */
2584 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2585
2586 /* Define this to be nonzero if shift instructions ignore all but the low-order
2587 few bits. */
2588 #define SHIFT_COUNT_TRUNCATED 1
2589
2590 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2591 is done just by pretending it is already truncated. */
2592 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2593 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2594
2595
2596 /* Specify the machine mode that pointers have.
2597 After generation of rtl, the compiler makes no further distinction
2598 between pointers and any other objects of this machine mode. */
2599
2600 #ifndef Pmode
2601 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2602 #endif
2603
2604 /* Give call MEMs SImode since it is the "most permissive" mode
2605 for both 32-bit and 64-bit targets. */
2606
2607 #define FUNCTION_MODE SImode
2608
2609 \f
2610 /* A C expression for the cost of moving data from a register in
2611 class FROM to one in class TO. The classes are expressed using
2612 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2613 the default; other values are interpreted relative to that.
2614
2615 It is not required that the cost always equal 2 when FROM is the
2616 same as TO; on some machines it is expensive to move between
2617 registers if they are not general registers.
2618
2619 If reload sees an insn consisting of a single `set' between two
2620 hard registers, and if `REGISTER_MOVE_COST' applied to their
2621 classes returns a value of 2, reload does not check to ensure
2622 that the constraints of the insn are met. Setting a cost of
2623 other than 2 will allow reload to verify that the constraints are
2624 met. You should do this if the `movM' pattern's constraints do
2625 not allow such copying. */
2626
2627 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2628 mips_register_move_cost (MODE, FROM, TO)
2629
2630 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2631 (mips_cost->memory_latency \
2632 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2633
2634 /* Define if copies to/from condition code registers should be avoided.
2635
2636 This is needed for the MIPS because reload_outcc is not complete;
2637 it needs to handle cases where the source is a general or another
2638 condition code register. */
2639 #define AVOID_CCMODE_COPIES
2640
2641 /* A C expression for the cost of a branch instruction. A value of
2642 1 is the default; other values are interpreted relative to that. */
2643
2644 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2645 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2646
2647 /* If defined, modifies the length assigned to instruction INSN as a
2648 function of the context in which it is used. LENGTH is an lvalue
2649 that contains the initially computed length of the insn and should
2650 be updated with the correct length of the insn. */
2651 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2652 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2653
2654 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2655 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2656 its operands. */
2657 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2658 "%*" OPCODE "%?\t" OPERANDS "%/"
2659
2660 /* Return the asm template for a call. INSN is the instruction's mnemonic
2661 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2662 of the target.
2663
2664 When generating GOT code without explicit relocation operators,
2665 all calls should use assembly macros. Otherwise, all indirect
2666 calls should use "jr" or "jalr"; we will arrange to restore $gp
2667 afterwards if necessary. Finally, we can only generate direct
2668 calls for -mabicalls by temporarily switching to non-PIC mode. */
2669 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2670 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2671 ? "%*" INSN "\t%" #OPNO "%/" \
2672 : REG_P (OPERANDS[OPNO]) \
2673 ? "%*" INSN "r\t%" #OPNO "%/" \
2674 : TARGET_ABICALLS_PIC2 \
2675 ? (".option\tpic0\n\t" \
2676 "%*" INSN "\t%" #OPNO "%/\n\t" \
2677 ".option\tpic2") \
2678 : "%*" INSN "\t%" #OPNO "%/")
2679 \f
2680 /* Control the assembler format that we output. */
2681
2682 /* Output to assembler file text saying following lines
2683 may contain character constants, extra white space, comments, etc. */
2684
2685 #ifndef ASM_APP_ON
2686 #define ASM_APP_ON " #APP\n"
2687 #endif
2688
2689 /* Output to assembler file text saying following lines
2690 no longer contain unusual constructs. */
2691
2692 #ifndef ASM_APP_OFF
2693 #define ASM_APP_OFF " #NO_APP\n"
2694 #endif
2695
2696 #define REGISTER_NAMES \
2697 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2698 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2699 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2700 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2701 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2702 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2703 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2704 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2705 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2706 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2707 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2708 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2709 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2710 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2711 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2712 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2713 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2714 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2715 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2716 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2717 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2718 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2719 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2720 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2721
2722 /* List the "software" names for each register. Also list the numerical
2723 names for $fp and $sp. */
2724
2725 #define ADDITIONAL_REGISTER_NAMES \
2726 { \
2727 { "$29", 29 + GP_REG_FIRST }, \
2728 { "$30", 30 + GP_REG_FIRST }, \
2729 { "at", 1 + GP_REG_FIRST }, \
2730 { "v0", 2 + GP_REG_FIRST }, \
2731 { "v1", 3 + GP_REG_FIRST }, \
2732 { "a0", 4 + GP_REG_FIRST }, \
2733 { "a1", 5 + GP_REG_FIRST }, \
2734 { "a2", 6 + GP_REG_FIRST }, \
2735 { "a3", 7 + GP_REG_FIRST }, \
2736 { "t0", 8 + GP_REG_FIRST }, \
2737 { "t1", 9 + GP_REG_FIRST }, \
2738 { "t2", 10 + GP_REG_FIRST }, \
2739 { "t3", 11 + GP_REG_FIRST }, \
2740 { "t4", 12 + GP_REG_FIRST }, \
2741 { "t5", 13 + GP_REG_FIRST }, \
2742 { "t6", 14 + GP_REG_FIRST }, \
2743 { "t7", 15 + GP_REG_FIRST }, \
2744 { "s0", 16 + GP_REG_FIRST }, \
2745 { "s1", 17 + GP_REG_FIRST }, \
2746 { "s2", 18 + GP_REG_FIRST }, \
2747 { "s3", 19 + GP_REG_FIRST }, \
2748 { "s4", 20 + GP_REG_FIRST }, \
2749 { "s5", 21 + GP_REG_FIRST }, \
2750 { "s6", 22 + GP_REG_FIRST }, \
2751 { "s7", 23 + GP_REG_FIRST }, \
2752 { "t8", 24 + GP_REG_FIRST }, \
2753 { "t9", 25 + GP_REG_FIRST }, \
2754 { "k0", 26 + GP_REG_FIRST }, \
2755 { "k1", 27 + GP_REG_FIRST }, \
2756 { "gp", 28 + GP_REG_FIRST }, \
2757 { "sp", 29 + GP_REG_FIRST }, \
2758 { "fp", 30 + GP_REG_FIRST }, \
2759 { "ra", 31 + GP_REG_FIRST }, \
2760 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2761 }
2762
2763 /* This is meant to be redefined in the host dependent files. It is a
2764 set of alternative names and regnums for mips coprocessors. */
2765
2766 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2767
2768 #define PRINT_OPERAND mips_print_operand
2769 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2770 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2771
2772 /* A C statement, to be executed after all slot-filler instructions
2773 have been output. If necessary, call `dbr_sequence_length' to
2774 determine the number of slots filled in a sequence (zero if not
2775 currently outputting a sequence), to decide how many no-ops to
2776 output, or whatever.
2777
2778 Don't define this macro if it has nothing to do, but it is
2779 helpful in reading assembly output if the extent of the delay
2780 sequence is made explicit (e.g. with white space).
2781
2782 Note that output routines for instructions with delay slots must
2783 be prepared to deal with not being output as part of a sequence
2784 (i.e. when the scheduling pass is not run, or when no slot
2785 fillers could be found.) The variable `final_sequence' is null
2786 when not processing a sequence, otherwise it contains the
2787 `sequence' rtx being output. */
2788
2789 #define DBR_OUTPUT_SEQEND(STREAM) \
2790 do \
2791 { \
2792 if (set_nomacro > 0 && --set_nomacro == 0) \
2793 fputs ("\t.set\tmacro\n", STREAM); \
2794 \
2795 if (set_noreorder > 0 && --set_noreorder == 0) \
2796 fputs ("\t.set\treorder\n", STREAM); \
2797 \
2798 fputs ("\n", STREAM); \
2799 } \
2800 while (0)
2801
2802 /* How to tell the debugger about changes of source files. */
2803 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2804
2805 /* mips-tfile does not understand .stabd directives. */
2806 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2807 dbxout_begin_stabn_sline (LINE); \
2808 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2809 } while (0)
2810
2811 /* Use .loc directives for SDB line numbers. */
2812 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2813 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2814
2815 /* The MIPS implementation uses some labels for its own purpose. The
2816 following lists what labels are created, and are all formed by the
2817 pattern $L[a-z].*. The machine independent portion of GCC creates
2818 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2819
2820 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2821 $Lb[0-9]+ Begin blocks for MIPS debug support
2822 $Lc[0-9]+ Label for use in s<xx> operation.
2823 $Le[0-9]+ End blocks for MIPS debug support */
2824
2825 #undef ASM_DECLARE_OBJECT_NAME
2826 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2827 mips_declare_object (STREAM, NAME, "", ":\n")
2828
2829 /* Globalizing directive for a label. */
2830 #define GLOBAL_ASM_OP "\t.globl\t"
2831
2832 /* This says how to define a global common symbol. */
2833
2834 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2835
2836 /* This says how to define a local common symbol (i.e., not visible to
2837 linker). */
2838
2839 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2840 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2841 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2842 #endif
2843
2844 /* This says how to output an external. It would be possible not to
2845 output anything and let undefined symbol become external. However
2846 the assembler uses length information on externals to allocate in
2847 data/sdata bss/sbss, thereby saving exec time. */
2848
2849 #undef ASM_OUTPUT_EXTERNAL
2850 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2851 mips_output_external(STREAM,DECL,NAME)
2852
2853 /* This is how to declare a function name. The actual work of
2854 emitting the label is moved to function_prologue, so that we can
2855 get the line number correctly emitted before the .ent directive,
2856 and after any .file directives. Define as empty so that the function
2857 is not declared before the .ent directive elsewhere. */
2858
2859 #undef ASM_DECLARE_FUNCTION_NAME
2860 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2861
2862 /* This is how to store into the string LABEL
2863 the symbol_ref name of an internal numbered label where
2864 PREFIX is the class of label and NUM is the number within the class.
2865 This is suitable for output with `assemble_name'. */
2866
2867 #undef ASM_GENERATE_INTERNAL_LABEL
2868 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2869 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2870
2871 /* Print debug labels as "foo = ." rather than "foo:" because they should
2872 represent a byte pointer rather than an ISA-encoded address. This is
2873 particularly important for code like:
2874
2875 $LFBxxx = .
2876 .cfi_startproc
2877 ...
2878 .section .gcc_except_table,...
2879 ...
2880 .uleb128 foo-$LFBxxx
2881
2882 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2883 likewise a byte pointer rather than an ISA-encoded address.
2884
2885 At the time of writing, this hook is not used for the function end
2886 label:
2887
2888 $LFExxx:
2889 .end foo
2890
2891 But this doesn't matter, because GAS doesn't treat a pre-.end label
2892 as a MIPS16 one anyway. */
2893
2894 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2895 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2896
2897 /* This is how to output an element of a case-vector that is absolute. */
2898
2899 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2900 fprintf (STREAM, "\t%s\t%sL%d\n", \
2901 ptr_mode == DImode ? ".dword" : ".word", \
2902 LOCAL_LABEL_PREFIX, \
2903 VALUE)
2904
2905 /* This is how to output an element of a case-vector. We can make the
2906 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2907 is supported. */
2908
2909 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2910 do { \
2911 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2912 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2913 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2914 else if (TARGET_GPWORD) \
2915 fprintf (STREAM, "\t%s\t%sL%d\n", \
2916 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2917 LOCAL_LABEL_PREFIX, VALUE); \
2918 else if (TARGET_RTP_PIC) \
2919 { \
2920 /* Make the entry relative to the start of the function. */ \
2921 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2922 fprintf (STREAM, "\t%s\t%sL%d-", \
2923 Pmode == DImode ? ".dword" : ".word", \
2924 LOCAL_LABEL_PREFIX, VALUE); \
2925 assemble_name (STREAM, XSTR (fnsym, 0)); \
2926 fprintf (STREAM, "\n"); \
2927 } \
2928 else \
2929 fprintf (STREAM, "\t%s\t%sL%d\n", \
2930 ptr_mode == DImode ? ".dword" : ".word", \
2931 LOCAL_LABEL_PREFIX, VALUE); \
2932 } while (0)
2933
2934 /* This is how to output an assembler line
2935 that says to advance the location counter
2936 to a multiple of 2**LOG bytes. */
2937
2938 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2939 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2940
2941 /* This is how to output an assembler line to advance the location
2942 counter by SIZE bytes. */
2943
2944 #undef ASM_OUTPUT_SKIP
2945 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2946 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2947
2948 /* This is how to output a string. */
2949 #undef ASM_OUTPUT_ASCII
2950 #define ASM_OUTPUT_ASCII mips_output_ascii
2951
2952 /* Output #ident as a in the read-only data section. */
2953 #undef ASM_OUTPUT_IDENT
2954 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2955 { \
2956 const char *p = STRING; \
2957 int size = strlen (p) + 1; \
2958 switch_to_section (readonly_data_section); \
2959 assemble_string (p, size); \
2960 }
2961 \f
2962 /* Default to -G 8 */
2963 #ifndef MIPS_DEFAULT_GVALUE
2964 #define MIPS_DEFAULT_GVALUE 8
2965 #endif
2966
2967 /* Define the strings to put out for each section in the object file. */
2968 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2969 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2970
2971 #undef READONLY_DATA_SECTION_ASM_OP
2972 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2973 \f
2974 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2975 do \
2976 { \
2977 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2978 TARGET_64BIT ? "daddiu" : "addiu", \
2979 reg_names[STACK_POINTER_REGNUM], \
2980 reg_names[STACK_POINTER_REGNUM], \
2981 TARGET_64BIT ? "sd" : "sw", \
2982 reg_names[REGNO], \
2983 reg_names[STACK_POINTER_REGNUM]); \
2984 } \
2985 while (0)
2986
2987 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2988 do \
2989 { \
2990 if (! set_noreorder) \
2991 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2992 \
2993 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2994 TARGET_64BIT ? "ld" : "lw", \
2995 reg_names[REGNO], \
2996 reg_names[STACK_POINTER_REGNUM], \
2997 TARGET_64BIT ? "daddu" : "addu", \
2998 reg_names[STACK_POINTER_REGNUM], \
2999 reg_names[STACK_POINTER_REGNUM]); \
3000 \
3001 if (! set_noreorder) \
3002 fprintf (STREAM, "\t.set\treorder\n"); \
3003 } \
3004 while (0)
3005
3006 /* How to start an assembler comment.
3007 The leading space is important (the mips native assembler requires it). */
3008 #ifndef ASM_COMMENT_START
3009 #define ASM_COMMENT_START " #"
3010 #endif
3011 \f
3012 /* Default definitions for size_t and ptrdiff_t. We must override the
3013 definitions from ../svr4.h on mips-*-linux-gnu. */
3014
3015 #undef SIZE_TYPE
3016 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3017
3018 #undef PTRDIFF_TYPE
3019 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3020
3021 /* The maximum number of bytes that can be copied by one iteration of
3022 a movmemsi loop; see mips_block_move_loop. */
3023 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3024 (UNITS_PER_WORD * 4)
3025
3026 /* The maximum number of bytes that can be copied by a straight-line
3027 implementation of movmemsi; see mips_block_move_straight. We want
3028 to make sure that any loop-based implementation will iterate at
3029 least twice. */
3030 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3031 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3032
3033 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3034 values were determined experimentally by benchmarking with CSiBE.
3035 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3036 for o32 where we have to restore $gp afterwards as well as make an
3037 indirect call), but in practice, bumping this up higher for
3038 TARGET_ABICALLS doesn't make much difference to code size. */
3039
3040 #define MIPS_CALL_RATIO 8
3041
3042 /* Any loop-based implementation of movmemsi will have at least
3043 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3044 moves, so allow individual copies of fewer elements.
3045
3046 When movmemsi is not available, use a value approximating
3047 the length of a memcpy call sequence, so that move_by_pieces
3048 will generate inline code if it is shorter than a function call.
3049 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3050 we'll have to generate a load/store pair for each, halve the
3051 value of MIPS_CALL_RATIO to take that into account. */
3052
3053 #define MOVE_RATIO(speed) \
3054 (HAVE_movmemsi \
3055 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3056 : MIPS_CALL_RATIO / 2)
3057
3058 /* movmemsi is meant to generate code that is at least as good as
3059 move_by_pieces. However, movmemsi effectively uses a by-pieces
3060 implementation both for moves smaller than a word and for word-aligned
3061 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
3062 allow the tree-level optimisers to do such moves by pieces, as it
3063 often exposes other optimization opportunities. We might as well
3064 continue to use movmemsi at the rtl level though, as it produces
3065 better code when scheduling is disabled (such as at -O). */
3066
3067 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
3068 (HAVE_movmemsi \
3069 ? (!currently_expanding_to_rtl \
3070 && ((ALIGN) < BITS_PER_WORD \
3071 ? (SIZE) < UNITS_PER_WORD \
3072 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
3073 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
3074 < (unsigned int) MOVE_RATIO (false)))
3075
3076 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3077 of the length of a memset call, but use the default otherwise. */
3078
3079 #define CLEAR_RATIO(speed)\
3080 ((speed) ? 15 : MIPS_CALL_RATIO)
3081
3082 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3083 optimizing for size adjust the ratio to account for the overhead of
3084 loading the constant and replicating it across the word. */
3085
3086 #define SET_RATIO(speed) \
3087 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3088
3089 /* STORE_BY_PIECES_P can be used when copying a constant string, but
3090 in that case each word takes 3 insns (lui, ori, sw), or more in
3091 64-bit mode, instead of 2 (lw, sw). For now we always fail this
3092 and let the move_by_pieces code copy the string from read-only
3093 memory. In the future, this could be tuned further for multi-issue
3094 CPUs that can issue stores down one pipe and arithmetic instructions
3095 down another; in that case, the lui/ori/sw combination would be a
3096 win for long enough strings. */
3097
3098 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
3099 \f
3100 #ifndef __mips16
3101 /* Since the bits of the _init and _fini function is spread across
3102 many object files, each potentially with its own GP, we must assume
3103 we need to load our GP. We don't preserve $gp or $ra, since each
3104 init/fini chunk is supposed to initialize $gp, and crti/crtn
3105 already take care of preserving $ra and, when appropriate, $gp. */
3106 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3107 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3108 asm (SECTION_OP "\n\
3109 .set noreorder\n\
3110 bal 1f\n\
3111 nop\n\
3112 1: .cpload $31\n\
3113 .set reorder\n\
3114 jal " USER_LABEL_PREFIX #FUNC "\n\
3115 " TEXT_SECTION_ASM_OP);
3116 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3117 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3118 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3119 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3120 asm (SECTION_OP "\n\
3121 .set noreorder\n\
3122 bal 1f\n\
3123 nop\n\
3124 1: .set reorder\n\
3125 .cpsetup $31, $2, 1b\n\
3126 jal " USER_LABEL_PREFIX #FUNC "\n\
3127 " TEXT_SECTION_ASM_OP);
3128 #endif
3129 #endif
3130
3131 #ifndef HAVE_AS_TLS
3132 #define HAVE_AS_TLS 0
3133 #endif
3134
3135 /* Return an asm string that atomically:
3136
3137 - Compares memory reference %1 to register %2 and, if they are
3138 equal, changes %1 to %3.
3139
3140 - Sets register %0 to the old value of memory reference %1.
3141
3142 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
3143 and OP is the instruction that should be used to load %3 into a
3144 register. */
3145 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
3146 "%(%<%[%|sync\n" \
3147 "1:\tll" SUFFIX "\t%0,%1\n" \
3148 "\tbne\t%0,%z2,2f\n" \
3149 "\t" OP "\t%@,%3\n" \
3150 "\tsc" SUFFIX "\t%@,%1\n" \
3151 "\tbeq%?\t%@,%.,1b\n" \
3152 "\tnop\n" \
3153 "\tsync%-%]%>%)\n" \
3154 "2:\n"
3155
3156 /* Return an asm string that atomically:
3157
3158 - Given that %2 contains a bit mask and %3 the inverted mask and
3159 that %4 and %5 have already been ANDed with %2.
3160
3161 - Compares the bits in memory reference %1 selected by mask %2 to
3162 register %4 and, if they are equal, changes the selected bits
3163 in memory to %5.
3164
3165 - Sets register %0 to the old value of memory reference %1.
3166
3167 OPS are the instructions needed to OR %5 with %@. */
3168 #define MIPS_COMPARE_AND_SWAP_12(OPS) \
3169 "%(%<%[%|sync\n" \
3170 "1:\tll\t%0,%1\n" \
3171 "\tand\t%@,%0,%2\n" \
3172 "\tbne\t%@,%z4,2f\n" \
3173 "\tand\t%@,%0,%3\n" \
3174 OPS \
3175 "\tsc\t%@,%1\n" \
3176 "\tbeq%?\t%@,%.,1b\n" \
3177 "\tnop\n" \
3178 "\tsync%-%]%>%)\n" \
3179 "2:\n"
3180
3181 #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
3182 #define MIPS_COMPARE_AND_SWAP_12_NONZERO_OP "\tor\t%@,%@,%5\n"
3183
3184
3185 /* Return an asm string that atomically:
3186
3187 - Sets memory reference %0 to %0 INSN %1.
3188
3189 SUFFIX is the suffix that should be added to "ll" and "sc"
3190 instructions. */
3191 #define MIPS_SYNC_OP(SUFFIX, INSN) \
3192 "%(%<%[%|sync\n" \
3193 "1:\tll" SUFFIX "\t%@,%0\n" \
3194 "\t" INSN "\t%@,%@,%1\n" \
3195 "\tsc" SUFFIX "\t%@,%0\n" \
3196 "\tbeq%?\t%@,%.,1b\n" \
3197 "\tnop\n" \
3198 "\tsync%-%]%>%)"
3199
3200 /* Return an asm string that atomically:
3201
3202 - Given that %1 contains a bit mask and %2 the inverted mask and
3203 that %3 has already been ANDed with %1.
3204
3205 - Sets the selected bits of memory reference %0 to %0 INSN %3.
3206
3207 - Uses scratch register %4.
3208
3209 AND_OP is an instruction done after INSN to mask INSN's result
3210 with the mask. For most operations, this is an AND with the
3211 inclusive mask (%1). For nand operations -- where the result of
3212 INSN is already correctly masked -- it instead performs a bitwise
3213 not. */
3214 #define MIPS_SYNC_OP_12(INSN, AND_OP) \
3215 "%(%<%[%|sync\n" \
3216 "1:\tll\t%4,%0\n" \
3217 "\tand\t%@,%4,%2\n" \
3218 "\t" INSN "\t%4,%4,%z3\n" \
3219 AND_OP \
3220 "\tor\t%@,%@,%4\n" \
3221 "\tsc\t%@,%0\n" \
3222 "\tbeq%?\t%@,%.,1b\n" \
3223 "\tnop\n" \
3224 "\tsync%-%]%>%)"
3225
3226 #define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n"
3227 #define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n"
3228
3229 /* Return an asm string that atomically:
3230
3231 - Given that %2 contains a bit mask and %3 the inverted mask and
3232 that %4 has already been ANDed with %2.
3233
3234 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3235
3236 - Sets %0 to the original value of %1.
3237
3238 - Uses scratch register %5.
3239
3240 AND_OP is an instruction done after INSN to mask INSN's result
3241 with the mask. For most operations, this is an AND with the
3242 inclusive mask (%1). For nand operations -- where the result of
3243 INSN is already correctly masked -- it instead performs a bitwise
3244 not. */
3245 #define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \
3246 "%(%<%[%|sync\n" \
3247 "1:\tll\t%0,%1\n" \
3248 "\tand\t%@,%0,%3\n" \
3249 "\t" INSN "\t%5,%0,%z4\n" \
3250 AND_OP \
3251 "\tor\t%@,%@,%5\n" \
3252 "\tsc\t%@,%1\n" \
3253 "\tbeq%?\t%@,%.,1b\n" \
3254 "\tnop\n" \
3255 "\tsync%-%]%>%)"
3256
3257 #define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n"
3258 #define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n"
3259
3260 /* Return an asm string that atomically:
3261
3262 - Given that %2 contains a bit mask and %3 the inverted mask and
3263 that %4 has already been ANDed with %2.
3264
3265 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3266
3267 - Sets %0 to the new value of %1.
3268
3269 AND_OP is an instruction done after INSN to mask INSN's result
3270 with the mask. For most operations, this is an AND with the
3271 inclusive mask (%1). For nand operations -- where the result of
3272 INSN is already correctly masked -- it instead performs a bitwise
3273 not. */
3274 #define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \
3275 "%(%<%[%|sync\n" \
3276 "1:\tll\t%0,%1\n" \
3277 "\tand\t%@,%0,%3\n" \
3278 "\t" INSN "\t%0,%0,%z4\n" \
3279 AND_OP \
3280 "\tor\t%@,%@,%0\n" \
3281 "\tsc\t%@,%1\n" \
3282 "\tbeq%?\t%@,%.,1b\n" \
3283 "\tnop\n" \
3284 "\tsync%-%]%>%)"
3285
3286 #define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n"
3287 #define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n"
3288
3289 /* Return an asm string that atomically:
3290
3291 - Sets memory reference %1 to %1 INSN %2.
3292
3293 - Sets register %0 to the old value of memory reference %1.
3294
3295 SUFFIX is the suffix that should be added to "ll" and "sc"
3296 instructions. */
3297 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
3298 "%(%<%[%|sync\n" \
3299 "1:\tll" SUFFIX "\t%0,%1\n" \
3300 "\t" INSN "\t%@,%0,%2\n" \
3301 "\tsc" SUFFIX "\t%@,%1\n" \
3302 "\tbeq%?\t%@,%.,1b\n" \
3303 "\tnop\n" \
3304 "\tsync%-%]%>%)"
3305
3306 /* Return an asm string that atomically:
3307
3308 - Sets memory reference %1 to %1 INSN %2.
3309
3310 - Sets register %0 to the new value of memory reference %1.
3311
3312 SUFFIX is the suffix that should be added to "ll" and "sc"
3313 instructions. */
3314 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3315 "%(%<%[%|sync\n" \
3316 "1:\tll" SUFFIX "\t%0,%1\n" \
3317 "\t" INSN "\t%@,%0,%2\n" \
3318 "\tsc" SUFFIX "\t%@,%1\n" \
3319 "\tbeq%?\t%@,%.,1b%~\n" \
3320 "\t" INSN "\t%0,%0,%2\n" \
3321 "\tsync%-%]%>%)"
3322
3323 /* Return an asm string that atomically:
3324
3325 - Sets memory reference %0 to ~(%0 AND %1).
3326
3327 SUFFIX is the suffix that should be added to "ll" and "sc"
3328 instructions. INSN is the and instruction needed to and a register
3329 with %2. */
3330 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3331 "%(%<%[%|sync\n" \
3332 "1:\tll" SUFFIX "\t%@,%0\n" \
3333 "\t" INSN "\t%@,%@,%1\n" \
3334 "\tnor\t%@,%@,%.\n" \
3335 "\tsc" SUFFIX "\t%@,%0\n" \
3336 "\tbeq%?\t%@,%.,1b\n" \
3337 "\tnop\n" \
3338 "\tsync%-%]%>%)"
3339
3340 /* Return an asm string that atomically:
3341
3342 - Sets memory reference %1 to ~(%1 AND %2).
3343
3344 - Sets register %0 to the old value of memory reference %1.
3345
3346 SUFFIX is the suffix that should be added to "ll" and "sc"
3347 instructions. INSN is the and instruction needed to and a register
3348 with %2. */
3349 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3350 "%(%<%[%|sync\n" \
3351 "1:\tll" SUFFIX "\t%0,%1\n" \
3352 "\t" INSN "\t%@,%0,%2\n" \
3353 "\tnor\t%@,%@,%.\n" \
3354 "\tsc" SUFFIX "\t%@,%1\n" \
3355 "\tbeq%?\t%@,%.,1b\n" \
3356 "\tnop\n" \
3357 "\tsync%-%]%>%)"
3358
3359 /* Return an asm string that atomically:
3360
3361 - Sets memory reference %1 to ~(%1 AND %2).
3362
3363 - Sets register %0 to the new value of memory reference %1.
3364
3365 SUFFIX is the suffix that should be added to "ll" and "sc"
3366 instructions. INSN is the and instruction needed to and a register
3367 with %2. */
3368 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3369 "%(%<%[%|sync\n" \
3370 "1:\tll" SUFFIX "\t%0,%1\n" \
3371 "\t" INSN "\t%0,%0,%2\n" \
3372 "\tnor\t%@,%0,%.\n" \
3373 "\tsc" SUFFIX "\t%@,%1\n" \
3374 "\tbeq%?\t%@,%.,1b%~\n" \
3375 "\tnor\t%0,%0,%.\n" \
3376 "\tsync%-%]%>%)"
3377
3378 /* Return an asm string that atomically:
3379
3380 - Sets memory reference %1 to %2.
3381
3382 - Sets register %0 to the old value of memory reference %1.
3383
3384 SUFFIX is the suffix that should be added to "ll" and "sc"
3385 instructions. OP is the and instruction that should be used to
3386 load %2 into a register. */
3387 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3388 "%(%<%[%|\n" \
3389 "1:\tll" SUFFIX "\t%0,%1\n" \
3390 "\t" OP "\t%@,%2\n" \
3391 "\tsc" SUFFIX "\t%@,%1\n" \
3392 "\tbeq%?\t%@,%.,1b\n" \
3393 "\tnop\n" \
3394 "\tsync%-%]%>%)"
3395
3396 /* Return an asm string that atomically:
3397
3398 - Given that %2 contains an inclusive mask, %3 and exclusive mask
3399 and %4 has already been ANDed with the inclusive mask.
3400
3401 - Sets bits selected by the inclusive mask of memory reference %1
3402 to %4.
3403
3404 - Sets register %0 to the old value of memory reference %1.
3405
3406 OPS are the instructions needed to OR %4 with %@.
3407
3408 Operand %2 is unused, but needed as to give the test_and_set_12
3409 insn the five operands expected by the expander. */
3410 #define MIPS_SYNC_EXCHANGE_12(OPS) \
3411 "%(%<%[%|\n" \
3412 "1:\tll\t%0,%1\n" \
3413 "\tand\t%@,%0,%3\n" \
3414 OPS \
3415 "\tsc\t%@,%1\n" \
3416 "\tbeq%?\t%@,%.,1b\n" \
3417 "\tnop\n" \
3418 "\tsync%-%]%>%)"
3419
3420 #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
3421 #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
3422
3423 #ifndef USED_FOR_TARGET
3424 extern const enum reg_class mips_regno_to_class[];
3425 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3426 extern bool mips_print_operand_punct[256];
3427 extern const char *current_function_file; /* filename current function is in */
3428 extern int num_source_filenames; /* current .file # */
3429 extern int set_noreorder; /* # of nested .set noreorder's */
3430 extern int set_nomacro; /* # of nested .set nomacro's */
3431 extern int mips_dbx_regno[];
3432 extern int mips_dwarf_regno[];
3433 extern bool mips_split_p[];
3434 extern bool mips_split_hi_p[];
3435 extern GTY(()) rtx cmp_operands[2];
3436 extern enum processor_type mips_arch; /* which cpu to codegen for */
3437 extern enum processor_type mips_tune; /* which cpu to schedule for */
3438 extern int mips_isa; /* architectural level */
3439 extern int mips_abi; /* which ABI to use */
3440 extern const struct mips_cpu_info *mips_arch_info;
3441 extern const struct mips_cpu_info *mips_tune_info;
3442 extern const struct mips_rtx_cost_data *mips_cost;
3443 extern bool mips_base_mips16;
3444 extern enum mips_code_readable_setting mips_code_readable;
3445 #endif
3446
3447 /* Enable querying of DFA units. */
3448 #define CPU_UNITS_QUERY 1
3449
3450 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3451 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3452
3453 /* This is necessary to avoid a warning about comparing different enum
3454 types. */
3455 #define mips_tune_attr ((enum attr_cpu) mips_tune)
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