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1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2019 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
29 #ifndef RS6000_OPTS_H
31 #endif
33 /* 128-bit floating point precision values. */
34 #ifndef RS6000_MODES_H
36 #endif
38 /* Definitions for the object file format. These are set at
39 compile-time. */
41 #define OBJECT_XCOFF 1
42 #define OBJECT_ELF 2
43 #define OBJECT_MACHO 4
45 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
46 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
47 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
49 #ifndef TARGET_AIX
50 #define TARGET_AIX 0
51 #endif
53 #ifndef TARGET_AIX_OS
54 #define TARGET_AIX_OS 0
55 #endif
57 /* Control whether function entry points use a "dot" symbol when
58 ABI_AIX. */
59 #define DOT_SYMBOLS 1
61 /* Default string to use for cpu if not specified. */
62 #ifndef TARGET_CPU_DEFAULT
63 #define TARGET_CPU_DEFAULT ((char *)0)
64 #endif
66 /* If configured for PPC405, support PPC405CR Erratum77. */
67 #ifdef CONFIG_PPC405CR
68 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
69 #else
70 #define PPC405_ERRATUM77 0
71 #endif
73 #if CHECKING_P
75 #else
77 #endif
79 /* Common ASM definitions used by ASM_SPEC among the various targets for
80 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to
81 provide the default assembler options if the user uses -mcpu=native, so if
82 you make changes here, make them also there. PR63177: Do not pass -mpower8
83 to the assembler if -mpower9-vector was also used. */
84 #define ASM_CPU_SPEC \
85 "%{mcpu=native: %(asm_cpu_native); \
86 mcpu=power9: -mpower9; \
87 mcpu=power8|mcpu=powerpc64le: %{mpower9-vector: -mpower9;: -mpower8}; \
88 mcpu=power7: -mpower7; \
89 mcpu=power6x: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \
90 mcpu=power6: -mpower6 %{!mvsx:%{!maltivec:-maltivec}}; \
91 mcpu=power5+: -mpower5; \
92 mcpu=power5: -mpower5; \
93 mcpu=power4: -mpower4; \
94 mcpu=power3: -mppc64; \
95 mcpu=powerpc: -mppc; \
96 mcpu=powerpc64: -mppc64; \
97 mcpu=a2: -ma2; \
98 mcpu=cell: -mcell; \
99 mcpu=rs64: -mppc64; \
100 mcpu=401: -mppc; \
101 mcpu=403: -m403; \
102 mcpu=405: -m405; \
103 mcpu=405fp: -m405; \
104 mcpu=440: -m440; \
105 mcpu=440fp: -m440; \
106 mcpu=464: -m440; \
107 mcpu=464fp: -m440; \
108 mcpu=476: -m476; \
109 mcpu=476fp: -m476; \
110 mcpu=505: -mppc; \
111 mcpu=601: -m601; \
112 mcpu=602: -mppc; \
113 mcpu=603: -mppc; \
114 mcpu=603e: -mppc; \
115 mcpu=ec603e: -mppc; \
116 mcpu=604: -mppc; \
117 mcpu=604e: -mppc; \
118 mcpu=620: -mppc64; \
119 mcpu=630: -mppc64; \
120 mcpu=740: -mppc; \
121 mcpu=750: -mppc; \
122 mcpu=G3: -mppc; \
123 mcpu=7400: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
124 mcpu=7450: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
125 mcpu=G4: -mppc %{!mvsx:%{!maltivec:-maltivec}}; \
126 mcpu=801: -mppc; \
127 mcpu=821: -mppc; \
128 mcpu=823: -mppc; \
129 mcpu=860: -mppc; \
130 mcpu=970: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \
131 mcpu=G5: -mpower4 %{!mvsx:%{!maltivec:-maltivec}}; \
132 mcpu=8540: -me500; \
133 mcpu=8548: -me500; \
134 mcpu=e300c2: -me300; \
135 mcpu=e300c3: -me300; \
136 mcpu=e500mc: -me500mc; \
137 mcpu=e500mc64: -me500mc64; \
138 mcpu=e5500: -me5500; \
139 mcpu=e6500: -me6500; \
140 mcpu=titan: -mtitan; \
141 mcpu=future: -mfuture; \
142 !mcpu*: %{mpower9-vector: -mpower9; \
143 mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \
144 mvsx: -mpower7; \
145 mpowerpc64: -mppc64;: %(asm_default)}; \
148 ASM_OPT_ANY
154 /* This macro defines names of additional specifications to put in the specs
155 that can be used in various specifications like CC1_SPEC. Its definition
156 is an initializer with a subgrouping for each command option.
158 Each subgrouping contains a string constant, that defines the
159 specification name, and a string constant that used by the GCC driver
160 program.
162 Do not define this macro if it does not need to do anything. */
164 #define SUBTARGET_EXTRA_SPECS
166 #define EXTRA_SPECS \
172 SUBTARGET_EXTRA_SPECS
174 /* -mcpu=native handling only makes sense with compiler running on
175 an PowerPC chip. If changing this condition, also change
176 the condition in driver-rs6000.c. */
177 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
178 /* In driver-rs6000.c. */
180 #define EXTRA_SPEC_FUNCTIONS \
182 #define HAVE_LOCAL_CPU_DETECT
185 #else
187 #endif
189 #ifndef CC1_CPU_SPEC
190 #ifdef HAVE_LOCAL_CPU_DETECT
191 #define CC1_CPU_SPEC \
192 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
193 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
194 #else
196 #endif
197 #endif
199 /* Architecture type. */
201 /* Define TARGET_MFCRF if the target assembler does not support the
202 optional field operand for mfcr. */
204 #ifndef HAVE_AS_MFCRF
205 #undef TARGET_MFCRF
206 #define TARGET_MFCRF 0
207 #endif
209 /* Define TARGET_TLS_MARKERS if the target assembler does not support
210 arg markers for __tls_get_addr calls. */
211 #ifndef HAVE_AS_TLS_MARKERS
212 #undef TARGET_TLS_MARKERS
213 #define TARGET_TLS_MARKERS 0
214 #else
215 #define TARGET_TLS_MARKERS tls_markers
216 #endif
218 #ifndef TARGET_SECURE_PLT
219 #define TARGET_SECURE_PLT 0
220 #endif
222 #ifndef TARGET_CMODEL
223 #define TARGET_CMODEL CMODEL_SMALL
224 #endif
226 #define TARGET_32BIT (! TARGET_64BIT)
228 #ifndef HAVE_AS_TLS
229 #define HAVE_AS_TLS 0
230 #endif
232 #ifndef HAVE_AS_PLTSEQ
233 #define HAVE_AS_PLTSEQ 0
234 #endif
236 #ifndef TARGET_PLTSEQ
237 #define TARGET_PLTSEQ 0
238 #endif
240 #ifndef TARGET_LINK_STACK
241 #define TARGET_LINK_STACK 0
242 #endif
244 #ifndef SET_TARGET_LINK_STACK
245 #define SET_TARGET_LINK_STACK(X) do { } while (0)
246 #endif
248 #ifndef TARGET_FLOAT128_ENABLE_TYPE
249 #define TARGET_FLOAT128_ENABLE_TYPE 0
250 #endif
252 /* Return 1 for a symbol ref for a thread-local storage symbol. */
253 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
254 (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0)
256 #ifdef IN_LIBGCC2
257 /* For libgcc2 we make sure this is a compile time constant */
258 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
259 #undef TARGET_POWERPC64
260 #define TARGET_POWERPC64 1
261 #else
262 #undef TARGET_POWERPC64
263 #define TARGET_POWERPC64 0
264 #endif
265 #else
266 /* The option machinery will define this. */
267 #endif
269 #define TARGET_DEFAULT (MASK_MULTIPLE)
271 /* Define generic processor types based upon current deployment. */
272 #define PROCESSOR_COMMON PROCESSOR_PPC601
273 #define PROCESSOR_POWERPC PROCESSOR_PPC604
274 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
276 /* Define the default processor. This is overridden by other tm.h files. */
277 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
278 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
280 /* Specify the dialect of assembler to use. Only new mnemonics are supported
281 starting with GCC 4.8, i.e. just one dialect, but for backwards
282 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
283 defined. */
284 #define ASSEMBLER_DIALECT 1
286 /* Debug support */
294 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
295 | MASK_DEBUG_ARG \
296 | MASK_DEBUG_REG \
297 | MASK_DEBUG_ADDR \
298 | MASK_DEBUG_COST \
299 | MASK_DEBUG_TARGET \
300 | MASK_DEBUG_BUILTIN)
302 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
303 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
304 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
305 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
306 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
307 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
308 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
310 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
311 long double format that uses a pair of doubles, or IEEE 128-bit floating
312 point. KFmode was added as a way to represent IEEE 128-bit floating point,
313 even if the default for long double is the IBM long double format.
314 Similarly IFmode is the IBM long double format even if the default is IEEE
315 128-bit. Don't allow IFmode if -msoft-float. */
316 #define FLOAT128_IEEE_P(MODE) \
317 ((TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
318 && ((MODE) == TFmode || (MODE) == TCmode)) \
319 || ((MODE) == KFmode) || ((MODE) == KCmode))
321 #define FLOAT128_IBM_P(MODE) \
322 ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \
323 && ((MODE) == TFmode || (MODE) == TCmode)) \
324 || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode)))
326 /* Helper macros to say whether a 128-bit floating point type can go in a
327 single vector register, or whether it needs paired scalar values. */
328 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
330 #define FLOAT128_2REG_P(MODE) \
331 (FLOAT128_IBM_P (MODE) \
332 || ((MODE) == TDmode) \
333 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
335 /* Return true for floating point that does not use a vector register. */
336 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
337 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
339 /* Describe the vector unit used for arithmetic operations. */
342 #define VECTOR_UNIT_NONE_P(MODE) \
343 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
345 #define VECTOR_UNIT_VSX_P(MODE) \
346 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
348 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
349 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
351 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
352 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
354 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
355 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
356 (int)VECTOR_VSX, \
357 (int)VECTOR_P8_VECTOR))
359 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
360 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
361 compatible, so allow it as well, rather than changing all of the uses of the
362 macro. */
363 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
364 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
365 (int)VECTOR_ALTIVEC, \
366 (int)VECTOR_P8_VECTOR))
368 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
369 same unit as the vector unit we are using, but we may want to migrate to
370 using VSX style loads even for types handled by altivec. */
373 #define VECTOR_MEM_NONE_P(MODE) \
374 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
376 #define VECTOR_MEM_VSX_P(MODE) \
377 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
379 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
380 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
382 #define VECTOR_MEM_ALTIVEC_P(MODE) \
383 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
385 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
386 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
387 (int)VECTOR_VSX, \
388 (int)VECTOR_P8_VECTOR))
390 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
391 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
392 (int)VECTOR_ALTIVEC, \
393 (int)VECTOR_P8_VECTOR))
395 /* Return the alignment of a given vector type, which is set based on the
396 vector unit use. VSX for instance can load 32 or 64 bit aligned words
397 without problems, while Altivec requires 128-bit aligned vectors. */
400 #define VECTOR_ALIGN(MODE) \
401 ((rs6000_vector_align[(MODE)] != 0) \
402 ? rs6000_vector_align[(MODE)] \
403 : (int)GET_MODE_BITSIZE ((MODE)))
405 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
406 with scalar instructions. */
407 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
409 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
410 with the ISA 3.0 MFVSRLD instructions. */
411 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
413 /* Alignment options for fields in structures for sub-targets following
414 AIX-like ABI.
415 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
416 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
418 Override the macro definitions when compiling libobjc to avoid undefined
419 reference to rs6000_alignment_flags due to library's use of GCC alignment
420 macros which use the macros below. */
422 #ifndef IN_TARGET_LIBS
423 #define MASK_ALIGN_POWER 0x00000000
424 #define MASK_ALIGN_NATURAL 0x00000001
425 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
426 #else
427 #define TARGET_ALIGN_NATURAL 0
428 #endif
430 /* We use values 126..128 to pick the appropriate long double type (IFmode,
431 KFmode, TFmode). */
432 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size > 64)
433 #define TARGET_IEEEQUAD rs6000_ieeequad
434 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
435 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
437 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
438 Enable 32-bit fcfid's on any of the switches for newer ISA machines. */
439 #define TARGET_FCFID (TARGET_POWERPC64 \
445 #define TARGET_FCTIDZ TARGET_FCFID
446 #define TARGET_STFIWX TARGET_PPC_GFXOPT
447 #define TARGET_LFIWAX TARGET_CMPB
448 #define TARGET_LFIWZX TARGET_POPCNTD
449 #define TARGET_FCFIDS TARGET_POPCNTD
450 #define TARGET_FCFIDU TARGET_POPCNTD
451 #define TARGET_FCFIDUS TARGET_POPCNTD
452 #define TARGET_FCTIDUZ TARGET_POPCNTD
453 #define TARGET_FCTIWUZ TARGET_POPCNTD
454 #define TARGET_CTZ TARGET_MODULO
455 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
456 #define TARGET_MADDLD TARGET_MODULO
458 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
459 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
460 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
461 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
462 && TARGET_POWERPC64)
463 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
464 && TARGET_POWERPC64)
466 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
467 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
468 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
470 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
471 loads are slow. */
472 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
474 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
475 in power7, so conditionalize them on p8 features. TImode syncs need quad
476 memory support. */
477 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
478 || TARGET_QUAD_MEMORY_ATOMIC \
479 || TARGET_DIRECT_MOVE)
481 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
483 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
484 to allocate the SDmode stack slot to get the value into the proper location
485 in the register. */
486 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
488 /* ISA 3.0 has new min/max functions that don't need fast math that are being
489 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
490 answers if the arguments are not in the normal range. */
491 #define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
492 && (TARGET_P9_MINMAX || !flag_trapping_math))
494 /* In switching from using target_flags to using rs6000_isa_flags, the options
495 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
496 OPTION_MASK_<xxx> back into MASK_<xxx>. */
497 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
498 #define MASK_CMPB OPTION_MASK_CMPB
499 #define MASK_CRYPTO OPTION_MASK_CRYPTO
500 #define MASK_DFP OPTION_MASK_DFP
501 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
502 #define MASK_DLMZB OPTION_MASK_DLMZB
503 #define MASK_EABI OPTION_MASK_EABI
504 #define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
505 #define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
506 #define MASK_FPRND OPTION_MASK_FPRND
507 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
508 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
509 #define MASK_HTM OPTION_MASK_HTM
510 #define MASK_ISEL OPTION_MASK_ISEL
511 #define MASK_MFCRF OPTION_MASK_MFCRF
512 #define MASK_MULHW OPTION_MASK_MULHW
513 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
514 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
515 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
516 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
517 #define MASK_P9_MISC OPTION_MASK_P9_MISC
518 #define MASK_POPCNTB OPTION_MASK_POPCNTB
519 #define MASK_POPCNTD OPTION_MASK_POPCNTD
520 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
521 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
522 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
523 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
524 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
525 #define MASK_UPDATE OPTION_MASK_UPDATE
526 #define MASK_VSX OPTION_MASK_VSX
527 #define MASK_FUTURE OPTION_MASK_FUTURE
529 #ifndef IN_LIBGCC2
530 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
531 #endif
533 #ifdef TARGET_64BIT
534 #define MASK_64BIT OPTION_MASK_64BIT
535 #endif
537 #ifdef TARGET_LITTLE_ENDIAN
538 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
539 #endif
541 #ifdef TARGET_REGNAMES
542 #define MASK_REGNAMES OPTION_MASK_REGNAMES
543 #endif
545 #ifdef TARGET_PROTOTYPE
546 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
547 #endif
549 #ifdef TARGET_MODULO
550 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
551 #endif
554 /* For power systems, we want to enable Altivec and VSX builtins even if the
555 user did not use -maltivec or -mvsx to allow the builtins to be used inside
556 of #pragma GCC target or the target attribute to change the code level for a
557 given system. */
559 #define TARGET_EXTRA_BUILTINS (TARGET_POWERPC64 \
564 || TARGET_ALTIVEC \
565 || TARGET_VSX \
566 || TARGET_HARD_FLOAT)
568 /* E500 cores only support plain "sync", not lwsync. */
569 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
570 || rs6000_cpu == PROCESSOR_PPC8548)
573 /* Which machine supports the various reciprocal estimate instructions. */
574 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT)
576 #define TARGET_FRE (TARGET_HARD_FLOAT \
577 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
579 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
580 && TARGET_PPC_GFXOPT)
582 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT \
583 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
585 /* Macro to say whether we can do optimizations where we need to do parts of
586 the calculation in 64-bit GPRs and then is transfered to the vector
587 registers. */
588 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
589 && TARGET_P8_VECTOR \
590 && TARGET_POWERPC64)
592 /* Whether the various reciprocal divide/square root estimate instructions
593 exist, and whether we should automatically generate code for the instruction
594 by default. */
602 #define RS6000_RECIP_HAVE_RE_P(MODE) \
603 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
605 #define RS6000_RECIP_AUTO_RE_P(MODE) \
606 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
608 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
609 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
611 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
612 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
614 /* The default CPU for TARGET_OPTION_OVERRIDE. */
615 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
617 /* Target pragma. */
618 #define REGISTER_TARGET_PRAGMAS() do { \
620 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
621 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
622 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
623 } while (0)
625 /* Target #defines. */
626 #define TARGET_CPU_CPP_BUILTINS() \
627 rs6000_cpu_cpp_builtins (pfile)
629 /* Target CPU versions for D. */
630 #define TARGET_D_CPU_VERSIONS rs6000_d_target_versions
632 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
633 we're compiling for. Some configurations may need to override it. */
634 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
635 do \
636 { \
637 if (BYTES_BIG_ENDIAN) \
638 { \
642 } \
643 else \
644 { \
648 } \
649 } \
650 while (0)
651 \f
652 /* Target machine storage layout. */
654 /* Define this macro if it is advisable to hold scalars in registers
655 in a wider mode than that declared by the program. In such cases,
656 the value is constrained to be within the bounds of the declared
657 type, but kept valid in the wider mode. The signedness of the
658 extension may differ from that of the type. */
660 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
661 if (GET_MODE_CLASS (MODE) == MODE_INT \
662 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
663 (MODE) = TARGET_32BIT ? SImode : DImode;
665 /* Define this if most significant bit is lowest numbered
666 in instructions that operate on numbered bit-fields. */
667 /* That is true on RS/6000. */
668 #define BITS_BIG_ENDIAN 1
670 /* Define this if most significant byte of a word is the lowest numbered. */
671 /* That is true on RS/6000. */
672 #define BYTES_BIG_ENDIAN 1
674 /* Define this if most significant word of a multiword number is lowest
675 numbered.
677 For RS/6000 we can decide arbitrarily since there are no machine
678 instructions for them. Might as well be consistent with bits and bytes. */
679 #define WORDS_BIG_ENDIAN 1
681 /* This says that for the IBM long double the larger magnitude double
682 comes first. It's really a two element double array, and arrays
683 don't index differently between little- and big-endian. */
684 #define LONG_DOUBLE_LARGE_FIRST 1
686 #define MAX_BITS_PER_WORD 64
688 /* Width of a word, in units (bytes). */
689 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
690 #ifdef IN_LIBGCC2
691 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
692 #else
693 #define MIN_UNITS_PER_WORD 4
694 #endif
695 #define UNITS_PER_FP_WORD 8
696 #define UNITS_PER_ALTIVEC_WORD 16
697 #define UNITS_PER_VSX_WORD 16
699 /* Type used for ptrdiff_t, as a string used in a declaration. */
702 /* Type used for size_t, as a string used in a declaration. */
705 /* Type used for wchar_t, as a string used in a declaration. */
708 /* Width of wchar_t in bits. */
709 #define WCHAR_TYPE_SIZE 16
711 /* A C expression for the size in bits of the type `short' on the
712 target machine. If you don't define this, the default is half a
713 word. (If this would be less than one storage unit, it is
714 rounded up to one unit.) */
715 #define SHORT_TYPE_SIZE 16
717 /* A C expression for the size in bits of the type `int' on the
718 target machine. If you don't define this, the default is one
719 word. */
720 #define INT_TYPE_SIZE 32
722 /* A C expression for the size in bits of the type `long' on the
723 target machine. If you don't define this, the default is one
724 word. */
725 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
727 /* A C expression for the size in bits of the type `long long' on the
728 target machine. If you don't define this, the default is two
729 words. */
730 #define LONG_LONG_TYPE_SIZE 64
732 /* A C expression for the size in bits of the type `float' on the
733 target machine. If you don't define this, the default is one
734 word. */
735 #define FLOAT_TYPE_SIZE 32
737 /* A C expression for the size in bits of the type `double' on the
738 target machine. If you don't define this, the default is two
739 words. */
740 #define DOUBLE_TYPE_SIZE 64
742 /* A C expression for the size in bits of the type `long double' on the target
743 machine. If you don't define this, the default is two words. */
744 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
746 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
747 #define WIDEST_HARDWARE_FP_SIZE 64
749 /* Width in bits of a pointer.
750 See also the macro `Pmode' defined below. */
752 #define POINTER_SIZE rs6000_pointer_size
754 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
755 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
757 /* Boundary (in *bits*) on which stack pointer should be aligned. */
758 #define STACK_BOUNDARY \
759 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
760 ? 64 : 128)
762 /* Allocation boundary (in *bits*) for the code of a function. */
763 #define FUNCTION_BOUNDARY 32
765 /* No data type wants to be aligned rounder than this. */
766 #define BIGGEST_ALIGNMENT 128
768 /* Alignment of field after `int : 0' in a structure. */
769 #define EMPTY_FIELD_BOUNDARY 32
771 /* Every structure's size must be a multiple of this. */
772 #define STRUCTURE_SIZE_BOUNDARY 8
774 /* A bit-field declared as `int' forces `int' alignment for the struct. */
775 #define PCC_BITFIELD_TYPE_MATTERS 1
779 /* A C expression to compute the alignment for a variables in the
780 local store. TYPE is the data type, and ALIGN is the alignment
781 that the object would ordinarily have. */
782 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
783 rs6000_data_alignment (TYPE, ALIGN, align_both)
785 /* Make arrays of chars word-aligned for the same reasons. */
786 #define DATA_ALIGNMENT(TYPE, ALIGN) \
787 rs6000_data_alignment (TYPE, ALIGN, align_opt)
789 /* Align vectors to 128 bits. */
790 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
791 rs6000_data_alignment (TYPE, ALIGN, align_abi)
793 /* Nonzero if move instructions will actually fail to work
794 when given unaligned data. */
795 #define STRICT_ALIGNMENT 0
796 \f
797 /* Standard register usage. */
799 /* Number of actual hardware registers.
800 The hardware registers are assigned numbers for the compiler
801 from 0 to just below FIRST_PSEUDO_REGISTER.
802 All registers that the compiler knows about must be given numbers,
803 even those that are not normally considered general registers.
805 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
806 a count register, a link register, and 8 condition register fields,
807 which we view here as separate registers. AltiVec adds 32 vector
808 registers and a VRsave register.
810 In addition, the difference between the frame and argument pointers is
811 a function of the number of registers saved, so we need to have a
812 register for AP that will later be eliminated in favor of SP or FP.
813 This is a normal register, but it is fixed.
815 We also create a pseudo register for float/int conversions, that will
816 really represent the memory location used. It is represented here as
817 a register, in order to work around problems in allocating stack storage
818 in inline functions.
820 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
821 pointer, which is eventually eliminated in favor of SP or FP. */
823 #define FIRST_PSEUDO_REGISTER 111
825 /* Use standard DWARF numbering for DWARF debugging information. */
826 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
828 /* Use gcc hard register numbering for eh_frame. */
829 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
831 /* Map register numbers held in the call frame info that gcc has
832 collected using DWARF_FRAME_REGNUM to those that should be output in
833 .debug_frame and .eh_frame. */
834 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
835 rs6000_dbx_register_number ((REGNO), (FOR_EH) ? 2 : 1)
837 /* 1 for registers that have pervasive standard uses
838 and are not available for the register allocator.
840 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
841 as a local register; for all other OS's r2 is the TOC pointer.
843 On System V implementations, r13 is fixed and not available for use. */
845 #define FIXED_REGISTERS \
847 0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
848 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
850 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
851 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
853 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
854 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
856 0, 0, 1, 1, \
858 0, 0, 0, 0, 0, 0, 0, 0, \
860 1, 1, 1 \
861 }
863 /* 1 for registers not available across function calls.
864 These must include the FIXED_REGISTERS and also any
865 registers that can be used without being saved.
866 The latter must include the registers where values are returned
867 and the register where structure-value addresses are passed.
868 Aside from that, you can include as many other registers as you like. */
870 #define CALL_USED_REGISTERS \
872 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
873 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
875 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
876 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
878 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
881 1, 1, 1, 1, \
883 1, 1, 0, 0, 0, 1, 1, 1, \
885 1, 1, 1 \
886 }
888 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
889 the entire set of `FIXED_REGISTERS' be included.
890 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
891 This macro is optional. If not specified, it defaults to the value
892 of `CALL_USED_REGISTERS'. */
894 #define CALL_REALLY_USED_REGISTERS \
896 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
897 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
899 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
900 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
902 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
903 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
905 1, 1, 1, 1, \
907 1, 1, 0, 0, 0, 1, 1, 1, \
909 0, 0, 0 \
910 }
912 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
914 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
915 #define FIRST_SAVED_FP_REGNO (14+32)
916 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
918 /* List the order in which to allocate registers. Each register must be
919 listed once, even those in FIXED_REGISTERS.
921 We allocate in the following order:
922 fp0 (not saved or used for anything)
923 fp13 - fp2 (not saved; incoming fp arg registers)
924 fp1 (not saved; return value)
925 fp31 - fp14 (saved; order given to save least number)
926 cr7, cr5 (not saved or special)
927 cr6 (not saved, but used for vector operations)
928 cr1 (not saved, but used for FP operations)
929 cr0 (not saved, but used for arithmetic operations)
930 cr4, cr3, cr2 (saved)
931 r9 (not saved; best for TImode)
932 r10, r8-r4 (not saved; highest first for less conflict with params)
933 r3 (not saved; return value register)
934 r11 (not saved; later alloc to help shrink-wrap)
935 r0 (not saved; cannot be base reg)
936 r31 - r13 (saved; order given to save least number)
937 r12 (not saved; if used for DImode or DFmode would use r13)
938 ctr (not saved; when we have the choice ctr is better)
939 lr (saved)
940 r1, r2, ap, ca (fixed)
941 v0 - v1 (not saved or used for anything)
942 v13 - v3 (not saved; incoming vector arg registers)
943 v2 (not saved; incoming vector arg reg; return value)
944 v19 - v14 (not saved or used for anything)
945 v31 - v20 (saved; order given to save least number)
946 vrsave, vscr (fixed)
947 sfp (fixed)
948 */
950 #if FIXED_R2 == 1
951 #define MAYBE_R2_AVAILABLE
952 #define MAYBE_R2_FIXED 2,
953 #else
954 #define MAYBE_R2_AVAILABLE 2,
955 #define MAYBE_R2_FIXED
956 #endif
958 #if FIXED_R13 == 1
959 #define EARLY_R12 12,
960 #define LATE_R12
961 #else
962 #define EARLY_R12
963 #define LATE_R12 12,
964 #endif
966 #define REG_ALLOC_ORDER \
967 {32, \
970 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
971 33, \
972 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
973 50, 49, 48, 47, 46, \
974 100, 107, 105, 106, 101, 104, 103, 102, \
975 MAYBE_R2_AVAILABLE \
976 9, 10, 8, 7, 6, 5, 4, \
977 3, EARLY_R12 11, 0, \
978 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
979 18, 17, 16, 15, 14, 13, LATE_R12 \
980 97, 96, \
981 1, MAYBE_R2_FIXED 99, 98, \
983 64, 65, \
984 77, 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, \
985 66, \
986 83, 82, 81, 80, 79, 78, \
987 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \
988 108, 109, \
989 110 \
990 }
992 /* True if register is floating-point. */
993 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
995 /* True if register is a condition register. */
996 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
998 /* True if register is a condition register, but not cr0. */
999 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1001 /* True if register is an integer register. */
1002 #define INT_REGNO_P(N) \
1003 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1005 /* True if register is the CA register. */
1006 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1008 /* True if register is an AltiVec register. */
1009 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1011 /* True if register is a VSX register. */
1012 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1014 /* Alternate name for any vector register supporting floating point, no matter
1015 which instruction set(s) are available. */
1016 #define VFLOAT_REGNO_P(N) \
1017 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1019 /* Alternate name for any vector register supporting integer, no matter which
1020 instruction set(s) are available. */
1021 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1023 /* Alternate name for any vector register supporting logical operations, no
1024 matter which instruction set(s) are available. Allow GPRs as well as the
1025 vector registers. */
1026 #define VLOGICAL_REGNO_P(N) \
1027 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1028 || (TARGET_VSX && FP_REGNO_P (N))) \
1030 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1031 enough space to account for vectors in FP regs. However, TFmode/TDmode
1032 should not use VSX instructions to do a caller save. */
1033 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1034 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1035 ? (MODE) \
1036 : TARGET_VSX \
1037 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1038 && FP_REGNO_P (REGNO) \
1039 ? V2DFmode \
1040 : FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1041 ? DFmode \
1042 : (MODE) == TDmode && FP_REGNO_P (REGNO) \
1043 ? DImode \
1044 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1046 #define VSX_VECTOR_MODE(MODE) \
1047 ((MODE) == V4SFmode \
1048 || (MODE) == V2DFmode) \
1050 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1051 really a vector, but we want to treat it as a vector for moves, and
1052 such. */
1054 #define ALTIVEC_VECTOR_MODE(MODE) \
1055 ((MODE) == V16QImode \
1056 || (MODE) == V8HImode \
1057 || (MODE) == V4SFmode \
1058 || (MODE) == V4SImode \
1059 || FLOAT128_VECTOR_P (MODE))
1061 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1062 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1063 || (MODE) == V2DImode || (MODE) == V1TImode)
1065 /* Post-reload, we can't use any new AltiVec registers, as we already
1066 emitted the vrsave mask. */
1068 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1069 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1071 /* Specify the cost of a branch insn; roughly the number of extra insns that
1072 should be added to avoid a branch.
1074 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1075 unscheduled conditional branch. */
1077 #define BRANCH_COST(speed_p, predictable_p) 3
1079 /* Override BRANCH_COST heuristic which empirically produces worse
1080 performance for removing short circuiting from the logical ops. */
1082 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1084 /* Specify the registers used for certain standard purposes.
1085 The values of these macros are register numbers. */
1087 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1088 /* #define PC_REGNUM */
1090 /* Register to use for pushing function arguments. */
1091 #define STACK_POINTER_REGNUM 1
1093 /* Base register for access to local variables of the function. */
1094 #define HARD_FRAME_POINTER_REGNUM 31
1096 /* Base register for access to local variables of the function. */
1097 #define FRAME_POINTER_REGNUM 110
1099 /* Base register for access to arguments of the function. */
1100 #define ARG_POINTER_REGNUM 99
1102 /* Place to put static chain when calling a function that requires it. */
1103 #define STATIC_CHAIN_REGNUM 11
1105 /* Base register for access to thread local storage variables. */
1106 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1108 \f
1109 /* Define the classes of registers for register constraints in the
1110 machine description. Also define ranges of constants.
1112 One of the classes must always be named ALL_REGS and include all hard regs.
1113 If there is more than one class, another class must be named NO_REGS
1114 and contain no registers.
1116 The name GENERAL_REGS must be the name of a class (or an alias for
1117 another name such as ALL_REGS). This is the class of registers
1118 that is allowed by "g" or "r" in a register constraint.
1119 Also, registers outside this class are allocated only when
1120 instructions express preferences for them.
1122 The classes must be numbered in nondecreasing order; that is,
1123 a larger-numbered class must never be contained completely
1124 in a smaller-numbered class.
1126 For any two classes, it is very desirable that there be another
1127 class that represents their union. */
1129 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1130 condition registers, plus three special registers, CTR, and the link
1131 register. AltiVec adds a vector register class. VSX registers overlap the
1132 FPR registers and the Altivec registers.
1134 However, r0 is special in that it cannot be used as a base register.
1135 So make a class for registers valid as base registers.
1137 Also, cr0 is the only condition code register that can be used in
1138 arithmetic insns, so make a separate class for it. */
1140 enum reg_class
1141 {
1142 NO_REGS,
1143 BASE_REGS,
1144 GENERAL_REGS,
1145 FLOAT_REGS,
1146 ALTIVEC_REGS,
1147 VSX_REGS,
1148 VRSAVE_REGS,
1149 VSCR_REGS,
1150 GEN_OR_FLOAT_REGS,
1151 GEN_OR_VSX_REGS,
1152 LINK_REGS,
1153 CTR_REGS,
1154 LINK_OR_CTR_REGS,
1155 SPECIAL_REGS,
1156 SPEC_OR_GEN_REGS,
1157 CR0_REGS,
1158 CR_REGS,
1159 NON_FLOAT_REGS,
1160 CA_REGS,
1161 ALL_REGS,
1162 LIM_REG_CLASSES
1163 };
1165 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1167 /* Give names of register classes as strings for dump file. */
1169 #define REG_CLASS_NAMES \
1170 { \
1191 }
1193 /* Define which registers fit in which classes.
1194 This is an initializer for a vector of HARD_REG_SET
1195 of length N_REG_CLASSES. */
1197 #define REG_CLASS_CONTENTS \
1198 { \
1200 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1202 { 0xfffffffe, 0x00000000, 0x00000000, 0x00004008 }, \
1204 { 0xffffffff, 0x00000000, 0x00000000, 0x00004008 }, \
1206 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, \
1208 { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \
1210 { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1212 { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \
1214 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, \
1216 { 0xffffffff, 0xffffffff, 0x00000000, 0x00004008 }, \
1218 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00004008 }, \
1220 { 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \
1222 { 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \
1224 { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \
1226 { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \
1228 { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \
1230 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \
1232 { 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \
1234 { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \
1236 { 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
1238 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
1239 }
1241 /* The same information, inverted:
1242 Return the class number of the smallest class containing
1243 reg number REGNO. This could be a conditional expression
1244 or could index an array. */
1248 #define REGNO_REG_CLASS(REGNO) \
1249 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1250 rs6000_regno_regclass[(REGNO)])
1252 /* Register classes for various constraints that are based on the target
1253 switches. */
1263 RS6000_CONSTRAINT_MAX
1264 };
1268 /* The class value for index registers, and the one for base regs. */
1269 #define INDEX_REG_CLASS GENERAL_REGS
1270 #define BASE_REG_CLASS BASE_REGS
1272 /* Return whether a given register class can hold VSX objects. */
1273 #define VSX_REG_CLASS_P(CLASS) \
1274 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1276 /* Return whether a given register class targets general purpose registers. */
1277 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1279 /* Given an rtx X being reloaded into a reg required to be
1280 in class CLASS, return the class of reg to actually use.
1281 In general this is just CLASS; but on some machines
1282 in some cases it is preferable to use a more restrictive class.
1284 On the RS/6000, we have to return NO_REGS when we want to reload a
1285 floating-point CONST_DOUBLE to force it to be copied to memory.
1287 We also don't want to reload integer values into floating-point
1288 registers if we can at all help it. In fact, this can
1289 cause reload to die, if it tries to generate a reload of CTR
1290 into a FP register and discovers it doesn't have the memory location
1291 required.
1293 ??? Would it be a good idea to have reload do the converse, that is
1294 try to reload floating modes into FP registers if possible?
1295 */
1297 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1298 rs6000_preferred_reload_class_ptr (X, CLASS)
1300 /* Return the register class of a scratch register needed to copy IN into
1301 or out of a register in CLASS in MODE. If it can be done directly,
1302 NO_REGS is returned. */
1304 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1305 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1307 /* Return the maximum number of consecutive registers
1308 needed to represent mode MODE in a register of class CLASS.
1310 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1311 a single reg is enough for two words, unless we have VSX, where the FP
1312 registers can hold 128 bits. */
1313 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1315 /* Stack layout; function entry, exit and calling. */
1317 /* Define this if pushing a word on the stack
1318 makes the stack pointer a smaller address. */
1319 #define STACK_GROWS_DOWNWARD 1
1321 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1322 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1324 /* Define this to nonzero if the nominal address of the stack frame
1325 is at the high-address end of the local variables;
1326 that is, each additional local variable allocated
1327 goes at a more negative offset in the frame.
1329 On the RS/6000, we grow upwards, from the area after the outgoing
1330 arguments. */
1331 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1332 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1334 /* Size of the fixed area on the stack */
1335 #define RS6000_SAVE_AREA \
1336 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1337 << (TARGET_64BIT ? 1 : 0))
1339 /* Stack offset for toc save slot. */
1340 #define RS6000_TOC_SAVE_SLOT \
1341 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1343 /* Align an address */
1344 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1346 /* Offset within stack frame to start allocating local variables at.
1347 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1348 first local allocated. Otherwise, it is the offset to the BEGINNING
1349 of the first local allocated.
1351 On the RS/6000, the frame pointer is the same as the stack pointer,
1352 except for dynamic allocations. So we start after the fixed area and
1353 outgoing parameter area.
1355 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1356 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1357 sizes of the fixed area and the parameter area must be a multiple of
1358 STACK_BOUNDARY. */
1360 #define RS6000_STARTING_FRAME_OFFSET \
1361 (cfun->calls_alloca \
1362 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1363 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1364 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1365 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1366 + RS6000_SAVE_AREA))
1368 /* Offset from the stack pointer register to an item dynamically
1369 allocated on the stack, e.g., by `alloca'.
1371 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1372 length of the outgoing arguments. The default is correct for most
1373 machines. See `function.c' for details.
1375 This value must be a multiple of STACK_BOUNDARY (hard coded in
1376 `emit-rtl.c'). */
1377 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1378 RS6000_ALIGN (crtl->outgoing_args_size.to_constant () \
1379 + STACK_POINTER_OFFSET, \
1380 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1382 /* If we generate an insn to push BYTES bytes,
1383 this says how many the stack pointer really advances by.
1384 On RS/6000, don't define this because there are no push insns. */
1385 /* #define PUSH_ROUNDING(BYTES) */
1387 /* Offset of first parameter from the argument pointer register value.
1388 On the RS/6000, we define the argument pointer to the start of the fixed
1389 area. */
1390 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1392 /* Offset from the argument pointer register value to the top of
1393 stack. This is different from FIRST_PARM_OFFSET because of the
1394 register save area. */
1395 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1397 /* Define this if stack space is still allocated for a parameter passed
1398 in a register. The value is the number of bytes allocated to this
1399 area. */
1400 #define REG_PARM_STACK_SPACE(FNDECL) \
1401 rs6000_reg_parm_stack_space ((FNDECL), false)
1403 /* Define this macro if space guaranteed when compiling a function body
1404 is different to space required when making a call, a situation that
1405 can arise with K&R style function definitions. */
1406 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1407 rs6000_reg_parm_stack_space ((FNDECL), true)
1409 /* Define this if the above stack space is to be considered part of the
1410 space allocated by the caller. */
1411 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1413 /* This is the difference between the logical top of stack and the actual sp.
1415 For the RS/6000, sp points past the fixed area. */
1416 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1418 /* Define this if the maximum size of all the outgoing args is to be
1419 accumulated and pushed during the prologue. The amount can be
1420 found in the variable crtl->outgoing_args_size. */
1421 #define ACCUMULATE_OUTGOING_ARGS 1
1423 /* Define how to find the value returned by a library function
1424 assuming the value has mode MODE. */
1426 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1428 /* DRAFT_V4_STRUCT_RET defaults off. */
1429 #define DRAFT_V4_STRUCT_RET 0
1431 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1432 #define DEFAULT_PCC_STRUCT_RETURN 0
1434 /* Mode of stack savearea.
1435 FUNCTION is VOIDmode because calling convention maintains SP.
1436 BLOCK needs Pmode for SP.
1437 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1438 #define STACK_SAVEAREA_MODE(LEVEL) \
1439 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1440 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1442 /* Minimum and maximum general purpose registers used to hold arguments. */
1443 #define GP_ARG_MIN_REG 3
1444 #define GP_ARG_MAX_REG 10
1445 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1447 /* Minimum and maximum floating point registers used to hold arguments. */
1448 #define FP_ARG_MIN_REG 33
1449 #define FP_ARG_AIX_MAX_REG 45
1450 #define FP_ARG_V4_MAX_REG 40
1451 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1452 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1453 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1455 /* Minimum and maximum AltiVec registers used to hold arguments. */
1456 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1457 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1458 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1460 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1461 #define AGGR_ARG_NUM_REG 8
1463 /* Return registers */
1464 #define GP_ARG_RETURN GP_ARG_MIN_REG
1465 #define FP_ARG_RETURN FP_ARG_MIN_REG
1466 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1467 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1468 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1469 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1470 ? (ALTIVEC_ARG_RETURN \
1471 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1472 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1474 /* Flags for the call/call_value rtl operations set up by function_arg */
1476 /* Bits in 0x00000001 are unused. */
1482 /* Identify PLT sequence for rs6000_pltseq_template. */
1484 RS6000_PLTSEQ_TOCSAVE,
1485 RS6000_PLTSEQ_PLT16_HA,
1486 RS6000_PLTSEQ_PLT16_LO,
1487 RS6000_PLTSEQ_MTCTR,
1488 RS6000_PLTSEQ_PLT_PCREL34
1489 };
1491 #define IS_V4_FP_ARGS(OP) \
1492 ((INTVAL (OP) & (CALL_V4_CLEAR_FP_ARGS | CALL_V4_SET_FP_ARGS)) != 0)
1494 /* Whether OP is an UNSPEC used in !TARGET_TLS_MARKER calls. */
1495 #define IS_NOMARK_TLSGETADDR(OP) \
1496 (!TARGET_TLS_MARKERS \
1497 && GET_CODE (OP) == UNSPEC \
1498 && (XINT (OP, 1) == UNSPEC_TLSGD \
1499 || XINT (OP, 1) == UNSPEC_TLSLD))
1501 /* We don't have prologue and epilogue functions to save/restore
1502 everything for most ABIs. */
1503 #define WORLD_SAVE_P(INFO) 0
1505 /* 1 if N is a possible register number for a function value
1506 as seen by the caller.
1508 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1509 #define FUNCTION_VALUE_REGNO_P(N) \
1510 ((N) == GP_ARG_RETURN \
1511 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1512 && TARGET_HARD_FLOAT) \
1513 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1514 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1516 /* 1 if N is a possible register number for function argument passing.
1517 On RS/6000, these are r3-r10 and fp1-fp13.
1518 On AltiVec, v2 - v13 are used for passing vectors. */
1519 #define FUNCTION_ARG_REGNO_P(N) \
1520 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1521 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1522 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1523 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1524 && TARGET_HARD_FLOAT))
1525 \f
1526 /* Define a data type for recording info about an argument list
1527 during the scan of that argument list. This data type should
1528 hold all necessary information about the function itself
1529 and about the args processed so far, enough to enable macros
1530 such as FUNCTION_ARG to determine where the next arg should go.
1532 On the RS/6000, this is a structure. The first element is the number of
1533 total argument words, the second is used to store the next
1534 floating-point register number, and the third says how many more args we
1535 have prototype types for.
1537 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1538 the next available GP register, `fregno' is the next available FP
1539 register, and `words' is the number of words used on the stack.
1541 The varargs/stdarg support requires that this structure's size
1542 be a multiple of sizeof(int). */
1545 {
1557 GPR space (darwin64) */
1563 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1564 for a call to a function whose data type is FNTYPE.
1565 For a library call, FNTYPE is 0. */
1567 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1568 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1569 N_NAMED_ARGS, FNDECL, VOIDmode)
1571 /* Similar, but when scanning the definition of a procedure. We always
1572 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1574 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1575 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1576 1000, current_function_decl, VOIDmode)
1578 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1580 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1581 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1582 0, NULL_TREE, MODE)
1584 #define PAD_VARARGS_DOWN \
1585 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1587 /* Output assembler code to FILE to increment profiler label # LABELNO
1588 for profiling a function entry. */
1590 #define FUNCTION_PROFILER(FILE, LABELNO) \
1591 output_function_profiler ((FILE), (LABELNO));
1593 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1594 the stack pointer does not matter. No definition is equivalent to
1595 always zero.
1597 On the RS/6000, this is nonzero because we can restore the stack from
1598 its backpointer, which we maintain. */
1599 #define EXIT_IGNORE_STACK 1
1601 /* Define this macro as a C expression that is nonzero for registers
1602 that are used by the epilogue or the return' pattern. The stack
1603 and frame pointer registers are already be assumed to be used as
1604 needed. */
1606 #define EPILOGUE_USES(REGNO) \
1607 ((reload_completed && (REGNO) == LR_REGNO) \
1608 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1609 || (crtl->calls_eh_return \
1610 && TARGET_AIX \
1611 && (REGNO) == 2))
1613 \f
1614 /* Length in units of the trampoline for entering a nested function. */
1616 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1617 \f
1618 /* Definitions for __builtin_return_address and __builtin_frame_address.
1619 __builtin_return_address (0) should give link register (LR_REGNO), enable
1620 this. */
1621 /* This should be uncommented, so that the link register is used, but
1622 currently this would result in unmatched insns and spilling fixed
1623 registers so we'll leave it for another day. When these problems are
1624 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1625 (mrs) */
1626 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1628 /* Number of bytes into the frame return addresses can be found. See
1629 rs6000_stack_info in rs6000.c for more information on how the different
1630 abi's store the return address. */
1631 #define RETURN_ADDRESS_OFFSET \
1632 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1634 /* The current return address is in the link register. The return address
1635 of anything farther back is accessed normally at an offset of 8 from the
1636 frame pointer. */
1637 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1638 (rs6000_return_addr (COUNT, FRAME))
1640 \f
1641 /* Definitions for register eliminations.
1643 We have two registers that can be eliminated on the RS/6000. First, the
1644 frame pointer register can often be eliminated in favor of the stack
1645 pointer register. Secondly, the argument pointer register can always be
1646 eliminated; it is replaced with either the stack or frame pointer.
1648 In addition, we use the elimination mechanism to see if r30 is needed
1649 Initially we assume that it isn't. If it is, we spill it. This is done
1650 by making it an eliminable register. We replace it with itself so that
1651 if it isn't needed, then existing uses won't be modified. */
1653 /* This is an array of structures. Each structure initializes one pair
1654 of eliminable registers. The "from" register number is given first,
1655 followed by "to". Eliminations of the same "from" register are listed
1656 in order of preference. */
1657 #define ELIMINABLE_REGS \
1658 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1659 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1660 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1661 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1662 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1663 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1665 /* Define the offset between two registers, one to be eliminated, and the other
1666 its replacement, at the start of a routine. */
1667 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1668 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1669 \f
1670 /* Addressing modes, and classification of registers for them. */
1672 #define HAVE_PRE_DECREMENT 1
1673 #define HAVE_PRE_INCREMENT 1
1674 #define HAVE_PRE_MODIFY_DISP 1
1675 #define HAVE_PRE_MODIFY_REG 1
1677 /* Macros to check register numbers against specific register classes. */
1679 /* These assume that REGNO is a hard or pseudo reg number.
1680 They give nonzero only if REGNO is a hard reg of the suitable class
1681 or a pseudo reg currently allocated to a suitable hard reg.
1682 Since they use reg_renumber, they are safe only once reg_renumber
1683 has been allocated, which happens in reginfo.c during register
1684 allocation. */
1686 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1687 (HARD_REGISTER_NUM_P (REGNO) \
1688 ? (REGNO) <= 31 \
1689 || (REGNO) == ARG_POINTER_REGNUM \
1690 || (REGNO) == FRAME_POINTER_REGNUM \
1691 : (reg_renumber[REGNO] >= 0 \
1692 && (reg_renumber[REGNO] <= 31 \
1693 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \
1694 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1696 #define REGNO_OK_FOR_BASE_P(REGNO) \
1697 (HARD_REGISTER_NUM_P (REGNO) \
1698 ? ((REGNO) > 0 && (REGNO) <= 31) \
1699 || (REGNO) == ARG_POINTER_REGNUM \
1700 || (REGNO) == FRAME_POINTER_REGNUM \
1701 : (reg_renumber[REGNO] > 0 \
1702 && (reg_renumber[REGNO] <= 31 \
1703 || reg_renumber[REGNO] == ARG_POINTER_REGNUM \
1704 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1706 /* Nonzero if X is a hard reg that can be used as an index
1707 or if it is a pseudo reg in the non-strict case. */
1708 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1709 ((!(STRICT) && !HARD_REGISTER_P (X)) \
1710 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1712 /* Nonzero if X is a hard reg that can be used as a base reg
1713 or if it is a pseudo reg in the non-strict case. */
1714 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1715 ((!(STRICT) && !HARD_REGISTER_P (X)) \
1716 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1718 \f
1719 /* Maximum number of registers that can appear in a valid memory address. */
1721 #define MAX_REGS_PER_ADDRESS 2
1723 /* Recognize any constant value that is a valid address. */
1725 #define CONSTANT_ADDRESS_P(X) \
1726 (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \
1727 || CONST_INT_P (X) || GET_CODE (X) == CONST \
1728 || GET_CODE (X) == HIGH)
1730 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
1731 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
1732 && EASY_VECTOR_15((n) >> 1) \
1733 && ((n) & 1) == 0)
1735 #define EASY_VECTOR_MSB(n,mode) \
1736 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
1737 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
1739 \f
1740 #define FIND_BASE_TERM rs6000_find_base_term
1741 \f
1742 /* The register number of the register used to address a table of
1743 static data addresses in memory. In some cases this register is
1744 defined by a processor's "application binary interface" (ABI).
1745 When this macro is defined, RTL is generated for this register
1746 once, as with the stack pointer and frame pointer registers. If
1747 this macro is not defined, it is up to the machine-dependent files
1748 to allocate such a register (if necessary). */
1750 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
1751 #define PIC_OFFSET_TABLE_REGNUM \
1752 (TARGET_TOC ? TOC_REGISTER \
1753 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
1754 : INVALID_REGNUM)
1756 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
1758 /* Define this macro if the register defined by
1759 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
1760 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
1762 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
1764 /* A C expression that is nonzero if X is a legitimate immediate
1765 operand on the target machine when generating position independent
1766 code. You can assume that X satisfies `CONSTANT_P', so you need
1767 not check this. You can also assume FLAG_PIC is true, so you need
1768 not check it either. You need not define this macro if all
1769 constants (including `SYMBOL_REF') can be immediate operands when
1770 generating position independent code. */
1772 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
1773 \f
1774 /* Specify the machine mode that this machine uses
1775 for the index in the tablejump instruction. */
1776 #define CASE_VECTOR_MODE SImode
1778 /* Define as C expression which evaluates to nonzero if the tablejump
1779 instruction expects the table to contain offsets from the address of the
1780 table.
1781 Do not define this if the table should contain absolute addresses. */
1782 #define CASE_VECTOR_PC_RELATIVE 1
1784 /* Define this as 1 if `char' should by default be signed; else as 0. */
1785 #define DEFAULT_SIGNED_CHAR 0
1787 /* An integer expression for the size in bits of the largest integer machine
1788 mode that should actually be used. */
1790 /* Allow pairs of registers to be used, which is the intent of the default. */
1791 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
1793 /* Max number of bytes we can move from memory to memory
1794 in one reasonably fast instruction. */
1795 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
1796 #define MAX_MOVE_MAX 8
1798 /* Nonzero if access to memory by bytes is no faster than for words.
1799 Also nonzero if doing byte operations (specifically shifts) in registers
1800 is undesirable. */
1801 #define SLOW_BYTE_ACCESS 1
1803 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1804 will either zero-extend or sign-extend. The value of this macro should
1805 be the code that says which one of the two operations is implicitly
1806 done, UNKNOWN if none. */
1807 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1809 /* Define if loading short immediate values into registers sign extends. */
1810 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1811 \f
1812 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
1813 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1814 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1816 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
1817 zero. The hardware instructions added in Power9 and the sequences using
1818 popcount return 32 or 64. */
1819 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1820 (TARGET_CTZ || TARGET_POPCNTD \
1821 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
1822 : ((VALUE) = -1, 2))
1824 /* Specify the machine mode that pointers have.
1825 After generation of rtl, the compiler makes no further distinction
1826 between pointers and any other objects of this machine mode. */
1828 #define Pmode rs6000_pmode
1830 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
1831 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
1833 /* Mode of a function address in a call instruction (for indexing purposes).
1834 Doesn't matter on RS/6000. */
1835 #define FUNCTION_MODE SImode
1837 /* Define this if addresses of constant functions
1838 shouldn't be put through pseudo regs where they can be cse'd.
1839 Desirable on machines where ordinary constants are expensive
1840 but a CALL with constant address is cheap. */
1841 #define NO_FUNCTION_CSE 1
1843 /* Define this to be nonzero if shift instructions ignore all but the low-order
1844 few bits.
1846 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
1847 have been dropped from the PowerPC architecture. */
1848 #define SHIFT_COUNT_TRUNCATED 0
1850 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
1851 should be adjusted to reflect any required changes. This macro is used when
1852 there is some systematic length adjustment required that would be difficult
1853 to express in the length attribute. */
1855 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
1857 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
1858 COMPARE, return the mode to be used for the comparison. For
1859 floating-point, CCFPmode should be used. CCUNSmode should be used
1860 for unsigned comparisons. CCEQmode should be used when we are
1861 doing an inequality comparison on the result of a
1862 comparison. CCmode should be used in all other cases. */
1864 #define SELECT_CC_MODE(OP,X,Y) \
1865 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
1866 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
1867 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
1868 ? CCEQmode : CCmode))
1870 /* Can the condition code MODE be safely reversed? This is safe in
1871 all cases on this port, because at present it doesn't use the
1872 trapping FP comparisons (fcmpo). */
1873 #define REVERSIBLE_CC_MODE(MODE) 1
1875 /* Given a condition code and a mode, return the inverse condition. */
1876 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
1878 \f
1879 /* Target cpu costs. */
1896 operations. */
1898 };
1901 \f
1902 /* Control the assembler format that we output. */
1904 /* A C string constant describing how to begin a comment in the target
1905 assembler language. The compiler assumes that the comment will end at
1906 the end of the line. */
1909 /* Flag to say the TOC is initialized */
1912 /* Macro to output a special constant pool entry. Go to WIN if we output
1913 it. Otherwise, it is written the usual way.
1915 On the RS/6000, toc entries are handled this way. */
1917 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
1918 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
1919 { \
1920 output_toc (FILE, X, LABELNO, MODE); \
1921 goto WIN; \
1922 } \
1923 }
1925 #ifdef HAVE_GAS_WEAK
1926 #define RS6000_WEAK 1
1927 #else
1928 #define RS6000_WEAK 0
1929 #endif
1931 #if RS6000_WEAK
1932 /* Used in lieu of ASM_WEAKEN_LABEL. */
1933 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
1934 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
1935 #endif
1937 #if HAVE_GAS_WEAKREF
1938 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
1939 do \
1940 { \
1942 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1944 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1945 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
1946 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1947 { \
1949 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
1951 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
1952 } \
1954 } while (0)
1955 #endif
1957 /* This implements the `alias' attribute. */
1958 #undef ASM_OUTPUT_DEF_FROM_DECLS
1959 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
1960 do \
1961 { \
1962 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
1963 const char *name = IDENTIFIER_POINTER (TARGET); \
1964 if (TREE_CODE (DECL) == FUNCTION_DECL \
1965 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
1966 { \
1967 if (TREE_PUBLIC (DECL)) \
1968 { \
1969 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1970 { \
1972 RS6000_OUTPUT_BASENAME (FILE, alias); \
1974 } \
1975 } \
1976 else if (TARGET_XCOFF) \
1977 { \
1978 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
1979 { \
1981 RS6000_OUTPUT_BASENAME (FILE, alias); \
1984 RS6000_OUTPUT_BASENAME (FILE, alias); \
1986 } \
1987 } \
1989 RS6000_OUTPUT_BASENAME (FILE, alias); \
1991 RS6000_OUTPUT_BASENAME (FILE, name); \
1993 } \
1994 ASM_OUTPUT_DEF (FILE, alias, name); \
1995 } \
1996 while (0)
1998 #define TARGET_ASM_FILE_START rs6000_file_start
2000 /* Output to assembler file text saying following lines
2001 may contain character constants, extra white space, comments, etc. */
2005 /* Output to assembler file text saying following lines
2006 no longer contain unusual constructs. */
2010 /* How to refer to registers in assembler output.
2011 This sequence is indexed by compiler's hard-register-number (see above). */
2015 #define REGISTER_NAMES \
2016 { \
2049 \
2082 \
2115 \
2120 \
2129 \
2132 \
2134 }
2136 /* Table of additional register names to use in user input. */
2138 #define ADDITIONAL_REGISTER_NAMES \
2187 }
2189 /* This is how to output an element of a case-vector that is relative. */
2191 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2192 do { char buf[100]; \
2195 assemble_name (FILE, buf); \
2198 assemble_name (FILE, buf); \
2200 } while (0)
2202 /* This is how to output an assembler line
2203 that says to advance the location counter
2204 to a multiple of 2**LOG bytes. */
2206 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2207 if ((LOG) != 0) \
2210 /* How to align the given loop. */
2211 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2213 /* Alignment guaranteed by __builtin_malloc. */
2214 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2215 However, specifying the stronger guarantee currently leads to
2216 a regression in SPEC CPU2006 437.leslie3d. The stronger
2217 guarantee should be implemented here once that's fixed. */
2218 #define MALLOC_ABI_ALIGNMENT (64)
2220 /* Pick up the return address upon entry to a procedure. Used for
2221 dwarf2 unwind information. This also enables the table driven
2222 mechanism. */
2224 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2225 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2227 /* Describe how we implement __builtin_eh_return. */
2228 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2229 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2231 /* Print operand X (an rtx) in assembler syntax to file FILE.
2232 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2233 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2235 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2237 /* Define which CODE values are valid. */
2241 /* Print a memory address as an operand to reference that memory location. */
2243 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2245 /* For switching between functions with different target attributes. */
2246 #define SWITCHABLE_TARGET 1
2248 /* uncomment for disabling the corresponding default options */
2249 /* #define MACHINE_no_sched_interblock */
2250 /* #define MACHINE_no_sched_speculative */
2251 /* #define MACHINE_no_sched_speculative_load */
2253 /* General flags. */
2256 /* Classification of the builtin functions as to which switches enable the
2257 builtin, and what attributes it should have. We used to use the target
2258 flags macros, but we've run out of bits, so we now map the options into new
2259 settings used here. */
2261 /* Builtin attributes. */
2273 modifies global state. */
2275 state/mem and does
2276 not modify global state. */
2280 /* Miscellaneous information. */
2287 /* Convenience macros to document the instruction type. */
2291 /* Builtin targets. For now, we reuse the masks for those options that are in
2292 target flags, and pick a random bit for ldbl128, which isn't in
2293 target_flags. */
2317 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2318 | RS6000_BTM_VSX \
2319 | RS6000_BTM_P8_VECTOR \
2320 | RS6000_BTM_P9_VECTOR \
2321 | RS6000_BTM_P9_MISC \
2322 | RS6000_BTM_MODULO \
2323 | RS6000_BTM_CRYPTO \
2324 | RS6000_BTM_FRE \
2325 | RS6000_BTM_FRES \
2326 | RS6000_BTM_FRSQRTE \
2327 | RS6000_BTM_FRSQRTES \
2328 | RS6000_BTM_HTM \
2329 | RS6000_BTM_POPCNTD \
2330 | RS6000_BTM_CELL \
2331 | RS6000_BTM_DFP \
2332 | RS6000_BTM_HARD_FLOAT \
2333 | RS6000_BTM_LDBL128 \
2334 | RS6000_BTM_POWERPC64 \
2335 | RS6000_BTM_FLOAT128 \
2336 | RS6000_BTM_FLOAT128_HW)
2338 /* Define builtin enum index. */
2340 #undef RS6000_BUILTIN_0
2341 #undef RS6000_BUILTIN_1
2342 #undef RS6000_BUILTIN_2
2343 #undef RS6000_BUILTIN_3
2344 #undef RS6000_BUILTIN_A
2345 #undef RS6000_BUILTIN_D
2346 #undef RS6000_BUILTIN_H
2347 #undef RS6000_BUILTIN_P
2348 #undef RS6000_BUILTIN_X
2350 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2351 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2352 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2353 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2354 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2355 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2356 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2357 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2358 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2360 enum rs6000_builtins
2361 {
2364 RS6000_BUILTIN_COUNT
2365 };
2367 #undef RS6000_BUILTIN_0
2368 #undef RS6000_BUILTIN_1
2369 #undef RS6000_BUILTIN_2
2370 #undef RS6000_BUILTIN_3
2371 #undef RS6000_BUILTIN_A
2372 #undef RS6000_BUILTIN_D
2373 #undef RS6000_BUILTIN_H
2374 #undef RS6000_BUILTIN_P
2375 #undef RS6000_BUILTIN_X
2377 enum rs6000_builtin_type_index
2378 {
2379 RS6000_BTI_NOT_OPAQUE,
2380 RS6000_BTI_opaque_V4SI,
2382 RS6000_BTI_V1TI,
2383 RS6000_BTI_V2DI,
2384 RS6000_BTI_V2DF,
2385 RS6000_BTI_V4HI,
2386 RS6000_BTI_V4SI,
2387 RS6000_BTI_V4SF,
2388 RS6000_BTI_V8HI,
2390 RS6000_BTI_unsigned_V1TI,
2391 RS6000_BTI_unsigned_V8HI,
2392 RS6000_BTI_unsigned_V4SI,
2393 RS6000_BTI_unsigned_V2DI,
2399 channels of 1, 5, 5, and 5 bits
2400 respectively as packed with the
2401 vpkpx insn. __pixel is only
2402 meaningful as a vector type.
2403 There is no corresponding scalar
2404 __pixel data type.) */
2433 RS6000_BTI_MAX
2434 };
2437 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2438 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2439 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2440 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2441 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2442 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2443 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2444 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2445 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2446 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2447 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2448 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2449 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2450 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2451 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2452 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2453 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2454 #define bool_long_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long_long])
2455 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2456 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2457 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2458 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2459 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2460 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2462 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2463 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2464 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2465 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2466 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2467 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2468 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2469 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2470 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2471 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2472 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2473 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2474 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2475 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2476 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2477 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2478 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2479 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2480 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2481 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2482 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2483 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2484 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2489 #ifndef USED_FOR_TARGET
2490 /* A C structure for machine-specific, per-function data.
2491 This is added to the cfun structure. */
2493 {
2494 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
2496 /* Flags if __builtin_return_address (0) was used. */
2498 /* Cache lr_save_p after expansion of builtin_eh_return. */
2500 /* Whether we need to save the TOC to the reserved stack location in the
2501 function prologue. */
2503 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
2504 varargs save area. */
2505 HOST_WIDE_INT varargs_save_offset;
2506 /* Alternative internal arg pointer for -fsplit-stack. */
2507 rtx split_stack_arg_pointer;
2509 /* Flag if r2 setup is needed with ELFv2 ABI. */
2511 /* The number of components we use for separate shrink-wrapping. */
2513 /* The components already handled by separate shrink-wrapping, which should
2514 not be considered by the prologue and epilogue. */
2520 #endif
2523 #define TARGET_SUPPORTS_WIDE_INT 1
2525 #if (GCC_VERSION >= 3000)
2526 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128
2527 #endif
2529 /* Whether a given VALUE is a valid 16 or 34-bit signed offset. */
2530 #define SIGNED_16BIT_OFFSET_P(VALUE) \
2531 IN_RANGE ((VALUE), \
2532 -(HOST_WIDE_INT_1 << 15), \
2533 (HOST_WIDE_INT_1 << 15) - 1)
2535 #define SIGNED_34BIT_OFFSET_P(VALUE) \
2536 IN_RANGE ((VALUE), \
2537 -(HOST_WIDE_INT_1 << 33), \
2538 (HOST_WIDE_INT_1 << 33) - 1)
2540 /* Like SIGNED_16BIT_OFFSET_P and SIGNED_34BIT_OFFSET_P, but with an extra
2541 argument that gives a length to validate a range of addresses, to allow for
2542 splitting insns into several insns, each of which has an offsettable
2543 address. */
2544 #define SIGNED_16BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \
2545 IN_RANGE ((VALUE), \
2546 -(HOST_WIDE_INT_1 << 15), \
2547 (HOST_WIDE_INT_1 << 15) - 1 - (EXTRA))
2549 #define SIGNED_34BIT_OFFSET_EXTRA_P(VALUE, EXTRA) \
2550 IN_RANGE ((VALUE), \
2551 -(HOST_WIDE_INT_1 << 33), \
2552 (HOST_WIDE_INT_1 << 33) - 1 - (EXTRA))