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PR target/21623:
[official-gcc.git] / gcc / config / sh / sh.h
blob44b9c93c1f7375616b832c352374cccc1138efb1
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
23
24 #ifndef GCC_SH_H
25 #define GCC_SH_H
26
27 #define TARGET_VERSION \
28 fputs (" (Hitachi SH)", stderr);
29
30 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
31 include it here, because bconfig.h is also included by gencodes.c . */
32 /* ??? No longer true. */
33 extern int code_for_indirect_jump_scratch;
34
35 #define TARGET_CPU_CPP_BUILTINS() \
36 do { \
37 builtin_define ("__sh__"); \
38 builtin_assert ("cpu=sh"); \
39 builtin_assert ("machine=sh"); \
40 switch ((int) sh_cpu) \
41 { \
42 case PROCESSOR_SH1: \
43 builtin_define ("__sh1__"); \
44 break; \
45 case PROCESSOR_SH2: \
46 builtin_define ("__sh2__"); \
47 break; \
48 case PROCESSOR_SH2E: \
49 builtin_define ("__SH2E__"); \
50 break; \
51 case PROCESSOR_SH2A: \
52 builtin_define ("__SH2A__"); \
53 builtin_define (TARGET_SH2A_DOUBLE \
54 ? (TARGET_FPU_SINGLE ? "__SH2A_SINGLE__" : "__SH2A_DOUBLE__") \
55 : TARGET_FPU_ANY ? "__SH2A_SINGLE_ONLY__" \
56 : "__SH2A_NOFPU__"); \
57 break; \
58 case PROCESSOR_SH3: \
59 builtin_define ("__sh3__"); \
60 builtin_define ("__SH3__"); \
61 if (TARGET_HARD_SH4) \
62 builtin_define ("__SH4_NOFPU__"); \
63 break; \
64 case PROCESSOR_SH3E: \
65 builtin_define (TARGET_HARD_SH4 ? "__SH4_SINGLE_ONLY__" : "__SH3E__"); \
66 break; \
67 case PROCESSOR_SH4: \
68 builtin_define (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__"); \
69 break; \
70 case PROCESSOR_SH4A: \
71 builtin_define ("__SH4A__"); \
72 builtin_define (TARGET_SH4 \
73 ? (TARGET_FPU_SINGLE ? "__SH4_SINGLE__" : "__SH4__") \
74 : TARGET_FPU_ANY ? "__SH4_SINGLE_ONLY__" \
75 : "__SH4_NOFPU__"); \
76 break; \
77 case PROCESSOR_SH5: \
78 { \
79 builtin_define_with_value ("__SH5__", \
80 TARGET_SHMEDIA64 ? "64" : "32", 0); \
81 builtin_define_with_value ("__SHMEDIA__", \
82 TARGET_SHMEDIA ? "1" : "0", 0); \
83 if (! TARGET_FPU_DOUBLE) \
84 builtin_define ("__SH4_NOFPU__"); \
85 } \
86 } \
87 if (TARGET_FPU_ANY) \
88 builtin_define ("__SH_FPU_ANY__"); \
89 if (TARGET_FPU_DOUBLE) \
90 builtin_define ("__SH_FPU_DOUBLE__"); \
91 if (TARGET_HITACHI) \
92 builtin_define ("__HITACHI__"); \
93 builtin_define (TARGET_LITTLE_ENDIAN \
94 ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__"); \
95 } while (0)
96
97 /* We can not debug without a frame pointer. */
98 /* #define CAN_DEBUG_WITHOUT_FP */
99
100 #define CONDITIONAL_REGISTER_USAGE do \
101 { \
102 int regno; \
103 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++) \
104 if (! VALID_REGISTER_P (regno)) \
105 fixed_regs[regno] = call_used_regs[regno] = 1; \
106 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */ \
107 if (TARGET_SH5) \
108 { \
109 call_used_regs[FIRST_GENERAL_REG + 8] \
110 = call_used_regs[FIRST_GENERAL_REG + 9] = 1; \
111 call_really_used_regs[FIRST_GENERAL_REG + 8] \
112 = call_really_used_regs[FIRST_GENERAL_REG + 9] = 1; \
113 } \
114 if (TARGET_SHMEDIA) \
115 { \
116 regno_reg_class[FIRST_GENERAL_REG] = GENERAL_REGS; \
117 CLEAR_HARD_REG_SET (reg_class_contents[FP0_REGS]); \
118 regno_reg_class[FIRST_FP_REG] = FP_REGS; \
119 } \
120 if (flag_pic) \
121 { \
122 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
123 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
124 } \
125 /* Renesas saves and restores mac registers on call. */ \
126 if (TARGET_HITACHI && ! TARGET_NOMACSAVE) \
127 { \
128 call_really_used_regs[MACH_REG] = 0; \
129 call_really_used_regs[MACL_REG] = 0; \
130 } \
131 for (regno = FIRST_FP_REG + (TARGET_LITTLE_ENDIAN != 0); \
132 regno <= LAST_FP_REG; regno += 2) \
133 SET_HARD_REG_BIT (reg_class_contents[DF_HI_REGS], regno); \
134 if (TARGET_SHMEDIA) \
135 { \
136 for (regno = FIRST_TARGET_REG; regno <= LAST_TARGET_REG; regno ++)\
137 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
138 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
139 } \
140 else \
141 for (regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++) \
142 if (! fixed_regs[regno] && call_really_used_regs[regno]) \
143 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno); \
144 } while (0)
145 \f
146 /* Nonzero if this is an ELF target - compile time only */
147 #define TARGET_ELF 0
148
149 /* Nonzero if we should generate code using type 2E insns. */
150 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
151
152 /* Nonzero if we should generate code using type 2A insns. */
153 #define TARGET_SH2A TARGET_HARD_SH2A
154 /* Nonzero if we should generate code using type 2A SF insns. */
155 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
156 /* Nonzero if we should generate code using type 2A DF insns. */
157 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
158
159 /* Nonzero if we should generate code using type 3E insns. */
160 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
161
162 /* Nonzero if the cache line size is 32. */
163 #define TARGET_CACHE32 (TARGET_HARD_SH4 || TARGET_SH5)
164
165 /* Nonzero if we schedule for a superscalar implementation. */
166 #define TARGET_SUPERSCALAR TARGET_HARD_SH4
167
168 /* Nonzero if the target has separate instruction and data caches. */
169 #define TARGET_HARVARD (TARGET_HARD_SH4 || TARGET_SH5)
170
171 /* Nonzero if a double-precision FPU is available. */
172 #define TARGET_FPU_DOUBLE \
173 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
174
175 /* Nonzero if an FPU is available. */
176 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
177
178 /* Nonzero if we should generate code using type 4 insns. */
179 #undef TARGET_SH4
180 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
181
182 /* Nonzero if we're generating code for the common subset of
183 instructions present on both SH4a and SH4al-dsp. */
184 #define TARGET_SH4A_ARCH TARGET_SH4A
185
186 /* Nonzero if we're generating code for SH4a, unless the use of the
187 FPU is disabled (which makes it compatible with SH4al-dsp). */
188 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
189
190 /* Nonzero if we should generate code using the SHcompact instruction
191 set and 32-bit ABI. */
192 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
193
194 /* Nonzero if we should generate code using the SHmedia instruction
195 set and ABI. */
196 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
197
198 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
199 ABI. */
200 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
201
202 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
203 ABI. */
204 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
205
206 /* Nonzero if we should generate code using SHmedia FPU instructions. */
207 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
208
209 /* This is not used by the SH2E calling convention */
210 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
211 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
212 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
213
214 #ifndef TARGET_CPU_DEFAULT
215 #define TARGET_CPU_DEFAULT SELECT_SH1
216 #define SUPPORT_SH1 1
217 #define SUPPORT_SH2E 1
218 #define SUPPORT_SH4 1
219 #define SUPPORT_SH4_SINGLE 1
220 #define SUPPORT_SH2A 1
221 #define SUPPORT_SH2A_SINGLE 1
222 #endif
223
224 #define TARGET_DIVIDE_INV \
225 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
226 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
227 || sh_div_strategy == SH_DIV_INV_CALL \
228 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
229 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
230 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
231 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
232 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
233 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
234 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
235 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
236 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
237
238 #define SELECT_SH1 (MASK_SH1)
239 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
240 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
241 | MASK_FPU_SINGLE)
242 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
243 | MASK_HARD_SH2A_DOUBLE \
244 | MASK_SH2 | MASK_SH1)
245 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
246 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
247 | MASK_SH1 | MASK_FPU_SINGLE)
248 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
249 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
250 | MASK_SH2 | MASK_SH1)
251 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
252 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
253 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
254 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E)
255 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
256 | SELECT_SH3)
257 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
258 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
259 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
260 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
261 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
262 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
263 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
264 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
265 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
266 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
267 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
268
269 #if SUPPORT_SH1
270 #define SUPPORT_SH2 1
271 #endif
272 #if SUPPORT_SH2
273 #define SUPPORT_SH3 1
274 #endif
275 #if SUPPORT_SH3
276 #define SUPPORT_SH4_NOFPU 1
277 #endif
278 #if SUPPORT_SH4_NOFPU
279 #define SUPPORT_SH4A_NOFPU 1
280 #define SUPPORT_SH4AL 1
281 #define SUPPORT_SH2A_NOFPU 1
282 #endif
283
284 #if SUPPORT_SH2E
285 #define SUPPORT_SH3E 1
286 #endif
287 #if SUPPORT_SH3E
288 #define SUPPORT_SH4_SINGLE_ONLY 1
289 #define SUPPORT_SH4A_SINGLE_ONLY 1
290 #define SUPPORT_SH2A_SINGLE_ONLY 1
291 #endif
292
293 #if SUPPORT_SH4
294 #define SUPPORT_SH4A 1
295 #endif
296
297 #if SUPPORT_SH4_SINGLE
298 #define SUPPORT_SH4A_SINGLE 1
299 #endif
300
301 #if SUPPORT_SH5_COMPAT
302 #define SUPPORT_SH5_32MEDIA 1
303 #endif
304
305 #if SUPPORT_SH5_COMPACT_NOFPU
306 #define SUPPORT_SH5_32MEDIA_NOFPU 1
307 #endif
308
309 #define SUPPORT_ANY_SH5_32MEDIA \
310 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
311 #define SUPPORT_ANY_SH5_64MEDIA \
312 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
313 #define SUPPORT_ANY_SH5 \
314 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
315
316 /* Reset all target-selection flags. */
317 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
318 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
319 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5)
320
321 /* This defaults us to big-endian. */
322 #ifndef TARGET_ENDIAN_DEFAULT
323 #define TARGET_ENDIAN_DEFAULT 0
324 #endif
325
326 #ifndef TARGET_OPT_DEFAULT
327 #define TARGET_OPT_DEFAULT MASK_ADJUST_UNROLL
328 #endif
329
330 #define TARGET_DEFAULT \
331 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
332
333 #ifndef SH_MULTILIB_CPU_DEFAULT
334 #define SH_MULTILIB_CPU_DEFAULT "m1"
335 #endif
336
337 #if TARGET_ENDIAN_DEFAULT
338 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
339 #else
340 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
341 #endif
342
343 #define CPP_SPEC " %(subtarget_cpp_spec) "
344
345 #ifndef SUBTARGET_CPP_SPEC
346 #define SUBTARGET_CPP_SPEC ""
347 #endif
348
349 #ifndef SUBTARGET_EXTRA_SPECS
350 #define SUBTARGET_EXTRA_SPECS
351 #endif
352
353 #define EXTRA_SPECS \
354 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
355 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
356 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
357 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
358 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
359 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
360 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
361 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
362 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
363 SUBTARGET_EXTRA_SPECS
364
365 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
366 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4}}}}"
367 #else
368 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4}"
369 #endif
370
371 #define SH_ASM_SPEC \
372 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)}\
373 %(subtarget_asm_isa_spec) %(subtarget_asm_spec)\
374 %{m2a:--isa=sh2a} \
375 %{m2a-single:--isa=sh2a} \
376 %{m2a-single-only:--isa=sh2a} \
377 %{m2a-nofpu:--isa=sh2a-nofpu} \
378 %{m5-compact*:--isa=SHcompact} \
379 %{m5-32media*:--isa=SHmedia --abi=32} \
380 %{m5-64media*:--isa=SHmedia --abi=64} \
381 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
382
383 #define ASM_SPEC SH_ASM_SPEC
384
385 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
386 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
387 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
388 #else
389 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
390 #endif
391 #endif
392
393 #if STRICT_NOFPU == 1
394 /* Strict nofpu means that the compiler should tell the assembler
395 to reject FPU instructions. E.g. from ASM inserts. */
396 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
397 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
398 #else
399 /* If there were an -isa option for sh5-nofpu then it would also go here. */
400 #define SUBTARGET_ASM_ISA_SPEC \
401 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
402 #endif
403 #else /* ! STRICT_NOFPU */
404 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
405 #endif
406
407 #ifndef SUBTARGET_ASM_SPEC
408 #define SUBTARGET_ASM_SPEC ""
409 #endif
410
411 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
412 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
413 #else
414 #define LINK_EMUL_PREFIX "sh%{ml:l}"
415 #endif
416
417 #if TARGET_CPU_DEFAULT & MASK_SH5
418 #if TARGET_CPU_DEFAULT & MASK_SH_E
419 #define LINK_DEFAULT_CPU_EMUL "32"
420 #if TARGET_CPU_DEFAULT & MASK_SH1
421 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
422 #else
423 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
424 #endif /* MASK_SH1 */
425 #else /* !MASK_SH_E */
426 #define LINK_DEFAULT_CPU_EMUL "64"
427 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
428 #endif /* MASK_SH_E */
429 #define ASM_ISA_DEFAULT_SPEC \
430 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
431 #else /* !MASK_SH5 */
432 #define LINK_DEFAULT_CPU_EMUL ""
433 #define ASM_ISA_DEFAULT_SPEC ""
434 #endif /* MASK_SH5 */
435
436 #define SUBTARGET_LINK_EMUL_SUFFIX ""
437 #define SUBTARGET_LINK_SPEC ""
438
439 /* svr4.h redefines LINK_SPEC inappropriately, so go via SH_LINK_SPEC,
440 so that we can undo the damage without code replication. */
441 #define LINK_SPEC SH_LINK_SPEC
442
443 #define SH_LINK_SPEC "\
444 -m %(link_emul_prefix)\
445 %{m5-compact*|m5-32media*:32}\
446 %{m5-64media*:64}\
447 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
448 %(subtarget_link_emul_suffix) \
449 %{mrelax:-relax} %(subtarget_link_spec)"
450
451 #ifndef SH_DIV_STR_FOR_SIZE
452 #define SH_DIV_STR_FOR_SIZE "call"
453 #endif
454
455 #define DRIVER_SELF_SPECS "%{m2a:%{ml:%eSH2a does not support little-endian}}"
456 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
457 do { \
458 if (LEVEL) \
459 { \
460 flag_omit_frame_pointer = -1; \
461 if (! SIZE) \
462 sh_div_str = "inv:minlat"; \
463 } \
464 if (SIZE) \
465 { \
466 target_flags |= MASK_SMALLCODE; \
467 sh_div_str = SH_DIV_STR_FOR_SIZE ; \
468 } \
469 /* We can't meaningfully test TARGET_SHMEDIA here, because -m options \
470 haven't been parsed yet, hence we';d read only the default. \
471 sh_target_reg_class will return NO_REGS if this is not SHMEDIA, so \
472 it's OK to always set flag_branch_target_load_optimize. */ \
473 if (LEVEL > 1) \
474 { \
475 flag_branch_target_load_optimize = 1; \
476 if (! (SIZE)) \
477 target_flags |= MASK_SAVE_ALL_TARGET_REGS; \
478 } \
479 /* Likewise, we can't meaningfully test TARGET_SH2E / TARGET_IEEE \
480 here, so leave it to OVERRIDE_OPTIONS to set \
481 flag_finite_math_only. We set it to 2 here so we know if the user \
482 explicitly requested this to be on or off. */ \
483 flag_finite_math_only = 2; \
484 /* If flag_schedule_insns is 1, we set it to 2 here so we know if \
485 the user explicitly requested this to be on or off. */ \
486 if (flag_schedule_insns > 0) \
487 flag_schedule_insns = 2; \
488 } while (0)
489
490 #define ASSEMBLER_DIALECT assembler_dialect
491
492 extern int assembler_dialect;
493
494 enum sh_divide_strategy_e {
495 SH_DIV_CALL,
496 SH_DIV_CALL2,
497 SH_DIV_FP,
498 SH_DIV_INV,
499 SH_DIV_INV_MINLAT,
500 SH_DIV_INV20U,
501 SH_DIV_INV20L,
502 SH_DIV_INV_CALL,
503 SH_DIV_INV_CALL2,
504 SH_DIV_INV_FP
505 };
506
507 extern enum sh_divide_strategy_e sh_div_strategy;
508
509 #ifndef SH_DIV_STRATEGY_DEFAULT
510 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
511 #endif
512
513 #define OVERRIDE_OPTIONS \
514 do { \
515 int regno; \
516 \
517 if (flag_finite_math_only == 2) \
518 flag_finite_math_only \
519 = !flag_signaling_nans && TARGET_SH2E && ! TARGET_IEEE; \
520 if (TARGET_SH2E && !flag_finite_math_only) \
521 target_flags |= MASK_IEEE; \
522 sh_cpu = CPU_SH1; \
523 assembler_dialect = 0; \
524 if (TARGET_SH2) \
525 sh_cpu = CPU_SH2; \
526 if (TARGET_SH2E) \
527 sh_cpu = CPU_SH2E; \
528 if (TARGET_SH2A) \
529 { \
530 sh_cpu = CPU_SH2A; \
531 if (TARGET_SH2A_DOUBLE) \
532 target_flags |= MASK_FMOVD; \
533 } \
534 if (TARGET_SH3) \
535 sh_cpu = CPU_SH3; \
536 if (TARGET_SH3E) \
537 sh_cpu = CPU_SH3E; \
538 if (TARGET_SH4) \
539 { \
540 assembler_dialect = 1; \
541 sh_cpu = CPU_SH4; \
542 } \
543 if (TARGET_SH4A_ARCH) \
544 { \
545 assembler_dialect = 1; \
546 sh_cpu = CPU_SH4A; \
547 } \
548 if (TARGET_SH5) \
549 { \
550 sh_cpu = CPU_SH5; \
551 target_flags |= MASK_ALIGN_DOUBLE; \
552 if (TARGET_SHMEDIA_FPU) \
553 target_flags |= MASK_FMOVD; \
554 if (TARGET_SHMEDIA) \
555 { \
556 /* There are no delay slots on SHmedia. */ \
557 flag_delayed_branch = 0; \
558 /* Relaxation isn't yet supported for SHmedia */ \
559 target_flags &= ~MASK_RELAX; \
560 /* After reload, if conversion does little good but can cause \
561 ICEs: \
562 - find_if_block doesn't do anything for SH because we don't\
563 have conditional execution patterns. (We use conditional\
564 move patterns, which are handled differently, and only \
565 before reload). \
566 - find_cond_trap doesn't do anything for the SH because we \
567 don't have conditional traps. \
568 - find_if_case_1 uses redirect_edge_and_branch_force in \
569 the only path that does an optimization, and this causes \
570 an ICE when branch targets are in registers. \
571 - find_if_case_2 doesn't do anything for the SHmedia after \
572 reload except when it can redirect a tablejump - and \
573 that's rather rare. */ \
574 flag_if_conversion2 = 0; \
575 if (! strcmp (sh_div_str, "call")) \
576 sh_div_strategy = SH_DIV_CALL; \
577 else if (! strcmp (sh_div_str, "call2")) \
578 sh_div_strategy = SH_DIV_CALL2; \
579 if (! strcmp (sh_div_str, "fp") && TARGET_FPU_ANY) \
580 sh_div_strategy = SH_DIV_FP; \
581 else if (! strcmp (sh_div_str, "inv")) \
582 sh_div_strategy = SH_DIV_INV; \
583 else if (! strcmp (sh_div_str, "inv:minlat")) \
584 sh_div_strategy = SH_DIV_INV_MINLAT; \
585 else if (! strcmp (sh_div_str, "inv20u")) \
586 sh_div_strategy = SH_DIV_INV20U; \
587 else if (! strcmp (sh_div_str, "inv20l")) \
588 sh_div_strategy = SH_DIV_INV20L; \
589 else if (! strcmp (sh_div_str, "inv:call2")) \
590 sh_div_strategy = SH_DIV_INV_CALL2; \
591 else if (! strcmp (sh_div_str, "inv:call")) \
592 sh_div_strategy = SH_DIV_INV_CALL; \
593 else if (! strcmp (sh_div_str, "inv:fp")) \
594 { \
595 if (TARGET_FPU_ANY) \
596 sh_div_strategy = SH_DIV_INV_FP; \
597 else \
598 sh_div_strategy = SH_DIV_INV; \
599 } \
600 } \
601 /* -fprofile-arcs needs a working libgcov . In unified tree \
602 configurations with newlib, this requires to configure with \
603 --with-newlib --with-headers. But there is no way to check \
604 here we have a working libgcov, so just assume that we have. */\
605 if (profile_flag) \
606 warning (0, "profiling is still experimental for this target");\
607 } \
608 else \
609 { \
610 /* Only the sh64-elf assembler fully supports .quad properly. */\
611 targetm.asm_out.aligned_op.di = NULL; \
612 targetm.asm_out.unaligned_op.di = NULL; \
613 } \
614 if (sh_divsi3_libfunc[0]) \
615 ; /* User supplied - leave it alone. */ \
616 else if (TARGET_HARD_SH4 && TARGET_SH2E) \
617 sh_divsi3_libfunc = "__sdivsi3_i4"; \
618 else if (TARGET_SH5) \
619 { \
620 if (TARGET_FPU_ANY && TARGET_SH1) \
621 sh_divsi3_libfunc = "__sdivsi3_i4"; \
622 else \
623 sh_divsi3_libfunc = "__sdivsi3_1"; \
624 } \
625 else \
626 sh_divsi3_libfunc = "__sdivsi3"; \
627 if (TARGET_FMOVD) \
628 reg_class_from_letter['e' - 'a'] = NO_REGS; \
629 \
630 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
631 if (! VALID_REGISTER_P (regno)) \
632 sh_register_names[regno][0] = '\0'; \
633 \
634 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++) \
635 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno))) \
636 sh_additional_register_names[regno][0] = '\0'; \
637 \
638 if (flag_omit_frame_pointer < 0) \
639 { \
640 /* The debugging information is sufficient, \
641 but gdb doesn't implement this yet */ \
642 if (0) \
643 flag_omit_frame_pointer \
644 = (PREFERRED_DEBUGGING_TYPE == DWARF2_DEBUG); \
645 else \
646 flag_omit_frame_pointer = 0; \
647 } \
648 \
649 if ((flag_pic && ! TARGET_PREFERGOT) \
650 || (TARGET_SHMEDIA && !TARGET_PT_FIXED)) \
651 flag_no_function_cse = 1; \
652 \
653 if (SMALL_REGISTER_CLASSES) \
654 { \
655 /* Never run scheduling before reload, since that can \
656 break global alloc, and generates slower code anyway due \
657 to the pressure on R0. */ \
658 /* Enable sched1 for SH4; ready queue will be reordered by \
659 the target hooks when pressure is high. We can not do this for \
660 SH3 and lower as they give spill failures for R0. */ \
661 if (!TARGET_HARD_SH4) \
662 flag_schedule_insns = 0; \
663 /* ??? Current exception handling places basic block boundaries \
664 after call_insns. It causes the high pressure on R0 and gives \
665 spill failures for R0 in reload. See PR 22553 and the thread \
666 on gcc-patches \
667 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */ \
668 else if (flag_exceptions) \
669 { \
670 if (flag_schedule_insns == 1) \
671 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
672 flag_schedule_insns = 0; \
673 } \
674 } \
675 \
676 if (align_loops == 0) \
677 align_loops = 1 << (TARGET_SH5 ? 3 : 2); \
678 if (align_jumps == 0) \
679 align_jumps = 1 << CACHE_LOG; \
680 else if (align_jumps < (TARGET_SHMEDIA ? 4 : 2)) \
681 align_jumps = TARGET_SHMEDIA ? 4 : 2; \
682 \
683 /* Allocation boundary (in *bytes*) for the code of a function. \
684 SH1: 32 bit alignment is faster, because instructions are always \
685 fetched as a pair from a longword boundary. \
686 SH2 .. SH5 : align to cache line start. */ \
687 if (align_functions == 0) \
688 align_functions \
689 = TARGET_SMALLCODE ? FUNCTION_BOUNDARY/8 : (1 << CACHE_LOG); \
690 /* The linker relaxation code breaks when a function contains \
691 alignments that are larger than that at the start of a \
692 compilation unit. */ \
693 if (TARGET_RELAX) \
694 { \
695 int min_align \
696 = align_loops > align_jumps ? align_loops : align_jumps; \
697 \
698 /* Also take possible .long constants / mova tables int account. */\
699 if (min_align < 4) \
700 min_align = 4; \
701 if (align_functions < min_align) \
702 align_functions = min_align; \
703 } \
704 } while (0)
705 \f
706 /* Target machine storage layout. */
707
708 /* Define this if most significant bit is lowest numbered
709 in instructions that operate on numbered bit-fields. */
710
711 #define BITS_BIG_ENDIAN 0
712
713 /* Define this if most significant byte of a word is the lowest numbered. */
714 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
715
716 /* Define this if most significant word of a multiword number is the lowest
717 numbered. */
718 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
719
720 /* Define this to set the endianness to use in libgcc2.c, which can
721 not depend on target_flags. */
722 #if defined(__LITTLE_ENDIAN__)
723 #define LIBGCC2_WORDS_BIG_ENDIAN 0
724 #else
725 #define LIBGCC2_WORDS_BIG_ENDIAN 1
726 #endif
727
728 #define MAX_BITS_PER_WORD 64
729
730 /* Width in bits of an `int'. We want just 32-bits, even if words are
731 longer. */
732 #define INT_TYPE_SIZE 32
733
734 /* Width in bits of a `long'. */
735 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
736
737 /* Width in bits of a `long long'. */
738 #define LONG_LONG_TYPE_SIZE 64
739
740 /* Width in bits of a `long double'. */
741 #define LONG_DOUBLE_TYPE_SIZE 64
742
743 /* Width of a word, in units (bytes). */
744 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
745 #define MIN_UNITS_PER_WORD 4
746
747 /* Scaling factor for Dwarf data offsets for CFI information.
748 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
749 SHmedia; however, since we do partial register saves for the registers
750 visible to SHcompact, and for target registers for SHMEDIA32, we have
751 to allow saves that are only 4-byte aligned. */
752 #define DWARF_CIE_DATA_ALIGNMENT -4
753
754 /* Width in bits of a pointer.
755 See also the macro `Pmode' defined below. */
756 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
757
758 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
759 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
760
761 /* Boundary (in *bits*) on which stack pointer should be aligned. */
762 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
763
764 /* The log (base 2) of the cache line size, in bytes. Processors prior to
765 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
766 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
767 #define CACHE_LOG (TARGET_CACHE32 ? 5 : TARGET_SH2 ? 4 : 2)
768
769 /* ABI given & required minimum allocation boundary (in *bits*) for the
770 code of a function. */
771 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
772
773 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
774 the vbit must go into the delta field of
775 pointers-to-member-functions. */
776 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
777 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
778
779 /* Alignment of field after `int : 0' in a structure. */
780 #define EMPTY_FIELD_BOUNDARY 32
781
782 /* No data type wants to be aligned rounder than this. */
783 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
784
785 /* The best alignment to use in cases where we have a choice. */
786 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
787
788 /* Make strings word-aligned so strcpy from constants will be faster. */
789 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
790 ((TREE_CODE (EXP) == STRING_CST \
791 && (ALIGN) < FASTEST_ALIGNMENT) \
792 ? FASTEST_ALIGNMENT : (ALIGN))
793
794 /* get_mode_alignment assumes complex values are always held in multiple
795 registers, but that is not the case on the SH; CQImode and CHImode are
796 held in a single integer register. SH5 also holds CSImode and SCmode
797 values in integer registers. This is relevant for argument passing on
798 SHcompact as we use a stack temp in order to pass CSImode by reference. */
799 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
800 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
801 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
802 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
803 : (unsigned) ALIGN)
804
805 /* Make arrays of chars word-aligned for the same reasons. */
806 #define DATA_ALIGNMENT(TYPE, ALIGN) \
807 (TREE_CODE (TYPE) == ARRAY_TYPE \
808 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
809 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
810
811 /* Number of bits which any structure or union's size must be a
812 multiple of. Each structure or union's size is rounded up to a
813 multiple of this. */
814 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
815
816 /* Set this nonzero if move instructions will actually fail to work
817 when given unaligned data. */
818 #define STRICT_ALIGNMENT 1
819
820 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
821 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
822 barrier_align (LABEL_AFTER_BARRIER)
823
824 #define LOOP_ALIGN(A_LABEL) \
825 ((! optimize || TARGET_HARD_SH4 || TARGET_SMALLCODE) \
826 ? 0 : sh_loop_align (A_LABEL))
827
828 #define LABEL_ALIGN(A_LABEL) \
829 ( \
830 (PREV_INSN (A_LABEL) \
831 && GET_CODE (PREV_INSN (A_LABEL)) == INSN \
832 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
833 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
834 /* explicit alignment insn in constant tables. */ \
835 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
836 : 0)
837
838 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
839 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
840
841 /* The base two logarithm of the known minimum alignment of an insn length. */
842 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
843 (GET_CODE (A_INSN) == INSN \
844 ? 1 << TARGET_SHMEDIA \
845 : GET_CODE (A_INSN) == JUMP_INSN || GET_CODE (A_INSN) == CALL_INSN \
846 ? 1 << TARGET_SHMEDIA \
847 : CACHE_LOG)
848 \f
849 /* Standard register usage. */
850
851 /* Register allocation for the Renesas calling convention:
852
853 r0 arg return
854 r1..r3 scratch
855 r4..r7 args in
856 r8..r13 call saved
857 r14 frame pointer/call saved
858 r15 stack pointer
859 ap arg pointer (doesn't really exist, always eliminated)
860 pr subroutine return address
861 t t bit
862 mach multiply/accumulate result, high part
863 macl multiply/accumulate result, low part.
864 fpul fp/int communication register
865 rap return address pointer register
866 fr0 fp arg return
867 fr1..fr3 scratch floating point registers
868 fr4..fr11 fp args in
869 fr12..fr15 call saved floating point registers */
870
871 #define MAX_REGISTER_NAME_LENGTH 5
872 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
873
874 #define SH_REGISTER_NAMES_INITIALIZER \
875 { \
876 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
877 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
878 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
879 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
880 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
881 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
882 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
883 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
884 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
885 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
886 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
887 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
888 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
889 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
890 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
891 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
892 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
893 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
894 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
895 "rap", "sfp" \
896 }
897
898 #define REGNAMES_ARR_INDEX_1(index) \
899 (sh_register_names[index])
900 #define REGNAMES_ARR_INDEX_2(index) \
901 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
902 #define REGNAMES_ARR_INDEX_4(index) \
903 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
904 #define REGNAMES_ARR_INDEX_8(index) \
905 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
906 #define REGNAMES_ARR_INDEX_16(index) \
907 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
908 #define REGNAMES_ARR_INDEX_32(index) \
909 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
910 #define REGNAMES_ARR_INDEX_64(index) \
911 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
912
913 #define REGISTER_NAMES \
914 { \
915 REGNAMES_ARR_INDEX_64 (0), \
916 REGNAMES_ARR_INDEX_64 (64), \
917 REGNAMES_ARR_INDEX_8 (128), \
918 REGNAMES_ARR_INDEX_8 (136), \
919 REGNAMES_ARR_INDEX_8 (144), \
920 REGNAMES_ARR_INDEX_2 (152) \
921 }
922
923 #define ADDREGNAMES_SIZE 32
924 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
925 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
926 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
927
928 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
929 { \
930 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
931 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
932 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
933 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
934 }
935
936 #define ADDREGNAMES_REGNO(index) \
937 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
938 : (-1))
939
940 #define ADDREGNAMES_ARR_INDEX_1(index) \
941 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
942 #define ADDREGNAMES_ARR_INDEX_2(index) \
943 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
944 #define ADDREGNAMES_ARR_INDEX_4(index) \
945 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
946 #define ADDREGNAMES_ARR_INDEX_8(index) \
947 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
948 #define ADDREGNAMES_ARR_INDEX_16(index) \
949 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
950 #define ADDREGNAMES_ARR_INDEX_32(index) \
951 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
952
953 #define ADDITIONAL_REGISTER_NAMES \
954 { \
955 ADDREGNAMES_ARR_INDEX_32 (0) \
956 }
957
958 /* Number of actual hardware registers.
959 The hardware registers are assigned numbers for the compiler
960 from 0 to just below FIRST_PSEUDO_REGISTER.
961 All registers that the compiler knows about must be given numbers,
962 even those that are not normally considered general registers. */
963
964 /* There are many other relevant definitions in sh.md's md_constants. */
965
966 #define FIRST_GENERAL_REG R0_REG
967 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
968 #define FIRST_FP_REG DR0_REG
969 #define LAST_FP_REG (FIRST_FP_REG + \
970 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
971 #define FIRST_XD_REG XD0_REG
972 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
973 #define FIRST_TARGET_REG TR0_REG
974 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
975
976 #define GENERAL_REGISTER_P(REGNO) \
977 IN_RANGE ((REGNO), \
978 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
979 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
980
981 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
982 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
983 || ((REGNO) == FRAME_POINTER_REGNUM))
984
985 #define FP_REGISTER_P(REGNO) \
986 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
987
988 #define XD_REGISTER_P(REGNO) \
989 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
990
991 #define FP_OR_XD_REGISTER_P(REGNO) \
992 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
993
994 #define FP_ANY_REGISTER_P(REGNO) \
995 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
996
997 #define SPECIAL_REGISTER_P(REGNO) \
998 ((REGNO) == GBR_REG || (REGNO) == T_REG \
999 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
1000
1001 #define TARGET_REGISTER_P(REGNO) \
1002 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
1003
1004 #define SHMEDIA_REGISTER_P(REGNO) \
1005 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
1006 || TARGET_REGISTER_P (REGNO))
1007
1008 /* This is to be used in CONDITIONAL_REGISTER_USAGE, to mark registers
1009 that should be fixed. */
1010 #define VALID_REGISTER_P(REGNO) \
1011 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
1012 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
1013 || (REGNO) == FRAME_POINTER_REGNUM \
1014 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
1015 || (TARGET_SH2E && (REGNO) == FPUL_REG))
1016
1017 /* The mode that should be generally used to store a register by
1018 itself in the stack, or to load it back. */
1019 #define REGISTER_NATURAL_MODE(REGNO) \
1020 (FP_REGISTER_P (REGNO) ? SFmode \
1021 : XD_REGISTER_P (REGNO) ? DFmode \
1022 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
1023 ? DImode \
1024 : SImode)
1025
1026 #define FIRST_PSEUDO_REGISTER 154
1027
1028 /* Don't count soft frame pointer. */
1029 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
1030
1031 /* 1 for registers that have pervasive standard uses
1032 and are not available for the register allocator.
1033
1034 Mach register is fixed 'cause it's only 10 bits wide for SH1.
1035 It is 32 bits wide for SH2. */
1036
1037 #define FIXED_REGISTERS \
1038 { \
1039 /* Regular registers. */ \
1040 0, 0, 0, 0, 0, 0, 0, 0, \
1041 0, 0, 0, 0, 0, 0, 0, 1, \
1042 /* r16 is reserved, r18 is the former pr. */ \
1043 1, 0, 0, 0, 0, 0, 0, 0, \
1044 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
1045 /* r26 is a global variable data pointer; r27 is for constants. */ \
1046 1, 1, 1, 1, 0, 0, 0, 0, \
1047 0, 0, 0, 0, 0, 0, 0, 0, \
1048 0, 0, 0, 0, 0, 0, 0, 0, \
1049 0, 0, 0, 0, 0, 0, 0, 0, \
1050 0, 0, 0, 0, 0, 0, 0, 1, \
1051 /* FP registers. */ \
1052 0, 0, 0, 0, 0, 0, 0, 0, \
1053 0, 0, 0, 0, 0, 0, 0, 0, \
1054 0, 0, 0, 0, 0, 0, 0, 0, \
1055 0, 0, 0, 0, 0, 0, 0, 0, \
1056 0, 0, 0, 0, 0, 0, 0, 0, \
1057 0, 0, 0, 0, 0, 0, 0, 0, \
1058 0, 0, 0, 0, 0, 0, 0, 0, \
1059 0, 0, 0, 0, 0, 0, 0, 0, \
1060 /* Branch target registers. */ \
1061 0, 0, 0, 0, 0, 0, 0, 0, \
1062 /* XD registers. */ \
1063 0, 0, 0, 0, 0, 0, 0, 0, \
1064 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1065 1, 1, 1, 1, 1, 1, 0, 1, \
1066 /*"rap", "sfp" */ \
1067 1, 1, \
1068 }
1069
1070 /* 1 for registers not available across function calls.
1071 These must include the FIXED_REGISTERS and also any
1072 registers that can be used without being saved.
1073 The latter must include the registers where values are returned
1074 and the register where structure-value addresses are passed.
1075 Aside from that, you can include as many other registers as you like. */
1076
1077 #define CALL_USED_REGISTERS \
1078 { \
1079 /* Regular registers. */ \
1080 1, 1, 1, 1, 1, 1, 1, 1, \
1081 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
1082 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
1083 across SH5 function calls. */ \
1084 0, 0, 0, 0, 0, 0, 0, 1, \
1085 1, 1, 1, 1, 1, 1, 1, 1, \
1086 1, 1, 1, 1, 0, 0, 0, 0, \
1087 0, 0, 0, 0, 1, 1, 1, 1, \
1088 1, 1, 1, 1, 0, 0, 0, 0, \
1089 0, 0, 0, 0, 0, 0, 0, 0, \
1090 0, 0, 0, 0, 1, 1, 1, 1, \
1091 /* FP registers. */ \
1092 1, 1, 1, 1, 1, 1, 1, 1, \
1093 1, 1, 1, 1, 0, 0, 0, 0, \
1094 1, 1, 1, 1, 1, 1, 1, 1, \
1095 1, 1, 1, 1, 1, 1, 1, 1, \
1096 1, 1, 1, 1, 0, 0, 0, 0, \
1097 0, 0, 0, 0, 0, 0, 0, 0, \
1098 0, 0, 0, 0, 0, 0, 0, 0, \
1099 0, 0, 0, 0, 0, 0, 0, 0, \
1100 /* Branch target registers. */ \
1101 1, 1, 1, 1, 1, 0, 0, 0, \
1102 /* XD registers. */ \
1103 1, 1, 1, 1, 1, 1, 0, 0, \
1104 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
1105 1, 1, 1, 1, 1, 1, 1, 1, \
1106 /*"rap", "sfp" */ \
1107 1, 1, \
1108 }
1109
1110 /* CONDITIONAL_REGISTER_USAGE might want to make a register call-used, yet
1111 fixed, like PIC_OFFSET_TABLE_REGNUM. */
1112 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
1113
1114 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
1115 across SHcompact function calls. We can't tell whether a called
1116 function is SHmedia or SHcompact, so we assume it may be when
1117 compiling SHmedia code with the 32-bit ABI, since that's the only
1118 ABI that can be linked with SHcompact code. */
1119 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
1120 (TARGET_SHMEDIA32 \
1121 && GET_MODE_SIZE (MODE) > 4 \
1122 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
1123 && (REGNO) <= FIRST_GENERAL_REG + 15) \
1124 || TARGET_REGISTER_P (REGNO) \
1125 || (REGNO) == PR_MEDIA_REG))
1126
1127 /* Return number of consecutive hard regs needed starting at reg REGNO
1128 to hold something of mode MODE.
1129 This is ordinarily the length in words of a value of mode MODE
1130 but can be less for certain modes in special long registers.
1131
1132 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
1133
1134 #define HARD_REGNO_NREGS(REGNO, MODE) \
1135 (XD_REGISTER_P (REGNO) \
1136 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
1137 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
1138 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
1139 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1140
1141 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1142 We can allow any mode in any general register. The special registers
1143 only allow SImode. Don't allow any mode in the PR. */
1144
1145 /* We cannot hold DCmode values in the XD registers because alter_reg
1146 handles subregs of them incorrectly. We could work around this by
1147 spacing the XD registers like the DR registers, but this would require
1148 additional memory in every compilation to hold larger register vectors.
1149 We could hold SFmode / SCmode values in XD registers, but that
1150 would require a tertiary reload when reloading from / to memory,
1151 and a secondary reload to reload from / to general regs; that
1152 seems to be a loosing proposition. */
1153 /* We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
1154 it won't be ferried through GP registers first. */
1155 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1156 (SPECIAL_REGISTER_P (REGNO) ? (MODE) == SImode \
1157 : (REGNO) == FPUL_REG ? (MODE) == SImode || (MODE) == SFmode \
1158 : FP_REGISTER_P (REGNO) && (MODE) == SFmode \
1159 ? 1 \
1160 : (MODE) == V2SFmode \
1161 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 2 == 0) \
1162 || GENERAL_REGISTER_P (REGNO)) \
1163 : (MODE) == V4SFmode \
1164 ? ((FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 4 == 0) \
1165 || GENERAL_REGISTER_P (REGNO)) \
1166 : (MODE) == V16SFmode \
1167 ? (TARGET_SHMEDIA \
1168 ? (FP_REGISTER_P (REGNO) && ((REGNO) - FIRST_FP_REG) % 16 == 0) \
1169 : (REGNO) == FIRST_XD_REG) \
1170 : FP_REGISTER_P (REGNO) \
1171 ? ((MODE) == SFmode || (MODE) == SImode \
1172 || ((TARGET_SH2E || TARGET_SHMEDIA) && (MODE) == SCmode) \
1173 || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) || (MODE) == DCmode \
1174 || (TARGET_SHMEDIA && ((MODE) == DFmode || (MODE) == DImode \
1175 || (MODE) == V2SFmode || (MODE) == TImode))) \
1176 && (((REGNO) - FIRST_FP_REG) & 1) == 0) \
1177 || ((TARGET_SH4 || TARGET_SHMEDIA) \
1178 && (MODE) == TImode \
1179 && (((REGNO) - FIRST_FP_REG) & 3) == 0)) \
1180 : XD_REGISTER_P (REGNO) \
1181 ? (MODE) == DFmode \
1182 : TARGET_REGISTER_P (REGNO) \
1183 ? ((MODE) == DImode || (MODE) == SImode || (MODE) == PDImode) \
1184 : (REGNO) == PR_REG ? (MODE) == SImode \
1185 : (REGNO) == FPSCR_REG ? (MODE) == PSImode \
1186 : 1)
1187
1188 /* Value is 1 if it is a good idea to tie two pseudo registers
1189 when one has mode MODE1 and one has mode MODE2.
1190 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1191 for any hard reg, then this must be 0 for correct output.
1192 That's the case for xd registers: we don't hold SFmode values in
1193 them, so we can't tie an SFmode pseudos with one in another
1194 floating-point mode. */
1195
1196 #define MODES_TIEABLE_P(MODE1, MODE2) \
1197 ((MODE1) == (MODE2) \
1198 || (TARGET_SHMEDIA \
1199 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
1200 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
1201 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
1202 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
1203 && (GET_MODE_SIZE (MODE2) <= 4)) \
1204 : ((MODE1) != SFmode && (MODE2) != SFmode))))
1205
1206 /* A C expression that is nonzero if hard register NEW_REG can be
1207 considered for use as a rename register for OLD_REG register */
1208
1209 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1210 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
1211
1212 /* Specify the registers used for certain standard purposes.
1213 The values of these macros are register numbers. */
1214
1215 /* Define this if the program counter is overloaded on a register. */
1216 /* #define PC_REGNUM 15*/
1217
1218 /* Register to use for pushing function arguments. */
1219 #define STACK_POINTER_REGNUM SP_REG
1220
1221 /* Base register for access to local variables of the function. */
1222 #define HARD_FRAME_POINTER_REGNUM FP_REG
1223
1224 /* Base register for access to local variables of the function. */
1225 #define FRAME_POINTER_REGNUM 153
1226
1227 /* Fake register that holds the address on the stack of the
1228 current function's return address. */
1229 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
1230
1231 /* Register to hold the addressing base for position independent
1232 code access to data items. */
1233 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
1234
1235 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
1236
1237 /* Value should be nonzero if functions must have frame pointers.
1238 Zero means the frame pointer need not be set up (and parms may be accessed
1239 via the stack pointer) in functions that seem suitable. */
1240
1241 #define FRAME_POINTER_REQUIRED 0
1242
1243 /* Definitions for register eliminations.
1244
1245 We have three registers that can be eliminated on the SH. First, the
1246 frame pointer register can often be eliminated in favor of the stack
1247 pointer register. Secondly, the argument pointer register can always be
1248 eliminated; it is replaced with either the stack or frame pointer.
1249 Third, there is the return address pointer, which can also be replaced
1250 with either the stack or the frame pointer. */
1251
1252 /* This is an array of structures. Each structure initializes one pair
1253 of eliminable registers. The "from" register number is given first,
1254 followed by "to". Eliminations of the same "from" register are listed
1255 in order of preference. */
1256
1257 /* If you add any registers here that are not actually hard registers,
1258 and that have any alternative of elimination that doesn't always
1259 apply, you need to amend calc_live_regs to exclude it, because
1260 reload spills all eliminable registers where it sees an
1261 can_eliminate == 0 entry, thus making them 'live' .
1262 If you add any hard registers that can be eliminated in different
1263 ways, you have to patch reload to spill them only when all alternatives
1264 of elimination fail. */
1265
1266 #define ELIMINABLE_REGS \
1267 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1268 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1269 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1270 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1271 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1272 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1273 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
1274
1275 /* Given FROM and TO register numbers, say whether this elimination
1276 is allowed. */
1277 #define CAN_ELIMINATE(FROM, TO) \
1278 (!((FROM) == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED))
1279
1280 /* Define the offset between two registers, one to be eliminated, and the other
1281 its replacement, at the start of a routine. */
1282
1283 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1284 OFFSET = initial_elimination_offset ((FROM), (TO))
1285
1286 /* Base register for access to arguments of the function. */
1287 #define ARG_POINTER_REGNUM AP_REG
1288
1289 /* Register in which the static-chain is passed to a function. */
1290 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
1291
1292 /* Don't default to pcc-struct-return, because we have already specified
1293 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
1294 target hook. */
1295
1296 #define DEFAULT_PCC_STRUCT_RETURN 0
1297
1298 #define SHMEDIA_REGS_STACK_ADJUST() \
1299 (TARGET_SHCOMPACT && current_function_has_nonlocal_label \
1300 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
1301 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
1302 : 0)
1303
1304 \f
1305 /* Define the classes of registers for register constraints in the
1306 machine description. Also define ranges of constants.
1307
1308 One of the classes must always be named ALL_REGS and include all hard regs.
1309 If there is more than one class, another class must be named NO_REGS
1310 and contain no registers.
1311
1312 The name GENERAL_REGS must be the name of a class (or an alias for
1313 another name such as ALL_REGS). This is the class of registers
1314 that is allowed by "g" or "r" in a register constraint.
1315 Also, registers outside this class are allocated only when
1316 instructions express preferences for them.
1317
1318 The classes must be numbered in nondecreasing order; that is,
1319 a larger-numbered class must never be contained completely
1320 in a smaller-numbered class.
1321
1322 For any two classes, it is very desirable that there be another
1323 class that represents their union. */
1324
1325 /* The SH has two sorts of general registers, R0 and the rest. R0 can
1326 be used as the destination of some of the arithmetic ops. There are
1327 also some special purpose registers; the T bit register, the
1328 Procedure Return Register and the Multiply Accumulate Registers. */
1329 /* Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1330 reg_class_subunion. We don't want to have an actual union class
1331 of these, because it would only be used when both classes are calculated
1332 to give the same cost, but there is only one FPUL register.
1333 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1334 applying to the actual instruction alternative considered. E.g., the
1335 y/r alternative of movsi_ie is considered to have no more cost that
1336 the r/r alternative, which is patently untrue. */
1337
1338 enum reg_class
1339 {
1340 NO_REGS,
1341 R0_REGS,
1342 PR_REGS,
1343 T_REGS,
1344 MAC_REGS,
1345 FPUL_REGS,
1346 SIBCALL_REGS,
1347 GENERAL_REGS,
1348 FP0_REGS,
1349 FP_REGS,
1350 DF_HI_REGS,
1351 DF_REGS,
1352 FPSCR_REGS,
1353 GENERAL_FP_REGS,
1354 GENERAL_DF_REGS,
1355 TARGET_REGS,
1356 ALL_REGS,
1357 LIM_REG_CLASSES
1358 };
1359
1360 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1361
1362 /* Give names of register classes as strings for dump file. */
1363 #define REG_CLASS_NAMES \
1364 { \
1365 "NO_REGS", \
1366 "R0_REGS", \
1367 "PR_REGS", \
1368 "T_REGS", \
1369 "MAC_REGS", \
1370 "FPUL_REGS", \
1371 "SIBCALL_REGS", \
1372 "GENERAL_REGS", \
1373 "FP0_REGS", \
1374 "FP_REGS", \
1375 "DF_HI_REGS", \
1376 "DF_REGS", \
1377 "FPSCR_REGS", \
1378 "GENERAL_FP_REGS", \
1379 "GENERAL_DF_REGS", \
1380 "TARGET_REGS", \
1381 "ALL_REGS", \
1382 }
1383
1384 /* Define which registers fit in which classes.
1385 This is an initializer for a vector of HARD_REG_SET
1386 of length N_REG_CLASSES. */
1387
1388 #define REG_CLASS_CONTENTS \
1389 { \
1390 /* NO_REGS: */ \
1391 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1392 /* R0_REGS: */ \
1393 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1394 /* PR_REGS: */ \
1395 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1396 /* T_REGS: */ \
1397 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1398 /* MAC_REGS: */ \
1399 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1400 /* FPUL_REGS: */ \
1401 { 0x00000000, 0x00000000, 0x00000000, 0x00000001, 0x00400000 }, \
1402 /* SIBCALL_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1403 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1404 /* GENERAL_REGS: */ \
1405 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1406 /* FP0_REGS: */ \
1407 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1408 /* FP_REGS: */ \
1409 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1410 /* DF_HI_REGS: Initialized in CONDITIONAL_REGISTER_USAGE. */ \
1411 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1412 /* DF_REGS: */ \
1413 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1414 /* FPSCR_REGS: */ \
1415 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1416 /* GENERAL_FP_REGS: */ \
1417 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1418 /* GENERAL_DF_REGS: */ \
1419 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1420 /* TARGET_REGS: */ \
1421 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1422 /* ALL_REGS: */ \
1423 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1424 }
1425
1426 /* The same information, inverted:
1427 Return the class number of the smallest class containing
1428 reg number REGNO. This could be a conditional expression
1429 or could index an array. */
1430
1431 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1432 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1433
1434 /* When defined, the compiler allows registers explicitly used in the
1435 rtl to be used as spill registers but prevents the compiler from
1436 extending the lifetime of these registers. */
1437
1438 #define SMALL_REGISTER_CLASSES (! TARGET_SHMEDIA)
1439
1440 /* The order in which register should be allocated. */
1441 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1442 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1443 spilled or used otherwise, we better have the FP_REGS allocated first. */
1444 #define REG_ALLOC_ORDER \
1445 {/* Caller-saved FPRs */ \
1446 65, 66, 67, 68, 69, 70, 71, 64, \
1447 72, 73, 74, 75, 80, 81, 82, 83, \
1448 84, 85, 86, 87, 88, 89, 90, 91, \
1449 92, 93, 94, 95, 96, 97, 98, 99, \
1450 /* Callee-saved FPRs */ \
1451 76, 77, 78, 79,100,101,102,103, \
1452 104,105,106,107,108,109,110,111, \
1453 112,113,114,115,116,117,118,119, \
1454 120,121,122,123,124,125,126,127, \
1455 136,137,138,139,140,141,142,143, \
1456 /* FPSCR */ 151, \
1457 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1458 1, 2, 3, 7, 6, 5, 4, 0, \
1459 8, 9, 17, 19, 20, 21, 22, 23, \
1460 36, 37, 38, 39, 40, 41, 42, 43, \
1461 60, 61, 62, \
1462 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1463 10, 11, 12, 13, 14, 18, \
1464 /* SH5 callee-saved GPRs */ \
1465 28, 29, 30, 31, 32, 33, 34, 35, \
1466 44, 45, 46, 47, 48, 49, 50, 51, \
1467 52, 53, 54, 55, 56, 57, 58, 59, \
1468 /* FPUL */ 150, \
1469 /* SH5 branch target registers */ \
1470 128,129,130,131,132,133,134,135, \
1471 /* Fixed registers */ \
1472 15, 16, 24, 25, 26, 27, 63,144, \
1473 145,146,147,148,149,152,153 }
1474
1475 /* The class value for index registers, and the one for base regs. */
1476 #define INDEX_REG_CLASS \
1477 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1478 #define BASE_REG_CLASS GENERAL_REGS
1479
1480 /* Get reg_class from a letter such as appears in the machine
1481 description. */
1482 extern enum reg_class reg_class_from_letter[];
1483
1484 /* We might use 'Rxx' constraints in the future for exotic reg classes.*/
1485 #define REG_CLASS_FROM_CONSTRAINT(C, STR) \
1486 (ISLOWER (C) ? reg_class_from_letter[(C)-'a'] : NO_REGS )
1487 \f
1488 /* Overview of uppercase letter constraints:
1489 A: Addresses (constraint len == 3)
1490 Ac4: sh4 cache operations
1491 Ac5: sh5 cache operations
1492 Bxx: miscellaneous constraints
1493 Bsc: SCRATCH - for the scratch register in movsi_ie in the
1494 fldi0 / fldi0 cases
1495 C: Constants other than only CONST_INT (constraint len == 3)
1496 C16: 16 bit constant, literal or symbolic
1497 Csy: label or symbol
1498 Cpg: non-explicit constants that can be directly loaded into a general
1499 purpose register in PIC code. like 's' except we don't allow
1500 PIC_DIRECT_ADDR_P
1501 IJKLMNOP: CONT_INT constants
1502 Ixx: signed xx bit
1503 J16: 0xffffffff00000000 | 0x00000000ffffffff
1504 Kxx: unsigned xx bit
1505 M: 1
1506 N: 0
1507 P27: 1 | 2 | 8 | 16
1508 Q: pc relative load operand
1509 Rxx: reserved for exotic register classes.
1510 S: extra memory (storage) constraints (constraint len == 3)
1511 Sua: unaligned memory operations
1512 W: vector
1513 Z: zero in any mode
1514
1515 unused CONST_INT constraint letters: LO
1516 unused EXTRA_CONSTRAINT letters: D T U Y */
1517
1518 #define CONSTRAINT_LEN(C,STR) \
1519 (((C) == 'A' || (C) == 'B' || (C) == 'C' \
1520 || (C) == 'I' || (C) == 'J' || (C) == 'K' || (C) == 'P' \
1521 || (C) == 'R' || (C) == 'S') \
1522 ? 3 : DEFAULT_CONSTRAINT_LEN ((C), (STR)))
1523
1524 /* The letters I, J, K, L and M in a register constraint string
1525 can be used to stand for particular ranges of immediate operands.
1526 This macro defines what the ranges are.
1527 C is the letter, and VALUE is a constant value.
1528 Return 1 if VALUE is in the range specified by C.
1529 I08: arithmetic operand -127..128, as used in add, sub, etc
1530 I16: arithmetic operand -32768..32767, as used in SHmedia movi and shori
1531 P27: shift operand 1,2,8 or 16
1532 K08: logical operand 0..255, as used in and, or, etc.
1533 M: constant 1
1534 N: constant 0
1535 I06: arithmetic operand -32..31, as used in SHmedia beqi, bnei and xori
1536 I10: arithmetic operand -512..511, as used in SHmedia andi, ori
1537 */
1538
1539 #define CONST_OK_FOR_I06(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32 \
1540 && ((HOST_WIDE_INT)(VALUE)) <= 31)
1541 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1542 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1543 #define CONST_OK_FOR_I10(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -512 \
1544 && ((HOST_WIDE_INT)(VALUE)) <= 511)
1545 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1546 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1547 #define CONST_OK_FOR_I20(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -524288 \
1548 && ((HOST_WIDE_INT)(VALUE)) <= 524287 \
1549 && TARGET_SH2A)
1550 #define CONST_OK_FOR_I(VALUE, STR) \
1551 ((STR)[1] == '0' && (STR)[2] == '6' ? CONST_OK_FOR_I06 (VALUE) \
1552 : (STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_I08 (VALUE) \
1553 : (STR)[1] == '1' && (STR)[2] == '0' ? CONST_OK_FOR_I10 (VALUE) \
1554 : (STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_I16 (VALUE) \
1555 : (STR)[1] == '2' && (STR)[2] == '0' ? CONST_OK_FOR_I20 (VALUE) \
1556 : 0)
1557
1558 #define CONST_OK_FOR_J16(VALUE) \
1559 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1560 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1561 #define CONST_OK_FOR_J(VALUE, STR) \
1562 ((STR)[1] == '1' && (STR)[2] == '6' ? CONST_OK_FOR_J16 (VALUE) \
1563 : 0)
1564
1565 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1566 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1567 #define CONST_OK_FOR_K(VALUE, STR) \
1568 ((STR)[1] == '0' && (STR)[2] == '8' ? CONST_OK_FOR_K08 (VALUE) \
1569 : 0)
1570 #define CONST_OK_FOR_P27(VALUE) \
1571 ((VALUE)==1||(VALUE)==2||(VALUE)==8||(VALUE)==16)
1572 #define CONST_OK_FOR_P(VALUE, STR) \
1573 ((STR)[1] == '2' && (STR)[2] == '7' ? CONST_OK_FOR_P27 (VALUE) \
1574 : 0)
1575 #define CONST_OK_FOR_M(VALUE) ((VALUE)==1)
1576 #define CONST_OK_FOR_N(VALUE) ((VALUE)==0)
1577 #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
1578 ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) \
1579 : (C) == 'J' ? CONST_OK_FOR_J ((VALUE), (STR)) \
1580 : (C) == 'K' ? CONST_OK_FOR_K ((VALUE), (STR)) \
1581 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \
1582 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \
1583 : (C) == 'P' ? CONST_OK_FOR_P ((VALUE), (STR)) \
1584 : 0)
1585
1586 /* Similar, but for floating constants, and defining letters G and H.
1587 Here VALUE is the CONST_DOUBLE rtx itself. */
1588
1589 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1590 ((C) == 'G' ? (fp_zero_operand (VALUE) && fldi_ok ()) \
1591 : (C) == 'H' ? (fp_one_operand (VALUE) && fldi_ok ()) \
1592 : (C) == 'F')
1593
1594 /* Given an rtx X being reloaded into a reg required to be
1595 in class CLASS, return the class of reg to actually use.
1596 In general this is just CLASS; but on some machines
1597 in some cases it is preferable to use a more restrictive class. */
1598
1599 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1600 ((CLASS) == NO_REGS && TARGET_SHMEDIA \
1601 && (GET_CODE (X) == CONST_DOUBLE \
1602 || GET_CODE (X) == SYMBOL_REF \
1603 || PIC_DIRECT_ADDR_P (X)) \
1604 ? GENERAL_REGS \
1605 : (CLASS)) \
1606
1607 #if 0
1608 #define SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,ELSE) \
1609 ((((REGCLASS_HAS_FP_REG (CLASS) \
1610 && (GET_CODE (X) == REG \
1611 && (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1612 || (FP_REGISTER_P (REGNO (X)) && (MODE) == SImode \
1613 && TARGET_FMOVD)))) \
1614 || (REGCLASS_HAS_GENERAL_REG (CLASS) \
1615 && GET_CODE (X) == REG \
1616 && FP_REGISTER_P (REGNO (X)))) \
1617 && ! TARGET_SHMEDIA \
1618 && ((MODE) == SFmode || (MODE) == SImode)) \
1619 ? FPUL_REGS \
1620 : (((CLASS) == FPUL_REGS \
1621 || (REGCLASS_HAS_FP_REG (CLASS) \
1622 && ! TARGET_SHMEDIA && MODE == SImode)) \
1623 && (GET_CODE (X) == MEM \
1624 || (GET_CODE (X) == REG \
1625 && (REGNO (X) >= FIRST_PSEUDO_REGISTER \
1626 || REGNO (X) == T_REG \
1627 || system_reg_operand (X, VOIDmode))))) \
1628 ? GENERAL_REGS \
1629 : (((CLASS) == TARGET_REGS \
1630 || (TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS)) \
1631 && !EXTRA_CONSTRAINT_Csy (X) \
1632 && (GET_CODE (X) != REG || ! GENERAL_REGISTER_P (REGNO (X)))) \
1633 ? GENERAL_REGS \
1634 : (((CLASS) == MAC_REGS || (CLASS) == PR_REGS) \
1635 && GET_CODE (X) == REG && ! GENERAL_REGISTER_P (REGNO (X)) \
1636 && (CLASS) != REGNO_REG_CLASS (REGNO (X))) \
1637 ? GENERAL_REGS \
1638 : ((CLASS) != GENERAL_REGS && GET_CODE (X) == REG \
1639 && TARGET_REGISTER_P (REGNO (X))) \
1640 ? GENERAL_REGS : (ELSE))
1641
1642 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,X) \
1643 SECONDARY_INOUT_RELOAD_CLASS(CLASS,MODE,X,NO_REGS)
1644
1645 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
1646 ((REGCLASS_HAS_FP_REG (CLASS) \
1647 && ! TARGET_SHMEDIA \
1648 && immediate_operand ((X), (MODE)) \
1649 && ! ((fp_zero_operand (X) || fp_one_operand (X)) \
1650 && (MODE) == SFmode && fldi_ok ())) \
1651 ? R0_REGS \
1652 : ((CLASS) == FPUL_REGS \
1653 && ((GET_CODE (X) == REG \
1654 && (REGNO (X) == MACL_REG || REGNO (X) == MACH_REG \
1655 || REGNO (X) == T_REG)) \
1656 || GET_CODE (X) == PLUS)) \
1657 ? GENERAL_REGS \
1658 : (CLASS) == FPUL_REGS && immediate_operand ((X), (MODE)) \
1659 ? (GET_CODE (X) == CONST_INT && CONST_OK_FOR_I08 (INTVAL (X)) \
1660 ? GENERAL_REGS \
1661 : R0_REGS) \
1662 : ((CLASS) == FPSCR_REGS \
1663 && ((GET_CODE (X) == REG && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1664 || (GET_CODE (X) == MEM && GET_CODE (XEXP ((X), 0)) == PLUS)))\
1665 ? GENERAL_REGS \
1666 : (REGCLASS_HAS_FP_REG (CLASS) \
1667 && TARGET_SHMEDIA \
1668 && immediate_operand ((X), (MODE)) \
1669 && (X) != CONST0_RTX (GET_MODE (X)) \
1670 && GET_MODE (X) != V4SFmode) \
1671 ? GENERAL_REGS \
1672 : (((MODE) == QImode || (MODE) == HImode) \
1673 && TARGET_SHMEDIA && inqhi_operand ((X), (MODE))) \
1674 ? GENERAL_REGS \
1675 : (TARGET_SHMEDIA && (CLASS) == GENERAL_REGS \
1676 && (GET_CODE (X) == LABEL_REF || PIC_DIRECT_ADDR_P (X))) \
1677 ? TARGET_REGS \
1678 : SECONDARY_INOUT_RELOAD_CLASS((CLASS),(MODE),(X), NO_REGS))
1679 #else
1680 #define HAVE_SECONDARY_RELOADS
1681 #endif
1682
1683 /* Return the maximum number of consecutive registers
1684 needed to represent mode MODE in a register of class CLASS.
1685
1686 If TARGET_SHMEDIA, we need two FP registers per word.
1687 Otherwise we will need at most one register per word. */
1688 #define CLASS_MAX_NREGS(CLASS, MODE) \
1689 (TARGET_SHMEDIA \
1690 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1691 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1692 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1693
1694 /* If defined, gives a class of registers that cannot be used as the
1695 operand of a SUBREG that changes the mode of the object illegally. */
1696 /* ??? We need to renumber the internal numbers for the frnn registers
1697 when in little endian in order to allow mode size changes. */
1698
1699 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1700 sh_cannot_change_mode_class (FROM, TO, CLASS)
1701 \f
1702 /* Stack layout; function entry, exit and calling. */
1703
1704 /* Define the number of registers that can hold parameters.
1705 These macros are used only in other macro definitions below. */
1706
1707 #define NPARM_REGS(MODE) \
1708 (TARGET_FPU_ANY && (MODE) == SFmode \
1709 ? (TARGET_SH5 ? 12 : 8) \
1710 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1711 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1712 ? (TARGET_SH5 ? 12 : 8) \
1713 : (TARGET_SH5 ? 8 : 4))
1714
1715 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1716 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1717
1718 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1719 #define FIRST_FP_RET_REG FIRST_FP_REG
1720
1721 /* Define this if pushing a word on the stack
1722 makes the stack pointer a smaller address. */
1723 #define STACK_GROWS_DOWNWARD
1724
1725 /* Define this macro to nonzero if the addresses of local variable slots
1726 are at negative offsets from the frame pointer. */
1727 #define FRAME_GROWS_DOWNWARD 1
1728
1729 /* Offset from the frame pointer to the first local variable slot to
1730 be allocated. */
1731 #define STARTING_FRAME_OFFSET 0
1732
1733 /* If we generate an insn to push BYTES bytes,
1734 this says how many the stack pointer really advances by. */
1735 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1736 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1737 do correct alignment. */
1738 #if 0
1739 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1740 #endif
1741
1742 /* Offset of first parameter from the argument pointer register value. */
1743 #define FIRST_PARM_OFFSET(FNDECL) 0
1744
1745 /* Value is the number of byte of arguments automatically
1746 popped when returning from a subroutine call.
1747 FUNDECL is the declaration node of the function (as a tree),
1748 FUNTYPE is the data type of the function (as a tree),
1749 or for a library call it is an identifier node for the subroutine name.
1750 SIZE is the number of bytes of arguments passed on the stack.
1751
1752 On the SH, the caller does not pop any of its arguments that were passed
1753 on the stack. */
1754 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1755
1756 /* Value is the number of bytes of arguments automatically popped when
1757 calling a subroutine.
1758 CUM is the accumulated argument list.
1759
1760 On SHcompact, the call trampoline pops arguments off the stack. */
1761 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1762
1763 /* Some subroutine macros specific to this machine. */
1764
1765 #define BASE_RETURN_VALUE_REG(MODE) \
1766 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1767 ? FIRST_FP_RET_REG \
1768 : TARGET_FPU_ANY && (MODE) == SCmode \
1769 ? FIRST_FP_RET_REG \
1770 : (TARGET_FPU_DOUBLE \
1771 && ((MODE) == DFmode || (MODE) == SFmode \
1772 || (MODE) == DCmode || (MODE) == SCmode )) \
1773 ? FIRST_FP_RET_REG \
1774 : FIRST_RET_REG)
1775
1776 #define BASE_ARG_REG(MODE) \
1777 ((TARGET_SH2E && ((MODE) == SFmode)) \
1778 ? FIRST_FP_PARM_REG \
1779 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1780 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1781 ? FIRST_FP_PARM_REG \
1782 : FIRST_PARM_REG)
1783
1784 /* Define how to find the value returned by a function.
1785 VALTYPE is the data type of the value (as a tree).
1786 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1787 otherwise, FUNC is 0.
1788 For the SH, this is like LIBCALL_VALUE, except that we must change the
1789 mode like PROMOTE_MODE does.
1790 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
1791 tested here has to be kept in sync with the one in explow.c:promote_mode. */
1792
1793 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1794 gen_rtx_REG ( \
1795 ((GET_MODE_CLASS (TYPE_MODE (VALTYPE)) == MODE_INT \
1796 && GET_MODE_SIZE (TYPE_MODE (VALTYPE)) < 4 \
1797 && (TREE_CODE (VALTYPE) == INTEGER_TYPE \
1798 || TREE_CODE (VALTYPE) == ENUMERAL_TYPE \
1799 || TREE_CODE (VALTYPE) == BOOLEAN_TYPE \
1800 || TREE_CODE (VALTYPE) == CHAR_TYPE \
1801 || TREE_CODE (VALTYPE) == REAL_TYPE \
1802 || TREE_CODE (VALTYPE) == OFFSET_TYPE)) \
1803 && sh_promote_prototypes (VALTYPE) \
1804 ? (TARGET_SHMEDIA64 ? DImode : SImode) : TYPE_MODE (VALTYPE)), \
1805 BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1806
1807 /* Define how to find the value returned by a library function
1808 assuming the value has mode MODE. */
1809 #define LIBCALL_VALUE(MODE) \
1810 gen_rtx_REG ((MODE), BASE_RETURN_VALUE_REG (MODE));
1811
1812 /* 1 if N is a possible register number for a function value. */
1813 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1814 ((REGNO) == FIRST_RET_REG || (TARGET_SH2E && (REGNO) == FIRST_FP_RET_REG) \
1815 || (TARGET_SHMEDIA_FPU && (REGNO) == FIRST_FP_RET_REG))
1816
1817 /* 1 if N is a possible register number for function argument passing. */
1818 /* ??? There are some callers that pass REGNO as int, and others that pass
1819 it as unsigned. We get warnings unless we do casts everywhere. */
1820 #define FUNCTION_ARG_REGNO_P(REGNO) \
1821 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1822 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1823 || (TARGET_FPU_ANY \
1824 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1825 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1826 + NPARM_REGS (SFmode))))
1827 \f
1828 /* Define a data type for recording info about an argument list
1829 during the scan of that argument list. This data type should
1830 hold all necessary information about the function itself
1831 and about the args processed so far, enough to enable macros
1832 such as FUNCTION_ARG to determine where the next arg should go.
1833
1834 On SH, this is a single integer, which is a number of words
1835 of arguments scanned so far (including the invisible argument,
1836 if any, which holds the structure-value-address).
1837 Thus NARGREGS or more means all following args should go on the stack. */
1838
1839 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1840 struct sh_args {
1841 int arg_count[2];
1842 int force_mem;
1843 /* Nonzero if a prototype is available for the function. */
1844 int prototype_p;
1845 /* The number of an odd floating-point register, that should be used
1846 for the next argument of type float. */
1847 int free_single_fp_reg;
1848 /* Whether we're processing an outgoing function call. */
1849 int outgoing;
1850 /* The number of general-purpose registers that should have been
1851 used to pass partial arguments, that are passed totally on the
1852 stack. On SHcompact, a call trampoline will pop them off the
1853 stack before calling the actual function, and, if the called
1854 function is implemented in SHcompact mode, the incoming arguments
1855 decoder will push such arguments back onto the stack. For
1856 incoming arguments, STACK_REGS also takes into account other
1857 arguments passed by reference, that the decoder will also push
1858 onto the stack. */
1859 int stack_regs;
1860 /* The number of general-purpose registers that should have been
1861 used to pass arguments, if the arguments didn't have to be passed
1862 by reference. */
1863 int byref_regs;
1864 /* Set as by shcompact_byref if the current argument is to be passed
1865 by reference. */
1866 int byref;
1867
1868 /* call_cookie is a bitmask used by call expanders, as well as
1869 function prologue and epilogues, to allow SHcompact to comply
1870 with the SH5 32-bit ABI, that requires 64-bit registers to be
1871 used even though only the lower 32-bit half is visible in
1872 SHcompact mode. The strategy is to call SHmedia trampolines.
1873
1874 The alternatives for each of the argument-passing registers are
1875 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1876 contents from the address in it; (d) add 8 to it, storing the
1877 result in the next register, then (c); (e) copy it from some
1878 floating-point register,
1879
1880 Regarding copies from floating-point registers, r2 may only be
1881 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1882 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1883 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1884 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1885 dr10.
1886
1887 The bit mask is structured as follows:
1888
1889 - 1 bit to tell whether to set up a return trampoline.
1890
1891 - 3 bits to count the number consecutive registers to pop off the
1892 stack.
1893
1894 - 4 bits for each of r9, r8, r7 and r6.
1895
1896 - 3 bits for each of r5, r4, r3 and r2.
1897
1898 - 3 bits set to 0 (the most significant ones)
1899
1900 3 2 1 0
1901 1098 7654 3210 9876 5432 1098 7654 3210
1902 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1903 2223 3344 4555 6666 7777 8888 9999 SSS-
1904
1905 - If F is set, the register must be copied from an FP register,
1906 whose number is encoded in the remaining bits.
1907
1908 - Else, if L is set, the register must be loaded from the address
1909 contained in it. If the P bit is *not* set, the address of the
1910 following dword should be computed first, and stored in the
1911 following register.
1912
1913 - Else, if P is set, the register alone should be popped off the
1914 stack.
1915
1916 - After all this processing, the number of registers represented
1917 in SSS will be popped off the stack. This is an optimization
1918 for pushing/popping consecutive registers, typically used for
1919 varargs and large arguments partially passed in registers.
1920
1921 - If T is set, a return trampoline will be set up for 64-bit
1922 return values to be split into 2 32-bit registers. */
1923 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1924 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1925 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1926 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1927 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1928 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1929 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1930 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1931 #define CALL_COOKIE_INT_REG(REG, VAL) \
1932 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1933 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1934 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1935 long call_cookie;
1936
1937 /* This is set to nonzero when the call in question must use the Renesas ABI,
1938 even without the -mrenesas option. */
1939 int renesas_abi;
1940 };
1941
1942 #define CUMULATIVE_ARGS struct sh_args
1943
1944 #define GET_SH_ARG_CLASS(MODE) \
1945 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1946 ? SH_ARG_FLOAT \
1947 /* There's no mention of complex float types in the SH5 ABI, so we
1948 should presumably handle them as aggregate types. */ \
1949 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1950 ? SH_ARG_INT \
1951 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1952 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1953 ? SH_ARG_FLOAT : SH_ARG_INT)
1954
1955 #define ROUND_ADVANCE(SIZE) \
1956 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1957
1958 /* Round a register number up to a proper boundary for an arg of mode
1959 MODE.
1960
1961 The SH doesn't care about double alignment, so we only
1962 round doubles to even regs when asked to explicitly. */
1963
1964 #define ROUND_REG(CUM, MODE) \
1965 (((TARGET_ALIGN_DOUBLE \
1966 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && ((MODE) == DFmode || (MODE) == DCmode) \
1967 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE)))\
1968 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1969 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1970 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1971 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1972
1973 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1974 for a call to a function whose data type is FNTYPE.
1975 For a library call, FNTYPE is 0.
1976
1977 On SH, the offset always starts at 0: the first parm reg is always
1978 the same reg for a given argument class.
1979
1980 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1981
1982 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1983 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL), (N_NAMED_ARGS), VOIDmode)
1984
1985 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1986 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1987
1988 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1989 sh_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
1990 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1991 sh_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1992
1993 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1994 This macro is only used in this file. */
1995
1996 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1997 (((TYPE) == 0 \
1998 || (! TREE_ADDRESSABLE ((tree)(TYPE)) \
1999 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
2000 || ! (AGGREGATE_TYPE_P (TYPE) \
2001 || (!TARGET_FPU_ANY \
2002 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
2003 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
2004 && ! (CUM).force_mem \
2005 && (TARGET_SH2E \
2006 ? ((MODE) == BLKmode \
2007 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
2008 + int_size_in_bytes (TYPE)) \
2009 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
2010 : ((ROUND_REG((CUM), (MODE)) \
2011 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
2012 <= NPARM_REGS (MODE))) \
2013 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
2014
2015 /* By accident we got stuck with passing SCmode on SH4 little endian
2016 in two registers that are nominally successive - which is different from
2017 two single SFmode values, where we take endianness translation into
2018 account. That does not work at all if an odd number of registers is
2019 already in use, so that got fixed, but library functions are still more
2020 likely to use complex numbers without mixing them with SFmode arguments
2021 (which in C would have to be structures), so for the sake of ABI
2022 compatibility the way SCmode values are passed when an even number of
2023 FP registers is in use remains different from a pair of SFmode values for
2024 now.
2025 I.e.:
2026 foo (double); a: fr5,fr4
2027 foo (float a, float b); a: fr5 b: fr4
2028 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
2029 this should be the other way round...
2030 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
2031 #define FUNCTION_ARG_SCmode_WART 1
2032
2033 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
2034 register in SHcompact mode, it must be padded in the most
2035 significant end. This means that passing it by reference wouldn't
2036 pad properly on a big-endian machine. In this particular case, we
2037 pass this argument on the stack, in a way that the call trampoline
2038 will load its value into the appropriate register. */
2039 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
2040 ((MODE) == BLKmode \
2041 && TARGET_SHCOMPACT \
2042 && ! TARGET_LITTLE_ENDIAN \
2043 && int_size_in_bytes (TYPE) > 4 \
2044 && int_size_in_bytes (TYPE) < 8)
2045
2046 /* Minimum alignment for an argument to be passed by callee-copy
2047 reference. We need such arguments to be aligned to 8 byte
2048 boundaries, because they'll be loaded using quad loads. */
2049 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
2050
2051 /* The SH5 ABI requires floating-point arguments to be passed to
2052 functions without a prototype in both an FP register and a regular
2053 register or the stack. When passing the argument in both FP and
2054 general-purpose registers, list the FP register first. */
2055 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
2056 (gen_rtx_PARALLEL \
2057 ((MODE), \
2058 gen_rtvec (2, \
2059 gen_rtx_EXPR_LIST \
2060 (VOIDmode, \
2061 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2062 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2063 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
2064 : NULL_RTX), \
2065 const0_rtx), \
2066 gen_rtx_EXPR_LIST \
2067 (VOIDmode, \
2068 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2069 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
2070 + (CUM).arg_count[(int) SH_ARG_INT]) \
2071 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
2072 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
2073 const0_rtx))))
2074
2075 /* The SH5 ABI requires regular registers or stack slots to be
2076 reserved for floating-point arguments. Registers are taken care of
2077 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
2078 Unfortunately, there's no way to just reserve a stack slot, so
2079 we'll end up needlessly storing a copy of the argument in the
2080 stack. For incoming arguments, however, the PARALLEL will be
2081 optimized to the register-only form, and the value in the stack
2082 slot won't be used at all. */
2083 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
2084 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
2085 ? gen_rtx_REG ((MODE), (REG)) \
2086 : gen_rtx_PARALLEL ((MODE), \
2087 gen_rtvec (2, \
2088 gen_rtx_EXPR_LIST \
2089 (VOIDmode, NULL_RTX, \
2090 const0_rtx), \
2091 gen_rtx_EXPR_LIST \
2092 (VOIDmode, gen_rtx_REG ((MODE), \
2093 (REG)), \
2094 const0_rtx))))
2095
2096 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2097 (TARGET_SH5 \
2098 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
2099 || (MODE) == DCmode) \
2100 && ((CUM).arg_count[(int) SH_ARG_INT] \
2101 + (int_size_in_bytes (TYPE) + 7) / 8) > NPARM_REGS (SImode))
2102
2103 /* Perform any needed actions needed for a function that is receiving a
2104 variable number of arguments. */
2105
2106 /* Implement `va_start' for varargs and stdarg. */
2107 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2108 sh_va_start (valist, nextarg)
2109
2110 /* Call the function profiler with a given profile label.
2111 We use two .aligns, so as to make sure that both the .long is aligned
2112 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
2113 from the trapa instruction. */
2114
2115 #define FUNCTION_PROFILER(STREAM,LABELNO) \
2116 { \
2117 if (TARGET_SHMEDIA) \
2118 { \
2119 fprintf((STREAM), "\tmovi\t33,r0\n"); \
2120 fprintf((STREAM), "\ttrapa\tr0\n"); \
2121 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2122 } \
2123 else \
2124 { \
2125 fprintf((STREAM), "\t.align\t2\n"); \
2126 fprintf((STREAM), "\ttrapa\t#33\n"); \
2127 fprintf((STREAM), "\t.align\t2\n"); \
2128 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
2129 } \
2130 }
2131
2132 /* Define this macro if the code for function profiling should come
2133 before the function prologue. Normally, the profiling code comes
2134 after. */
2135
2136 #define PROFILE_BEFORE_PROLOGUE
2137
2138 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2139 the stack pointer does not matter. The value is tested only in
2140 functions that have frame pointers.
2141 No definition is equivalent to always zero. */
2142
2143 #define EXIT_IGNORE_STACK 1
2144
2145 /*
2146 On the SH, the trampoline looks like
2147 2 0002 D202 mov.l l2,r2
2148 1 0000 D301 mov.l l1,r3
2149 3 0004 422B jmp @r2
2150 4 0006 0009 nop
2151 5 0008 00000000 l1: .long area
2152 6 000c 00000000 l2: .long function */
2153
2154 /* Length in units of the trampoline for entering a nested function. */
2155 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
2156
2157 /* Alignment required for a trampoline in bits . */
2158 #define TRAMPOLINE_ALIGNMENT \
2159 ((CACHE_LOG < 3 || (TARGET_SMALLCODE && ! TARGET_HARVARD)) ? 32 \
2160 : TARGET_SHMEDIA ? 256 : 64)
2161
2162 /* Emit RTL insns to initialize the variable parts of a trampoline.
2163 FNADDR is an RTX for the address of the function's pure code.
2164 CXT is an RTX for the static chain value for the function. */
2165
2166 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
2167 sh_initialize_trampoline ((TRAMP), (FNADDR), (CXT))
2168
2169 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
2170
2171 #define TRAMPOLINE_ADJUST_ADDRESS(TRAMP) do \
2172 { \
2173 if (TARGET_SHMEDIA) \
2174 (TRAMP) = expand_simple_binop (Pmode, PLUS, (TRAMP), const1_rtx, \
2175 gen_reg_rtx (Pmode), 0, \
2176 OPTAB_LIB_WIDEN); \
2177 } while (0)
2178
2179 /* A C expression whose value is RTL representing the value of the return
2180 address for the frame COUNT steps up from the current frame.
2181 FRAMEADDR is already the frame pointer of the COUNT frame, so we
2182 can ignore COUNT. */
2183
2184 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2185 (((COUNT) == 0) ? sh_get_pr_initial_val () : (rtx) 0)
2186
2187 /* A C expression whose value is RTL representing the location of the
2188 incoming return address at the beginning of any function, before the
2189 prologue. This RTL is either a REG, indicating that the return
2190 value is saved in REG, or a MEM representing a location in
2191 the stack. */
2192 #define INCOMING_RETURN_ADDR_RTX \
2193 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
2194 \f
2195 /* Addressing modes, and classification of registers for them. */
2196 #define HAVE_POST_INCREMENT TARGET_SH1
2197 #define HAVE_PRE_DECREMENT TARGET_SH1
2198
2199 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
2200 ? 0 : TARGET_SH1)
2201 #define USE_LOAD_PRE_DECREMENT(mode) 0
2202 #define USE_STORE_POST_INCREMENT(mode) 0
2203 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
2204 ? 0 : TARGET_SH1)
2205
2206 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2207 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2208 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2209
2210 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
2211 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
2212 < (TARGET_SMALLCODE ? 2 : ((ALIGN >= 32) ? 16 : 2)))
2213
2214 /* Macros to check register numbers against specific register classes. */
2215
2216 /* These assume that REGNO is a hard or pseudo reg number.
2217 They give nonzero only if REGNO is a hard reg of the suitable class
2218 or a pseudo reg currently allocated to a suitable hard reg.
2219 Since they use reg_renumber, they are safe only once reg_renumber
2220 has been allocated, which happens in local-alloc.c. */
2221
2222 #define REGNO_OK_FOR_BASE_P(REGNO) \
2223 (GENERAL_OR_AP_REGISTER_P (REGNO) \
2224 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
2225 #define REGNO_OK_FOR_INDEX_P(REGNO) \
2226 (TARGET_SHMEDIA \
2227 ? (GENERAL_REGISTER_P (REGNO) \
2228 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
2229 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
2230
2231 /* Maximum number of registers that can appear in a valid memory
2232 address. */
2233
2234 #define MAX_REGS_PER_ADDRESS 2
2235
2236 /* Recognize any constant value that is a valid address. */
2237
2238 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
2239
2240 /* Nonzero if the constant value X is a legitimate general operand. */
2241
2242 #define LEGITIMATE_CONSTANT_P(X) \
2243 (TARGET_SHMEDIA \
2244 ? ((GET_MODE (X) != DFmode \
2245 && GET_MODE_CLASS (GET_MODE (X)) != MODE_VECTOR_FLOAT) \
2246 || (X) == CONST0_RTX (GET_MODE (X)) \
2247 || ! TARGET_SHMEDIA_FPU \
2248 || TARGET_SHMEDIA64) \
2249 : (GET_CODE (X) != CONST_DOUBLE \
2250 || GET_MODE (X) == DFmode || GET_MODE (X) == SFmode \
2251 || (TARGET_SH2E && (fp_zero_operand (X) || fp_one_operand (X)))))
2252
2253 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2254 and check its validity for a certain class.
2255 We have two alternate definitions for each of them.
2256 The usual definition accepts all pseudo regs; the other rejects
2257 them unless they have been allocated suitable hard regs.
2258 The symbol REG_OK_STRICT causes the latter definition to be used. */
2259
2260 #ifndef REG_OK_STRICT
2261
2262 /* Nonzero if X is a hard reg that can be used as a base reg
2263 or if it is a pseudo reg. */
2264 #define REG_OK_FOR_BASE_P(X) \
2265 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2266
2267 /* Nonzero if X is a hard reg that can be used as an index
2268 or if it is a pseudo reg. */
2269 #define REG_OK_FOR_INDEX_P(X) \
2270 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2271 : REGNO (X) == R0_REG) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2272
2273 /* Nonzero if X/OFFSET is a hard reg that can be used as an index
2274 or if X is a pseudo reg. */
2275 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2276 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
2277 : REGNO (X) == R0_REG && OFFSET == 0) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
2278
2279 #else
2280
2281 /* Nonzero if X is a hard reg that can be used as a base reg. */
2282 #define REG_OK_FOR_BASE_P(X) \
2283 REGNO_OK_FOR_BASE_P (REGNO (X))
2284
2285 /* Nonzero if X is a hard reg that can be used as an index. */
2286 #define REG_OK_FOR_INDEX_P(X) \
2287 REGNO_OK_FOR_INDEX_P (REGNO (X))
2288
2289 /* Nonzero if X/OFFSET is a hard reg that can be used as an index. */
2290 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET) \
2291 (REGNO_OK_FOR_INDEX_P (REGNO (X)) && (OFFSET) == 0)
2292
2293 #endif
2294
2295 /* The 'Q' constraint is a pc relative load operand. */
2296 #define EXTRA_CONSTRAINT_Q(OP) \
2297 (GET_CODE (OP) == MEM \
2298 && ((GET_CODE (XEXP ((OP), 0)) == LABEL_REF) \
2299 || (GET_CODE (XEXP ((OP), 0)) == CONST \
2300 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == PLUS \
2301 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == LABEL_REF \
2302 && GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 1)) == CONST_INT)))
2303
2304 /* Extra address constraints. */
2305 #define EXTRA_CONSTRAINT_A(OP, STR) 0
2306
2307 /* Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber
2308 operand is not SCRATCH (i.e. REG) then R0 is probably being
2309 used, hence mova is being used, hence do not select this pattern */
2310 #define EXTRA_CONSTRAINT_Bsc(OP) (GET_CODE(OP) == SCRATCH)
2311 #define EXTRA_CONSTRAINT_B(OP, STR) \
2312 ((STR)[1] == 's' && (STR)[2] == 'c' ? EXTRA_CONSTRAINT_Bsc (OP) \
2313 : 0)
2314
2315 /* The `C16' constraint is a 16-bit constant, literal or symbolic. */
2316 #define EXTRA_CONSTRAINT_C16(OP) \
2317 (GET_CODE (OP) == CONST \
2318 && GET_CODE (XEXP ((OP), 0)) == SIGN_EXTEND \
2319 && (GET_MODE (XEXP ((OP), 0)) == DImode \
2320 || GET_MODE (XEXP ((OP), 0)) == SImode) \
2321 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == TRUNCATE \
2322 && GET_MODE (XEXP (XEXP ((OP), 0), 0)) == HImode \
2323 && (MOVI_SHORI_BASE_OPERAND_P (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) \
2324 || (GET_CODE (XEXP (XEXP (XEXP ((OP), 0), 0), 0)) == ASHIFTRT \
2325 && (MOVI_SHORI_BASE_OPERAND_P \
2326 (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), 0))) \
2327 && GET_CODE (XEXP (XEXP (XEXP (XEXP ((OP), 0), 0), 0), \
2328 1)) == CONST_INT)))
2329
2330 /* Check whether OP is a datalabel unspec. */
2331 #define DATALABEL_REF_NO_CONST_P(OP) \
2332 (GET_CODE (OP) == UNSPEC \
2333 && XINT ((OP), 1) == UNSPEC_DATALABEL \
2334 && XVECLEN ((OP), 0) == 1 \
2335 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
2336
2337 #define GOT_ENTRY_P(OP) \
2338 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2339 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
2340
2341 #define GOTPLT_ENTRY_P(OP) \
2342 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2343 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
2344
2345 #define UNSPEC_GOTOFF_P(OP) \
2346 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
2347
2348 #define GOTOFF_P(OP) \
2349 (GET_CODE (OP) == CONST \
2350 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
2351 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
2352 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
2353 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT)))
2354
2355 #define PIC_ADDR_P(OP) \
2356 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
2357 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
2358
2359 #define PIC_OFFSET_P(OP) \
2360 (PIC_ADDR_P (OP) \
2361 && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) == MINUS \
2362 && reg_mentioned_p (pc_rtx, XEXP (XVECEXP (XEXP ((OP), 0), 0, 0), 1)))
2363
2364 #define PIC_DIRECT_ADDR_P(OP) \
2365 (PIC_ADDR_P (OP) && GET_CODE (XVECEXP (XEXP ((OP), 0), 0, 0)) != MINUS)
2366
2367 #define NON_PIC_REFERENCE_P(OP) \
2368 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
2369 || (GET_CODE (OP) == CONST \
2370 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
2371 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
2372 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
2373 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
2374 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
2375 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
2376 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
2377 && GET_CODE (XEXP (XEXP ((OP), 0), 1)) == CONST_INT))
2378
2379 #define PIC_REFERENCE_P(OP) \
2380 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
2381 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
2382
2383 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
2384 (flag_pic \
2385 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
2386 || PIC_OFFSET_P (OP)) \
2387 : NON_PIC_REFERENCE_P (OP))
2388
2389 /* The `Csy' constraint is a label or a symbol. */
2390 #define EXTRA_CONSTRAINT_Csy(OP) \
2391 (NON_PIC_REFERENCE_P (OP) || PIC_DIRECT_ADDR_P (OP))
2392
2393 /* A zero in any shape or form. */
2394 #define EXTRA_CONSTRAINT_Z(OP) \
2395 ((OP) == CONST0_RTX (GET_MODE (OP)))
2396
2397 /* Any vector constant we can handle. */
2398 #define EXTRA_CONSTRAINT_W(OP) \
2399 (GET_CODE (OP) == CONST_VECTOR \
2400 && (sh_rep_vec ((OP), VOIDmode) \
2401 || (HOST_BITS_PER_WIDE_INT >= 64 \
2402 ? sh_const_vec ((OP), VOIDmode) \
2403 : sh_1el_vec ((OP), VOIDmode))))
2404
2405 /* A non-explicit constant that can be loaded directly into a general purpose
2406 register. This is like 's' except we don't allow PIC_DIRECT_ADDR_P. */
2407 #define EXTRA_CONSTRAINT_Cpg(OP) \
2408 (CONSTANT_P (OP) \
2409 && GET_CODE (OP) != CONST_INT \
2410 && GET_CODE (OP) != CONST_DOUBLE \
2411 && (!flag_pic \
2412 || (LEGITIMATE_PIC_OPERAND_P (OP) \
2413 && (! PIC_ADDR_P (OP) || PIC_OFFSET_P (OP)) \
2414 && GET_CODE (OP) != LABEL_REF)))
2415 #define EXTRA_CONSTRAINT_C(OP, STR) \
2416 ((STR)[1] == '1' && (STR)[2] == '6' ? EXTRA_CONSTRAINT_C16 (OP) \
2417 : (STR)[1] == 's' && (STR)[2] == 'y' ? EXTRA_CONSTRAINT_Csy (OP) \
2418 : (STR)[1] == 'p' && (STR)[2] == 'g' ? EXTRA_CONSTRAINT_Cpg (OP) \
2419 : 0)
2420
2421 #define EXTRA_MEMORY_CONSTRAINT(C,STR) ((C) == 'S')
2422 #define EXTRA_CONSTRAINT_Sr0(OP) \
2423 (memory_operand((OP), GET_MODE (OP)) \
2424 && ! refers_to_regno_p (R0_REG, R0_REG + 1, OP, (rtx *)0))
2425 #define EXTRA_CONSTRAINT_Sua(OP) \
2426 (memory_operand((OP), GET_MODE (OP)) \
2427 && GET_CODE (XEXP (OP, 0)) != PLUS)
2428 #define EXTRA_CONSTRAINT_S(OP, STR) \
2429 ((STR)[1] == 'r' && (STR)[2] == '0' ? EXTRA_CONSTRAINT_Sr0 (OP) \
2430 : (STR)[1] == 'u' && (STR)[2] == 'a' ? EXTRA_CONSTRAINT_Sua (OP) \
2431 : 0)
2432
2433 #define EXTRA_CONSTRAINT_STR(OP, C, STR) \
2434 ((C) == 'Q' ? EXTRA_CONSTRAINT_Q (OP) \
2435 : (C) == 'A' ? EXTRA_CONSTRAINT_A ((OP), (STR)) \
2436 : (C) == 'B' ? EXTRA_CONSTRAINT_B ((OP), (STR)) \
2437 : (C) == 'C' ? EXTRA_CONSTRAINT_C ((OP), (STR)) \
2438 : (C) == 'S' ? EXTRA_CONSTRAINT_S ((OP), (STR)) \
2439 : (C) == 'W' ? EXTRA_CONSTRAINT_W (OP) \
2440 : (C) == 'Z' ? EXTRA_CONSTRAINT_Z (OP) \
2441 : 0)
2442 \f
2443 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
2444 that is a valid memory address for an instruction.
2445 The MODE argument is the machine mode for the MEM expression
2446 that wants to use this address. */
2447
2448 #define MODE_DISP_OK_4(X,MODE) \
2449 (GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2450 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode))
2451
2452 #define MODE_DISP_OK_8(X,MODE) \
2453 ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2454 && ! (INTVAL(X) & 3) && ! (TARGET_SH4 && (MODE) == DFmode))
2455
2456 #undef MODE_DISP_OK_4
2457 #define MODE_DISP_OK_4(X,MODE) \
2458 ((GET_MODE_SIZE (MODE) == 4 && (unsigned) INTVAL (X) < 64 \
2459 && ! (INTVAL (X) & 3) && ! (TARGET_SH2E && (MODE) == SFmode)) \
2460 || ((GET_MODE_SIZE(MODE)==4) && ((unsigned)INTVAL(X)<16383) \
2461 && ! (INTVAL(X) & 3) && TARGET_SH2A))
2462
2463 #undef MODE_DISP_OK_8
2464 #define MODE_DISP_OK_8(X,MODE) \
2465 (((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<60) \
2466 && ! (INTVAL(X) & 3) && ! ((TARGET_SH4 || TARGET_SH2A) && (MODE) == DFmode)) \
2467 || ((GET_MODE_SIZE(MODE)==8) && ((unsigned)INTVAL(X)<8192) \
2468 && ! (INTVAL(X) & (TARGET_SH2A_DOUBLE ? 7 : 3)) && (TARGET_SH2A && (MODE) == DFmode)))
2469
2470 #define BASE_REGISTER_RTX_P(X) \
2471 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
2472 || (GET_CODE (X) == SUBREG \
2473 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2474 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2475 && GET_CODE (SUBREG_REG (X)) == REG \
2476 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
2477
2478 /* Since this must be r0, which is a single register class, we must check
2479 SUBREGs more carefully, to be sure that we don't accept one that extends
2480 outside the class. */
2481 #define INDEX_REGISTER_RTX_P(X) \
2482 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
2483 || (GET_CODE (X) == SUBREG \
2484 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
2485 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
2486 && GET_CODE (SUBREG_REG (X)) == REG \
2487 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X))))
2488
2489 /* Jump to LABEL if X is a valid address RTX. This must also take
2490 REG_OK_STRICT into account when deciding about valid registers, but it uses
2491 the above macros so we are in luck.
2492
2493 Allow REG
2494 REG+disp
2495 REG+r0
2496 REG++
2497 --REG */
2498
2499 /* ??? The SH2e does not have the REG+disp addressing mode when loading values
2500 into the FRx registers. We implement this by setting the maximum offset
2501 to zero when the value is SFmode. This also restricts loading of SFmode
2502 values into the integer registers, but that can't be helped. */
2503
2504 /* The SH allows a displacement in a QI or HI amode, but only when the
2505 other operand is R0. GCC doesn't handle this very well, so we forgo
2506 all of that.
2507
2508 A legitimate index for a QI or HI is 0, SI can be any number 0..63,
2509 DI can be any number 0..60. */
2510
2511 #define GO_IF_LEGITIMATE_INDEX(MODE, OP, LABEL) \
2512 do { \
2513 if (GET_CODE (OP) == CONST_INT) \
2514 { \
2515 if (TARGET_SHMEDIA) \
2516 { \
2517 int MODE_SIZE; \
2518 /* Check if this the address of an unaligned load / store. */\
2519 if ((MODE) == VOIDmode) \
2520 { \
2521 if (CONST_OK_FOR_I06 (INTVAL (OP))) \
2522 goto LABEL; \
2523 break; \
2524 } \
2525 MODE_SIZE = GET_MODE_SIZE (MODE); \
2526 if (! (INTVAL (OP) & (MODE_SIZE - 1)) \
2527 && INTVAL (OP) >= -512 * MODE_SIZE \
2528 && INTVAL (OP) < 512 * MODE_SIZE) \
2529 goto LABEL; \
2530 else \
2531 break; \
2532 } \
2533 if (MODE_DISP_OK_4 ((OP), (MODE))) goto LABEL; \
2534 if (MODE_DISP_OK_8 ((OP), (MODE))) goto LABEL; \
2535 } \
2536 } while(0)
2537
2538 #define ALLOW_INDEXED_ADDRESS \
2539 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
2540
2541 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2542 { \
2543 if (BASE_REGISTER_RTX_P (X)) \
2544 goto LABEL; \
2545 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2546 && ! TARGET_SHMEDIA \
2547 && BASE_REGISTER_RTX_P (XEXP ((X), 0))) \
2548 goto LABEL; \
2549 else if (GET_CODE (X) == PLUS \
2550 && ((MODE) != PSImode || reload_completed)) \
2551 { \
2552 rtx xop0 = XEXP ((X), 0); \
2553 rtx xop1 = XEXP ((X), 1); \
2554 if (GET_MODE_SIZE (MODE) <= 8 && BASE_REGISTER_RTX_P (xop0)) \
2555 GO_IF_LEGITIMATE_INDEX ((MODE), xop1, LABEL); \
2556 if ((ALLOW_INDEXED_ADDRESS || GET_MODE (X) == DImode \
2557 || ((xop0 == stack_pointer_rtx \
2558 || xop0 == hard_frame_pointer_rtx) \
2559 && REG_P (xop1) && REGNO (xop1) == R0_REG) \
2560 || ((xop1 == stack_pointer_rtx \
2561 || xop1 == hard_frame_pointer_rtx) \
2562 && REG_P (xop0) && REGNO (xop0) == R0_REG)) \
2563 && ((!TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 4) \
2564 || (TARGET_SHMEDIA && GET_MODE_SIZE (MODE) <= 8) \
2565 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
2566 && TARGET_FMOVD && MODE == DFmode))) \
2567 { \
2568 if (BASE_REGISTER_RTX_P (xop1) && INDEX_REGISTER_RTX_P (xop0))\
2569 goto LABEL; \
2570 if (INDEX_REGISTER_RTX_P (xop1) && BASE_REGISTER_RTX_P (xop0))\
2571 goto LABEL; \
2572 } \
2573 } \
2574 }
2575 \f
2576 /* Try machine-dependent ways of modifying an illegitimate address
2577 to be legitimate. If we find one, return the new, valid address.
2578 This macro is used in only one place: `memory_address' in explow.c.
2579
2580 OLDX is the address as it was before break_out_memory_refs was called.
2581 In some cases it is useful to look at this to decide what needs to be done.
2582
2583 MODE and WIN are passed so that this macro can use
2584 GO_IF_LEGITIMATE_ADDRESS.
2585
2586 It is always safe for this macro to do nothing. It exists to recognize
2587 opportunities to optimize the output.
2588
2589 For the SH, if X is almost suitable for indexing, but the offset is
2590 out of range, convert it into a normal form so that cse has a chance
2591 of reducing the number of address registers used. */
2592
2593 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2594 { \
2595 if (flag_pic) \
2596 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2597 if (GET_CODE (X) == PLUS \
2598 && (GET_MODE_SIZE (MODE) == 4 \
2599 || GET_MODE_SIZE (MODE) == 8) \
2600 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
2601 && BASE_REGISTER_RTX_P (XEXP ((X), 0)) \
2602 && ! TARGET_SHMEDIA \
2603 && ! ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && (MODE) == DFmode) \
2604 && ! (TARGET_SH2E && (MODE) == SFmode)) \
2605 { \
2606 rtx index_rtx = XEXP ((X), 1); \
2607 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2608 rtx sum; \
2609 \
2610 GO_IF_LEGITIMATE_INDEX ((MODE), index_rtx, WIN); \
2611 /* On rare occasions, we might get an unaligned pointer \
2612 that is indexed in a way to give an aligned address. \
2613 Therefore, keep the lower two bits in offset_base. */ \
2614 /* Instead of offset_base 128..131 use 124..127, so that \
2615 simple add suffices. */ \
2616 if (offset > 127) \
2617 { \
2618 offset_base = ((offset + 4) & ~60) - 4; \
2619 } \
2620 else \
2621 offset_base = offset & ~60; \
2622 /* Sometimes the normal form does not suit DImode. We \
2623 could avoid that by using smaller ranges, but that \
2624 would give less optimized code when SImode is \
2625 prevalent. */ \
2626 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2627 { \
2628 sum = expand_binop (Pmode, add_optab, XEXP ((X), 0), \
2629 GEN_INT (offset_base), NULL_RTX, 0, \
2630 OPTAB_LIB_WIDEN); \
2631 \
2632 (X) = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base)); \
2633 goto WIN; \
2634 } \
2635 } \
2636 }
2637
2638 /* A C compound statement that attempts to replace X, which is an address
2639 that needs reloading, with a valid memory address for an operand of
2640 mode MODE. WIN is a C statement label elsewhere in the code.
2641
2642 Like for LEGITIMIZE_ADDRESS, for the SH we try to get a normal form
2643 of the address. That will allow inheritance of the address reloads. */
2644
2645 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2646 { \
2647 if (GET_CODE (X) == PLUS \
2648 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2649 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2650 && BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2651 && ! TARGET_SHMEDIA \
2652 && ! (TARGET_SH4 && (MODE) == DFmode) \
2653 && ! ((MODE) == PSImode && (TYPE) == RELOAD_FOR_INPUT_ADDRESS) \
2654 && (ALLOW_INDEXED_ADDRESS \
2655 || XEXP ((X), 0) == stack_pointer_rtx \
2656 || XEXP ((X), 0) == hard_frame_pointer_rtx)) \
2657 { \
2658 rtx index_rtx = XEXP (X, 1); \
2659 HOST_WIDE_INT offset = INTVAL (index_rtx), offset_base; \
2660 rtx sum; \
2661 \
2662 if (TARGET_SH2A && (MODE) == DFmode && (offset & 0x7)) \
2663 { \
2664 push_reload (X, NULL_RTX, &X, NULL, \
2665 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2666 (TYPE)); \
2667 goto WIN; \
2668 } \
2669 if (TARGET_SH2E && MODE == SFmode) \
2670 { \
2671 X = copy_rtx (X); \
2672 push_reload (index_rtx, NULL_RTX, &XEXP (X, 1), NULL, \
2673 R0_REGS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2674 (TYPE)); \
2675 goto WIN; \
2676 } \
2677 /* Instead of offset_base 128..131 use 124..127, so that \
2678 simple add suffices. */ \
2679 if (offset > 127) \
2680 { \
2681 offset_base = ((offset + 4) & ~60) - 4; \
2682 } \
2683 else \
2684 offset_base = offset & ~60; \
2685 /* Sometimes the normal form does not suit DImode. We \
2686 could avoid that by using smaller ranges, but that \
2687 would give less optimized code when SImode is \
2688 prevalent. */ \
2689 if (GET_MODE_SIZE (MODE) + offset - offset_base <= 64) \
2690 { \
2691 sum = gen_rtx_PLUS (Pmode, XEXP (X, 0), \
2692 GEN_INT (offset_base)); \
2693 X = gen_rtx_PLUS (Pmode, sum, GEN_INT (offset - offset_base));\
2694 push_reload (sum, NULL_RTX, &XEXP (X, 0), NULL, \
2695 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), \
2696 (TYPE)); \
2697 goto WIN; \
2698 } \
2699 } \
2700 /* We must re-recognize what we created before. */ \
2701 else if (GET_CODE (X) == PLUS \
2702 && (GET_MODE_SIZE (MODE) == 4 || GET_MODE_SIZE (MODE) == 8) \
2703 && GET_CODE (XEXP (X, 0)) == PLUS \
2704 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \
2705 && BASE_REGISTER_RTX_P (XEXP (XEXP (X, 0), 0)) \
2706 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2707 && ! TARGET_SHMEDIA \
2708 && ! (TARGET_SH2E && MODE == SFmode)) \
2709 { \
2710 /* Because this address is so complex, we know it must have \
2711 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus, \
2712 it is already unshared, and needs no further unsharing. */ \
2713 push_reload (XEXP ((X), 0), NULL_RTX, &XEXP ((X), 0), NULL, \
2714 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, (OPNUM), (TYPE));\
2715 goto WIN; \
2716 } \
2717 }
2718
2719 /* Go to LABEL if ADDR (a legitimate address expression)
2720 has an effect that depends on the machine mode it is used for.
2721
2722 ??? Strictly speaking, we should also include all indexed addressing,
2723 because the index scale factor is the length of the operand.
2724 However, the impact of GO_IF_MODE_DEPENDENT_ADDRESS would be to
2725 high if we did that. So we rely on reload to fix things up. */
2726
2727 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2728 { \
2729 if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_INC) \
2730 goto LABEL; \
2731 }
2732 \f
2733 /* Specify the machine mode that this machine uses
2734 for the index in the tablejump instruction. */
2735 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
2736
2737 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
2738 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
2739 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
2740 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
2741 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
2742 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
2743 : SImode)
2744
2745 /* Define as C expression which evaluates to nonzero if the tablejump
2746 instruction expects the table to contain offsets from the address of the
2747 table.
2748 Do not define this if the table should contain absolute addresses. */
2749 #define CASE_VECTOR_PC_RELATIVE 1
2750
2751 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
2752 #define FLOAT_TYPE_SIZE 32
2753
2754 /* Since the SH2e has only `float' support, it is desirable to make all
2755 floating point types equivalent to `float'. */
2756 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE) ? 32 : 64)
2757
2758 /* 'char' is signed by default. */
2759 #define DEFAULT_SIGNED_CHAR 1
2760
2761 /* The type of size_t unsigned int. */
2762 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
2763
2764 #undef PTRDIFF_TYPE
2765 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
2766
2767 #define WCHAR_TYPE "short unsigned int"
2768 #define WCHAR_TYPE_SIZE 16
2769
2770 #define SH_ELF_WCHAR_TYPE "long int"
2771
2772 /* Max number of bytes we can move from memory to memory
2773 in one reasonably fast instruction. */
2774 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
2775
2776 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
2777 MOVE_MAX is not a compile-time constant. */
2778 #define MAX_MOVE_MAX 8
2779
2780 /* Max number of bytes we want move_by_pieces to be able to copy
2781 efficiently. */
2782 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
2783
2784 /* Define if operations between registers always perform the operation
2785 on the full register even if a narrower mode is specified. */
2786 #define WORD_REGISTER_OPERATIONS
2787
2788 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2789 will either zero-extend or sign-extend. The value of this macro should
2790 be the code that says which one of the two operations is implicitly
2791 done, UNKNOWN if none. */
2792 /* For SHmedia, we can truncate to QImode easier using zero extension. */
2793 /* FP registers can load SImode values, but don't implicitly sign-extend
2794 them to DImode. */
2795 #define LOAD_EXTEND_OP(MODE) \
2796 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
2797 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
2798
2799 /* Define if loading short immediate values into registers sign extends. */
2800 #define SHORT_IMMEDIATES_SIGN_EXTEND
2801
2802 /* Nonzero if access to memory by bytes is no faster than for words. */
2803 #define SLOW_BYTE_ACCESS 1
2804
2805 /* Immediate shift counts are truncated by the output routines (or was it
2806 the assembler?). Shift counts in a register are truncated by SH. Note
2807 that the native compiler puts too large (> 32) immediate shift counts
2808 into a register and shifts by the register, letting the SH decide what
2809 to do instead of doing that itself. */
2810 /* ??? The library routines in lib1funcs.asm truncate the shift count.
2811 However, the SH3 has hardware shifts that do not truncate exactly as gcc
2812 expects - the sign bit is significant - so it appears that we need to
2813 leave this zero for correct SH3 code. */
2814 #define SHIFT_COUNT_TRUNCATED (! TARGET_SH3 && ! TARGET_SH2A)
2815
2816 /* All integers have the same format so truncation is easy. */
2817 /* But SHmedia must sign-extend DImode when truncating to SImode. */
2818 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
2819 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
2820
2821 /* Define this if addresses of constant functions
2822 shouldn't be put through pseudo regs where they can be cse'd.
2823 Desirable on machines where ordinary constants are expensive
2824 but a CALL with constant address is cheap. */
2825 /*#define NO_FUNCTION_CSE 1*/
2826
2827 /* The machine modes of pointers and functions. */
2828 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
2829 #define FUNCTION_MODE Pmode
2830
2831 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
2832 are actually function calls with some special constraints on arguments
2833 and register usage.
2834
2835 These macros tell reorg that the references to arguments and
2836 register clobbers for insns of type sfunc do not appear to happen
2837 until after the millicode call. This allows reorg to put insns
2838 which set the argument registers into the delay slot of the millicode
2839 call -- thus they act more like traditional CALL_INSNs.
2840
2841 get_attr_is_sfunc will try to recognize the given insn, so make sure to
2842 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
2843 in particular. */
2844
2845 #define INSN_SETS_ARE_DELAYED(X) \
2846 ((GET_CODE (X) == INSN \
2847 && GET_CODE (PATTERN (X)) != SEQUENCE \
2848 && GET_CODE (PATTERN (X)) != USE \
2849 && GET_CODE (PATTERN (X)) != CLOBBER \
2850 && get_attr_is_sfunc (X)))
2851
2852 #define INSN_REFERENCES_ARE_DELAYED(X) \
2853 ((GET_CODE (X) == INSN \
2854 && GET_CODE (PATTERN (X)) != SEQUENCE \
2855 && GET_CODE (PATTERN (X)) != USE \
2856 && GET_CODE (PATTERN (X)) != CLOBBER \
2857 && get_attr_is_sfunc (X)))
2858
2859 \f
2860 /* Position Independent Code. */
2861
2862 /* We can't directly access anything that contains a symbol,
2863 nor can we indirect via the constant pool. */
2864 #define LEGITIMATE_PIC_OPERAND_P(X) \
2865 ((! nonpic_symbol_mentioned_p (X) \
2866 && (GET_CODE (X) != SYMBOL_REF \
2867 || ! CONSTANT_POOL_ADDRESS_P (X) \
2868 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
2869 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
2870
2871 #define SYMBOLIC_CONST_P(X) \
2872 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
2873 && nonpic_symbol_mentioned_p (X))
2874 \f
2875 /* Compute extra cost of moving data between one register class
2876 and another. */
2877
2878 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
2879 uses this information. Hence, the general register <-> floating point
2880 register information here is not used for SFmode. */
2881
2882 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
2883 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS \
2884 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
2885
2886 #define REGCLASS_HAS_FP_REG(CLASS) \
2887 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
2888 || (CLASS) == DF_REGS || (CLASS) == DF_HI_REGS)
2889
2890 #define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) \
2891 sh_register_move_cost ((MODE), (SRCCLASS), (DSTCLASS))
2892
2893 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
2894 would be so that people with slow memory systems could generate
2895 different code that does fewer memory accesses. */
2896
2897 /* A C expression for the cost of a branch instruction. A value of 1
2898 is the default; other values are interpreted relative to that.
2899 The SH1 does not have delay slots, hence we get a pipeline stall
2900 at every branch. The SH4 is superscalar, so the single delay slot
2901 is not sufficient to keep both pipelines filled. */
2902 #define BRANCH_COST (TARGET_SH5 ? 1 : ! TARGET_SH2 || TARGET_HARD_SH4 ? 2 : 1)
2903 \f
2904 /* Assembler output control. */
2905
2906 /* A C string constant describing how to begin a comment in the target
2907 assembler language. The compiler assumes that the comment will end at
2908 the end of the line. */
2909 #define ASM_COMMENT_START "!"
2910
2911 #define ASM_APP_ON ""
2912 #define ASM_APP_OFF ""
2913 #define FILE_ASM_OP "\t.file\n"
2914 #define SET_ASM_OP "\t.set\t"
2915
2916 /* How to change between sections. */
2917
2918 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 ? "\t.section\t.text..SHmedia32,\"ax\"" : "\t.text")
2919 #define DATA_SECTION_ASM_OP "\t.data"
2920
2921 #if defined CRT_BEGIN || defined CRT_END
2922 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
2923 # undef TEXT_SECTION_ASM_OP
2924 # if __SHMEDIA__ == 1 && __SH5__ == 32
2925 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
2926 # else
2927 # define TEXT_SECTION_ASM_OP "\t.text"
2928 # endif
2929 #endif
2930
2931
2932 /* If defined, a C expression whose value is a string containing the
2933 assembler operation to identify the following data as
2934 uninitialized global data. If not defined, and neither
2935 `ASM_OUTPUT_BSS' nor `ASM_OUTPUT_ALIGNED_BSS' are defined,
2936 uninitialized global data will be output in the data section if
2937 `-fno-common' is passed, otherwise `ASM_OUTPUT_COMMON' will be
2938 used. */
2939 #ifndef BSS_SECTION_ASM_OP
2940 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
2941 #endif
2942
2943 /* Like `ASM_OUTPUT_BSS' except takes the required alignment as a
2944 separate, explicit argument. If you define this macro, it is used
2945 in place of `ASM_OUTPUT_BSS', and gives you more flexibility in
2946 handling the required alignment of the variable. The alignment is
2947 specified as the number of bits.
2948
2949 Try to use function `asm_output_aligned_bss' defined in file
2950 `varasm.c' when defining this macro. */
2951 #ifndef ASM_OUTPUT_ALIGNED_BSS
2952 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
2953 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
2954 #endif
2955
2956 /* Define this so that jump tables go in same section as the current function,
2957 which could be text or it could be a user defined section. */
2958 #define JUMP_TABLES_IN_TEXT_SECTION 1
2959
2960 #undef DO_GLOBAL_CTORS_BODY
2961 #define DO_GLOBAL_CTORS_BODY \
2962 { \
2963 typedef (*pfunc)(); \
2964 extern pfunc __ctors[]; \
2965 extern pfunc __ctors_end[]; \
2966 pfunc *p; \
2967 for (p = __ctors_end; p > __ctors; ) \
2968 { \
2969 (*--p)(); \
2970 } \
2971 }
2972
2973 #undef DO_GLOBAL_DTORS_BODY
2974 #define DO_GLOBAL_DTORS_BODY \
2975 { \
2976 typedef (*pfunc)(); \
2977 extern pfunc __dtors[]; \
2978 extern pfunc __dtors_end[]; \
2979 pfunc *p; \
2980 for (p = __dtors; p < __dtors_end; p++) \
2981 { \
2982 (*p)(); \
2983 } \
2984 }
2985
2986 #define ASM_OUTPUT_REG_PUSH(file, v) \
2987 { \
2988 if (TARGET_SHMEDIA) \
2989 { \
2990 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2991 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2992 } \
2993 else \
2994 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2995 }
2996
2997 #define ASM_OUTPUT_REG_POP(file, v) \
2998 { \
2999 if (TARGET_SHMEDIA) \
3000 { \
3001 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
3002 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
3003 } \
3004 else \
3005 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
3006 }
3007
3008 /* DBX register number for a given compiler register number. */
3009 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
3010 to match gdb. */
3011 /* svr4.h undefines this macro, yet we really want to use the same numbers
3012 for coff as for elf, so we go via another macro: SH_DBX_REGISTER_NUMBER. */
3013 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
3014 register exists, so we should return -1 for invalid register numbers. */
3015 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
3016
3017 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
3018 used to use the encodings 245..260, but that doesn't make sense:
3019 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
3020 the FP registers stay the same when switching between compact and media
3021 mode. Hence, we also need to use the same dwarf frame columns.
3022 Likewise, we need to support unwind information for SHmedia registers
3023 even in compact code. */
3024 #define SH_DBX_REGISTER_NUMBER(REGNO) \
3025 (IN_RANGE ((REGNO), \
3026 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
3027 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
3028 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
3029 : ((int) (REGNO) >= FIRST_FP_REG \
3030 && ((int) (REGNO) \
3031 <= (FIRST_FP_REG + \
3032 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
3033 ? ((unsigned) (REGNO) - FIRST_FP_REG \
3034 + (TARGET_SH5 ? 77 : 25)) \
3035 : XD_REGISTER_P (REGNO) \
3036 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
3037 : TARGET_REGISTER_P (REGNO) \
3038 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
3039 : (REGNO) == PR_REG \
3040 ? (TARGET_SH5 ? 18 : 17) \
3041 : (REGNO) == PR_MEDIA_REG \
3042 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
3043 : (REGNO) == T_REG \
3044 ? (TARGET_SH5 ? 242 : 18) \
3045 : (REGNO) == GBR_REG \
3046 ? (TARGET_SH5 ? 238 : 19) \
3047 : (REGNO) == MACH_REG \
3048 ? (TARGET_SH5 ? 239 : 20) \
3049 : (REGNO) == MACL_REG \
3050 ? (TARGET_SH5 ? 240 : 21) \
3051 : (REGNO) == FPUL_REG \
3052 ? (TARGET_SH5 ? 244 : 23) \
3053 : (unsigned) -1)
3054
3055 /* This is how to output a reference to a symbol_ref. On SH5,
3056 references to non-code symbols must be preceded by `datalabel'. */
3057 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
3058 do \
3059 { \
3060 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
3061 fputs ("datalabel ", (FILE)); \
3062 assemble_name ((FILE), XSTR ((SYM), 0)); \
3063 } \
3064 while (0)
3065
3066 /* This is how to output an assembler line
3067 that says to advance the location counter
3068 to a multiple of 2**LOG bytes. */
3069
3070 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
3071 if ((LOG) != 0) \
3072 fprintf ((FILE), "\t.align %d\n", (LOG))
3073
3074 /* Globalizing directive for a label. */
3075 #define GLOBAL_ASM_OP "\t.global\t"
3076
3077 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
3078
3079 /* Output a relative address table. */
3080
3081 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
3082 switch (GET_MODE (BODY)) \
3083 { \
3084 case SImode: \
3085 if (TARGET_SH5) \
3086 { \
3087 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
3088 (VALUE), (REL)); \
3089 break; \
3090 } \
3091 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3092 break; \
3093 case HImode: \
3094 if (TARGET_SH5) \
3095 { \
3096 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
3097 (VALUE), (REL)); \
3098 break; \
3099 } \
3100 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3101 break; \
3102 case QImode: \
3103 if (TARGET_SH5) \
3104 { \
3105 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
3106 (VALUE), (REL)); \
3107 break; \
3108 } \
3109 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
3110 break; \
3111 default: \
3112 break; \
3113 }
3114
3115 /* Output an absolute table element. */
3116
3117 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
3118 if (! optimize || TARGET_BIGTABLE) \
3119 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
3120 else \
3121 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
3122
3123 \f
3124 /* A C statement to be executed just prior to the output of
3125 assembler code for INSN, to modify the extracted operands so
3126 they will be output differently.
3127
3128 Here the argument OPVEC is the vector containing the operands
3129 extracted from INSN, and NOPERANDS is the number of elements of
3130 the vector which contain meaningful data for this insn.
3131 The contents of this vector are what will be used to convert the insn
3132 template into assembler code, so you can change the assembler output
3133 by changing the contents of the vector. */
3134
3135 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3136 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
3137
3138 /* Print operand X (an rtx) in assembler syntax to file FILE.
3139 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
3140 For `%' followed by punctuation, CODE is the punctuation and X is null. */
3141
3142 #define PRINT_OPERAND(STREAM, X, CODE) print_operand ((STREAM), (X), (CODE))
3143
3144 /* Print a memory address as an operand to reference that memory location. */
3145
3146 #define PRINT_OPERAND_ADDRESS(STREAM,X) print_operand_address ((STREAM), (X))
3147
3148 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
3149 ((CHAR) == '.' || (CHAR) == '#' || (CHAR) == '@' || (CHAR) == ',' \
3150 || (CHAR) == '$' || (CHAR) == '\'' || (CHAR) == '>')
3151
3152 /* Recognize machine-specific patterns that may appear within
3153 constants. Used for PIC-specific UNSPECs. */
3154 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
3155 do \
3156 if (GET_CODE (X) == UNSPEC && XVECLEN ((X), 0) == 1) \
3157 { \
3158 switch (XINT ((X), 1)) \
3159 { \
3160 case UNSPEC_DATALABEL: \
3161 fputs ("datalabel ", (STREAM)); \
3162 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3163 break; \
3164 case UNSPEC_PIC: \
3165 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */ \
3166 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3167 break; \
3168 case UNSPEC_GOT: \
3169 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3170 fputs ("@GOT", (STREAM)); \
3171 break; \
3172 case UNSPEC_GOTOFF: \
3173 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3174 fputs ("@GOTOFF", (STREAM)); \
3175 break; \
3176 case UNSPEC_PLT: \
3177 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3178 fputs ("@PLT", (STREAM)); \
3179 break; \
3180 case UNSPEC_GOTPLT: \
3181 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3182 fputs ("@GOTPLT", (STREAM)); \
3183 break; \
3184 case UNSPEC_DTPOFF: \
3185 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3186 fputs ("@DTPOFF", (STREAM)); \
3187 break; \
3188 case UNSPEC_GOTTPOFF: \
3189 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3190 fputs ("@GOTTPOFF", (STREAM)); \
3191 break; \
3192 case UNSPEC_TPOFF: \
3193 output_addr_const ((STREAM), XVECEXP ((X), 0, 0)); \
3194 fputs ("@TPOFF", (STREAM)); \
3195 break; \
3196 case UNSPEC_CALLER: \
3197 { \
3198 char name[32]; \
3199 /* LPCS stands for Label for PIC Call Site. */ \
3200 ASM_GENERATE_INTERNAL_LABEL \
3201 (name, "LPCS", INTVAL (XVECEXP ((X), 0, 0))); \
3202 assemble_name ((STREAM), name); \
3203 } \
3204 break; \
3205 default: \
3206 goto FAIL; \
3207 } \
3208 break; \
3209 } \
3210 else \
3211 goto FAIL; \
3212 while (0)
3213
3214 \f
3215 extern struct rtx_def *sh_compare_op0;
3216 extern struct rtx_def *sh_compare_op1;
3217
3218 /* Which processor to schedule for. The elements of the enumeration must
3219 match exactly the cpu attribute in the sh.md file. */
3220
3221 enum processor_type {
3222 PROCESSOR_SH1,
3223 PROCESSOR_SH2,
3224 PROCESSOR_SH2E,
3225 PROCESSOR_SH2A,
3226 PROCESSOR_SH3,
3227 PROCESSOR_SH3E,
3228 PROCESSOR_SH4,
3229 PROCESSOR_SH4A,
3230 PROCESSOR_SH5
3231 };
3232
3233 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
3234 extern enum processor_type sh_cpu;
3235
3236 extern int optimize; /* needed for gen_casesi. */
3237
3238 enum mdep_reorg_phase_e
3239 {
3240 SH_BEFORE_MDEP_REORG,
3241 SH_INSERT_USES_LABELS,
3242 SH_SHORTEN_BRANCHES0,
3243 SH_FIXUP_PCLOAD,
3244 SH_SHORTEN_BRANCHES1,
3245 SH_AFTER_MDEP_REORG
3246 };
3247
3248 extern enum mdep_reorg_phase_e mdep_reorg_phase;
3249
3250 /* Handle Renesas compiler's pragmas. */
3251 #define REGISTER_TARGET_PRAGMAS() do { \
3252 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
3253 c_register_pragma (0, "trapa", sh_pr_trapa); \
3254 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
3255 } while (0)
3256
3257 /* Set when processing a function with pragma interrupt turned on. */
3258
3259 extern int pragma_interrupt;
3260
3261 /* Set when processing a function with interrupt attribute. */
3262
3263 extern int current_function_interrupt;
3264
3265 /* Set to an RTX containing the address of the stack to switch to
3266 for interrupt functions. */
3267 extern struct rtx_def *sp_switch;
3268
3269 \f
3270 /* Instructions with unfilled delay slots take up an
3271 extra two bytes for the nop in the delay slot.
3272 sh-dsp parallel processing insns are four bytes long. */
3273
3274 #define ADJUST_INSN_LENGTH(X, LENGTH) \
3275 (LENGTH) += sh_insn_length_adjustment (X);
3276 \f
3277 /* Define this macro if it is advisable to hold scalars in registers
3278 in a wider mode than that declared by the program. In such cases,
3279 the value is constrained to be within the bounds of the declared
3280 type, but kept valid in the wider mode. The signedness of the
3281 extension may differ from that of the type.
3282
3283 Leaving the unsignedp unchanged gives better code than always setting it
3284 to 0. This is despite the fact that we have only signed char and short
3285 load instructions. */
3286 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
3287 if (GET_MODE_CLASS (MODE) == MODE_INT \
3288 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
3289 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
3290 (MODE) = (TARGET_SH1 ? SImode \
3291 : TARGET_SHMEDIA32 ? SImode : DImode);
3292
3293 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
3294
3295 #define SIDI_OFF (TARGET_LITTLE_ENDIAN ? 0 : 4)
3296
3297 /* ??? Define ACCUMULATE_OUTGOING_ARGS? This is more efficient than pushing
3298 and popping arguments. However, we do have push/pop instructions, and
3299 rather limited offsets (4 bits) in load/store instructions, so it isn't
3300 clear if this would give better code. If implemented, should check for
3301 compatibility problems. */
3302
3303 #define SH_DYNAMIC_SHIFT_COST \
3304 (TARGET_HARD_SH4 ? 1 : TARGET_SH3 ? (TARGET_SMALLCODE ? 1 : 2) : 20)
3305
3306
3307 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
3308
3309 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
3310
3311 #define ACTUAL_NORMAL_MODE(ENTITY) \
3312 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3313
3314 #define NORMAL_MODE(ENTITY) \
3315 (sh_cfun_interrupt_handler_p () \
3316 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
3317 : ACTUAL_NORMAL_MODE (ENTITY))
3318
3319 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
3320
3321 #define MODE_EXIT(ENTITY) \
3322 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
3323
3324 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
3325 && (REGNO) == FPSCR_REG)
3326
3327 #define MODE_NEEDED(ENTITY, INSN) \
3328 (recog_memoized (INSN) >= 0 \
3329 ? get_attr_fp_mode (INSN) \
3330 : FP_MODE_NONE)
3331
3332 #define MODE_AFTER(MODE, INSN) \
3333 (TARGET_HITACHI \
3334 && recog_memoized (INSN) >= 0 \
3335 && get_attr_fp_set (INSN) != FP_SET_NONE \
3336 ? (int) get_attr_fp_set (INSN) \
3337 : (MODE))
3338
3339 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
3340 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
3341
3342 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
3343 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
3344
3345 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
3346 sh_can_redirect_branch ((INSN), (SEQ))
3347
3348 #define DWARF_FRAME_RETURN_COLUMN \
3349 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
3350
3351 #define EH_RETURN_DATA_REGNO(N) \
3352 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
3353
3354 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
3355 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
3356
3357 /* We have to distinguish between code and data, so that we apply
3358 datalabel where and only where appropriate. Use sdataN for data. */
3359 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
3360 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
3361 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
3362 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
3363
3364 /* Handle special EH pointer encodings. Absolute, pc-relative, and
3365 indirect are handled automatically. */
3366 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
3367 do { \
3368 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
3369 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
3370 { \
3371 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
3372 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
3373 if (0) goto DONE; \
3374 } \
3375 } while (0)
3376
3377 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
3378 /* SH constant pool breaks the devices in crtstuff.c to control section
3379 in where code resides. We have to write it as asm code. */
3380 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3381 asm (SECTION_OP "\n\
3382 mov.l 1f,r1\n\
3383 mova 2f,r0\n\
3384 braf r1\n\
3385 lds r0,pr\n\
3386 0: .p2align 2\n\
3387 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
3388 2:\n" TEXT_SECTION_ASM_OP);
3389 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
3390
3391 #define SIMULTANEOUS_PREFETCHES 2
3392
3393 /* FIXME: middle-end support for highpart optimizations is missing. */
3394 #define high_life_started reload_in_progress
3395
3396 #endif /* ! GCC_SH_H */
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