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Remove not needed __builtin_expect due to malloc predictor.
[official-gcc.git] / gcc / config / mips / mips.h
blob6804b792ff1041c106bfe719d34857ffb78180af
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY_SPEED
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target when optimizing code for speed, typically because
50 the branches are always predicted taken and so incur a large overhead
51 when not taken.
52
53 PTF_AVOID_BRANCHLIKELY_SIZE
54 As above but when optimizing for size.
55
56 PTF_AVOID_BRANCHLIKELY_ALWAYS
57 As above but regardless of whether we optimize for speed or size.
58
59 PTF_AVOID_IMADD
60 Set if it is usually not profitable to use the integer MADD or MSUB
61 instructions because of the overhead of getting the result out of
62 the HI/LO registers. */
63
64 #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1
65 #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2
66 #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \
67 PTF_AVOID_BRANCHLIKELY_SIZE)
68 #define PTF_AVOID_IMADD 0x4
69
70 /* Information about one recognized processor. Defined here for the
71 benefit of TARGET_CPU_CPP_BUILTINS. */
72 struct mips_cpu_info {
73 /* The 'canonical' name of the processor as far as GCC is concerned.
74 It's typically a manufacturer's prefix followed by a numerical
75 designation. It should be lowercase. */
76 const char *name;
77
78 /* The internal processor number that most closely matches this
79 entry. Several processors can have the same value, if there's no
80 difference between them from GCC's point of view. */
81 enum processor cpu;
82
83 /* The ISA level that the processor implements. */
84 int isa;
85
86 /* A mask of PTF_* values. */
87 unsigned int tune_flags;
88 };
89
90 #include "config/mips/mips-opts.h"
91
92 /* Macros to silence warnings about numbers being signed in traditional
93 C and unsigned in ISO C when compiled on 32-bit hosts. */
94
95 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
96 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
97 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
98
99 \f
100 /* Run-time compilation parameters selecting different hardware subsets. */
101
102 /* True if we are generating position-independent VxWorks RTP code. */
103 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
104
105 /* Compact branches must not be used if the user either selects the
106 'never' policy or the 'optimal' policy on a core that lacks
107 compact branch instructions. */
108 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \
109 || (mips_cb == MIPS_CB_OPTIMAL \
110 && !ISA_HAS_COMPACT_BRANCHES))
111
112 /* Compact branches may be used if the user either selects the
113 'always' policy or the 'optimal' policy on a core that supports
114 compact branch instructions. */
115 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \
116 || (mips_cb == MIPS_CB_OPTIMAL \
117 && ISA_HAS_COMPACT_BRANCHES))
118
119 /* Compact branches must always be generated if the user selects
120 the 'always' policy or the 'optimal' policy om a core that
121 lacks delay slot branch instructions. */
122 #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \
123 || (mips_cb == MIPS_CB_OPTIMAL \
124 && !ISA_HAS_DELAY_SLOTS))
125
126 /* Special handling for JRC that exists in microMIPSR3 as well as R6
127 ISAs with full compact branch support. */
128 #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \
129 || TARGET_MICROMIPS) \
130 && mips_cb != MIPS_CB_NEVER)
131
132 /* True if the output file is marked as ".abicalls; .option pic0"
133 (-call_nonpic). */
134 #define TARGET_ABICALLS_PIC0 \
135 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
136
137 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
138 #define TARGET_ABICALLS_PIC2 \
139 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
140
141 /* True if the call patterns should be split into a jalr followed by
142 an instruction to restore $gp. It is only safe to split the load
143 from the call when every use of $gp is explicit.
144
145 See mips_must_initialize_gp_p for details about how we manage the
146 global pointer. */
147
148 #define TARGET_SPLIT_CALLS \
149 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
150
151 /* True if we're generating a form of -mabicalls in which we can use
152 operators like %hi and %lo to refer to locally-binding symbols.
153 We can only do this for -mno-shared, and only then if we can use
154 relocation operations instead of assembly macros. It isn't really
155 worth using absolute sequences for 64-bit symbols because GOT
156 accesses are so much shorter. */
157
158 #define TARGET_ABSOLUTE_ABICALLS \
159 (TARGET_ABICALLS \
160 && !TARGET_SHARED \
161 && TARGET_EXPLICIT_RELOCS \
162 && !ABI_HAS_64BIT_SYMBOLS)
163
164 /* True if we can optimize sibling calls. For simplicity, we only
165 handle cases in which call_insn_operand will reject invalid
166 sibcall addresses. There are two cases in which this isn't true:
167
168 - TARGET_MIPS16. call_insn_operand accepts constant addresses
169 but there is no direct jump instruction. It isn't worth
170 using sibling calls in this case anyway; they would usually
171 be longer than normal calls.
172
173 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
174 accepts global constants, but all sibcalls must be indirect. */
175 #define TARGET_SIBCALLS \
176 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
177
178 /* True if we need to use a global offset table to access some symbols. */
179 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
180
181 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
182 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
183
184 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
185 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
186
187 /* True if we should use .cprestore to store to the cprestore slot.
188
189 We continue to use .cprestore for explicit-reloc code so that JALs
190 inside inline asms will work correctly. */
191 #define TARGET_CPRESTORE_DIRECTIVE \
192 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
193
194 /* True if we can use the J and JAL instructions. */
195 #define TARGET_ABSOLUTE_JUMPS \
196 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
197
198 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
199 This is true for both the PIC and non-PIC VxWorks RTP modes. */
200 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
201
202 /* True if .gpword or .gpdword should be used for switch tables. */
203 #define TARGET_GPWORD \
204 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
205
206 /* True if the output must have a writable .eh_frame.
207 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
208 #ifdef HAVE_LD_PERSONALITY_RELAXATION
209 #define TARGET_WRITABLE_EH_FRAME 0
210 #else
211 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
212 #endif
213
214 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
215 #ifdef HAVE_AS_DSPR1_MULT
216 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
217 #else
218 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
219 #endif
220
221 /* ISA has LSA available. */
222 #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA)
223
224 /* ISA has DLSA available. */
225 #define ISA_HAS_DLSA (TARGET_64BIT \
226 && (mips_isa_rev >= 6 \
227 || ISA_HAS_MSA))
228
229 /* The ISA compression flags that are currently in effect. */
230 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
231
232 /* Generate mips16 code */
233 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
234 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
235 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
236 /* Generate mips16e register save/restore sequences. */
237 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
238
239 /* True if we're generating a form of MIPS16 code in which general
240 text loads are allowed. */
241 #define TARGET_MIPS16_TEXT_LOADS \
242 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
243
244 /* True if we're generating a form of MIPS16 code in which PC-relative
245 loads are allowed. */
246 #define TARGET_MIPS16_PCREL_LOADS \
247 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
248
249 /* Generic ISA defines. */
250 #define ISA_MIPS1 (mips_isa == 1)
251 #define ISA_MIPS2 (mips_isa == 2)
252 #define ISA_MIPS3 (mips_isa == 3)
253 #define ISA_MIPS4 (mips_isa == 4)
254 #define ISA_MIPS32 (mips_isa == 32)
255 #define ISA_MIPS32R2 (mips_isa == 33)
256 #define ISA_MIPS32R3 (mips_isa == 34)
257 #define ISA_MIPS32R5 (mips_isa == 36)
258 #define ISA_MIPS32R6 (mips_isa == 37)
259 #define ISA_MIPS64 (mips_isa == 64)
260 #define ISA_MIPS64R2 (mips_isa == 65)
261 #define ISA_MIPS64R3 (mips_isa == 66)
262 #define ISA_MIPS64R5 (mips_isa == 68)
263 #define ISA_MIPS64R6 (mips_isa == 69)
264
265 /* Architecture target defines. */
266 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
267 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
268 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
269 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
270 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
271 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
272 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
273 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
274 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
275 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
276 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
277 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
278 #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000)
279 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
280 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
281 || mips_arch == PROCESSOR_OCTEON2 \
282 || mips_arch == PROCESSOR_OCTEON3)
283 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
284 || mips_arch == PROCESSOR_OCTEON3)
285 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
286 || mips_arch == PROCESSOR_SB1A)
287 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
288 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
289
290 /* Scheduling target defines. */
291 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
292 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
293 || mips_tune == PROCESSOR_24KF2_1 \
294 || mips_tune == PROCESSOR_24KF1_1)
295 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
296 || mips_tune == PROCESSOR_74KF2_1 \
297 || mips_tune == PROCESSOR_74KF1_1 \
298 || mips_tune == PROCESSOR_74KF3_2)
299 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
300 || mips_tune == PROCESSOR_LOONGSON_2F)
301 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
302 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
303 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
304 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
305 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
306 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
307 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
308 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
309 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
310 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
311 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
312 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
313 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
314 || mips_tune == PROCESSOR_OCTEON2 \
315 || mips_tune == PROCESSOR_OCTEON3)
316 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
317 || mips_tune == PROCESSOR_SB1A)
318 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
319 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
320 #define TUNE_P6600 (mips_tune == PROCESSOR_P6600)
321
322 /* Whether vector modes and intrinsics for ST Microelectronics
323 Loongson-2E/2F processors should be enabled. In o32 pairs of
324 floating-point registers provide 64-bit values. */
325 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
326 && (TARGET_LOONGSON_2EF \
327 || TARGET_LOONGSON_3A))
328
329 /* True if the pre-reload scheduler should try to create chains of
330 multiply-add or multiply-subtract instructions. For example,
331 suppose we have:
332
333 t1 = a * b
334 t2 = t1 + c * d
335 t3 = e * f
336 t4 = t3 - g * h
337
338 t1 will have a higher priority than t2 and t3 will have a higher
339 priority than t4. However, before reload, there is no dependence
340 between t1 and t3, and they can often have similar priorities.
341 The scheduler will then tend to prefer:
342
343 t1 = a * b
344 t3 = e * f
345 t2 = t1 + c * d
346 t4 = t3 - g * h
347
348 which stops us from making full use of macc/madd-style instructions.
349 This sort of situation occurs frequently in Fourier transforms and
350 in unrolled loops.
351
352 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
353 queue so that chained multiply-add and multiply-subtract instructions
354 appear ahead of any other instruction that is likely to clobber lo.
355 In the example above, if t2 and t3 become ready at the same time,
356 the code ensures that t2 is scheduled first.
357
358 Multiply-accumulate instructions are a bigger win for some targets
359 than others, so this macro is defined on an opt-in basis. */
360 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
361 || TUNE_MIPS4120 \
362 || TUNE_MIPS4130 \
363 || TUNE_24K \
364 || TUNE_P5600)
365
366 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
367 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
368
369 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
370 directly accessible, while the command-line options select
371 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
372 in use. */
373 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
374 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
375
376 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
377 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
378 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
379
380 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
381 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
382 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
383 && !TARGET_ODD_SPREG)
384
385 /* False if SC acts as a memory barrier with respect to itself,
386 otherwise a SYNC will be emitted after SC for atomic operations
387 that require ordering between the SC and following loads and
388 stores. It does not tell anything about ordering of loads and
389 stores prior to and following the SC, only about the SC itself and
390 those loads and stores follow it. */
391 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
392
393 /* Define preprocessor macros for the -march and -mtune options.
394 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
395 processor. If INFO's canonical name is "foo", define PREFIX to
396 be "foo", and define an additional macro PREFIX_FOO. */
397 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
398 do \
399 { \
400 char *macro, *p; \
401 \
402 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
403 for (p = macro; *p != 0; p++) \
404 if (*p == '+') \
405 *p = 'P'; \
406 else \
407 *p = TOUPPER (*p); \
408 \
409 builtin_define (macro); \
410 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
411 free (macro); \
412 } \
413 while (0)
414
415 /* Target CPU builtins. */
416 #define TARGET_CPU_CPP_BUILTINS() \
417 do \
418 { \
419 builtin_assert ("machine=mips"); \
420 builtin_assert ("cpu=mips"); \
421 builtin_define ("__mips__"); \
422 builtin_define ("_mips"); \
423 \
424 /* We do this here because __mips is defined below and so we \
425 can't use builtin_define_std. We don't ever want to define \
426 "mips" for VxWorks because some of the VxWorks headers \
427 construct include filenames from a root directory macro, \
428 an architecture macro and a filename, where the architecture \
429 macro expands to 'mips'. If we define 'mips' to 1, the \
430 architecture macro expands to 1 as well. */ \
431 if (!flag_iso && !TARGET_VXWORKS) \
432 builtin_define ("mips"); \
433 \
434 if (TARGET_64BIT) \
435 builtin_define ("__mips64"); \
436 \
437 /* Treat _R3000 and _R4000 like register-size \
438 defines, which is how they've historically \
439 been used. */ \
440 if (TARGET_64BIT) \
441 { \
442 builtin_define_std ("R4000"); \
443 builtin_define ("_R4000"); \
444 } \
445 else \
446 { \
447 builtin_define_std ("R3000"); \
448 builtin_define ("_R3000"); \
449 } \
450 \
451 if (TARGET_FLOAT64) \
452 builtin_define ("__mips_fpr=64"); \
453 else if (TARGET_FLOATXX) \
454 builtin_define ("__mips_fpr=0"); \
455 else \
456 builtin_define ("__mips_fpr=32"); \
457 \
458 if (mips_base_compression_flags & MASK_MIPS16) \
459 builtin_define ("__mips16"); \
460 \
461 if (TARGET_MIPS3D) \
462 builtin_define ("__mips3d"); \
463 \
464 if (TARGET_SMARTMIPS) \
465 builtin_define ("__mips_smartmips"); \
466 \
467 if (mips_base_compression_flags & MASK_MICROMIPS) \
468 builtin_define ("__mips_micromips"); \
469 \
470 if (TARGET_MCU) \
471 builtin_define ("__mips_mcu"); \
472 \
473 if (TARGET_EVA) \
474 builtin_define ("__mips_eva"); \
475 \
476 if (TARGET_DSP) \
477 { \
478 builtin_define ("__mips_dsp"); \
479 if (TARGET_DSPR2) \
480 { \
481 builtin_define ("__mips_dspr2"); \
482 builtin_define ("__mips_dsp_rev=2"); \
483 } \
484 else \
485 builtin_define ("__mips_dsp_rev=1"); \
486 } \
487 \
488 if (ISA_HAS_MSA) \
489 { \
490 builtin_define ("__mips_msa"); \
491 builtin_define ("__mips_msa_width=128"); \
492 } \
493 \
494 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
495 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
496 \
497 if (ISA_MIPS1) \
498 { \
499 builtin_define ("__mips=1"); \
500 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
501 } \
502 else if (ISA_MIPS2) \
503 { \
504 builtin_define ("__mips=2"); \
505 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
506 } \
507 else if (ISA_MIPS3) \
508 { \
509 builtin_define ("__mips=3"); \
510 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
511 } \
512 else if (ISA_MIPS4) \
513 { \
514 builtin_define ("__mips=4"); \
515 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
516 } \
517 else if (mips_isa >= 32 && mips_isa < 64) \
518 { \
519 builtin_define ("__mips=32"); \
520 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
521 } \
522 else if (mips_isa >= 64) \
523 { \
524 builtin_define ("__mips=64"); \
525 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
526 } \
527 if (mips_isa_rev > 0) \
528 builtin_define_with_int_value ("__mips_isa_rev", \
529 mips_isa_rev); \
530 \
531 switch (mips_abi) \
532 { \
533 case ABI_32: \
534 builtin_define ("_ABIO32=1"); \
535 builtin_define ("_MIPS_SIM=_ABIO32"); \
536 break; \
537 \
538 case ABI_N32: \
539 builtin_define ("_ABIN32=2"); \
540 builtin_define ("_MIPS_SIM=_ABIN32"); \
541 break; \
542 \
543 case ABI_64: \
544 builtin_define ("_ABI64=3"); \
545 builtin_define ("_MIPS_SIM=_ABI64"); \
546 break; \
547 \
548 case ABI_O64: \
549 builtin_define ("_ABIO64=4"); \
550 builtin_define ("_MIPS_SIM=_ABIO64"); \
551 break; \
552 } \
553 \
554 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
555 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
556 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
557 builtin_define_with_int_value ("_MIPS_FPSET", \
558 32 / MAX_FPRS_PER_FMT); \
559 builtin_define_with_int_value ("_MIPS_SPFPSET", \
560 TARGET_ODD_SPREG ? 32 : 16); \
561 \
562 /* These defines reflect the ABI in use, not whether the \
563 FPU is directly accessible. */ \
564 if (TARGET_NO_FLOAT) \
565 builtin_define ("__mips_no_float"); \
566 else if (TARGET_HARD_FLOAT_ABI) \
567 builtin_define ("__mips_hard_float"); \
568 else \
569 builtin_define ("__mips_soft_float"); \
570 \
571 if (TARGET_SINGLE_FLOAT) \
572 builtin_define ("__mips_single_float"); \
573 \
574 if (TARGET_PAIRED_SINGLE_FLOAT) \
575 builtin_define ("__mips_paired_single_float"); \
576 \
577 if (mips_abs == MIPS_IEEE_754_2008) \
578 builtin_define ("__mips_abs2008"); \
579 \
580 if (mips_nan == MIPS_IEEE_754_2008) \
581 builtin_define ("__mips_nan2008"); \
582 \
583 if (TARGET_BIG_ENDIAN) \
584 { \
585 builtin_define_std ("MIPSEB"); \
586 builtin_define ("_MIPSEB"); \
587 } \
588 else \
589 { \
590 builtin_define_std ("MIPSEL"); \
591 builtin_define ("_MIPSEL"); \
592 } \
593 \
594 /* Whether calls should go through $25. The separate __PIC__ \
595 macro indicates whether abicalls code might use a GOT. */ \
596 if (TARGET_ABICALLS) \
597 builtin_define ("__mips_abicalls"); \
598 \
599 /* Whether Loongson vector modes are enabled. */ \
600 if (TARGET_LOONGSON_VECTORS) \
601 builtin_define ("__mips_loongson_vector_rev"); \
602 \
603 /* Historical Octeon macro. */ \
604 if (TARGET_OCTEON) \
605 builtin_define ("__OCTEON__"); \
606 \
607 if (TARGET_SYNCI) \
608 builtin_define ("__mips_synci"); \
609 \
610 /* Macros dependent on the C dialect. */ \
611 if (preprocessing_asm_p ()) \
612 { \
613 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
614 builtin_define ("_LANGUAGE_ASSEMBLY"); \
615 } \
616 else if (c_dialect_cxx ()) \
617 { \
618 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
619 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
620 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
621 } \
622 else \
623 { \
624 builtin_define_std ("LANGUAGE_C"); \
625 builtin_define ("_LANGUAGE_C"); \
626 } \
627 if (c_dialect_objc ()) \
628 { \
629 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
630 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
631 /* Bizarre, but retained for backwards compatibility. */ \
632 builtin_define_std ("LANGUAGE_C"); \
633 builtin_define ("_LANGUAGE_C"); \
634 } \
635 \
636 if (mips_abi == ABI_EABI) \
637 builtin_define ("__mips_eabi"); \
638 \
639 if (TARGET_CACHE_BUILTIN) \
640 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
641 if (!ISA_HAS_LXC1_SXC1) \
642 builtin_define ("__mips_no_lxc1_sxc1"); \
643 if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \
644 builtin_define ("__mips_no_madd4"); \
645 } \
646 while (0)
647
648 /* Default target_flags if no switches are specified */
649
650 #ifndef TARGET_DEFAULT
651 #define TARGET_DEFAULT 0
652 #endif
653
654 #ifndef TARGET_CPU_DEFAULT
655 #define TARGET_CPU_DEFAULT 0
656 #endif
657
658 #ifndef TARGET_ENDIAN_DEFAULT
659 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
660 #endif
661
662 #ifdef IN_LIBGCC2
663 #undef TARGET_64BIT
664 /* Make this compile time constant for libgcc2 */
665 #ifdef __mips64
666 #define TARGET_64BIT 1
667 #else
668 #define TARGET_64BIT 0
669 #endif
670 #endif /* IN_LIBGCC2 */
671
672 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
673 when compiled with hardware floating point. This is because MIPS16
674 code cannot save and restore the floating-point registers, which is
675 important if in a mixed MIPS16/non-MIPS16 environment. */
676
677 #ifdef IN_LIBGCC2
678 #if __mips_hard_float
679 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
680 #endif
681 #endif /* IN_LIBGCC2 */
682
683 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
684
685 #ifndef MULTILIB_ENDIAN_DEFAULT
686 #if TARGET_ENDIAN_DEFAULT == 0
687 #define MULTILIB_ENDIAN_DEFAULT "EL"
688 #else
689 #define MULTILIB_ENDIAN_DEFAULT "EB"
690 #endif
691 #endif
692
693 #ifndef MULTILIB_ISA_DEFAULT
694 #if MIPS_ISA_DEFAULT == 1
695 #define MULTILIB_ISA_DEFAULT "mips1"
696 #elif MIPS_ISA_DEFAULT == 2
697 #define MULTILIB_ISA_DEFAULT "mips2"
698 #elif MIPS_ISA_DEFAULT == 3
699 #define MULTILIB_ISA_DEFAULT "mips3"
700 #elif MIPS_ISA_DEFAULT == 4
701 #define MULTILIB_ISA_DEFAULT "mips4"
702 #elif MIPS_ISA_DEFAULT == 32
703 #define MULTILIB_ISA_DEFAULT "mips32"
704 #elif MIPS_ISA_DEFAULT == 33
705 #define MULTILIB_ISA_DEFAULT "mips32r2"
706 #elif MIPS_ISA_DEFAULT == 37
707 #define MULTILIB_ISA_DEFAULT "mips32r6"
708 #elif MIPS_ISA_DEFAULT == 64
709 #define MULTILIB_ISA_DEFAULT "mips64"
710 #elif MIPS_ISA_DEFAULT == 65
711 #define MULTILIB_ISA_DEFAULT "mips64r2"
712 #elif MIPS_ISA_DEFAULT == 69
713 #define MULTILIB_ISA_DEFAULT "mips64r6"
714 #else
715 #define MULTILIB_ISA_DEFAULT "mips1"
716 #endif
717 #endif
718
719 #ifndef MIPS_ABI_DEFAULT
720 #define MIPS_ABI_DEFAULT ABI_32
721 #endif
722
723 /* Use the most portable ABI flag for the ASM specs. */
724
725 #if MIPS_ABI_DEFAULT == ABI_32
726 #define MULTILIB_ABI_DEFAULT "mabi=32"
727 #elif MIPS_ABI_DEFAULT == ABI_O64
728 #define MULTILIB_ABI_DEFAULT "mabi=o64"
729 #elif MIPS_ABI_DEFAULT == ABI_N32
730 #define MULTILIB_ABI_DEFAULT "mabi=n32"
731 #elif MIPS_ABI_DEFAULT == ABI_64
732 #define MULTILIB_ABI_DEFAULT "mabi=64"
733 #elif MIPS_ABI_DEFAULT == ABI_EABI
734 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
735 #endif
736
737 #ifndef MULTILIB_DEFAULTS
738 #define MULTILIB_DEFAULTS \
739 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
740 #endif
741
742 /* We must pass -EL to the linker by default for little endian embedded
743 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
744 linker will default to using big-endian output files. The OUTPUT_FORMAT
745 line must be in the linker script, otherwise -EB/-EL will not work. */
746
747 #ifndef ENDIAN_SPEC
748 #if TARGET_ENDIAN_DEFAULT == 0
749 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
750 #else
751 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
752 #endif
753 #endif
754
755 /* A spec condition that matches all non-mips16 -mips arguments. */
756
757 #define MIPS_ISA_LEVEL_OPTION_SPEC \
758 "mips1|mips2|mips3|mips4|mips32*|mips64*"
759
760 /* A spec condition that matches all non-mips16 architecture arguments. */
761
762 #define MIPS_ARCH_OPTION_SPEC \
763 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
764
765 /* A spec that infers a -mips argument from an -march argument. */
766
767 #define MIPS_ISA_LEVEL_SPEC \
768 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
769 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
770 %{march=mips2|march=r6000:-mips2} \
771 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
772 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
773 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
774 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
775 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
776 |march=34k*|march=74k*|march=m14k*|march=1004k* \
777 |march=interaptiv: -mips32r2} \
778 %{march=mips32r3: -mips32r3} \
779 %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \
780 %{march=mips32r6: -mips32r6} \
781 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
782 |march=xlr: -mips64} \
783 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
784 %{march=mips64r3: -mips64r3} \
785 %{march=mips64r5: -mips64r5} \
786 %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}"
787
788 /* A spec that injects the default multilib ISA if no architecture is
789 specified. */
790
791 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
792 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
793 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
794
795 /* A spec that infers a -mhard-float or -msoft-float setting from an
796 -march argument. Note that soft-float and hard-float code are not
797 link-compatible. */
798
799 #define MIPS_ARCH_FLOAT_SPEC \
800 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
801 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
802 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
803 |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
804 march=*: -mhard-float}"
805
806 /* A spec condition that matches 32-bit options. It only works if
807 MIPS_ISA_LEVEL_SPEC has been applied. */
808
809 #define MIPS_32BIT_OPTION_SPEC \
810 "mips1|mips2|mips32*|mgp32"
811
812 /* A spec condition that matches architectures should be targeted with
813 o32 FPXX for compatibility reasons. */
814 #define MIPS_FPXX_OPTION_SPEC \
815 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
816 mips64|mips64r2|mips64r3|mips64r5"
817
818 /* Infer a -msynci setting from a -mips argument, on the assumption that
819 -msynci is desired where possible. */
820 #define MIPS_ISA_SYNCI_SPEC \
821 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
822 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
823
824 /* Infer a -mnan=2008 setting from a -mips argument. */
825 #define MIPS_ISA_NAN2008_SPEC \
826 "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \
827 %{!msoft-float:-mnan=2008}}"
828
829 #if (MIPS_ABI_DEFAULT == ABI_O64 \
830 || MIPS_ABI_DEFAULT == ABI_N32 \
831 || MIPS_ABI_DEFAULT == ABI_64)
832 #define OPT_ARCH64 "mabi=32|mgp32:;"
833 #define OPT_ARCH32 "mabi=32|mgp32"
834 #else
835 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
836 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
837 #endif
838
839 /* Support for a compile-time default CPU, et cetera. The rules are:
840 --with-arch is ignored if -march is specified or a -mips is specified
841 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
842 --with-tune is ignored if -mtune is specified; likewise
843 --with-tune-32 and --with-tune-64.
844 --with-abi is ignored if -mabi is specified.
845 --with-float is ignored if -mhard-float or -msoft-float are
846 specified.
847 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
848 specified.
849 --with-nan is ignored if -mnan is specified.
850 --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are
851 specified.
852 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
853 or -mno-odd-spreg are specified.
854 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
855 specified. */
856 #define OPTION_DEFAULT_SPECS \
857 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
858 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
859 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
860 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
861 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
862 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
863 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
864 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
865 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
866 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
867 {"fp_32", "%{" OPT_ARCH32 \
868 ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \
869 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
870 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
871 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
872 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
873 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
874 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \
875 {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
876 {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
877
878 /* A spec that infers the:
879 -mnan=2008 setting from a -mips argument,
880 -mdsp setting from a -march argument. */
881 #define BASE_DRIVER_SELF_SPECS \
882 MIPS_ISA_NAN2008_SPEC, \
883 "%{!mno-dsp: \
884 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \
885 |march=interaptiv: -mdsp} \
886 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
887
888 #define DRIVER_SELF_SPECS \
889 MIPS_ISA_LEVEL_SPEC, \
890 BASE_DRIVER_SELF_SPECS
891
892 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
893 && ISA_HAS_COND_TRAP)
894
895 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
896
897 /* True if the ABI can only work with 64-bit integer registers. We
898 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
899 otherwise floating-point registers must also be 64-bit. */
900 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
901
902 /* Likewise for 32-bit regs. */
903 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
904
905 /* True if the file format uses 64-bit symbols. At present, this is
906 only true for n64, which uses 64-bit ELF. */
907 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
908
909 /* True if symbols are 64 bits wide. This is usually determined by
910 the ABI's file format, but it can be overridden by -msym32. Note that
911 overriding the size with -msym32 changes the ABI of relocatable objects,
912 although it doesn't change the ABI of a fully-linked object. */
913 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
914 && Pmode == DImode \
915 && !TARGET_SYM32)
916
917 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
918 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
919 || ISA_MIPS4 \
920 || ISA_MIPS64 \
921 || ISA_MIPS64R2 \
922 || ISA_MIPS64R3 \
923 || ISA_MIPS64R5 \
924 || ISA_MIPS64R6)
925
926 #define ISA_HAS_JR (mips_isa_rev <= 5)
927
928 #define ISA_HAS_DELAY_SLOTS 1
929
930 #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6)
931
932 /* ISA has branch likely instructions (e.g. mips2). */
933 /* Disable branchlikely for tx39 until compare rewrite. They haven't
934 been generated up to this point. */
935 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
936
937 /* ISA has 32 single-precision registers. */
938 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
939 && !TARGET_LOONGSON_3A) \
940 || TARGET_FLOAT64 \
941 || TARGET_MIPS5900)
942
943 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
944 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
945 || TARGET_MIPS5400 \
946 || TARGET_MIPS5500 \
947 || TARGET_MIPS5900 \
948 || TARGET_MIPS7000 \
949 || TARGET_MIPS9000 \
950 || TARGET_MAD \
951 || (mips_isa_rev >= 1 \
952 && mips_isa_rev <= 5)) \
953 && !TARGET_MIPS16)
954
955 /* ISA has a three-operand multiplication instruction. */
956 #define ISA_HAS_DMUL3 (TARGET_64BIT \
957 && TARGET_OCTEON \
958 && !TARGET_MIPS16)
959
960 /* ISA has HI and LO registers. */
961 #define ISA_HAS_HILO (mips_isa_rev <= 5)
962
963 /* ISA supports instructions DMULT and DMULTU. */
964 #define ISA_HAS_DMULT (TARGET_64BIT \
965 && !TARGET_MIPS5900 \
966 && mips_isa_rev <= 5)
967
968 /* ISA supports instructions MULT and MULTU. */
969 #define ISA_HAS_MULT (mips_isa_rev <= 5)
970
971 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
972 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
973
974 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
975 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
976
977 /* For Loongson, it is preferable to use the Loongson-specific division and
978 modulo instructions instead of the regular (D)DIV(U) instruction,
979 because the former are faster and can also have the effect of reducing
980 code size. */
981 #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \
982 || TARGET_LOONGSON_3A) \
983 && !TARGET_MIPS16)
984
985 /* ISA supports instructions DDIV and DDIVU. */
986 #define ISA_HAS_DDIV (TARGET_64BIT \
987 && !TARGET_MIPS5900 \
988 && !ISA_AVOID_DIV_HILO \
989 && mips_isa_rev <= 5)
990
991 /* ISA supports instructions DIV and DIVU.
992 This is always true, but the macro is needed for ISA_HAS_<D>DIV
993 in mips.md. */
994 #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \
995 && mips_isa_rev <= 5)
996
997 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
998 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
999
1000 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
1001 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
1002
1003 /* ISA has the floating-point conditional move instructions introduced
1004 in mips4. */
1005 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
1006 || (mips_isa_rev >= 1 \
1007 && mips_isa_rev <= 5)) \
1008 && !TARGET_MIPS5500 \
1009 && !TARGET_MIPS16)
1010
1011 /* ISA has the integer conditional move instructions introduced in mips4 and
1012 ST Loongson 2E/2F. */
1013 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
1014 || TARGET_MIPS5900 \
1015 || TARGET_LOONGSON_2EF)
1016
1017 /* ISA has LDC1 and SDC1. */
1018 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
1019 && !TARGET_MIPS5900 \
1020 && !TARGET_MIPS16)
1021
1022 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
1023 branch on CC, and move (both FP and non-FP) on CC. */
1024 #define ISA_HAS_8CC (ISA_MIPS4 \
1025 || (mips_isa_rev >= 1 \
1026 && mips_isa_rev <= 5))
1027
1028 /* ISA has the FP condition code instructions that store the flag in an
1029 FP register. */
1030 #define ISA_HAS_CCF (mips_isa_rev >= 6)
1031
1032 #define ISA_HAS_SEL (mips_isa_rev >= 6)
1033
1034 /* This is a catch all for other mips4 instructions: indexed load, the
1035 FP madd and msub instructions, and the FP recip and recip sqrt
1036 instructions. Note that this macro should only be used by other
1037 ISA_HAS_* macros. */
1038 #define ISA_HAS_FP4 ((ISA_MIPS4 \
1039 || ISA_MIPS64 \
1040 || (mips_isa_rev >= 2 \
1041 && mips_isa_rev <= 5)) \
1042 && !TARGET_MIPS16)
1043
1044 /* ISA has floating-point indexed load and store instructions
1045 (LWXC1, LDXC1, SWXC1 and SDXC1). */
1046 #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \
1047 && mips_lxc1_sxc1)
1048
1049 /* ISA has paired-single instructions. */
1050 #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \
1051 || (mips_isa_rev >= 2 \
1052 && mips_isa_rev <= 5)) \
1053 && !TARGET_OCTEON)
1054
1055 /* ISA has conditional trap instructions. */
1056 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
1057 && !TARGET_MIPS16)
1058
1059 /* ISA has conditional trap with immediate instructions. */
1060 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
1061 && mips_isa_rev <= 5 \
1062 && !TARGET_MIPS16)
1063
1064 /* ISA has integer multiply-accumulate instructions, madd and msub. */
1065 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
1066 && mips_isa_rev <= 5)
1067
1068 /* Integer multiply-accumulate instructions should be generated. */
1069 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
1070
1071 /* ISA has 4 operand fused madd instructions of the form
1072 'd = [+-] (a * b [+-] c)'. */
1073 #define ISA_HAS_FUSED_MADD4 (mips_madd4 \
1074 && (TARGET_MIPS8000 \
1075 || TARGET_LOONGSON_3A))
1076
1077 /* ISA has 4 operand unfused madd instructions of the form
1078 'd = [+-] (a * b [+-] c)'. */
1079 #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \
1080 && ISA_HAS_FP4 \
1081 && !TARGET_MIPS8000 \
1082 && !TARGET_LOONGSON_3A)
1083
1084 /* ISA has 3 operand r6 fused madd instructions of the form
1085 'c = c [+-] (a * b)'. */
1086 #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6)
1087
1088 /* ISA has 3 operand loongson fused madd instructions of the form
1089 'c = [+-] (a * b [+-] c)'. */
1090 #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF
1091
1092 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1093 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1094 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1095 this restriction to the MIPS IV ISA too. */
1096 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1097 (((ISA_HAS_FP4 \
1098 && ((MODE) == SFmode \
1099 || ((TARGET_FLOAT64 \
1100 || mips_isa_rev >= 2) \
1101 && (MODE) == DFmode))) \
1102 || (((MODE) == SFmode \
1103 || (MODE) == DFmode) \
1104 && (mips_isa_rev >= 6)) \
1105 || (TARGET_SB1 \
1106 && (MODE) == V2SFmode)) \
1107 && !TARGET_MIPS16)
1108
1109 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1110
1111 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1112
1113 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1114
1115 /* ISA has count leading zeroes/ones instruction (not implemented). */
1116 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1117
1118 /* ISA has three operand multiply instructions that put
1119 the high part in an accumulator: mulhi or mulhiu. */
1120 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1121 || TARGET_MIPS5500 \
1122 || TARGET_SR71K) \
1123 && !TARGET_MIPS16)
1124
1125 /* ISA has three operand multiply instructions that negate the
1126 result and put the result in an accumulator. */
1127 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1128 || TARGET_MIPS5500 \
1129 || TARGET_SR71K) \
1130 && !TARGET_MIPS16)
1131
1132 /* ISA has three operand multiply instructions that subtract the
1133 result from a 4th operand and put the result in an accumulator. */
1134 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1135 || TARGET_MIPS5500 \
1136 || TARGET_SR71K) \
1137 && !TARGET_MIPS16)
1138
1139 /* ISA has three operand multiply instructions that add the result
1140 to a 4th operand and put the result in an accumulator. */
1141 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1142 || TARGET_MIPS4130 \
1143 || TARGET_MIPS5400 \
1144 || TARGET_MIPS5500 \
1145 || TARGET_SR71K) \
1146 && !TARGET_MIPS16)
1147
1148 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1149 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1150 || TARGET_MIPS4130) \
1151 && !TARGET_MIPS16)
1152
1153 /* ISA has the "ror" (rotate right) instructions. */
1154 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1155 || TARGET_MIPS5400 \
1156 || TARGET_MIPS5500 \
1157 || TARGET_SR71K \
1158 || TARGET_SMARTMIPS) \
1159 && !TARGET_MIPS16)
1160
1161 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1162 64-bit targets also provide DSBH and DSHD. */
1163 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1164
1165 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1166 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1167 || TARGET_LOONGSON_2EF \
1168 || TARGET_MIPS5900 \
1169 || mips_isa_rev >= 1) \
1170 && !TARGET_MIPS16)
1171
1172 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1173 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
1174
1175 /* ISA has data indexed prefetch instructions. This controls use of
1176 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1177 (prefx is a cop1x instruction, so can only be used if FP is
1178 enabled.) */
1179 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1180
1181 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1182 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1183 also requires TARGET_DOUBLE_FLOAT. */
1184 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1185
1186 /* ISA includes the MIPS32r2 seb and seh instructions. */
1187 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1188
1189 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1190 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1191
1192 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1193 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1194 && mips_isa_rev >= 2)
1195
1196 /* ISA has lwxs instruction (load w/scaled index address. */
1197 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1198 && !TARGET_MIPS16)
1199
1200 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1201 #define ISA_HAS_LBX (TARGET_OCTEON2)
1202 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1203 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1204 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1205 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1206 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1207 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1208 && TARGET_64BIT)
1209
1210 /* The DSP ASE is available. */
1211 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1212
1213 /* Revision 2 of the DSP ASE is available. */
1214 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1215
1216 /* The MSA ASE is available. */
1217 #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16)
1218
1219 /* True if the result of a load is not available to the next instruction.
1220 A nop will then be needed between instructions like "lw $4,..."
1221 and "addiu $4,$4,1". */
1222 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1223 && !TARGET_MIPS3900 \
1224 && !TARGET_MIPS5900 \
1225 && !TARGET_MIPS16 \
1226 && !TARGET_MICROMIPS)
1227
1228 /* Likewise mtc1 and mfc1. */
1229 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1230 && !TARGET_MIPS5900 \
1231 && !TARGET_LOONGSON_2EF)
1232
1233 /* Likewise floating-point comparisons. */
1234 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1235 && !TARGET_MIPS5900 \
1236 && !TARGET_LOONGSON_2EF)
1237
1238 /* True if mflo and mfhi can be immediately followed by instructions
1239 which write to the HI and LO registers.
1240
1241 According to MIPS specifications, MIPS ISAs I, II, and III need
1242 (at least) two instructions between the reads of HI/LO and
1243 instructions which write them, and later ISAs do not. Contradicting
1244 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1245 the UM for the NEC Vr5000) document needing the instructions between
1246 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1247 MIPS64 and later ISAs to have the interlocks, plus any specific
1248 earlier-ISA CPUs for which CPU documentation declares that the
1249 instructions are really interlocked. */
1250 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1251 || TARGET_MIPS5500 \
1252 || TARGET_MIPS5900 \
1253 || TARGET_LOONGSON_2EF)
1254
1255 /* ISA includes synci, jr.hb and jalr.hb. */
1256 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1257
1258 /* ISA includes sync. */
1259 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1260 #define GENERATE_SYNC \
1261 (target_flags_explicit & MASK_LLSC \
1262 ? TARGET_LLSC && !TARGET_MIPS16 \
1263 : ISA_HAS_SYNC)
1264
1265 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1266 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1267 instructions. */
1268 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1269 #define GENERATE_LL_SC \
1270 (target_flags_explicit & MASK_LLSC \
1271 ? TARGET_LLSC && !TARGET_MIPS16 \
1272 : ISA_HAS_LL_SC)
1273
1274 #define ISA_HAS_SWAP (TARGET_XLP)
1275 #define ISA_HAS_LDADD (TARGET_XLP)
1276
1277 /* ISA includes the baddu instruction. */
1278 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1279
1280 /* ISA includes the bbit* instructions. */
1281 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1282
1283 /* ISA includes the cins instruction. */
1284 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1285
1286 /* ISA includes the exts instruction. */
1287 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1288
1289 /* ISA includes the seq and sne instructions. */
1290 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1291
1292 /* ISA includes the pop instruction. */
1293 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1294
1295 /* The CACHE instruction is available in non-MIPS16 code. */
1296 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1297
1298 /* The CACHE instruction is available. */
1299 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1300 \f
1301 /* Tell collect what flags to pass to nm. */
1302 #ifndef NM_FLAGS
1303 #define NM_FLAGS "-Bn"
1304 #endif
1305
1306 \f
1307 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1308 the assembler. It may be overridden by subtargets.
1309
1310 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1311 COFF debugging info. */
1312
1313 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1314 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1315 %{g} %{g0} %{g1} %{g2} %{g3} \
1316 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1317 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1318 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}"
1319 #endif
1320
1321 /* FP_ASM_SPEC represents the floating-point options that must be passed
1322 to the assembler when FPXX support exists. Prior to that point the
1323 assembler could accept the options but were not required for
1324 correctness. We only add the options when absolutely necessary
1325 because passing -msoft-float to the assembler will cause it to reject
1326 all hard-float instructions which may require some user code to be
1327 updated. */
1328
1329 #ifdef HAVE_AS_DOT_MODULE
1330 #define FP_ASM_SPEC "\
1331 %{mhard-float} %{msoft-float} \
1332 %{msingle-float} %{mdouble-float}"
1333 #else
1334 #define FP_ASM_SPEC
1335 #endif
1336
1337 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1338 overridden by subtargets. */
1339
1340 #ifndef SUBTARGET_ASM_SPEC
1341 #define SUBTARGET_ASM_SPEC ""
1342 #endif
1343
1344 #undef ASM_SPEC
1345 #define ASM_SPEC "\
1346 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1347 %{mips32*} %{mips64*} \
1348 %{mips16} %{mno-mips16:-no-mips16} \
1349 %{mmicromips} %{mno-micromips} \
1350 %{mips3d} %{mno-mips3d:-no-mips3d} \
1351 %{mdmx} %{mno-mdmx:-no-mdmx} \
1352 %{mdsp} %{mno-dsp} \
1353 %{mdspr2} %{mno-dspr2} \
1354 %{mmcu} %{mno-mcu} \
1355 %{meva} %{mno-eva} \
1356 %{mvirt} %{mno-virt} \
1357 %{mxpa} %{mno-xpa} \
1358 %{mcrc} %{mno-crc} \
1359 %{mginv} %{mno-ginv} \
1360 %{mmsa} %{mno-msa} \
1361 %{msmartmips} %{mno-smartmips} \
1362 %{mmt} %{mno-mt} \
1363 %{mfix-rm7000} %{mno-fix-rm7000} \
1364 %{mfix-vr4120} %{mfix-vr4130} \
1365 %{mfix-24k} \
1366 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1367 %(subtarget_asm_debugging_spec) \
1368 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1369 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1370 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1371 %{modd-spreg} %{mno-odd-spreg} \
1372 %{mshared} %{mno-shared} \
1373 %{msym32} %{mno-sym32} \
1374 %{mtune=*}" \
1375 FP_ASM_SPEC "\
1376 %(subtarget_asm_spec)"
1377
1378 /* Extra switches sometimes passed to the linker. */
1379
1380 #ifndef LINK_SPEC
1381 #define LINK_SPEC "\
1382 %(endian_spec) \
1383 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1384 %{shared}"
1385 #endif /* LINK_SPEC defined */
1386
1387
1388 /* Specs for the compiler proper */
1389
1390 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1391 overridden by subtargets. */
1392 #ifndef SUBTARGET_CC1_SPEC
1393 #define SUBTARGET_CC1_SPEC ""
1394 #endif
1395
1396 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1397
1398 #undef CC1_SPEC
1399 #define CC1_SPEC "\
1400 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1401 %(subtarget_cc1_spec)"
1402
1403 /* Preprocessor specs. */
1404
1405 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1406 overridden by subtargets. */
1407 #ifndef SUBTARGET_CPP_SPEC
1408 #define SUBTARGET_CPP_SPEC ""
1409 #endif
1410
1411 #define CPP_SPEC "%(subtarget_cpp_spec)"
1412
1413 /* This macro defines names of additional specifications to put in the specs
1414 that can be used in various specifications like CC1_SPEC. Its definition
1415 is an initializer with a subgrouping for each command option.
1416
1417 Each subgrouping contains a string constant, that defines the
1418 specification name, and a string constant that used by the GCC driver
1419 program.
1420
1421 Do not define this macro if it does not need to do anything. */
1422
1423 #define EXTRA_SPECS \
1424 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1425 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1426 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1427 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1428 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1429 { "endian_spec", ENDIAN_SPEC }, \
1430 SUBTARGET_EXTRA_SPECS
1431
1432 #ifndef SUBTARGET_EXTRA_SPECS
1433 #define SUBTARGET_EXTRA_SPECS
1434 #endif
1435 \f
1436 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1437 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1438
1439 #ifndef PREFERRED_DEBUGGING_TYPE
1440 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1441 #endif
1442
1443 /* The size of DWARF addresses should be the same as the size of symbols
1444 in the target file format. They shouldn't depend on things like -msym32,
1445 because many DWARF consumers do not allow the mixture of address sizes
1446 that one would then get from linking -msym32 code with -msym64 code.
1447
1448 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1449 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1450 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1451
1452 /* By default, turn on GDB extensions. */
1453 #define DEFAULT_GDB_EXTENSIONS 1
1454
1455 /* Registers may have a prefix which can be ignored when matching
1456 user asm and register definitions. */
1457 #ifndef REGISTER_PREFIX
1458 #define REGISTER_PREFIX "$"
1459 #endif
1460
1461 /* Local compiler-generated symbols must have a prefix that the assembler
1462 understands. By default, this is $, although some targets (e.g.,
1463 NetBSD-ELF) need to override this. */
1464
1465 #ifndef LOCAL_LABEL_PREFIX
1466 #define LOCAL_LABEL_PREFIX "$"
1467 #endif
1468
1469 /* By default on the mips, external symbols do not have an underscore
1470 prepended, but some targets (e.g., NetBSD) require this. */
1471
1472 #ifndef USER_LABEL_PREFIX
1473 #define USER_LABEL_PREFIX ""
1474 #endif
1475
1476 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1477 since the length can run past this up to a continuation point. */
1478 #undef DBX_CONTIN_LENGTH
1479 #define DBX_CONTIN_LENGTH 1500
1480
1481 /* How to renumber registers for dbx and gdb. */
1482 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1483
1484 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1485 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1486
1487 /* The DWARF 2 CFA column which tracks the return address. */
1488 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1489
1490 /* Before the prologue, RA lives in r31. */
1491 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1492
1493 /* Describe how we implement __builtin_eh_return. */
1494 #define EH_RETURN_DATA_REGNO(N) \
1495 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1496
1497 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1498
1499 #define EH_USES(N) mips_eh_uses (N)
1500
1501 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1502 The default for this in 64-bit mode is 8, which causes problems with
1503 SFmode register saves. */
1504 #define DWARF_CIE_DATA_ALIGNMENT -4
1505
1506 /* Correct the offset of automatic variables and arguments. Note that
1507 the MIPS debug format wants all automatic variables and arguments
1508 to be in terms of the virtual frame pointer (stack pointer before
1509 any adjustment in the function), while the MIPS 3.0 linker wants
1510 the frame pointer to be the stack pointer after the initial
1511 adjustment. */
1512
1513 #define DEBUGGER_AUTO_OFFSET(X) \
1514 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1515 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1516 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1517 \f
1518 /* Target machine storage layout */
1519
1520 #define BITS_BIG_ENDIAN 0
1521 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1522 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1523
1524 #define MAX_BITS_PER_WORD 64
1525
1526 /* Width of a word, in units (bytes). */
1527 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1528 #ifndef IN_LIBGCC2
1529 #define MIN_UNITS_PER_WORD 4
1530 #endif
1531
1532 /* Width of a MSA vector register in bytes. */
1533 #define UNITS_PER_MSA_REG 16
1534 /* Width of a MSA vector register in bits. */
1535 #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT)
1536
1537 /* For MIPS, width of a floating point register. */
1538 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1539
1540 /* The number of consecutive floating-point registers needed to store the
1541 largest format supported by the FPU. */
1542 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1543
1544 /* The number of consecutive floating-point registers needed to store the
1545 smallest format supported by the FPU. */
1546 #define MIN_FPRS_PER_FMT \
1547 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1548
1549 /* The largest size of value that can be held in floating-point
1550 registers and moved with a single instruction. */
1551 #define UNITS_PER_HWFPVALUE \
1552 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1553
1554 /* The largest size of value that can be held in floating-point
1555 registers. */
1556 #define UNITS_PER_FPVALUE \
1557 (TARGET_SOFT_FLOAT_ABI ? 0 \
1558 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1559 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1560
1561 /* The number of bytes in a double. */
1562 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1563
1564 /* Set the sizes of the core types. */
1565 #define SHORT_TYPE_SIZE 16
1566 #define INT_TYPE_SIZE 32
1567 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1568 #define LONG_LONG_TYPE_SIZE 64
1569
1570 #define FLOAT_TYPE_SIZE 32
1571 #define DOUBLE_TYPE_SIZE 64
1572 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1573
1574 /* Define the sizes of fixed-point types. */
1575 #define SHORT_FRACT_TYPE_SIZE 8
1576 #define FRACT_TYPE_SIZE 16
1577 #define LONG_FRACT_TYPE_SIZE 32
1578 #define LONG_LONG_FRACT_TYPE_SIZE 64
1579
1580 #define SHORT_ACCUM_TYPE_SIZE 16
1581 #define ACCUM_TYPE_SIZE 32
1582 #define LONG_ACCUM_TYPE_SIZE 64
1583 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1584 doesn't support 128-bit integers for MIPS32 currently. */
1585 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1586
1587 /* long double is not a fixed mode, but the idea is that, if we
1588 support long double, we also want a 128-bit integer type. */
1589 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1590
1591 /* Width in bits of a pointer. */
1592 #ifndef POINTER_SIZE
1593 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1594 #endif
1595
1596 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1597 #define PARM_BOUNDARY BITS_PER_WORD
1598
1599 /* Allocation boundary (in *bits*) for the code of a function. */
1600 #define FUNCTION_BOUNDARY 32
1601
1602 /* Alignment of field after `int : 0' in a structure. */
1603 #define EMPTY_FIELD_BOUNDARY 32
1604
1605 /* Every structure's size must be a multiple of this. */
1606 /* 8 is observed right on a DECstation and on riscos 4.02. */
1607 #define STRUCTURE_SIZE_BOUNDARY 8
1608
1609 /* There is no point aligning anything to a rounder boundary than
1610 LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is
1611 BITS_PER_MSA_REG. */
1612 #define BIGGEST_ALIGNMENT \
1613 (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE)
1614
1615 /* All accesses must be aligned. */
1616 #define STRICT_ALIGNMENT 1
1617
1618 /* Define this if you wish to imitate the way many other C compilers
1619 handle alignment of bitfields and the structures that contain
1620 them.
1621
1622 The behavior is that the type written for a bit-field (`int',
1623 `short', or other integer type) imposes an alignment for the
1624 entire structure, as if the structure really did contain an
1625 ordinary field of that type. In addition, the bit-field is placed
1626 within the structure so that it would fit within such a field,
1627 not crossing a boundary for it.
1628
1629 Thus, on most machines, a bit-field whose type is written as `int'
1630 would not cross a four-byte boundary, and would force four-byte
1631 alignment for the whole structure. (The alignment used may not
1632 be four bytes; it is controlled by the other alignment
1633 parameters.)
1634
1635 If the macro is defined, its definition should be a C expression;
1636 a nonzero value for the expression enables this behavior. */
1637
1638 #define PCC_BITFIELD_TYPE_MATTERS 1
1639
1640 /* If defined, a C expression to compute the alignment for a static
1641 variable. TYPE is the data type, and ALIGN is the alignment that
1642 the object would ordinarily have. The value of this macro is used
1643 instead of that alignment to align the object.
1644
1645 If this macro is not defined, then ALIGN is used.
1646
1647 One use of this macro is to increase alignment of medium-size
1648 data to make it all fit in fewer cache lines. Another is to
1649 cause character arrays to be word-aligned so that `strcpy' calls
1650 that copy constants to character arrays can be done inline. */
1651
1652 #undef DATA_ALIGNMENT
1653 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1654 ((((ALIGN) < BITS_PER_WORD) \
1655 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1656 || TREE_CODE (TYPE) == UNION_TYPE \
1657 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1658
1659 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1660 character arrays to be word-aligned so that `strcpy' calls that copy
1661 constants to character arrays can be done inline, and 'strcmp' can be
1662 optimised to use word loads. */
1663 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1664 DATA_ALIGNMENT (TYPE, ALIGN)
1665
1666 #define PAD_VARARGS_DOWN \
1667 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1668
1669 /* Define if operations between registers always perform the operation
1670 on the full register even if a narrower mode is specified. */
1671 #define WORD_REGISTER_OPERATIONS 1
1672
1673 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1674 moves. All other references are zero extended. */
1675 #define LOAD_EXTEND_OP(MODE) \
1676 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1677 ? SIGN_EXTEND : ZERO_EXTEND)
1678
1679 /* Define this macro if it is advisable to hold scalars in registers
1680 in a wider mode than that declared by the program. In such cases,
1681 the value is constrained to be within the bounds of the declared
1682 type, but kept valid in the wider mode. The signedness of the
1683 extension may differ from that of the type. */
1684
1685 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1686 if (GET_MODE_CLASS (MODE) == MODE_INT \
1687 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1688 { \
1689 if ((MODE) == SImode) \
1690 (UNSIGNEDP) = 0; \
1691 (MODE) = Pmode; \
1692 }
1693
1694 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1695 Extensions of pointers to word_mode must be signed. */
1696 #define POINTERS_EXTEND_UNSIGNED false
1697
1698 /* Define if loading short immediate values into registers sign extends. */
1699 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1700
1701 /* The [d]clz instructions have the natural values at 0. */
1702
1703 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1704 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1705 \f
1706 /* Standard register usage. */
1707
1708 /* Number of hardware registers. We have:
1709
1710 - 32 integer registers
1711 - 32 floating point registers
1712 - 8 condition code registers
1713 - 2 accumulator registers (hi and lo)
1714 - 32 registers each for coprocessors 0, 2 and 3
1715 - 4 fake registers:
1716 - ARG_POINTER_REGNUM
1717 - FRAME_POINTER_REGNUM
1718 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1719 - CPRESTORE_SLOT_REGNUM
1720 - 2 dummy entries that were used at various times in the past.
1721 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1722 - 6 DSP control registers */
1723
1724 #define FIRST_PSEUDO_REGISTER 188
1725
1726 /* By default, fix the kernel registers ($26 and $27), the global
1727 pointer ($28) and the stack pointer ($29). This can change
1728 depending on the command-line options.
1729
1730 Regarding coprocessor registers: without evidence to the contrary,
1731 it's best to assume that each coprocessor register has a unique
1732 use. This can be overridden, in, e.g., mips_option_override or
1733 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1734 inappropriate for a particular target. */
1735
1736 #define FIXED_REGISTERS \
1737 { \
1738 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1739 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1740 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1741 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1742 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1743 /* COP0 registers */ \
1744 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1745 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1746 /* COP2 registers */ \
1747 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1748 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1749 /* COP3 registers */ \
1750 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1751 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1752 /* 6 DSP accumulator registers & 6 control registers */ \
1753 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1754 }
1755
1756
1757 /* Set up this array for o32 by default.
1758
1759 Note that we don't mark $31 as a call-clobbered register. The idea is
1760 that it's really the call instructions themselves which clobber $31.
1761 We don't care what the called function does with it afterwards.
1762
1763 This approach makes it easier to implement sibcalls. Unlike normal
1764 calls, sibcalls don't clobber $31, so the register reaches the
1765 called function in tact. EPILOGUE_USES says that $31 is useful
1766 to the called function. */
1767
1768 #define CALL_USED_REGISTERS \
1769 { \
1770 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1771 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1772 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1773 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1774 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1775 /* COP0 registers */ \
1776 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1777 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1778 /* COP2 registers */ \
1779 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1780 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1781 /* COP3 registers */ \
1782 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1783 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1784 /* 6 DSP accumulator registers & 6 control registers */ \
1785 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1786 }
1787
1788
1789 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1790
1791 #define CALL_REALLY_USED_REGISTERS \
1792 { /* General registers. */ \
1793 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1794 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1795 /* Floating-point registers. */ \
1796 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1797 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1798 /* Others. */ \
1799 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1800 /* COP0 registers */ \
1801 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1802 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1803 /* COP2 registers */ \
1804 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1805 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1806 /* COP3 registers */ \
1807 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1808 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1809 /* 6 DSP accumulator registers & 6 control registers */ \
1810 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1811 }
1812
1813 /* Internal macros to classify a register number as to whether it's a
1814 general purpose register, a floating point register, a
1815 multiply/divide register, or a status register. */
1816
1817 #define GP_REG_FIRST 0
1818 #define GP_REG_LAST 31
1819 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1820 #define GP_DBX_FIRST 0
1821 #define K0_REG_NUM (GP_REG_FIRST + 26)
1822 #define K1_REG_NUM (GP_REG_FIRST + 27)
1823 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1824
1825 #define FP_REG_FIRST 32
1826 #define FP_REG_LAST 63
1827 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1828 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1829
1830 #define MD_REG_FIRST 64
1831 #define MD_REG_LAST 65
1832 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1833 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1834
1835 #define MSA_REG_FIRST FP_REG_FIRST
1836 #define MSA_REG_LAST FP_REG_LAST
1837 #define MSA_REG_NUM FP_REG_NUM
1838
1839 /* The DWARF 2 CFA column which tracks the return address from a
1840 signal handler context. This means that to maintain backwards
1841 compatibility, no hard register can be assigned this column if it
1842 would need to be handled by the DWARF unwinder. */
1843 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1844
1845 #define ST_REG_FIRST 67
1846 #define ST_REG_LAST 74
1847 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1848
1849
1850 /* FIXME: renumber. */
1851 #define COP0_REG_FIRST 80
1852 #define COP0_REG_LAST 111
1853 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1854
1855 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1856 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1857 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1858
1859 #define COP2_REG_FIRST 112
1860 #define COP2_REG_LAST 143
1861 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1862
1863 #define COP3_REG_FIRST 144
1864 #define COP3_REG_LAST 175
1865 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1866
1867 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1868 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1869 #define ALL_COP_REG_LAST COP3_REG_LAST
1870 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1871
1872 #define DSP_ACC_REG_FIRST 176
1873 #define DSP_ACC_REG_LAST 181
1874 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1875
1876 #define AT_REGNUM (GP_REG_FIRST + 1)
1877 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1878 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1879
1880 /* A few bitfield locations for the coprocessor registers. */
1881 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1882 the cause register for the EIC interrupt mode. */
1883 #define CAUSE_IPL 10
1884 /* COP1 Enable is at bit 29 of the status register. */
1885 #define SR_COP1 29
1886 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1887 #define SR_IPL 10
1888 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status
1889 register. */
1890 #define SR_IM0 8
1891 /* Exception Level is at bit 1 of the status register. */
1892 #define SR_EXL 1
1893 /* Interrupt Enable is at bit 0 of the status register. */
1894 #define SR_IE 0
1895
1896 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1897 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1898 should be used instead. */
1899 #define FPSW_REGNUM ST_REG_FIRST
1900
1901 #define GP_REG_P(REGNO) \
1902 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1903 #define M16_REG_P(REGNO) \
1904 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1905 #define M16STORE_REG_P(REGNO) \
1906 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1907 #define FP_REG_P(REGNO) \
1908 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1909 #define MD_REG_P(REGNO) \
1910 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1911 #define ST_REG_P(REGNO) \
1912 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1913 #define COP0_REG_P(REGNO) \
1914 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1915 #define COP2_REG_P(REGNO) \
1916 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1917 #define COP3_REG_P(REGNO) \
1918 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1919 #define ALL_COP_REG_P(REGNO) \
1920 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1921 /* Test if REGNO is one of the 6 new DSP accumulators. */
1922 #define DSP_ACC_REG_P(REGNO) \
1923 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1924 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1925 #define ACC_REG_P(REGNO) \
1926 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1927 #define MSA_REG_P(REGNO) \
1928 ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM)
1929
1930 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1931 #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X)))
1932
1933 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1934 to initialize the mips16 gp pseudo register. */
1935 #define CONST_GP_P(X) \
1936 (GET_CODE (X) == CONST \
1937 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1938 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1939
1940 /* Return coprocessor number from register number. */
1941
1942 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1943 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1944 : COP3_REG_P (REGNO) ? '3' : '?')
1945
1946
1947 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1948 mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
1949
1950 /* Select a register mode required for caller save of hard regno REGNO. */
1951 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1952 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1953
1954 /* Register to use for pushing function arguments. */
1955 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1956
1957 /* These two registers don't really exist: they get eliminated to either
1958 the stack or hard frame pointer. */
1959 #define ARG_POINTER_REGNUM 77
1960 #define FRAME_POINTER_REGNUM 78
1961
1962 /* $30 is not available on the mips16, so we use $17 as the frame
1963 pointer. */
1964 #define HARD_FRAME_POINTER_REGNUM \
1965 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1966
1967 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1968 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1969
1970 /* Register in which static-chain is passed to a function. */
1971 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1972
1973 /* Registers used as temporaries in prologue/epilogue code:
1974
1975 - If a MIPS16 PIC function needs access to _gp, it first loads
1976 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1977
1978 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1979 register. The register must not conflict with MIPS16_PIC_TEMP.
1980
1981 - If we aren't generating MIPS16 code, the prologue can also use
1982 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1983
1984 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1985 register.
1986
1987 If we're generating MIPS16 code, these registers must come from the
1988 core set of 8. The prologue registers mustn't conflict with any
1989 incoming arguments, the static chain pointer, or the frame pointer.
1990 The epilogue temporary mustn't conflict with the return registers,
1991 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1992 or the EH data registers.
1993
1994 If we're generating interrupt handlers, we use K0 as a temporary register
1995 in prologue/epilogue code. */
1996
1997 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1998 #define MIPS_PROLOGUE_TEMP_REGNUM \
1999 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
2000 #define MIPS_PROLOGUE_TEMP2_REGNUM \
2001 (TARGET_MIPS16 \
2002 ? (gcc_unreachable (), INVALID_REGNUM) \
2003 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
2004 #define MIPS_EPILOGUE_TEMP_REGNUM \
2005 (cfun->machine->interrupt_handler_p \
2006 ? K0_REG_NUM \
2007 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
2008
2009 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
2010 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
2011 #define MIPS_PROLOGUE_TEMP2(MODE) \
2012 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
2013 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
2014
2015 /* Define this macro if it is as good or better to call a constant
2016 function address than to call an address kept in a register. */
2017 #define NO_FUNCTION_CSE 1
2018
2019 /* The ABI-defined global pointer. Sometimes we use a different
2020 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
2021 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
2022
2023 /* We normally use $28 as the global pointer. However, when generating
2024 n32/64 PIC, it is better for leaf functions to use a call-clobbered
2025 register instead. They can then avoid saving and restoring $28
2026 and perhaps avoid using a frame at all.
2027
2028 When a leaf function uses something other than $28, mips_expand_prologue
2029 will modify pic_offset_table_rtx in place. Take the register number
2030 from there after reload. */
2031 #define PIC_OFFSET_TABLE_REGNUM \
2032 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
2033 \f
2034 /* Define the classes of registers for register constraints in the
2035 machine description. Also define ranges of constants.
2036
2037 One of the classes must always be named ALL_REGS and include all hard regs.
2038 If there is more than one class, another class must be named NO_REGS
2039 and contain no registers.
2040
2041 The name GENERAL_REGS must be the name of a class (or an alias for
2042 another name such as ALL_REGS). This is the class of registers
2043 that is allowed by "g" or "r" in a register constraint.
2044 Also, registers outside this class are allocated only when
2045 instructions express preferences for them.
2046
2047 The classes must be numbered in nondecreasing order; that is,
2048 a larger-numbered class must never be contained completely
2049 in a smaller-numbered class.
2050
2051 For any two classes, it is very desirable that there be another
2052 class that represents their union. */
2053
2054 enum reg_class
2055 {
2056 NO_REGS, /* no registers in set */
2057 M16_STORE_REGS, /* microMIPS store registers */
2058 M16_REGS, /* mips16 directly accessible registers */
2059 M16_SP_REGS, /* mips16 + $sp */
2060 T_REG, /* mips16 T register ($24) */
2061 M16_T_REGS, /* mips16 registers plus T register */
2062 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2063 V1_REG, /* Register $v1 ($3) used for TLS access. */
2064 SPILL_REGS, /* All but $sp and call preserved regs are in here */
2065 LEA_REGS, /* Every GPR except $25 */
2066 GR_REGS, /* integer registers */
2067 FP_REGS, /* floating point registers */
2068 MD0_REG, /* first multiply/divide register */
2069 MD1_REG, /* second multiply/divide register */
2070 MD_REGS, /* multiply/divide registers (hi/lo) */
2071 COP0_REGS, /* generic coprocessor classes */
2072 COP2_REGS,
2073 COP3_REGS,
2074 ST_REGS, /* status registers (fp status) */
2075 DSP_ACC_REGS, /* DSP accumulator registers */
2076 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
2077 FRAME_REGS, /* $arg and $frame */
2078 GR_AND_MD0_REGS, /* union classes */
2079 GR_AND_MD1_REGS,
2080 GR_AND_MD_REGS,
2081 GR_AND_ACC_REGS,
2082 ALL_REGS, /* all registers */
2083 LIM_REG_CLASSES /* max value + 1 */
2084 };
2085
2086 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2087
2088 #define GENERAL_REGS GR_REGS
2089
2090 /* An initializer containing the names of the register classes as C
2091 string constants. These names are used in writing some of the
2092 debugging dumps. */
2093
2094 #define REG_CLASS_NAMES \
2095 { \
2096 "NO_REGS", \
2097 "M16_STORE_REGS", \
2098 "M16_REGS", \
2099 "M16_SP_REGS", \
2100 "T_REG", \
2101 "M16_T_REGS", \
2102 "PIC_FN_ADDR_REG", \
2103 "V1_REG", \
2104 "SPILL_REGS", \
2105 "LEA_REGS", \
2106 "GR_REGS", \
2107 "FP_REGS", \
2108 "MD0_REG", \
2109 "MD1_REG", \
2110 "MD_REGS", \
2111 /* coprocessor registers */ \
2112 "COP0_REGS", \
2113 "COP2_REGS", \
2114 "COP3_REGS", \
2115 "ST_REGS", \
2116 "DSP_ACC_REGS", \
2117 "ACC_REGS", \
2118 "FRAME_REGS", \
2119 "GR_AND_MD0_REGS", \
2120 "GR_AND_MD1_REGS", \
2121 "GR_AND_MD_REGS", \
2122 "GR_AND_ACC_REGS", \
2123 "ALL_REGS" \
2124 }
2125
2126 /* An initializer containing the contents of the register classes,
2127 as integers which are bit masks. The Nth integer specifies the
2128 contents of class N. The way the integer MASK is interpreted is
2129 that register R is in the class if `MASK & (1 << R)' is 1.
2130
2131 When the machine has more than 32 registers, an integer does not
2132 suffice. Then the integers are replaced by sub-initializers,
2133 braced groupings containing several integers. Each
2134 sub-initializer must be suitable as an initializer for the type
2135 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2136
2137 #define REG_CLASS_CONTENTS \
2138 { \
2139 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2140 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2141 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2142 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2143 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2144 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2145 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2146 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2147 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2148 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2149 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2150 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2151 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2152 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2153 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2154 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2155 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2156 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2157 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2158 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2159 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2160 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2161 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2162 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2163 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2164 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2165 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2166 }
2167
2168
2169 /* A C expression whose value is a register class containing hard
2170 register REGNO. In general there is more that one such class;
2171 choose a class which is "minimal", meaning that no smaller class
2172 also contains the register. */
2173
2174 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2175
2176 /* A macro whose definition is the name of the class to which a
2177 valid base register must belong. A base register is one used in
2178 an address which is the register value plus a displacement. */
2179
2180 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2181
2182 /* A macro whose definition is the name of the class to which a
2183 valid index register must belong. An index register is one used
2184 in an address where its value is either multiplied by a scale
2185 factor or added to another register (as well as added to a
2186 displacement). */
2187
2188 #define INDEX_REG_CLASS NO_REGS
2189
2190 /* We generally want to put call-clobbered registers ahead of
2191 call-saved ones. (IRA expects this.) */
2192
2193 #define REG_ALLOC_ORDER \
2194 { /* Accumulator registers. When GPRs and accumulators have equal \
2195 cost, we generally prefer to use accumulators. For example, \
2196 a division of multiplication result is better allocated to LO, \
2197 so that we put the MFLO at the point of use instead of at the \
2198 point of definition. It's also needed if we're to take advantage \
2199 of the extra accumulators available with -mdspr2. In some cases, \
2200 it can also help to reduce register pressure. */ \
2201 64, 65,176,177,178,179,180,181, \
2202 /* Call-clobbered GPRs. */ \
2203 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2204 24, 25, 31, \
2205 /* The global pointer. This is call-clobbered for o32 and o64 \
2206 abicalls, call-saved for n32 and n64 abicalls, and a program \
2207 invariant otherwise. Putting it between the call-clobbered \
2208 and call-saved registers should cope with all eventualities. */ \
2209 28, \
2210 /* Call-saved GPRs. */ \
2211 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2212 /* GPRs that can never be exposed to the register allocator. */ \
2213 0, 26, 27, 29, \
2214 /* Call-clobbered FPRs. */ \
2215 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2216 48, 49, 50, 51, \
2217 /* FPRs that are usually call-saved. The odd ones are actually \
2218 call-clobbered for n32, but listing them ahead of the even \
2219 registers might encourage the register allocator to fragment \
2220 the available FPR pairs. We need paired FPRs to store long \
2221 doubles, so it isn't clear that using a different order \
2222 for n32 would be a win. */ \
2223 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2224 /* None of the remaining classes have defined call-saved \
2225 registers. */ \
2226 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2227 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2228 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2229 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2230 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2231 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2232 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2233 182,183,184,185,186,187 \
2234 }
2235
2236 /* True if VALUE is an unsigned 6-bit number. */
2237
2238 #define UIMM6_OPERAND(VALUE) \
2239 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2240
2241 /* True if VALUE is a signed 10-bit number. */
2242
2243 #define IMM10_OPERAND(VALUE) \
2244 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2245
2246 /* True if VALUE is a signed 16-bit number. */
2247
2248 #define SMALL_OPERAND(VALUE) \
2249 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2250
2251 /* True if VALUE is an unsigned 16-bit number. */
2252
2253 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2254 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2255
2256 /* True if VALUE can be loaded into a register using LUI. */
2257
2258 #define LUI_OPERAND(VALUE) \
2259 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2260 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2261
2262 /* Return a value X with the low 16 bits clear, and such that
2263 VALUE - X is a signed 16-bit value. */
2264
2265 #define CONST_HIGH_PART(VALUE) \
2266 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2267
2268 #define CONST_LOW_PART(VALUE) \
2269 ((VALUE) - CONST_HIGH_PART (VALUE))
2270
2271 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2272 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2273 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2274 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2275 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2276
2277 /* The HI and LO registers can only be reloaded via the general
2278 registers. Condition code registers can only be loaded to the
2279 general registers, and from the floating point registers. */
2280
2281 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2282 mips_secondary_reload_class (CLASS, MODE, X, true)
2283 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2284 mips_secondary_reload_class (CLASS, MODE, X, false)
2285
2286 /* Return the maximum number of consecutive registers
2287 needed to represent mode MODE in a register of class CLASS. */
2288
2289 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2290 \f
2291 /* Stack layout; function entry, exit and calling. */
2292
2293 #define STACK_GROWS_DOWNWARD 1
2294
2295 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
2296 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
2297
2298 /* Size of the area allocated in the frame to save the GP. */
2299
2300 #define MIPS_GP_SAVE_AREA_SIZE \
2301 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2302
2303 #define RETURN_ADDR_RTX mips_return_addr
2304
2305 /* Mask off the MIPS16 ISA bit in unwind addresses.
2306
2307 The reason for this is a little subtle. When unwinding a call,
2308 we are given the call's return address, which on most targets
2309 is the address of the following instruction. However, what we
2310 actually want to find is the EH region for the call itself.
2311 The target-independent unwind code therefore searches for "RA - 1".
2312
2313 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2314 RA - 1 is therefore the real (even-valued) start of the return
2315 instruction. EH region labels are usually odd-valued MIPS16 symbols
2316 too, so a search for an even address within a MIPS16 region would
2317 usually work.
2318
2319 However, there is an exception. If the end of an EH region is also
2320 the end of a function, the end label is allowed to be even. This is
2321 necessary because a following non-MIPS16 function may also need EH
2322 information for its first instruction.
2323
2324 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2325 non-ISA-encoded address. This probably isn't ideal, but it is
2326 the traditional (legacy) behavior. It is therefore only safe
2327 to search MIPS EH regions for an _odd-valued_ address.
2328
2329 Masking off the ISA bit means that the target-independent code
2330 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2331 #define MASK_RETURN_ADDR GEN_INT (-2)
2332
2333
2334 /* Similarly, don't use the least-significant bit to tell pointers to
2335 code from vtable index. */
2336
2337 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2338
2339 /* The eliminations to $17 are only used for mips16 code. See the
2340 definition of HARD_FRAME_POINTER_REGNUM. */
2341
2342 #define ELIMINABLE_REGS \
2343 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2344 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2345 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2346 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2347 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2348 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2349
2350 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2351 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2352
2353 /* Allocate stack space for arguments at the beginning of each function. */
2354 #define ACCUMULATE_OUTGOING_ARGS 1
2355
2356 /* The argument pointer always points to the first argument. */
2357 #define FIRST_PARM_OFFSET(FNDECL) 0
2358
2359 /* o32 and o64 reserve stack space for all argument registers. */
2360 #define REG_PARM_STACK_SPACE(FNDECL) \
2361 (TARGET_OLDABI \
2362 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2363 : 0)
2364
2365 /* Define this if it is the responsibility of the caller to
2366 allocate the area reserved for arguments passed in registers.
2367 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2368 of this macro is to determine whether the space is included in
2369 `crtl->outgoing_args_size'. */
2370 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2371
2372 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2373 \f
2374 /* Symbolic macros for the registers used to return integer and floating
2375 point values. */
2376
2377 #define GP_RETURN (GP_REG_FIRST + 2)
2378 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2379
2380 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2381
2382 /* Symbolic macros for the first/last argument registers. */
2383
2384 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2385 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2386 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2387 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2388
2389 /* True if MODE is vector and supported in a MSA vector register. */
2390 #define MSA_SUPPORTED_MODE_P(MODE) \
2391 (ISA_HAS_MSA \
2392 && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \
2393 && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
2394 || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT))
2395
2396 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2397 are used for returning complex double values in soft-float code, so $6 is the
2398 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2399 $gp itself as the temporary. */
2400 #define POST_CALL_TMP_REG \
2401 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2402
2403 /* 1 if N is a possible register number for function argument passing.
2404 We have no FP argument registers when soft-float. Special handling
2405 is required for O32 where only even numbered registers are used for
2406 O32-FPXX and O32-FP64. */
2407
2408 #define FUNCTION_ARG_REGNO_P(N) \
2409 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2410 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2411 && (mips_abi != ABI_32 \
2412 || TARGET_FLOAT32 \
2413 || ((N) % 2 == 0)))) \
2414 && !fixed_regs[N])
2415 \f
2416 /* This structure has to cope with two different argument allocation
2417 schemes. Most MIPS ABIs view the arguments as a structure, of which
2418 the first N words go in registers and the rest go on the stack. If I
2419 < N, the Ith word might go in Ith integer argument register or in a
2420 floating-point register. For these ABIs, we only need to remember
2421 the offset of the current argument into the structure.
2422
2423 The EABI instead allocates the integer and floating-point arguments
2424 separately. The first N words of FP arguments go in FP registers,
2425 the rest go on the stack. Likewise, the first N words of the other
2426 arguments go in integer registers, and the rest go on the stack. We
2427 need to maintain three counts: the number of integer registers used,
2428 the number of floating-point registers used, and the number of words
2429 passed on the stack.
2430
2431 We could keep separate information for the two ABIs (a word count for
2432 the standard ABIs, and three separate counts for the EABI). But it
2433 seems simpler to view the standard ABIs as forms of EABI that do not
2434 allocate floating-point registers.
2435
2436 So for the standard ABIs, the first N words are allocated to integer
2437 registers, and mips_function_arg decides on an argument-by-argument
2438 basis whether that argument should really go in an integer register,
2439 or in a floating-point one. */
2440
2441 typedef struct mips_args {
2442 /* Always true for varargs functions. Otherwise true if at least
2443 one argument has been passed in an integer register. */
2444 int gp_reg_found;
2445
2446 /* The number of arguments seen so far. */
2447 unsigned int arg_number;
2448
2449 /* The number of integer registers used so far. For all ABIs except
2450 EABI, this is the number of words that have been added to the
2451 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2452 unsigned int num_gprs;
2453
2454 /* For EABI, the number of floating-point registers used so far. */
2455 unsigned int num_fprs;
2456
2457 /* The number of words passed on the stack. */
2458 unsigned int stack_words;
2459
2460 /* On the mips16, we need to keep track of which floating point
2461 arguments were passed in general registers, but would have been
2462 passed in the FP regs if this were a 32-bit function, so that we
2463 can move them to the FP regs if we wind up calling a 32-bit
2464 function. We record this information in fp_code, encoded in base
2465 four. A zero digit means no floating point argument, a one digit
2466 means an SFmode argument, and a two digit means a DFmode argument,
2467 and a three digit is not used. The low order digit is the first
2468 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2469 an SFmode argument. ??? A more sophisticated approach will be
2470 needed if MIPS_ABI != ABI_32. */
2471 int fp_code;
2472
2473 /* True if the function has a prototype. */
2474 int prototype;
2475 } CUMULATIVE_ARGS;
2476
2477 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2478 for a call to a function whose data type is FNTYPE.
2479 For a library call, FNTYPE is 0. */
2480
2481 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2482 mips_init_cumulative_args (&CUM, FNTYPE)
2483
2484 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2485 (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD)
2486
2487 /* True if using EABI and varargs can be passed in floating-point
2488 registers. Under these conditions, we need a more complex form
2489 of va_list, which tracks GPR, FPR and stack arguments separately. */
2490 #define EABI_FLOAT_VARARGS_P \
2491 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2492
2493 \f
2494 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2495
2496 /* Treat LOC as a byte offset from the stack pointer and round it up
2497 to the next fully-aligned offset. */
2498 #define MIPS_STACK_ALIGN(LOC) \
2499 (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
2500
2501 \f
2502 /* Output assembler code to FILE to increment profiler label # LABELNO
2503 for profiling a function entry. */
2504
2505 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2506
2507 /* The profiler preserves all interesting registers, including $31. */
2508 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2509
2510 /* No mips port has ever used the profiler counter word, so don't emit it
2511 or the label for it. */
2512
2513 #define NO_PROFILE_COUNTERS 1
2514
2515 /* Define this macro if the code for function profiling should come
2516 before the function prologue. Normally, the profiling code comes
2517 after. */
2518
2519 /* #define PROFILE_BEFORE_PROLOGUE */
2520
2521 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2522 the stack pointer does not matter. The value is tested only in
2523 functions that have frame pointers.
2524 No definition is equivalent to always zero. */
2525
2526 #define EXIT_IGNORE_STACK 1
2527
2528 \f
2529 /* Trampolines are a block of code followed by two pointers. */
2530
2531 #define TRAMPOLINE_SIZE \
2532 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2533
2534 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2535 pointers from a single LUI base. */
2536
2537 #define TRAMPOLINE_ALIGNMENT 64
2538
2539 /* mips_trampoline_init calls this library function to flush
2540 program and data caches. */
2541
2542 #ifndef CACHE_FLUSH_FUNC
2543 #define CACHE_FLUSH_FUNC "_flush_cache"
2544 #endif
2545
2546 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2547 /* Flush both caches. We need to flush the data cache in case \
2548 the system has a write-back cache. */ \
2549 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2550 LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \
2551 GEN_INT (3), TYPE_MODE (integer_type_node))
2552
2553 \f
2554 /* Addressing modes, and classification of registers for them. */
2555
2556 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2557 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2558 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2559 \f
2560 /* Maximum number of registers that can appear in a valid memory address. */
2561
2562 #define MAX_REGS_PER_ADDRESS 1
2563
2564 /* Check for constness inline but use mips_legitimate_address_p
2565 to check whether a constant really is an address. */
2566
2567 #define CONSTANT_ADDRESS_P(X) \
2568 (CONSTANT_P (X) && memory_address_p (SImode, X))
2569
2570 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2571 'the start of the function that this code is output in'. */
2572
2573 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2574 do { \
2575 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2576 asm_fprintf ((FILE), "%U%s", \
2577 XSTR (XEXP (DECL_RTL (current_function_decl), \
2578 0), 0)); \
2579 else \
2580 asm_fprintf ((FILE), "%U%s", (NAME)); \
2581 } while (0)
2582 \f
2583 /* Flag to mark a function decl symbol that requires a long call. */
2584 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2585 #define SYMBOL_REF_LONG_CALL_P(X) \
2586 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2587
2588 /* This flag marks functions that cannot be lazily bound. */
2589 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2590 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2591 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2592
2593 /* True if we're generating a form of MIPS16 code in which jump tables
2594 are stored in the text section and encoded as 16-bit PC-relative
2595 offsets. This is only possible when general text loads are allowed,
2596 since the table access itself will be an "lh" instruction. If the
2597 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2598 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2599
2600 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2601
2602 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2603
2604 /* Only use short offsets if their range will not overflow. */
2605 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2606 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2607 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2608 : SImode)
2609
2610 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2611
2612 /* Define this as 1 if `char' should by default be signed; else as 0. */
2613 #ifndef DEFAULT_SIGNED_CHAR
2614 #define DEFAULT_SIGNED_CHAR 1
2615 #endif
2616
2617 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2618 we generally don't want to use them for copying arbitrary data.
2619 A single N-word move is usually the same cost as N single-word moves. */
2620 #define MOVE_MAX UNITS_PER_WORD
2621 /* We don't modify it for MSA as it is only used by the classic reload. */
2622 #define MAX_MOVE_MAX 8
2623
2624 /* Define this macro as a C expression which is nonzero if
2625 accessing less than a word of memory (i.e. a `char' or a
2626 `short') is no faster than accessing a word of memory, i.e., if
2627 such access require more than one instruction or if there is no
2628 difference in cost between byte and (aligned) word loads.
2629
2630 On RISC machines, it tends to generate better code to define
2631 this as 1, since it avoids making a QI or HI mode register.
2632
2633 But, generating word accesses for -mips16 is generally bad as shifts
2634 (often extended) would be needed for byte accesses. */
2635 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2636
2637 /* Standard MIPS integer shifts truncate the shift amount to the
2638 width of the shifted operand. However, Loongson vector shifts
2639 do not truncate the shift amount at all. */
2640 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2641
2642
2643 /* Specify the machine mode that pointers have.
2644 After generation of rtl, the compiler makes no further distinction
2645 between pointers and any other objects of this machine mode. */
2646
2647 #ifndef Pmode
2648 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2649 #endif
2650
2651 /* Give call MEMs SImode since it is the "most permissive" mode
2652 for both 32-bit and 64-bit targets. */
2653
2654 #define FUNCTION_MODE SImode
2655
2656 \f
2657 /* We allocate $fcc registers by hand and can't cope with moves of
2658 CCmode registers to and from pseudos (or memory). */
2659 #define AVOID_CCMODE_COPIES
2660
2661 /* A C expression for the cost of a branch instruction. A value of
2662 1 is the default; other values are interpreted relative to that. */
2663
2664 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2665 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2666
2667 /* The MIPS port has several functions that return an instruction count.
2668 Multiplying the count by this value gives the number of bytes that
2669 the instructions occupy. */
2670 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2671
2672 /* The length of a NOP in bytes. */
2673 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2674
2675 /* If defined, modifies the length assigned to instruction INSN as a
2676 function of the context in which it is used. LENGTH is an lvalue
2677 that contains the initially computed length of the insn and should
2678 be updated with the correct length of the insn. */
2679 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2680 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2681
2682 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2683 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2684 its operands. */
2685 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2686 "%*" OPCODE "%?\t" OPERANDS "%/"
2687
2688 #define MIPS_BRANCH_C(OPCODE, OPERANDS) \
2689 "%*" OPCODE "%:\t" OPERANDS
2690
2691 /* Return an asm string that forces INSN to be treated as an absolute
2692 J or JAL instruction instead of an assembler macro. */
2693 #define MIPS_ABSOLUTE_JUMP(INSN) \
2694 (TARGET_ABICALLS_PIC2 \
2695 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2696 : INSN)
2697
2698 \f
2699 /* Control the assembler format that we output. */
2700
2701 /* Output to assembler file text saying following lines
2702 may contain character constants, extra white space, comments, etc. */
2703
2704 #ifndef ASM_APP_ON
2705 #define ASM_APP_ON " #APP\n"
2706 #endif
2707
2708 /* Output to assembler file text saying following lines
2709 no longer contain unusual constructs. */
2710
2711 #ifndef ASM_APP_OFF
2712 #define ASM_APP_OFF " #NO_APP\n"
2713 #endif
2714
2715 #define REGISTER_NAMES \
2716 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2717 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2718 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2719 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2720 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2721 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2722 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2723 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2724 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2725 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2726 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2727 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2728 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2729 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2730 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2731 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2732 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2733 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2734 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2735 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2736 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2737 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2738 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2739 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2740
2741 /* List the "software" names for each register. Also list the numerical
2742 names for $fp and $sp. */
2743
2744 #define ADDITIONAL_REGISTER_NAMES \
2745 { \
2746 { "$29", 29 + GP_REG_FIRST }, \
2747 { "$30", 30 + GP_REG_FIRST }, \
2748 { "at", 1 + GP_REG_FIRST }, \
2749 { "v0", 2 + GP_REG_FIRST }, \
2750 { "v1", 3 + GP_REG_FIRST }, \
2751 { "a0", 4 + GP_REG_FIRST }, \
2752 { "a1", 5 + GP_REG_FIRST }, \
2753 { "a2", 6 + GP_REG_FIRST }, \
2754 { "a3", 7 + GP_REG_FIRST }, \
2755 { "t0", 8 + GP_REG_FIRST }, \
2756 { "t1", 9 + GP_REG_FIRST }, \
2757 { "t2", 10 + GP_REG_FIRST }, \
2758 { "t3", 11 + GP_REG_FIRST }, \
2759 { "t4", 12 + GP_REG_FIRST }, \
2760 { "t5", 13 + GP_REG_FIRST }, \
2761 { "t6", 14 + GP_REG_FIRST }, \
2762 { "t7", 15 + GP_REG_FIRST }, \
2763 { "s0", 16 + GP_REG_FIRST }, \
2764 { "s1", 17 + GP_REG_FIRST }, \
2765 { "s2", 18 + GP_REG_FIRST }, \
2766 { "s3", 19 + GP_REG_FIRST }, \
2767 { "s4", 20 + GP_REG_FIRST }, \
2768 { "s5", 21 + GP_REG_FIRST }, \
2769 { "s6", 22 + GP_REG_FIRST }, \
2770 { "s7", 23 + GP_REG_FIRST }, \
2771 { "t8", 24 + GP_REG_FIRST }, \
2772 { "t9", 25 + GP_REG_FIRST }, \
2773 { "k0", 26 + GP_REG_FIRST }, \
2774 { "k1", 27 + GP_REG_FIRST }, \
2775 { "gp", 28 + GP_REG_FIRST }, \
2776 { "sp", 29 + GP_REG_FIRST }, \
2777 { "fp", 30 + GP_REG_FIRST }, \
2778 { "ra", 31 + GP_REG_FIRST }, \
2779 { "$w0", 0 + FP_REG_FIRST }, \
2780 { "$w1", 1 + FP_REG_FIRST }, \
2781 { "$w2", 2 + FP_REG_FIRST }, \
2782 { "$w3", 3 + FP_REG_FIRST }, \
2783 { "$w4", 4 + FP_REG_FIRST }, \
2784 { "$w5", 5 + FP_REG_FIRST }, \
2785 { "$w6", 6 + FP_REG_FIRST }, \
2786 { "$w7", 7 + FP_REG_FIRST }, \
2787 { "$w8", 8 + FP_REG_FIRST }, \
2788 { "$w9", 9 + FP_REG_FIRST }, \
2789 { "$w10", 10 + FP_REG_FIRST }, \
2790 { "$w11", 11 + FP_REG_FIRST }, \
2791 { "$w12", 12 + FP_REG_FIRST }, \
2792 { "$w13", 13 + FP_REG_FIRST }, \
2793 { "$w14", 14 + FP_REG_FIRST }, \
2794 { "$w15", 15 + FP_REG_FIRST }, \
2795 { "$w16", 16 + FP_REG_FIRST }, \
2796 { "$w17", 17 + FP_REG_FIRST }, \
2797 { "$w18", 18 + FP_REG_FIRST }, \
2798 { "$w19", 19 + FP_REG_FIRST }, \
2799 { "$w20", 20 + FP_REG_FIRST }, \
2800 { "$w21", 21 + FP_REG_FIRST }, \
2801 { "$w22", 22 + FP_REG_FIRST }, \
2802 { "$w23", 23 + FP_REG_FIRST }, \
2803 { "$w24", 24 + FP_REG_FIRST }, \
2804 { "$w25", 25 + FP_REG_FIRST }, \
2805 { "$w26", 26 + FP_REG_FIRST }, \
2806 { "$w27", 27 + FP_REG_FIRST }, \
2807 { "$w28", 28 + FP_REG_FIRST }, \
2808 { "$w29", 29 + FP_REG_FIRST }, \
2809 { "$w30", 30 + FP_REG_FIRST }, \
2810 { "$w31", 31 + FP_REG_FIRST } \
2811 }
2812
2813 #define DBR_OUTPUT_SEQEND(STREAM) \
2814 do \
2815 { \
2816 /* Undo the effect of '%*'. */ \
2817 mips_pop_asm_switch (&mips_nomacro); \
2818 mips_pop_asm_switch (&mips_noreorder); \
2819 /* Emit a blank line after the delay slot for emphasis. */ \
2820 fputs ("\n", STREAM); \
2821 } \
2822 while (0)
2823
2824 /* The MIPS implementation uses some labels for its own purpose. The
2825 following lists what labels are created, and are all formed by the
2826 pattern $L[a-z].*. The machine independent portion of GCC creates
2827 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2828
2829 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2830 $Lb[0-9]+ Begin blocks for MIPS debug support
2831 $Lc[0-9]+ Label for use in s<xx> operation.
2832 $Le[0-9]+ End blocks for MIPS debug support */
2833
2834 #undef ASM_DECLARE_OBJECT_NAME
2835 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2836 mips_declare_object (STREAM, NAME, "", ":\n")
2837
2838 /* Globalizing directive for a label. */
2839 #define GLOBAL_ASM_OP "\t.globl\t"
2840
2841 /* This says how to define a global common symbol. */
2842
2843 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2844
2845 /* This says how to define a local common symbol (i.e., not visible to
2846 linker). */
2847
2848 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2849 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2850 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2851 #endif
2852
2853 /* This says how to output an external. It would be possible not to
2854 output anything and let undefined symbol become external. However
2855 the assembler uses length information on externals to allocate in
2856 data/sdata bss/sbss, thereby saving exec time. */
2857
2858 #undef ASM_OUTPUT_EXTERNAL
2859 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2860 mips_output_external(STREAM,DECL,NAME)
2861
2862 /* This is how to declare a function name. The actual work of
2863 emitting the label is moved to function_prologue, so that we can
2864 get the line number correctly emitted before the .ent directive,
2865 and after any .file directives. Define as empty so that the function
2866 is not declared before the .ent directive elsewhere. */
2867
2868 #undef ASM_DECLARE_FUNCTION_NAME
2869 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2870
2871 /* This is how to store into the string LABEL
2872 the symbol_ref name of an internal numbered label where
2873 PREFIX is the class of label and NUM is the number within the class.
2874 This is suitable for output with `assemble_name'. */
2875
2876 #undef ASM_GENERATE_INTERNAL_LABEL
2877 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2878 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2879
2880 /* Print debug labels as "foo = ." rather than "foo:" because they should
2881 represent a byte pointer rather than an ISA-encoded address. This is
2882 particularly important for code like:
2883
2884 $LFBxxx = .
2885 .cfi_startproc
2886 ...
2887 .section .gcc_except_table,...
2888 ...
2889 .uleb128 foo-$LFBxxx
2890
2891 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2892 likewise a byte pointer rather than an ISA-encoded address.
2893
2894 At the time of writing, this hook is not used for the function end
2895 label:
2896
2897 $LFExxx:
2898 .end foo
2899
2900 But this doesn't matter, because GAS doesn't treat a pre-.end label
2901 as a MIPS16 one anyway. */
2902
2903 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2904 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2905
2906 /* This is how to output an element of a case-vector that is absolute. */
2907
2908 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2909 fprintf (STREAM, "\t%s\t%sL%d\n", \
2910 ptr_mode == DImode ? ".dword" : ".word", \
2911 LOCAL_LABEL_PREFIX, \
2912 VALUE)
2913
2914 /* This is how to output an element of a case-vector. We can make the
2915 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2916 is supported. */
2917
2918 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2919 do { \
2920 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2921 { \
2922 if (GET_MODE (BODY) == HImode) \
2923 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2924 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2925 else \
2926 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2927 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2928 } \
2929 else if (TARGET_GPWORD) \
2930 fprintf (STREAM, "\t%s\t%sL%d\n", \
2931 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2932 LOCAL_LABEL_PREFIX, VALUE); \
2933 else if (TARGET_RTP_PIC) \
2934 { \
2935 /* Make the entry relative to the start of the function. */ \
2936 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2937 fprintf (STREAM, "\t%s\t%sL%d-", \
2938 Pmode == DImode ? ".dword" : ".word", \
2939 LOCAL_LABEL_PREFIX, VALUE); \
2940 assemble_name (STREAM, XSTR (fnsym, 0)); \
2941 fprintf (STREAM, "\n"); \
2942 } \
2943 else \
2944 fprintf (STREAM, "\t%s\t%sL%d\n", \
2945 ptr_mode == DImode ? ".dword" : ".word", \
2946 LOCAL_LABEL_PREFIX, VALUE); \
2947 } while (0)
2948
2949 /* Mark inline jump tables as data for the purpose of disassembly. For
2950 simplicity embed the jump table's label number in the local symbol
2951 produced so that multiple jump tables within a single function end
2952 up marked with unique symbols. Retain the alignment setting from
2953 `elfos.h' as we are replacing the definition from there. */
2954
2955 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2956 #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \
2957 do \
2958 { \
2959 ASM_OUTPUT_ALIGN ((STREAM), 2); \
2960 if (JUMP_TABLES_IN_TEXT_SECTION) \
2961 mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \
2962 } \
2963 while (0)
2964
2965 /* Reset text marking to code after an inline jump table. Like with
2966 the beginning of a jump table use the label number to keep symbols
2967 unique. */
2968
2969 #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \
2970 do \
2971 if (JUMP_TABLES_IN_TEXT_SECTION) \
2972 mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \
2973 while (0)
2974
2975 /* This is how to output an assembler line
2976 that says to advance the location counter
2977 to a multiple of 2**LOG bytes. */
2978
2979 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2980 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2981
2982 /* This is how to output an assembler line to advance the location
2983 counter by SIZE bytes. */
2984
2985 #undef ASM_OUTPUT_SKIP
2986 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2987 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2988
2989 /* This is how to output a string. */
2990 #undef ASM_OUTPUT_ASCII
2991 #define ASM_OUTPUT_ASCII mips_output_ascii
2992
2993 \f
2994 /* Default to -G 8 */
2995 #ifndef MIPS_DEFAULT_GVALUE
2996 #define MIPS_DEFAULT_GVALUE 8
2997 #endif
2998
2999 /* Define the strings to put out for each section in the object file. */
3000 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
3001 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
3002
3003 #undef READONLY_DATA_SECTION_ASM_OP
3004 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3005 \f
3006 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3007 do \
3008 { \
3009 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
3010 TARGET_64BIT ? "daddiu" : "addiu", \
3011 reg_names[STACK_POINTER_REGNUM], \
3012 reg_names[STACK_POINTER_REGNUM], \
3013 TARGET_64BIT ? "sd" : "sw", \
3014 reg_names[REGNO], \
3015 reg_names[STACK_POINTER_REGNUM]); \
3016 } \
3017 while (0)
3018
3019 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3020 do \
3021 { \
3022 mips_push_asm_switch (&mips_noreorder); \
3023 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3024 TARGET_64BIT ? "ld" : "lw", \
3025 reg_names[REGNO], \
3026 reg_names[STACK_POINTER_REGNUM], \
3027 TARGET_64BIT ? "daddu" : "addu", \
3028 reg_names[STACK_POINTER_REGNUM], \
3029 reg_names[STACK_POINTER_REGNUM]); \
3030 mips_pop_asm_switch (&mips_noreorder); \
3031 } \
3032 while (0)
3033
3034 /* How to start an assembler comment.
3035 The leading space is important (the mips native assembler requires it). */
3036 #ifndef ASM_COMMENT_START
3037 #define ASM_COMMENT_START " #"
3038 #endif
3039 \f
3040 #undef SIZE_TYPE
3041 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3042
3043 #undef PTRDIFF_TYPE
3044 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3045
3046 /* The minimum alignment of any expanded block move. */
3047 #define MIPS_MIN_MOVE_MEM_ALIGN 16
3048
3049 /* The maximum number of bytes that can be copied by one iteration of
3050 a movmemsi loop; see mips_block_move_loop. */
3051 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3052 (UNITS_PER_WORD * 4)
3053
3054 /* The maximum number of bytes that can be copied by a straight-line
3055 implementation of movmemsi; see mips_block_move_straight. We want
3056 to make sure that any loop-based implementation will iterate at
3057 least twice. */
3058 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3059 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3060
3061 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3062 values were determined experimentally by benchmarking with CSiBE.
3063 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3064 for o32 where we have to restore $gp afterwards as well as make an
3065 indirect call), but in practice, bumping this up higher for
3066 TARGET_ABICALLS doesn't make much difference to code size. */
3067
3068 #define MIPS_CALL_RATIO 8
3069
3070 /* Any loop-based implementation of movmemsi will have at least
3071 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3072 moves, so allow individual copies of fewer elements.
3073
3074 When movmemsi is not available, use a value approximating
3075 the length of a memcpy call sequence, so that move_by_pieces
3076 will generate inline code if it is shorter than a function call.
3077 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3078 we'll have to generate a load/store pair for each, halve the
3079 value of MIPS_CALL_RATIO to take that into account. */
3080
3081 #define MOVE_RATIO(speed) \
3082 (HAVE_movmemsi \
3083 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3084 : MIPS_CALL_RATIO / 2)
3085
3086 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3087 of the length of a memset call, but use the default otherwise. */
3088
3089 #define CLEAR_RATIO(speed)\
3090 ((speed) ? 15 : MIPS_CALL_RATIO)
3091
3092 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3093 optimizing for size adjust the ratio to account for the overhead of
3094 loading the constant and replicating it across the word. */
3095
3096 #define SET_RATIO(speed) \
3097 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3098 \f
3099 /* Since the bits of the _init and _fini function is spread across
3100 many object files, each potentially with its own GP, we must assume
3101 we need to load our GP. We don't preserve $gp or $ra, since each
3102 init/fini chunk is supposed to initialize $gp, and crti/crtn
3103 already take care of preserving $ra and, when appropriate, $gp. */
3104 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3105 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3106 asm (SECTION_OP "\n\
3107 .set push\n\
3108 .set nomips16\n\
3109 .set noreorder\n\
3110 bal 1f\n\
3111 nop\n\
3112 1: .cpload $31\n\
3113 .set reorder\n\
3114 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3115 jalr $25\n\
3116 .set pop\n\
3117 " TEXT_SECTION_ASM_OP);
3118 #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32)
3119 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3120 asm (SECTION_OP "\n\
3121 .set push\n\
3122 .set nomips16\n\
3123 .set noreorder\n\
3124 bal 1f\n\
3125 nop\n\
3126 1: .set reorder\n\
3127 .cpsetup $31, $2, 1b\n\
3128 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3129 jalr $25\n\
3130 .set pop\n\
3131 " TEXT_SECTION_ASM_OP);
3132 #elif (defined _ABI64 && _MIPS_SIM == _ABI64)
3133 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3134 asm (SECTION_OP "\n\
3135 .set push\n\
3136 .set nomips16\n\
3137 .set noreorder\n\
3138 bal 1f\n\
3139 nop\n\
3140 1: .set reorder\n\
3141 .cpsetup $31, $2, 1b\n\
3142 dla $25, " USER_LABEL_PREFIX #FUNC "\n\
3143 jalr $25\n\
3144 .set pop\n\
3145 " TEXT_SECTION_ASM_OP);
3146 #endif
3147
3148 #ifndef HAVE_AS_TLS
3149 #define HAVE_AS_TLS 0
3150 #endif
3151
3152 #ifndef HAVE_AS_NAN
3153 #define HAVE_AS_NAN 0
3154 #endif
3155
3156 #ifndef USED_FOR_TARGET
3157 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3158 struct mips_asm_switch {
3159 /* The FOO in the description above. */
3160 const char *name;
3161
3162 /* The current block nesting level, or 0 if we aren't in a block. */
3163 int nesting_level;
3164 };
3165
3166 extern const enum reg_class mips_regno_to_class[];
3167 extern const char *current_function_file; /* filename current function is in */
3168 extern int num_source_filenames; /* current .file # */
3169 extern struct mips_asm_switch mips_noreorder;
3170 extern struct mips_asm_switch mips_nomacro;
3171 extern struct mips_asm_switch mips_noat;
3172 extern int mips_dbx_regno[];
3173 extern int mips_dwarf_regno[];
3174 extern bool mips_split_p[];
3175 extern bool mips_split_hi_p[];
3176 extern bool mips_use_pcrel_pool_p[];
3177 extern const char *mips_lo_relocs[];
3178 extern const char *mips_hi_relocs[];
3179 extern enum processor mips_arch; /* which cpu to codegen for */
3180 extern enum processor mips_tune; /* which cpu to schedule for */
3181 extern int mips_isa; /* architectural level */
3182 extern int mips_isa_rev;
3183 extern const struct mips_cpu_info *mips_arch_info;
3184 extern const struct mips_cpu_info *mips_tune_info;
3185 extern unsigned int mips_base_compression_flags;
3186 extern GTY(()) struct target_globals *mips16_globals;
3187 extern GTY(()) struct target_globals *micromips_globals;
3188
3189 /* Information about a function's frame layout. */
3190 struct GTY(()) mips_frame_info {
3191 /* The size of the frame in bytes. */
3192 HOST_WIDE_INT total_size;
3193
3194 /* The number of bytes allocated to variables. */
3195 HOST_WIDE_INT var_size;
3196
3197 /* The number of bytes allocated to outgoing function arguments. */
3198 HOST_WIDE_INT args_size;
3199
3200 /* The number of bytes allocated to the .cprestore slot, or 0 if there
3201 is no such slot. */
3202 HOST_WIDE_INT cprestore_size;
3203
3204 /* Bit X is set if the function saves or restores GPR X. */
3205 unsigned int mask;
3206
3207 /* Likewise FPR X. */
3208 unsigned int fmask;
3209
3210 /* Likewise doubleword accumulator X ($acX). */
3211 unsigned int acc_mask;
3212
3213 /* The number of GPRs, FPRs, doubleword accumulators and COP0
3214 registers saved. */
3215 unsigned int num_gp;
3216 unsigned int num_fp;
3217 unsigned int num_acc;
3218 unsigned int num_cop0_regs;
3219
3220 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
3221 save slots from the top of the frame, or zero if no such slots are
3222 needed. */
3223 HOST_WIDE_INT gp_save_offset;
3224 HOST_WIDE_INT fp_save_offset;
3225 HOST_WIDE_INT acc_save_offset;
3226 HOST_WIDE_INT cop0_save_offset;
3227
3228 /* Likewise, but giving offsets from the bottom of the frame. */
3229 HOST_WIDE_INT gp_sp_offset;
3230 HOST_WIDE_INT fp_sp_offset;
3231 HOST_WIDE_INT acc_sp_offset;
3232 HOST_WIDE_INT cop0_sp_offset;
3233
3234 /* Similar, but the value passed to _mcount. */
3235 HOST_WIDE_INT ra_fp_offset;
3236
3237 /* The offset of arg_pointer_rtx from the bottom of the frame. */
3238 HOST_WIDE_INT arg_pointer_offset;
3239
3240 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
3241 HOST_WIDE_INT hard_frame_pointer_offset;
3242 };
3243
3244 /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */
3245 enum mips_int_mask
3246 {
3247 INT_MASK_EIC = -1,
3248 INT_MASK_SW0 = 0,
3249 INT_MASK_SW1 = 1,
3250 INT_MASK_HW0 = 2,
3251 INT_MASK_HW1 = 3,
3252 INT_MASK_HW2 = 4,
3253 INT_MASK_HW3 = 5,
3254 INT_MASK_HW4 = 6,
3255 INT_MASK_HW5 = 7
3256 };
3257
3258 /* Enumeration to mark the existence of the shadow register set.
3259 SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack
3260 pointer. */
3261 enum mips_shadow_set
3262 {
3263 SHADOW_SET_NO,
3264 SHADOW_SET_YES,
3265 SHADOW_SET_INTSTACK
3266 };
3267
3268 struct GTY(()) machine_function {
3269 /* The next floating-point condition-code register to allocate
3270 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
3271 unsigned int next_fcc;
3272
3273 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
3274 rtx mips16_gp_pseudo_rtx;
3275
3276 /* The number of extra stack bytes taken up by register varargs.
3277 This area is allocated by the callee at the very top of the frame. */
3278 int varargs_size;
3279
3280 /* The current frame information, calculated by mips_compute_frame_info. */
3281 struct mips_frame_info frame;
3282
3283 /* The register to use as the function's global pointer, or INVALID_REGNUM
3284 if the function doesn't need one. */
3285 unsigned int global_pointer;
3286
3287 /* How many instructions it takes to load a label into $AT, or 0 if
3288 this property hasn't yet been calculated. */
3289 unsigned int load_label_num_insns;
3290
3291 /* True if mips_adjust_insn_length should ignore an instruction's
3292 hazard attribute. */
3293 bool ignore_hazard_length_p;
3294
3295 /* True if the whole function is suitable for .set noreorder and
3296 .set nomacro. */
3297 bool all_noreorder_p;
3298
3299 /* True if the function has "inflexible" and "flexible" references
3300 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
3301 and mips_cfun_has_flexible_gp_ref_p for details. */
3302 bool has_inflexible_gp_insn_p;
3303 bool has_flexible_gp_insn_p;
3304
3305 /* True if the function's prologue must load the global pointer
3306 value into pic_offset_table_rtx and store the same value in
3307 the function's cprestore slot (if any). Even if this value
3308 is currently false, we may decide to set it to true later;
3309 see mips_must_initialize_gp_p () for details. */
3310 bool must_initialize_gp_p;
3311
3312 /* True if the current function must restore $gp after any potential
3313 clobber. This value is only meaningful during the first post-epilogue
3314 split_insns pass; see mips_must_initialize_gp_p () for details. */
3315 bool must_restore_gp_when_clobbered_p;
3316
3317 /* True if this is an interrupt handler. */
3318 bool interrupt_handler_p;
3319
3320 /* Records the way in which interrupts should be masked. Only used if
3321 interrupts are not kept masked. */
3322 enum mips_int_mask int_mask;
3323
3324 /* Records if this is an interrupt handler that uses shadow registers. */
3325 enum mips_shadow_set use_shadow_register_set;
3326
3327 /* True if this is an interrupt handler that should keep interrupts
3328 masked. */
3329 bool keep_interrupts_masked_p;
3330
3331 /* True if this is an interrupt handler that should use DERET
3332 instead of ERET. */
3333 bool use_debug_exception_return_p;
3334
3335 /* True if at least one of the formal parameters to a function must be
3336 written to the frame header (probably so its address can be taken). */
3337 bool does_not_use_frame_header;
3338
3339 /* True if none of the functions that are called by this function need
3340 stack space allocated for their arguments. */
3341 bool optimize_call_stack;
3342
3343 /* True if one of the functions calling this function may not allocate
3344 a frame header. */
3345 bool callers_may_not_allocate_frame;
3346
3347 /* True if GCC stored callee saved registers in the frame header. */
3348 bool use_frame_header_for_callee_saved_regs;
3349 };
3350 #endif
3351
3352 /* Enable querying of DFA units. */
3353 #define CPU_UNITS_QUERY 1
3354
3355 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3356 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3357
3358 /* As on most targets, we want the .eh_frame section to be read-only where
3359 possible. And as on most targets, this means two things:
3360
3361 (a) Non-locally-binding pointers must have an indirect encoding,
3362 so that the addresses in the .eh_frame section itself become
3363 locally-binding.
3364
3365 (b) A shared library's .eh_frame section must encode locally-binding
3366 pointers in a relative (relocation-free) form.
3367
3368 However, MIPS has traditionally not allowed directives like:
3369
3370 .long x-.
3371
3372 in cases where "x" is in a different section, or is not defined in the
3373 same assembly file. We are therefore unable to emit the PC-relative
3374 form required by (b) at assembly time.
3375
3376 Fortunately, the linker is able to convert absolute addresses into
3377 PC-relative addresses on our behalf. Unfortunately, only certain
3378 versions of the linker know how to do this for indirect pointers,
3379 and for personality data. We must fall back on using writable
3380 .eh_frame sections for shared libraries if the linker does not
3381 support this feature. */
3382 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3383 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3384
3385 /* For switching between MIPS16 and non-MIPS16 modes. */
3386 #define SWITCHABLE_TARGET 1
3387
3388 /* Several named MIPS patterns depend on Pmode. These patterns have the
3389 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3390 Add the appropriate suffix to generator function NAME and invoke it
3391 with arguments ARGS. */
3392 #define PMODE_INSN(NAME, ARGS) \
3393 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3394
3395 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3396 need to change these from /lib and /usr/lib. */
3397 #if MIPS_ABI_DEFAULT == ABI_N32
3398 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3399 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3400 #elif MIPS_ABI_DEFAULT == ABI_64
3401 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3402 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3403 #endif
3404
3405 /* Load store bonding is not supported by micromips and fix_24k. The
3406 performance can be degraded for those targets. Hence, do not bond for
3407 micromips or fix_24k. */
3408 #define ENABLE_LD_ST_PAIRS \
3409 (TARGET_LOAD_STORE_PAIRS \
3410 && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \
3411 && !TARGET_MICROMIPS && !TARGET_FIX_24K)
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