| blob | 3528f1a05f070eeb44cd2cb618dfb83f5b564a38 |
1 ;; Machine description for RISC-V 'V' Extension for GNU compiler.
2 ;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
3 ;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; This file describes the RISC-V 'V' Extension, Version 1.0.
22 ;;
23 ;; This file include :
24 ;;
25 ;; - Intrinsics (https://github.com/riscv/rvv-intrinsic-doc)
26 ;; - Auto-vectorization (autovec.md)
27 ;; - Optimization (autovec-opt.md)
29 (include "vector-iterators.md")
31 (define_constants [
32 (INVALID_ATTRIBUTE 255)
33 (X0_REGNUM 0)
34 ])
36 ;; True if the type is RVV instructions that include VTYPE
37 ;; global status register in the use op list.
38 ;; We known VTYPE has 4 fields: SEW, LMUL, TA, MA.
39 ;; The instruction need any of VTYPE field is set as true
40 ;; in this attribute.
41 (define_attr "has_vtype_op" "false,true"
42 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
43 vldux,vldox,vstux,vstox,vldff,\
44 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
45 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
46 vsalu,vaalu,vsmul,vsshift,vnclip,\
47 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
48 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
49 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
50 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
51 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
52 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovvx,vimovxv,vfmovvf,vfmovfv,\
53 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
54 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
55 vssegtux,vssegtox,vlsegdff")
56 (const_string "true")]
57 (const_string "false")))
59 ;; True if the type is RVV instructions that include VL
60 ;; global status register in the use op list.
61 ;; The instruction need vector length to be specified is set
62 ;; in this attribute.
63 (define_attr "has_vl_op" "false,true"
64 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,\
65 vldux,vldox,vstux,vstox,vldff,\
66 vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,\
67 vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,\
68 vsalu,vaalu,vsmul,vsshift,vnclip,\
69 vfalu,vfwalu,vfmul,vfdiv,vfwmul,vfmuladd,vfwmuladd,vfsqrt,vfrecp,\
70 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
71 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,\
72 vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
73 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
74 vmalu,vmpop,vmffs,vmsfs,vmiota,vmidx,vimovxv,vfmovfv,\
75 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
76 vgather,vcompress,vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,\
77 vssegtux,vssegtox,vlsegdff")
78 (const_string "true")]
79 (const_string "false")))
81 ;; The default SEW of RVV instruction. This attribute doesn't mean the instruction
82 ;; is necessary to require SEW check for example vlm.v which require ratio to
83 ;; check. However, we need default value of SEW for vsetvl instruction since there
84 ;; is no field for ratio in the vsetvl instruction encoding.
85 (define_attr "sew" ""
86 (cond [(eq_attr "mode" "RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,\
87 RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,\
88 RVVM1x8QI,RVVMF2x8QI,RVVMF4x8QI,RVVMF8x8QI,\
89 RVVM1x7QI,RVVMF2x7QI,RVVMF4x7QI,RVVMF8x7QI,\
90 RVVM1x6QI,RVVMF2x6QI,RVVMF4x6QI,RVVMF8x6QI,\
91 RVVM1x5QI,RVVMF2x5QI,RVVMF4x5QI,RVVMF8x5QI,\
92 RVVM2x4QI,RVVM1x4QI,RVVMF2x4QI,RVVMF4x4QI,RVVMF8x4QI,\
93 RVVM2x3QI,RVVM1x3QI,RVVMF2x3QI,RVVMF4x3QI,RVVMF8x3QI,\
94 RVVM4x2QI,RVVM2x2QI,RVVM1x2QI,RVVMF2x2QI,RVVMF4x2QI,RVVMF8x2QI,\
95 V1QI,V2QI,V4QI,V8QI,V16QI,V32QI,V64QI,V128QI,V256QI,V512QI,V1024QI,V2048QI,V4096QI,\
96 V1BI,V2BI,V4BI,V8BI,V16BI,V32BI,V64BI,V128BI,V256BI,V512BI,V1024BI,V2048BI,V4096BI")
97 (const_int 8)
98 (eq_attr "mode" "RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,\
99 RVVM1x8HI,RVVMF2x8HI,RVVMF4x8HI,\
100 RVVM1x7HI,RVVMF2x7HI,RVVMF4x7HI,\
101 RVVM1x6HI,RVVMF2x6HI,RVVMF4x6HI,\
102 RVVM1x5HI,RVVMF2x5HI,RVVMF4x5HI,\
103 RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,\
104 RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,\
105 RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,\
106 RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,\
107 RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,\
108 RVVM1x7HF,RVVMF2x7HF,RVVMF4x7HF,\
109 RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,\
110 RVVM1x5HF,RVVMF2x5HF,RVVMF4x5HF,\
111 RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF,RVVMF4x4HF,\
112 RVVM2x3HF,RVVM1x3HF,RVVMF2x3HF,RVVMF4x3HF,\
113 RVVM4x2HF,RVVM2x2HF,RVVM1x2HF,RVVMF2x2HF,RVVMF4x2HF,\
114 V1HI,V2HI,V4HI,V8HI,V16HI,V32HI,V64HI,V128HI,V256HI,V512HI,V1024HI,V2048HI,\
115 V1HF,V2HF,V4HF,V8HF,V16HF,V32HF,V64HF,V128HF,V256HF,V512HF,V1024HF,V2048HF")
116 (const_int 16)
117 (eq_attr "mode" "RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI,\
118 RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF,\
119 RVVM1x8SI,RVVMF2x8SI,\
120 RVVM1x7SI,RVVMF2x7SI,\
121 RVVM1x6SI,RVVMF2x6SI,\
122 RVVM1x5SI,RVVMF2x5SI,\
123 RVVMF2x4SI,RVVMF2x3SI,\
124 RVVM2x4SI,RVVM1x4SI,\
125 RVVM2x3SI,RVVM1x3SI,\
126 RVVM4x2SI,RVVM2x2SI,RVVM1x2SI,RVVMF2x2SI,\
127 RVVM1x8SF,RVVMF2x8SF,\
128 RVVM1x7SF,RVVMF2x7SF,\
129 RVVM1x6SF,RVVMF2x6SF,\
130 RVVM1x5SF,RVVMF2x5SF,\
131 RVVM2x4SF,RVVM1x4SF,RVVMF2x4SF,\
132 RVVM2x3SF,RVVM1x3SF,RVVMF2x3SF,\
133 RVVM4x2SF,RVVM2x2SF,RVVM1x2SF,RVVMF2x2SF,\
134 V1SI,V2SI,V4SI,V8SI,V16SI,V32SI,V64SI,V128SI,V256SI,V512SI,V1024SI,\
135 V1SF,V2SF,V4SF,V8SF,V16SF,V32SF,V64SF,V128SF,V256SF,V512SF,V1024SF")
136 (const_int 32)
137 (eq_attr "mode" "RVVM8DI,RVVM4DI,RVVM2DI,RVVM1DI,\
138 RVVM8DF,RVVM4DF,RVVM2DF,RVVM1DF,\
139 RVVM1x8DI,RVVM1x7DI,RVVM1x6DI,RVVM1x5DI,\
140 RVVM2x4DI,RVVM1x4DI,\
141 RVVM2x3DI,RVVM1x3DI,\
142 RVVM4x2DI,RVVM2x2DI,RVVM1x2DI,\
143 RVVM1x8DF,RVVM1x7DF,RVVM1x6DF,RVVM1x5DF,\
144 RVVM2x4DF,RVVM1x4DF,\
145 RVVM2x3DF,RVVM1x3DF,\
146 RVVM4x2DF,RVVM2x2DF,RVVM1x2DF,\
147 V1DI,V2DI,V4DI,V8DI,V16DI,V32DI,V64DI,V128DI,V256DI,V512DI,\
148 V1DF,V2DF,V4DF,V8DF,V16DF,V32DF,V64DF,V128DF,V256DF,V512DF")
149 (const_int 64)]
150 (const_int INVALID_ATTRIBUTE)))
152 ;; Ditto to LMUL.
153 (define_attr "vlmul" ""
154 (cond [(eq_attr "mode" "RVVM8QI,RVVM1BI") (symbol_ref "riscv_vector::LMUL_8")
155 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (symbol_ref "riscv_vector::LMUL_4")
156 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (symbol_ref "riscv_vector::LMUL_2")
157 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (symbol_ref "riscv_vector::LMUL_1")
158 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (symbol_ref "riscv_vector::LMUL_F2")
159 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (symbol_ref "riscv_vector::LMUL_F4")
160 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (symbol_ref "riscv_vector::LMUL_F8")
161 (eq_attr "mode" "RVVM8HI") (symbol_ref "riscv_vector::LMUL_8")
162 (eq_attr "mode" "RVVM4HI") (symbol_ref "riscv_vector::LMUL_4")
163 (eq_attr "mode" "RVVM2HI") (symbol_ref "riscv_vector::LMUL_2")
164 (eq_attr "mode" "RVVM1HI") (symbol_ref "riscv_vector::LMUL_1")
165 (eq_attr "mode" "RVVMF2HI") (symbol_ref "riscv_vector::LMUL_F2")
166 (eq_attr "mode" "RVVMF4HI") (symbol_ref "riscv_vector::LMUL_F4")
167 (eq_attr "mode" "RVVM8HF") (symbol_ref "riscv_vector::LMUL_8")
168 (eq_attr "mode" "RVVM4HF") (symbol_ref "riscv_vector::LMUL_4")
169 (eq_attr "mode" "RVVM2HF") (symbol_ref "riscv_vector::LMUL_2")
170 (eq_attr "mode" "RVVM1HF") (symbol_ref "riscv_vector::LMUL_1")
171 (eq_attr "mode" "RVVMF2HF") (symbol_ref "riscv_vector::LMUL_F2")
172 (eq_attr "mode" "RVVMF4HF") (symbol_ref "riscv_vector::LMUL_F4")
173 (eq_attr "mode" "RVVM8SI") (symbol_ref "riscv_vector::LMUL_8")
174 (eq_attr "mode" "RVVM4SI") (symbol_ref "riscv_vector::LMUL_4")
175 (eq_attr "mode" "RVVM2SI") (symbol_ref "riscv_vector::LMUL_2")
176 (eq_attr "mode" "RVVM1SI") (symbol_ref "riscv_vector::LMUL_1")
177 (eq_attr "mode" "RVVMF2SI") (symbol_ref "riscv_vector::LMUL_F2")
178 (eq_attr "mode" "RVVM8SF") (symbol_ref "riscv_vector::LMUL_8")
179 (eq_attr "mode" "RVVM4SF") (symbol_ref "riscv_vector::LMUL_4")
180 (eq_attr "mode" "RVVM2SF") (symbol_ref "riscv_vector::LMUL_2")
181 (eq_attr "mode" "RVVM1SF") (symbol_ref "riscv_vector::LMUL_1")
182 (eq_attr "mode" "RVVMF2SF") (symbol_ref "riscv_vector::LMUL_F2")
183 (eq_attr "mode" "RVVM8DI") (symbol_ref "riscv_vector::LMUL_8")
184 (eq_attr "mode" "RVVM4DI") (symbol_ref "riscv_vector::LMUL_4")
185 (eq_attr "mode" "RVVM2DI") (symbol_ref "riscv_vector::LMUL_2")
186 (eq_attr "mode" "RVVM1DI") (symbol_ref "riscv_vector::LMUL_1")
187 (eq_attr "mode" "RVVM8DF") (symbol_ref "riscv_vector::LMUL_8")
188 (eq_attr "mode" "RVVM4DF") (symbol_ref "riscv_vector::LMUL_4")
189 (eq_attr "mode" "RVVM2DF") (symbol_ref "riscv_vector::LMUL_2")
190 (eq_attr "mode" "RVVM1DF") (symbol_ref "riscv_vector::LMUL_1")
191 (eq_attr "mode" "RVVM1x8QI") (symbol_ref "riscv_vector::LMUL_1")
192 (eq_attr "mode" "RVVMF2x8QI") (symbol_ref "riscv_vector::LMUL_F2")
193 (eq_attr "mode" "RVVMF4x8QI") (symbol_ref "riscv_vector::LMUL_F4")
194 (eq_attr "mode" "RVVMF8x8QI") (symbol_ref "riscv_vector::LMUL_F8")
195 (eq_attr "mode" "RVVM1x7QI") (symbol_ref "riscv_vector::LMUL_1")
196 (eq_attr "mode" "RVVMF2x7QI") (symbol_ref "riscv_vector::LMUL_F2")
197 (eq_attr "mode" "RVVMF4x7QI") (symbol_ref "riscv_vector::LMUL_F4")
198 (eq_attr "mode" "RVVMF8x7QI") (symbol_ref "riscv_vector::LMUL_F8")
199 (eq_attr "mode" "RVVM1x6QI") (symbol_ref "riscv_vector::LMUL_1")
200 (eq_attr "mode" "RVVMF2x6QI") (symbol_ref "riscv_vector::LMUL_F2")
201 (eq_attr "mode" "RVVMF4x6QI") (symbol_ref "riscv_vector::LMUL_F4")
202 (eq_attr "mode" "RVVMF8x6QI") (symbol_ref "riscv_vector::LMUL_F8")
203 (eq_attr "mode" "RVVM1x5QI") (symbol_ref "riscv_vector::LMUL_1")
204 (eq_attr "mode" "RVVMF2x5QI") (symbol_ref "riscv_vector::LMUL_F2")
205 (eq_attr "mode" "RVVMF4x5QI") (symbol_ref "riscv_vector::LMUL_F4")
206 (eq_attr "mode" "RVVMF8x5QI") (symbol_ref "riscv_vector::LMUL_F8")
207 (eq_attr "mode" "RVVM2x4QI") (symbol_ref "riscv_vector::LMUL_2")
208 (eq_attr "mode" "RVVM1x4QI") (symbol_ref "riscv_vector::LMUL_1")
209 (eq_attr "mode" "RVVMF2x4QI") (symbol_ref "riscv_vector::LMUL_F2")
210 (eq_attr "mode" "RVVMF4x4QI") (symbol_ref "riscv_vector::LMUL_F4")
211 (eq_attr "mode" "RVVMF8x4QI") (symbol_ref "riscv_vector::LMUL_F8")
212 (eq_attr "mode" "RVVM2x3QI") (symbol_ref "riscv_vector::LMUL_2")
213 (eq_attr "mode" "RVVM1x3QI") (symbol_ref "riscv_vector::LMUL_1")
214 (eq_attr "mode" "RVVMF2x3QI") (symbol_ref "riscv_vector::LMUL_F2")
215 (eq_attr "mode" "RVVMF4x3QI") (symbol_ref "riscv_vector::LMUL_F4")
216 (eq_attr "mode" "RVVMF8x3QI") (symbol_ref "riscv_vector::LMUL_F8")
217 (eq_attr "mode" "RVVM4x2QI") (symbol_ref "riscv_vector::LMUL_4")
218 (eq_attr "mode" "RVVM2x2QI") (symbol_ref "riscv_vector::LMUL_2")
219 (eq_attr "mode" "RVVM1x2QI") (symbol_ref "riscv_vector::LMUL_1")
220 (eq_attr "mode" "RVVMF2x2QI") (symbol_ref "riscv_vector::LMUL_F2")
221 (eq_attr "mode" "RVVMF4x2QI") (symbol_ref "riscv_vector::LMUL_F4")
222 (eq_attr "mode" "RVVMF8x2QI") (symbol_ref "riscv_vector::LMUL_F8")
223 (eq_attr "mode" "RVVM1x8HI") (symbol_ref "riscv_vector::LMUL_1")
224 (eq_attr "mode" "RVVMF2x8HI") (symbol_ref "riscv_vector::LMUL_F2")
225 (eq_attr "mode" "RVVMF4x8HI") (symbol_ref "riscv_vector::LMUL_F4")
226 (eq_attr "mode" "RVVM1x7HI") (symbol_ref "riscv_vector::LMUL_1")
227 (eq_attr "mode" "RVVMF2x7HI") (symbol_ref "riscv_vector::LMUL_F2")
228 (eq_attr "mode" "RVVMF4x7HI") (symbol_ref "riscv_vector::LMUL_F4")
229 (eq_attr "mode" "RVVM1x6HI") (symbol_ref "riscv_vector::LMUL_1")
230 (eq_attr "mode" "RVVMF2x6HI") (symbol_ref "riscv_vector::LMUL_F2")
231 (eq_attr "mode" "RVVMF4x6HI") (symbol_ref "riscv_vector::LMUL_F4")
232 (eq_attr "mode" "RVVM1x5HI") (symbol_ref "riscv_vector::LMUL_1")
233 (eq_attr "mode" "RVVMF2x5HI") (symbol_ref "riscv_vector::LMUL_F2")
234 (eq_attr "mode" "RVVMF4x5HI") (symbol_ref "riscv_vector::LMUL_F4")
235 (eq_attr "mode" "RVVM2x4HI") (symbol_ref "riscv_vector::LMUL_2")
236 (eq_attr "mode" "RVVM1x4HI") (symbol_ref "riscv_vector::LMUL_1")
237 (eq_attr "mode" "RVVMF2x4HI") (symbol_ref "riscv_vector::LMUL_F2")
238 (eq_attr "mode" "RVVMF4x4HI") (symbol_ref "riscv_vector::LMUL_F4")
239 (eq_attr "mode" "RVVM2x3HI") (symbol_ref "riscv_vector::LMUL_2")
240 (eq_attr "mode" "RVVM1x3HI") (symbol_ref "riscv_vector::LMUL_1")
241 (eq_attr "mode" "RVVMF2x3HI") (symbol_ref "riscv_vector::LMUL_F2")
242 (eq_attr "mode" "RVVMF4x3HI") (symbol_ref "riscv_vector::LMUL_F4")
243 (eq_attr "mode" "RVVM4x2HI") (symbol_ref "riscv_vector::LMUL_4")
244 (eq_attr "mode" "RVVM2x2HI") (symbol_ref "riscv_vector::LMUL_2")
245 (eq_attr "mode" "RVVM1x2HI") (symbol_ref "riscv_vector::LMUL_1")
246 (eq_attr "mode" "RVVMF2x2HI") (symbol_ref "riscv_vector::LMUL_F2")
247 (eq_attr "mode" "RVVMF4x2HI") (symbol_ref "riscv_vector::LMUL_F4")
248 (eq_attr "mode" "RVVM1x8HF") (symbol_ref "riscv_vector::LMUL_1")
249 (eq_attr "mode" "RVVMF2x8HF") (symbol_ref "riscv_vector::LMUL_F2")
250 (eq_attr "mode" "RVVMF4x8HF") (symbol_ref "riscv_vector::LMUL_F4")
251 (eq_attr "mode" "RVVM1x7HF") (symbol_ref "riscv_vector::LMUL_1")
252 (eq_attr "mode" "RVVMF2x7HF") (symbol_ref "riscv_vector::LMUL_F2")
253 (eq_attr "mode" "RVVMF4x7HF") (symbol_ref "riscv_vector::LMUL_F4")
254 (eq_attr "mode" "RVVM1x6HF") (symbol_ref "riscv_vector::LMUL_1")
255 (eq_attr "mode" "RVVMF2x6HF") (symbol_ref "riscv_vector::LMUL_F2")
256 (eq_attr "mode" "RVVMF4x6HF") (symbol_ref "riscv_vector::LMUL_F4")
257 (eq_attr "mode" "RVVM1x5HF") (symbol_ref "riscv_vector::LMUL_1")
258 (eq_attr "mode" "RVVMF2x5HF") (symbol_ref "riscv_vector::LMUL_F2")
259 (eq_attr "mode" "RVVMF4x5HF") (symbol_ref "riscv_vector::LMUL_F4")
260 (eq_attr "mode" "RVVM2x4HF") (symbol_ref "riscv_vector::LMUL_2")
261 (eq_attr "mode" "RVVM1x4HF") (symbol_ref "riscv_vector::LMUL_1")
262 (eq_attr "mode" "RVVMF2x4HF") (symbol_ref "riscv_vector::LMUL_F2")
263 (eq_attr "mode" "RVVMF4x4HF") (symbol_ref "riscv_vector::LMUL_F4")
264 (eq_attr "mode" "RVVM2x3HF") (symbol_ref "riscv_vector::LMUL_2")
265 (eq_attr "mode" "RVVM1x3HF") (symbol_ref "riscv_vector::LMUL_1")
266 (eq_attr "mode" "RVVMF2x3HF") (symbol_ref "riscv_vector::LMUL_F2")
267 (eq_attr "mode" "RVVMF4x3HF") (symbol_ref "riscv_vector::LMUL_F4")
268 (eq_attr "mode" "RVVM4x2HF") (symbol_ref "riscv_vector::LMUL_4")
269 (eq_attr "mode" "RVVM2x2HF") (symbol_ref "riscv_vector::LMUL_2")
270 (eq_attr "mode" "RVVM1x2HF") (symbol_ref "riscv_vector::LMUL_1")
271 (eq_attr "mode" "RVVMF2x2HF") (symbol_ref "riscv_vector::LMUL_F2")
272 (eq_attr "mode" "RVVMF4x2HF") (symbol_ref "riscv_vector::LMUL_F4")
273 (eq_attr "mode" "RVVM1x8SI") (symbol_ref "riscv_vector::LMUL_1")
274 (eq_attr "mode" "RVVMF2x8SI") (symbol_ref "riscv_vector::LMUL_F2")
275 (eq_attr "mode" "RVVM1x7SI") (symbol_ref "riscv_vector::LMUL_1")
276 (eq_attr "mode" "RVVMF2x7SI") (symbol_ref "riscv_vector::LMUL_F2")
277 (eq_attr "mode" "RVVM1x6SI") (symbol_ref "riscv_vector::LMUL_1")
278 (eq_attr "mode" "RVVMF2x6SI") (symbol_ref "riscv_vector::LMUL_F2")
279 (eq_attr "mode" "RVVM1x5SI") (symbol_ref "riscv_vector::LMUL_1")
280 (eq_attr "mode" "RVVMF2x5SI") (symbol_ref "riscv_vector::LMUL_F2")
281 (eq_attr "mode" "RVVM2x4SI") (symbol_ref "riscv_vector::LMUL_2")
282 (eq_attr "mode" "RVVM1x4SI") (symbol_ref "riscv_vector::LMUL_1")
283 (eq_attr "mode" "RVVMF2x4SI") (symbol_ref "riscv_vector::LMUL_F2")
284 (eq_attr "mode" "RVVM2x3SI") (symbol_ref "riscv_vector::LMUL_2")
285 (eq_attr "mode" "RVVM1x3SI") (symbol_ref "riscv_vector::LMUL_1")
286 (eq_attr "mode" "RVVMF2x3SI") (symbol_ref "riscv_vector::LMUL_F2")
287 (eq_attr "mode" "RVVM4x2SI") (symbol_ref "riscv_vector::LMUL_4")
288 (eq_attr "mode" "RVVM2x2SI") (symbol_ref "riscv_vector::LMUL_2")
289 (eq_attr "mode" "RVVM1x2SI") (symbol_ref "riscv_vector::LMUL_1")
290 (eq_attr "mode" "RVVMF2x2SI") (symbol_ref "riscv_vector::LMUL_F2")
291 (eq_attr "mode" "RVVM1x8SF") (symbol_ref "riscv_vector::LMUL_1")
292 (eq_attr "mode" "RVVMF2x8SF") (symbol_ref "riscv_vector::LMUL_F2")
293 (eq_attr "mode" "RVVM1x7SF") (symbol_ref "riscv_vector::LMUL_1")
294 (eq_attr "mode" "RVVMF2x7SF") (symbol_ref "riscv_vector::LMUL_F2")
295 (eq_attr "mode" "RVVM1x6SF") (symbol_ref "riscv_vector::LMUL_1")
296 (eq_attr "mode" "RVVMF2x6SF") (symbol_ref "riscv_vector::LMUL_F2")
297 (eq_attr "mode" "RVVM1x5SF") (symbol_ref "riscv_vector::LMUL_1")
298 (eq_attr "mode" "RVVMF2x5SF") (symbol_ref "riscv_vector::LMUL_F2")
299 (eq_attr "mode" "RVVM2x4SF") (symbol_ref "riscv_vector::LMUL_2")
300 (eq_attr "mode" "RVVM1x4SF") (symbol_ref "riscv_vector::LMUL_1")
301 (eq_attr "mode" "RVVMF2x4SF") (symbol_ref "riscv_vector::LMUL_F2")
302 (eq_attr "mode" "RVVM2x3SF") (symbol_ref "riscv_vector::LMUL_2")
303 (eq_attr "mode" "RVVM1x3SF") (symbol_ref "riscv_vector::LMUL_1")
304 (eq_attr "mode" "RVVMF2x3SF") (symbol_ref "riscv_vector::LMUL_F2")
305 (eq_attr "mode" "RVVM4x2SF") (symbol_ref "riscv_vector::LMUL_4")
306 (eq_attr "mode" "RVVM2x2SF") (symbol_ref "riscv_vector::LMUL_2")
307 (eq_attr "mode" "RVVM1x2SF") (symbol_ref "riscv_vector::LMUL_1")
308 (eq_attr "mode" "RVVMF2x2SF") (symbol_ref "riscv_vector::LMUL_F2")
309 (eq_attr "mode" "RVVM1x8DI") (symbol_ref "riscv_vector::LMUL_1")
310 (eq_attr "mode" "RVVM1x7DI") (symbol_ref "riscv_vector::LMUL_1")
311 (eq_attr "mode" "RVVM1x6DI") (symbol_ref "riscv_vector::LMUL_1")
312 (eq_attr "mode" "RVVM1x5DI") (symbol_ref "riscv_vector::LMUL_1")
313 (eq_attr "mode" "RVVM2x4DI") (symbol_ref "riscv_vector::LMUL_2")
314 (eq_attr "mode" "RVVM1x4DI") (symbol_ref "riscv_vector::LMUL_1")
315 (eq_attr "mode" "RVVM2x3DI") (symbol_ref "riscv_vector::LMUL_2")
316 (eq_attr "mode" "RVVM1x3DI") (symbol_ref "riscv_vector::LMUL_1")
317 (eq_attr "mode" "RVVM4x2DI") (symbol_ref "riscv_vector::LMUL_4")
318 (eq_attr "mode" "RVVM2x2DI") (symbol_ref "riscv_vector::LMUL_2")
319 (eq_attr "mode" "RVVM1x2DI") (symbol_ref "riscv_vector::LMUL_1")
320 (eq_attr "mode" "RVVM1x8DF") (symbol_ref "riscv_vector::LMUL_1")
321 (eq_attr "mode" "RVVM1x7DF") (symbol_ref "riscv_vector::LMUL_1")
322 (eq_attr "mode" "RVVM1x6DF") (symbol_ref "riscv_vector::LMUL_1")
323 (eq_attr "mode" "RVVM1x5DF") (symbol_ref "riscv_vector::LMUL_1")
324 (eq_attr "mode" "RVVM2x4DF") (symbol_ref "riscv_vector::LMUL_2")
325 (eq_attr "mode" "RVVM1x4DF") (symbol_ref "riscv_vector::LMUL_1")
326 (eq_attr "mode" "RVVM2x3DF") (symbol_ref "riscv_vector::LMUL_2")
327 (eq_attr "mode" "RVVM1x3DF") (symbol_ref "riscv_vector::LMUL_1")
328 (eq_attr "mode" "RVVM4x2DF") (symbol_ref "riscv_vector::LMUL_4")
329 (eq_attr "mode" "RVVM2x2DF") (symbol_ref "riscv_vector::LMUL_2")
330 (eq_attr "mode" "RVVM1x2DF") (symbol_ref "riscv_vector::LMUL_1")
332 ;; VLS modes.
333 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_vlmul(E_V1QImode)")
334 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_vlmul(E_V2QImode)")
335 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_vlmul(E_V4QImode)")
336 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_vlmul(E_V8QImode)")
337 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_vlmul(E_V16QImode)")
338 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_vlmul(E_V32QImode)")
339 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_vlmul(E_V64QImode)")
340 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_vlmul(E_V128QImode)")
341 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_vlmul(E_V256QImode)")
342 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_vlmul(E_V512QImode)")
343 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_vlmul(E_V1024QImode)")
344 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_vlmul(E_V2048QImode)")
345 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_vlmul(E_V4096QImode)")
346 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_vlmul(E_V1HImode)")
347 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_vlmul(E_V2HImode)")
348 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_vlmul(E_V4HImode)")
349 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_vlmul(E_V8HImode)")
350 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_vlmul(E_V16HImode)")
351 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_vlmul(E_V32HImode)")
352 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_vlmul(E_V64HImode)")
353 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_vlmul(E_V128HImode)")
354 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_vlmul(E_V256HImode)")
355 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_vlmul(E_V512HImode)")
356 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_vlmul(E_V1024HImode)")
357 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_vlmul(E_V2048HImode)")
358 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_vlmul(E_V1SImode)")
359 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_vlmul(E_V2SImode)")
360 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_vlmul(E_V4SImode)")
361 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_vlmul(E_V8SImode)")
362 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_vlmul(E_V16SImode)")
363 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_vlmul(E_V32SImode)")
364 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_vlmul(E_V64SImode)")
365 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_vlmul(E_V128SImode)")
366 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_vlmul(E_V256SImode)")
367 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_vlmul(E_V512SImode)")
368 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_vlmul(E_V1024SImode)")
369 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_vlmul(E_V1DImode)")
370 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_vlmul(E_V2DImode)")
371 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_vlmul(E_V4DImode)")
372 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_vlmul(E_V8DImode)")
373 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_vlmul(E_V16DImode)")
374 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_vlmul(E_V32DImode)")
375 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_vlmul(E_V64DImode)")
376 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_vlmul(E_V128DImode)")
377 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_vlmul(E_V256DImode)")
378 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_vlmul(E_V512DImode)")
379 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_vlmul(E_V1HFmode)")
380 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_vlmul(E_V2HFmode)")
381 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_vlmul(E_V4HFmode)")
382 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_vlmul(E_V8HFmode)")
383 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_vlmul(E_V16HFmode)")
384 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_vlmul(E_V32HFmode)")
385 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_vlmul(E_V64HFmode)")
386 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_vlmul(E_V128HFmode)")
387 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_vlmul(E_V256HFmode)")
388 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_vlmul(E_V512HFmode)")
389 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_vlmul(E_V1024HFmode)")
390 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_vlmul(E_V2048HFmode)")
391 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_vlmul(E_V1SFmode)")
392 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_vlmul(E_V2SFmode)")
393 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_vlmul(E_V4SFmode)")
394 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_vlmul(E_V8SFmode)")
395 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_vlmul(E_V16SFmode)")
396 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_vlmul(E_V32SFmode)")
397 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_vlmul(E_V64SFmode)")
398 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_vlmul(E_V128SFmode)")
399 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_vlmul(E_V256SFmode)")
400 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_vlmul(E_V512SFmode)")
401 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_vlmul(E_V1024SFmode)")
402 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_vlmul(E_V1DFmode)")
403 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_vlmul(E_V2DFmode)")
404 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_vlmul(E_V4DFmode)")
405 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_vlmul(E_V8DFmode)")
406 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_vlmul(E_V16DFmode)")
407 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_vlmul(E_V32DFmode)")
408 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_vlmul(E_V64DFmode)")
409 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_vlmul(E_V128DFmode)")
410 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_vlmul(E_V256DFmode)")
411 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_vlmul(E_V512DFmode)")]
412 (const_int INVALID_ATTRIBUTE)))
414 ;; It is valid for instruction that require sew/lmul ratio.
415 (define_attr "ratio" ""
416 (cond [(eq_attr "type" "vimov,vfmov,vldux,vldox,vstux,vstox,\
417 vialu,vshift,vicmp,vimul,vidiv,vsalu,\
418 vext,viwalu,viwmul,vicalu,vnshift,\
419 vimuladd,vimerge,vaalu,vsmul,vsshift,\
420 vnclip,viminmax,viwmuladd,vmffs,vmsfs,\
421 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,\
422 vfwalu,vfwmul,vfsqrt,vfrecp,vfsgnj,vfcmp,\
423 vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
424 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
425 vfncvtftof,vfmuladd,vfwmuladd,vfclass,vired,\
426 viwred,vfredu,vfredo,vfwredu,vfwredo,vimovvx,\
427 vimovxv,vfmovvf,vfmovfv,vslideup,vslidedown,\
428 vislide1up,vislide1down,vfslide1up,vfslide1down,\
429 vgather,vcompress,vlsegdux,vlsegdox,vssegtux,vssegtox")
430 (const_int INVALID_ATTRIBUTE)
431 (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
432 (eq_attr "mode" "RVVM4QI,RVVMF2BI") (const_int 2)
433 (eq_attr "mode" "RVVM2QI,RVVMF4BI") (const_int 4)
434 (eq_attr "mode" "RVVM1QI,RVVMF8BI") (const_int 8)
435 (eq_attr "mode" "RVVMF2QI,RVVMF16BI") (const_int 16)
436 (eq_attr "mode" "RVVMF4QI,RVVMF32BI") (const_int 32)
437 (eq_attr "mode" "RVVMF8QI,RVVMF64BI") (const_int 64)
438 (eq_attr "mode" "RVVM8HI") (const_int 2)
439 (eq_attr "mode" "RVVM4HI") (const_int 4)
440 (eq_attr "mode" "RVVM2HI") (const_int 8)
441 (eq_attr "mode" "RVVM1HI") (const_int 16)
442 (eq_attr "mode" "RVVMF2HI") (const_int 32)
443 (eq_attr "mode" "RVVMF4HI") (const_int 64)
444 (eq_attr "mode" "RVVM8HF") (const_int 2)
445 (eq_attr "mode" "RVVM4HF") (const_int 4)
446 (eq_attr "mode" "RVVM2HF") (const_int 8)
447 (eq_attr "mode" "RVVM1HF") (const_int 16)
448 (eq_attr "mode" "RVVMF2HF") (const_int 32)
449 (eq_attr "mode" "RVVMF4HF") (const_int 64)
450 (eq_attr "mode" "RVVM8SI") (const_int 4)
451 (eq_attr "mode" "RVVM4SI") (const_int 8)
452 (eq_attr "mode" "RVVM2SI") (const_int 16)
453 (eq_attr "mode" "RVVM1SI") (const_int 32)
454 (eq_attr "mode" "RVVMF2SI") (const_int 64)
455 (eq_attr "mode" "RVVM8SF") (const_int 4)
456 (eq_attr "mode" "RVVM4SF") (const_int 8)
457 (eq_attr "mode" "RVVM2SF") (const_int 16)
458 (eq_attr "mode" "RVVM1SF") (const_int 32)
459 (eq_attr "mode" "RVVMF2SF") (const_int 64)
460 (eq_attr "mode" "RVVM8DI") (const_int 8)
461 (eq_attr "mode" "RVVM4DI") (const_int 16)
462 (eq_attr "mode" "RVVM2DI") (const_int 32)
463 (eq_attr "mode" "RVVM1DI") (const_int 64)
464 (eq_attr "mode" "RVVM8DF") (const_int 8)
465 (eq_attr "mode" "RVVM4DF") (const_int 16)
466 (eq_attr "mode" "RVVM2DF") (const_int 32)
467 (eq_attr "mode" "RVVM1DF") (const_int 64)
468 (eq_attr "mode" "RVVM1x8QI") (const_int 8)
469 (eq_attr "mode" "RVVMF2x8QI") (const_int 16)
470 (eq_attr "mode" "RVVMF4x8QI") (const_int 32)
471 (eq_attr "mode" "RVVMF8x8QI") (const_int 64)
472 (eq_attr "mode" "RVVM1x7QI") (const_int 8)
473 (eq_attr "mode" "RVVMF2x7QI") (const_int 16)
474 (eq_attr "mode" "RVVMF4x7QI") (const_int 32)
475 (eq_attr "mode" "RVVMF8x7QI") (const_int 64)
476 (eq_attr "mode" "RVVM1x6QI") (const_int 8)
477 (eq_attr "mode" "RVVMF2x6QI") (const_int 16)
478 (eq_attr "mode" "RVVMF4x6QI") (const_int 32)
479 (eq_attr "mode" "RVVMF8x6QI") (const_int 64)
480 (eq_attr "mode" "RVVM1x5QI") (const_int 8)
481 (eq_attr "mode" "RVVMF2x5QI") (const_int 16)
482 (eq_attr "mode" "RVVMF4x5QI") (const_int 32)
483 (eq_attr "mode" "RVVMF8x5QI") (const_int 64)
484 (eq_attr "mode" "RVVM2x4QI") (const_int 4)
485 (eq_attr "mode" "RVVM1x4QI") (const_int 8)
486 (eq_attr "mode" "RVVMF2x4QI") (const_int 16)
487 (eq_attr "mode" "RVVMF4x4QI") (const_int 32)
488 (eq_attr "mode" "RVVMF8x4QI") (const_int 64)
489 (eq_attr "mode" "RVVM2x3QI") (const_int 4)
490 (eq_attr "mode" "RVVM1x3QI") (const_int 8)
491 (eq_attr "mode" "RVVMF2x3QI") (const_int 16)
492 (eq_attr "mode" "RVVMF4x3QI") (const_int 32)
493 (eq_attr "mode" "RVVMF8x3QI") (const_int 64)
494 (eq_attr "mode" "RVVM4x2QI") (const_int 2)
495 (eq_attr "mode" "RVVM2x2QI") (const_int 4)
496 (eq_attr "mode" "RVVM1x2QI") (const_int 8)
497 (eq_attr "mode" "RVVMF2x2QI") (const_int 16)
498 (eq_attr "mode" "RVVMF4x2QI") (const_int 32)
499 (eq_attr "mode" "RVVMF8x2QI") (const_int 64)
500 (eq_attr "mode" "RVVM1x8HI") (const_int 16)
501 (eq_attr "mode" "RVVMF2x8HI") (const_int 32)
502 (eq_attr "mode" "RVVMF4x8HI") (const_int 64)
503 (eq_attr "mode" "RVVM1x7HI") (const_int 16)
504 (eq_attr "mode" "RVVMF2x7HI") (const_int 32)
505 (eq_attr "mode" "RVVMF4x7HI") (const_int 64)
506 (eq_attr "mode" "RVVM1x6HI") (const_int 16)
507 (eq_attr "mode" "RVVMF2x6HI") (const_int 32)
508 (eq_attr "mode" "RVVMF4x6HI") (const_int 64)
509 (eq_attr "mode" "RVVM1x5HI") (const_int 16)
510 (eq_attr "mode" "RVVMF2x5HI") (const_int 32)
511 (eq_attr "mode" "RVVMF4x5HI") (const_int 64)
512 (eq_attr "mode" "RVVM2x4HI") (const_int 8)
513 (eq_attr "mode" "RVVM1x4HI") (const_int 16)
514 (eq_attr "mode" "RVVMF2x4HI") (const_int 32)
515 (eq_attr "mode" "RVVMF4x4HI") (const_int 64)
516 (eq_attr "mode" "RVVM2x3HI") (const_int 8)
517 (eq_attr "mode" "RVVM1x3HI") (const_int 16)
518 (eq_attr "mode" "RVVMF2x3HI") (const_int 32)
519 (eq_attr "mode" "RVVMF4x3HI") (const_int 64)
520 (eq_attr "mode" "RVVM4x2HI") (const_int 4)
521 (eq_attr "mode" "RVVM2x2HI") (const_int 8)
522 (eq_attr "mode" "RVVM1x2HI") (const_int 16)
523 (eq_attr "mode" "RVVMF2x2HI") (const_int 32)
524 (eq_attr "mode" "RVVMF4x2HI") (const_int 64)
525 (eq_attr "mode" "RVVM1x8HF") (const_int 16)
526 (eq_attr "mode" "RVVMF2x8HF") (const_int 32)
527 (eq_attr "mode" "RVVMF4x8HF") (const_int 64)
528 (eq_attr "mode" "RVVM1x7HF") (const_int 16)
529 (eq_attr "mode" "RVVMF2x7HF") (const_int 32)
530 (eq_attr "mode" "RVVMF4x7HF") (const_int 64)
531 (eq_attr "mode" "RVVM1x6HF") (const_int 16)
532 (eq_attr "mode" "RVVMF2x6HF") (const_int 32)
533 (eq_attr "mode" "RVVMF4x6HF") (const_int 64)
534 (eq_attr "mode" "RVVM1x5HF") (const_int 16)
535 (eq_attr "mode" "RVVMF2x5HF") (const_int 32)
536 (eq_attr "mode" "RVVMF4x5HF") (const_int 64)
537 (eq_attr "mode" "RVVM2x4HF") (const_int 8)
538 (eq_attr "mode" "RVVM1x4HF") (const_int 16)
539 (eq_attr "mode" "RVVMF2x4HF") (const_int 32)
540 (eq_attr "mode" "RVVMF4x4HF") (const_int 64)
541 (eq_attr "mode" "RVVM2x3HF") (const_int 8)
542 (eq_attr "mode" "RVVM1x3HF") (const_int 16)
543 (eq_attr "mode" "RVVMF2x3HF") (const_int 32)
544 (eq_attr "mode" "RVVMF4x3HF") (const_int 64)
545 (eq_attr "mode" "RVVM4x2HF") (const_int 4)
546 (eq_attr "mode" "RVVM2x2HF") (const_int 8)
547 (eq_attr "mode" "RVVM1x2HF") (const_int 16)
548 (eq_attr "mode" "RVVMF2x2HF") (const_int 32)
549 (eq_attr "mode" "RVVMF4x2HF") (const_int 64)
550 (eq_attr "mode" "RVVM1x8SI") (const_int 32)
551 (eq_attr "mode" "RVVMF2x8SI") (const_int 64)
552 (eq_attr "mode" "RVVM1x7SI") (const_int 32)
553 (eq_attr "mode" "RVVMF2x7SI") (const_int 64)
554 (eq_attr "mode" "RVVM1x6SI") (const_int 32)
555 (eq_attr "mode" "RVVMF2x6SI") (const_int 64)
556 (eq_attr "mode" "RVVM1x5SI") (const_int 32)
557 (eq_attr "mode" "RVVMF2x5SI") (const_int 64)
558 (eq_attr "mode" "RVVM2x4SI") (const_int 16)
559 (eq_attr "mode" "RVVM1x4SI") (const_int 32)
560 (eq_attr "mode" "RVVMF2x4SI") (const_int 64)
561 (eq_attr "mode" "RVVM2x3SI") (const_int 16)
562 (eq_attr "mode" "RVVM1x3SI") (const_int 32)
563 (eq_attr "mode" "RVVMF2x3SI") (const_int 64)
564 (eq_attr "mode" "RVVM4x2SI") (const_int 8)
565 (eq_attr "mode" "RVVM2x2SI") (const_int 16)
566 (eq_attr "mode" "RVVM1x2SI") (const_int 32)
567 (eq_attr "mode" "RVVMF2x2SI") (const_int 64)
568 (eq_attr "mode" "RVVM1x8SF") (const_int 32)
569 (eq_attr "mode" "RVVMF2x8SF") (const_int 64)
570 (eq_attr "mode" "RVVM1x7SF") (const_int 32)
571 (eq_attr "mode" "RVVMF2x7SF") (const_int 64)
572 (eq_attr "mode" "RVVM1x6SF") (const_int 32)
573 (eq_attr "mode" "RVVMF2x6SF") (const_int 64)
574 (eq_attr "mode" "RVVM1x5SF") (const_int 32)
575 (eq_attr "mode" "RVVMF2x5SF") (const_int 64)
576 (eq_attr "mode" "RVVM2x4SF") (const_int 16)
577 (eq_attr "mode" "RVVM1x4SF") (const_int 32)
578 (eq_attr "mode" "RVVMF2x4SF") (const_int 64)
579 (eq_attr "mode" "RVVM2x3SF") (const_int 16)
580 (eq_attr "mode" "RVVM1x3SF") (const_int 32)
581 (eq_attr "mode" "RVVMF2x3SF") (const_int 64)
582 (eq_attr "mode" "RVVM4x2SF") (const_int 8)
583 (eq_attr "mode" "RVVM2x2SF") (const_int 16)
584 (eq_attr "mode" "RVVM1x2SF") (const_int 32)
585 (eq_attr "mode" "RVVMF2x2SF") (const_int 64)
586 (eq_attr "mode" "RVVM1x8DI") (const_int 64)
587 (eq_attr "mode" "RVVM1x7DI") (const_int 64)
588 (eq_attr "mode" "RVVM1x6DI") (const_int 64)
589 (eq_attr "mode" "RVVM1x5DI") (const_int 64)
590 (eq_attr "mode" "RVVM2x4DI") (const_int 32)
591 (eq_attr "mode" "RVVM1x4DI") (const_int 64)
592 (eq_attr "mode" "RVVM2x3DI") (const_int 32)
593 (eq_attr "mode" "RVVM1x3DI") (const_int 64)
594 (eq_attr "mode" "RVVM4x2DI") (const_int 16)
595 (eq_attr "mode" "RVVM2x2DI") (const_int 32)
596 (eq_attr "mode" "RVVM1x2DI") (const_int 64)
597 (eq_attr "mode" "RVVM1x8DF") (const_int 64)
598 (eq_attr "mode" "RVVM1x7DF") (const_int 64)
599 (eq_attr "mode" "RVVM1x6DF") (const_int 64)
600 (eq_attr "mode" "RVVM1x5DF") (const_int 64)
601 (eq_attr "mode" "RVVM2x4DF") (const_int 32)
602 (eq_attr "mode" "RVVM1x4DF") (const_int 64)
603 (eq_attr "mode" "RVVM2x3DF") (const_int 32)
604 (eq_attr "mode" "RVVM1x3DF") (const_int 64)
605 (eq_attr "mode" "RVVM4x2DF") (const_int 16)
606 (eq_attr "mode" "RVVM2x2DF") (const_int 32)
607 (eq_attr "mode" "RVVM1x2DF") (const_int 64)
609 ;; VLS modes.
610 (eq_attr "mode" "V1QI,V1BI") (symbol_ref "riscv_vector::get_ratio(E_V1QImode)")
611 (eq_attr "mode" "V2QI,V2BI") (symbol_ref "riscv_vector::get_ratio(E_V2QImode)")
612 (eq_attr "mode" "V4QI,V4BI") (symbol_ref "riscv_vector::get_ratio(E_V4QImode)")
613 (eq_attr "mode" "V8QI,V8BI") (symbol_ref "riscv_vector::get_ratio(E_V8QImode)")
614 (eq_attr "mode" "V16QI,V16BI") (symbol_ref "riscv_vector::get_ratio(E_V16QImode)")
615 (eq_attr "mode" "V32QI,V32BI") (symbol_ref "riscv_vector::get_ratio(E_V32QImode)")
616 (eq_attr "mode" "V64QI,V64BI") (symbol_ref "riscv_vector::get_ratio(E_V64QImode)")
617 (eq_attr "mode" "V128QI,V128BI") (symbol_ref "riscv_vector::get_ratio(E_V128QImode)")
618 (eq_attr "mode" "V256QI,V256BI") (symbol_ref "riscv_vector::get_ratio(E_V256QImode)")
619 (eq_attr "mode" "V512QI,V512BI") (symbol_ref "riscv_vector::get_ratio(E_V512QImode)")
620 (eq_attr "mode" "V1024QI,V1024BI") (symbol_ref "riscv_vector::get_ratio(E_V1024QImode)")
621 (eq_attr "mode" "V2048QI,V2048BI") (symbol_ref "riscv_vector::get_ratio(E_V2048QImode)")
622 (eq_attr "mode" "V4096QI,V4096BI") (symbol_ref "riscv_vector::get_ratio(E_V4096QImode)")
623 (eq_attr "mode" "V1HI") (symbol_ref "riscv_vector::get_ratio(E_V1HImode)")
624 (eq_attr "mode" "V2HI") (symbol_ref "riscv_vector::get_ratio(E_V2HImode)")
625 (eq_attr "mode" "V4HI") (symbol_ref "riscv_vector::get_ratio(E_V4HImode)")
626 (eq_attr "mode" "V8HI") (symbol_ref "riscv_vector::get_ratio(E_V8HImode)")
627 (eq_attr "mode" "V16HI") (symbol_ref "riscv_vector::get_ratio(E_V16HImode)")
628 (eq_attr "mode" "V32HI") (symbol_ref "riscv_vector::get_ratio(E_V32HImode)")
629 (eq_attr "mode" "V64HI") (symbol_ref "riscv_vector::get_ratio(E_V64HImode)")
630 (eq_attr "mode" "V128HI") (symbol_ref "riscv_vector::get_ratio(E_V128HImode)")
631 (eq_attr "mode" "V256HI") (symbol_ref "riscv_vector::get_ratio(E_V256HImode)")
632 (eq_attr "mode" "V512HI") (symbol_ref "riscv_vector::get_ratio(E_V512HImode)")
633 (eq_attr "mode" "V1024HI") (symbol_ref "riscv_vector::get_ratio(E_V1024HImode)")
634 (eq_attr "mode" "V2048HI") (symbol_ref "riscv_vector::get_ratio(E_V2048HImode)")
635 (eq_attr "mode" "V1SI") (symbol_ref "riscv_vector::get_ratio(E_V1SImode)")
636 (eq_attr "mode" "V2SI") (symbol_ref "riscv_vector::get_ratio(E_V2SImode)")
637 (eq_attr "mode" "V4SI") (symbol_ref "riscv_vector::get_ratio(E_V4SImode)")
638 (eq_attr "mode" "V8SI") (symbol_ref "riscv_vector::get_ratio(E_V8SImode)")
639 (eq_attr "mode" "V16SI") (symbol_ref "riscv_vector::get_ratio(E_V16SImode)")
640 (eq_attr "mode" "V32SI") (symbol_ref "riscv_vector::get_ratio(E_V32SImode)")
641 (eq_attr "mode" "V64SI") (symbol_ref "riscv_vector::get_ratio(E_V64SImode)")
642 (eq_attr "mode" "V128SI") (symbol_ref "riscv_vector::get_ratio(E_V128SImode)")
643 (eq_attr "mode" "V256SI") (symbol_ref "riscv_vector::get_ratio(E_V256SImode)")
644 (eq_attr "mode" "V512SI") (symbol_ref "riscv_vector::get_ratio(E_V512SImode)")
645 (eq_attr "mode" "V1024SI") (symbol_ref "riscv_vector::get_ratio(E_V1024SImode)")
646 (eq_attr "mode" "V1DI") (symbol_ref "riscv_vector::get_ratio(E_V1DImode)")
647 (eq_attr "mode" "V2DI") (symbol_ref "riscv_vector::get_ratio(E_V2DImode)")
648 (eq_attr "mode" "V4DI") (symbol_ref "riscv_vector::get_ratio(E_V4DImode)")
649 (eq_attr "mode" "V8DI") (symbol_ref "riscv_vector::get_ratio(E_V8DImode)")
650 (eq_attr "mode" "V16DI") (symbol_ref "riscv_vector::get_ratio(E_V16DImode)")
651 (eq_attr "mode" "V32DI") (symbol_ref "riscv_vector::get_ratio(E_V32DImode)")
652 (eq_attr "mode" "V64DI") (symbol_ref "riscv_vector::get_ratio(E_V64DImode)")
653 (eq_attr "mode" "V128DI") (symbol_ref "riscv_vector::get_ratio(E_V128DImode)")
654 (eq_attr "mode" "V256DI") (symbol_ref "riscv_vector::get_ratio(E_V256DImode)")
655 (eq_attr "mode" "V512DI") (symbol_ref "riscv_vector::get_ratio(E_V512DImode)")
656 (eq_attr "mode" "V1HF") (symbol_ref "riscv_vector::get_ratio(E_V1HFmode)")
657 (eq_attr "mode" "V2HF") (symbol_ref "riscv_vector::get_ratio(E_V2HFmode)")
658 (eq_attr "mode" "V4HF") (symbol_ref "riscv_vector::get_ratio(E_V4HFmode)")
659 (eq_attr "mode" "V8HF") (symbol_ref "riscv_vector::get_ratio(E_V8HFmode)")
660 (eq_attr "mode" "V16HF") (symbol_ref "riscv_vector::get_ratio(E_V16HFmode)")
661 (eq_attr "mode" "V32HF") (symbol_ref "riscv_vector::get_ratio(E_V32HFmode)")
662 (eq_attr "mode" "V64HF") (symbol_ref "riscv_vector::get_ratio(E_V64HFmode)")
663 (eq_attr "mode" "V128HF") (symbol_ref "riscv_vector::get_ratio(E_V128HFmode)")
664 (eq_attr "mode" "V256HF") (symbol_ref "riscv_vector::get_ratio(E_V256HFmode)")
665 (eq_attr "mode" "V512HF") (symbol_ref "riscv_vector::get_ratio(E_V512HFmode)")
666 (eq_attr "mode" "V1024HF") (symbol_ref "riscv_vector::get_ratio(E_V1024HFmode)")
667 (eq_attr "mode" "V2048HF") (symbol_ref "riscv_vector::get_ratio(E_V2048HFmode)")
668 (eq_attr "mode" "V1SF") (symbol_ref "riscv_vector::get_ratio(E_V1SFmode)")
669 (eq_attr "mode" "V2SF") (symbol_ref "riscv_vector::get_ratio(E_V2SFmode)")
670 (eq_attr "mode" "V4SF") (symbol_ref "riscv_vector::get_ratio(E_V4SFmode)")
671 (eq_attr "mode" "V8SF") (symbol_ref "riscv_vector::get_ratio(E_V8SFmode)")
672 (eq_attr "mode" "V16SF") (symbol_ref "riscv_vector::get_ratio(E_V16SFmode)")
673 (eq_attr "mode" "V32SF") (symbol_ref "riscv_vector::get_ratio(E_V32SFmode)")
674 (eq_attr "mode" "V64SF") (symbol_ref "riscv_vector::get_ratio(E_V64SFmode)")
675 (eq_attr "mode" "V128SF") (symbol_ref "riscv_vector::get_ratio(E_V128SFmode)")
676 (eq_attr "mode" "V256SF") (symbol_ref "riscv_vector::get_ratio(E_V256SFmode)")
677 (eq_attr "mode" "V512SF") (symbol_ref "riscv_vector::get_ratio(E_V512SFmode)")
678 (eq_attr "mode" "V1024SF") (symbol_ref "riscv_vector::get_ratio(E_V1024SFmode)")
679 (eq_attr "mode" "V1DF") (symbol_ref "riscv_vector::get_ratio(E_V1DFmode)")
680 (eq_attr "mode" "V2DF") (symbol_ref "riscv_vector::get_ratio(E_V2DFmode)")
681 (eq_attr "mode" "V4DF") (symbol_ref "riscv_vector::get_ratio(E_V4DFmode)")
682 (eq_attr "mode" "V8DF") (symbol_ref "riscv_vector::get_ratio(E_V8DFmode)")
683 (eq_attr "mode" "V16DF") (symbol_ref "riscv_vector::get_ratio(E_V16DFmode)")
684 (eq_attr "mode" "V32DF") (symbol_ref "riscv_vector::get_ratio(E_V32DFmode)")
685 (eq_attr "mode" "V64DF") (symbol_ref "riscv_vector::get_ratio(E_V64DFmode)")
686 (eq_attr "mode" "V128DF") (symbol_ref "riscv_vector::get_ratio(E_V128DFmode)")
687 (eq_attr "mode" "V256DF") (symbol_ref "riscv_vector::get_ratio(E_V256DFmode)")
688 (eq_attr "mode" "V512DF") (symbol_ref "riscv_vector::get_ratio(E_V512DFmode)")]
689 (const_int INVALID_ATTRIBUTE)))
691 ;; The index of operand[] to get the merge op.
692 (define_attr "merge_op_idx" ""
693 (cond [(eq_attr "type" "vlde,vimov,vfmov,vldm,vlds,vmalu,vldux,vldox,vicmp,\
694 vialu,vshift,viminmax,vimul,vidiv,vsalu,vext,viwalu,\
695 viwmul,vnshift,vaalu,vsmul,vsshift,vnclip,vmsfs,\
696 vmiota,vmidx,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
697 vfsqrt,vfrecp,vfsgnj,vfcmp,vfcvtitof,vfcvtftoi,vfwcvtitof,\
698 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,\
699 vired,viwred,vfredu,vfredo,vfwredu,vfwredo,vimovxv,vfmovfv,\
700 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
701 vgather,vldff,viwmuladd,vfwmuladd,vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff")
702 (const_int 2)
704 (eq_attr "type" "vimerge,vfmerge,vcompress")
705 (const_int 1)
707 (eq_attr "type" "vimuladd,vfmuladd")
708 (const_int 5)]
709 (const_int INVALID_ATTRIBUTE)))
711 ;; The index of operand[] represents the machine mode of the instruction.
712 (define_attr "mode_idx" ""
713 (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vldff,vldr,vstr,\
714 vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vialu,vext,vicalu,\
715 vshift,vicmp,viminmax,vimul,vidiv,vimuladd,vimerge,vimov,\
716 vsalu,vaalu,vsmul,vsshift,vfalu,vfmul,vfdiv,vfmuladd,vfsqrt,vfrecp,\
717 vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\
718 vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\
719 vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
720 vgather,vcompress,vmov,vnclip,vnshift")
721 (const_int 0)
723 (eq_attr "type" "vimovvx,vfmovvf")
724 (const_int 1)
726 (eq_attr "type" "vssegte,vmpop,vmffs")
727 (const_int 2)
729 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi,
730 vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo")
731 (const_int 3)
733 (eq_attr "type" "viwalu,viwmul,viwmuladd,vfwalu,vfwmul,vfwmuladd")
734 (const_int 4)]
735 (const_int INVALID_ATTRIBUTE)))
737 ;; The index of operand[] to get the avl op.
738 (define_attr "vl_op_idx" ""
739 (cond [(eq_attr "type" "vlde,vste,vimov,vfmov,vldm,vstm,vmalu,vsts,vstux,\
740 vstox,vext,vmsfs,vmiota,vfsqrt,vfrecp,vfcvtitof,vldff,\
741 vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,\
742 vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,vcompress,\
743 vlsegde,vssegts,vssegtux,vssegtox,vlsegdff")
744 (const_int 4)
746 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
747 ;; wheras it is pred_strided_load if operands[3] is vector mode.
748 (eq_attr "type" "vlds")
749 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
750 (const_int 5)
751 (const_int 4))
753 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
754 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
755 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
756 vfsgnj,vfmerge,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
757 vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
758 vgather,viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox")
759 (const_int 5)
761 (eq_attr "type" "vicmp,vimuladd,vfcmp,vfmuladd")
762 (const_int 6)
764 (eq_attr "type" "vmpop,vmffs,vmidx,vssegte")
765 (const_int 3)]
766 (const_int INVALID_ATTRIBUTE)))
768 ;; The tail policy op value.
769 (define_attr "ta" ""
770 (cond [(eq_attr "type" "vlde,vimov,vfmov,vext,vmiota,vfsqrt,vfrecp,\
771 vfcvtitof,vfcvtftoi,vfwcvtitof,vfwcvtftoi,vfwcvtftof,\
772 vfncvtitof,vfncvtftoi,vfncvtftof,vfclass,vimovxv,vfmovfv,\
773 vcompress,vldff,vlsegde,vlsegdff")
774 (symbol_ref "riscv_vector::get_ta(operands[5])")
776 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
777 ;; wheras it is pred_strided_load if operands[3] is vector mode.
778 (eq_attr "type" "vlds")
779 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
780 (symbol_ref "riscv_vector::get_ta(operands[6])")
781 (symbol_ref "riscv_vector::get_ta(operands[5])"))
783 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
784 viwalu,viwmul,vnshift,vimerge,vaalu,vsmul,\
785 vsshift,vnclip,vfalu,vfmul,vfminmax,vfdiv,\
786 vfwalu,vfwmul,vfsgnj,vfmerge,vired,viwred,vfredu,\
787 vfredo,vfwredu,vfwredo,vslideup,vslidedown,vislide1up,\
788 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
789 vlsegds,vlsegdux,vlsegdox")
790 (symbol_ref "riscv_vector::get_ta(operands[6])")
792 (eq_attr "type" "vimuladd,vfmuladd")
793 (symbol_ref "riscv_vector::get_ta(operands[7])")
795 (eq_attr "type" "vmidx")
796 (symbol_ref "riscv_vector::get_ta(operands[4])")]
797 (const_int INVALID_ATTRIBUTE)))
799 ;; The mask policy op value.
800 (define_attr "ma" ""
801 (cond [(eq_attr "type" "vlde,vext,vmiota,vfsqrt,vfrecp,vfcvtitof,vfcvtftoi,\
802 vfwcvtitof,vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,\
803 vfncvtftof,vfclass,vldff,vlsegde,vlsegdff")
804 (symbol_ref "riscv_vector::get_ma(operands[6])")
806 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
807 ;; wheras it is pred_strided_load if operands[3] is vector mode.
808 (eq_attr "type" "vlds")
809 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
810 (symbol_ref "riscv_vector::get_ma(operands[7])")
811 (symbol_ref "riscv_vector::get_ma(operands[6])"))
813 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
814 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
815 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,\
816 vfwalu,vfwmul,vfsgnj,vfcmp,vslideup,vslidedown,\
817 vislide1up,vislide1down,vfslide1up,vfslide1down,vgather,\
818 viwmuladd,vfwmuladd,vlsegds,vlsegdux,vlsegdox")
819 (symbol_ref "riscv_vector::get_ma(operands[7])")
821 (eq_attr "type" "vimuladd,vfmuladd")
822 (symbol_ref "riscv_vector::get_ma(operands[8])")
824 (eq_attr "type" "vmsfs,vmidx")
825 (symbol_ref "riscv_vector::get_ma(operands[5])")]
826 (const_int INVALID_ATTRIBUTE)))
828 ;; The avl type value.
829 (define_attr "avl_type_idx" ""
830 (cond [(eq_attr "type" "vlde,vldff,vste,vimov,vfmov,vext,vimerge,\
831 vfsqrt,vfrecp,vfmerge,vfcvtitof,vfcvtftoi,vfwcvtitof,\
832 vfwcvtftoi,vfwcvtftof,vfncvtitof,vfncvtftoi,vfncvtftof,\
833 vfclass,vired,viwred,vfredu,vfredo,vfwredu,vfwredo,\
834 vimovxv,vfmovfv,vlsegde,vlsegdff")
835 (const_int 7)
836 (eq_attr "type" "vldm,vstm,vmalu,vmalu")
837 (const_int 5)
839 ;; If operands[3] of "vlds" is not vector mode, it is pred_broadcast.
840 ;; wheras it is pred_strided_load if operands[3] is vector mode.
841 (eq_attr "type" "vlds")
842 (if_then_else (match_test "VECTOR_MODE_P (GET_MODE (operands[3]))")
843 (const_int 8)
844 (const_int 7))
846 (eq_attr "type" "vldux,vldox,vialu,vshift,viminmax,vimul,vidiv,vsalu,\
847 viwalu,viwmul,vnshift,vaalu,vsmul,vsshift,\
848 vnclip,vicmp,vfalu,vfmul,vfminmax,vfdiv,vfwalu,vfwmul,\
849 vfsgnj,vfcmp,vslideup,vslidedown,vislide1up,\
850 vislide1down,vfslide1up,vfslide1down,vgather,viwmuladd,vfwmuladd,\
851 vlsegds,vlsegdux,vlsegdox")
852 (const_int 8)
853 (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox")
854 (const_int 5)
856 (eq_attr "type" "vimuladd,vfmuladd")
857 (const_int 9)
859 (eq_attr "type" "vmsfs,vmidx,vcompress")
860 (const_int 6)
862 (eq_attr "type" "vmpop,vmffs,vssegte")
863 (const_int 4)]
864 (const_int INVALID_ATTRIBUTE)))
866 ;; Defines rounding mode of an fixed-point operation.
868 (define_attr "vxrm_mode" "rnu,rne,rdn,rod,none"
869 (cond [(eq_attr "type" "vaalu,vsmul,vsshift,vnclip")
870 (cond
871 [(match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNU")
872 (const_string "rnu")
874 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RNE")
875 (const_string "rne")
877 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_RDN")
878 (const_string "rdn")
880 (match_test "INTVAL (operands[9]) == riscv_vector::VXRM_ROD")
881 (const_string "rod")]
882 (const_string "none"))]
883 (const_string "none")))
885 ;; Defines rounding mode of an floating-point operation.
886 (define_attr "frm_mode" ""
887 (cond [(eq_attr "type" "vfalu,vfwalu,vfmul,vfdiv,vfwmul")
888 (symbol_ref "riscv_vector::FRM_DYN")]
889 (symbol_ref "riscv_vector::FRM_NONE")))
891 ;; -----------------------------------------------------------------
892 ;; ---- Miscellaneous Operations
893 ;; -----------------------------------------------------------------
895 (define_insn "@vundefined<mode>"
896 [(set (match_operand:V 0 "register_operand" "=vr")
897 (unspec:V [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
898 "TARGET_VECTOR"
899 ""
900 [(set_attr "type" "vector")])
902 (define_insn "@vundefined<mode>"
903 [(set (match_operand:VB 0 "register_operand" "=vr")
904 (unspec:VB [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
905 "TARGET_VECTOR"
906 ""
907 [(set_attr "type" "vector")])
909 (define_insn "@vundefined<mode>"
910 [(set (match_operand:VT 0 "register_operand" "=vr")
911 (unspec:VT [(reg:SI X0_REGNUM)] UNSPEC_VUNDEF))]
912 "TARGET_VECTOR"
913 ""
914 [(set_attr "type" "vector")])
916 (define_expand "@vreinterpret<mode>"
917 [(set (match_operand:V 0 "register_operand")
918 (match_operand 1 "vector_any_register_operand"))]
919 "TARGET_VECTOR"
920 {
921 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
922 DONE;
923 }
924 )
926 (define_expand "@vreinterpret<mode>"
927 [(set (match_operand:VB 0 "register_operand")
928 (match_operand 1 "vector_any_register_operand"))]
929 "TARGET_VECTOR"
930 {
931 emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
932 DONE;
933 }
934 )
936 ;; This pattern is used to hold the AVL operand for
937 ;; RVV instructions that implicity use VLMAX AVL.
938 ;; RVV instruction implicitly use GPR that is ultimately
939 ;; defined by this pattern is safe for VSETVL pass emit
940 ;; a vsetvl instruction modify this register after RA.
941 ;; Case 1:
942 ;; vlmax_avl a5
943 ;; ... (across many blocks)
944 ;; vadd (implicit use a5) ====> emit: vsetvl a5,zero
945 ;; Case 2:
946 ;; vlmax_avl a5
947 ;; ... (across many blocks)
948 ;; mv a6,a5
949 ;; ... (across many blocks)
950 ;; vadd (implicit use a6) ====> emit: vsetvl a6,zero
951 ;; Case 3:
952 ;; vlmax_avl a5
953 ;; ... (across many blocks)
954 ;; store mem,a5 (spill)
955 ;; ... (across many blocks)
956 ;; load a7,mem (spill)
957 ;; ... (across many blocks)
958 ;; vadd (implicit use a7) ====> emit: vsetvl a7,zero
959 ;; Such cases are all safe for VSETVL PASS to emit a vsetvl
960 ;; instruction that modifies the AVL operand.
961 (define_insn "@vlmax_avl<mode>"
962 [(set (match_operand:P 0 "register_operand" "=r")
963 (unspec:P [(match_operand:P 1 "const_int_operand" "i")] UNSPEC_VLMAX))]
964 "TARGET_VECTOR"
965 ""
966 [(set_attr "type" "vsetvl_pre")]
967 )
969 ;; Set VXRM
970 (define_insn "vxrmsi"
971 [(set (reg:SI VXRM_REGNUM)
972 (match_operand:SI 0 "const_int_operand" "i"))]
973 "TARGET_VECTOR"
974 "csrwi\tvxrm,%0"
975 [(set_attr "type" "wrvxrm")
976 (set_attr "mode" "SI")])
978 ;; Set FRM
979 (define_insn "fsrmsi_backup"
980 [(set (match_operand:SI 0 "register_operand" "=r,r")
981 (reg:SI FRM_REGNUM))
982 (set (reg:SI FRM_REGNUM)
983 (match_operand:SI 1 "reg_or_int_operand" "r,i"))]
984 "TARGET_VECTOR"
985 "@
986 fsrm\t%0,%1
987 fsrmi\t%0,%1"
988 [(set_attr "type" "wrfrm,wrfrm")
989 (set_attr "mode" "SI")]
990 )
992 (define_insn "fsrmsi_restore"
993 [(set (reg:SI FRM_REGNUM)
994 (match_operand:SI 0 "reg_or_int_operand" "r,i"))]
995 "TARGET_VECTOR"
996 "@
997 fsrm\t%0
998 fsrmi\t%0"
999 [(set_attr "type" "wrfrm,wrfrm")
1000 (set_attr "mode" "SI")]
1001 )
1003 ;; The volatile fsrmsi restore is used for the exit point for the
1004 ;; dynamic mode switching. It will generate one volatile fsrm a5
1005 ;; which won't be eliminated.
1006 (define_insn "fsrmsi_restore_volatile"
1007 [(set (reg:SI FRM_REGNUM)
1008 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1009 UNSPECV_FRM_RESTORE_EXIT))]
1010 "TARGET_VECTOR"
1011 "fsrm\t%0"
1012 [(set_attr "type" "wrfrm")
1013 (set_attr "mode" "SI")]
1014 )
1016 ;; Read FRM
1017 (define_insn "frrmsi"
1018 [(set (match_operand:SI 0 "register_operand" "=r")
1019 (reg:SI FRM_REGNUM))]
1020 "TARGET_VECTOR"
1021 "frrm\t%0"
1022 [(set_attr "type" "rdfrm")
1023 (set_attr "mode" "SI")]
1024 )
1026 ;; -----------------------------------------------------------------
1027 ;; ---- Moves Operations
1028 ;; -----------------------------------------------------------------
1030 (define_expand "mov<mode>"
1031 [(set (match_operand:V 0 "reg_or_mem_operand")
1032 (match_operand:V 1 "general_operand"))]
1033 "TARGET_VECTOR"
1034 {
1035 /* For whole register move, we transform the pattern into the format
1036 that excludes the clobber of scratch register.
1038 We include clobber of a scalar scratch register which is going to be
1039 used for emit of vsetvl instruction after reload_completed since we
1040 need vsetvl instruction to set VL/VTYPE global status for fractional
1041 vector load/store.
1043 For example:
1044 [(set (match_operand:RVVMF8QI v24)
1045 (match_operand:RVVMF8QI (mem: a4)))
1046 (clobber (scratch:SI a5))]
1047 ====>> vsetvl a5,zero,e8,mf8
1048 ====>> vle8.v v24,(a4)
1050 Philosophy:
1052 - Clobber a scalar scratch register for each mov<mode>.
1054 - Classify the machine_mode mode = <MODE>mode into 2 class:
1055 Whole register move and fractional register move.
1057 - Transform and remove scratch clobber register for whole
1058 register move so that we can avoid occupying the scalar
1059 registers.
1061 - We can not leave it to TARGET_SECONDARY_RELOAD since it happens
1062 before spilling. The clobber scratch is used by spilling fractional
1063 registers in IRA/LRA so it's too early. */
1065 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1066 DONE;
1067 })
1069 ;; This pattern is used for code-gen for whole register load/stores.
1070 ;; Also applicable for all register moves.
1071 ;; Fractional vector modes load/store are not allowed to match this pattern.
1072 ;; Mask modes load/store are not allowed to match this pattern.
1073 ;; We seperate "*mov<mode>" into "*mov<mode>_whole" and "*mov<mode>_fract" because
1074 ;; we don't want to include fractional load/store in "*mov<mode>" which will
1075 ;; create unexpected patterns in LRA.
1076 ;; For example:
1077 ;; ira rtl:
1078 ;; (insn 20 19 9 2 (set (reg/v:RVVMF4QI 97 v1 [ v1 ])
1079 ;; (reg:RVVMF4QI 134 [ _1 ])) "rvv.c":9:22 571 {*movvnx2qi_fract}
1080 ;; (nil))
1081 ;; When the value of pseudo register 134 of the insn above is discovered already
1082 ;; spilled in the memory during LRA.
1083 ;; LRA will reload this pattern into a memory load instruction pattern.
1084 ;; Because RVVMF4QI is a fractional vector, we want LRA reload this pattern into
1085 ;; (insn 20 19 9 2 (parallel [
1086 ;; (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1087 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8]))
1088 ;; (clobber (reg:SI 14 a4 [149]))])
1089 ;; So that we could be able to emit vsetvl instruction using clobber sratch a4.
1090 ;; To let LRA generate the expected pattern, we should exclude fractional vector
1091 ;; load/store in "*mov<mode>_whole". Otherwise, it will reload this pattern into:
1092 ;; (insn 20 19 9 2 (set (reg:RVVMF4QI 98 v2 [orig:134 _1 ] [134])
1093 ;; (mem/c:RVVMF4QI (reg:SI 13 a3 [155]) [1 %sfp+[-2, -2] S[2, 2] A8])))
1094 ;; which is not the pattern we want.
1095 ;; According the facts above, we make "*mov<mode>_whole" includes load/store/move for whole
1096 ;; vector modes according to '-march' and "*mov<mode>_fract" only include fractional vector modes.
1097 (define_insn "*mov<mode>_whole"
1098 [(set (match_operand:V_WHOLE 0 "reg_or_mem_operand" "=vr, m,vr")
1099 (match_operand:V_WHOLE 1 "reg_or_mem_operand" " m,vr,vr"))]
1100 "TARGET_VECTOR"
1101 "@
1102 vl%m1re<sew>.v\t%0,%1
1103 vs%m1r.v\t%1,%0
1104 vmv%m1r.v\t%0,%1"
1105 [(set_attr "type" "vldr,vstr,vmov")
1106 (set_attr "mode" "<MODE>")])
1108 (define_insn "*mov<mode>_fract"
1109 [(set (match_operand:V_FRACT 0 "register_operand" "=vr")
1110 (match_operand:V_FRACT 1 "register_operand" " vr"))]
1111 "TARGET_VECTOR"
1112 "vmv1r.v\t%0,%1"
1113 [(set_attr "type" "vmov")
1114 (set_attr "mode" "<MODE>")])
1116 (define_expand "mov<mode>"
1117 [(set (match_operand:VB 0 "reg_or_mem_operand")
1118 (match_operand:VB 1 "general_operand"))]
1119 "TARGET_VECTOR"
1120 {
1121 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1122 DONE;
1123 })
1125 (define_insn "*mov<mode>"
1126 [(set (match_operand:VB 0 "register_operand" "=vr")
1127 (match_operand:VB 1 "register_operand" " vr"))]
1128 "TARGET_VECTOR"
1129 "vmv1r.v\t%0,%1"
1130 [(set_attr "type" "vmov")
1131 (set_attr "mode" "<MODE>")])
1133 (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
1134 [(parallel
1135 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
1136 (match_operand:V_FRACT 1 "reg_or_mem_operand"))
1137 (clobber (match_scratch:P 2))])]
1138 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1139 {})
1141 (define_expand "@mov<VB:mode><P:mode>_lra"
1142 [(parallel
1143 [(set (match_operand:VB 0 "reg_or_mem_operand")
1144 (match_operand:VB 1 "reg_or_mem_operand"))
1145 (clobber (match_scratch:P 2))])]
1146 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1147 {})
1149 (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
1150 [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
1151 (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
1152 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1153 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1154 "#"
1155 "&& reload_completed"
1156 [(const_int 0)]
1157 {
1158 if (REG_P (operands[0]) && REG_P (operands[1]))
1159 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1160 else
1161 {
1162 riscv_vector::emit_vlmax_vsetvl (<V_FRACT:MODE>mode, operands[2]);
1163 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<V_FRACT:MODE>mode),
1164 riscv_vector::UNARY_OP, operands, operands[2]);
1165 }
1166 DONE;
1167 }
1168 [(set_attr "type" "vector")]
1169 )
1171 (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
1172 [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
1173 (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
1174 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1175 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1176 "#"
1177 "&& reload_completed"
1178 [(const_int 0)]
1179 {
1180 if (REG_P (operands[0]) && REG_P (operands[1]))
1181 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1182 else
1183 {
1184 riscv_vector::emit_vlmax_vsetvl (<VB:MODE>mode, operands[2]);
1185 riscv_vector::emit_vlmax_insn_lra (code_for_pred_mov (<VB:MODE>mode),
1186 riscv_vector::UNARY_MASK_OP, operands, operands[2]);
1187 }
1188 DONE;
1189 }
1190 [(set_attr "type" "vector")]
1191 )
1193 ;; Define tuple modes data movement.
1194 ;; operands[2] is used to save the offset of each subpart.
1195 ;; operands[3] is used to calculate the address for each subpart.
1196 ;; operands[4] is VL of vsevli instruction.
1197 (define_expand "mov<mode>"
1198 [(parallel [(set (match_operand:VT 0 "reg_or_mem_operand")
1199 (match_operand:VT 1 "general_operand"))
1200 (clobber (match_dup 2))
1201 (clobber (match_dup 3))
1202 (clobber (match_dup 4))])]
1203 "TARGET_VECTOR"
1204 {
1205 /* Need to force register if mem <- !reg. */
1206 if (MEM_P (operands[0]) && !REG_P (operands[1]))
1207 operands[1] = force_reg (<MODE>mode, operands[1]);
1209 if (GET_CODE (operands[1]) == CONST_VECTOR)
1210 {
1211 riscv_vector::expand_tuple_move (operands);
1212 DONE;
1213 }
1215 operands[2] = gen_rtx_SCRATCH (Pmode);
1216 operands[3] = gen_rtx_SCRATCH (Pmode);
1217 operands[4] = gen_rtx_SCRATCH (Pmode);
1218 })
1220 (define_insn_and_split "*mov<VT:mode>_<P:mode>"
1221 [(set (match_operand:VT 0 "reg_or_mem_operand" "=vr,vr, m")
1222 (match_operand:VT 1 "reg_or_mem_operand" " vr, m,vr"))
1223 (clobber (match_scratch:P 2 "=X,&r,&r"))
1224 (clobber (match_scratch:P 3 "=X,&r,&r"))
1225 (clobber (match_scratch:P 4 "=X,&r,&r"))]
1226 "TARGET_VECTOR"
1227 "#"
1228 "&& reload_completed"
1229 [(const_int 0)]
1230 {
1231 riscv_vector::expand_tuple_move (operands);
1232 DONE;
1233 }
1234 [(set_attr "type" "vmov,vlde,vste")
1235 (set_attr "mode" "<VT:MODE>")
1236 (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))
1237 (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))])
1239 ;; -----------------------------------------------------------------
1240 ;; ---- VLS Moves Operations
1241 ;; -----------------------------------------------------------------
1243 (define_expand "mov<mode>"
1244 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand")
1245 (match_operand:VLS_AVL_IMM 1 "general_operand"))]
1246 "TARGET_VECTOR"
1247 {
1248 if (riscv_vector::legitimize_move (operands[0], &operands[1]))
1249 DONE;
1250 })
1252 (define_insn_and_split "*mov<mode>"
1253 [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
1254 (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
1255 "TARGET_VECTOR
1256 && (register_operand (operands[0], <MODE>mode)
1257 || register_operand (operands[1], <MODE>mode))"
1258 "@
1259 #
1260 #
1261 vmv%m1r.v\t%0,%1"
1262 "&& reload_completed
1263 && (!register_operand (operands[0], <MODE>mode)
1264 || !register_operand (operands[1], <MODE>mode))"
1265 [(const_int 0)]
1266 {
1267 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1268 gcc_assert (ok_p);
1269 DONE;
1270 }
1271 [(set_attr "type" "vmov")]
1272 )
1274 (define_expand "mov<mode>"
1275 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1276 (match_operand:VLS_AVL_REG 1 "general_operand"))]
1277 "TARGET_VECTOR"
1278 {
1279 bool ok_p = riscv_vector::legitimize_move (operands[0], &operands[1]);
1280 gcc_assert (ok_p);
1281 DONE;
1282 })
1284 (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
1285 [(parallel
1286 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
1287 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
1288 (clobber (match_scratch:P 2))])]
1289 "TARGET_VECTOR && (lra_in_progress || reload_completed)"
1290 {})
1292 (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
1293 [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
1294 (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
1295 (clobber (match_scratch:P 2 "=&r,&r,X"))]
1296 "TARGET_VECTOR && (lra_in_progress || reload_completed)
1297 && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
1298 || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
1299 "#"
1300 "&& reload_completed"
1301 [(const_int 0)]
1302 {
1303 if (REG_P (operands[0]) && REG_P (operands[1]))
1304 emit_insn (gen_rtx_SET (operands[0], operands[1]));
1305 else
1306 {
1307 emit_move_insn (operands[2], gen_int_mode (GET_MODE_NUNITS (<VLS_AVL_REG:MODE>mode),
1308 Pmode));
1309 unsigned insn_flags
1310 = GET_MODE_CLASS (<VLS_AVL_REG:MODE>mode) == MODE_VECTOR_BOOL
1311 ? riscv_vector::UNARY_MASK_OP
1312 : riscv_vector::UNARY_OP;
1313 riscv_vector::emit_nonvlmax_insn (code_for_pred_mov (<VLS_AVL_REG:MODE>mode),
1314 insn_flags, operands, operands[2]);
1315 }
1316 DONE;
1317 }
1318 [(set_attr "type" "vmov")]
1319 )
1321 (define_insn "*mov<mode>_vls"
1322 [(set (match_operand:VLS 0 "register_operand" "=vr")
1323 (match_operand:VLS 1 "register_operand" " vr"))]
1324 "TARGET_VECTOR"
1325 "vmv%m1r.v\t%0,%1"
1326 [(set_attr "type" "vmov")
1327 (set_attr "mode" "<MODE>")])
1329 (define_insn "*mov<mode>_vls"
1330 [(set (match_operand:VLSB 0 "register_operand" "=vr")
1331 (match_operand:VLSB 1 "register_operand" " vr"))]
1332 "TARGET_VECTOR"
1333 "vmv1r.v\t%0,%1"
1334 [(set_attr "type" "vmov")
1335 (set_attr "mode" "<MODE>")])
1337 (define_expand "movmisalign<mode>"
1338 [(set (match_operand:VLS 0 "nonimmediate_operand")
1339 (match_operand:VLS 1 "general_operand"))]
1340 "TARGET_VECTOR"
1341 {
1342 /* To support misalign data movement, we should use
1343 minimum element alignment load/store. */
1344 unsigned int size = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode));
1345 poly_int64 nunits = GET_MODE_NUNITS (<MODE>mode) * size;
1346 machine_mode mode = riscv_vector::get_vector_mode (QImode, nunits).require ();
1347 operands[0] = gen_lowpart (mode, operands[0]);
1348 operands[1] = gen_lowpart (mode, operands[1]);
1349 if (MEM_P (operands[0]) && !register_operand (operands[1], mode))
1350 operands[1] = force_reg (mode, operands[1]);
1351 riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode), riscv_vector::UNARY_OP, operands);
1352 DONE;
1353 }
1354 )
1356 ;; According to RVV ISA:
1357 ;; If an element accessed by a vector memory instruction is not naturally aligned to the size of the element,
1358 ;; either the element is transferred successfully or an address misaligned exception is raised on that element.
1359 (define_expand "movmisalign<mode>"
1360 [(set (match_operand:V 0 "nonimmediate_operand")
1361 (match_operand:V 1 "general_operand"))]
1362 "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
1363 {
1364 emit_move_insn (operands[0], operands[1]);
1365 DONE;
1366 }
1367 )
1369 ;; -----------------------------------------------------------------
1370 ;; ---- Duplicate Operations
1371 ;; -----------------------------------------------------------------
1373 (define_expand "vec_duplicate<mode>"
1374 [(set (match_operand:V_VLS 0 "register_operand")
1375 (vec_duplicate:V_VLS
1376 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1377 "TARGET_VECTOR"
1378 {
1379 /* Early expand DImode broadcast in RV32 system to avoid RA reload
1380 generate (set (reg) (vec_duplicate:DI)). */
1381 if (maybe_gt (GET_MODE_SIZE (<VEL>mode), GET_MODE_SIZE (Pmode)))
1382 {
1383 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1384 riscv_vector::UNARY_OP, operands);
1385 DONE;
1386 }
1387 /* Otherwise, allow it fall into general vec_duplicate pattern
1388 which allow us to have vv->vx combine optimization in later pass. */
1389 })
1391 ;; According to GCC internal:
1392 ;; This pattern only handles duplicates of non-constant inputs.
1393 ;; Constant vectors go through the movm pattern instead.
1394 ;; So "direct_broadcast_operand" can only be mem or reg, no CONSTANT.
1395 (define_insn_and_split "*vec_duplicate<mode>"
1396 [(set (match_operand:V_VLS 0 "register_operand")
1397 (vec_duplicate:V_VLS
1398 (match_operand:<VEL> 1 "direct_broadcast_operand")))]
1399 "TARGET_VECTOR && can_create_pseudo_p ()"
1400 "#"
1401 "&& 1"
1402 [(const_int 0)]
1403 {
1404 riscv_vector::emit_vlmax_insn (code_for_pred_broadcast (<MODE>mode),
1405 riscv_vector::UNARY_OP, operands);
1406 DONE;
1407 }
1408 [(set_attr "type" "vector")]
1409 )
1411 ;; -----------------------------------------------------------------
1412 ;; ---- 6. Configuration-Setting Instructions
1413 ;; -----------------------------------------------------------------
1414 ;; Includes:
1415 ;; - 6.1 vsetvli/vsetivl/vsetvl instructions
1416 ;; -----------------------------------------------------------------
1418 ;; we dont't define vsetvli as unspec_volatile which has side effects.
1419 ;; This instruction can be scheduled by the instruction scheduler.
1420 ;; This means these instructions will be deleted when
1421 ;; there is no instructions using vl or vtype in the following.
1422 ;; rd | rs1 | AVL value | Effect on vl
1423 ;; - | !x0 | x[rs1] | Normal stripmining
1424 ;; !x0 | x0 | ~0 | Set vl to VLMAX
1425 ;; operands[0]: VL.
1426 ;; operands[1]: AVL.
1427 ;; operands[2]: SEW
1428 ;; operands[3]: LMUL
1429 ;; operands[4]: Tail policy 0 or 1 (undisturbed/agnostic)
1430 ;; operands[5]: Mask policy 0 or 1 (undisturbed/agnostic)
1432 ;; We define 2 types of "vsetvl*" instruction patterns:
1434 ;; - "@vsetvl<mode>" is a parallel format which has side effects.
1436 ;; - "@vsetvl<mode>_no_side_effects" has no side effects.
1438 ;; - "@vsetvl<mode>" is used by "vsetvl" intrinsics and "insert-vsetvl" PASS.
1440 ;; - "@vsetvl<mode>_no_side_effects" is used by GCC standard patterns.
1442 ;; - "@vsetvl<mode>" includes VL/VTYPE global registers status (define set)
1443 ;; and each RVV instruction includes VL/VTYPE global registers status (use)
1444 ;; so that we can guarantee each RVV instruction can execute with correct
1445 ;; VL/VTYPE global registers status after "insert-vsetvl" PASS.
1447 ;; - "@vsetvl<mode>_no_side_effects" has no side effects and excludes VL/VTYPE
1448 ;; global registers status (define set). It's only used by GCC standard pattern
1449 ;; expansion. For example: "mov<mode>" pattern for fractional vector modes which
1450 ;; need to set VL/VTYPE. Then we could manually call this pattern to gain benefits
1451 ;; from the optimization of each GCC internal PASS.
1453 ;; 1. void foo (float *in, float *out)
1454 ;; {
1455 ;; vfloat32mf2_t v = *(vfloat32mf2_t*)in;
1456 ;; *(vfloat32mf2_t*)out = v;
1457 ;; }
1458 ;; We could eliminate the second "vsetvl" by calling "@vsetvl<mode>_no_side_effects".
1459 ;;
1460 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1461 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; vsetvli a4,zero,e32,mf2,ta,ma
1462 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1463 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; --
1464 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1465 ;; ret ;; ret
1467 ;; 2. void foo (int8_t *in, int8_t *out, int M)
1468 ;; {
1469 ;; for (int i = 0; i < M; i++){
1470 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1471 ;; *(vint8mf2_t*)(out + i) = v;
1472 ;; }
1473 ;; }
1474 ;;
1475 ;; Hoist "vsetvl" instruction in LICM:
1476 ;; "@vsetvl<mode>": ;; "@vsetvl<mode>_no_side_effects":
1477 ;; - ;; vsetvli a4,zero,e32,mf2,ta,ma
1478 ;; LOOP: ;; LOOP:
1479 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1480 ;; vle32.v v24,(a0) ;; vle32.v v24,(a0)
1481 ;; vsetvli a4,zero,e32,mf2,ta,ma ;; -
1482 ;; vse32.v v24,(a1) ;; vse32.v v24,(a1)
1484 ;; However, it may produce wrong codegen if we exclude VL/VTYPE in "vsevl<mode>".
1485 ;; 3. void foo (int8_t *in, int8_t *out, int32_t *in2, int32_t *out2, int M)
1486 ;; {
1487 ;; for (int i = 0; i < M; i++){
1488 ;; vint8mf2_t v = *(vint8mf2_t*)(in + i);
1489 ;; vint32mf2_t v2 = *(vint32mf2_t*)(in + i + i);
1490 ;; *(vint8mf2_t*)(out + i) = v;
1491 ;; *(vint32mf2_t*)(out + i + i) = v2;
1492 ;; }
1493 ;; }
1494 ;;
1495 ;; vsetvli a6,zero,e8,mf2,ta,ma
1496 ;; vsetvli a2,zero,e32,mf2,ta,ma
1497 ;; LOOP:
1498 ;; vle8.v v25,(a0)
1499 ;; vle32.v v24,(a5)
1500 ;; addi a0,a0,1
1501 ;; vse8.v v25,(a1)
1502 ;; vse32.v v24,(a3)
1503 ;;
1504 ;; Both vle8.v and vle32.v are using the wrong VL/VTYPE status.
1505 ;; We leave it to "insert-vsetvl" PASS to correct this situation.
1507 ;; The "insert-vsetvl" PASS mechanism:
1508 ;; 1. Before "insert-vsetvl" PASS, only RVV instructions are generated
1509 ;; by GCC standard pattern expansion has the corresponding "vsetvl".
1510 ;; We exploit each GCC internal optimization pass to optimize the "vsetvl".
1511 ;; 2. Correct the VL/VTYPE status for each GCC standard pattern RVV instructions.
1512 ;; Insert vsetvl for each RVV instructions that has no VL/VTYPE status if necessary.
1513 ;; For example: RVV intrinsics.
1514 ;; 3. Optimize "vsetvl" instructions.
1516 (define_insn "@vsetvl<mode>"
1517 [(set (match_operand:P 0 "register_operand" "=r")
1518 (unspec:P [(match_operand:P 1 "csr_operand" "rK")
1519 (match_operand 2 "const_int_operand" "i")
1520 (match_operand 3 "const_int_operand" "i")
1521 (match_operand 4 "const_int_operand" "i")
1522 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))
1523 (set (reg:SI VL_REGNUM)
1524 (unspec:SI [(match_dup 1)
1525 (match_dup 2)
1526 (match_dup 3)] UNSPEC_VSETVL))
1527 (set (reg:SI VTYPE_REGNUM)
1528 (unspec:SI [(match_dup 2)
1529 (match_dup 3)
1530 (match_dup 4)
1531 (match_dup 5)] UNSPEC_VSETVL))]
1532 "TARGET_VECTOR"
1533 "vset%i1vli\t%0,%1,e%2,%m3,t%p4,m%p5"
1534 [(set_attr "type" "vsetvl")
1535 (set_attr "mode" "<MODE>")
1536 (set (attr "sew") (symbol_ref "INTVAL (operands[2])"))
1537 (set (attr "vlmul") (symbol_ref "INTVAL (operands[3])"))
1538 (set (attr "ta") (symbol_ref "INTVAL (operands[4])"))
1539 (set (attr "ma") (symbol_ref "INTVAL (operands[5])"))])
1541 ;; vsetvl zero,zero,vtype instruction.
1542 ;; This pattern has no side effects and does not set X0 register.
1543 (define_insn "vsetvl_vtype_change_only"
1544 [(set (reg:SI VTYPE_REGNUM)
1545 (unspec:SI
1546 [(match_operand 0 "const_int_operand" "i")
1547 (match_operand 1 "const_int_operand" "i")
1548 (match_operand 2 "const_int_operand" "i")
1549 (match_operand 3 "const_int_operand" "i")] UNSPEC_VSETVL))]
1550 "TARGET_VECTOR"
1551 "vsetvli\tzero,zero,e%0,%m1,t%p2,m%p3"
1552 [(set_attr "type" "vsetvl")
1553 (set_attr "mode" "SI")
1554 (set (attr "sew") (symbol_ref "INTVAL (operands[0])"))
1555 (set (attr "vlmul") (symbol_ref "INTVAL (operands[1])"))
1556 (set (attr "ta") (symbol_ref "INTVAL (operands[2])"))
1557 (set (attr "ma") (symbol_ref "INTVAL (operands[3])"))])
1559 ;; vsetvl zero,rs1,vtype instruction.
1560 ;; The reason we need this pattern since we should avoid setting X0 register
1561 ;; in vsetvl instruction pattern.
1562 (define_insn "@vsetvl_discard_result<mode>"
1563 [(set (reg:SI VL_REGNUM)
1564 (unspec:SI [(match_operand:P 0 "csr_operand" "rK")
1565 (match_operand 1 "const_int_operand" "i")
1566 (match_operand 2 "const_int_operand" "i")] UNSPEC_VSETVL))
1567 (set (reg:SI VTYPE_REGNUM)
1568 (unspec:SI [(match_dup 1)
1569 (match_dup 2)
1570 (match_operand 3 "const_int_operand" "i")
1571 (match_operand 4 "const_int_operand" "i")] UNSPEC_VSETVL))]
1572 "TARGET_VECTOR"
1573 "vset%i0vli\tzero,%0,e%1,%m2,t%p3,m%p4"
1574 [(set_attr "type" "vsetvl")
1575 (set_attr "mode" "<MODE>")
1576 (set (attr "sew") (symbol_ref "INTVAL (operands[1])"))
1577 (set (attr "vlmul") (symbol_ref "INTVAL (operands[2])"))
1578 (set (attr "ta") (symbol_ref "INTVAL (operands[3])"))
1579 (set (attr "ma") (symbol_ref "INTVAL (operands[4])"))])
1581 ;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects.
1582 ;; Since we have many optmization passes from "expand" to "reload_completed",
1583 ;; such pattern can allow us gain benefits of these optimizations.
1584 (define_insn_and_split "@vsetvl<mode>_no_side_effects"
1585 [(set (match_operand:P 0 "register_operand" "=r")
1586 (unspec:P [(match_operand:P 1 "csr_operand" "rK")
1587 (match_operand 2 "const_int_operand" "i")
1588 (match_operand 3 "const_int_operand" "i")
1589 (match_operand 4 "const_int_operand" "i")
1590 (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))]
1591 "TARGET_VECTOR"
1592 "#"
1593 "&& epilogue_completed"
1594 [(parallel
1595 [(set (match_dup 0)
1596 (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3)
1597 (match_dup 4) (match_dup 5)] UNSPEC_VSETVL))
1598 (set (reg:SI VL_REGNUM)
1599 (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL))
1600 (set (reg:SI VTYPE_REGNUM)
1601 (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4)
1602 (match_dup 5)] UNSPEC_VSETVL))])]
1603 ""
1604 [(set_attr "type" "vsetvl")
1605 (set_attr "mode" "SI")])
1607 ;; This pattern use to combine bellow two insns and then further remove
1608 ;; unnecessary sign_extend operations:
1609 ;; (set (reg:DI 134 [ _1 ])
1610 ;; (unspec:DI [
1611 ;; (const_int 19 [0x13])
1612 ;; (const_int 8 [0x8])
1613 ;; (const_int 5 [0x5])
1614 ;; (const_int 2 [0x2]) repeated x2
1615 ;; ] UNSPEC_VSETVL))
1616 ;; (set (reg/v:DI 135 [ <retval> ])
1617 ;; (sign_extend:DI (subreg:SI (reg:DI 134 [ _1 ]) 0)))
1618 ;;
1619 ;; The reason we can remove signe_extend is because currently the vl value
1620 ;; returned by the vsetvl instruction ranges from 0 to 65536 (uint16_t), and
1621 ;; bits 17 to 63 (including 31) are always 0, so there is no change after
1622 ;; sign_extend. Note that for HI and QI modes we cannot do this.
1623 ;; Of course, if the range of instructions returned by vsetvl later expands
1624 ;; to 32bits, then this combine pattern needs to be removed. But that could be
1625 ;; a long time from now.
1626 (define_insn_and_split "*vsetvldi_no_side_effects_si_extend"
1627 [(set (match_operand:DI 0 "register_operand")
1628 (sign_extend:DI
1629 (subreg:SI
1630 (unspec:DI [(match_operand:P 1 "csr_operand")
1631 (match_operand 2 "const_int_operand")
1632 (match_operand 3 "const_int_operand")
1633 (match_operand 4 "const_int_operand")
1634 (match_operand 5 "const_int_operand")] UNSPEC_VSETVL) 0)))]
1635 "TARGET_VECTOR && TARGET_64BIT"
1636 "#"
1637 "&& 1"
1638 [(set (match_dup 0)
1639 (unspec:DI [(match_dup 1)
1640 (match_dup 2)
1641 (match_dup 3)
1642 (match_dup 4)
1643 (match_dup 5)] UNSPEC_VSETVL))]
1644 ""
1645 [(set_attr "type" "vsetvl")
1646 (set_attr "mode" "SI")])
1648 ;; RVV machine description matching format
1649 ;; (define_insn ""
1650 ;; [(set (match_operand:MODE 0)
1651 ;; (if_then_else:MODE
1652 ;; (unspec:<MODE:VM>
1653 ;; [(match_operand:<VM> 1 "vector_mask_operand")
1654 ;; (match_operand N + 4 "vector_length_operand")
1655 ;; (match_operand N + 5 "const_int_operand")
1656 ;; (match_operand N + 6 "const_int_operand")
1657 ;; (reg:SI VL_REGNUM)
1658 ;; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1659 ;; (instruction operation:MODE
1660 ;; (match_operand 3
1661 ;; (match_operand 4
1662 ;; (match_operand 5
1663 ;; ................
1664 ;; (match_operand N + 3)
1665 ;; (match_operand:MODE 2 "vector_reg_or_const0_operand")))]
1666 ;;
1667 ;; (unspec:[........] UNSPEC_VPREDICATE) is a predicate wrapper.
1668 ;; Include mask predicate && length predicate && vector policy.
1670 ;; -------------------------------------------------------------------------------
1671 ;; ---- Predicated Mov
1672 ;; -------------------------------------------------------------------------------
1673 ;; Includes:
1674 ;; - 7.4. Vector Unit-Stride Instructions
1675 ;; - 11.15 Vector Integer Merge Instructions
1676 ;; - 11.16 Vector Integer Move Instructions
1677 ;; - 13.16 Vector Floating-Point Move Instruction
1678 ;; - 15.1 Vector Mask-Register Logical Instructions
1679 ;; -------------------------------------------------------------------------------
1681 ;; vle.v/vse.v/vmv.v.v.
1682 ;; For vle.v/vmv.v.v, we may need merge and mask operand.
1683 ;; For vse.v, we don't need merge operand, so it should always match "vu".
1684 ;; constraint alternative 0 ~ 1 match vle.v.
1685 ;; constraint alternative 2 match vse.v.
1686 ;; constraint alternative 3 match vmv.v.v.
1688 ;; If operand 3 is a const_vector, then it is left to pred_braordcast patterns.
1689 (define_expand "@pred_mov<mode>"
1690 [(set (match_operand:V_VLS 0 "nonimmediate_operand")
1691 (if_then_else:V_VLS
1692 (unspec:<VM>
1693 [(match_operand:<VM> 1 "vector_mask_operand")
1694 (match_operand 4 "vector_length_operand")
1695 (match_operand 5 "const_int_operand")
1696 (match_operand 6 "const_int_operand")
1697 (match_operand 7 "const_int_operand")
1698 (reg:SI VL_REGNUM)
1699 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1700 (match_operand:V_VLS 3 "vector_move_operand")
1701 (match_operand:V_VLS 2 "vector_merge_operand")))]
1702 "TARGET_VECTOR"
1703 {})
1705 ;; vle.v/vse.v,vmv.v.v
1706 (define_insn_and_split "*pred_mov<mode>"
1707 [(set (match_operand:V_VLS 0 "nonimmediate_operand" "=vr, vr, vd, m, vr, vr")
1708 (if_then_else:V_VLS
1709 (unspec:<VM>
1710 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, Wc1")
1711 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
1712 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
1713 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
1714 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
1715 (reg:SI VL_REGNUM)
1716 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1717 (match_operand:V_VLS 3 "reg_or_mem_operand" " m, m, m, vr, vr, vr")
1718 (match_operand:V_VLS 2 "vector_merge_operand" " 0, vu, vu, vu, vu, 0")))]
1719 "(TARGET_VECTOR
1720 && (register_operand (operands[0], <MODE>mode)
1721 || register_operand (operands[3], <MODE>mode)))"
1722 "@
1723 vle<sew>.v\t%0,%3%p1
1724 vle<sew>.v\t%0,%3
1725 vle<sew>.v\t%0,%3,%1.t
1726 vse<sew>.v\t%3,%0%p1
1727 vmv.v.v\t%0,%3
1728 vmv.v.v\t%0,%3"
1729 "&& register_operand (operands[0], <MODE>mode)
1730 && register_operand (operands[3], <MODE>mode)
1731 && satisfies_constraint_vu (operands[2])
1732 && INTVAL (operands[7]) == riscv_vector::VLMAX"
1733 [(set (match_dup 0) (match_dup 3))]
1734 ""
1735 [(set_attr "type" "vlde,vlde,vlde,vste,vimov,vimov")
1736 (set_attr "mode" "<MODE>")])
1738 ;; Dedicated pattern for vse.v instruction since we can't reuse pred_mov pattern to include
1739 ;; memory operand as input which will produce inferior codegen.
1740 (define_insn "@pred_store<mode>"
1741 [(set (match_operand:V 0 "memory_operand" "+m")
1742 (if_then_else:V
1743 (unspec:<VM>
1744 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
1745 (match_operand 3 "vector_length_operand" " rK")
1746 (match_operand 4 "const_int_operand" " i")
1747 (reg:SI VL_REGNUM)
1748 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1749 (match_operand:V 2 "register_operand" " vr")
1750 (match_dup 0)))]
1751 "TARGET_VECTOR"
1752 "vse<sew>.v\t%2,%0%p1"
1753 [(set_attr "type" "vste")
1754 (set_attr "mode" "<MODE>")
1755 (set (attr "avl_type_idx") (const_int 4))
1756 (set_attr "vl_op_idx" "3")])
1758 ;; vlm.v/vsm.v/vmclr.m/vmset.m.
1759 ;; constraint alternative 0 match vlm.v.
1760 ;; constraint alternative 1 match vsm.v.
1761 ;; constraint alternative 3 match vmclr.m.
1762 ;; constraint alternative 4 match vmset.m.
1763 (define_insn_and_split "@pred_mov<mode>"
1764 [(set (match_operand:VB_VLS 0 "nonimmediate_operand" "=vr, m, vr, vr, vr")
1765 (if_then_else:VB_VLS
1766 (unspec:VB_VLS
1767 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1")
1768 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK")
1769 (match_operand 5 "const_int_operand" " i, i, i, i, i")
1770 (reg:SI VL_REGNUM)
1771 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1772 (match_operand:VB_VLS 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")
1773 (match_operand:VB_VLS 2 "vector_undef_operand" " vu, vu, vu, vu, vu")))]
1774 "TARGET_VECTOR"
1775 "@
1776 vlm.v\t%0,%3
1777 vsm.v\t%3,%0
1778 vmmv.m\t%0,%3
1779 vmclr.m\t%0
1780 vmset.m\t%0"
1781 "&& register_operand (operands[0], <MODE>mode)
1782 && register_operand (operands[3], <MODE>mode)
1783 && INTVAL (operands[5]) == riscv_vector::VLMAX"
1784 [(set (match_dup 0) (match_dup 3))]
1785 ""
1786 [(set_attr "type" "vldm,vstm,vmalu,vmalu,vmalu")
1787 (set_attr "mode" "<MODE>")])
1789 ;; Dedicated pattern for vsm.v instruction since we can't reuse pred_mov pattern to include
1790 ;; memory operand as input which will produce inferior codegen.
1791 (define_insn "@pred_store<mode>"
1792 [(set (match_operand:VB 0 "memory_operand" "+m")
1793 (if_then_else:VB
1794 (unspec:VB
1795 [(match_operand:VB 1 "vector_all_trues_mask_operand" "Wc1")
1796 (match_operand 3 "vector_length_operand" " rK")
1797 (match_operand 4 "const_int_operand" " i")
1798 (reg:SI VL_REGNUM)
1799 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1800 (match_operand:VB 2 "register_operand" " vr")
1801 (match_dup 0)))]
1802 "TARGET_VECTOR"
1803 "vsm.v\t%2,%0"
1804 [(set_attr "type" "vstm")
1805 (set_attr "mode" "<MODE>")
1806 (set (attr "avl_type_idx") (const_int 4))
1807 (set_attr "vl_op_idx" "3")])
1809 (define_insn "@pred_merge<mode>"
1810 [(set (match_operand:V_VLS 0 "register_operand" "=vd,vd,vd,vd")
1811 (if_then_else:V_VLS
1812 (unspec:<VM>
1813 [(match_operand 5 "vector_length_operand" " rK,rK,rK,rK")
1814 (match_operand 6 "const_int_operand" " i, i, i, i")
1815 (match_operand 7 "const_int_operand" " i, i, i, i")
1816 (reg:SI VL_REGNUM)
1817 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1818 (vec_merge:V_VLS
1819 (match_operand:V_VLS 3 "vector_arith_operand" " vr,vr,vi,vi")
1820 (match_operand:V_VLS 2 "register_operand" " vr,vr,vr,vr")
1821 (match_operand:<VM> 4 "register_operand" " vm,vm,vm,vm"))
1822 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0,vu, 0")))]
1823 "TARGET_VECTOR"
1824 "vmerge.v%o3m\t%0,%2,%v3,%4"
1825 [(set_attr "type" "vimerge")
1826 (set_attr "mode" "<MODE>")])
1828 (define_insn "@pred_merge<mode>_scalar"
1829 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd")
1830 (if_then_else:V_VLSI_QHS
1831 (unspec:<VM>
1832 [(match_operand 5 "vector_length_operand" " rK,rK")
1833 (match_operand 6 "const_int_operand" " i, i")
1834 (match_operand 7 "const_int_operand" " i, i")
1835 (reg:SI VL_REGNUM)
1836 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1837 (vec_merge:V_VLSI_QHS
1838 (vec_duplicate:V_VLSI_QHS
1839 (match_operand:<VEL> 3 "register_operand" " r, r"))
1840 (match_operand:V_VLSI_QHS 2 "register_operand" " vr,vr")
1841 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1842 (match_operand:V_VLSI_QHS 1 "vector_merge_operand" " vu, 0")))]
1843 "TARGET_VECTOR"
1844 "vmerge.vxm\t%0,%2,%3,%4"
1845 [(set_attr "type" "vimerge")
1846 (set_attr "mode" "<MODE>")])
1848 (define_expand "@pred_merge<mode>_scalar"
1849 [(set (match_operand:V_VLSI_D 0 "register_operand")
1850 (if_then_else:V_VLSI_D
1851 (unspec:<VM>
1852 [(match_operand 5 "vector_length_operand")
1853 (match_operand 6 "const_int_operand")
1854 (match_operand 7 "const_int_operand")
1855 (reg:SI VL_REGNUM)
1856 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1857 (vec_merge:V_VLSI_D
1858 (vec_duplicate:V_VLSI_D
1859 (match_operand:<VEL> 3 "reg_or_int_operand"))
1860 (match_operand:V_VLSI_D 2 "register_operand")
1861 (match_operand:<VM> 4 "register_operand"))
1862 (match_operand:V_VLSI_D 1 "vector_merge_operand")))]
1863 "TARGET_VECTOR"
1864 {
1865 if (riscv_vector::sew64_scalar_helper (
1866 operands,
1867 /* scalar op */&operands[3],
1868 /* vl */operands[5],
1869 <MODE>mode,
1870 riscv_vector::simm5_p (operands[3]),
1871 [] (rtx *operands, rtx boardcast_scalar) {
1872 emit_insn (gen_pred_merge<mode> (operands[0], operands[1],
1873 operands[2], boardcast_scalar, operands[4], operands[5],
1874 operands[6], operands[7]));
1875 },
1876 (riscv_vector::avl_type) INTVAL (operands[7])))
1877 DONE;
1878 })
1880 (define_insn "*pred_merge<mode>_scalar"
1881 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1882 (if_then_else:V_VLSI_D
1883 (unspec:<VM>
1884 [(match_operand 5 "vector_length_operand" " rK,rK")
1885 (match_operand 6 "const_int_operand" " i, i")
1886 (match_operand 7 "const_int_operand" " i, i")
1887 (reg:SI VL_REGNUM)
1888 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1889 (vec_merge:V_VLSI_D
1890 (vec_duplicate:V_VLSI_D
1891 (match_operand:<VEL> 3 "register_operand" " r, r"))
1892 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1893 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1894 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1895 "TARGET_VECTOR"
1896 "vmerge.vxm\t%0,%2,%3,%4"
1897 [(set_attr "type" "vimerge")
1898 (set_attr "mode" "<MODE>")])
1900 (define_insn "*pred_merge<mode>_extended_scalar"
1901 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd")
1902 (if_then_else:V_VLSI_D
1903 (unspec:<VM>
1904 [(match_operand 5 "vector_length_operand" " rK,rK")
1905 (match_operand 6 "const_int_operand" " i, i")
1906 (match_operand 7 "const_int_operand" " i, i")
1907 (reg:SI VL_REGNUM)
1908 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1909 (vec_merge:V_VLSI_D
1910 (vec_duplicate:V_VLSI_D
1911 (sign_extend:<VEL>
1912 (match_operand:<VSUBEL> 3 "register_operand" " r, r")))
1913 (match_operand:V_VLSI_D 2 "register_operand" " vr,vr")
1914 (match_operand:<VM> 4 "register_operand" " vm,vm"))
1915 (match_operand:V_VLSI_D 1 "vector_merge_operand" " vu, 0")))]
1916 "TARGET_VECTOR"
1917 "vmerge.vxm\t%0,%2,%3,%4"
1918 [(set_attr "type" "vimerge")
1919 (set_attr "mode" "<MODE>")])
1921 ;; -------------------------------------------------------------------------------
1922 ;; ---- Predicated Broadcast
1923 ;; -------------------------------------------------------------------------------
1924 ;; Includes:
1925 ;; - 7.5. Vector Strided Instructions (zero stride)
1926 ;; - 11.16 Vector Integer Move Instructions (vmv.v.x)
1927 ;; - 13.16 Vector Floating-Point Move Instruction (vfmv.v.f)
1928 ;; - 16.1 Integer Scalar Move Instructions (vmv.s.x)
1929 ;; - 16.2 Floating-Point Scalar Move Instructions (vfmv.s.f)
1930 ;; -------------------------------------------------------------------------------
1932 ;; According to RVV ISA, vector-scalar instruction doesn't support
1933 ;; operand fetched from 2 consecutive registers, so we should use
1934 ;; vlse.v which is a memory access to broadcast a DImode scalar into a vector.
1935 ;;
1936 ;; Since the optimization flow in GCC is as follows:
1937 ;; expand --> LICM (Loop invariant) --> split.
1938 ;; To use LICM optimization, we postpone generation of vlse.v to split stage since
1939 ;; a memory access instruction can not be optimized by LICM (Loop invariant).
1940 (define_expand "@pred_broadcast<mode>"
1941 [(set (match_operand:V_VLS 0 "register_operand")
1942 (if_then_else:V_VLS
1943 (unspec:<VM>
1944 [(match_operand:<VM> 1 "vector_broadcast_mask_operand")
1945 (match_operand 4 "vector_length_operand")
1946 (match_operand 5 "const_int_operand")
1947 (match_operand 6 "const_int_operand")
1948 (match_operand 7 "const_int_operand")
1949 (reg:SI VL_REGNUM)
1950 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
1951 (vec_duplicate:V_VLS
1952 (match_operand:<VEL> 3 "direct_broadcast_operand"))
1953 (match_operand:V_VLS 2 "vector_merge_operand")))]
1954 "TARGET_VECTOR"
1955 {
1956 /* Handle vmv.s.x instruction (Wb1 mask) which has memory scalar. */
1957 if (satisfies_constraint_Wdm (operands[3]))
1958 {
1959 if (satisfies_constraint_Wb1 (operands[1]))
1960 {
1961 /* Case 1: vmv.s.x (TA, x == memory) ==> vlse.v (TA) */
1962 if (satisfies_constraint_vu (operands[2]))
1963 operands[1] = CONSTM1_RTX (<VM>mode);
1964 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode))
1965 {
1966 /* Case 2: vmv.s.x (TU, x == memory) ==>
1967 vl = 0 or 1; + vlse.v (TU) in RV32 system */
1968 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
1969 operands[1] = CONSTM1_RTX (<VM>mode);
1970 }
1971 else
1972 /* Case 3: load x (memory) to register. */
1973 operands[3] = force_reg (<VEL>mode, operands[3]);
1974 }
1975 }
1976 else if (GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)
1977 && (immediate_operand (operands[3], Pmode)
1978 || (CONST_POLY_INT_P (operands[3])
1979 && known_ge (rtx_to_poly_int64 (operands[3]), 0U)
1980 && known_le (rtx_to_poly_int64 (operands[3]), GET_MODE_SIZE (<MODE>mode)))))
1981 {
1982 rtx tmp = gen_reg_rtx (Pmode);
1983 poly_int64 value = rtx_to_poly_int64 (operands[3]);
1984 emit_move_insn (tmp, gen_int_mode (value, Pmode));
1985 operands[3] = gen_rtx_SIGN_EXTEND (<VEL>mode, tmp);
1986 }
1987 else
1988 operands[3] = force_reg (<VEL>mode, operands[3]);
1989 })
1991 (define_insn_and_split "*pred_broadcast<mode>"
1992 [(set (match_operand:V_VLSI 0 "register_operand" "=vr, vr, vd, vd, vr, vr, vr, vr")
1993 (if_then_else:V_VLSI
1994 (unspec:<VM>
1995 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
1996 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
1997 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
1998 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
1999 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2000 (reg:SI VL_REGNUM)
2001 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2002 (vec_duplicate:V_VLSI
2003 (match_operand:<VEL> 3 "direct_broadcast_operand" " r, r,Wdm,Wdm,Wdm,Wdm, r, r"))
2004 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2005 "TARGET_VECTOR"
2006 "@
2007 vmv.v.x\t%0,%3
2008 vmv.v.x\t%0,%3
2009 vlse<sew>.v\t%0,%3,zero,%1.t
2010 vlse<sew>.v\t%0,%3,zero,%1.t
2011 vlse<sew>.v\t%0,%3,zero
2012 vlse<sew>.v\t%0,%3,zero
2013 vmv.s.x\t%0,%3
2014 vmv.s.x\t%0,%3"
2015 "(register_operand (operands[3], <VEL>mode)
2016 || CONST_POLY_INT_P (operands[3]))
2017 && GET_MODE_BITSIZE (<VEL>mode) > GET_MODE_BITSIZE (Pmode)"
2018 [(set (match_dup 0)
2019 (if_then_else:V_VLSI (unspec:<VM> [(match_dup 1) (match_dup 4)
2020 (match_dup 5) (match_dup 6) (match_dup 7)
2021 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2022 (vec_duplicate:V_VLSI (match_dup 3))
2023 (match_dup 2)))]
2024 {
2025 gcc_assert (can_create_pseudo_p ());
2026 if (CONST_POLY_INT_P (operands[3]))
2027 {
2028 rtx tmp = gen_reg_rtx (<VEL>mode);
2029 emit_move_insn (tmp, operands[3]);
2030 operands[3] = tmp;
2031 }
2032 rtx m = assign_stack_local (<VEL>mode, GET_MODE_SIZE (<VEL>mode),
2033 GET_MODE_ALIGNMENT (<VEL>mode));
2034 m = validize_mem (m);
2035 emit_move_insn (m, operands[3]);
2036 m = gen_rtx_MEM (<VEL>mode, force_reg (Pmode, XEXP (m, 0)));
2037 operands[3] = m;
2039 /* For SEW = 64 in RV32 system, we expand vmv.s.x:
2040 andi a2,a2,1
2041 vsetvl zero,a2,e64
2042 vlse64.v */
2043 if (satisfies_constraint_Wb1 (operands[1]))
2044 {
2045 operands[4] = riscv_vector::gen_avl_for_scalar_move (operands[4]);
2046 operands[1] = CONSTM1_RTX (<VM>mode);
2047 }
2048 }
2049 [(set_attr "type" "vimov,vimov,vlds,vlds,vlds,vlds,vimovxv,vimovxv")
2050 (set_attr "mode" "<MODE>")])
2052 (define_insn "*pred_broadcast<mode>"
2053 [(set (match_operand:V_VLSF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, vr, vr")
2054 (if_then_else:V_VLSF_ZVFHMIN
2055 (unspec:<VM>
2056 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm, vm,Wc1,Wc1,Wb1,Wb1")
2057 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
2058 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
2059 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2060 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2061 (reg:SI VL_REGNUM)
2062 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2063 (vec_duplicate:V_VLSF_ZVFHMIN
2064 (match_operand:<VEL> 3 "direct_broadcast_operand" " f, f,Wdm,Wdm,Wdm,Wdm, f, f"))
2065 (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand" "vu, 0, vu, 0, vu, 0, vu, 0")))]
2066 "TARGET_VECTOR"
2067 "@
2068 vfmv.v.f\t%0,%3
2069 vfmv.v.f\t%0,%3
2070 vlse<sew>.v\t%0,%3,zero,%1.t
2071 vlse<sew>.v\t%0,%3,zero,%1.t
2072 vlse<sew>.v\t%0,%3,zero
2073 vlse<sew>.v\t%0,%3,zero
2074 vfmv.s.f\t%0,%3
2075 vfmv.s.f\t%0,%3"
2076 [(set_attr "type" "vfmov,vfmov,vlds,vlds,vlds,vlds,vfmovfv,vfmovfv")
2077 (set_attr "mode" "<MODE>")])
2079 (define_insn "*pred_broadcast<mode>_extended_scalar"
2080 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vr, vr, vr, vr")
2081 (if_then_else:V_VLSI_D
2082 (unspec:<VM>
2083 [(match_operand:<VM> 1 "vector_broadcast_mask_operand" "Wc1,Wc1,Wb1,Wb1")
2084 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
2085 (match_operand 5 "const_int_operand" " i, i, i, i")
2086 (match_operand 6 "const_int_operand" " i, i, i, i")
2087 (match_operand 7 "const_int_operand" " i, i, i, i")
2088 (reg:SI VL_REGNUM)
2089 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2090 (vec_duplicate:V_VLSI_D
2091 (sign_extend:<VEL>
2092 (match_operand:<VSUBEL> 3 "register_operand" " r, r, r, r")))
2093 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2094 "TARGET_VECTOR"
2095 "@
2096 vmv.v.x\t%0,%3
2097 vmv.v.x\t%0,%3
2098 vmv.s.x\t%0,%3
2099 vmv.s.x\t%0,%3"
2100 [(set_attr "type" "vimov,vimov,vimovxv,vimovxv")
2101 (set_attr "mode" "<MODE>")])
2103 (define_insn "*pred_broadcast<mode>_zero"
2104 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2105 (if_then_else:V_VLS
2106 (unspec:<VM>
2107 [(match_operand:<VM> 1 "vector_least_significant_set_mask_operand" "Wb1, Wb1")
2108 (match_operand 4 "vector_length_operand" " rK, rK")
2109 (match_operand 5 "const_int_operand" " i, i")
2110 (match_operand 6 "const_int_operand" " i, i")
2111 (match_operand 7 "const_int_operand" " i, i")
2112 (reg:SI VL_REGNUM)
2113 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2114 (match_operand:V_VLS 3 "vector_const_0_operand" "Wc0, Wc0")
2115 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2116 "TARGET_VECTOR"
2117 "vmv.s.x\t%0,zero"
2118 [(set_attr "type" "vimovxv,vimovxv")
2119 (set_attr "mode" "<MODE>")])
2121 ;; Because (vec_duplicate imm) will be converted to (const_vector imm),
2122 ;; This pattern is used to handle this case.
2123 (define_insn "*pred_broadcast<mode>_imm"
2124 [(set (match_operand:V_VLS 0 "register_operand" "=vr, vr")
2125 (if_then_else:V_VLS
2126 (unspec:<VM>
2127 [(match_operand:<VM> 1 "vector_all_trues_mask_operand" " Wc1, Wc1")
2128 (match_operand 4 "vector_length_operand" " rK, rK")
2129 (match_operand 5 "const_int_operand" " i, i")
2130 (match_operand 6 "const_int_operand" " i, i")
2131 (match_operand 7 "const_int_operand" " i, i")
2132 (reg:SI VL_REGNUM)
2133 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2134 (match_operand:V_VLS 3 "vector_const_int_or_double_0_operand" "viWc0, viWc0")
2135 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
2136 "TARGET_VECTOR"
2137 "vmv.v.i\t%0,%v3"
2138 [(set_attr "type" "vimov,vimov")
2139 (set_attr "mode" "<MODE>")])
2141 ;; -------------------------------------------------------------------------------
2142 ;; ---- Predicated Strided loads/stores
2143 ;; -------------------------------------------------------------------------------
2144 ;; Includes:
2145 ;; - 7.5. Vector Strided Instructions
2146 ;; -------------------------------------------------------------------------------
2148 (define_insn "@pred_strided_load<mode>"
2149 [(set (match_operand:V 0 "register_operand" "=vr, vr, vd, vr, vr, vd")
2150 (if_then_else:V
2151 (unspec:<VM>
2152 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm, vmWc1, Wc1, vm")
2153 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2154 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2155 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2156 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2157 (reg:SI VL_REGNUM)
2158 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2159 (unspec:V
2160 [(match_operand:V 3 "memory_operand" " m, m, m, m, m, m")
2161 (match_operand 4 "<V:stride_predicate>" "<V:stride_load_constraint>")] UNSPEC_STRIDED)
2162 (match_operand:V 2 "vector_merge_operand" " 0, vu, vu, 0, vu, vu")))]
2163 "TARGET_VECTOR"
2164 "@
2165 vlse<sew>.v\t%0,%3,%z4%p1
2166 vlse<sew>.v\t%0,%3,%z4
2167 vlse<sew>.v\t%0,%3,%z4,%1.t
2168 vle<sew>.v\t%0,%3%p1
2169 vle<sew>.v\t%0,%3
2170 vle<sew>.v\t%0,%3,%1.t"
2171 [(set_attr "type" "vlds")
2172 (set_attr "mode" "<MODE>")])
2174 (define_insn "@pred_strided_store<mode>"
2175 [(set (match_operand:V 0 "memory_operand" "+m, m")
2176 (if_then_else:V
2177 (unspec:<VM>
2178 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, vmWc1")
2179 (match_operand 4 "vector_length_operand" " rK, rK")
2180 (match_operand 5 "const_int_operand" " i, i")
2181 (reg:SI VL_REGNUM)
2182 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2183 (unspec:V
2184 [(match_operand 2 "<V:stride_predicate>" "<V:stride_store_constraint>")
2185 (match_operand:V 3 "register_operand" " vr, vr")] UNSPEC_STRIDED)
2186 (match_dup 0)))]
2187 "TARGET_VECTOR"
2188 "@
2189 vsse<sew>.v\t%3,%0,%z2%p1
2190 vse<sew>.v\t%3,%0%p1"
2191 [(set_attr "type" "vsts")
2192 (set_attr "mode" "<MODE>")
2193 (set (attr "avl_type_idx") (const_int 5))])
2195 ;; -------------------------------------------------------------------------------
2196 ;; ---- Predicated indexed loads/stores
2197 ;; -------------------------------------------------------------------------------
2198 ;; Includes:
2199 ;; - 7.6. Vector Indexed Instructions
2200 ;; -------------------------------------------------------------------------------
2202 ;; DEST eew is same as SOURCE eew, DEST register can overlap SOURCE.
2203 (define_insn "@pred_indexed_<order>load<mode>_same_eew"
2204 [(set (match_operand:VINDEXED 0 "register_operand" "=vd, vr,vd, vr")
2205 (if_then_else:VINDEXED
2206 (unspec:<VM>
2207 [(match_operand:<VM> 1 "vector_mask_operand" " vm,Wc1,vm,Wc1")
2208 (match_operand 5 "vector_length_operand" " rK, rK,rK, rK")
2209 (match_operand 6 "const_int_operand" " i, i, i, i")
2210 (match_operand 7 "const_int_operand" " i, i, i, i")
2211 (match_operand 8 "const_int_operand" " i, i, i, i")
2212 (reg:SI VL_REGNUM)
2213 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2214 (unspec:VINDEXED
2215 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ,rJ, rJ")
2216 (mem:BLK (scratch))
2217 (match_operand:<VINDEX> 4 "register_operand" " vr, vr,vr, vr")] ORDER)
2218 (match_operand:VINDEXED 2 "vector_merge_operand" " vu, vu, 0, 0")))]
2219 "TARGET_VECTOR"
2220 "vl<order>xei<sew>.v\t%0,(%z3),%4%p1"
2221 [(set_attr "type" "vld<order>x")
2222 (set_attr "mode" "<MODE>")])
2224 ;; DEST eew is greater than SOURCE eew.
2225 (define_insn "@pred_indexed_<order>load<mode>_x2_greater_eew"
2226 [(set (match_operand:VEEWEXT2 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
2227 (if_then_else:VEEWEXT2
2228 (unspec:<VM>
2229 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
2230 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
2231 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2232 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2233 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
2234 (reg:SI VL_REGNUM)
2235 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2236 (unspec:VEEWEXT2
2237 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ, rJ, rJ")
2238 (mem:BLK (scratch))
2239 (match_operand:<VINDEX_DOUBLE_TRUNC> 4 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")] ORDER)
2240 (match_operand:VEEWEXT2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
2241 "TARGET_VECTOR"
2242 "vl<order>xei<double_trunc_sew>.v\t%0,(%z3),%4%p1"
2243 [(set_attr "type" "vld<order>x")
2244 (set_attr "mode" "<MODE>")
2245 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
2247 (define_insn "@pred_indexed_<order>load<mode>_x4_greater_eew"
2248 [(set (match_operand:VEEWEXT4 0 "register_operand" "=vr, vr, vr, vr, ?&vr, ?&vr")
2249 (if_then_else:VEEWEXT4
2250 (unspec:<VM>
2251 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
2252 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2253 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2254 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2255 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2256 (reg:SI VL_REGNUM)
2257 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2258 (unspec:VEEWEXT4
2259 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2260 (mem:BLK (scratch))
2261 (match_operand:<VINDEX_QUAD_TRUNC> 4 "register_operand" " W43, W43, W86, W86, vr, vr")] ORDER)
2262 (match_operand:VEEWEXT4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2263 "TARGET_VECTOR"
2264 "vl<order>xei<quad_trunc_sew>.v\t%0,(%z3),%4%p1"
2265 [(set_attr "type" "vld<order>x")
2266 (set_attr "mode" "<MODE>")
2267 (set_attr "group_overlap" "W43,W43,W86,W86,none,none")])
2269 (define_insn "@pred_indexed_<order>load<mode>_x8_greater_eew"
2270 [(set (match_operand:VEEWEXT8 0 "register_operand" "=vr, vr, ?&vr, ?&vr")
2271 (if_then_else:VEEWEXT8
2272 (unspec:<VM>
2273 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
2274 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
2275 (match_operand 6 "const_int_operand" " i, i, i, i")
2276 (match_operand 7 "const_int_operand" " i, i, i, i")
2277 (match_operand 8 "const_int_operand" " i, i, i, i")
2278 (reg:SI VL_REGNUM)
2279 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2280 (unspec:VEEWEXT8
2281 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ")
2282 (mem:BLK (scratch))
2283 (match_operand:<VINDEX_OCT_TRUNC> 4 "register_operand" " W87, W87, vr, vr")] ORDER)
2284 (match_operand:VEEWEXT8 2 "vector_merge_operand" " vu, 0, vu, 0")))]
2285 "TARGET_VECTOR"
2286 "vl<order>xei<oct_trunc_sew>.v\t%0,(%z3),%4%p1"
2287 [(set_attr "type" "vld<order>x")
2288 (set_attr "mode" "<MODE>")
2289 (set_attr "group_overlap" "W87,W87,none,none")])
2291 ;; DEST eew is smaller than SOURCE eew.
2292 (define_insn "@pred_indexed_<order>load<mode>_x2_smaller_eew"
2293 [(set (match_operand:VEEWTRUNC2 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2294 (if_then_else:VEEWTRUNC2
2295 (unspec:<VM>
2296 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2297 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2298 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2299 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2300 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2301 (reg:SI VL_REGNUM)
2302 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2303 (unspec:VEEWTRUNC2
2304 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2305 (mem:BLK (scratch))
2306 (match_operand:<VINDEX_DOUBLE_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2307 (match_operand:VEEWTRUNC2 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2308 "TARGET_VECTOR"
2309 "vl<order>xei<double_ext_sew>.v\t%0,(%z3),%4%p1"
2310 [(set_attr "type" "vld<order>x")
2311 (set_attr "mode" "<MODE>")])
2313 (define_insn "@pred_indexed_<order>load<mode>_x4_smaller_eew"
2314 [(set (match_operand:VEEWTRUNC4 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2315 (if_then_else:VEEWTRUNC4
2316 (unspec:<VM>
2317 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2318 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2319 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2320 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2321 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2322 (reg:SI VL_REGNUM)
2323 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2324 (unspec:VEEWTRUNC4
2325 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2326 (mem:BLK (scratch))
2327 (match_operand:<VINDEX_QUAD_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2328 (match_operand:VEEWTRUNC4 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2329 "TARGET_VECTOR"
2330 "vl<order>xei<quad_ext_sew>.v\t%0,(%z3),%4%p1"
2331 [(set_attr "type" "vld<order>x")
2332 (set_attr "mode" "<MODE>")])
2334 (define_insn "@pred_indexed_<order>load<mode>_x8_smaller_eew"
2335 [(set (match_operand:VEEWTRUNC8 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
2336 (if_then_else:VEEWTRUNC8
2337 (unspec:<VM>
2338 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
2339 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
2340 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
2341 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
2342 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
2343 (reg:SI VL_REGNUM)
2344 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2345 (unspec:VEEWTRUNC8
2346 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ, rJ, rJ, rJ")
2347 (mem:BLK (scratch))
2348 (match_operand:<VINDEX_OCT_EXT> 4 "register_operand" " 0, 0, 0, 0, vr, vr")] ORDER)
2349 (match_operand:VEEWTRUNC8 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
2350 "TARGET_VECTOR"
2351 "vl<order>xei<oct_ext_sew>.v\t%0,(%z3),%4%p1"
2352 [(set_attr "type" "vld<order>x")
2353 (set_attr "mode" "<MODE>")])
2355 (define_insn "@pred_indexed_<order>store<RATIO64:mode><RATIO64I:mode>"
2356 [(set (mem:BLK (scratch))
2357 (unspec:BLK
2358 [(unspec:<VM>
2359 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2360 (match_operand 4 "vector_length_operand" " rK")
2361 (match_operand 5 "const_int_operand" " i")
2362 (reg:SI VL_REGNUM)
2363 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2364 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2365 (match_operand:RATIO64I 2 "register_operand" " vr")
2366 (match_operand:RATIO64 3 "register_operand" " vr")] ORDER))]
2367 "TARGET_VECTOR"
2368 "vs<order>xei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
2369 [(set_attr "type" "vst<order>x")
2370 (set_attr "mode" "<RATIO64:MODE>")])
2372 (define_insn "@pred_indexed_<order>store<RATIO32:mode><RATIO32I:mode>"
2373 [(set (mem:BLK (scratch))
2374 (unspec:BLK
2375 [(unspec:<VM>
2376 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2377 (match_operand 4 "vector_length_operand" " rK")
2378 (match_operand 5 "const_int_operand" " i")
2379 (reg:SI VL_REGNUM)
2380 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2381 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2382 (match_operand:RATIO32I 2 "register_operand" " vr")
2383 (match_operand:RATIO32 3 "register_operand" " vr")] ORDER))]
2384 "TARGET_VECTOR"
2385 "vs<order>xei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
2386 [(set_attr "type" "vst<order>x")
2387 (set_attr "mode" "<RATIO32:MODE>")])
2389 (define_insn "@pred_indexed_<order>store<RATIO16:mode><RATIO16I:mode>"
2390 [(set (mem:BLK (scratch))
2391 (unspec:BLK
2392 [(unspec:<VM>
2393 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2394 (match_operand 4 "vector_length_operand" " rK")
2395 (match_operand 5 "const_int_operand" " i")
2396 (reg:SI VL_REGNUM)
2397 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2398 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2399 (match_operand:RATIO16I 2 "register_operand" " vr")
2400 (match_operand:RATIO16 3 "register_operand" " vr")] ORDER))]
2401 "TARGET_VECTOR"
2402 "vs<order>xei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
2403 [(set_attr "type" "vst<order>x")
2404 (set_attr "mode" "<RATIO16:MODE>")])
2406 (define_insn "@pred_indexed_<order>store<RATIO8:mode><RATIO8I:mode>"
2407 [(set (mem:BLK (scratch))
2408 (unspec:BLK
2409 [(unspec:<VM>
2410 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2411 (match_operand 4 "vector_length_operand" " rK")
2412 (match_operand 5 "const_int_operand" " i")
2413 (reg:SI VL_REGNUM)
2414 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2415 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2416 (match_operand:RATIO8I 2 "register_operand" " vr")
2417 (match_operand:RATIO8 3 "register_operand" " vr")] ORDER))]
2418 "TARGET_VECTOR"
2419 "vs<order>xei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
2420 [(set_attr "type" "vst<order>x")
2421 (set_attr "mode" "<RATIO8:MODE>")])
2423 (define_insn "@pred_indexed_<order>store<RATIO4:mode><RATIO4I:mode>"
2424 [(set (mem:BLK (scratch))
2425 (unspec:BLK
2426 [(unspec:<VM>
2427 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2428 (match_operand 4 "vector_length_operand" " rK")
2429 (match_operand 5 "const_int_operand" " i")
2430 (reg:SI VL_REGNUM)
2431 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2432 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2433 (match_operand:RATIO4I 2 "register_operand" " vr")
2434 (match_operand:RATIO4 3 "register_operand" " vr")] ORDER))]
2435 "TARGET_VECTOR"
2436 "vs<order>xei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
2437 [(set_attr "type" "vst<order>x")
2438 (set_attr "mode" "<RATIO4:MODE>")])
2440 (define_insn "@pred_indexed_<order>store<RATIO2:mode><RATIO2I:mode>"
2441 [(set (mem:BLK (scratch))
2442 (unspec:BLK
2443 [(unspec:<VM>
2444 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2445 (match_operand 4 "vector_length_operand" " rK")
2446 (match_operand 5 "const_int_operand" " i")
2447 (reg:SI VL_REGNUM)
2448 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2449 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2450 (match_operand:RATIO2I 2 "register_operand" " vr")
2451 (match_operand:RATIO2 3 "register_operand" " vr")] ORDER))]
2452 "TARGET_VECTOR"
2453 "vs<order>xei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
2454 [(set_attr "type" "vst<order>x")
2455 (set_attr "mode" "<RATIO2:MODE>")])
2457 (define_insn "@pred_indexed_<order>store<RATIO1:mode><RATIO1:mode>"
2458 [(set (mem:BLK (scratch))
2459 (unspec:BLK
2460 [(unspec:<VM>
2461 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
2462 (match_operand 4 "vector_length_operand" " rK")
2463 (match_operand 5 "const_int_operand" " i")
2464 (reg:SI VL_REGNUM)
2465 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2466 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
2467 (match_operand:RATIO1 2 "register_operand" " vr")
2468 (match_operand:RATIO1 3 "register_operand" " vr")] ORDER))]
2469 "TARGET_VECTOR"
2470 "vs<order>xei<RATIO1:sew>.v\t%3,(%z1),%2%p0"
2471 [(set_attr "type" "vst<order>x")
2472 (set_attr "mode" "<RATIO1:MODE>")])
2474 ;; -------------------------------------------------------------------------------
2475 ;; ---- Predicated integer binary operations
2476 ;; -------------------------------------------------------------------------------
2477 ;; Includes:
2478 ;; - 11.1 Vector Single-Width Integer Add and Subtract
2479 ;; - 11.4 Vector Integer Add-with-Carry/Subtract-with-Borrow Instructions
2480 ;; - 11.5 Vector Bitwise Logical Instructions
2481 ;; - 11.6 Vector Single-Width Bit Shift Instructions
2482 ;; - 11.9 Vector Integer Min/Max Instructions
2483 ;; - 11.10 Vector Single-Width Integer Multiply Instructions
2484 ;; - 11.11 Vector Integer Divide Instructions
2485 ;; -------------------------------------------------------------------------------
2487 (define_insn "@pred_<optab><mode>"
2488 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr, vd, vd, vr, vr")
2489 (if_then_else:V_VLSI
2490 (unspec:<VM>
2491 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1, vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
2492 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK, rK")
2493 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2494 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2495 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
2496 (reg:SI VL_REGNUM)
2497 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2498 (any_int_binop:V_VLSI
2499 (match_operand:V_VLSI 3 "<binop_rhs1_predicate>" "<binop_rhs1_constraint>")
2500 (match_operand:V_VLSI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
2501 (match_operand:V_VLSI 2 "vector_merge_operand" "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
2502 "TARGET_VECTOR"
2503 "@
2504 v<insn>.vv\t%0,%3,%4%p1
2505 v<insn>.vv\t%0,%3,%4%p1
2506 v<insn>.vv\t%0,%3,%4%p1
2507 v<insn>.vv\t%0,%3,%4%p1
2508 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2509 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2510 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2511 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
2512 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2513 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2514 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1
2515 v<binop_reverse_vi_variant_insn>\t%0,<binop_reverse_vi_variant_op>%p1"
2516 [(set_attr "type" "<int_binop_insn_type>")
2517 (set_attr "mode" "<MODE>")])
2519 ;; vx instructions patterns.
2520 ;; Note: Unlike vv patterns, we should split them since they are variant.
2521 ;; For vsll.vx/vsra.vx/vsrl.vx the scalar mode should be Pmode wheras the
2522 ;; scalar mode is inner mode of the RVV mode for other vx patterns.
2523 (define_insn "@pred_<optab><mode>_scalar"
2524 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr,vd,vd, vr, vr")
2525 (if_then_else:V_VLSI
2526 (unspec:<VM>
2527 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1,vm,vm,Wc1,Wc1")
2528 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK,rK,rK, rK, rK")
2529 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
2530 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
2531 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
2532 (reg:SI VL_REGNUM)
2533 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2534 (any_shift:V_VLSI
2535 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr,vr,vr, vr, vr")
2536 (match_operand 4 "pmode_reg_or_uimm5_operand" " r, r, r, r, K, K, K, K"))
2537 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0,vu, 0, vu, 0")))]
2538 "TARGET_VECTOR"
2539 "v<insn>.v%o4\t%0,%3,%4%p1"
2540 [(set_attr "type" "vshift")
2541 (set_attr "mode" "<MODE>")])
2543 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
2544 (define_insn "@pred_<optab><mode>_scalar"
2545 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2546 (if_then_else:V_VLSI_QHS
2547 (unspec:<VM>
2548 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2549 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2550 (match_operand 6 "const_int_operand" " i, i, i, i")
2551 (match_operand 7 "const_int_operand" " i, i, i, i")
2552 (match_operand 8 "const_int_operand" " i, i, i, i")
2553 (reg:SI VL_REGNUM)
2554 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2555 (any_commutative_binop:V_VLSI_QHS
2556 (vec_duplicate:V_VLSI_QHS
2557 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2558 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2559 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2560 "TARGET_VECTOR"
2561 "v<insn>.vx\t%0,%3,%z4%p1"
2562 [(set_attr "type" "<int_binop_insn_type>")
2563 (set_attr "mode" "<MODE>")])
2565 (define_insn "@pred_<optab><mode>_scalar"
2566 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2567 (if_then_else:V_VLSI_QHS
2568 (unspec:<VM>
2569 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2570 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2571 (match_operand 6 "const_int_operand" " i, i, i, i")
2572 (match_operand 7 "const_int_operand" " i, i, i, i")
2573 (match_operand 8 "const_int_operand" " i, i, i, i")
2574 (reg:SI VL_REGNUM)
2575 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2576 (any_non_commutative_binop:V_VLSI_QHS
2577 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr")
2578 (vec_duplicate:V_VLSI_QHS
2579 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2580 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2581 "TARGET_VECTOR"
2582 "v<insn>.vx\t%0,%3,%z4%p1"
2583 [(set_attr "type" "<int_binop_insn_type>")
2584 (set_attr "mode" "<MODE>")])
2586 (define_insn "@pred_sub<mode>_reverse_scalar"
2587 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2588 (if_then_else:V_VLSI_QHS
2589 (unspec:<VM>
2590 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2591 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2592 (match_operand 6 "const_int_operand" " i, i, i, i")
2593 (match_operand 7 "const_int_operand" " i, i, i, i")
2594 (match_operand 8 "const_int_operand" " i, i, i, i")
2595 (reg:SI VL_REGNUM)
2596 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2597 (minus:V_VLSI_QHS
2598 (vec_duplicate:V_VLSI_QHS
2599 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2600 (match_operand:V_VLSI_QHS 3 "register_operand" "vr,vr, vr, vr"))
2601 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2602 "TARGET_VECTOR"
2603 "vrsub.vx\t%0,%3,%z4%p1"
2604 [(set_attr "type" "vialu")
2605 (set_attr "mode" "<MODE>")])
2607 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
2608 ;; we need to deal with SEW = 64 in RV32 system.
2609 (define_expand "@pred_<optab><mode>_scalar"
2610 [(set (match_operand:V_VLSI_D 0 "register_operand")
2611 (if_then_else:V_VLSI_D
2612 (unspec:<VM>
2613 [(match_operand:<VM> 1 "vector_mask_operand")
2614 (match_operand 5 "vector_length_operand")
2615 (match_operand 6 "const_int_operand")
2616 (match_operand 7 "const_int_operand")
2617 (match_operand 8 "const_int_operand")
2618 (reg:SI VL_REGNUM)
2619 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2620 (any_commutative_binop:V_VLSI_D
2621 (vec_duplicate:V_VLSI_D
2622 (match_operand:<VEL> 4 "reg_or_int_operand"))
2623 (match_operand:V_VLSI_D 3 "register_operand"))
2624 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2625 "TARGET_VECTOR"
2626 {
2627 if (riscv_vector::sew64_scalar_helper (
2628 operands,
2629 /* scalar op */&operands[4],
2630 /* vl */operands[5],
2631 <MODE>mode,
2632 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2633 [] (rtx *operands, rtx boardcast_scalar) {
2634 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2635 operands[2], operands[3], boardcast_scalar, operands[5],
2636 operands[6], operands[7], operands[8]));
2637 },
2638 (riscv_vector::avl_type) INTVAL (operands[8])))
2639 DONE;
2640 })
2642 (define_insn "*pred_<optab><mode>_scalar"
2643 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2644 (if_then_else:V_VLSI_D
2645 (unspec:<VM>
2646 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2647 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2648 (match_operand 6 "const_int_operand" " i, i, i, i")
2649 (match_operand 7 "const_int_operand" " i, i, i, i")
2650 (match_operand 8 "const_int_operand" " i, i, i, i")
2651 (reg:SI VL_REGNUM)
2652 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2653 (any_commutative_binop:V_VLSI_D
2654 (vec_duplicate:V_VLSI_D
2655 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2656 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2657 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2658 "TARGET_VECTOR"
2659 "v<insn>.vx\t%0,%3,%z4%p1"
2660 [(set_attr "type" "<int_binop_insn_type>")
2661 (set_attr "mode" "<MODE>")])
2663 (define_insn "*pred_<optab><mode>_extended_scalar"
2664 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2665 (if_then_else:V_VLSI_D
2666 (unspec:<VM>
2667 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2668 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2669 (match_operand 6 "const_int_operand" " i, i, i, i")
2670 (match_operand 7 "const_int_operand" " i, i, i, i")
2671 (match_operand 8 "const_int_operand" " i, i, i, i")
2672 (reg:SI VL_REGNUM)
2673 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2674 (any_commutative_binop:V_VLSI_D
2675 (vec_duplicate:V_VLSI_D
2676 (sign_extend:<VEL>
2677 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2678 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2679 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2680 "TARGET_VECTOR"
2681 "v<insn>.vx\t%0,%3,%z4%p1"
2682 [(set_attr "type" "<int_binop_insn_type>")
2683 (set_attr "mode" "<MODE>")])
2685 (define_expand "@pred_<optab><mode>_scalar"
2686 [(set (match_operand:V_VLSI_D 0 "register_operand")
2687 (if_then_else:V_VLSI_D
2688 (unspec:<VM>
2689 [(match_operand:<VM> 1 "vector_mask_operand")
2690 (match_operand 5 "vector_length_operand")
2691 (match_operand 6 "const_int_operand")
2692 (match_operand 7 "const_int_operand")
2693 (match_operand 8 "const_int_operand")
2694 (reg:SI VL_REGNUM)
2695 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2696 (any_non_commutative_binop:V_VLSI_D
2697 (match_operand:V_VLSI_D 3 "register_operand")
2698 (vec_duplicate:V_VLSI_D
2699 (match_operand:<VEL> 4 "reg_or_int_operand")))
2700 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2701 "TARGET_VECTOR"
2702 {
2703 if (riscv_vector::sew64_scalar_helper (
2704 operands,
2705 /* scalar op */&operands[4],
2706 /* vl */operands[5],
2707 <MODE>mode,
2708 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
2709 [] (rtx *operands, rtx boardcast_scalar) {
2710 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
2711 operands[2], operands[3], boardcast_scalar, operands[5],
2712 operands[6], operands[7], operands[8]));
2713 },
2714 (riscv_vector::avl_type) INTVAL (operands[8])))
2715 DONE;
2716 })
2718 (define_insn "*pred_<optab><mode>_scalar"
2719 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2720 (if_then_else:V_VLSI_D
2721 (unspec:<VM>
2722 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2723 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2724 (match_operand 6 "const_int_operand" " i, i, i, i")
2725 (match_operand 7 "const_int_operand" " i, i, i, i")
2726 (match_operand 8 "const_int_operand" " i, i, i, i")
2727 (reg:SI VL_REGNUM)
2728 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2729 (any_non_commutative_binop:V_VLSI_D
2730 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2731 (vec_duplicate:V_VLSI_D
2732 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2733 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2734 "TARGET_VECTOR"
2735 "v<insn>.vx\t%0,%3,%z4%p1"
2736 [(set_attr "type" "<int_binop_insn_type>")
2737 (set_attr "mode" "<MODE>")])
2739 (define_insn "*pred_<optab><mode>_extended_scalar"
2740 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2741 (if_then_else:V_VLSI_D
2742 (unspec:<VM>
2743 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2744 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2745 (match_operand 6 "const_int_operand" " i, i, i, i")
2746 (match_operand 7 "const_int_operand" " i, i, i, i")
2747 (match_operand 8 "const_int_operand" " i, i, i, i")
2748 (reg:SI VL_REGNUM)
2749 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2750 (any_non_commutative_binop:V_VLSI_D
2751 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr")
2752 (vec_duplicate:V_VLSI_D
2753 (sign_extend:<VEL>
2754 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))))
2755 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2756 "TARGET_VECTOR"
2757 "v<insn>.vx\t%0,%3,%z4%p1"
2758 [(set_attr "type" "<int_binop_insn_type>")
2759 (set_attr "mode" "<MODE>")])
2761 (define_expand "@pred_sub<mode>_reverse_scalar"
2762 [(set (match_operand:V_VLSI_D 0 "register_operand")
2763 (if_then_else:V_VLSI_D
2764 (unspec:<VM>
2765 [(match_operand:<VM> 1 "vector_mask_operand")
2766 (match_operand 5 "vector_length_operand")
2767 (match_operand 6 "const_int_operand")
2768 (match_operand 7 "const_int_operand")
2769 (match_operand 8 "const_int_operand")
2770 (reg:SI VL_REGNUM)
2771 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2772 (minus:V_VLSI_D
2773 (vec_duplicate:V_VLSI_D
2774 (match_operand:<VEL> 4 "reg_or_int_operand"))
2775 (match_operand:V_VLSI_D 3 "register_operand"))
2776 (match_operand:V_VLSI_D 2 "vector_merge_operand")))]
2777 "TARGET_VECTOR"
2778 {
2779 if (riscv_vector::sew64_scalar_helper (
2780 operands,
2781 /* scalar op */&operands[4],
2782 /* vl */operands[5],
2783 <MODE>mode,
2784 riscv_vector::neg_simm5_p (operands[4]),
2785 [] (rtx *operands, rtx boardcast_scalar) {
2786 emit_insn (gen_pred_sub<mode> (operands[0], operands[1],
2787 operands[2], boardcast_scalar, operands[3], operands[5],
2788 operands[6], operands[7], operands[8]));
2789 },
2790 (riscv_vector::avl_type) INTVAL (operands[8])))
2791 DONE;
2792 })
2794 (define_insn "*pred_sub<mode>_reverse_scalar"
2795 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2796 (if_then_else:V_VLSI_D
2797 (unspec:<VM>
2798 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2799 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2800 (match_operand 6 "const_int_operand" " i, i, i, i")
2801 (match_operand 7 "const_int_operand" " i, i, i, i")
2802 (match_operand 8 "const_int_operand" " i, i, i, i")
2803 (reg:SI VL_REGNUM)
2804 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2805 (minus:V_VLSI_D
2806 (vec_duplicate:V_VLSI_D
2807 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2808 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2809 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2810 "TARGET_VECTOR"
2811 "vrsub.vx\t%0,%3,%z4%p1"
2812 [(set_attr "type" "vialu")
2813 (set_attr "mode" "<MODE>")])
2815 (define_insn "*pred_sub<mode>_extended_reverse_scalar"
2816 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,vd, vr, vr")
2817 (if_then_else:V_VLSI_D
2818 (unspec:<VM>
2819 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2820 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2821 (match_operand 6 "const_int_operand" " i, i, i, i")
2822 (match_operand 7 "const_int_operand" " i, i, i, i")
2823 (match_operand 8 "const_int_operand" " i, i, i, i")
2824 (reg:SI VL_REGNUM)
2825 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2826 (minus:V_VLSI_D
2827 (vec_duplicate:V_VLSI_D
2828 (sign_extend:<VEL>
2829 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2830 (match_operand:V_VLSI_D 3 "register_operand" "vr,vr, vr, vr"))
2831 (match_operand:V_VLSI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2832 "TARGET_VECTOR"
2833 "vrsub.vx\t%0,%3,%z4%p1"
2834 [(set_attr "type" "vialu")
2835 (set_attr "mode" "<MODE>")])
2837 ;; Multiply High instructions.
2838 (define_insn "@pred_mulh<v_su><mode>"
2839 [(set (match_operand:VFULLI 0 "register_operand" "=vd,vd, vr, vr")
2840 (if_then_else:VFULLI
2841 (unspec:<VM>
2842 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2843 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2844 (match_operand 6 "const_int_operand" " i, i, i, i")
2845 (match_operand 7 "const_int_operand" " i, i, i, i")
2846 (match_operand 8 "const_int_operand" " i, i, i, i")
2847 (reg:SI VL_REGNUM)
2848 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2849 (unspec:VFULLI
2850 [(match_operand:VFULLI 3 "register_operand" "vr,vr, vr, vr")
2851 (match_operand:VFULLI 4 "register_operand" "vr,vr, vr, vr")] VMULH)
2852 (match_operand:VFULLI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2853 "TARGET_VECTOR"
2854 "vmulh<v_su>.vv\t%0,%3,%4%p1"
2855 [(set_attr "type" "vimul")
2856 (set_attr "mode" "<MODE>")])
2858 (define_insn "@pred_mulh<v_su><mode>_scalar"
2859 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd, vr, vr")
2860 (if_then_else:VI_QHS
2861 (unspec:<VM>
2862 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2863 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2864 (match_operand 6 "const_int_operand" " i, i, i, i")
2865 (match_operand 7 "const_int_operand" " i, i, i, i")
2866 (match_operand 8 "const_int_operand" " i, i, i, i")
2867 (reg:SI VL_REGNUM)
2868 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2869 (unspec:VI_QHS
2870 [(vec_duplicate:VI_QHS
2871 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2872 (match_operand:VI_QHS 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2873 (match_operand:VI_QHS 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2874 "TARGET_VECTOR"
2875 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2876 [(set_attr "type" "vimul")
2877 (set_attr "mode" "<MODE>")])
2879 (define_expand "@pred_mulh<v_su><mode>_scalar"
2880 [(set (match_operand:VFULLI_D 0 "register_operand")
2881 (if_then_else:VFULLI_D
2882 (unspec:<VM>
2883 [(match_operand:<VM> 1 "vector_mask_operand")
2884 (match_operand 5 "vector_length_operand")
2885 (match_operand 6 "const_int_operand")
2886 (match_operand 7 "const_int_operand")
2887 (match_operand 8 "const_int_operand")
2888 (reg:SI VL_REGNUM)
2889 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2890 (unspec:VFULLI_D
2891 [(vec_duplicate:VFULLI_D
2892 (match_operand:<VEL> 4 "reg_or_int_operand"))
2893 (match_operand:VFULLI_D 3 "register_operand")] VMULH)
2894 (match_operand:VFULLI_D 2 "vector_merge_operand")))]
2895 "TARGET_VECTOR"
2896 {
2897 if (riscv_vector::sew64_scalar_helper (
2898 operands,
2899 /* scalar op */&operands[4],
2900 /* vl */operands[5],
2901 <MODE>mode,
2902 false,
2903 [] (rtx *operands, rtx boardcast_scalar) {
2904 emit_insn (gen_pred_mulh<v_su><mode> (operands[0], operands[1],
2905 operands[2], operands[3], boardcast_scalar, operands[5],
2906 operands[6], operands[7], operands[8]));
2907 },
2908 (riscv_vector::avl_type) INTVAL (operands[8])))
2909 DONE;
2910 })
2912 (define_insn "*pred_mulh<v_su><mode>_scalar"
2913 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
2914 (if_then_else:VFULLI_D
2915 (unspec:<VM>
2916 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2917 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2918 (match_operand 6 "const_int_operand" " i, i, i, i")
2919 (match_operand 7 "const_int_operand" " i, i, i, i")
2920 (match_operand 8 "const_int_operand" " i, i, i, i")
2921 (reg:SI VL_REGNUM)
2922 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2923 (unspec:VFULLI_D
2924 [(vec_duplicate:VFULLI_D
2925 (match_operand:<VEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ"))
2926 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2927 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2928 "TARGET_VECTOR"
2929 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2930 [(set_attr "type" "vimul")
2931 (set_attr "mode" "<MODE>")])
2933 (define_insn "*pred_mulh<v_su><mode>_extended_scalar"
2934 [(set (match_operand:VFULLI_D 0 "register_operand" "=vd,vd, vr, vr")
2935 (if_then_else:VFULLI_D
2936 (unspec:<VM>
2937 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
2938 (match_operand 5 "vector_length_operand" "rK,rK, rK, rK")
2939 (match_operand 6 "const_int_operand" " i, i, i, i")
2940 (match_operand 7 "const_int_operand" " i, i, i, i")
2941 (match_operand 8 "const_int_operand" " i, i, i, i")
2942 (reg:SI VL_REGNUM)
2943 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2944 (unspec:VFULLI_D
2945 [(vec_duplicate:VFULLI_D
2946 (sign_extend:<VEL>
2947 (match_operand:<VSUBEL> 4 "reg_or_0_operand" "rJ,rJ, rJ, rJ")))
2948 (match_operand:VFULLI_D 3 "register_operand" "vr,vr, vr, vr")] VMULH)
2949 (match_operand:VFULLI_D 2 "vector_merge_operand" "vu, 0, vu, 0")))]
2950 "TARGET_VECTOR"
2951 "vmulh<v_su>.vx\t%0,%3,%z4%p1"
2952 [(set_attr "type" "vimul")
2953 (set_attr "mode" "<MODE>")])
2955 ;; Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
2956 (define_insn "@pred_adc<mode>"
2957 [(set (match_operand:VI 0 "register_operand" "=vd,vd,vd,vd")
2958 (if_then_else:VI
2959 (unspec:<VM>
2960 [(match_operand 5 "vector_length_operand" "rK,rK,rK,rK")
2961 (match_operand 6 "const_int_operand" " i, i, i, i")
2962 (match_operand 7 "const_int_operand" " i, i, i, i")
2963 (reg:SI VL_REGNUM)
2964 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2965 (unspec:VI
2966 [(plus:VI
2967 (match_operand:VI 2 "register_operand" "vr,vr,vr,vr")
2968 (match_operand:VI 3 "vector_arith_operand" "vr,vr,vi,vi"))
2969 (match_operand:<VM> 4 "register_operand" "vm,vm,vm,vm")] UNSPEC_VADC)
2970 (match_operand:VI 1 "vector_merge_operand" "vu, 0,vu, 0")))]
2971 "TARGET_VECTOR"
2972 "vadc.v%o3m\t%0,%2,%v3,%4"
2973 [(set_attr "type" "vicalu")
2974 (set_attr "mode" "<MODE>")
2975 (set_attr "merge_op_idx" "1")
2976 (set_attr "vl_op_idx" "5")
2977 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
2978 (set (attr "avl_type_idx") (const_int 7))])
2980 (define_insn "@pred_sbc<mode>"
2981 [(set (match_operand:VI 0 "register_operand" "=vd,vd")
2982 (if_then_else:VI
2983 (unspec:<VM>
2984 [(match_operand 5 "vector_length_operand" "rK,rK")
2985 (match_operand 6 "const_int_operand" " i, i")
2986 (match_operand 7 "const_int_operand" " i, i")
2987 (reg:SI VL_REGNUM)
2988 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
2989 (unspec:VI
2990 [(minus:VI
2991 (match_operand:VI 2 "register_operand" "vr,vr")
2992 (match_operand:VI 3 "register_operand" "vr,vr"))
2993 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
2994 (match_operand:VI 1 "vector_merge_operand" "vu, 0")))]
2995 "TARGET_VECTOR"
2996 "vsbc.vvm\t%0,%2,%3,%4"
2997 [(set_attr "type" "vicalu")
2998 (set_attr "mode" "<MODE>")
2999 (set_attr "merge_op_idx" "1")
3000 (set_attr "vl_op_idx" "5")
3001 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3002 (set (attr "avl_type_idx") (const_int 7))])
3004 (define_insn "@pred_adc<mode>_scalar"
3005 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3006 (if_then_else:VI_QHS
3007 (unspec:<VM>
3008 [(match_operand 5 "vector_length_operand" "rK,rK")
3009 (match_operand 6 "const_int_operand" " i, i")
3010 (match_operand 7 "const_int_operand" " i, i")
3011 (reg:SI VL_REGNUM)
3012 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3013 (unspec:VI_QHS
3014 [(plus:VI_QHS
3015 (vec_duplicate:VI_QHS
3016 (match_operand:<VEL> 3 "register_operand" " r, r"))
3017 (match_operand:VI_QHS 2 "register_operand" "vr,vr"))
3018 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3019 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3020 "TARGET_VECTOR"
3021 "vadc.vxm\t%0,%2,%3,%4"
3022 [(set_attr "type" "vicalu")
3023 (set_attr "mode" "<MODE>")
3024 (set_attr "merge_op_idx" "1")
3025 (set_attr "vl_op_idx" "5")
3026 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3027 (set (attr "avl_type_idx") (const_int 7))])
3029 (define_insn "@pred_sbc<mode>_scalar"
3030 [(set (match_operand:VI_QHS 0 "register_operand" "=vd,vd")
3031 (if_then_else:VI_QHS
3032 (unspec:<VM>
3033 [(match_operand 5 "vector_length_operand" "rK,rK")
3034 (match_operand 6 "const_int_operand" " i, i")
3035 (match_operand 7 "const_int_operand" " i, i")
3036 (reg:SI VL_REGNUM)
3037 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3038 (unspec:VI_QHS
3039 [(minus:VI_QHS
3040 (match_operand:VI_QHS 2 "register_operand" "vr,vr")
3041 (vec_duplicate:VI_QHS
3042 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3043 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3044 (match_operand:VI_QHS 1 "vector_merge_operand" "vu, 0")))]
3045 "TARGET_VECTOR"
3046 "vsbc.vxm\t%0,%2,%z3,%4"
3047 [(set_attr "type" "vicalu")
3048 (set_attr "mode" "<MODE>")
3049 (set_attr "merge_op_idx" "1")
3050 (set_attr "vl_op_idx" "5")
3051 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3052 (set (attr "avl_type_idx") (const_int 7))])
3054 (define_expand "@pred_adc<mode>_scalar"
3055 [(set (match_operand:VI_D 0 "register_operand")
3056 (if_then_else:VI_D
3057 (unspec:<VM>
3058 [(match_operand 5 "vector_length_operand")
3059 (match_operand 6 "const_int_operand")
3060 (match_operand 7 "const_int_operand")
3061 (reg:SI VL_REGNUM)
3062 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3063 (unspec:VI_D
3064 [(plus:VI_D
3065 (vec_duplicate:VI_D
3066 (match_operand:<VEL> 3 "reg_or_int_operand"))
3067 (match_operand:VI_D 2 "register_operand"))
3068 (match_operand:<VM> 4 "register_operand")] UNSPEC_VADC)
3069 (match_operand:VI_D 1 "vector_merge_operand")))]
3070 "TARGET_VECTOR"
3071 {
3072 if (riscv_vector::sew64_scalar_helper (
3073 operands,
3074 /* scalar op */&operands[3],
3075 /* vl */operands[5],
3076 <MODE>mode,
3077 riscv_vector::simm5_p (operands[3]),
3078 [] (rtx *operands, rtx boardcast_scalar) {
3079 emit_insn (gen_pred_adc<mode> (operands[0], operands[1],
3080 operands[2], boardcast_scalar, operands[4], operands[5],
3081 operands[6], operands[7]));
3082 },
3083 (riscv_vector::avl_type) INTVAL (operands[7])))
3084 DONE;
3085 })
3087 (define_insn "*pred_adc<mode>_scalar"
3088 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3089 (if_then_else:VI_D
3090 (unspec:<VM>
3091 [(match_operand 5 "vector_length_operand" "rK,rK")
3092 (match_operand 6 "const_int_operand" " i, i")
3093 (match_operand 7 "const_int_operand" " i, i")
3094 (reg:SI VL_REGNUM)
3095 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3096 (unspec:VI_D
3097 [(plus:VI_D
3098 (vec_duplicate:VI_D
3099 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ"))
3100 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3101 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3102 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3103 "TARGET_VECTOR"
3104 "vadc.vxm\t%0,%2,%z3,%4"
3105 [(set_attr "type" "vicalu")
3106 (set_attr "mode" "<MODE>")
3107 (set_attr "merge_op_idx" "1")
3108 (set_attr "vl_op_idx" "5")
3109 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3110 (set (attr "avl_type_idx") (const_int 7))])
3112 (define_insn "*pred_adc<mode>_extended_scalar"
3113 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3114 (if_then_else:VI_D
3115 (unspec:<VM>
3116 [(match_operand 5 "vector_length_operand" "rK,rK")
3117 (match_operand 6 "const_int_operand" " i, i")
3118 (match_operand 7 "const_int_operand" " i, i")
3119 (reg:SI VL_REGNUM)
3120 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3121 (unspec:VI_D
3122 [(plus:VI_D
3123 (vec_duplicate:VI_D
3124 (sign_extend:<VEL>
3125 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ")))
3126 (match_operand:VI_D 2 "register_operand" "vr,vr"))
3127 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VADC)
3128 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3129 "TARGET_VECTOR"
3130 "vadc.vxm\t%0,%2,%z3,%4"
3131 [(set_attr "type" "vicalu")
3132 (set_attr "mode" "<MODE>")
3133 (set_attr "merge_op_idx" "1")
3134 (set_attr "vl_op_idx" "5")
3135 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3136 (set (attr "avl_type_idx") (const_int 7))])
3138 (define_expand "@pred_sbc<mode>_scalar"
3139 [(set (match_operand:VI_D 0 "register_operand")
3140 (if_then_else:VI_D
3141 (unspec:<VM>
3142 [(match_operand 5 "vector_length_operand")
3143 (match_operand 6 "const_int_operand")
3144 (match_operand 7 "const_int_operand")
3145 (reg:SI VL_REGNUM)
3146 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3147 (unspec:VI_D
3148 [(minus:VI_D
3149 (match_operand:VI_D 2 "register_operand")
3150 (vec_duplicate:VI_D
3151 (match_operand:<VEL> 3 "reg_or_int_operand")))
3152 (match_operand:<VM> 4 "register_operand")] UNSPEC_VSBC)
3153 (match_operand:VI_D 1 "vector_merge_operand")))]
3154 "TARGET_VECTOR"
3155 {
3156 if (riscv_vector::sew64_scalar_helper (
3157 operands,
3158 /* scalar op */&operands[3],
3159 /* vl */operands[5],
3160 <MODE>mode,
3161 false,
3162 [] (rtx *operands, rtx boardcast_scalar) {
3163 emit_insn (gen_pred_sbc<mode> (operands[0], operands[1],
3164 operands[2], boardcast_scalar, operands[4], operands[5],
3165 operands[6], operands[7]));
3166 },
3167 (riscv_vector::avl_type) INTVAL (operands[7])))
3168 DONE;
3169 })
3171 (define_insn "*pred_sbc<mode>_scalar"
3172 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3173 (if_then_else:VI_D
3174 (unspec:<VM>
3175 [(match_operand 5 "vector_length_operand" "rK,rK")
3176 (match_operand 6 "const_int_operand" " i, i")
3177 (match_operand 7 "const_int_operand" " i, i")
3178 (reg:SI VL_REGNUM)
3179 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3180 (unspec:VI_D
3181 [(minus:VI_D
3182 (match_operand:VI_D 2 "register_operand" "vr,vr")
3183 (vec_duplicate:VI_D
3184 (match_operand:<VEL> 3 "reg_or_0_operand" "rJ,rJ")))
3185 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3186 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3187 "TARGET_VECTOR"
3188 "vsbc.vxm\t%0,%2,%z3,%4"
3189 [(set_attr "type" "vicalu")
3190 (set_attr "mode" "<MODE>")
3191 (set_attr "merge_op_idx" "1")
3192 (set_attr "vl_op_idx" "5")
3193 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3194 (set (attr "avl_type_idx") (const_int 7))])
3196 (define_insn "*pred_sbc<mode>_extended_scalar"
3197 [(set (match_operand:VI_D 0 "register_operand" "=vd,vd")
3198 (if_then_else:VI_D
3199 (unspec:<VM>
3200 [(match_operand 5 "vector_length_operand" "rK,rK")
3201 (match_operand 6 "const_int_operand" " i, i")
3202 (match_operand 7 "const_int_operand" " i, i")
3203 (reg:SI VL_REGNUM)
3204 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3205 (unspec:VI_D
3206 [(minus:VI_D
3207 (match_operand:VI_D 2 "register_operand" "vr,vr")
3208 (vec_duplicate:VI_D
3209 (sign_extend:<VEL>
3210 (match_operand:<VSUBEL> 3 "reg_or_0_operand" "rJ,rJ"))))
3211 (match_operand:<VM> 4 "register_operand" "vm,vm")] UNSPEC_VSBC)
3212 (match_operand:VI_D 1 "vector_merge_operand" "vu, 0")))]
3213 "TARGET_VECTOR"
3214 "vsbc.vxm\t%0,%2,%z3,%4"
3215 [(set_attr "type" "vicalu")
3216 (set_attr "mode" "<MODE>")
3217 (set_attr "merge_op_idx" "1")
3218 (set_attr "vl_op_idx" "5")
3219 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
3220 (set (attr "avl_type_idx") (const_int 7))])
3222 (define_insn "@pred_madc<mode>"
3223 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3224 (unspec:<VM>
3225 [(plus:VI
3226 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3227 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3228 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3229 (unspec:<VM>
3230 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3231 (match_operand 5 "const_int_operand" " i, i, i")
3232 (reg:SI VL_REGNUM)
3233 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3234 "TARGET_VECTOR"
3235 "vmadc.v%o2m\t%0,%1,%v2,%3"
3236 [(set_attr "type" "vicalu")
3237 (set_attr "mode" "<MODE>")
3238 (set_attr "vl_op_idx" "4")
3239 (set (attr "avl_type_idx") (const_int 5))])
3241 (define_insn "@pred_msbc<mode>"
3242 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr")
3243 (unspec:<VM>
3244 [(minus:VI
3245 (match_operand:VI 1 "register_operand" " 0, vr, vr")
3246 (match_operand:VI 2 "register_operand" " vr, 0, vr"))
3247 (match_operand:<VM> 3 "register_operand" " vm, vm, vm")
3248 (unspec:<VM>
3249 [(match_operand 4 "vector_length_operand" " rK, rK, rK")
3250 (match_operand 5 "const_int_operand" " i, i, i")
3251 (reg:SI VL_REGNUM)
3252 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3253 "TARGET_VECTOR"
3254 "vmsbc.vvm\t%0,%1,%2,%3"
3255 [(set_attr "type" "vicalu")
3256 (set_attr "mode" "<MODE>")
3257 (set_attr "vl_op_idx" "4")
3258 (set (attr "avl_type_idx") (const_int 5))])
3260 (define_insn "@pred_madc<mode>_scalar"
3261 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3262 (unspec:<VM>
3263 [(plus:VI_QHS
3264 (vec_duplicate:VI_QHS
3265 (match_operand:<VEL> 2 "register_operand" " r, r"))
3266 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3267 (match_operand:<VM> 3 "register_operand" " vm, vm")
3268 (unspec:<VM>
3269 [(match_operand 4 "vector_length_operand" " rK, rK")
3270 (match_operand 5 "const_int_operand" " i, i")
3271 (reg:SI VL_REGNUM)
3272 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3273 "TARGET_VECTOR"
3274 "vmadc.vxm\t%0,%1,%2,%3"
3275 [(set_attr "type" "vicalu")
3276 (set_attr "mode" "<MODE>")
3277 (set_attr "vl_op_idx" "4")
3278 (set (attr "avl_type_idx") (const_int 5))])
3280 (define_insn "@pred_msbc<mode>_scalar"
3281 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3282 (unspec:<VM>
3283 [(minus:VI_QHS
3284 (vec_duplicate:VI_QHS
3285 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3286 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3287 (match_operand:<VM> 3 "register_operand" " vm, vm")
3288 (unspec:<VM>
3289 [(match_operand 4 "vector_length_operand" " rK, rK")
3290 (match_operand 5 "const_int_operand" " i, i")
3291 (reg:SI VL_REGNUM)
3292 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3293 "TARGET_VECTOR"
3294 "vmsbc.vxm\t%0,%1,%z2,%3"
3295 [(set_attr "type" "vicalu")
3296 (set_attr "mode" "<MODE>")
3297 (set_attr "vl_op_idx" "4")
3298 (set (attr "avl_type_idx") (const_int 5))])
3300 (define_expand "@pred_madc<mode>_scalar"
3301 [(set (match_operand:<VM> 0 "register_operand")
3302 (unspec:<VM>
3303 [(plus:VI_D
3304 (vec_duplicate:VI_D
3305 (match_operand:<VEL> 2 "reg_or_int_operand"))
3306 (match_operand:VI_D 1 "register_operand"))
3307 (match_operand:<VM> 3 "register_operand")
3308 (unspec:<VM>
3309 [(match_operand 4 "vector_length_operand")
3310 (match_operand 5 "const_int_operand")
3311 (reg:SI VL_REGNUM)
3312 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3313 "TARGET_VECTOR"
3314 {
3315 if (riscv_vector::sew64_scalar_helper (
3316 operands,
3317 /* scalar op */&operands[2],
3318 /* vl */operands[4],
3319 <MODE>mode,
3320 riscv_vector::simm5_p (operands[2]),
3321 [] (rtx *operands, rtx boardcast_scalar) {
3322 emit_insn (gen_pred_madc<mode> (operands[0], operands[1],
3323 boardcast_scalar, operands[3], operands[4], operands[5]));
3324 },
3325 (riscv_vector::avl_type) INTVAL (operands[5])))
3326 DONE;
3327 })
3329 (define_insn "*pred_madc<mode>_scalar"
3330 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3331 (unspec:<VM>
3332 [(plus:VI_D
3333 (vec_duplicate:VI_D
3334 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3335 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3336 (match_operand:<VM> 3 "register_operand" " vm, vm")
3337 (unspec:<VM>
3338 [(match_operand 4 "vector_length_operand" " rK, rK")
3339 (match_operand 5 "const_int_operand" " i, i")
3340 (reg:SI VL_REGNUM)
3341 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3342 "TARGET_VECTOR"
3343 "vmadc.vxm\t%0,%1,%z2,%3"
3344 [(set_attr "type" "vicalu")
3345 (set_attr "mode" "<MODE>")
3346 (set_attr "vl_op_idx" "4")
3347 (set (attr "avl_type_idx") (const_int 5))])
3349 (define_insn "*pred_madc<mode>_extended_scalar"
3350 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3351 (unspec:<VM>
3352 [(plus:VI_D
3353 (vec_duplicate:VI_D
3354 (sign_extend:<VEL>
3355 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3356 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3357 (match_operand:<VM> 3 "register_operand" " vm, vm")
3358 (unspec:<VM>
3359 [(match_operand 4 "vector_length_operand" " rK, rK")
3360 (match_operand 5 "const_int_operand" " i, i")
3361 (reg:SI VL_REGNUM)
3362 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))]
3363 "TARGET_VECTOR"
3364 "vmadc.vxm\t%0,%1,%z2,%3"
3365 [(set_attr "type" "vicalu")
3366 (set_attr "mode" "<MODE>")
3367 (set_attr "vl_op_idx" "4")
3368 (set (attr "avl_type_idx") (const_int 5))])
3370 (define_expand "@pred_msbc<mode>_scalar"
3371 [(set (match_operand:<VM> 0 "register_operand")
3372 (unspec:<VM>
3373 [(minus:VI_D
3374 (vec_duplicate:VI_D
3375 (match_operand:<VEL> 2 "reg_or_int_operand"))
3376 (match_operand:VI_D 1 "register_operand"))
3377 (match_operand:<VM> 3 "register_operand")
3378 (unspec:<VM>
3379 [(match_operand 4 "vector_length_operand")
3380 (match_operand 5 "const_int_operand")
3381 (reg:SI VL_REGNUM)
3382 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3383 "TARGET_VECTOR"
3384 {
3385 if (riscv_vector::sew64_scalar_helper (
3386 operands,
3387 /* scalar op */&operands[2],
3388 /* vl */operands[4],
3389 <MODE>mode,
3390 false,
3391 [] (rtx *operands, rtx boardcast_scalar) {
3392 emit_insn (gen_pred_msbc<mode> (operands[0], operands[1],
3393 boardcast_scalar, operands[3], operands[4], operands[5]));
3394 },
3395 (riscv_vector::avl_type) INTVAL (operands[5])))
3396 DONE;
3397 })
3399 (define_insn "*pred_msbc<mode>_scalar"
3400 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3401 (unspec:<VM>
3402 [(minus:VI_D
3403 (vec_duplicate:VI_D
3404 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3405 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3406 (match_operand:<VM> 3 "register_operand" " vm, vm")
3407 (unspec:<VM>
3408 [(match_operand 4 "vector_length_operand" " rK, rK")
3409 (match_operand 5 "const_int_operand" " i, i")
3410 (reg:SI VL_REGNUM)
3411 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3412 "TARGET_VECTOR"
3413 "vmsbc.vxm\t%0,%1,%z2,%3"
3414 [(set_attr "type" "vicalu")
3415 (set_attr "mode" "<MODE>")
3416 (set_attr "vl_op_idx" "4")
3417 (set (attr "avl_type_idx") (const_int 5))])
3419 (define_insn "*pred_msbc<mode>_extended_scalar"
3420 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3421 (unspec:<VM>
3422 [(minus:VI_D
3423 (vec_duplicate:VI_D
3424 (sign_extend:<VEL>
3425 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3426 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3427 (match_operand:<VM> 3 "register_operand" " vm, vm")
3428 (unspec:<VM>
3429 [(match_operand 4 "vector_length_operand" " rK, rK")
3430 (match_operand 5 "const_int_operand" " i, i")
3431 (reg:SI VL_REGNUM)
3432 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))]
3433 "TARGET_VECTOR"
3434 "vmsbc.vxm\t%0,%1,%z2,%3"
3435 [(set_attr "type" "vicalu")
3436 (set_attr "mode" "<MODE>")
3437 (set_attr "vl_op_idx" "4")
3438 (set (attr "avl_type_idx") (const_int 5))])
3440 (define_insn "@pred_madc<mode>_overflow"
3441 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr, &vr")
3442 (unspec:<VM>
3443 [(plus:VI
3444 (match_operand:VI 1 "register_operand" " %0, vr, vr")
3445 (match_operand:VI 2 "vector_arith_operand" "vrvi, vr, vi"))
3446 (unspec:<VM>
3447 [(match_operand 3 "vector_length_operand" " rK, rK, rK")
3448 (match_operand 4 "const_int_operand" " i, i, i")
3449 (reg:SI VL_REGNUM)
3450 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3451 "TARGET_VECTOR"
3452 "vmadc.v%o2\t%0,%1,%v2"
3453 [(set_attr "type" "vicalu")
3454 (set_attr "mode" "<MODE>")
3455 (set_attr "vl_op_idx" "3")
3456 (set (attr "avl_type_idx") (const_int 4))])
3458 (define_insn "@pred_msbc<mode>_overflow"
3459 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, &vr, &vr")
3460 (unspec:<VM>
3461 [(minus:VI
3462 (match_operand:VI 1 "register_operand" " 0, vr, vr, vr")
3463 (match_operand:VI 2 "register_operand" " vr, 0, vr, vi"))
3464 (unspec:<VM>
3465 [(match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
3466 (match_operand 4 "const_int_operand" " i, i, i, i")
3467 (reg:SI VL_REGNUM)
3468 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3469 "TARGET_VECTOR"
3470 "vmsbc.vv\t%0,%1,%2"
3471 [(set_attr "type" "vicalu")
3472 (set_attr "mode" "<MODE>")
3473 (set_attr "vl_op_idx" "3")
3474 (set (attr "avl_type_idx") (const_int 4))])
3476 (define_insn "@pred_madc<mode>_overflow_scalar"
3477 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3478 (unspec:<VM>
3479 [(plus:VI_QHS
3480 (vec_duplicate:VI_QHS
3481 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3482 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3483 (unspec:<VM>
3484 [(match_operand 3 "vector_length_operand" " rK, rK")
3485 (match_operand 4 "const_int_operand" " i, i")
3486 (reg:SI VL_REGNUM)
3487 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3488 "TARGET_VECTOR"
3489 "vmadc.vx\t%0,%1,%z2"
3490 [(set_attr "type" "vicalu")
3491 (set_attr "mode" "<MODE>")
3492 (set_attr "vl_op_idx" "3")
3493 (set (attr "avl_type_idx") (const_int 4))])
3495 (define_insn "@pred_msbc<mode>_overflow_scalar"
3496 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3497 (unspec:<VM>
3498 [(minus:VI_QHS
3499 (vec_duplicate:VI_QHS
3500 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3501 (match_operand:VI_QHS 1 "register_operand" " 0, vr"))
3502 (unspec:<VM>
3503 [(match_operand 3 "vector_length_operand" " rK, rK")
3504 (match_operand 4 "const_int_operand" " i, i")
3505 (reg:SI VL_REGNUM)
3506 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3507 "TARGET_VECTOR"
3508 "vmsbc.vx\t%0,%1,%z2"
3509 [(set_attr "type" "vicalu")
3510 (set_attr "mode" "<MODE>")
3511 (set_attr "vl_op_idx" "3")
3512 (set (attr "avl_type_idx") (const_int 4))])
3514 (define_expand "@pred_madc<mode>_overflow_scalar"
3515 [(set (match_operand:<VM> 0 "register_operand")
3516 (unspec:<VM>
3517 [(plus:VI_D
3518 (vec_duplicate:VI_D
3519 (match_operand:<VEL> 2 "reg_or_int_operand"))
3520 (match_operand:VI_D 1 "register_operand"))
3521 (unspec:<VM>
3522 [(match_operand 3 "vector_length_operand")
3523 (match_operand 4 "const_int_operand")
3524 (reg:SI VL_REGNUM)
3525 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3526 "TARGET_VECTOR"
3527 {
3528 if (riscv_vector::sew64_scalar_helper (
3529 operands,
3530 /* scalar op */&operands[2],
3531 /* vl */operands[3],
3532 <MODE>mode,
3533 riscv_vector::simm5_p (operands[2]),
3534 [] (rtx *operands, rtx boardcast_scalar) {
3535 emit_insn (gen_pred_madc<mode>_overflow (operands[0], operands[1],
3536 boardcast_scalar, operands[3], operands[4]));
3537 },
3538 (riscv_vector::avl_type) INTVAL (operands[4])))
3539 DONE;
3540 })
3542 (define_insn "*pred_madc<mode>_overflow_scalar"
3543 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3544 (unspec:<VM>
3545 [(plus:VI_D
3546 (vec_duplicate:VI_D
3547 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3548 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3549 (unspec:<VM>
3550 [(match_operand 3 "vector_length_operand" " rK, rK")
3551 (match_operand 4 "const_int_operand" " i, i")
3552 (reg:SI VL_REGNUM)
3553 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3554 "TARGET_VECTOR"
3555 "vmadc.vx\t%0,%1,%z2"
3556 [(set_attr "type" "vicalu")
3557 (set_attr "mode" "<MODE>")
3558 (set_attr "vl_op_idx" "3")
3559 (set (attr "avl_type_idx") (const_int 4))])
3561 (define_insn "*pred_madc<mode>_overflow_extended_scalar"
3562 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3563 (unspec:<VM>
3564 [(plus:VI_D
3565 (vec_duplicate:VI_D
3566 (sign_extend:<VEL>
3567 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3568 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3569 (unspec:<VM>
3570 [(match_operand 3 "vector_length_operand" " rK, rK")
3571 (match_operand 4 "const_int_operand" " i, i")
3572 (reg:SI VL_REGNUM)
3573 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3574 "TARGET_VECTOR"
3575 "vmadc.vx\t%0,%1,%z2"
3576 [(set_attr "type" "vicalu")
3577 (set_attr "mode" "<MODE>")
3578 (set_attr "vl_op_idx" "3")
3579 (set (attr "avl_type_idx") (const_int 4))])
3581 (define_expand "@pred_msbc<mode>_overflow_scalar"
3582 [(set (match_operand:<VM> 0 "register_operand")
3583 (unspec:<VM>
3584 [(minus:VI_D
3585 (vec_duplicate:VI_D
3586 (match_operand:<VEL> 2 "reg_or_int_operand"))
3587 (match_operand:VI_D 1 "register_operand"))
3588 (unspec:<VM>
3589 [(match_operand 3 "vector_length_operand")
3590 (match_operand 4 "const_int_operand")
3591 (reg:SI VL_REGNUM)
3592 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3593 "TARGET_VECTOR"
3594 {
3595 if (riscv_vector::sew64_scalar_helper (
3596 operands,
3597 /* scalar op */&operands[2],
3598 /* vl */operands[3],
3599 <MODE>mode,
3600 false,
3601 [] (rtx *operands, rtx boardcast_scalar) {
3602 emit_insn (gen_pred_msbc<mode>_overflow (operands[0], operands[1],
3603 boardcast_scalar, operands[3], operands[4]));
3604 },
3605 (riscv_vector::avl_type) INTVAL (operands[4])))
3606 DONE;
3607 })
3609 (define_insn "*pred_msbc<mode>_overflow_scalar"
3610 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3611 (unspec:<VM>
3612 [(minus:VI_D
3613 (vec_duplicate:VI_D
3614 (match_operand:<VEL> 2 "reg_or_0_operand" " rJ, rJ"))
3615 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3616 (unspec:<VM>
3617 [(match_operand 3 "vector_length_operand" " rK, rK")
3618 (match_operand 4 "const_int_operand" " i, i")
3619 (reg:SI VL_REGNUM)
3620 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3621 "TARGET_VECTOR"
3622 "vmsbc.vx\t%0,%1,%z2"
3623 [(set_attr "type" "vicalu")
3624 (set_attr "mode" "<MODE>")
3625 (set_attr "vl_op_idx" "3")
3626 (set (attr "avl_type_idx") (const_int 4))])
3628 (define_insn "*pred_msbc<mode>_overflow_extended_scalar"
3629 [(set (match_operand:<VM> 0 "register_operand" "=vr, &vr")
3630 (unspec:<VM>
3631 [(minus:VI_D
3632 (vec_duplicate:VI_D
3633 (sign_extend:<VEL>
3634 (match_operand:<VSUBEL> 2 "reg_or_0_operand" " rJ, rJ")))
3635 (match_operand:VI_D 1 "register_operand" " 0, vr"))
3636 (unspec:<VM>
3637 [(match_operand 3 "vector_length_operand" " rK, rK")
3638 (match_operand 4 "const_int_operand" " i, i")
3639 (reg:SI VL_REGNUM)
3640 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))]
3641 "TARGET_VECTOR"
3642 "vmsbc.vx\t%0,%1,%z2"
3643 [(set_attr "type" "vicalu")
3644 (set_attr "mode" "<MODE>")
3645 (set_attr "vl_op_idx" "3")
3646 (set (attr "avl_type_idx") (const_int 4))])
3648 ;; -------------------------------------------------------------------------------
3649 ;; ---- Predicated integer unary operations
3650 ;; -------------------------------------------------------------------------------
3651 ;; Includes:
3652 ;; - vneg.v/vnot.v
3653 ;; -------------------------------------------------------------------------------
3655 (define_insn "@pred_<optab><mode>"
3656 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,vd, vr, vr")
3657 (if_then_else:V_VLSI
3658 (unspec:<VM>
3659 [(match_operand:<VM> 1 "vector_mask_operand" "vm,vm,Wc1,Wc1")
3660 (match_operand 4 "vector_length_operand" "rK,rK, rK, rK")
3661 (match_operand 5 "const_int_operand" " i, i, i, i")
3662 (match_operand 6 "const_int_operand" " i, i, i, i")
3663 (match_operand 7 "const_int_operand" " i, i, i, i")
3664 (reg:SI VL_REGNUM)
3665 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3666 (any_int_unop:V_VLSI
3667 (match_operand:V_VLSI 3 "register_operand" "vr,vr, vr, vr"))
3668 (match_operand:V_VLSI 2 "vector_merge_operand" "vu, 0, vu, 0")))]
3669 "TARGET_VECTOR"
3670 "v<insn>.v\t%0,%3%p1"
3671 [(set_attr "type" "vialu")
3672 (set_attr "mode" "<MODE>")
3673 (set_attr "vl_op_idx" "4")
3674 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3675 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3676 (set (attr "avl_type_idx") (const_int 7))])
3678 ;; -------------------------------------------------------------------------------
3679 ;; ---- Predicated integer widening binary operations
3680 ;; -------------------------------------------------------------------------------
3681 ;; Includes:
3682 ;; - 11.2 Vector Widening Integer Add/Subtract
3683 ;; - 11.3 Vector Integer Extension
3684 ;; - 11.12 Vector Widening Integer Multiply Instructions
3685 ;; -------------------------------------------------------------------------------
3687 ;; Vector Double-Widening Sign-extend and Zero-extend.
3688 (define_insn "@pred_<optab><mode>_vf2"
3689 [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
3690 (if_then_else:VWEXTI
3691 (unspec:<VM>
3692 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
3693 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
3694 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
3695 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
3696 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
3697 (reg:SI VL_REGNUM)
3698 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3699 (any_extend:VWEXTI
3700 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
3701 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
3702 "TARGET_VECTOR"
3703 "v<sz>ext.vf2\t%0,%3%p1"
3704 [(set_attr "type" "vext")
3705 (set_attr "mode" "<MODE>")
3706 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
3708 ;; Vector Quad-Widening Sign-extend and Zero-extend.
3709 (define_insn "@pred_<optab><mode>_vf4"
3710 [(set (match_operand:VQEXTI 0 "register_operand" "=vr, vr, vr, vr, ?&vr, ?&vr")
3711 (if_then_else:VQEXTI
3712 (unspec:<VM>
3713 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
3714 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3715 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
3716 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3717 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3718 (reg:SI VL_REGNUM)
3719 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3720 (any_extend:VQEXTI
3721 (match_operand:<V_QUAD_TRUNC> 3 "register_operand" " W43, W43, W86, W86, vr, vr"))
3722 (match_operand:VQEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
3723 "TARGET_VECTOR"
3724 "v<sz>ext.vf4\t%0,%3%p1"
3725 [(set_attr "type" "vext")
3726 (set_attr "mode" "<MODE>")
3727 (set_attr "group_overlap" "W43,W43,W86,W86,none,none")])
3729 ;; Vector Oct-Widening Sign-extend and Zero-extend.
3730 (define_insn "@pred_<optab><mode>_vf8"
3731 [(set (match_operand:VOEXTI 0 "register_operand" "=vr, vr, ?&vr, ?&vr")
3732 (if_then_else:VOEXTI
3733 (unspec:<VM>
3734 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
3735 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
3736 (match_operand 5 "const_int_operand" " i, i, i, i")
3737 (match_operand 6 "const_int_operand" " i, i, i, i")
3738 (match_operand 7 "const_int_operand" " i, i, i, i")
3739 (reg:SI VL_REGNUM)
3740 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3741 (any_extend:VOEXTI
3742 (match_operand:<V_OCT_TRUNC> 3 "register_operand" " W87, W87, vr, vr"))
3743 (match_operand:VOEXTI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
3744 "TARGET_VECTOR"
3745 "v<sz>ext.vf8\t%0,%3%p1"
3746 [(set_attr "type" "vext")
3747 (set_attr "mode" "<MODE>")
3748 (set_attr "group_overlap" "W87,W87,none,none")])
3750 ;; Vector Widening Add/Subtract/Multiply.
3751 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
3752 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3753 (if_then_else:VWEXTI
3754 (unspec:<VM>
3755 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3756 (match_operand 5 "vector_length_operand" " rK, rK")
3757 (match_operand 6 "const_int_operand" " i, i")
3758 (match_operand 7 "const_int_operand" " i, i")
3759 (match_operand 8 "const_int_operand" " i, i")
3760 (reg:SI VL_REGNUM)
3761 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3762 (any_widen_binop:VWEXTI
3763 (any_extend:VWEXTI
3764 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3765 (any_extend:VWEXTI
3766 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3767 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3768 "TARGET_VECTOR"
3769 "vw<any_widen_binop:insn><any_extend:u>.vv\t%0,%3,%4%p1"
3770 [(set_attr "type" "vi<widen_binop_insn_type>")
3771 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3773 (define_insn "@pred_dual_widen_<any_widen_binop:optab><any_extend:su><mode>_scalar"
3774 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3775 (if_then_else:VWEXTI
3776 (unspec:<VM>
3777 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3778 (match_operand 5 "vector_length_operand" " rK, rK")
3779 (match_operand 6 "const_int_operand" " i, i")
3780 (match_operand 7 "const_int_operand" " i, i")
3781 (match_operand 8 "const_int_operand" " i, i")
3782 (reg:SI VL_REGNUM)
3783 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3784 (any_widen_binop:VWEXTI
3785 (any_extend:VWEXTI
3786 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3787 (any_extend:VWEXTI
3788 (vec_duplicate:<V_DOUBLE_TRUNC>
3789 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3790 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3791 "TARGET_VECTOR"
3792 "vw<any_widen_binop:insn><any_extend:u>.vx\t%0,%3,%z4%p1"
3793 [(set_attr "type" "vi<widen_binop_insn_type>")
3794 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3796 (define_insn "@pred_single_widen_sub<any_extend:su><mode>"
3797 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3798 (if_then_else:VWEXTI
3799 (unspec:<VM>
3800 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3801 (match_operand 5 "vector_length_operand" " rK, rK")
3802 (match_operand 6 "const_int_operand" " i, i")
3803 (match_operand 7 "const_int_operand" " i, i")
3804 (match_operand 8 "const_int_operand" " i, i")
3805 (reg:SI VL_REGNUM)
3806 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3807 (minus:VWEXTI
3808 (match_operand:VWEXTI 3 "register_operand" " vr, vr")
3809 (any_extend:VWEXTI
3810 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3811 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3812 "TARGET_VECTOR"
3813 "vwsub<any_extend:u>.wv\t%0,%3,%4%p1"
3814 [(set_attr "type" "viwalu")
3815 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3817 (define_insn "@pred_single_widen_add<any_extend:su><mode>"
3818 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3819 (if_then_else:VWEXTI
3820 (unspec:<VM>
3821 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3822 (match_operand 5 "vector_length_operand" " rK, rK")
3823 (match_operand 6 "const_int_operand" " i, i")
3824 (match_operand 7 "const_int_operand" " i, i")
3825 (match_operand 8 "const_int_operand" " i, i")
3826 (reg:SI VL_REGNUM)
3827 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3828 (plus:VWEXTI
3829 (any_extend:VWEXTI
3830 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
3831 (match_operand:VWEXTI 3 "register_operand" " vr, vr"))
3832 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3833 "TARGET_VECTOR"
3834 "vwadd<any_extend:u>.wv\t%0,%3,%4%p1"
3835 [(set_attr "type" "viwalu")
3836 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3838 (define_insn "@pred_single_widen_<plus_minus:optab><any_extend:su><mode>_scalar"
3839 [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr")
3840 (if_then_else:VWEXTI
3841 (unspec:<VM>
3842 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3843 (match_operand 5 "vector_length_operand" " rK, rK")
3844 (match_operand 6 "const_int_operand" " i, i")
3845 (match_operand 7 "const_int_operand" " i, i")
3846 (match_operand 8 "const_int_operand" " i, i")
3847 (reg:SI VL_REGNUM)
3848 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3849 (plus_minus:VWEXTI
3850 (match_operand:VWEXTI 3 "register_operand" " vr, vr")
3851 (any_extend:VWEXTI
3852 (vec_duplicate:<V_DOUBLE_TRUNC>
3853 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3854 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3855 "TARGET_VECTOR"
3856 "vw<plus_minus:insn><any_extend:u>.wx\t%0,%3,%z4%p1"
3857 [(set_attr "type" "vi<widen_binop_insn_type>")
3858 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3860 (define_insn "@pred_widen_mulsu<mode>"
3861 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3862 (if_then_else:VWEXTI
3863 (unspec:<VM>
3864 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3865 (match_operand 5 "vector_length_operand" " rK, rK")
3866 (match_operand 6 "const_int_operand" " i, i")
3867 (match_operand 7 "const_int_operand" " i, i")
3868 (match_operand 8 "const_int_operand" " i, i")
3869 (reg:SI VL_REGNUM)
3870 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3871 (mult:VWEXTI
3872 (sign_extend:VWEXTI
3873 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3874 (zero_extend:VWEXTI
3875 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
3876 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3877 "TARGET_VECTOR"
3878 "vwmulsu.vv\t%0,%3,%4%p1"
3879 [(set_attr "type" "viwmul")
3880 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3882 (define_insn "@pred_widen_mulsu<mode>_scalar"
3883 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
3884 (if_then_else:VWEXTI
3885 (unspec:<VM>
3886 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
3887 (match_operand 5 "vector_length_operand" " rK, rK")
3888 (match_operand 6 "const_int_operand" " i, i")
3889 (match_operand 7 "const_int_operand" " i, i")
3890 (match_operand 8 "const_int_operand" " i, i")
3891 (reg:SI VL_REGNUM)
3892 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3893 (mult:VWEXTI
3894 (sign_extend:VWEXTI
3895 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
3896 (zero_extend:VWEXTI
3897 (vec_duplicate:<V_DOUBLE_TRUNC>
3898 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ"))))
3899 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
3900 "TARGET_VECTOR"
3901 "vwmulsu.vx\t%0,%3,%z4%p1"
3902 [(set_attr "type" "viwmul")
3903 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3905 ;; vwcvt<u>.x.x.v
3906 (define_insn "@pred_<optab><mode>"
3907 [(set (match_operand:VWEXTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
3908 (if_then_else:VWEXTI
3909 (unspec:<VM>
3910 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
3911 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
3912 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
3913 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
3914 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
3915 (reg:SI VL_REGNUM)
3916 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3917 (plus:VWEXTI
3918 (any_extend:VWEXTI
3919 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
3920 (vec_duplicate:VWEXTI
3921 (reg:<VEL> X0_REGNUM)))
3922 (match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
3923 "TARGET_VECTOR"
3924 "vwcvt<u>.x.x.v\t%0,%3%p1"
3925 [(set_attr "type" "viwalu")
3926 (set_attr "mode" "<V_DOUBLE_TRUNC>")
3927 (set_attr "vl_op_idx" "4")
3928 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
3929 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
3930 (set (attr "avl_type_idx") (const_int 7))
3931 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
3933 ;; -------------------------------------------------------------------------------
3934 ;; ---- Predicated integer Narrowing operations
3935 ;; -------------------------------------------------------------------------------
3936 ;; Includes:
3937 ;; - 11.7 Vector Narrowing Integer Right Shift Instructions
3938 ;; -------------------------------------------------------------------------------
3940 ;; The destination EEW is smaller than the source EEW and the overlap is in the
3941 ;; lowest-numbered part of the source register group
3942 ;; e.g, when LMUL = 1, vnsrl.wi v0,v0,3 is legal but a destination of v1 is not.
3943 (define_insn "@pred_narrow_<optab><mode>"
3944 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
3945 (if_then_else:<V_DOUBLE_TRUNC>
3946 (unspec:<VM>
3947 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
3948 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
3949 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3950 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3951 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
3952 (reg:SI VL_REGNUM)
3953 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3954 (truncate:<V_DOUBLE_TRUNC>
3955 (any_shiftrt:VWEXTI
3956 (match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
3957 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")))
3958 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
3959 "TARGET_VECTOR"
3960 "vn<insn>.w%o4\t%0,%3,%v4%p1"
3961 [(set_attr "type" "vnshift")
3962 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3964 (define_insn "@pred_narrow_<optab><mode>_scalar"
3965 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
3966 (if_then_else:<V_DOUBLE_TRUNC>
3967 (unspec:<VM>
3968 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
3969 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3970 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3971 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3972 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
3973 (reg:SI VL_REGNUM)
3974 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3975 (truncate:<V_DOUBLE_TRUNC>
3976 (any_shiftrt:VWEXTI
3977 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
3978 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")))
3979 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
3980 "TARGET_VECTOR"
3981 "vn<insn>.w%o4\t%0,%3,%4%p1"
3982 [(set_attr "type" "vnshift")
3983 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
3985 ;; vncvt.x.x.w
3986 (define_insn "@pred_trunc<mode>"
3987 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
3988 (if_then_else:<V_DOUBLE_TRUNC>
3989 (unspec:<VM>
3990 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
3991 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
3992 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
3993 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
3994 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
3995 (reg:SI VL_REGNUM)
3996 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
3997 (truncate:<V_DOUBLE_TRUNC>
3998 (match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
3999 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4000 "TARGET_VECTOR"
4001 "vncvt.x.x.w\t%0,%3%p1"
4002 [(set_attr "type" "vnshift")
4003 (set_attr "mode" "<V_DOUBLE_TRUNC>")
4004 (set_attr "vl_op_idx" "4")
4005 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
4006 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4007 (set (attr "avl_type_idx") (const_int 7))])
4009 ;; -------------------------------------------------------------------------------
4010 ;; ---- Predicated fixed-point operations
4011 ;; -------------------------------------------------------------------------------
4012 ;; Includes:
4013 ;; - 12.1 Vector Single-Width Saturating Add and Subtract
4014 ;; - 12.2 Vector Single-Width Aaveraging Add and Subtract
4015 ;; - 12.3 Vector Single-Width Fractional Multiply with Rounding and Saturation
4016 ;; - 12.4 Vector Single-Width Scaling Shift Instructions
4017 ;; - 12.5 Vector Narrowing Fixed-Point Clip Instructions
4018 ;; -------------------------------------------------------------------------------
4020 ;; Saturating Add and Subtract
4021 (define_insn "@pred_<optab><mode>"
4022 [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr, vd, vd, vr, vr")
4023 (if_then_else:VI
4024 (unspec:<VM>
4025 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1, vm, vm,Wc1,Wc1")
4026 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
4027 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
4028 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
4029 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
4030 (reg:SI VL_REGNUM)
4031 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4032 (any_sat_int_binop:VI
4033 (match_operand:VI 3 "<binop_rhs1_predicate>" " vr, vr, vr, vr, vr, vr, vr, vr")
4034 (match_operand:VI 4 "<binop_rhs2_predicate>" "<binop_rhs2_constraint>"))
4035 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
4036 "TARGET_VECTOR"
4037 "@
4038 v<insn>.vv\t%0,%3,%4%p1
4039 v<insn>.vv\t%0,%3,%4%p1
4040 v<insn>.vv\t%0,%3,%4%p1
4041 v<insn>.vv\t%0,%3,%4%p1
4042 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4043 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4044 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1
4045 v<binop_vi_variant_insn>\t%0,<binop_vi_variant_op>%p1"
4046 [(set_attr "type" "<int_binop_insn_type>")
4047 (set_attr "mode" "<MODE>")])
4049 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4050 (define_insn "@pred_<optab><mode>_scalar"
4051 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4052 (if_then_else:VI_QHS
4053 (unspec:<VM>
4054 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4055 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4056 (match_operand 6 "const_int_operand" " i, i, i, i")
4057 (match_operand 7 "const_int_operand" " i, i, i, i")
4058 (match_operand 8 "const_int_operand" " i, i, i, i")
4059 (reg:SI VL_REGNUM)
4060 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4061 (sat_int_plus_binop:VI_QHS
4062 (vec_duplicate:VI_QHS
4063 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4064 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr"))
4065 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4066 "TARGET_VECTOR"
4067 "v<insn>.vx\t%0,%3,%4%p1"
4068 [(set_attr "type" "<int_binop_insn_type>")
4069 (set_attr "mode" "<MODE>")])
4071 (define_insn "@pred_<optab><mode>_scalar"
4072 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vd, vr, vr")
4073 (if_then_else:VI_QHS
4074 (unspec:<VM>
4075 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4076 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4077 (match_operand 6 "const_int_operand" " i, i, i, i")
4078 (match_operand 7 "const_int_operand" " i, i, i, i")
4079 (match_operand 8 "const_int_operand" " i, i, i, i")
4080 (reg:SI VL_REGNUM)
4081 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4082 (sat_int_minus_binop:VI_QHS
4083 (match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4084 (vec_duplicate:VI_QHS
4085 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4086 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4087 "TARGET_VECTOR"
4088 "v<insn>.vx\t%0,%3,%4%p1"
4089 [(set_attr "type" "<int_binop_insn_type>")
4090 (set_attr "mode" "<MODE>")])
4092 (define_expand "@pred_<optab><mode>_scalar"
4093 [(set (match_operand:VI_D 0 "register_operand")
4094 (if_then_else:VI_D
4095 (unspec:<VM>
4096 [(match_operand:<VM> 1 "vector_mask_operand")
4097 (match_operand 5 "vector_length_operand")
4098 (match_operand 6 "const_int_operand")
4099 (match_operand 7 "const_int_operand")
4100 (match_operand 8 "const_int_operand")
4101 (reg:SI VL_REGNUM)
4102 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4103 (sat_int_plus_binop:VI_D
4104 (vec_duplicate:VI_D
4105 (match_operand:<VEL> 4 "reg_or_int_operand"))
4106 (match_operand:VI_D 3 "register_operand"))
4107 (match_operand:VI_D 2 "vector_merge_operand")))]
4108 "TARGET_VECTOR"
4109 {
4110 if (riscv_vector::sew64_scalar_helper (
4111 operands,
4112 /* scalar op */&operands[4],
4113 /* vl */operands[5],
4114 <MODE>mode,
4115 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4116 [] (rtx *operands, rtx boardcast_scalar) {
4117 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4118 operands[2], operands[3], boardcast_scalar, operands[5],
4119 operands[6], operands[7], operands[8]));
4120 },
4121 (riscv_vector::avl_type) INTVAL (operands[8])))
4122 DONE;
4123 })
4125 (define_insn "*pred_<optab><mode>_scalar"
4126 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4127 (if_then_else:VI_D
4128 (unspec:<VM>
4129 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4130 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4131 (match_operand 6 "const_int_operand" " i, i, i, i")
4132 (match_operand 7 "const_int_operand" " i, i, i, i")
4133 (match_operand 8 "const_int_operand" " i, i, i, i")
4134 (reg:SI VL_REGNUM)
4135 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4136 (sat_int_plus_binop:VI_D
4137 (vec_duplicate:VI_D
4138 (match_operand:<VEL> 4 "register_operand" " r, r, r, r"))
4139 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4140 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4141 "TARGET_VECTOR"
4142 "v<insn>.vx\t%0,%3,%4%p1"
4143 [(set_attr "type" "<int_binop_insn_type>")
4144 (set_attr "mode" "<MODE>")])
4146 (define_insn "*pred_<optab><mode>_extended_scalar"
4147 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4148 (if_then_else:VI_D
4149 (unspec:<VM>
4150 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4151 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4152 (match_operand 6 "const_int_operand" " i, i, i, i")
4153 (match_operand 7 "const_int_operand" " i, i, i, i")
4154 (match_operand 8 "const_int_operand" " i, i, i, i")
4155 (reg:SI VL_REGNUM)
4156 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4157 (sat_int_plus_binop:VI_D
4158 (vec_duplicate:VI_D
4159 (sign_extend:<VEL>
4160 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r")))
4161 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr"))
4162 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4163 "TARGET_VECTOR"
4164 "v<insn>.vx\t%0,%3,%4%p1"
4165 [(set_attr "type" "<int_binop_insn_type>")
4166 (set_attr "mode" "<MODE>")])
4168 (define_expand "@pred_<optab><mode>_scalar"
4169 [(set (match_operand:VI_D 0 "register_operand")
4170 (if_then_else:VI_D
4171 (unspec:<VM>
4172 [(match_operand:<VM> 1 "vector_mask_operand")
4173 (match_operand 5 "vector_length_operand")
4174 (match_operand 6 "const_int_operand")
4175 (match_operand 7 "const_int_operand")
4176 (match_operand 8 "const_int_operand")
4177 (reg:SI VL_REGNUM)
4178 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4179 (sat_int_minus_binop:VI_D
4180 (match_operand:VI_D 3 "register_operand")
4181 (vec_duplicate:VI_D
4182 (match_operand:<VEL> 4 "reg_or_int_operand")))
4183 (match_operand:VI_D 2 "vector_merge_operand")))]
4184 "TARGET_VECTOR"
4185 {
4186 if (riscv_vector::sew64_scalar_helper (
4187 operands,
4188 /* scalar op */&operands[4],
4189 /* vl */operands[5],
4190 <MODE>mode,
4191 riscv_vector::has_vi_variant_p (<CODE>, operands[4]),
4192 [] (rtx *operands, rtx boardcast_scalar) {
4193 emit_insn (gen_pred_<optab><mode> (operands[0], operands[1],
4194 operands[2], operands[3], boardcast_scalar, operands[5],
4195 operands[6], operands[7], operands[8]));
4196 },
4197 (riscv_vector::avl_type) INTVAL (operands[8])))
4198 DONE;
4199 })
4201 (define_insn "*pred_<optab><mode>_scalar"
4202 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4203 (if_then_else:VI_D
4204 (unspec:<VM>
4205 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4206 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4207 (match_operand 6 "const_int_operand" " i, i, i, i")
4208 (match_operand 7 "const_int_operand" " i, i, i, i")
4209 (match_operand 8 "const_int_operand" " i, i, i, i")
4210 (reg:SI VL_REGNUM)
4211 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4212 (sat_int_minus_binop:VI_D
4213 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4214 (vec_duplicate:VI_D
4215 (match_operand:<VEL> 4 "register_operand" " r, r, r, r")))
4216 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4217 "TARGET_VECTOR"
4218 "v<insn>.vx\t%0,%3,%4%p1"
4219 [(set_attr "type" "<int_binop_insn_type>")
4220 (set_attr "mode" "<MODE>")])
4222 (define_insn "*pred_<optab><mode>_extended_scalar"
4223 [(set (match_operand:VI_D 0 "register_operand" "=vd, vd, vr, vr")
4224 (if_then_else:VI_D
4225 (unspec:<VM>
4226 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4227 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4228 (match_operand 6 "const_int_operand" " i, i, i, i")
4229 (match_operand 7 "const_int_operand" " i, i, i, i")
4230 (match_operand 8 "const_int_operand" " i, i, i, i")
4231 (reg:SI VL_REGNUM)
4232 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4233 (sat_int_minus_binop:VI_D
4234 (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4235 (vec_duplicate:VI_D
4236 (sign_extend:<VEL>
4237 (match_operand:<VSUBEL> 4 "register_operand" " r, r, r, r"))))
4238 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4239 "TARGET_VECTOR"
4240 "v<insn>.vx\t%0,%3,%4%p1"
4241 [(set_attr "type" "<int_binop_insn_type>")
4242 (set_attr "mode" "<MODE>")])
4244 (define_insn "@pred_<sat_op><mode>"
4245 [(set (match_operand:VI 0 "register_operand" "=vd, vd, vr, vr")
4246 (if_then_else:VI
4247 (unspec:<VM>
4248 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4249 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4250 (match_operand 6 "const_int_operand" " i, i, i, i")
4251 (match_operand 7 "const_int_operand" " i, i, i, i")
4252 (match_operand 8 "const_int_operand" " i, i, i, i")
4253 (match_operand 9 "const_int_operand" " i, i, i, i")
4254 (reg:SI VL_REGNUM)
4255 (reg:SI VTYPE_REGNUM)
4256 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4257 (unspec:VI
4258 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4259 (match_operand:VI 4 "register_operand" " vr, vr, vr, vr")] VSAT_OP)
4260 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4261 "TARGET_VECTOR"
4262 "v<sat_op>.vv\t%0,%3,%4%p1"
4263 [(set_attr "type" "<sat_insn_type>")
4264 (set_attr "mode" "<MODE>")])
4266 ;; Handle GET_MODE_INNER (mode) = QImode, HImode, SImode.
4267 (define_insn "@pred_<sat_op><mode>_scalar"
4268 [(set (match_operand:VI_QHS 0 "register_operand" "=vd, vr, vd, vr")
4269 (if_then_else:VI_QHS
4270 (unspec:<VM>
4271 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4272 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4273 (match_operand 6 "const_int_operand" " i, i, i, i")
4274 (match_operand 7 "const_int_operand" " i, i, i, i")
4275 (match_operand 8 "const_int_operand" " i, i, i, i")
4276 (match_operand 9 "const_int_operand" " i, i, i, i")
4277 (reg:SI VL_REGNUM)
4278 (reg:SI VTYPE_REGNUM)
4279 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4280 (unspec:VI_QHS
4281 [(match_operand:VI_QHS 3 "register_operand" " vr, vr, vr, vr")
4282 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4283 (match_operand:VI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4284 "TARGET_VECTOR"
4285 "v<sat_op>.vx\t%0,%3,%z4%p1"
4286 [(set_attr "type" "<sat_insn_type>")
4287 (set_attr "mode" "<MODE>")])
4289 (define_insn "@pred_<sat_op><mode>_scalar"
4290 [(set (match_operand:VI 0 "register_operand" "=vd, vr, vd, vr")
4291 (if_then_else:VI
4292 (unspec:<VM>
4293 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4294 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4295 (match_operand 6 "const_int_operand" " i, i, i, i")
4296 (match_operand 7 "const_int_operand" " i, i, i, i")
4297 (match_operand 8 "const_int_operand" " i, i, i, i")
4298 (match_operand 9 "const_int_operand" " i, i, i, i")
4299 (reg:SI VL_REGNUM)
4300 (reg:SI VTYPE_REGNUM)
4301 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4302 (unspec:VI
4303 [(match_operand:VI 3 "register_operand" " vr, vr, vr, vr")
4304 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSAT_SHIFT_OP)
4305 (match_operand:VI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4306 "TARGET_VECTOR"
4307 "v<sat_op>.v%o4\t%0,%3,%4%p1"
4308 [(set_attr "type" "<sat_insn_type>")
4309 (set_attr "mode" "<MODE>")])
4311 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4312 ;; we need to deal with SEW = 64 in RV32 system.
4313 (define_expand "@pred_<sat_op><mode>_scalar"
4314 [(set (match_operand:VI_D 0 "register_operand")
4315 (if_then_else:VI_D
4316 (unspec:<VM>
4317 [(match_operand:<VM> 1 "vector_mask_operand")
4318 (match_operand 5 "vector_length_operand")
4319 (match_operand 6 "const_int_operand")
4320 (match_operand 7 "const_int_operand")
4321 (match_operand 8 "const_int_operand")
4322 (match_operand 9 "const_int_operand")
4323 (reg:SI VL_REGNUM)
4324 (reg:SI VTYPE_REGNUM)
4325 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4326 (unspec:VI_D
4327 [(match_operand:VI_D 3 "register_operand")
4328 (match_operand:<VEL> 4 "reg_or_int_operand")] VSAT_ARITH_OP)
4329 (match_operand:VI_D 2 "vector_merge_operand")))]
4330 "TARGET_VECTOR"
4331 {
4332 if (riscv_vector::sew64_scalar_helper (
4333 operands,
4334 /* scalar op */&operands[4],
4335 /* vl */operands[5],
4336 <MODE>mode,
4337 false,
4338 [] (rtx *operands, rtx boardcast_scalar) {
4339 emit_insn (gen_pred_<sat_op><mode> (operands[0], operands[1],
4340 operands[2], operands[3], boardcast_scalar, operands[5],
4341 operands[6], operands[7], operands[8], operands[9]));
4342 },
4343 (riscv_vector::avl_type) INTVAL (operands[8])))
4344 DONE;
4345 })
4347 (define_insn "*pred_<sat_op><mode>_scalar"
4348 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4349 (if_then_else:VI_D
4350 (unspec:<VM>
4351 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4352 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4353 (match_operand 6 "const_int_operand" " i, i, i, i")
4354 (match_operand 7 "const_int_operand" " i, i, i, i")
4355 (match_operand 8 "const_int_operand" " i, i, i, i")
4356 (match_operand 9 "const_int_operand" " i, i, i, i")
4357 (reg:SI VL_REGNUM)
4358 (reg:SI VTYPE_REGNUM)
4359 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4360 (unspec:VI_D
4361 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4362 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSAT_ARITH_OP)
4363 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4364 "TARGET_VECTOR"
4365 "v<sat_op>.vx\t%0,%3,%z4%p1"
4366 [(set_attr "type" "<sat_insn_type>")
4367 (set_attr "mode" "<MODE>")])
4369 (define_insn "*pred_<sat_op><mode>_extended_scalar"
4370 [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, vd, vr")
4371 (if_then_else:VI_D
4372 (unspec:<VM>
4373 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
4374 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
4375 (match_operand 6 "const_int_operand" " i, i, i, i")
4376 (match_operand 7 "const_int_operand" " i, i, i, i")
4377 (match_operand 8 "const_int_operand" " i, i, i, i")
4378 (match_operand 9 "const_int_operand" " i, i, i, i")
4379 (reg:SI VL_REGNUM)
4380 (reg:SI VTYPE_REGNUM)
4381 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4382 (unspec:VI_D
4383 [(match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
4384 (sign_extend:<VEL>
4385 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSAT_ARITH_OP)
4386 (match_operand:VI_D 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4387 "TARGET_VECTOR"
4388 "v<sat_op>.vx\t%0,%3,%z4%p1"
4389 [(set_attr "type" "<sat_insn_type>")
4390 (set_attr "mode" "<MODE>")])
4392 ;; CLIP
4393 (define_insn "@pred_narrow_clip<v_su><mode>"
4394 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd,vd, vr, vr,vd, vr, &vr, &vr, vd, vr, &vr, &vr")
4395 (if_then_else:<V_DOUBLE_TRUNC>
4396 (unspec:<VM>
4397 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm,Wc1,Wc1,vm,Wc1,vmWc1,vmWc1, vm,Wc1,vmWc1,vmWc1")
4398 (match_operand 5 "vector_length_operand" " rK,rK, rK, rK,rK, rK, rK, rK, rK, rK, rK, rK")
4399 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4400 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4401 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4402 (match_operand 9 "const_int_operand" " i, i, i, i, i, i, i, i, i, i, i, i")
4403 (reg:SI VL_REGNUM)
4404 (reg:SI VTYPE_REGNUM)
4405 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4406 (unspec:<V_DOUBLE_TRUNC>
4407 [(match_operand:VWEXTI 3 "register_operand" " vr,vr, vr, vr, 0, 0, vr, vr, 0, 0, vr, vr")
4408 (match_operand:<V_DOUBLE_TRUNC> 4 "vector_shift_operand" " 0, 0, 0, 0,vr, vr, vr, vr, vk, vk, vk, vk")] VNCLIP)
4409 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " 0,vu, 0, vu,vu, vu, vu, 0, vu, vu, vu, 0")))]
4410 "TARGET_VECTOR"
4411 "vnclip<v_su>.w%o4\t%0,%3,%v4%p1"
4412 [(set_attr "type" "vnclip")
4413 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4415 (define_insn "@pred_narrow_clip<v_su><mode>_scalar"
4416 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
4417 (if_then_else:<V_DOUBLE_TRUNC>
4418 (unspec:<VM>
4419 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
4420 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
4421 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
4422 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
4423 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
4424 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
4425 (reg:SI VL_REGNUM)
4426 (reg:SI VTYPE_REGNUM)
4427 (reg:SI VXRM_REGNUM)] UNSPEC_VPREDICATE)
4428 (unspec:<V_DOUBLE_TRUNC>
4429 [(match_operand:VWEXTI 3 "register_operand" " 0, 0, 0, 0, vr, vr")
4430 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK, rK, rK")] VNCLIP)
4431 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
4432 "TARGET_VECTOR"
4433 "vnclip<v_su>.w%o4\t%0,%3,%4%p1"
4434 [(set_attr "type" "vnclip")
4435 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
4437 ;; -------------------------------------------------------------------------------
4438 ;; ---- Predicated integer comparison operations
4439 ;; -------------------------------------------------------------------------------
4440 ;; Includes:
4441 ;; - 11.8 Vector Integer Comparision Instructions
4442 ;; -------------------------------------------------------------------------------
4444 (define_expand "@pred_cmp<mode>"
4445 [(set (match_operand:<VM> 0 "register_operand")
4446 (if_then_else:<VM>
4447 (unspec:<VM>
4448 [(match_operand:<VM> 1 "vector_mask_operand")
4449 (match_operand 6 "vector_length_operand")
4450 (match_operand 7 "const_int_operand")
4451 (match_operand 8 "const_int_operand")
4452 (reg:SI VL_REGNUM)
4453 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4454 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4455 [(match_operand:V_VLSI 4 "register_operand")
4456 (match_operand:V_VLSI 5 "vector_arith_operand")])
4457 (match_operand:<VM> 2 "vector_merge_operand")))]
4458 "TARGET_VECTOR"
4459 {})
4461 (define_insn "*pred_cmp<mode>_merge_tie_mask"
4462 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4463 (if_then_else:<VM>
4464 (unspec:<VM>
4465 [(match_operand:<VM> 1 "register_operand" " 0")
4466 (match_operand 5 "vector_length_operand" " rK")
4467 (match_operand 6 "const_int_operand" " i")
4468 (match_operand 7 "const_int_operand" " i")
4469 (reg:SI VL_REGNUM)
4470 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4471 (match_operator:<VM> 2 "comparison_except_ltge_operator"
4472 [(match_operand:V_VLSI 3 "register_operand" " vr")
4473 (match_operand:V_VLSI 4 "vector_arith_operand" "vrvi")])
4474 (match_dup 1)))]
4475 "TARGET_VECTOR"
4476 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4477 [(set_attr "type" "vicmp")
4478 (set_attr "mode" "<MODE>")
4479 (set_attr "merge_op_idx" "1")
4480 (set_attr "vl_op_idx" "5")
4481 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4482 (set (attr "avl_type_idx") (const_int 7))])
4484 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4485 (define_insn "*pred_cmp<mode>"
4486 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr")
4487 (if_then_else:<VM>
4488 (unspec:<VM>
4489 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4490 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4491 (match_operand 7 "const_int_operand" " i, i, i, i")
4492 (match_operand 8 "const_int_operand" " i, i, i, i")
4493 (reg:SI VL_REGNUM)
4494 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4495 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4496 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
4497 (match_operand:V_VLSI 5 "vector_arith_operand" " vr, vr, vi, vi")])
4498 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4499 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4500 "vms%B3.v%o5\t%0,%4,%v5%p1"
4501 [(set_attr "type" "vicmp")
4502 (set_attr "mode" "<MODE>")])
4504 ;; We use early-clobber for source LMUL > dest LMUL.
4505 (define_insn "*pred_cmp<mode>_narrow"
4506 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4507 (if_then_else:<VM>
4508 (unspec:<VM>
4509 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4510 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4511 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4512 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4513 (reg:SI VL_REGNUM)
4514 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4515 (match_operator:<VM> 3 "comparison_except_ltge_operator"
4516 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4517 (match_operand:V_VLSI 5 "vector_arith_operand" " vrvi, vrvi, 0, 0, vrvi, 0, 0, vrvi, vrvi")])
4518 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4519 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4520 "vms%B3.v%o5\t%0,%4,%v5%p1"
4521 [(set_attr "type" "vicmp")
4522 (set_attr "mode" "<MODE>")])
4524 (define_expand "@pred_ltge<mode>"
4525 [(set (match_operand:<VM> 0 "register_operand")
4526 (if_then_else:<VM>
4527 (unspec:<VM>
4528 [(match_operand:<VM> 1 "vector_mask_operand")
4529 (match_operand 6 "vector_length_operand")
4530 (match_operand 7 "const_int_operand")
4531 (match_operand 8 "const_int_operand")
4532 (reg:SI VL_REGNUM)
4533 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4534 (match_operator:<VM> 3 "ltge_operator"
4535 [(match_operand:V_VLSI 4 "register_operand")
4536 (match_operand:V_VLSI 5 "vector_neg_arith_operand")])
4537 (match_operand:<VM> 2 "vector_merge_operand")))]
4538 "TARGET_VECTOR"
4539 {})
4541 (define_insn "*pred_ltge<mode>_merge_tie_mask"
4542 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4543 (if_then_else:<VM>
4544 (unspec:<VM>
4545 [(match_operand:<VM> 1 "register_operand" " 0")
4546 (match_operand 5 "vector_length_operand" " rK")
4547 (match_operand 6 "const_int_operand" " i")
4548 (match_operand 7 "const_int_operand" " i")
4549 (reg:SI VL_REGNUM)
4550 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4551 (match_operator:<VM> 2 "ltge_operator"
4552 [(match_operand:V_VLSI 3 "register_operand" " vr")
4553 (match_operand:V_VLSI 4 "vector_neg_arith_operand" "vrvj")])
4554 (match_dup 1)))]
4555 "TARGET_VECTOR"
4556 "vms%B2.v%o4\t%0,%3,%v4,v0.t"
4557 [(set_attr "type" "vicmp")
4558 (set_attr "mode" "<MODE>")
4559 (set_attr "merge_op_idx" "1")
4560 (set_attr "vl_op_idx" "5")
4561 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4562 (set (attr "avl_type_idx") (const_int 7))])
4564 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4565 (define_insn "*pred_ltge<mode>"
4566 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr, vr, vr")
4567 (if_then_else:<VM>
4568 (unspec:<VM>
4569 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1")
4570 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK")
4571 (match_operand 7 "const_int_operand" " i, i, i, i")
4572 (match_operand 8 "const_int_operand" " i, i, i, i")
4573 (reg:SI VL_REGNUM)
4574 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4575 (match_operator:<VM> 3 "ltge_operator"
4576 [(match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
4577 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vr, vr, vj, vj")])
4578 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
4579 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4580 "vms%B3.v%o5\t%0,%4,%v5%p1"
4581 [(set_attr "type" "vicmp")
4582 (set_attr "mode" "<MODE>")])
4584 ;; We use early-clobber for source LMUL > dest LMUL.
4585 (define_insn "*pred_ltge<mode>_narrow"
4586 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
4587 (if_then_else:<VM>
4588 (unspec:<VM>
4589 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
4590 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
4591 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4592 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
4593 (reg:SI VL_REGNUM)
4594 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4595 (match_operator:<VM> 3 "ltge_operator"
4596 [(match_operand:V_VLSI 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
4597 (match_operand:V_VLSI 5 "vector_neg_arith_operand" " vrvj, vrvj, 0, 0, vrvj, 0, 0, vrvj, vrvj")])
4598 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
4599 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4600 "vms%B3.v%o5\t%0,%4,%v5%p1"
4601 [(set_attr "type" "vicmp")
4602 (set_attr "mode" "<MODE>")])
4604 (define_expand "@pred_cmp<mode>_scalar"
4605 [(set (match_operand:<VM> 0 "register_operand")
4606 (if_then_else:<VM>
4607 (unspec:<VM>
4608 [(match_operand:<VM> 1 "vector_mask_operand")
4609 (match_operand 6 "vector_length_operand")
4610 (match_operand 7 "const_int_operand")
4611 (match_operand 8 "const_int_operand")
4612 (reg:SI VL_REGNUM)
4613 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4614 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4615 [(match_operand:V_VLSI_QHS 4 "register_operand")
4616 (vec_duplicate:V_VLSI_QHS
4617 (match_operand:<VEL> 5 "register_operand"))])
4618 (match_operand:<VM> 2 "vector_merge_operand")))]
4619 "TARGET_VECTOR"
4620 {})
4622 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4623 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4624 (if_then_else:<VM>
4625 (unspec:<VM>
4626 [(match_operand:<VM> 1 "register_operand" " 0")
4627 (match_operand 5 "vector_length_operand" " rK")
4628 (match_operand 6 "const_int_operand" " i")
4629 (match_operand 7 "const_int_operand" " i")
4630 (reg:SI VL_REGNUM)
4631 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4632 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4633 [(match_operand:V_VLSI_QHS 3 "register_operand" " vr")
4634 (vec_duplicate:V_VLSI_QHS
4635 (match_operand:<VEL> 4 "register_operand" " r"))])
4636 (match_dup 1)))]
4637 "TARGET_VECTOR"
4638 "vms%B2.vx\t%0,%3,%4,v0.t"
4639 [(set_attr "type" "vicmp")
4640 (set_attr "mode" "<MODE>")
4641 (set_attr "merge_op_idx" "1")
4642 (set_attr "vl_op_idx" "5")
4643 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4644 (set (attr "avl_type_idx") (const_int 7))])
4646 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4647 (define_insn "*pred_cmp<mode>_scalar"
4648 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4649 (if_then_else:<VM>
4650 (unspec:<VM>
4651 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4652 (match_operand 6 "vector_length_operand" " rK, rK")
4653 (match_operand 7 "const_int_operand" " i, i")
4654 (match_operand 8 "const_int_operand" " i, i")
4655 (reg:SI VL_REGNUM)
4656 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4657 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4658 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")
4659 (vec_duplicate:V_VLSI_QHS
4660 (match_operand:<VEL> 5 "register_operand" " r, r"))])
4661 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4662 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4663 "vms%B3.vx\t%0,%4,%5%p1"
4664 [(set_attr "type" "vicmp")
4665 (set_attr "mode" "<MODE>")])
4667 ;; We use early-clobber for source LMUL > dest LMUL.
4668 (define_insn "*pred_cmp<mode>_scalar_narrow"
4669 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4670 (if_then_else:<VM>
4671 (unspec:<VM>
4672 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4673 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4674 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4675 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4676 (reg:SI VL_REGNUM)
4677 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4678 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4679 [(match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")
4680 (vec_duplicate:V_VLSI_QHS
4681 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4682 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4683 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4684 "vms%B3.vx\t%0,%4,%5%p1"
4685 [(set_attr "type" "vicmp")
4686 (set_attr "mode" "<MODE>")])
4688 (define_expand "@pred_eqne<mode>_scalar"
4689 [(set (match_operand:<VM> 0 "register_operand")
4690 (if_then_else:<VM>
4691 (unspec:<VM>
4692 [(match_operand:<VM> 1 "vector_mask_operand")
4693 (match_operand 6 "vector_length_operand")
4694 (match_operand 7 "const_int_operand")
4695 (match_operand 8 "const_int_operand")
4696 (reg:SI VL_REGNUM)
4697 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4698 (match_operator:<VM> 3 "equality_operator"
4699 [(vec_duplicate:V_VLSI_QHS
4700 (match_operand:<VEL> 5 "register_operand"))
4701 (match_operand:V_VLSI_QHS 4 "register_operand")])
4702 (match_operand:<VM> 2 "vector_merge_operand")))]
4703 "TARGET_VECTOR"
4704 {})
4706 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
4707 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4708 (if_then_else:<VM>
4709 (unspec:<VM>
4710 [(match_operand:<VM> 1 "register_operand" " 0")
4711 (match_operand 5 "vector_length_operand" " rK")
4712 (match_operand 6 "const_int_operand" " i")
4713 (match_operand 7 "const_int_operand" " i")
4714 (reg:SI VL_REGNUM)
4715 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4716 (match_operator:<VM> 2 "equality_operator"
4717 [(vec_duplicate:V_VLSI_QHS
4718 (match_operand:<VEL> 4 "register_operand" " r"))
4719 (match_operand:V_VLSI_QHS 3 "register_operand" " vr")])
4720 (match_dup 1)))]
4721 "TARGET_VECTOR"
4722 "vms%B2.vx\t%0,%3,%4,v0.t"
4723 [(set_attr "type" "vicmp")
4724 (set_attr "mode" "<MODE>")
4725 (set_attr "merge_op_idx" "1")
4726 (set_attr "vl_op_idx" "5")
4727 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4728 (set (attr "avl_type_idx") (const_int 7))])
4730 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4731 (define_insn "*pred_eqne<mode>_scalar"
4732 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4733 (if_then_else:<VM>
4734 (unspec:<VM>
4735 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4736 (match_operand 6 "vector_length_operand" " rK, rK")
4737 (match_operand 7 "const_int_operand" " i, i")
4738 (match_operand 8 "const_int_operand" " i, i")
4739 (reg:SI VL_REGNUM)
4740 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4741 (match_operator:<VM> 3 "equality_operator"
4742 [(vec_duplicate:V_VLSI_QHS
4743 (match_operand:<VEL> 5 "register_operand" " r, r"))
4744 (match_operand:V_VLSI_QHS 4 "register_operand" " vr, vr")])
4745 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4746 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4747 "vms%B3.vx\t%0,%4,%5%p1"
4748 [(set_attr "type" "vicmp")
4749 (set_attr "mode" "<MODE>")])
4751 ;; We use early-clobber for source LMUL > dest LMUL.
4752 (define_insn "*pred_eqne<mode>_scalar_narrow"
4753 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4754 (if_then_else:<VM>
4755 (unspec:<VM>
4756 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4757 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4758 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4759 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4760 (reg:SI VL_REGNUM)
4761 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4762 (match_operator:<VM> 3 "equality_operator"
4763 [(vec_duplicate:V_VLSI_QHS
4764 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
4765 (match_operand:V_VLSI_QHS 4 "register_operand" " vr, 0, 0, vr, vr")])
4766 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4767 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4768 "vms%B3.vx\t%0,%4,%5%p1"
4769 [(set_attr "type" "vicmp")
4770 (set_attr "mode" "<MODE>")])
4772 ;; Handle GET_MODE_INNER (mode) = DImode. We need to split them since
4773 ;; we need to deal with SEW = 64 in RV32 system.
4774 (define_expand "@pred_cmp<mode>_scalar"
4775 [(set (match_operand:<VM> 0 "register_operand")
4776 (if_then_else:<VM>
4777 (unspec:<VM>
4778 [(match_operand:<VM> 1 "vector_mask_operand")
4779 (match_operand 6 "vector_length_operand")
4780 (match_operand 7 "const_int_operand")
4781 (match_operand 8 "const_int_operand")
4782 (reg:SI VL_REGNUM)
4783 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4784 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4785 [(match_operand:V_VLSI_D 4 "register_operand")
4786 (vec_duplicate:V_VLSI_D
4787 (match_operand:<VEL> 5 "reg_or_int_operand"))])
4788 (match_operand:<VM> 2 "vector_merge_operand")))]
4789 "TARGET_VECTOR"
4790 {
4791 enum rtx_code code = GET_CODE (operands[3]);
4792 if (riscv_vector::sew64_scalar_helper (
4793 operands,
4794 /* scalar op */&operands[5],
4795 /* vl */operands[6],
4796 <MODE>mode,
4797 riscv_vector::has_vi_variant_p (code, operands[5]),
4798 code == LT || code == LTU ?
4799 [] (rtx *operands, rtx boardcast_scalar) {
4800 emit_insn (gen_pred_ltge<mode> (operands[0], operands[1],
4801 operands[2], operands[3], operands[4], boardcast_scalar,
4802 operands[6], operands[7], operands[8]));
4803 }
4804 :
4805 [] (rtx *operands, rtx boardcast_scalar) {
4806 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4807 operands[2], operands[3], operands[4], boardcast_scalar,
4808 operands[6], operands[7], operands[8]));
4809 },
4810 (riscv_vector::avl_type) INTVAL (operands[8])))
4811 DONE;
4812 })
4814 (define_expand "@pred_eqne<mode>_scalar"
4815 [(set (match_operand:<VM> 0 "register_operand")
4816 (if_then_else:<VM>
4817 (unspec:<VM>
4818 [(match_operand:<VM> 1 "vector_mask_operand")
4819 (match_operand 6 "vector_length_operand")
4820 (match_operand 7 "const_int_operand")
4821 (match_operand 8 "const_int_operand")
4822 (reg:SI VL_REGNUM)
4823 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4824 (match_operator:<VM> 3 "equality_operator"
4825 [(vec_duplicate:V_VLSI_D
4826 (match_operand:<VEL> 5 "reg_or_int_operand"))
4827 (match_operand:V_VLSI_D 4 "register_operand")])
4828 (match_operand:<VM> 2 "vector_merge_operand")))]
4829 "TARGET_VECTOR"
4830 {
4831 enum rtx_code code = GET_CODE (operands[3]);
4832 if (riscv_vector::sew64_scalar_helper (
4833 operands,
4834 /* scalar op */&operands[5],
4835 /* vl */operands[6],
4836 <MODE>mode,
4837 riscv_vector::has_vi_variant_p (code, operands[5]),
4838 [] (rtx *operands, rtx boardcast_scalar) {
4839 emit_insn (gen_pred_cmp<mode> (operands[0], operands[1],
4840 operands[2], operands[3], operands[4], boardcast_scalar,
4841 operands[6], operands[7], operands[8]));
4842 },
4843 (riscv_vector::avl_type) INTVAL (operands[8])))
4844 DONE;
4845 })
4847 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
4848 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4849 (if_then_else:<VM>
4850 (unspec:<VM>
4851 [(match_operand:<VM> 1 "register_operand" " 0")
4852 (match_operand 5 "vector_length_operand" " rK")
4853 (match_operand 6 "const_int_operand" " i")
4854 (match_operand 7 "const_int_operand" " i")
4855 (reg:SI VL_REGNUM)
4856 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4857 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4858 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
4859 (vec_duplicate:V_VLSI_D
4860 (match_operand:<VEL> 4 "register_operand" " r"))])
4861 (match_dup 1)))]
4862 "TARGET_VECTOR"
4863 "vms%B2.vx\t%0,%3,%4,v0.t"
4864 [(set_attr "type" "vicmp")
4865 (set_attr "mode" "<MODE>")
4866 (set_attr "merge_op_idx" "1")
4867 (set_attr "vl_op_idx" "5")
4868 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4869 (set (attr "avl_type_idx") (const_int 7))])
4871 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
4872 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4873 (if_then_else:<VM>
4874 (unspec:<VM>
4875 [(match_operand:<VM> 1 "register_operand" " 0")
4876 (match_operand 5 "vector_length_operand" " rK")
4877 (match_operand 6 "const_int_operand" " i")
4878 (match_operand 7 "const_int_operand" " i")
4879 (reg:SI VL_REGNUM)
4880 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4881 (match_operator:<VM> 2 "equality_operator"
4882 [(vec_duplicate:V_VLSI_D
4883 (match_operand:<VEL> 4 "register_operand" " r"))
4884 (match_operand:V_VLSI_D 3 "register_operand" " vr")])
4885 (match_dup 1)))]
4886 "TARGET_VECTOR"
4887 "vms%B2.vx\t%0,%3,%4,v0.t"
4888 [(set_attr "type" "vicmp")
4889 (set_attr "mode" "<MODE>")
4890 (set_attr "merge_op_idx" "1")
4891 (set_attr "vl_op_idx" "5")
4892 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
4893 (set (attr "avl_type_idx") (const_int 7))])
4895 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4896 (define_insn "*pred_cmp<mode>_scalar"
4897 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4898 (if_then_else:<VM>
4899 (unspec:<VM>
4900 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4901 (match_operand 6 "vector_length_operand" " rK, rK")
4902 (match_operand 7 "const_int_operand" " i, i")
4903 (match_operand 8 "const_int_operand" " i, i")
4904 (reg:SI VL_REGNUM)
4905 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4906 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4907 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
4908 (vec_duplicate:V_VLSI_D
4909 (match_operand:<VEL> 5 "register_operand" " r, r"))])
4910 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4911 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4912 "vms%B3.vx\t%0,%4,%5%p1"
4913 [(set_attr "type" "vicmp")
4914 (set_attr "mode" "<MODE>")])
4916 ;; We use early-clobber for source LMUL > dest LMUL.
4917 (define_insn "*pred_cmp<mode>_scalar_narrow"
4918 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4919 (if_then_else:<VM>
4920 (unspec:<VM>
4921 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4922 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4923 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4924 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4925 (reg:SI VL_REGNUM)
4926 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4927 (match_operator:<VM> 3 "comparison_except_eqge_operator"
4928 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
4929 (vec_duplicate:V_VLSI_D
4930 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))])
4931 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4932 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4933 "vms%B3.vx\t%0,%4,%5%p1"
4934 [(set_attr "type" "vicmp")
4935 (set_attr "mode" "<MODE>")])
4937 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
4938 (define_insn "*pred_eqne<mode>_scalar"
4939 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
4940 (if_then_else:<VM>
4941 (unspec:<VM>
4942 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
4943 (match_operand 6 "vector_length_operand" " rK, rK")
4944 (match_operand 7 "const_int_operand" " i, i")
4945 (match_operand 8 "const_int_operand" " i, i")
4946 (reg:SI VL_REGNUM)
4947 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4948 (match_operator:<VM> 3 "equality_operator"
4949 [(vec_duplicate:V_VLSI_D
4950 (match_operand:<VEL> 5 "register_operand" " r, r"))
4951 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")])
4952 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
4953 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
4954 "vms%B3.vx\t%0,%4,%5%p1"
4955 [(set_attr "type" "vicmp")
4956 (set_attr "mode" "<MODE>")])
4958 ;; We use early-clobber for source LMUL > dest LMUL.
4959 (define_insn "*pred_eqne<mode>_scalar_narrow"
4960 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
4961 (if_then_else:<VM>
4962 (unspec:<VM>
4963 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
4964 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
4965 (match_operand 7 "const_int_operand" " i, i, i, i, i")
4966 (match_operand 8 "const_int_operand" " i, i, i, i, i")
4967 (reg:SI VL_REGNUM)
4968 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4969 (match_operator:<VM> 3 "equality_operator"
4970 [(vec_duplicate:V_VLSI_D
4971 (match_operand:<VEL> 5 "register_operand" " r, r, r, r, r"))
4972 (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
4973 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
4974 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
4975 "vms%B3.vx\t%0,%4,%5%p1"
4976 [(set_attr "type" "vicmp")
4977 (set_attr "mode" "<MODE>")])
4979 (define_insn "*pred_cmp<mode>_extended_scalar_merge_tie_mask"
4980 [(set (match_operand:<VM> 0 "register_operand" "=vm")
4981 (if_then_else:<VM>
4982 (unspec:<VM>
4983 [(match_operand:<VM> 1 "register_operand" " 0")
4984 (match_operand 5 "vector_length_operand" " rK")
4985 (match_operand 6 "const_int_operand" " i")
4986 (match_operand 7 "const_int_operand" " i")
4987 (reg:SI VL_REGNUM)
4988 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
4989 (match_operator:<VM> 2 "comparison_except_eqge_operator"
4990 [(match_operand:V_VLSI_D 3 "register_operand" " vr")
4991 (vec_duplicate:V_VLSI_D
4992 (sign_extend:<VEL>
4993 (match_operand:<VSUBEL> 4 "register_operand" " r")))])
4994 (match_dup 1)))]
4995 "TARGET_VECTOR"
4996 "vms%B2.vx\t%0,%3,%4,v0.t"
4997 [(set_attr "type" "vicmp")
4998 (set_attr "mode" "<MODE>")
4999 (set_attr "merge_op_idx" "1")
5000 (set_attr "vl_op_idx" "5")
5001 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5002 (set (attr "avl_type_idx") (const_int 7))])
5004 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5005 (define_insn "*pred_cmp<mode>_extended_scalar"
5006 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
5007 (if_then_else:<VM>
5008 (unspec:<VM>
5009 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
5010 (match_operand 6 "vector_length_operand" " rK, rK")
5011 (match_operand 7 "const_int_operand" " i, i")
5012 (match_operand 8 "const_int_operand" " i, i")
5013 (reg:SI VL_REGNUM)
5014 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5015 (match_operator:<VM> 3 "comparison_except_eqge_operator"
5016 [(match_operand:V_VLSI_D 4 "register_operand" " vr, vr")
5017 (vec_duplicate:V_VLSI_D
5018 (sign_extend:<VEL>
5019 (match_operand:<VSUBEL> 5 "register_operand" " r, r")))])
5020 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
5021 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
5022 "vms%B3.vx\t%0,%4,%5%p1"
5023 [(set_attr "type" "vicmp")
5024 (set_attr "mode" "<MODE>")])
5026 (define_insn "*pred_cmp<mode>_extended_scalar_narrow"
5027 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5028 (if_then_else:<VM>
5029 (unspec:<VM>
5030 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5031 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5032 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5033 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5034 (reg:SI VL_REGNUM)
5035 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5036 (match_operator:<VM> 3 "comparison_except_eqge_operator"
5037 [(match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")
5038 (vec_duplicate:V_VLSI_D
5039 (sign_extend:<VEL>
5040 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))])
5041 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5042 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
5043 "vms%B3.vx\t%0,%4,%5%p1"
5044 [(set_attr "type" "vicmp")
5045 (set_attr "mode" "<MODE>")])
5047 (define_insn "*pred_eqne<mode>_extended_scalar_merge_tie_mask"
5048 [(set (match_operand:<VM> 0 "register_operand" "=vm")
5049 (if_then_else:<VM>
5050 (unspec:<VM>
5051 [(match_operand:<VM> 1 "register_operand" " 0")
5052 (match_operand 5 "vector_length_operand" " rK")
5053 (match_operand 6 "const_int_operand" " i")
5054 (match_operand 7 "const_int_operand" " i")
5055 (reg:SI VL_REGNUM)
5056 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5057 (match_operator:<VM> 2 "equality_operator"
5058 [(vec_duplicate:V_VLSI_D
5059 (sign_extend:<VEL>
5060 (match_operand:<VSUBEL> 4 "register_operand" " r")))
5061 (match_operand:V_VLSI_D 3 "register_operand" " vr")])
5062 (match_dup 1)))]
5063 "TARGET_VECTOR"
5064 "vms%B2.vx\t%0,%3,%4,v0.t"
5065 [(set_attr "type" "vicmp")
5066 (set_attr "mode" "<MODE>")
5067 (set_attr "merge_op_idx" "1")
5068 (set_attr "vl_op_idx" "5")
5069 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
5070 (set (attr "avl_type_idx") (const_int 7))])
5072 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
5073 (define_insn "*pred_eqne<mode>_extended_scalar"
5074 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
5075 (if_then_else:<VM>
5076 (unspec:<VM>
5077 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
5078 (match_operand 6 "vector_length_operand" " rK, rK")
5079 (match_operand 7 "const_int_operand" " i, i")
5080 (match_operand 8 "const_int_operand" " i, i")
5081 (reg:SI VL_REGNUM)
5082 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5083 (match_operator:<VM> 3 "equality_operator"
5084 [(vec_duplicate:V_VLSI_D
5085 (sign_extend:<VEL>
5086 (match_operand:<VSUBEL> 5 "register_operand" " r, r")))
5087 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr")])
5088 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
5089 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
5090 "vms%B3.vx\t%0,%4,%5%p1"
5091 [(set_attr "type" "vicmp")
5092 (set_attr "mode" "<MODE>")])
5094 (define_insn "*pred_eqne<mode>_extended_scalar_narrow"
5095 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
5096 (if_then_else:<VM>
5097 (unspec:<VM>
5098 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
5099 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
5100 (match_operand 7 "const_int_operand" " i, i, i, i, i")
5101 (match_operand 8 "const_int_operand" " i, i, i, i, i")
5102 (reg:SI VL_REGNUM)
5103 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5104 (match_operator:<VM> 3 "equality_operator"
5105 [(vec_duplicate:V_VLSI_D
5106 (sign_extend:<VEL>
5107 (match_operand:<VSUBEL> 5 "register_operand" " r, r, r, r, r")))
5108 (match_operand:V_VLSI_D 4 "register_operand" " vr, 0, 0, vr, vr")])
5109 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
5110 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
5111 "vms%B3.vx\t%0,%4,%5%p1"
5112 [(set_attr "type" "vicmp")
5113 (set_attr "mode" "<MODE>")])
5115 ;; GE, vmsge.vx/vmsgeu.vx
5116 ;;
5117 ;; unmasked va >= x
5118 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x
5119 ;; - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd
5120 ;;
5121 ;; masked va >= x, vd != v0
5122 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5123 ;; - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
5124 ;;
5125 ;; masked va >= x, vd == v0
5126 ;; - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5127 ;; - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt
5128 (define_expand "@pred_ge<mode>_scalar"
5129 [(set (match_operand:<VM> 0 "register_operand")
5130 (if_then_else:<VM>
5131 (unspec:<VM>
5132 [(match_operand:<VM> 1 "vector_mask_operand")
5133 (match_operand 6 "vector_length_operand")
5134 (match_operand 7 "const_int_operand")
5135 (match_operand 8 "const_int_operand")
5136 (reg:SI VL_REGNUM)
5137 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5138 (match_operator:<VM> 3 "ge_operator"
5139 [(match_operand:V_VLSI 4 "register_operand")
5140 (vec_duplicate:V_VLSI
5141 (match_operand:<VEL> 5 "reg_or_int_operand"))])
5142 (match_operand:<VM> 2 "vector_merge_operand")))]
5143 "TARGET_VECTOR"
5144 {
5145 enum rtx_code code = GET_CODE (operands[3]);
5146 rtx undef = RVV_VUNDEF (<VM>mode);
5147 rtx tmp = gen_reg_rtx (<VM>mode);
5148 if (code == GEU && rtx_equal_p (operands[5], const0_rtx))
5149 {
5150 /* If vmsgeu with 0 immediate, expand it to vmset. */
5151 if (satisfies_constraint_Wc1 (operands[1]))
5152 emit_insn (
5153 gen_pred_mov (<VM>mode, operands[0], CONSTM1_RTX (<VM>mode), undef,
5154 CONSTM1_RTX (<VM>mode), operands[6], operands[8]));
5155 else
5156 {
5157 /* If vmsgeu_mask with 0 immediate, expand it to vmor mask, maskedoff.
5158 */
5159 if (rtx_equal_p (operands[1], operands[2]))
5160 emit_move_insn (operands[0], operands[1]);
5161 else if (register_operand (operands[2], <VM>mode))
5162 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5163 CONSTM1_RTX (<VM>mode), undef, operands[1],
5164 operands[2], operands[6], operands[8]));
5165 else
5166 emit_insn (gen_pred (IOR, <VM>mode, operands[0],
5167 CONSTM1_RTX (<VM>mode), undef, operands[1],
5168 operands[1], operands[6], operands[8]));
5169 }
5170 }
5171 else if (riscv_vector::neg_simm5_p (operands[5]))
5172 emit_insn (
5173 gen_pred_ltge<mode> (operands[0], operands[1], operands[2], operands[3],
5174 operands[4],
5175 gen_const_vec_duplicate (<MODE>mode, operands[5]),
5176 operands[6], operands[7], operands[8]));
5177 else
5178 {
5179 if (code == GE)
5180 operands[3] = gen_rtx_fmt_ee (LT, <VM>mode, XEXP (operands[3], 0),
5181 XEXP (operands[3], 1));
5182 else
5183 operands[3] = gen_rtx_fmt_ee (LTU, <VM>mode, XEXP (operands[3], 0),
5184 XEXP (operands[3], 1));
5185 if (GET_MODE_BITSIZE (<VEL>mode) <= GET_MODE_BITSIZE (Pmode))
5186 operands[5] = force_reg (<VEL>mode, operands[5]);
5188 if (satisfies_constraint_Wc1 (operands[1]))
5189 {
5190 /* unmasked va >= x
5191 - pseudoinstruction: vmsge{u}.vx vd, va, x
5192 - expansion: vmslt{u}.vx vd, va, x; vmnand.mm vd, vd, vd. */
5193 emit_insn (
5194 gen_pred_cmp<mode>_scalar (tmp, operands[1], operands[2],
5195 operands[3], operands[4], operands[5],
5196 operands[6], operands[7], operands[8]));
5197 emit_insn (gen_pred_nand<vm> (operands[0], CONSTM1_RTX (<VM>mode),
5198 undef, tmp, tmp, operands[6], operands[8]));
5199 }
5200 else
5201 {
5202 if (rtx_equal_p (operands[1], operands[2]))
5203 {
5204 /* masked va >= x, vd == v0
5205 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t, vt
5206 - expansion: vmslt{u}.vx vt, va, x; vmandn.mm vd, vd, vt. */
5207 emit_insn (gen_pred_cmp<mode>_scalar (
5208 tmp, CONSTM1_RTX (<VM>mode), undef, operands[3], operands[4],
5209 operands[5], operands[6], operands[7], operands[8]));
5210 emit_insn (
5211 gen_pred_andnot<vm> (operands[0], CONSTM1_RTX (<VM>mode), undef,
5212 operands[1], tmp, operands[6], operands[8]));
5213 }
5214 else
5215 {
5216 /* masked va >= x, vd != v0
5217 - pseudoinstruction: vmsge{u}.vx vd, va, x, v0.t
5218 - expansion: vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0.
5219 */
5220 emit_insn (gen_pred_cmp<mode>_scalar (
5221 tmp, operands[1], operands[2], operands[3], operands[4],
5222 operands[5], operands[6], operands[7], operands[8]));
5223 emit_insn (gen_pred (XOR, <VM>mode, operands[0],
5224 CONSTM1_RTX (<VM>mode), undef, tmp,
5225 operands[1], operands[6], operands[8]));
5226 }
5227 }
5228 }
5229 DONE;
5230 })
5232 ;; -------------------------------------------------------------------------------
5233 ;; ---- Predicated integer ternary operations
5234 ;; -------------------------------------------------------------------------------
5235 ;; Includes:
5236 ;; - 11.13 Vector Single-Width Integer Multiply-Add Instructions
5237 ;; -------------------------------------------------------------------------------
5239 (define_expand "@pred_mul_plus<mode>"
5240 [(set (match_operand:V_VLSI 0 "register_operand")
5241 (if_then_else:V_VLSI
5242 (unspec:<VM>
5243 [(match_operand:<VM> 1 "vector_mask_operand")
5244 (match_operand 6 "vector_length_operand")
5245 (match_operand 7 "const_int_operand")
5246 (match_operand 8 "const_int_operand")
5247 (match_operand 9 "const_int_operand")
5248 (reg:SI VL_REGNUM)
5249 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5250 (plus:V_VLSI
5251 (mult:V_VLSI
5252 (match_operand:V_VLSI 2 "register_operand")
5253 (match_operand:V_VLSI 3 "register_operand"))
5254 (match_operand:V_VLSI 4 "register_operand"))
5255 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5256 "TARGET_VECTOR"
5257 {
5258 riscv_vector::prepare_ternary_operands (operands);
5259 })
5261 (define_insn "*pred_mul_plus<mode>_undef"
5262 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5263 (if_then_else:V_VLSI
5264 (unspec:<VM>
5265 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5266 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5267 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5268 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5269 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5270 (reg:SI VL_REGNUM)
5271 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5272 (plus:V_VLSI
5273 (mult:V_VLSI
5274 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5275 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr"))
5276 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
5277 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5278 "TARGET_VECTOR"
5279 "@
5280 vmadd.vv\t%0,%4,%5%p1
5281 vmacc.vv\t%0,%3,%4%p1
5282 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%3,%4%p1
5283 vmadd.vv\t%0,%4,%5%p1
5284 vmacc.vv\t%0,%3,%4%p1
5285 vmv.v.v\t%0,%5\;vmacc.vv\t%0,%3,%4%p1"
5286 [(set_attr "type" "vimuladd")
5287 (set_attr "mode" "<MODE>")])
5289 (define_insn "*pred_madd<mode>"
5290 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5291 (if_then_else:V_VLSI
5292 (unspec:<VM>
5293 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5294 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5295 (match_operand 6 "const_int_operand" " i, i, i, i")
5296 (match_operand 7 "const_int_operand" " i, i, i, i")
5297 (match_operand 8 "const_int_operand" " i, i, i, i")
5298 (reg:SI VL_REGNUM)
5299 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5300 (plus:V_VLSI
5301 (mult:V_VLSI
5302 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5303 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5304 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5305 (match_dup 2)))]
5306 "TARGET_VECTOR"
5307 "@
5308 vmadd.vv\t%0,%3,%4%p1
5309 vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1
5310 vmadd.vv\t%0,%3,%4%p1
5311 vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1"
5312 [(set_attr "type" "vimuladd")
5313 (set_attr "mode" "<MODE>")
5314 (set_attr "merge_op_idx" "4")
5315 (set_attr "vl_op_idx" "5")
5316 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5317 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5318 (set (attr "avl_type_idx") (const_int 8))])
5320 (define_insn "*pred_macc<mode>"
5321 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5322 (if_then_else:V_VLSI
5323 (unspec:<VM>
5324 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5325 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5326 (match_operand 6 "const_int_operand" " i, i, i, i")
5327 (match_operand 7 "const_int_operand" " i, i, i, i")
5328 (match_operand 8 "const_int_operand" " i, i, i, i")
5329 (reg:SI VL_REGNUM)
5330 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5331 (plus:V_VLSI
5332 (mult:V_VLSI
5333 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5334 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5335 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5336 (match_dup 4)))]
5337 "TARGET_VECTOR"
5338 "@
5339 vmacc.vv\t%0,%2,%3%p1
5340 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1
5341 vmacc.vv\t%0,%2,%3%p1
5342 vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1"
5343 [(set_attr "type" "vimuladd")
5344 (set_attr "mode" "<MODE>")
5345 (set_attr "merge_op_idx" "2")
5346 (set_attr "vl_op_idx" "5")
5347 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5348 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5349 (set (attr "avl_type_idx") (const_int 8))])
5351 (define_expand "@pred_mul_plus<mode>_scalar"
5352 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5353 (if_then_else:V_VLSI_QHS
5354 (unspec:<VM>
5355 [(match_operand:<VM> 1 "vector_mask_operand")
5356 (match_operand 6 "vector_length_operand")
5357 (match_operand 7 "const_int_operand")
5358 (match_operand 8 "const_int_operand")
5359 (match_operand 9 "const_int_operand")
5360 (reg:SI VL_REGNUM)
5361 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5362 (plus:V_VLSI_QHS
5363 (mult:V_VLSI_QHS
5364 (vec_duplicate:V_VLSI_QHS
5365 (match_operand:<VEL> 2 "register_operand"))
5366 (match_operand:V_VLSI_QHS 3 "register_operand"))
5367 (match_operand:V_VLSI_QHS 4 "register_operand"))
5368 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5369 "TARGET_VECTOR"
5370 {})
5372 (define_insn "*pred_madd<mode>_scalar"
5373 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5374 (if_then_else:V_VLSI
5375 (unspec:<VM>
5376 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5377 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5378 (match_operand 6 "const_int_operand" " i, i, i, i")
5379 (match_operand 7 "const_int_operand" " i, i, i, i")
5380 (match_operand 8 "const_int_operand" " i, i, i, i")
5381 (reg:SI VL_REGNUM)
5382 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5383 (plus:V_VLSI
5384 (mult:V_VLSI
5385 (vec_duplicate:V_VLSI
5386 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5387 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr"))
5388 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr"))
5389 (match_dup 3)))]
5390 "TARGET_VECTOR"
5391 "@
5392 vmadd.vx\t%0,%2,%4%p1
5393 vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1
5394 vmadd.vx\t%0,%2,%4%p1
5395 vmv.v.v\t%0,%3\;vmadd.vx\t%0,%2,%4%p1"
5396 [(set_attr "type" "vimuladd")
5397 (set_attr "mode" "<MODE>")
5398 (set_attr "merge_op_idx" "4")
5399 (set_attr "vl_op_idx" "5")
5400 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5401 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5402 (set (attr "avl_type_idx") (const_int 8))])
5404 (define_insn "*pred_macc<mode>_scalar"
5405 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5406 (if_then_else:V_VLSI
5407 (unspec:<VM>
5408 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5409 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5410 (match_operand 6 "const_int_operand" " i, i, i, i")
5411 (match_operand 7 "const_int_operand" " i, i, i, i")
5412 (match_operand 8 "const_int_operand" " i, i, i, i")
5413 (reg:SI VL_REGNUM)
5414 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5415 (plus:V_VLSI
5416 (mult:V_VLSI
5417 (vec_duplicate:V_VLSI
5418 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5419 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr"))
5420 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr"))
5421 (match_dup 4)))]
5422 "TARGET_VECTOR"
5423 "@
5424 vmacc.vx\t%0,%2,%3%p1
5425 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5426 vmacc.vx\t%0,%2,%3%p1
5427 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5428 [(set_attr "type" "vimuladd")
5429 (set_attr "mode" "<MODE>")
5430 (set_attr "merge_op_idx" "2")
5431 (set_attr "vl_op_idx" "5")
5432 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5433 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5434 (set (attr "avl_type_idx") (const_int 8))])
5436 (define_expand "@pred_mul_plus<mode>_scalar"
5437 [(set (match_operand:V_VLSI_D 0 "register_operand")
5438 (if_then_else:V_VLSI_D
5439 (unspec:<VM>
5440 [(match_operand:<VM> 1 "vector_mask_operand")
5441 (match_operand 6 "vector_length_operand")
5442 (match_operand 7 "const_int_operand")
5443 (match_operand 8 "const_int_operand")
5444 (match_operand 9 "const_int_operand")
5445 (reg:SI VL_REGNUM)
5446 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5447 (plus:V_VLSI_D
5448 (mult:V_VLSI_D
5449 (vec_duplicate:V_VLSI_D
5450 (match_operand:<VEL> 2 "reg_or_int_operand"))
5451 (match_operand:V_VLSI_D 3 "register_operand"))
5452 (match_operand:V_VLSI_D 4 "register_operand"))
5453 (match_operand:V_VLSI_D 5 "register_operand")))]
5454 "TARGET_VECTOR"
5455 {
5456 if (riscv_vector::sew64_scalar_helper (
5457 operands,
5458 /* scalar op */&operands[2],
5459 /* vl */operands[6],
5460 <MODE>mode,
5461 false,
5462 [] (rtx *operands, rtx boardcast_scalar) {
5463 emit_insn (gen_pred_mul_plus<mode> (operands[0], operands[1],
5464 boardcast_scalar, operands[3], operands[4], operands[5],
5465 operands[6], operands[7], operands[8], operands[9]));
5466 },
5467 (riscv_vector::avl_type) INTVAL (operands[9])))
5468 DONE;
5469 })
5471 (define_insn "*pred_madd<mode>_extended_scalar"
5472 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5473 (if_then_else:V_VLSI_D
5474 (unspec:<VM>
5475 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5476 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5477 (match_operand 6 "const_int_operand" " i, i, i, i")
5478 (match_operand 7 "const_int_operand" " i, i, i, i")
5479 (match_operand 8 "const_int_operand" " i, i, i, i")
5480 (reg:SI VL_REGNUM)
5481 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5482 (plus:V_VLSI_D
5483 (mult:V_VLSI_D
5484 (vec_duplicate:V_VLSI_D
5485 (sign_extend:<VEL>
5486 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5487 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr"))
5488 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr"))
5489 (match_dup 3)))]
5490 "TARGET_VECTOR"
5491 "@
5492 vmadd.vx\t%0,%2,%4%p1
5493 vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1
5494 vmadd.vx\t%0,%2,%4%p1
5495 vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1"
5496 [(set_attr "type" "vimuladd")
5497 (set_attr "mode" "<MODE>")
5498 (set_attr "merge_op_idx" "4")
5499 (set_attr "vl_op_idx" "5")
5500 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5501 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5502 (set (attr "avl_type_idx") (const_int 8))])
5504 (define_insn "*pred_macc<mode>_extended_scalar"
5505 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5506 (if_then_else:V_VLSI_D
5507 (unspec:<VM>
5508 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5509 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5510 (match_operand 6 "const_int_operand" " i, i, i, i")
5511 (match_operand 7 "const_int_operand" " i, i, i, i")
5512 (match_operand 8 "const_int_operand" " i, i, i, i")
5513 (reg:SI VL_REGNUM)
5514 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5515 (plus:V_VLSI_D
5516 (mult:V_VLSI_D
5517 (vec_duplicate:V_VLSI_D
5518 (sign_extend:<VEL>
5519 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5520 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr"))
5521 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr"))
5522 (match_dup 4)))]
5523 "TARGET_VECTOR"
5524 "@
5525 vmacc.vx\t%0,%2,%3%p1
5526 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1
5527 vmacc.vx\t%0,%2,%3%p1
5528 vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1"
5529 [(set_attr "type" "vimuladd")
5530 (set_attr "mode" "<MODE>")
5531 (set_attr "merge_op_idx" "2")
5532 (set_attr "vl_op_idx" "5")
5533 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5534 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5535 (set (attr "avl_type_idx") (const_int 8))])
5537 (define_expand "@pred_minus_mul<mode>"
5538 [(set (match_operand:V_VLSI 0 "register_operand")
5539 (if_then_else:V_VLSI
5540 (unspec:<VM>
5541 [(match_operand:<VM> 1 "vector_mask_operand")
5542 (match_operand 6 "vector_length_operand")
5543 (match_operand 7 "const_int_operand")
5544 (match_operand 8 "const_int_operand")
5545 (match_operand 9 "const_int_operand")
5546 (reg:SI VL_REGNUM)
5547 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5548 (minus:V_VLSI
5549 (match_operand:V_VLSI 4 "register_operand")
5550 (mult:V_VLSI
5551 (match_operand:V_VLSI 2 "register_operand")
5552 (match_operand:V_VLSI 3 "register_operand")))
5553 (match_operand:V_VLSI 5 "vector_merge_operand")))]
5554 "TARGET_VECTOR"
5555 {
5556 riscv_vector::prepare_ternary_operands (operands);
5557 })
5559 (define_insn "*pred_minus_mul<mode>_undef"
5560 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd,?&vd, vr, vr,?&vr")
5561 (if_then_else:V_VLSI
5562 (unspec:<VM>
5563 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, vm,Wc1,Wc1, Wc1")
5564 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
5565 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
5566 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
5567 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
5568 (reg:SI VL_REGNUM)
5569 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5570 (minus:V_VLSI
5571 (match_operand:V_VLSI 5 "register_operand" " vr, 0, vr, vr, 0, vr")
5572 (mult:V_VLSI
5573 (match_operand:V_VLSI 3 "register_operand" " 0, vr, vr, 0, vr, vr")
5574 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr, vr, vr")))
5575 (match_operand:V_VLSI 2 "vector_undef_operand")))]
5576 "TARGET_VECTOR"
5577 "@
5578 vnmsub.vv\t%0,%4,%5%p1
5579 vnmsac.vv\t%0,%3,%4%p1
5580 vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1
5581 vnmsub.vv\t%0,%4,%5%p1
5582 vnmsac.vv\t%0,%3,%4%p1
5583 vmv.v.v\t%0,%3\;vnmsub.vv\t%0,%4,%5%p1"
5584 [(set_attr "type" "vimuladd")
5585 (set_attr "mode" "<MODE>")])
5587 (define_insn "*pred_nmsub<mode>"
5588 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5589 (if_then_else:V_VLSI
5590 (unspec:<VM>
5591 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5592 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5593 (match_operand 6 "const_int_operand" " i, i, i, i")
5594 (match_operand 7 "const_int_operand" " i, i, i, i")
5595 (match_operand 8 "const_int_operand" " i, i, i, i")
5596 (reg:SI VL_REGNUM)
5597 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5598 (minus:V_VLSI
5599 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5600 (mult:V_VLSI
5601 (match_operand:V_VLSI 2 "register_operand" " 0, vr, 0, vr")
5602 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5603 (match_dup 2)))]
5604 "TARGET_VECTOR"
5605 "@
5606 vnmsub.vv\t%0,%3,%4%p1
5607 vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1
5608 vnmsub.vv\t%0,%3,%4%p1
5609 vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1"
5610 [(set_attr "type" "vimuladd")
5611 (set_attr "mode" "<MODE>")
5612 (set_attr "merge_op_idx" "4")
5613 (set_attr "vl_op_idx" "5")
5614 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5615 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5616 (set (attr "avl_type_idx") (const_int 8))])
5618 (define_insn "*pred_nmsac<mode>"
5619 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5620 (if_then_else:V_VLSI
5621 (unspec:<VM>
5622 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5623 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5624 (match_operand 6 "const_int_operand" " i, i, i, i")
5625 (match_operand 7 "const_int_operand" " i, i, i, i")
5626 (match_operand 8 "const_int_operand" " i, i, i, i")
5627 (reg:SI VL_REGNUM)
5628 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5629 (minus:V_VLSI
5630 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5631 (mult:V_VLSI
5632 (match_operand:V_VLSI 2 "register_operand" " vr, vr, vr, vr")
5633 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5634 (match_dup 4)))]
5635 "TARGET_VECTOR"
5636 "@
5637 vnmsac.vv\t%0,%2,%3%p1
5638 vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1
5639 vnmsac.vv\t%0,%2,%3%p1
5640 vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1"
5641 [(set_attr "type" "vimuladd")
5642 (set_attr "mode" "<MODE>")
5643 (set_attr "merge_op_idx" "2")
5644 (set_attr "vl_op_idx" "5")
5645 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5646 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5647 (set (attr "avl_type_idx") (const_int 8))])
5649 (define_expand "@pred_minus_mul<mode>_scalar"
5650 [(set (match_operand:V_VLSI_QHS 0 "register_operand")
5651 (if_then_else:V_VLSI_QHS
5652 (unspec:<VM>
5653 [(match_operand:<VM> 1 "vector_mask_operand")
5654 (match_operand 6 "vector_length_operand")
5655 (match_operand 7 "const_int_operand")
5656 (match_operand 8 "const_int_operand")
5657 (match_operand 9 "const_int_operand")
5658 (reg:SI VL_REGNUM)
5659 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5660 (minus:V_VLSI_QHS
5661 (match_operand:V_VLSI_QHS 4 "register_operand")
5662 (mult:V_VLSI_QHS
5663 (vec_duplicate:V_VLSI_QHS
5664 (match_operand:<VEL> 2 "register_operand"))
5665 (match_operand:V_VLSI_QHS 3 "register_operand")))
5666 (match_operand:V_VLSI_QHS 5 "register_operand")))]
5667 "TARGET_VECTOR"
5668 {})
5670 (define_insn "*pred_nmsub<mode>_scalar"
5671 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5672 (if_then_else:V_VLSI
5673 (unspec:<VM>
5674 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5675 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5676 (match_operand 6 "const_int_operand" " i, i, i, i")
5677 (match_operand 7 "const_int_operand" " i, i, i, i")
5678 (match_operand 8 "const_int_operand" " i, i, i, i")
5679 (reg:SI VL_REGNUM)
5680 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5681 (minus:V_VLSI
5682 (match_operand:V_VLSI 4 "register_operand" " vr, vr, vr, vr")
5683 (mult:V_VLSI
5684 (vec_duplicate:V_VLSI
5685 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5686 (match_operand:V_VLSI 3 "register_operand" " 0, vr, 0, vr")))
5687 (match_dup 3)))]
5688 "TARGET_VECTOR"
5689 "@
5690 vnmsub.vx\t%0,%2,%4%p1
5691 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5692 vnmsub.vx\t%0,%2,%4%p1
5693 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5694 [(set_attr "type" "vimuladd")
5695 (set_attr "mode" "<MODE>")
5696 (set_attr "merge_op_idx" "4")
5697 (set_attr "vl_op_idx" "5")
5698 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5699 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5700 (set (attr "avl_type_idx") (const_int 8))])
5702 (define_insn "*pred_nmsac<mode>_scalar"
5703 [(set (match_operand:V_VLSI 0 "register_operand" "=vd,?&vd, vr,?&vr")
5704 (if_then_else:V_VLSI
5705 (unspec:<VM>
5706 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5707 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5708 (match_operand 6 "const_int_operand" " i, i, i, i")
5709 (match_operand 7 "const_int_operand" " i, i, i, i")
5710 (match_operand 8 "const_int_operand" " i, i, i, i")
5711 (reg:SI VL_REGNUM)
5712 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5713 (minus:V_VLSI
5714 (match_operand:V_VLSI 4 "register_operand" " 0, vr, 0, vr")
5715 (mult:V_VLSI
5716 (vec_duplicate:V_VLSI
5717 (match_operand:<VEL> 2 "register_operand" " r, r, r, r"))
5718 (match_operand:V_VLSI 3 "register_operand" " vr, vr, vr, vr")))
5719 (match_dup 4)))]
5720 "TARGET_VECTOR"
5721 "@
5722 vnmsac.vx\t%0,%2,%3%p1
5723 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5724 vnmsac.vx\t%0,%2,%3%p1
5725 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5726 [(set_attr "type" "vimuladd")
5727 (set_attr "mode" "<MODE>")
5728 (set_attr "merge_op_idx" "2")
5729 (set_attr "vl_op_idx" "5")
5730 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5731 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5732 (set (attr "avl_type_idx") (const_int 8))])
5734 (define_expand "@pred_minus_mul<mode>_scalar"
5735 [(set (match_operand:V_VLSI_D 0 "register_operand")
5736 (if_then_else:V_VLSI_D
5737 (unspec:<VM>
5738 [(match_operand:<VM> 1 "vector_mask_operand")
5739 (match_operand 6 "vector_length_operand")
5740 (match_operand 7 "const_int_operand")
5741 (match_operand 8 "const_int_operand")
5742 (match_operand 9 "const_int_operand")
5743 (reg:SI VL_REGNUM)
5744 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5745 (minus:V_VLSI_D
5746 (match_operand:V_VLSI_D 4 "register_operand")
5747 (mult:V_VLSI_D
5748 (vec_duplicate:V_VLSI_D
5749 (match_operand:<VEL> 2 "reg_or_int_operand"))
5750 (match_operand:V_VLSI_D 3 "register_operand")))
5751 (match_operand:V_VLSI_D 5 "register_operand")))]
5752 "TARGET_VECTOR"
5753 {
5754 if (riscv_vector::sew64_scalar_helper (
5755 operands,
5756 /* scalar op */&operands[2],
5757 /* vl */operands[6],
5758 <MODE>mode,
5759 false,
5760 [] (rtx *operands, rtx boardcast_scalar) {
5761 emit_insn (gen_pred_minus_mul<mode> (operands[0], operands[1],
5762 boardcast_scalar, operands[3], operands[4], operands[5],
5763 operands[6], operands[7], operands[8], operands[9]));
5764 },
5765 (riscv_vector::avl_type) INTVAL (operands[9])))
5766 DONE;
5767 })
5769 (define_insn "*pred_nmsub<mode>_extended_scalar"
5770 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5771 (if_then_else:V_VLSI_D
5772 (unspec:<VM>
5773 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5774 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5775 (match_operand 6 "const_int_operand" " i, i, i, i")
5776 (match_operand 7 "const_int_operand" " i, i, i, i")
5777 (match_operand 8 "const_int_operand" " i, i, i, i")
5778 (reg:SI VL_REGNUM)
5779 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5780 (minus:V_VLSI_D
5781 (match_operand:V_VLSI_D 4 "register_operand" " vr, vr, vr, vr")
5782 (mult:V_VLSI_D
5783 (vec_duplicate:V_VLSI_D
5784 (sign_extend:<VEL>
5785 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5786 (match_operand:V_VLSI_D 3 "register_operand" " 0, vr, 0, vr")))
5787 (match_dup 3)))]
5788 "TARGET_VECTOR"
5789 "@
5790 vnmsub.vx\t%0,%2,%4%p1
5791 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1
5792 vnmsub.vx\t%0,%2,%4%p1
5793 vmv.v.v\t%0,%3\;vnmsub.vx\t%0,%2,%4%p1"
5794 [(set_attr "type" "vimuladd")
5795 (set_attr "mode" "<MODE>")
5796 (set_attr "merge_op_idx" "4")
5797 (set_attr "vl_op_idx" "5")
5798 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5799 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5800 (set (attr "avl_type_idx") (const_int 8))])
5802 (define_insn "*pred_nmsac<mode>_extended_scalar"
5803 [(set (match_operand:V_VLSI_D 0 "register_operand" "=vd,?&vd, vr,?&vr")
5804 (if_then_else:V_VLSI_D
5805 (unspec:<VM>
5806 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
5807 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
5808 (match_operand 6 "const_int_operand" " i, i, i, i")
5809 (match_operand 7 "const_int_operand" " i, i, i, i")
5810 (match_operand 8 "const_int_operand" " i, i, i, i")
5811 (reg:SI VL_REGNUM)
5812 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5813 (minus:V_VLSI_D
5814 (match_operand:V_VLSI_D 4 "register_operand" " 0, vr, 0, vr")
5815 (mult:V_VLSI_D
5816 (vec_duplicate:V_VLSI_D
5817 (sign_extend:<VEL>
5818 (match_operand:<VSUBEL> 2 "register_operand" " r, r, r, r")))
5819 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")))
5820 (match_dup 4)))]
5821 "TARGET_VECTOR"
5822 "@
5823 vnmsac.vx\t%0,%2,%3%p1
5824 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1
5825 vnmsac.vx\t%0,%2,%3%p1
5826 vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1"
5827 [(set_attr "type" "vimuladd")
5828 (set_attr "mode" "<MODE>")
5829 (set_attr "merge_op_idx" "2")
5830 (set_attr "vl_op_idx" "5")
5831 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
5832 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
5833 (set (attr "avl_type_idx") (const_int 8))])
5835 ;; -------------------------------------------------------------------------------
5836 ;; ---- Predicated widen integer ternary operations
5837 ;; -------------------------------------------------------------------------------
5838 ;; Includes:
5839 ;; - 11.14 Vector Widening Integer Multiply-Add Instructions
5840 ;; -------------------------------------------------------------------------------
5842 (define_insn "@pred_widen_mul_plus<su><mode>"
5843 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5844 (if_then_else:VWEXTI
5845 (unspec:<VM>
5846 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5847 (match_operand 5 "vector_length_operand" " rK")
5848 (match_operand 6 "const_int_operand" " i")
5849 (match_operand 7 "const_int_operand" " i")
5850 (match_operand 8 "const_int_operand" " i")
5851 (reg:SI VL_REGNUM)
5852 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5853 (plus:VWEXTI
5854 (mult:VWEXTI
5855 (any_extend:VWEXTI
5856 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5857 (any_extend:VWEXTI
5858 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5859 (match_operand:VWEXTI 2 "register_operand" " 0"))
5860 (match_dup 2)))]
5861 "TARGET_VECTOR"
5862 "vwmacc<u>.vv\t%0,%3,%4%p1"
5863 [(set_attr "type" "viwmuladd")
5864 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5866 (define_insn "@pred_widen_mul_plus<su><mode>_scalar"
5867 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5868 (if_then_else:VWEXTI
5869 (unspec:<VM>
5870 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5871 (match_operand 5 "vector_length_operand" " rK")
5872 (match_operand 6 "const_int_operand" " i")
5873 (match_operand 7 "const_int_operand" " i")
5874 (match_operand 8 "const_int_operand" " i")
5875 (reg:SI VL_REGNUM)
5876 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5877 (plus:VWEXTI
5878 (mult:VWEXTI
5879 (any_extend:VWEXTI
5880 (vec_duplicate:<V_DOUBLE_TRUNC>
5881 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5882 (any_extend:VWEXTI
5883 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5884 (match_operand:VWEXTI 2 "register_operand" " 0"))
5885 (match_dup 2)))]
5886 "TARGET_VECTOR"
5887 "vwmacc<u>.vx\t%0,%3,%4%p1"
5888 [(set_attr "type" "viwmuladd")
5889 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5891 (define_insn "@pred_widen_mul_plussu<mode>"
5892 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5893 (if_then_else:VWEXTI
5894 (unspec:<VM>
5895 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5896 (match_operand 5 "vector_length_operand" " rK")
5897 (match_operand 6 "const_int_operand" " i")
5898 (match_operand 7 "const_int_operand" " i")
5899 (match_operand 8 "const_int_operand" " i")
5900 (reg:SI VL_REGNUM)
5901 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5902 (plus:VWEXTI
5903 (mult:VWEXTI
5904 (sign_extend:VWEXTI
5905 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
5906 (zero_extend:VWEXTI
5907 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5908 (match_operand:VWEXTI 2 "register_operand" " 0"))
5909 (match_dup 2)))]
5910 "TARGET_VECTOR"
5911 "vwmaccsu.vv\t%0,%3,%4%p1"
5912 [(set_attr "type" "viwmuladd")
5913 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5915 (define_insn "@pred_widen_mul_plussu<mode>_scalar"
5916 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5917 (if_then_else:VWEXTI
5918 (unspec:<VM>
5919 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5920 (match_operand 5 "vector_length_operand" " rK")
5921 (match_operand 6 "const_int_operand" " i")
5922 (match_operand 7 "const_int_operand" " i")
5923 (match_operand 8 "const_int_operand" " i")
5924 (reg:SI VL_REGNUM)
5925 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5926 (plus:VWEXTI
5927 (mult:VWEXTI
5928 (sign_extend:VWEXTI
5929 (vec_duplicate:<V_DOUBLE_TRUNC>
5930 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5931 (zero_extend:VWEXTI
5932 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5933 (match_operand:VWEXTI 2 "register_operand" " 0"))
5934 (match_dup 2)))]
5935 "TARGET_VECTOR"
5936 "vwmaccsu.vx\t%0,%3,%4%p1"
5937 [(set_attr "type" "viwmuladd")
5938 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5940 (define_insn "@pred_widen_mul_plusus<mode>_scalar"
5941 [(set (match_operand:VWEXTI 0 "register_operand" "=&vr")
5942 (if_then_else:VWEXTI
5943 (unspec:<VM>
5944 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
5945 (match_operand 5 "vector_length_operand" " rK")
5946 (match_operand 6 "const_int_operand" " i")
5947 (match_operand 7 "const_int_operand" " i")
5948 (match_operand 8 "const_int_operand" " i")
5949 (reg:SI VL_REGNUM)
5950 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5951 (plus:VWEXTI
5952 (mult:VWEXTI
5953 (zero_extend:VWEXTI
5954 (vec_duplicate:<V_DOUBLE_TRUNC>
5955 (match_operand:<VSUBEL> 3 "register_operand" " r")))
5956 (sign_extend:VWEXTI
5957 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
5958 (match_operand:VWEXTI 2 "register_operand" " 0"))
5959 (match_dup 2)))]
5960 "TARGET_VECTOR"
5961 "vwmaccus.vx\t%0,%3,%4%p1"
5962 [(set_attr "type" "viwmuladd")
5963 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
5965 ;; -------------------------------------------------------------------------------
5966 ;; ---- Predicated BOOL mask operations
5967 ;; -------------------------------------------------------------------------------
5968 ;; Includes:
5969 ;; - 15.1 Vector Mask-Register Logical Instructions
5970 ;; - 15.2 Vector count population in mask vcpop.m
5971 ;; - 15.3 vfirst find-first-set mask bit
5972 ;; - 15.4 vmsbf.m set-before-first mask bit
5973 ;; - 15.5 vmsif.m set-including-first mask bit
5974 ;; - 15.6 vmsof.m set-only-first mask bit
5975 ;; - 15.8 Vector Iota Instruction
5976 ;; - 15.9 Vector Element Index Instruction
5977 ;; -------------------------------------------------------------------------------
5979 ;; We keep this pattern same as pred_mov so that we can gain more optimizations.
5980 ;; For example, if we have vmxor.mm v1,v1,v1. It will be optmized as vmclr.m which
5981 ;; is generated by pred_mov.
5982 (define_insn "@pred_<optab><mode>"
5983 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
5984 (if_then_else:VB_VLS
5985 (unspec:VB_VLS
5986 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
5987 (match_operand 5 "vector_length_operand" " rK")
5988 (match_operand 6 "const_int_operand" " i")
5989 (reg:SI VL_REGNUM)
5990 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
5991 (any_bitwise:VB_VLS
5992 (match_operand:VB_VLS 3 "register_operand" " vr")
5993 (match_operand:VB_VLS 4 "register_operand" " vr"))
5994 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
5995 "TARGET_VECTOR"
5996 "vm<insn>.mm\t%0,%3,%4"
5997 [(set_attr "type" "vmalu")
5998 (set_attr "mode" "<MODE>")
5999 (set_attr "vl_op_idx" "5")
6000 (set (attr "avl_type_idx") (const_int 6))])
6002 (define_insn "@pred_n<optab><mode>"
6003 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6004 (if_then_else:VB_VLS
6005 (unspec:VB_VLS
6006 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6007 (match_operand 5 "vector_length_operand" " rK")
6008 (match_operand 6 "const_int_operand" " i")
6009 (reg:SI VL_REGNUM)
6010 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6011 (not:VB_VLS
6012 (any_bitwise:VB_VLS
6013 (match_operand:VB_VLS 3 "register_operand" " vr")
6014 (match_operand:VB_VLS 4 "register_operand" " vr")))
6015 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6016 "TARGET_VECTOR"
6017 "vm<ninsn>.mm\t%0,%3,%4"
6018 [(set_attr "type" "vmalu")
6019 (set_attr "mode" "<MODE>")
6020 (set_attr "vl_op_idx" "5")
6021 (set (attr "avl_type_idx") (const_int 6))])
6023 (define_insn "@pred_<optab>not<mode>"
6024 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6025 (if_then_else:VB_VLS
6026 (unspec:VB_VLS
6027 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6028 (match_operand 5 "vector_length_operand" " rK")
6029 (match_operand 6 "const_int_operand" " i")
6030 (reg:SI VL_REGNUM)
6031 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6032 (and_ior:VB_VLS
6033 (match_operand:VB_VLS 3 "register_operand" " vr")
6034 (not:VB_VLS
6035 (match_operand:VB_VLS 4 "register_operand" " vr")))
6036 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6037 "TARGET_VECTOR"
6038 "vm<insn>n.mm\t%0,%3,%4"
6039 [(set_attr "type" "vmalu")
6040 (set_attr "mode" "<MODE>")
6041 (set_attr "vl_op_idx" "5")
6042 (set (attr "avl_type_idx") (const_int 6))])
6044 (define_insn "@pred_not<mode>"
6045 [(set (match_operand:VB_VLS 0 "register_operand" "=vr")
6046 (if_then_else:VB_VLS
6047 (unspec:VB_VLS
6048 [(match_operand:VB_VLS 1 "vector_all_trues_mask_operand" "Wc1")
6049 (match_operand 4 "vector_length_operand" " rK")
6050 (match_operand 5 "const_int_operand" " i")
6051 (reg:SI VL_REGNUM)
6052 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6053 (not:VB_VLS
6054 (match_operand:VB_VLS 3 "register_operand" " vr"))
6055 (match_operand:VB_VLS 2 "vector_undef_operand" " vu")))]
6056 "TARGET_VECTOR"
6057 "vmnot.m\t%0,%3"
6058 [(set_attr "type" "vmalu")
6059 (set_attr "mode" "<MODE>")
6060 (set_attr "vl_op_idx" "4")
6061 (set (attr "avl_type_idx") (const_int 5))])
6063 (define_insn "@pred_popcount<VB:mode><P:mode>"
6064 [(set (match_operand:P 0 "register_operand" "=r")
6065 (popcount:P
6066 (unspec:VB
6067 [(and:VB
6068 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6069 (match_operand:VB 2 "register_operand" " vr"))
6070 (match_operand 3 "vector_length_operand" " rK")
6071 (match_operand 4 "const_int_operand" " i")
6072 (reg:SI VL_REGNUM)
6073 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
6074 "TARGET_VECTOR"
6075 "vcpop.m\t%0,%2%p1"
6076 [(set_attr "type" "vmpop")
6077 (set_attr "mode" "<VB:MODE>")])
6079 (define_insn "@pred_ffs<VB:mode><P:mode>"
6080 [(set (match_operand:P 0 "register_operand" "=r")
6081 (plus:P
6082 (ffs:P
6083 (unspec:VB
6084 [(and:VB
6085 (match_operand:VB 1 "vector_mask_operand" "vmWc1")
6086 (match_operand:VB 2 "register_operand" " vr"))
6087 (match_operand 3 "vector_length_operand" " rK")
6088 (match_operand 4 "const_int_operand" " i")
6089 (reg:SI VL_REGNUM)
6090 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))
6091 (const_int -1)))]
6092 "TARGET_VECTOR"
6093 "vfirst.m\t%0,%2%p1"
6094 [(set_attr "type" "vmffs")
6095 (set_attr "mode" "<VB:MODE>")])
6097 (define_insn "@pred_<misc_op><mode>"
6098 [(set (match_operand:VB 0 "register_operand" "=&vr, &vr")
6099 (if_then_else:VB
6100 (unspec:VB
6101 [(match_operand:VB 1 "vector_mask_operand" "vmWc1,vmWc1")
6102 (match_operand 4 "vector_length_operand" " rK, rK")
6103 (match_operand 5 "const_int_operand" " i, i")
6104 (match_operand 6 "const_int_operand" " i, i")
6105 (reg:SI VL_REGNUM)
6106 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6107 (unspec:VB
6108 [(match_operand:VB 3 "register_operand" " vr, vr")] VMISC)
6109 (match_operand:VB 2 "vector_merge_operand" " vu, 0")))]
6110 "TARGET_VECTOR"
6111 "vm<misc_op>.m\t%0,%3%p1"
6112 [(set_attr "type" "vmsfs")
6113 (set_attr "mode" "<MODE>")])
6115 (define_insn "@pred_iota<mode>"
6116 [(set (match_operand:VI 0 "register_operand" "=&vr, &vr")
6117 (if_then_else:VI
6118 (unspec:<VM>
6119 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
6120 (match_operand 4 "vector_length_operand" " rK, rK")
6121 (match_operand 5 "const_int_operand" " i, i")
6122 (match_operand 6 "const_int_operand" " i, i")
6123 (match_operand 7 "const_int_operand" " i, i")
6124 (reg:SI VL_REGNUM)
6125 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6126 (unspec:VI
6127 [(match_operand:<VM> 3 "register_operand" " vr, vr")] UNSPEC_VIOTA)
6128 (match_operand:VI 2 "vector_merge_operand" " vu, 0")))]
6129 "TARGET_VECTOR"
6130 "viota.m\t%0,%3%p1"
6131 [(set_attr "type" "vmiota")
6132 (set_attr "mode" "<MODE>")])
6134 (define_insn "@pred_series<mode>"
6135 [(set (match_operand:V_VLSI 0 "register_operand" "=vd, vd, vr, vr")
6136 (if_then_else:V_VLSI
6137 (unspec:<VM>
6138 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6139 (match_operand 3 "vector_length_operand" " rK, rK, rK, rK")
6140 (match_operand 4 "const_int_operand" " i, i, i, i")
6141 (match_operand 5 "const_int_operand" " i, i, i, i")
6142 (match_operand 6 "const_int_operand" " i, i, i, i")
6143 (reg:SI VL_REGNUM)
6144 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6145 (vec_series:V_VLSI (const_int 0) (const_int 1))
6146 (match_operand:V_VLSI 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6147 "TARGET_VECTOR"
6148 "vid.v\t%0%p1"
6149 [(set_attr "type" "vmidx")
6150 (set_attr "mode" "<MODE>")])
6152 ;; -------------------------------------------------------------------------------
6153 ;; ---- Predicated floating-point binary operations
6154 ;; -------------------------------------------------------------------------------
6155 ;; Includes:
6156 ;; - 13.2 Vector Single-Width Floating-Point Add/Subtract Instructions
6157 ;; - 13.4 Vector Single-Width Floating-Point Multiply/Divide Instructions
6158 ;; - 13.11 Vector Floating-Point MIN/MAX Instructions
6159 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions
6160 ;; -------------------------------------------------------------------------------
6162 (define_insn "@pred_<optab><mode>"
6163 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6164 (if_then_else:V_VLSF
6165 (unspec:<VM>
6166 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6167 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6168 (match_operand 6 "const_int_operand" " i, i, i, i")
6169 (match_operand 7 "const_int_operand" " i, i, i, i")
6170 (match_operand 8 "const_int_operand" " i, i, i, i")
6171 (match_operand 9 "const_int_operand" " i, i, i, i")
6172 (reg:SI VL_REGNUM)
6173 (reg:SI VTYPE_REGNUM)
6174 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6175 (any_float_binop:V_VLSF
6176 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6177 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6178 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6179 "TARGET_VECTOR"
6180 "vf<insn>.vv\t%0,%3,%4%p1"
6181 [(set_attr "type" "<float_insn_type>")
6182 (set_attr "mode" "<MODE>")
6183 (set (attr "frm_mode")
6184 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6186 (define_insn "@pred_<optab><mode>"
6187 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6188 (if_then_else:V_VLSF
6189 (unspec:<VM>
6190 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6191 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6192 (match_operand 6 "const_int_operand" " i, i, i, i")
6193 (match_operand 7 "const_int_operand" " i, i, i, i")
6194 (match_operand 8 "const_int_operand" " i, i, i, i")
6195 (reg:SI VL_REGNUM)
6196 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6197 (any_float_binop_nofrm:V_VLSF
6198 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6199 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6200 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6201 "TARGET_VECTOR"
6202 "vf<insn>.vv\t%0,%3,%4%p1"
6203 [(set_attr "type" "<float_insn_type>")
6204 (set_attr "mode" "<MODE>")])
6206 (define_insn "@pred_<ieee_fmaxmin_op><mode>"
6207 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6208 (if_then_else:V_VLSF
6209 (unspec:<VM>
6210 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6211 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6212 (match_operand 6 "const_int_operand" " i, i, i, i")
6213 (match_operand 7 "const_int_operand" " i, i, i, i")
6214 (match_operand 8 "const_int_operand" " i, i, i, i")
6215 (reg:SI VL_REGNUM)
6216 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6217 (unspec:V_VLSF
6218 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6219 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")]
6220 UNSPEC_VFMAXMIN)
6221 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6222 "TARGET_VECTOR"
6223 "v<ieee_fmaxmin_op>.vv\t%0,%3,%4%p1"
6224 [(set_attr "type" "vfminmax")
6225 (set_attr "mode" "<MODE>")])
6227 (define_insn "@pred_<optab><mode>_scalar"
6228 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6229 (if_then_else:VF
6230 (unspec:<VM>
6231 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6232 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6233 (match_operand 6 "const_int_operand" " i, i, i, i")
6234 (match_operand 7 "const_int_operand" " i, i, i, i")
6235 (match_operand 8 "const_int_operand" " i, i, i, i")
6236 (match_operand 9 "const_int_operand" " i, i, i, i")
6237 (reg:SI VL_REGNUM)
6238 (reg:SI VTYPE_REGNUM)
6239 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6240 (commutative_float_binop:VF
6241 (vec_duplicate:VF
6242 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6243 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6244 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6245 "TARGET_VECTOR"
6246 "vf<insn>.vf\t%0,%3,%4%p1"
6247 [(set_attr "type" "<float_insn_type>")
6248 (set_attr "mode" "<MODE>")
6249 (set (attr "frm_mode")
6250 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6252 (define_insn "@pred_<optab><mode>_scalar"
6253 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6254 (if_then_else:VF
6255 (unspec:<VM>
6256 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6257 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6258 (match_operand 6 "const_int_operand" " i, i, i, i")
6259 (match_operand 7 "const_int_operand" " i, i, i, i")
6260 (match_operand 8 "const_int_operand" " i, i, i, i")
6261 (reg:SI VL_REGNUM)
6262 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6263 (commutative_float_binop_nofrm:VF
6264 (vec_duplicate:VF
6265 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6266 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6267 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6268 "TARGET_VECTOR"
6269 "vf<insn>.vf\t%0,%3,%4%p1"
6270 [(set_attr "type" "<float_insn_type>")
6271 (set_attr "mode" "<MODE>")])
6273 (define_insn "@pred_<ieee_fmaxmin_op><mode>_scalar"
6274 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6275 (if_then_else:VF
6276 (unspec:<VM>
6277 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6278 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6279 (match_operand 6 "const_int_operand" " i, i, i, i")
6280 (match_operand 7 "const_int_operand" " i, i, i, i")
6281 (match_operand 8 "const_int_operand" " i, i, i, i")
6282 (reg:SI VL_REGNUM)
6283 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6284 (unspec:VF
6285 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6286 (vec_duplicate:VF
6287 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))]
6288 UNSPEC_VFMAXMIN)
6289 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6290 "TARGET_VECTOR"
6291 "v<ieee_fmaxmin_op>.vf\t%0,%3,%4%p1"
6292 [(set_attr "type" "vfminmax")
6293 (set_attr "mode" "<MODE>")])
6295 (define_insn "@pred_<optab><mode>_scalar"
6296 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6297 (if_then_else:VF
6298 (unspec:<VM>
6299 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6300 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6301 (match_operand 6 "const_int_operand" " i, i, i, i")
6302 (match_operand 7 "const_int_operand" " i, i, i, i")
6303 (match_operand 8 "const_int_operand" " i, i, i, i")
6304 (match_operand 9 "const_int_operand" " i, i, i, i")
6305 (reg:SI VL_REGNUM)
6306 (reg:SI VTYPE_REGNUM)
6307 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6308 (non_commutative_float_binop:VF
6309 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6310 (vec_duplicate:VF
6311 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")))
6312 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6313 "TARGET_VECTOR"
6314 "vf<insn>.vf\t%0,%3,%4%p1"
6315 [(set_attr "type" "<float_insn_type>")
6316 (set_attr "mode" "<MODE>")
6317 (set (attr "frm_mode")
6318 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6320 (define_insn "@pred_<optab><mode>_reverse_scalar"
6321 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6322 (if_then_else:VF
6323 (unspec:<VM>
6324 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6325 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6326 (match_operand 6 "const_int_operand" " i, i, i, i")
6327 (match_operand 7 "const_int_operand" " i, i, i, i")
6328 (match_operand 8 "const_int_operand" " i, i, i, i")
6329 (match_operand 9 "const_int_operand" " i, i, i, i")
6330 (reg:SI VL_REGNUM)
6331 (reg:SI VTYPE_REGNUM)
6332 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6333 (non_commutative_float_binop:VF
6334 (vec_duplicate:VF
6335 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))
6336 (match_operand:VF 3 "register_operand" " vr, vr, vr, vr"))
6337 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6338 "TARGET_VECTOR"
6339 "vfr<insn>.vf\t%0,%3,%4%p1"
6340 [(set_attr "type" "<float_insn_type>")
6341 (set_attr "mode" "<MODE>")
6342 (set (attr "frm_mode")
6343 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6345 (define_insn "@pred_<copysign><mode>"
6346 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6347 (if_then_else:V_VLSF
6348 (unspec:<VM>
6349 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6350 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6351 (match_operand 6 "const_int_operand" " i, i, i, i")
6352 (match_operand 7 "const_int_operand" " i, i, i, i")
6353 (match_operand 8 "const_int_operand" " i, i, i, i")
6354 (reg:SI VL_REGNUM)
6355 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6356 (unspec:V_VLSF
6357 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6358 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS)
6359 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6360 "TARGET_VECTOR"
6361 "vfsgnj<nx>.vv\t%0,%3,%4%p1"
6362 [(set_attr "type" "vfsgnj")
6363 (set_attr "mode" "<MODE>")])
6365 (define_insn "@pred_ncopysign<mode>"
6366 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6367 (if_then_else:VF
6368 (unspec:<VM>
6369 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6370 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6371 (match_operand 6 "const_int_operand" " i, i, i, i")
6372 (match_operand 7 "const_int_operand" " i, i, i, i")
6373 (match_operand 8 "const_int_operand" " i, i, i, i")
6374 (reg:SI VL_REGNUM)
6375 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6376 (neg:VF
6377 (unspec:VF
6378 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6379 (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] UNSPEC_VCOPYSIGN))
6380 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6381 "TARGET_VECTOR"
6382 "vfsgnjn.vv\t%0,%3,%4%p1"
6383 [(set_attr "type" "vfsgnj")
6384 (set_attr "mode" "<MODE>")])
6386 (define_insn "@pred_<copysign><mode>_scalar"
6387 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6388 (if_then_else:V_VLSF
6389 (unspec:<VM>
6390 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6391 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6392 (match_operand 6 "const_int_operand" " i, i, i, i")
6393 (match_operand 7 "const_int_operand" " i, i, i, i")
6394 (match_operand 8 "const_int_operand" " i, i, i, i")
6395 (reg:SI VL_REGNUM)
6396 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6397 (unspec:V_VLSF
6398 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
6399 (vec_duplicate:V_VLSF
6400 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS)
6401 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6402 "TARGET_VECTOR"
6403 "vfsgnj<nx>.vf\t%0,%3,%4%p1"
6404 [(set_attr "type" "vfsgnj")
6405 (set_attr "mode" "<MODE>")])
6407 (define_insn "@pred_ncopysign<mode>_scalar"
6408 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6409 (if_then_else:VF
6410 (unspec:<VM>
6411 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6412 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6413 (match_operand 6 "const_int_operand" " i, i, i, i")
6414 (match_operand 7 "const_int_operand" " i, i, i, i")
6415 (match_operand 8 "const_int_operand" " i, i, i, i")
6416 (reg:SI VL_REGNUM)
6417 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6418 (neg:VF
6419 (unspec:VF
6420 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")
6421 (vec_duplicate:VF
6422 (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] UNSPEC_VCOPYSIGN))
6423 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6424 "TARGET_VECTOR"
6425 "vfsgnjn.vf\t%0,%3,%4%p1"
6426 [(set_attr "type" "vfsgnj")
6427 (set_attr "mode" "<MODE>")])
6429 ;; -------------------------------------------------------------------------------
6430 ;; ---- Predicated floating-point ternary operations
6431 ;; -------------------------------------------------------------------------------
6432 ;; Includes:
6433 ;; - 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions
6434 ;; -------------------------------------------------------------------------------
6436 (define_expand "@pred_mul_<optab><mode>"
6437 [(set (match_operand:V_VLSF 0 "register_operand")
6438 (if_then_else:V_VLSF
6439 (unspec:<VM>
6440 [(match_operand:<VM> 1 "vector_mask_operand")
6441 (match_operand 6 "vector_length_operand")
6442 (match_operand 7 "const_int_operand")
6443 (match_operand 8 "const_int_operand")
6444 (match_operand 9 "const_int_operand")
6445 (match_operand 10 "const_int_operand")
6446 (reg:SI VL_REGNUM)
6447 (reg:SI VTYPE_REGNUM)
6448 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6449 (plus_minus:V_VLSF
6450 (mult:V_VLSF
6451 (match_operand:V_VLSF 2 "register_operand")
6452 (match_operand:V_VLSF 3 "register_operand"))
6453 (match_operand:V_VLSF 4 "register_operand"))
6454 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6455 "TARGET_VECTOR"
6456 {
6457 riscv_vector::prepare_ternary_operands (operands);
6458 })
6460 (define_insn "*pred_mul_<optab><mode>_undef"
6461 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6462 (if_then_else:V_VLSF
6463 (unspec:<VM>
6464 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6465 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6466 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6467 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6468 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6469 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6470 (reg:SI VL_REGNUM)
6471 (reg:SI VTYPE_REGNUM)
6472 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6473 (plus_minus:V_VLSF
6474 (mult:V_VLSF
6475 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6476 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr"))
6477 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6478 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6479 "TARGET_VECTOR"
6480 "@
6481 vf<madd_msub>.vv\t%0,%4,%5%p1
6482 vf<macc_msac>.vv\t%0,%3,%4%p1
6483 vmv.v.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1
6484 vf<madd_msub>.vv\t%0,%4,%5%p1
6485 vf<macc_msac>.vv\t%0,%3,%4%p1
6486 vmv.v.v\t%0,%3\;vf<madd_msub>.vv\t%0,%4,%5%p1"
6487 [(set_attr "type" "vfmuladd")
6488 (set_attr "mode" "<MODE>")
6489 (set (attr "frm_mode")
6490 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6492 (define_insn "*pred_<madd_msub><mode>"
6493 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6494 (if_then_else:V_VLSF
6495 (unspec:<VM>
6496 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6497 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6498 (match_operand 6 "const_int_operand" " i, i, i, i")
6499 (match_operand 7 "const_int_operand" " i, i, i, i")
6500 (match_operand 8 "const_int_operand" " i, i, i, i")
6501 (match_operand 9 "const_int_operand" " i, i, i, i")
6502 (reg:SI VL_REGNUM)
6503 (reg:SI VTYPE_REGNUM)
6504 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6505 (plus_minus:V_VLSF
6506 (mult:V_VLSF
6507 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6508 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6509 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6510 (match_dup 2)))]
6511 "TARGET_VECTOR"
6512 "@
6513 vf<madd_msub>.vv\t%0,%3,%4%p1
6514 vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1
6515 vf<madd_msub>.vv\t%0,%3,%4%p1
6516 vmv.v.v\t%0,%2\;vf<madd_msub>.vv\t%0,%3,%4%p1"
6517 [(set_attr "type" "vfmuladd")
6518 (set_attr "mode" "<MODE>")
6519 (set_attr "merge_op_idx" "4")
6520 (set_attr "vl_op_idx" "5")
6521 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6522 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6523 (set (attr "avl_type_idx") (const_int 8))
6524 (set (attr "frm_mode")
6525 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6527 (define_insn "*pred_<macc_msac><mode>"
6528 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6529 (if_then_else:V_VLSF
6530 (unspec:<VM>
6531 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6532 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6533 (match_operand 6 "const_int_operand" " i, i, i, i")
6534 (match_operand 7 "const_int_operand" " i, i, i, i")
6535 (match_operand 8 "const_int_operand" " i, i, i, i")
6536 (match_operand 9 "const_int_operand" " i, i, i, i")
6537 (reg:SI VL_REGNUM)
6538 (reg:SI VTYPE_REGNUM)
6539 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6540 (plus_minus:V_VLSF
6541 (mult:V_VLSF
6542 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6543 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6544 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6545 (match_dup 4)))]
6546 "TARGET_VECTOR"
6547 "@
6548 vf<macc_msac>.vv\t%0,%2,%3%p1
6549 vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1
6550 vf<macc_msac>.vv\t%0,%2,%3%p1
6551 vmv.v.v\t%0,%4\;vf<macc_msac>.vv\t%0,%2,%3%p1"
6552 [(set_attr "type" "vfmuladd")
6553 (set_attr "mode" "<MODE>")
6554 (set_attr "merge_op_idx" "2")
6555 (set_attr "vl_op_idx" "5")
6556 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6557 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6558 (set (attr "avl_type_idx") (const_int 8))
6559 (set (attr "frm_mode")
6560 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6562 (define_expand "@pred_mul_<optab><mode>_scalar"
6563 [(set (match_operand:V_VLSF 0 "register_operand")
6564 (if_then_else:V_VLSF
6565 (unspec:<VM>
6566 [(match_operand:<VM> 1 "vector_mask_operand")
6567 (match_operand 6 "vector_length_operand")
6568 (match_operand 7 "const_int_operand")
6569 (match_operand 8 "const_int_operand")
6570 (match_operand 9 "const_int_operand")
6571 (match_operand 10 "const_int_operand")
6572 (reg:SI VL_REGNUM)
6573 (reg:SI VTYPE_REGNUM)
6574 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6575 (plus_minus:V_VLSF
6576 (mult:V_VLSF
6577 (vec_duplicate:V_VLSF
6578 (match_operand:<VEL> 2 "register_operand"))
6579 (match_operand:V_VLSF 3 "register_operand"))
6580 (match_operand:V_VLSF 4 "register_operand"))
6581 (match_operand:V_VLSF 5 "register_operand")))]
6582 "TARGET_VECTOR"
6583 {})
6585 (define_insn "*pred_<madd_msub><mode>_scalar"
6586 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6587 (if_then_else:V_VLSF
6588 (unspec:<VM>
6589 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6590 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6591 (match_operand 6 "const_int_operand" " i, i, i, i")
6592 (match_operand 7 "const_int_operand" " i, i, i, i")
6593 (match_operand 8 "const_int_operand" " i, i, i, i")
6594 (match_operand 9 "const_int_operand" " i, i, i, i")
6595 (reg:SI VL_REGNUM)
6596 (reg:SI VTYPE_REGNUM)
6597 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6598 (plus_minus:V_VLSF
6599 (mult:V_VLSF
6600 (vec_duplicate:V_VLSF
6601 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6602 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr"))
6603 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6604 (match_dup 3)))]
6605 "TARGET_VECTOR"
6606 "@
6607 vf<madd_msub>.vf\t%0,%2,%4%p1
6608 vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1
6609 vf<madd_msub>.vf\t%0,%2,%4%p1
6610 vmv.v.v\t%0,%3\;vf<madd_msub>.vf\t%0,%2,%4%p1"
6611 [(set_attr "type" "vfmuladd")
6612 (set_attr "mode" "<MODE>")
6613 (set_attr "merge_op_idx" "4")
6614 (set_attr "vl_op_idx" "5")
6615 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6616 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6617 (set (attr "avl_type_idx") (const_int 8))
6618 (set (attr "frm_mode")
6619 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6621 (define_insn "*pred_<macc_msac><mode>_scalar"
6622 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6623 (if_then_else:V_VLSF
6624 (unspec:<VM>
6625 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6626 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6627 (match_operand 6 "const_int_operand" " i, i, i, i")
6628 (match_operand 7 "const_int_operand" " i, i, i, i")
6629 (match_operand 8 "const_int_operand" " i, i, i, i")
6630 (match_operand 9 "const_int_operand" " i, i, i, i")
6631 (reg:SI VL_REGNUM)
6632 (reg:SI VTYPE_REGNUM)
6633 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6634 (plus_minus:V_VLSF
6635 (mult:V_VLSF
6636 (vec_duplicate:V_VLSF
6637 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6638 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6639 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6640 (match_dup 4)))]
6641 "TARGET_VECTOR"
6642 "@
6643 vf<macc_msac>.vf\t%0,%2,%3%p1
6644 vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1
6645 vf<macc_msac>.vf\t%0,%2,%3%p1
6646 vmv.v.v\t%0,%4\;vf<macc_msac>.vf\t%0,%2,%3%p1"
6647 [(set_attr "type" "vfmuladd")
6648 (set_attr "mode" "<MODE>")
6649 (set_attr "merge_op_idx" "2")
6650 (set_attr "vl_op_idx" "5")
6651 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6652 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6653 (set (attr "avl_type_idx") (const_int 8))
6654 (set (attr "frm_mode")
6655 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6657 (define_expand "@pred_mul_neg_<optab><mode>"
6658 [(set (match_operand:V_VLSF 0 "register_operand")
6659 (if_then_else:V_VLSF
6660 (unspec:<VM>
6661 [(match_operand:<VM> 1 "vector_mask_operand")
6662 (match_operand 6 "vector_length_operand")
6663 (match_operand 7 "const_int_operand")
6664 (match_operand 8 "const_int_operand")
6665 (match_operand 9 "const_int_operand")
6666 (match_operand 10 "const_int_operand")
6667 (reg:SI VL_REGNUM)
6668 (reg:SI VTYPE_REGNUM)
6669 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6670 (plus_minus:V_VLSF
6671 (neg:V_VLSF
6672 (mult:V_VLSF
6673 (match_operand:V_VLSF 2 "register_operand")
6674 (match_operand:V_VLSF 3 "register_operand")))
6675 (match_operand:V_VLSF 4 "register_operand"))
6676 (match_operand:V_VLSF 5 "vector_merge_operand")))]
6677 "TARGET_VECTOR"
6678 {
6679 riscv_vector::prepare_ternary_operands (operands);
6680 })
6682 (define_insn "*pred_mul_neg_<optab><mode>_undef"
6683 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd,?&vd, vr, vr,?&vr")
6684 (if_then_else:V_VLSF
6685 (unspec:<VM>
6686 [(match_operand:<VM> 1 "vector_mask_operand" " vm,vm, vm,Wc1,Wc1, Wc1")
6687 (match_operand 6 "vector_length_operand" " rK,rK, rK, rK, rK, rK")
6688 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
6689 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
6690 (match_operand 9 "const_int_operand" " i, i, i, i, i, i")
6691 (match_operand 10 "const_int_operand" " i, i, i, i, i, i")
6692 (reg:SI VL_REGNUM)
6693 (reg:SI VTYPE_REGNUM)
6694 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6695 (plus_minus:V_VLSF
6696 (neg:V_VLSF
6697 (mult:V_VLSF
6698 (match_operand:V_VLSF 3 "register_operand" " 0,vr, vr, 0, vr, vr")
6699 (match_operand:V_VLSF 4 "register_operand" " vr,vr, vr, vr, vr, vr")))
6700 (match_operand:V_VLSF 5 "register_operand" " vr, 0, vr, vr, 0, vr"))
6701 (match_operand:V_VLSF 2 "vector_undef_operand")))]
6702 "TARGET_VECTOR"
6703 "@
6704 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6705 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6706 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6707 vf<nmsub_nmadd>.vv\t%0,%4,%5%p1
6708 vf<nmsac_nmacc>.vv\t%0,%3,%4%p1
6709 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vv\t%0,%4,%5%p1"
6710 [(set_attr "type" "vfmuladd")
6711 (set_attr "mode" "<MODE>")
6712 (set (attr "frm_mode")
6713 (symbol_ref "riscv_vector::get_frm_mode (operands[10])"))])
6715 (define_insn "*pred_<nmsub_nmadd><mode>"
6716 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6717 (if_then_else:V_VLSF
6718 (unspec:<VM>
6719 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6720 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6721 (match_operand 6 "const_int_operand" " i, i, i, i")
6722 (match_operand 7 "const_int_operand" " i, i, i, i")
6723 (match_operand 8 "const_int_operand" " i, i, i, i")
6724 (match_operand 9 "const_int_operand" " i, i, i, i")
6725 (reg:SI VL_REGNUM)
6726 (reg:SI VTYPE_REGNUM)
6727 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6728 (plus_minus:V_VLSF
6729 (neg:V_VLSF
6730 (mult:V_VLSF
6731 (match_operand:V_VLSF 2 "register_operand" " 0, vr, 0, vr")
6732 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6733 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6734 (match_dup 2)))]
6735 "TARGET_VECTOR"
6736 "@
6737 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6738 vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6739 vf<nmsub_nmadd>.vv\t%0,%3,%4%p1
6740 vmv.v.v\t%0,%2\;vf<nmsub_nmadd>.vv\t%0,%3,%4%p1"
6741 [(set_attr "type" "vfmuladd")
6742 (set_attr "mode" "<MODE>")
6743 (set_attr "merge_op_idx" "4")
6744 (set_attr "vl_op_idx" "5")
6745 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6746 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6747 (set (attr "avl_type_idx") (const_int 8))
6748 (set (attr "frm_mode")
6749 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6751 (define_insn "*pred_<nmsac_nmacc><mode>"
6752 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6753 (if_then_else:V_VLSF
6754 (unspec:<VM>
6755 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6756 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6757 (match_operand 6 "const_int_operand" " i, i, i, i")
6758 (match_operand 7 "const_int_operand" " i, i, i, i")
6759 (match_operand 8 "const_int_operand" " i, i, i, i")
6760 (match_operand 9 "const_int_operand" " i, i, i, i")
6761 (reg:SI VL_REGNUM)
6762 (reg:SI VTYPE_REGNUM)
6763 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6764 (plus_minus:V_VLSF
6765 (neg:V_VLSF
6766 (mult:V_VLSF
6767 (match_operand:V_VLSF 2 "register_operand" " vr, vr, vr, vr")
6768 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6769 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6770 (match_dup 4)))]
6771 "TARGET_VECTOR"
6772 "@
6773 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6774 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6775 vf<nmsac_nmacc>.vv\t%0,%2,%3%p1
6776 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vv\t%0,%2,%3%p1"
6777 [(set_attr "type" "vfmuladd")
6778 (set_attr "mode" "<MODE>")
6779 (set_attr "merge_op_idx" "2")
6780 (set_attr "vl_op_idx" "5")
6781 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6782 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6783 (set (attr "avl_type_idx") (const_int 8))
6784 (set (attr "frm_mode")
6785 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6787 (define_expand "@pred_mul_neg_<optab><mode>_scalar"
6788 [(set (match_operand:V_VLSF 0 "register_operand")
6789 (if_then_else:V_VLSF
6790 (unspec:<VM>
6791 [(match_operand:<VM> 1 "vector_mask_operand")
6792 (match_operand 6 "vector_length_operand")
6793 (match_operand 7 "const_int_operand")
6794 (match_operand 8 "const_int_operand")
6795 (match_operand 9 "const_int_operand")
6796 (match_operand 10 "const_int_operand")
6797 (reg:SI VL_REGNUM)
6798 (reg:SI VTYPE_REGNUM)
6799 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6800 (plus_minus:V_VLSF
6801 (neg:V_VLSF
6802 (mult:V_VLSF
6803 (vec_duplicate:V_VLSF
6804 (match_operand:<VEL> 2 "register_operand"))
6805 (match_operand:V_VLSF 3 "register_operand")))
6806 (match_operand:V_VLSF 4 "register_operand"))
6807 (match_operand:V_VLSF 5 "register_operand")))]
6808 "TARGET_VECTOR"
6809 {})
6811 (define_insn "*pred_<nmsub_nmadd><mode>_scalar"
6812 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6813 (if_then_else:V_VLSF
6814 (unspec:<VM>
6815 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6816 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6817 (match_operand 6 "const_int_operand" " i, i, i, i")
6818 (match_operand 7 "const_int_operand" " i, i, i, i")
6819 (match_operand 8 "const_int_operand" " i, i, i, i")
6820 (match_operand 9 "const_int_operand" " i, i, i, i")
6821 (reg:SI VL_REGNUM)
6822 (reg:SI VTYPE_REGNUM)
6823 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6824 (plus_minus:V_VLSF
6825 (neg:V_VLSF
6826 (mult:V_VLSF
6827 (vec_duplicate:V_VLSF
6828 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6829 (match_operand:V_VLSF 3 "register_operand" " 0, vr, 0, vr")))
6830 (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr"))
6831 (match_dup 3)))]
6832 "TARGET_VECTOR"
6833 "@
6834 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6835 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6836 vf<nmsub_nmadd>.vf\t%0,%2,%4%p1
6837 vmv.v.v\t%0,%3\;vf<nmsub_nmadd>.vf\t%0,%2,%4%p1"
6838 [(set_attr "type" "vfmuladd")
6839 (set_attr "mode" "<MODE>")
6840 (set_attr "merge_op_idx" "4")
6841 (set_attr "vl_op_idx" "5")
6842 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6843 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6844 (set (attr "avl_type_idx") (const_int 8))
6845 (set (attr "frm_mode")
6846 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6848 (define_insn "*pred_<nmsac_nmacc><mode>_scalar"
6849 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, ?&vd, vr, ?&vr")
6850 (if_then_else:V_VLSF
6851 (unspec:<VM>
6852 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1, Wc1")
6853 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
6854 (match_operand 6 "const_int_operand" " i, i, i, i")
6855 (match_operand 7 "const_int_operand" " i, i, i, i")
6856 (match_operand 8 "const_int_operand" " i, i, i, i")
6857 (match_operand 9 "const_int_operand" " i, i, i, i")
6858 (reg:SI VL_REGNUM)
6859 (reg:SI VTYPE_REGNUM)
6860 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6861 (plus_minus:V_VLSF
6862 (neg:V_VLSF
6863 (mult:V_VLSF
6864 (vec_duplicate:V_VLSF
6865 (match_operand:<VEL> 2 "register_operand" " f, f, f, f"))
6866 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")))
6867 (match_operand:V_VLSF 4 "register_operand" " 0, vr, 0, vr"))
6868 (match_dup 4)))]
6869 "TARGET_VECTOR"
6870 "@
6871 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6872 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6873 vf<nmsac_nmacc>.vf\t%0,%2,%3%p1
6874 vmv.v.v\t%0,%4\;vf<nmsac_nmacc>.vf\t%0,%2,%3%p1"
6875 [(set_attr "type" "vfmuladd")
6876 (set_attr "mode" "<MODE>")
6877 (set_attr "merge_op_idx" "2")
6878 (set_attr "vl_op_idx" "5")
6879 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])"))
6880 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])"))
6881 (set (attr "avl_type_idx") (const_int 8))
6882 (set (attr "frm_mode")
6883 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
6885 ;; -------------------------------------------------------------------------------
6886 ;; ---- Predicated floating-point unary operations
6887 ;; -------------------------------------------------------------------------------
6888 ;; Includes:
6889 ;; - 13.8 Vector Floating-Point Square-Root Instruction
6890 ;; - 13.9 Vector Floating-Point Reciprocal Square-Root Estimate Instruction
6891 ;; - 13.10 Vector Floating-Point Reciprocal Estimate Instruction
6892 ;; - 13.12 Vector Floating-Point Sign-Injection Instructions (vfneg.v/vfabs.v)
6893 ;; - 13.14 Vector Floating-Point Classify Instruction
6894 ;; -------------------------------------------------------------------------------
6896 (define_insn "@pred_<optab><mode>"
6897 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6898 (if_then_else:V_VLSF
6899 (unspec:<VM>
6900 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6901 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6902 (match_operand 5 "const_int_operand" " i, i, i, i")
6903 (match_operand 6 "const_int_operand" " i, i, i, i")
6904 (match_operand 7 "const_int_operand" " i, i, i, i")
6905 (match_operand 8 "const_int_operand" " i, i, i, i")
6906 (reg:SI VL_REGNUM)
6907 (reg:SI VTYPE_REGNUM)
6908 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6909 (any_float_unop:V_VLSF
6910 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6911 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6912 "TARGET_VECTOR"
6913 "vf<insn>.v\t%0,%3%p1"
6914 [(set_attr "type" "<float_insn_type>")
6915 (set_attr "mode" "<MODE>")
6916 (set_attr "vl_op_idx" "4")
6917 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6918 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6919 (set (attr "avl_type_idx") (const_int 7))
6920 (set (attr "frm_mode")
6921 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6923 (define_insn "@pred_<optab><mode>"
6924 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
6925 (if_then_else:V_VLSF
6926 (unspec:<VM>
6927 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6928 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6929 (match_operand 5 "const_int_operand" " i, i, i, i")
6930 (match_operand 6 "const_int_operand" " i, i, i, i")
6931 (match_operand 7 "const_int_operand" " i, i, i, i")
6932 (reg:SI VL_REGNUM)
6933 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6934 (any_float_unop_nofrm:V_VLSF
6935 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
6936 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6937 "TARGET_VECTOR"
6938 "vf<insn>.v\t%0,%3%p1"
6939 [(set_attr "type" "<float_insn_type>")
6940 (set_attr "mode" "<MODE>")
6941 (set_attr "vl_op_idx" "4")
6942 (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[5])"))
6943 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
6944 (set (attr "avl_type_idx") (const_int 7))])
6946 (define_insn "@pred_<misc_op><mode>"
6947 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6948 (if_then_else:VF
6949 (unspec:<VM>
6950 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6951 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6952 (match_operand 5 "const_int_operand" " i, i, i, i")
6953 (match_operand 6 "const_int_operand" " i, i, i, i")
6954 (match_operand 7 "const_int_operand" " i, i, i, i")
6955 (reg:SI VL_REGNUM)
6956 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6957 (unspec:VF
6958 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC)
6959 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6960 "TARGET_VECTOR"
6961 "vf<misc_op>.v\t%0,%3%p1"
6962 [(set_attr "type" "<float_insn_type>")
6963 (set_attr "mode" "<MODE>")])
6965 (define_insn "@pred_<misc_frm_op><mode>"
6966 [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr")
6967 (if_then_else:VF
6968 (unspec:<VM>
6969 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6970 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6971 (match_operand 5 "const_int_operand" " i, i, i, i")
6972 (match_operand 6 "const_int_operand" " i, i, i, i")
6973 (match_operand 7 "const_int_operand" " i, i, i, i")
6974 (match_operand 8 "const_int_operand" " i, i, i, i")
6975 (reg:SI VL_REGNUM)
6976 (reg:SI VTYPE_REGNUM)
6977 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
6978 (unspec:VF
6979 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] VFMISC_FRM)
6980 (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
6981 "TARGET_VECTOR"
6982 "vf<misc_frm_op>.v\t%0,%3%p1"
6983 [(set_attr "type" "<float_frm_insn_type>")
6984 (set_attr "mode" "<MODE>")
6985 (set (attr "frm_mode")
6986 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
6988 (define_insn "@pred_class<mode>"
6989 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
6990 (if_then_else:<VCONVERT>
6991 (unspec:<VM>
6992 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
6993 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
6994 (match_operand 5 "const_int_operand" " i, i, i, i")
6995 (match_operand 6 "const_int_operand" " i, i, i, i")
6996 (match_operand 7 "const_int_operand" " i, i, i, i")
6997 (reg:SI VL_REGNUM)
6998 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
6999 (unspec:<VCONVERT>
7000 [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr")] UNSPEC_VFCLASS)
7001 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7002 "TARGET_VECTOR"
7003 "vfclass.v\t%0,%3%p1"
7004 [(set_attr "type" "vfclass")
7005 (set_attr "mode" "<MODE>")])
7007 ;; -------------------------------------------------------------------------------
7008 ;; ---- Predicated floating-point widen binary operations
7009 ;; -------------------------------------------------------------------------------
7010 ;; Includes:
7011 ;; - 13.3 Vector Widening Floating-Point Add/Subtract Instructions
7012 ;; - 13.5 Vector Widening Floating-Point Multiply
7013 ;; -------------------------------------------------------------------------------
7015 ;; Vector Widening Add/Subtract/Multiply.
7016 (define_insn "@pred_dual_widen_<optab><mode>"
7017 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7018 (if_then_else:VWEXTF
7019 (unspec:<VM>
7020 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7021 (match_operand 5 "vector_length_operand" " rK, rK")
7022 (match_operand 6 "const_int_operand" " i, i")
7023 (match_operand 7 "const_int_operand" " i, i")
7024 (match_operand 8 "const_int_operand" " i, i")
7025 (match_operand 9 "const_int_operand" " i, i")
7026 (reg:SI VL_REGNUM)
7027 (reg:SI VTYPE_REGNUM)
7028 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7029 (any_widen_binop:VWEXTF
7030 (float_extend:VWEXTF
7031 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7032 (float_extend:VWEXTF
7033 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7034 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7035 "TARGET_VECTOR"
7036 "vfw<insn>.vv\t%0,%3,%4%p1"
7037 [(set_attr "type" "vf<widen_binop_insn_type>")
7038 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7039 (set (attr "frm_mode")
7040 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7042 (define_insn "@pred_dual_widen_<optab><mode>_scalar"
7043 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7044 (if_then_else:VWEXTF
7045 (unspec:<VM>
7046 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7047 (match_operand 5 "vector_length_operand" " rK, rK")
7048 (match_operand 6 "const_int_operand" " i, i")
7049 (match_operand 7 "const_int_operand" " i, i")
7050 (match_operand 8 "const_int_operand" " i, i")
7051 (match_operand 9 "const_int_operand" " i, i")
7052 (reg:SI VL_REGNUM)
7053 (reg:SI VTYPE_REGNUM)
7054 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7055 (any_widen_binop:VWEXTF
7056 (float_extend:VWEXTF
7057 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr"))
7058 (float_extend:VWEXTF
7059 (vec_duplicate:<V_DOUBLE_TRUNC>
7060 (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
7061 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7062 "TARGET_VECTOR"
7063 "vfw<insn>.vf\t%0,%3,%4%p1"
7064 [(set_attr "type" "vf<widen_binop_insn_type>")
7065 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7066 (set (attr "frm_mode")
7067 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7069 (define_insn "@pred_single_widen_add<mode>"
7070 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7071 (if_then_else:VWEXTF
7072 (unspec:<VM>
7073 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7074 (match_operand 5 "vector_length_operand" " rK, rK")
7075 (match_operand 6 "const_int_operand" " i, i")
7076 (match_operand 7 "const_int_operand" " i, i")
7077 (match_operand 8 "const_int_operand" " i, i")
7078 (match_operand 9 "const_int_operand" " i, i")
7079 (reg:SI VL_REGNUM)
7080 (reg:SI VTYPE_REGNUM)
7081 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7082 (plus:VWEXTF
7083 (float_extend:VWEXTF
7084 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
7085 (match_operand:VWEXTF 3 "register_operand" " vr, vr"))
7086 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7087 "TARGET_VECTOR"
7088 "vfwadd.wv\t%0,%3,%4%p1"
7089 [(set_attr "type" "vfwalu")
7090 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7091 (set (attr "frm_mode")
7092 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7094 (define_insn "@pred_single_widen_sub<mode>"
7095 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
7096 (if_then_else:VWEXTF
7097 (unspec:<VM>
7098 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7099 (match_operand 5 "vector_length_operand" " rK, rK")
7100 (match_operand 6 "const_int_operand" " i, i")
7101 (match_operand 7 "const_int_operand" " i, i")
7102 (match_operand 8 "const_int_operand" " i, i")
7103 (match_operand 9 "const_int_operand" " i, i")
7104 (reg:SI VL_REGNUM)
7105 (reg:SI VTYPE_REGNUM)
7106 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7107 (minus:VWEXTF
7108 (match_operand:VWEXTF 3 "register_operand" " vr, vr")
7109 (float_extend:VWEXTF
7110 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr")))
7111 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7112 "TARGET_VECTOR"
7113 "vfwsub.wv\t%0,%3,%4%p1"
7114 [(set_attr "type" "vfwalu")
7115 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7116 (set (attr "frm_mode")
7117 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7119 (define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
7120 [(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr")
7121 (if_then_else:VWEXTF
7122 (unspec:<VM>
7123 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7124 (match_operand 5 "vector_length_operand" " rK, rK")
7125 (match_operand 6 "const_int_operand" " i, i")
7126 (match_operand 7 "const_int_operand" " i, i")
7127 (match_operand 8 "const_int_operand" " i, i")
7128 (match_operand 9 "const_int_operand" " i, i")
7129 (reg:SI VL_REGNUM)
7130 (reg:SI VTYPE_REGNUM)
7131 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7132 (plus_minus:VWEXTF
7133 (match_operand:VWEXTF 3 "register_operand" " vr, vr")
7134 (float_extend:VWEXTF
7135 (vec_duplicate:<V_DOUBLE_TRUNC>
7136 (match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
7137 (match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
7138 "TARGET_VECTOR"
7139 "vfw<insn>.wf\t%0,%3,%4%p1"
7140 [(set_attr "type" "vf<widen_binop_insn_type>")
7141 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7142 (set (attr "frm_mode")
7143 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7145 ;; -------------------------------------------------------------------------------
7146 ;; ---- Predicated widen floating-point ternary operations
7147 ;; -------------------------------------------------------------------------------
7148 ;; Includes:
7149 ;; - 13.7 Vector Widening Floating-Point Fused Multiply-Add Instructions
7150 ;; -------------------------------------------------------------------------------
7152 (define_insn "@pred_widen_mul_<optab><mode>"
7153 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7154 (if_then_else:VWEXTF
7155 (unspec:<VM>
7156 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7157 (match_operand 5 "vector_length_operand" " rK")
7158 (match_operand 6 "const_int_operand" " i")
7159 (match_operand 7 "const_int_operand" " i")
7160 (match_operand 8 "const_int_operand" " i")
7161 (match_operand 9 "const_int_operand" " i")
7162 (reg:SI VL_REGNUM)
7163 (reg:SI VTYPE_REGNUM)
7164 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7165 (plus_minus:VWEXTF
7166 (mult:VWEXTF
7167 (float_extend:VWEXTF
7168 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7169 (float_extend:VWEXTF
7170 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7171 (match_operand:VWEXTF 2 "register_operand" " 0"))
7172 (match_dup 2)))]
7173 "TARGET_VECTOR"
7174 "vfw<macc_msac>.vv\t%0,%3,%4%p1"
7175 [(set_attr "type" "vfwmuladd")
7176 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7177 (set (attr "frm_mode")
7178 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7180 (define_insn "@pred_widen_mul_<optab><mode>_scalar"
7181 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7182 (if_then_else:VWEXTF
7183 (unspec:<VM>
7184 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7185 (match_operand 5 "vector_length_operand" " rK")
7186 (match_operand 6 "const_int_operand" " i")
7187 (match_operand 7 "const_int_operand" " i")
7188 (match_operand 8 "const_int_operand" " i")
7189 (match_operand 9 "const_int_operand" " i")
7190 (reg:SI VL_REGNUM)
7191 (reg:SI VTYPE_REGNUM)
7192 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7193 (plus_minus:VWEXTF
7194 (mult:VWEXTF
7195 (float_extend:VWEXTF
7196 (vec_duplicate:<V_DOUBLE_TRUNC>
7197 (match_operand:<VSUBEL> 3 "register_operand" " f")))
7198 (float_extend:VWEXTF
7199 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr")))
7200 (match_operand:VWEXTF 2 "register_operand" " 0"))
7201 (match_dup 2)))]
7202 "TARGET_VECTOR"
7203 "vfw<macc_msac>.vf\t%0,%3,%4%p1"
7204 [(set_attr "type" "vfwmuladd")
7205 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7206 (set (attr "frm_mode")
7207 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7209 (define_insn "@pred_widen_mul_neg_<optab><mode>"
7210 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7211 (if_then_else:VWEXTF
7212 (unspec:<VM>
7213 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7214 (match_operand 5 "vector_length_operand" " rK")
7215 (match_operand 6 "const_int_operand" " i")
7216 (match_operand 7 "const_int_operand" " i")
7217 (match_operand 8 "const_int_operand" " i")
7218 (match_operand 9 "const_int_operand" " i")
7219 (reg:SI VL_REGNUM)
7220 (reg:SI VTYPE_REGNUM)
7221 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7222 (plus_minus:VWEXTF
7223 (neg:VWEXTF
7224 (mult:VWEXTF
7225 (float_extend:VWEXTF
7226 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr"))
7227 (float_extend:VWEXTF
7228 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7229 (match_operand:VWEXTF 2 "register_operand" " 0"))
7230 (match_dup 2)))]
7231 "TARGET_VECTOR"
7232 "vfw<nmsac_nmacc>.vv\t%0,%3,%4%p1"
7233 [(set_attr "type" "vfwmuladd")
7234 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7235 (set (attr "frm_mode")
7236 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7238 (define_insn "@pred_widen_mul_neg_<optab><mode>_scalar"
7239 [(set (match_operand:VWEXTF 0 "register_operand" "=&vr")
7240 (if_then_else:VWEXTF
7241 (unspec:<VM>
7242 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1")
7243 (match_operand 5 "vector_length_operand" " rK")
7244 (match_operand 6 "const_int_operand" " i")
7245 (match_operand 7 "const_int_operand" " i")
7246 (match_operand 8 "const_int_operand" " i")
7247 (match_operand 9 "const_int_operand" " i")
7248 (reg:SI VL_REGNUM)
7249 (reg:SI VTYPE_REGNUM)
7250 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7251 (plus_minus:VWEXTF
7252 (neg:VWEXTF
7253 (mult:VWEXTF
7254 (float_extend:VWEXTF
7255 (vec_duplicate:<V_DOUBLE_TRUNC>
7256 (match_operand:<VSUBEL> 3 "register_operand" " f")))
7257 (float_extend:VWEXTF
7258 (match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr"))))
7259 (match_operand:VWEXTF 2 "register_operand" " 0"))
7260 (match_dup 2)))]
7261 "TARGET_VECTOR"
7262 "vfw<nmsac_nmacc>.vf\t%0,%3,%4%p1"
7263 [(set_attr "type" "vfwmuladd")
7264 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7265 (set (attr "frm_mode")
7266 (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
7268 ;; -------------------------------------------------------------------------------
7269 ;; ---- Predicated floating-point comparison operations
7270 ;; -------------------------------------------------------------------------------
7271 ;; Includes:
7272 ;; - 13.13 Vector Floating-Point Compare Instructions
7273 ;; -------------------------------------------------------------------------------
7275 (define_expand "@pred_cmp<mode>"
7276 [(set (match_operand:<VM> 0 "register_operand")
7277 (if_then_else:<VM>
7278 (unspec:<VM>
7279 [(match_operand:<VM> 1 "vector_mask_operand")
7280 (match_operand 6 "vector_length_operand")
7281 (match_operand 7 "const_int_operand")
7282 (match_operand 8 "const_int_operand")
7283 (reg:SI VL_REGNUM)
7284 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7285 (match_operator:<VM> 3 "signed_order_operator"
7286 [(match_operand:V_VLSF 4 "register_operand")
7287 (match_operand:V_VLSF 5 "register_operand")])
7288 (match_operand:<VM> 2 "vector_merge_operand")))]
7289 "TARGET_VECTOR"
7290 {})
7292 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7293 (define_insn "*pred_cmp<mode>"
7294 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7295 (if_then_else:<VM>
7296 (unspec:<VM>
7297 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7298 (match_operand 6 "vector_length_operand" " rK, rK")
7299 (match_operand 7 "const_int_operand" " i, i")
7300 (match_operand 8 "const_int_operand" " i, i")
7301 (reg:SI VL_REGNUM)
7302 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7303 (match_operator:<VM> 3 "signed_order_operator"
7304 [(match_operand:V_VLSF 4 "register_operand" " vr, vr")
7305 (match_operand:V_VLSF 5 "register_operand" " vr, vr")])
7306 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7307 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7308 "vmf%B3.vv\t%0,%4,%5%p1"
7309 [(set_attr "type" "vfcmp")
7310 (set_attr "mode" "<MODE>")])
7312 (define_insn "*pred_cmp<mode>_narrow_merge_tie_mask"
7313 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7314 (if_then_else:<VM>
7315 (unspec:<VM>
7316 [(match_operand:<VM> 1 "register_operand" " 0")
7317 (match_operand 5 "vector_length_operand" " rK")
7318 (match_operand 6 "const_int_operand" " i")
7319 (match_operand 7 "const_int_operand" " i")
7320 (reg:SI VL_REGNUM)
7321 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7322 (match_operator:<VM> 2 "signed_order_operator"
7323 [(match_operand:V_VLSF 3 "register_operand" " vr")
7324 (match_operand:V_VLSF 4 "register_operand" " vr")])
7325 (match_dup 1)))]
7326 "TARGET_VECTOR"
7327 "vmf%B2.vv\t%0,%3,%4,v0.t"
7328 [(set_attr "type" "vfcmp")
7329 (set_attr "mode" "<MODE>")
7330 (set_attr "merge_op_idx" "1")
7331 (set_attr "vl_op_idx" "5")
7332 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7333 (set (attr "avl_type_idx") (const_int 7))])
7335 ;; We use early-clobber for source LMUL > dest LMUL.
7336 (define_insn "*pred_cmp<mode>_narrow"
7337 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, vr, vr, vr, vr, &vr, &vr")
7338 (if_then_else:<VM>
7339 (unspec:<VM>
7340 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7341 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK, rK")
7342 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7343 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i, i")
7344 (reg:SI VL_REGNUM)
7345 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7346 (match_operator:<VM> 3 "signed_order_operator"
7347 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, vr, 0, 0, vr, 0, vr, vr")
7348 (match_operand:V_VLSF 5 "register_operand" " vr, vr, 0, 0, vr, 0, 0, vr, vr")])
7349 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, vu, vu, 0, 0, 0, vu, 0")))]
7350 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7351 "vmf%B3.vv\t%0,%4,%5%p1"
7352 [(set_attr "type" "vfcmp")
7353 (set_attr "mode" "<MODE>")])
7355 (define_expand "@pred_cmp<mode>_scalar"
7356 [(set (match_operand:<VM> 0 "register_operand")
7357 (if_then_else:<VM>
7358 (unspec:<VM>
7359 [(match_operand:<VM> 1 "vector_mask_operand")
7360 (match_operand 6 "vector_length_operand")
7361 (match_operand 7 "const_int_operand")
7362 (match_operand 8 "const_int_operand")
7363 (reg:SI VL_REGNUM)
7364 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7365 (match_operator:<VM> 3 "signed_order_operator"
7366 [(match_operand:V_VLSF 4 "register_operand")
7367 (vec_duplicate:V_VLSF
7368 (match_operand:<VEL> 5 "register_operand"))])
7369 (match_operand:<VM> 2 "vector_merge_operand")))]
7370 "TARGET_VECTOR"
7371 {})
7373 (define_insn "*pred_cmp<mode>_scalar_merge_tie_mask"
7374 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7375 (if_then_else:<VM>
7376 (unspec:<VM>
7377 [(match_operand:<VM> 1 "register_operand" " 0")
7378 (match_operand 5 "vector_length_operand" " rK")
7379 (match_operand 6 "const_int_operand" " i")
7380 (match_operand 7 "const_int_operand" " i")
7381 (reg:SI VL_REGNUM)
7382 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7383 (match_operator:<VM> 2 "signed_order_operator"
7384 [(match_operand:V_VLSF 3 "register_operand" " vr")
7385 (vec_duplicate:V_VLSF
7386 (match_operand:<VEL> 4 "register_operand" " f"))])
7387 (match_dup 1)))]
7388 "TARGET_VECTOR"
7389 "vmf%B2.vf\t%0,%3,%4,v0.t"
7390 [(set_attr "type" "vfcmp")
7391 (set_attr "mode" "<MODE>")
7392 (set_attr "merge_op_idx" "1")
7393 (set_attr "vl_op_idx" "5")
7394 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7395 (set (attr "avl_type_idx") (const_int 7))])
7397 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7398 (define_insn "*pred_cmp<mode>_scalar"
7399 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7400 (if_then_else:<VM>
7401 (unspec:<VM>
7402 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7403 (match_operand 6 "vector_length_operand" " rK, rK")
7404 (match_operand 7 "const_int_operand" " i, i")
7405 (match_operand 8 "const_int_operand" " i, i")
7406 (reg:SI VL_REGNUM)
7407 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7408 (match_operator:<VM> 3 "signed_order_operator"
7409 [(match_operand:V_VLSF 4 "register_operand" " vr, vr")
7410 (vec_duplicate:V_VLSF
7411 (match_operand:<VEL> 5 "register_operand" " f, f"))])
7412 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7413 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7414 "vmf%B3.vf\t%0,%4,%5%p1"
7415 [(set_attr "type" "vfcmp")
7416 (set_attr "mode" "<MODE>")])
7418 ;; We use early-clobber for source LMUL > dest LMUL.
7419 (define_insn "*pred_cmp<mode>_scalar_narrow"
7420 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7421 (if_then_else:<VM>
7422 (unspec:<VM>
7423 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7424 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7425 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7426 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7427 (reg:SI VL_REGNUM)
7428 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7429 (match_operator:<VM> 3 "signed_order_operator"
7430 [(match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")
7431 (vec_duplicate:V_VLSF
7432 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))])
7433 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7434 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7435 "vmf%B3.vf\t%0,%4,%5%p1"
7436 [(set_attr "type" "vfcmp")
7437 (set_attr "mode" "<MODE>")])
7439 (define_expand "@pred_eqne<mode>_scalar"
7440 [(set (match_operand:<VM> 0 "register_operand")
7441 (if_then_else:<VM>
7442 (unspec:<VM>
7443 [(match_operand:<VM> 1 "vector_mask_operand")
7444 (match_operand 6 "vector_length_operand")
7445 (match_operand 7 "const_int_operand")
7446 (match_operand 8 "const_int_operand")
7447 (reg:SI VL_REGNUM)
7448 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7449 (match_operator:<VM> 3 "equality_operator"
7450 [(vec_duplicate:V_VLSF
7451 (match_operand:<VEL> 5 "register_operand"))
7452 (match_operand:V_VLSF 4 "register_operand")])
7453 (match_operand:<VM> 2 "vector_merge_operand")))]
7454 "TARGET_VECTOR"
7455 {})
7457 (define_insn "*pred_eqne<mode>_scalar_merge_tie_mask"
7458 [(set (match_operand:<VM> 0 "register_operand" "=vm")
7459 (if_then_else:<VM>
7460 (unspec:<VM>
7461 [(match_operand:<VM> 1 "register_operand" " 0")
7462 (match_operand 5 "vector_length_operand" " rK")
7463 (match_operand 6 "const_int_operand" " i")
7464 (match_operand 7 "const_int_operand" " i")
7465 (reg:SI VL_REGNUM)
7466 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7467 (match_operator:<VM> 2 "equality_operator"
7468 [(vec_duplicate:V_VLSF
7469 (match_operand:<VEL> 4 "register_operand" " f"))
7470 (match_operand:V_VLSF 3 "register_operand" " vr")])
7471 (match_dup 1)))]
7472 "TARGET_VECTOR"
7473 "vmf%B2.vf\t%0,%3,%4,v0.t"
7474 [(set_attr "type" "vfcmp")
7475 (set_attr "mode" "<MODE>")
7476 (set_attr "merge_op_idx" "1")
7477 (set_attr "vl_op_idx" "5")
7478 (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
7479 (set (attr "avl_type_idx") (const_int 7))])
7481 ;; We don't use early-clobber for LMUL <= 1 to get better codegen.
7482 (define_insn "*pred_eqne<mode>_scalar"
7483 [(set (match_operand:<VM> 0 "register_operand" "=vr, vr")
7484 (if_then_else:<VM>
7485 (unspec:<VM>
7486 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7487 (match_operand 6 "vector_length_operand" " rK, rK")
7488 (match_operand 7 "const_int_operand" " i, i")
7489 (match_operand 8 "const_int_operand" " i, i")
7490 (reg:SI VL_REGNUM)
7491 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7492 (match_operator:<VM> 3 "equality_operator"
7493 [(vec_duplicate:V_VLSF
7494 (match_operand:<VEL> 5 "register_operand" " f, f"))
7495 (match_operand:V_VLSF 4 "register_operand" " vr, vr")])
7496 (match_operand:<VM> 2 "vector_merge_operand" " vu, 0")))]
7497 "TARGET_VECTOR && riscv_vector::cmp_lmul_le_one (<MODE>mode)"
7498 "vmf%B3.vf\t%0,%4,%5%p1"
7499 [(set_attr "type" "vfcmp")
7500 (set_attr "mode" "<MODE>")])
7502 ;; We use early-clobber for source LMUL > dest LMUL.
7503 (define_insn "*pred_eqne<mode>_scalar_narrow"
7504 [(set (match_operand:<VM> 0 "register_operand" "=vm, vr, vr, &vr, &vr")
7505 (if_then_else:<VM>
7506 (unspec:<VM>
7507 [(match_operand:<VM> 1 "vector_mask_operand" " 0,vmWc1,vmWc1,vmWc1,vmWc1")
7508 (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK")
7509 (match_operand 7 "const_int_operand" " i, i, i, i, i")
7510 (match_operand 8 "const_int_operand" " i, i, i, i, i")
7511 (reg:SI VL_REGNUM)
7512 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7513 (match_operator:<VM> 3 "equality_operator"
7514 [(vec_duplicate:V_VLSF
7515 (match_operand:<VEL> 5 "register_operand" " f, f, f, f, f"))
7516 (match_operand:V_VLSF 4 "register_operand" " vr, 0, 0, vr, vr")])
7517 (match_operand:<VM> 2 "vector_merge_operand" " vu, vu, 0, vu, 0")))]
7518 "TARGET_VECTOR && riscv_vector::cmp_lmul_gt_one (<MODE>mode)"
7519 "vmf%B3.vf\t%0,%4,%5%p1"
7520 [(set_attr "type" "vfcmp")
7521 (set_attr "mode" "<MODE>")])
7523 ;; -------------------------------------------------------------------------------
7524 ;; ---- Predicated floating-point merge
7525 ;; -------------------------------------------------------------------------------
7526 ;; Includes:
7527 ;; - 13.15 Vector Floating-Point Merge Instruction
7528 ;; -------------------------------------------------------------------------------
7530 (define_insn "@pred_merge<mode>_scalar"
7531 [(set (match_operand:V_VLSF 0 "register_operand" "=vd,vd")
7532 (if_then_else:V_VLSF
7533 (unspec:<VM>
7534 [(match_operand 5 "vector_length_operand" " rK,rK")
7535 (match_operand 6 "const_int_operand" " i, i")
7536 (match_operand 7 "const_int_operand" " i, i")
7537 (reg:SI VL_REGNUM)
7538 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7539 (vec_merge:V_VLSF
7540 (vec_duplicate:V_VLSF
7541 (match_operand:<VEL> 3 "register_operand" " f, f"))
7542 (match_operand:V_VLSF 2 "register_operand" " vr,vr")
7543 (match_operand:<VM> 4 "register_operand" " vm,vm"))
7544 (match_operand:V_VLSF 1 "vector_merge_operand" " vu, 0")))]
7545 "TARGET_VECTOR"
7546 "vfmerge.vfm\t%0,%2,%3,%4"
7547 [(set_attr "type" "vfmerge")
7548 (set_attr "mode" "<MODE>")])
7550 ;; -------------------------------------------------------------------------------
7551 ;; ---- Predicated floating-point conversions
7552 ;; -------------------------------------------------------------------------------
7553 ;; Includes:
7554 ;; - 13.17 Single-Width Floating-Point/Integer Type-Convert Instructions
7555 ;; -------------------------------------------------------------------------------
7557 (define_insn "@pred_fcvt_x<v_su>_f<mode>"
7558 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7559 (if_then_else:<VCONVERT>
7560 (unspec:<VM>
7561 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7562 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7563 (match_operand 5 "const_int_operand" " i, i, i, i")
7564 (match_operand 6 "const_int_operand" " i, i, i, i")
7565 (match_operand 7 "const_int_operand" " i, i, i, i")
7566 (match_operand 8 "const_int_operand" " i, i, i, i")
7567 (reg:SI VL_REGNUM)
7568 (reg:SI VTYPE_REGNUM)
7569 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7570 (unspec:<VCONVERT>
7571 [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")] VFCVTS)
7572 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7573 "TARGET_VECTOR"
7574 "vfcvt.x<v_su>.f.v\t%0,%3%p1"
7575 [(set_attr "type" "vfcvtftoi")
7576 (set_attr "mode" "<MODE>")
7577 (set (attr "frm_mode")
7578 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7580 (define_insn "@pred_<fix_cvt><mode>"
7581 [(set (match_operand:<VCONVERT> 0 "register_operand" "=vd, vd, vr, vr")
7582 (if_then_else:<VCONVERT>
7583 (unspec:<VM>
7584 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7585 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7586 (match_operand 5 "const_int_operand" " i, i, i, i")
7587 (match_operand 6 "const_int_operand" " i, i, i, i")
7588 (match_operand 7 "const_int_operand" " i, i, i, i")
7589 (reg:SI VL_REGNUM)
7590 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7591 (any_fix:<VCONVERT>
7592 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr"))
7593 (match_operand:<VCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7594 "TARGET_VECTOR"
7595 "vfcvt.rtz.x<u>.f.v\t%0,%3%p1"
7596 [(set_attr "type" "vfcvtftoi")
7597 (set_attr "mode" "<MODE>")])
7599 (define_insn "@pred_<float_cvt><mode>"
7600 [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr")
7601 (if_then_else:V_VLSF
7602 (unspec:<VM>
7603 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
7604 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
7605 (match_operand 5 "const_int_operand" " i, i, i, i")
7606 (match_operand 6 "const_int_operand" " i, i, i, i")
7607 (match_operand 7 "const_int_operand" " i, i, i, i")
7608 (match_operand 8 "const_int_operand" " i, i, i, i")
7609 (reg:SI VL_REGNUM)
7610 (reg:SI VTYPE_REGNUM)
7611 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7612 (any_float:V_VLSF
7613 (match_operand:<VCONVERT> 3 "register_operand" " vr, vr, vr, vr"))
7614 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
7615 "TARGET_VECTOR"
7616 "vfcvt.f.x<u>.v\t%0,%3%p1"
7617 [(set_attr "type" "vfcvtitof")
7618 (set_attr "mode" "<MODE>")
7619 (set (attr "frm_mode")
7620 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7622 ;; -------------------------------------------------------------------------------
7623 ;; ---- Predicated floating-point widen conversions
7624 ;; -------------------------------------------------------------------------------
7625 ;; Includes:
7626 ;; - 13.18 Widening Floating-Point/Integer Type-Convert Instructions
7627 ;; -------------------------------------------------------------------------------
7629 (define_insn "@pred_widen_fcvt_x<v_su>_f<mode>"
7630 [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
7631 (if_then_else:VWCONVERTI
7632 (unspec:<VM>
7633 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7634 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
7635 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
7636 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
7637 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
7638 (match_operand 8 "const_int_operand" " i, i, i, i, i, i, i, i")
7639 (reg:SI VL_REGNUM)
7640 (reg:SI VTYPE_REGNUM)
7641 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7642 (unspec:VWCONVERTI
7643 [(match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr")] VFCVTS)
7644 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
7645 "TARGET_VECTOR"
7646 "vfwcvt.x<v_su>.f.v\t%0,%3%p1"
7647 [(set_attr "type" "vfwcvtftoi")
7648 (set_attr "mode" "<VNCONVERT>")
7649 (set (attr "frm_mode")
7650 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))
7651 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
7653 (define_insn "@pred_widen_<fix_cvt><mode>"
7654 [(set (match_operand:VWCONVERTI 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
7655 (if_then_else:VWCONVERTI
7656 (unspec:<VM>
7657 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7658 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
7659 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
7660 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
7661 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
7662 (reg:SI VL_REGNUM)
7663 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7664 (any_fix:VWCONVERTI
7665 (match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
7666 (match_operand:VWCONVERTI 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
7667 "TARGET_VECTOR"
7668 "vfwcvt.rtz.x<u>.f.v\t%0,%3%p1"
7669 [(set_attr "type" "vfwcvtftoi")
7670 (set_attr "mode" "<VNCONVERT>")
7671 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
7673 (define_insn "@pred_widen_<float_cvt><mode>"
7674 [(set (match_operand:V_VLSF 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
7675 (if_then_else:V_VLSF
7676 (unspec:<VM>
7677 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7678 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
7679 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
7680 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
7681 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
7682 (reg:SI VL_REGNUM)
7683 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7684 (any_float:V_VLSF
7685 (match_operand:<VNCONVERT> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
7686 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
7687 "TARGET_VECTOR"
7688 "vfwcvt.f.x<u>.v\t%0,%3%p1"
7689 [(set_attr "type" "vfwcvtitof")
7690 (set_attr "mode" "<VNCONVERT>")
7691 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
7693 (define_insn "@pred_extend<mode>"
7694 [(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand" "=vr, vr, vr, vr, vr, vr, ?&vr, ?&vr")
7695 (if_then_else:VWEXTF_ZVFHMIN
7696 (unspec:<VM>
7697 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1,vmWc1")
7698 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK, rK, rK")
7699 (match_operand 5 "const_int_operand" " i, i, i, i, i, i, i, i")
7700 (match_operand 6 "const_int_operand" " i, i, i, i, i, i, i, i")
7701 (match_operand 7 "const_int_operand" " i, i, i, i, i, i, i, i")
7702 (reg:SI VL_REGNUM)
7703 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7704 (float_extend:VWEXTF_ZVFHMIN
7705 (match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " W21, W21, W42, W42, W84, W84, vr, vr"))
7706 (match_operand:VWEXTF_ZVFHMIN 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0, vu, 0")))]
7707 "TARGET_VECTOR"
7708 "vfwcvt.f.f.v\t%0,%3%p1"
7709 [(set_attr "type" "vfwcvtftof")
7710 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7711 (set_attr "group_overlap" "W21,W21,W42,W42,W84,W84,none,none")])
7713 ;; -------------------------------------------------------------------------------
7714 ;; ---- Predicated floating-point narrow conversions
7715 ;; -------------------------------------------------------------------------------
7716 ;; Includes:
7717 ;; - 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
7718 ;; -------------------------------------------------------------------------------
7720 (define_insn "@pred_narrow_fcvt_x<v_su>_f<mode>"
7721 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7722 (if_then_else:<VNCONVERT>
7723 (unspec:<VM>
7724 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7725 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7726 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7727 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7728 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7729 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7730 (reg:SI VL_REGNUM)
7731 (reg:SI VTYPE_REGNUM)
7732 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7733 (unspec:<VNCONVERT>
7734 [(match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr")] VFCVTS)
7735 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7736 "TARGET_VECTOR"
7737 "vfncvt.x<v_su>.f.w\t%0,%3%p1"
7738 [(set_attr "type" "vfncvtftoi")
7739 (set_attr "mode" "<VNCONVERT>")
7740 (set (attr "frm_mode")
7741 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7743 (define_insn "@pred_narrow_<fix_cvt><mode>"
7744 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7745 (if_then_else:<VNCONVERT>
7746 (unspec:<VM>
7747 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7748 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7749 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7750 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7751 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7752 (reg:SI VL_REGNUM)
7753 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7754 (any_fix:<VNCONVERT>
7755 (match_operand:V_VLSF 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7756 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7757 "TARGET_VECTOR"
7758 "vfncvt.rtz.x<u>.f.w\t%0,%3%p1"
7759 [(set_attr "type" "vfncvtftoi")
7760 (set_attr "mode" "<VNCONVERT>")])
7762 (define_insn "@pred_narrow_<float_cvt><mode>"
7763 [(set (match_operand:<VNCONVERT> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7764 (if_then_else:<VNCONVERT>
7765 (unspec:<VM>
7766 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7767 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7768 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7769 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7770 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7771 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7772 (reg:SI VL_REGNUM)
7773 (reg:SI VTYPE_REGNUM)
7774 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7775 (any_float:<VNCONVERT>
7776 (match_operand:VWCONVERTI 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7777 (match_operand:<VNCONVERT> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7778 "TARGET_VECTOR"
7779 "vfncvt.f.x<u>.w\t%0,%3%p1"
7780 [(set_attr "type" "vfncvtitof")
7781 (set_attr "mode" "<VNCONVERT>")
7782 (set (attr "frm_mode")
7783 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7785 (define_insn "@pred_trunc<mode>"
7786 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7787 (if_then_else:<V_DOUBLE_TRUNC>
7788 (unspec:<VM>
7789 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7790 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7791 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7792 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7793 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7794 (match_operand 8 "const_int_operand" " i, i, i, i, i, i")
7795 (reg:SI VL_REGNUM)
7796 (reg:SI VTYPE_REGNUM)
7797 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7798 (float_truncate:<V_DOUBLE_TRUNC>
7799 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))
7800 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7801 "TARGET_VECTOR"
7802 "vfncvt.f.f.w\t%0,%3%p1"
7803 [(set_attr "type" "vfncvtftof")
7804 (set_attr "mode" "<V_DOUBLE_TRUNC>")
7805 (set (attr "frm_mode")
7806 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7808 (define_insn "@pred_rod_trunc<mode>"
7809 [(set (match_operand:<V_DOUBLE_TRUNC> 0 "register_operand" "=vd, vd, vr, vr, &vr, &vr")
7810 (if_then_else:<V_DOUBLE_TRUNC>
7811 (unspec:<VM>
7812 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1,vmWc1,vmWc1")
7813 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK, rK")
7814 (match_operand 5 "const_int_operand" " i, i, i, i, i, i")
7815 (match_operand 6 "const_int_operand" " i, i, i, i, i, i")
7816 (match_operand 7 "const_int_operand" " i, i, i, i, i, i")
7817 (reg:SI VL_REGNUM)
7818 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7819 (unspec:<V_DOUBLE_TRUNC>
7820 [(float_truncate:<V_DOUBLE_TRUNC>
7821 (match_operand:VWEXTF_ZVFHMIN 3 "register_operand" " 0, 0, 0, 0, vr, vr"))] UNSPEC_ROD)
7822 (match_operand:<V_DOUBLE_TRUNC> 2 "vector_merge_operand" " vu, 0, vu, 0, vu, 0")))]
7823 "TARGET_VECTOR"
7824 "vfncvt.rod.f.f.w\t%0,%3%p1"
7825 [(set_attr "type" "vfncvtftof")
7826 (set_attr "mode" "<V_DOUBLE_TRUNC>")])
7828 ;; -------------------------------------------------------------------------------
7829 ;; ---- Predicated reduction operations
7830 ;; -------------------------------------------------------------------------------
7831 ;; Includes:
7832 ;; - 14.1 Vector Single-Width Integer Reduction Instructions
7833 ;; - 14.2 Vector Widening Integer Reduction Instructions
7834 ;; - 14.3 Vector Single-Width Floating-Point Reduction Instructions
7835 ;; - 14.4 Vector Widening Floating-Point Reduction Instructions
7836 ;; -------------------------------------------------------------------------------
7838 ;; Integer Reduction (vred(sum|maxu|max|minu|min|and|or|xor).vs)
7839 (define_insn "@pred_<reduc_op><mode>"
7840 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7841 (unspec:<V_LMUL1>
7842 [(unspec:<VM>
7843 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7844 (match_operand 5 "vector_length_operand" " rK, rK")
7845 (match_operand 6 "const_int_operand" " i, i")
7846 (match_operand 7 "const_int_operand" " i, i")
7847 (reg:SI VL_REGNUM)
7848 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7849 (unspec:<V_LMUL1> [
7850 (match_operand:V_VLSI 3 "register_operand" " vr, vr")
7851 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7852 ] ANY_REDUC)
7853 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7854 "TARGET_VECTOR"
7855 "v<reduc_op>.vs\t%0,%3,%4%p1"
7856 [(set_attr "type" "vired")
7857 (set_attr "mode" "<MODE>")])
7859 ;; Integer Widen Reduction Sum (vwredsum[u].vs)
7860 (define_insn "@pred_<reduc_op><mode>"
7861 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr,&vr")
7862 (unspec:<V_EXT_LMUL1>
7863 [(unspec:<VM>
7864 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7865 (match_operand 5 "vector_length_operand" " rK, rK")
7866 (match_operand 6 "const_int_operand" " i, i")
7867 (match_operand 7 "const_int_operand" " i, i")
7868 (reg:SI VL_REGNUM)
7869 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7870 (unspec:<V_EXT_LMUL1> [
7871 (match_operand:VI_QHS 3 "register_operand" " vr, vr")
7872 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr0, vr0")
7873 ] ANY_WREDUC)
7874 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7875 "TARGET_VECTOR"
7876 "v<reduc_op>.vs\t%0,%3,%4%p1"
7877 [(set_attr "type" "viwred")
7878 (set_attr "mode" "<MODE>")])
7880 ;; Float Reduction (vfred(max|min).vs)
7881 (define_insn "@pred_<reduc_op><mode>"
7882 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr, vr")
7883 (unspec:<V_LMUL1>
7884 [(unspec:<VM>
7885 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7886 (match_operand 5 "vector_length_operand" " rK, rK")
7887 (match_operand 6 "const_int_operand" " i, i")
7888 (match_operand 7 "const_int_operand" " i, i")
7889 (reg:SI VL_REGNUM)
7890 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
7891 (unspec:<V_LMUL1> [
7892 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7893 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7894 ] ANY_FREDUC)
7895 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7896 "TARGET_VECTOR"
7897 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7898 [(set_attr "type" "vfredu")
7899 (set_attr "mode" "<MODE>")])
7901 ;; Float Reduction Sum (vfred[ou]sum.vs)
7902 (define_insn "@pred_<reduc_op><mode>"
7903 [(set (match_operand:<V_LMUL1> 0 "register_operand" "=vr,vr")
7904 (unspec:<V_LMUL1>
7905 [(unspec:<VM>
7906 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7907 (match_operand 5 "vector_length_operand" " rK, rK")
7908 (match_operand 6 "const_int_operand" " i, i")
7909 (match_operand 7 "const_int_operand" " i, i")
7910 (match_operand 8 "const_int_operand" " i, i")
7911 (reg:SI VL_REGNUM)
7912 (reg:SI VTYPE_REGNUM)
7913 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7914 (unspec:<V_LMUL1> [
7915 (match_operand:V_VLSF 3 "register_operand" " vr, vr")
7916 (match_operand:<V_LMUL1> 4 "register_operand" " vr, vr")
7917 ] ANY_FREDUC_SUM)
7918 (match_operand:<V_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7919 "TARGET_VECTOR"
7920 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7921 [(set_attr "type" "vfred<order>")
7922 (set_attr "mode" "<MODE>")
7923 (set (attr "frm_mode")
7924 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7926 ;; Float Widen Reduction Sum (vfwred[ou]sum.vs)
7927 (define_insn "@pred_<reduc_op><mode>"
7928 [(set (match_operand:<V_EXT_LMUL1> 0 "register_operand" "=&vr, &vr")
7929 (unspec:<V_EXT_LMUL1>
7930 [(unspec:<VM>
7931 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
7932 (match_operand 5 "vector_length_operand" " rK, rK")
7933 (match_operand 6 "const_int_operand" " i, i")
7934 (match_operand 7 "const_int_operand" " i, i")
7935 (match_operand 8 "const_int_operand" " i, i")
7936 (reg:SI VL_REGNUM)
7937 (reg:SI VTYPE_REGNUM)
7938 (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
7939 (unspec:<V_EXT_LMUL1> [
7940 (match_operand:VF_HS 3 "register_operand" " vr, vr")
7941 (match_operand:<V_EXT_LMUL1> 4 "register_operand" " vr0, vr0")
7942 ] ANY_FWREDUC_SUM)
7943 (match_operand:<V_EXT_LMUL1> 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))]
7944 "TARGET_VECTOR"
7945 "vf<reduc_op>.vs\t%0,%3,%4%p1"
7946 [(set_attr "type" "vfwred<order>")
7947 (set_attr "mode" "<MODE>")
7948 (set (attr "frm_mode")
7949 (symbol_ref "riscv_vector::get_frm_mode (operands[8])"))])
7951 ;; -------------------------------------------------------------------------------
7952 ;; ---- Predicated permutation operations
7953 ;; -------------------------------------------------------------------------------
7954 ;; Includes:
7955 ;; - 16.1 Integer Scalar Move Instructions
7956 ;; - 16.2 Floating-Point Scalar Move Instructions
7957 ;; - 16.3 Vector Slide Instructions
7958 ;; - 16.4 Vector Register Gather Instructions
7959 ;; - 16.5 Vector Compress Instruction
7960 ;; -------------------------------------------------------------------------------
7962 (define_expand "@pred_extract_first<mode>"
7963 [(set (match_operand:<VEL> 0 "register_operand")
7964 (unspec:<VEL>
7965 [(vec_select:<VEL>
7966 (match_operand:V_VLSI 1 "reg_or_mem_operand")
7967 (parallel [(const_int 0)]))
7968 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7969 "TARGET_VECTOR"
7970 {
7971 if (MEM_P (operands[1]))
7972 {
7973 /* Combine vle.v + vmv.x.s ==> lw. */
7974 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
7975 DONE;
7976 }
7977 })
7979 (define_insn_and_split "*pred_extract_first<mode>"
7980 [(set (match_operand:<VEL> 0 "register_operand" "=r")
7981 (unspec:<VEL>
7982 [(vec_select:<VEL>
7983 (match_operand:V_VLSI 1 "register_operand" "vr")
7984 (parallel [(const_int 0)]))
7985 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
7986 "TARGET_VECTOR"
7987 "vmv.x.s\t%0,%1"
7988 "known_gt (GET_MODE_BITSIZE (<VEL>mode), GET_MODE_BITSIZE (Pmode))"
7989 [(const_int 0)]
7990 {
7991 /* In rv32 system, we can't use vmv.x.s directly.
7992 Instead, we should generate this following code sequence:
7993 vsrl.vx v16,v8,a0
7994 vmv.x.s a1,v16
7995 vmv.x.s a0,v8 */
7996 rtx nbits = force_reg (Pmode, gen_int_mode (GET_MODE_BITSIZE (Pmode), Pmode));
7997 rtx high_bits = gen_reg_rtx (<MODE>mode);
7998 emit_insn (gen_pred_scalar (LSHIFTRT, <MODE>mode, high_bits, CONSTM1_RTX (<VM>mode),
7999 RVV_VUNDEF (<MODE>mode), operands[1], nbits, /* vl */ const1_rtx,
8000 gen_int_mode (riscv_vector::TAIL_ANY, Pmode),
8001 gen_int_mode (riscv_vector::MASK_ANY, Pmode),
8002 gen_int_mode (riscv_vector::NONVLMAX, Pmode)));
8003 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8004 gen_highpart (SImode, operands[0]), high_bits));
8005 emit_insn (gen_pred_extract_first_trunc (<MODE>mode,
8006 gen_lowpart (SImode, operands[0]), operands[1]));
8007 DONE;
8008 }
8009 [(set_attr "type" "vimovvx")
8010 (set_attr "mode" "<MODE>")])
8012 (define_insn "@pred_extract_first_trunc<mode>"
8013 [(set (match_operand:SI 0 "register_operand" "=r")
8014 (truncate:SI
8015 (unspec:<VEL>
8016 [(vec_select:<VEL>
8017 (match_operand:V_VLSI_D 1 "register_operand" "vr")
8018 (parallel [(const_int 0)]))
8019 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)))]
8020 "TARGET_VECTOR"
8021 "vmv.x.s\t%0,%1"
8022 [(set_attr "type" "vimovvx")
8023 (set_attr "mode" "<MODE>")])
8025 (define_expand "@pred_extract_first<mode>"
8026 [(set (match_operand:<VEL> 0 "register_operand")
8027 (unspec:<VEL>
8028 [(vec_select:<VEL>
8029 (match_operand:V_VLSF 1 "reg_or_mem_operand")
8030 (parallel [(const_int 0)]))
8031 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8032 "TARGET_VECTOR"
8033 {
8034 if (MEM_P (operands[1]))
8035 {
8036 /* Combine vle.v + vmv.f.s ==> flw. */
8037 emit_move_insn (operands[0], gen_rtx_MEM (<VEL>mode, XEXP (operands[1], 0)));
8038 DONE;
8039 }
8040 })
8042 (define_insn "*pred_extract_first<mode>"
8043 [(set (match_operand:<VEL> 0 "register_operand" "=f")
8044 (unspec:<VEL>
8045 [(vec_select:<VEL>
8046 (match_operand:V_VLSF 1 "register_operand" "vr")
8047 (parallel [(const_int 0)]))
8048 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE))]
8049 "TARGET_VECTOR"
8050 "vfmv.f.s\t%0,%1"
8051 [(set_attr "type" "vfmovvf")
8052 (set_attr "mode" "<MODE>")])
8054 ;; vslide instructions
8055 (define_insn "@pred_slide<ud><mode>"
8056 [(set (match_operand:V_VLS 0 "register_operand" "<ud_constraint>")
8057 (unspec:V_VLS
8058 [(unspec:<VM>
8059 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8060 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8061 (match_operand 6 "const_int_operand" " i, i, i, i")
8062 (match_operand 7 "const_int_operand" " i, i, i, i")
8063 (match_operand 8 "const_int_operand" " i, i, i, i")
8064 (reg:SI VL_REGNUM)
8065 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8066 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0, vu, 0")
8067 (match_operand:V_VLS 3 "register_operand" " vr, vr, vr, vr")
8068 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK, rK, rK")] VSLIDES))]
8069 "TARGET_VECTOR"
8070 "vslide<ud>.v%o4\t%0,%3,%4%p1"
8071 [(set_attr "type" "vslide<ud>")
8072 (set_attr "mode" "<MODE>")])
8074 ;; vslide1 instructions
8075 (define_insn "@pred_slide<ud><mode>"
8076 [(set (match_operand:V_VLSI_QHS 0 "register_operand" "<ud_constraint>")
8077 (unspec:V_VLSI_QHS
8078 [(unspec:<VM>
8079 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8080 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8081 (match_operand 6 "const_int_operand" " i, i, i, i")
8082 (match_operand 7 "const_int_operand" " i, i, i, i")
8083 (match_operand 8 "const_int_operand" " i, i, i, i")
8084 (reg:SI VL_REGNUM)
8085 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8086 (match_operand:V_VLSI_QHS 2 "vector_merge_operand" " vu, 0, vu, 0")
8087 (match_operand:V_VLSI_QHS 3 "register_operand" " vr, vr, vr, vr")
8088 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8089 "TARGET_VECTOR"
8090 "vslide<ud>.vx\t%0,%3,%z4%p1"
8091 [(set_attr "type" "vislide<ud>")
8092 (set_attr "mode" "<MODE>")])
8094 (define_expand "@pred_slide<ud><mode>"
8095 [(set (match_operand:V_VLSI_D 0 "register_operand")
8096 (unspec:V_VLSI_D
8097 [(unspec:<VM>
8098 [(match_operand:<VM> 1 "vector_mask_operand")
8099 (match_operand 5 "reg_or_int_operand")
8100 (match_operand 6 "const_int_operand")
8101 (match_operand 7 "const_int_operand")
8102 (match_operand 8 "const_int_operand")
8103 (reg:SI VL_REGNUM)
8104 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8105 (match_operand:V_VLSI_D 2 "vector_merge_operand")
8106 (match_operand:V_VLSI_D 3 "register_operand")
8107 (match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
8108 "TARGET_VECTOR"
8109 {
8110 poly_uint64 nunits = GET_MODE_NUNITS (<MODE>mode) * 2;
8111 machine_mode vsimode = riscv_vector::get_vector_mode (SImode, nunits).require ();
8112 machine_mode vbimode = riscv_vector::get_vector_mode (BImode, nunits).require ();
8113 if (riscv_vector::slide1_sew64_helper (<UNSPEC>, <MODE>mode,
8114 vsimode, vbimode,
8115 operands))
8116 DONE;
8117 })
8119 (define_insn "*pred_slide<ud><mode>"
8120 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8121 (unspec:V_VLSI_D
8122 [(unspec:<VM>
8123 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8124 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8125 (match_operand 6 "const_int_operand" " i, i, i, i")
8126 (match_operand 7 "const_int_operand" " i, i, i, i")
8127 (match_operand 8 "const_int_operand" " i, i, i, i")
8128 (reg:SI VL_REGNUM)
8129 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8130 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8131 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8132 (match_operand:<VEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ")] VSLIDES1))]
8133 "TARGET_VECTOR"
8134 "vslide<ud>.vx\t%0,%3,%z4%p1"
8135 [(set_attr "type" "vislide<ud>")
8136 (set_attr "mode" "<MODE>")])
8138 (define_insn "*pred_slide<ud><mode>_extended"
8139 [(set (match_operand:V_VLSI_D 0 "register_operand" "<ud_constraint>")
8140 (unspec:V_VLSI_D
8141 [(unspec:<VM>
8142 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8143 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8144 (match_operand 6 "const_int_operand" " i, i, i, i")
8145 (match_operand 7 "const_int_operand" " i, i, i, i")
8146 (match_operand 8 "const_int_operand" " i, i, i, i")
8147 (reg:SI VL_REGNUM)
8148 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8149 (match_operand:V_VLSI_D 2 "vector_merge_operand" " vu, 0, vu, 0")
8150 (match_operand:V_VLSI_D 3 "register_operand" " vr, vr, vr, vr")
8151 (sign_extend:<VEL>
8152 (match_operand:<VSUBEL> 4 "reg_or_0_operand" " rJ, rJ, rJ, rJ"))] VSLIDES1))]
8153 "TARGET_VECTOR"
8154 "vslide<ud>.vx\t%0,%3,%z4%p1"
8155 [(set_attr "type" "vislide<ud>")
8156 (set_attr "mode" "<MODE>")])
8158 ;; vfslide1 instructions
8159 (define_insn "@pred_slide<ud><mode>"
8160 [(set (match_operand:V_VLSF 0 "register_operand" "<ud_constraint>")
8161 (unspec:V_VLSF
8162 [(unspec:<VM>
8163 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
8164 (match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
8165 (match_operand 6 "const_int_operand" " i, i, i, i")
8166 (match_operand 7 "const_int_operand" " i, i, i, i")
8167 (match_operand 8 "const_int_operand" " i, i, i, i")
8168 (reg:SI VL_REGNUM)
8169 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8170 (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")
8171 (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr")
8172 (match_operand:<VEL> 4 "register_operand" " f, f, f, f")] VFSLIDES1))]
8173 "TARGET_VECTOR"
8174 "vfslide<ud>.vf\t%0,%3,%4%p1"
8175 [(set_attr "type" "vfslide<ud>")
8176 (set_attr "mode" "<MODE>")])
8178 ;; vrgather
8179 (define_insn "@pred_gather<mode>"
8180 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8181 (if_then_else:V_VLS
8182 (unspec:<VM>
8183 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8184 (match_operand 5 "vector_length_operand" " rK, rK")
8185 (match_operand 6 "const_int_operand" " i, i")
8186 (match_operand 7 "const_int_operand" " i, i")
8187 (match_operand 8 "const_int_operand" " i, i")
8188 (reg:SI VL_REGNUM)
8189 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8190 (unspec:V_VLS
8191 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8192 (match_operand:<VINDEX> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHER)
8193 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8194 "TARGET_VECTOR"
8195 "vrgather.vv\t%0,%3,%4%p1"
8196 [(set_attr "type" "vgather")
8197 (set_attr "mode" "<MODE>")])
8199 (define_insn "@pred_gather<mode>_scalar"
8200 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8201 (if_then_else:V_VLS
8202 (unspec:<VM>
8203 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8204 (match_operand 5 "vector_length_operand" " rK, rK")
8205 (match_operand 6 "const_int_operand" " i, i")
8206 (match_operand 7 "const_int_operand" " i, i")
8207 (match_operand 8 "const_int_operand" " i, i")
8208 (reg:SI VL_REGNUM)
8209 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8210 (unspec:V_VLS
8211 [(match_operand:V_VLS 3 "register_operand" " vr, vr")
8212 (match_operand 4 "pmode_reg_or_uimm5_operand" " rK, rK")] UNSPEC_VRGATHER)
8213 (match_operand:V_VLS 2 "vector_merge_operand" " vu, 0")))]
8214 "TARGET_VECTOR"
8215 "vrgather.v%o4\t%0,%3,%4%p1"
8216 [(set_attr "type" "vgather")
8217 (set_attr "mode" "<MODE>")])
8219 ;; vrgatherei16
8220 (define_insn "@pred_gatherei16<mode>"
8221 [(set (match_operand:VEI16 0 "register_operand" "=&vr, &vr")
8222 (if_then_else:VEI16
8223 (unspec:<VM>
8224 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8225 (match_operand 5 "vector_length_operand" " rK, rK")
8226 (match_operand 6 "const_int_operand" " i, i")
8227 (match_operand 7 "const_int_operand" " i, i")
8228 (match_operand 8 "const_int_operand" " i, i")
8229 (reg:SI VL_REGNUM)
8230 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8231 (unspec:VEI16
8232 [(match_operand:VEI16 3 "register_operand" " vr, vr")
8233 (match_operand:<VINDEXEI16> 4 "register_operand" " vr, vr")] UNSPEC_VRGATHEREI16)
8234 (match_operand:VEI16 2 "vector_merge_operand" " vu, 0")))]
8235 "TARGET_VECTOR"
8236 "vrgatherei16.vv\t%0,%3,%4%p1"
8237 [(set_attr "type" "vgather")
8238 (set_attr "mode" "<MODE>")])
8240 ;; vcompress
8241 (define_insn "@pred_compress<mode>"
8242 [(set (match_operand:V_VLS 0 "register_operand" "=&vr, &vr")
8243 (unspec:V_VLS
8244 [(unspec:<VM>
8245 [(match_operand:<VM> 3 "register_operand" " vm, vm")
8246 (match_operand 4 "vector_length_operand" " rK, rK")
8247 (match_operand 5 "const_int_operand" " i, i")
8248 (match_operand 6 "const_int_operand" " i, i")
8249 (reg:SI VL_REGNUM)
8250 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8251 (match_operand:V_VLS 2 "register_operand" " vr, vr")
8252 (match_operand:V_VLS 1 "vector_merge_operand" " vu, 0")] UNSPEC_VCOMPRESS))]
8253 "TARGET_VECTOR"
8254 "vcompress.vm\t%0,%2,%3"
8255 [(set_attr "type" "vcompress")
8256 (set_attr "mode" "<MODE>")])
8258 ;; -------------------------------------------------------------------------------
8259 ;; ---- Predicated Fault-Only-First loads
8260 ;; -------------------------------------------------------------------------------
8261 ;; Includes:
8262 ;; - 7.7. Unit-stride Fault-Only-First Loads
8263 ;; -------------------------------------------------------------------------------
8265 (define_insn "read_vlsi"
8266 [(set (match_operand:SI 0 "register_operand" "=r")
8267 (reg:SI VL_REGNUM))]
8268 "TARGET_VECTOR"
8269 "csrr\t%0,vl"
8270 [(set_attr "type" "rdvl")
8271 (set_attr "mode" "SI")])
8273 (define_insn "read_vldi_zero_extend"
8274 [(set (match_operand:DI 0 "register_operand" "=r")
8275 (zero_extend:DI (reg:SI VL_REGNUM)))]
8276 "TARGET_VECTOR && TARGET_64BIT"
8277 "csrr\t%0,vl"
8278 [(set_attr "type" "rdvl")
8279 (set_attr "mode" "DI")])
8281 (define_insn "@pred_fault_load<mode>"
8282 [(set (match_operand:V 0 "register_operand" "=vd, vd, vr, vr")
8283 (if_then_else:V
8284 (unspec:<VM>
8285 [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm, Wc1, Wc1")
8286 (match_operand 4 "vector_length_operand" " rK, rK, rK, rK")
8287 (match_operand 5 "const_int_operand" " i, i, i, i")
8288 (match_operand 6 "const_int_operand" " i, i, i, i")
8289 (match_operand 7 "const_int_operand" " i, i, i, i")
8290 (reg:SI VL_REGNUM)
8291 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8292 (unspec:V
8293 [(match_operand:V 3 "memory_operand" " m, m, m, m")] UNSPEC_VLEFF)
8294 (match_operand:V 2 "vector_merge_operand" " vu, 0, vu, 0")))
8295 (set (reg:SI VL_REGNUM)
8296 (unspec:SI
8297 [(if_then_else:V
8298 (unspec:<VM>
8299 [(match_dup 1) (match_dup 4) (match_dup 5)
8300 (match_dup 6) (match_dup 7)
8301 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8302 (unspec:V [(match_dup 3)] UNSPEC_VLEFF)
8303 (match_dup 2))] UNSPEC_MODIFY_VL))]
8304 "TARGET_VECTOR"
8305 "vle<sew>ff.v\t%0,%3%p1"
8306 [(set_attr "type" "vldff")
8307 (set_attr "mode" "<MODE>")])
8310 ;; -------------------------------------------------------------------------------
8311 ;; ---- Predicated Segment loads/stores
8312 ;; -------------------------------------------------------------------------------
8313 ;; Includes:
8314 ;; - 7.8.1. Vector Unit-Stride Segment Loads and Stores
8315 ;; - 7.8.2. Vector Strided Segment Loads and Stores
8316 ;; - 7.8.3. Vector Indexed Segment Loads and Stores
8317 ;; -------------------------------------------------------------------------------
8319 (define_insn "@pred_unit_strided_load<mode>"
8320 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8321 (if_then_else:VT
8322 (unspec:<VM>
8323 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8324 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8325 (match_operand 5 "const_int_operand" " i, i, i")
8326 (match_operand 6 "const_int_operand" " i, i, i")
8327 (match_operand 7 "const_int_operand" " i, i, i")
8328 (reg:SI VL_REGNUM)
8329 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8330 (unspec:VT
8331 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8332 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED)
8333 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8334 "TARGET_VECTOR"
8335 "vlseg<nf>e<sew>.v\t%0,(%z3)%p1"
8336 [(set_attr "type" "vlsegde")
8337 (set_attr "mode" "<MODE>")])
8339 (define_insn "@pred_unit_strided_store<mode>"
8340 [(set (mem:BLK (scratch))
8341 (unspec:BLK
8342 [(unspec:<VM>
8343 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8344 (match_operand 3 "vector_length_operand" " rK")
8345 (match_operand 4 "const_int_operand" " i")
8346 (reg:SI VL_REGNUM)
8347 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8348 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8349 (match_operand:VT 2 "register_operand" " vr")
8350 (mem:BLK (scratch))] UNSPEC_UNIT_STRIDED))]
8351 "TARGET_VECTOR"
8352 "vsseg<nf>e<sew>.v\t%2,(%z1)%p0"
8353 [(set_attr "type" "vssegte")
8354 (set_attr "mode" "<MODE>")])
8356 (define_insn "@pred_strided_load<mode>"
8357 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8358 (if_then_else:VT
8359 (unspec:<VM>
8360 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8361 (match_operand 5 "vector_length_operand" " rK, rK, rK")
8362 (match_operand 6 "const_int_operand" " i, i, i")
8363 (match_operand 7 "const_int_operand" " i, i, i")
8364 (match_operand 8 "const_int_operand" " i, i, i")
8365 (reg:SI VL_REGNUM)
8366 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8367 (unspec:VT
8368 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8369 (match_operand 4 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8370 (mem:BLK (scratch))] UNSPEC_STRIDED)
8371 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))]
8372 "TARGET_VECTOR"
8373 "vlsseg<nf>e<sew>.v\t%0,(%z3),%z4%p1"
8374 [(set_attr "type" "vlsegds")
8375 (set_attr "mode" "<MODE>")])
8377 (define_insn "@pred_strided_store<mode>"
8378 [(set (mem:BLK (scratch))
8379 (unspec:BLK
8380 [(unspec:<VM>
8381 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8382 (match_operand 4 "vector_length_operand" " rK")
8383 (match_operand 5 "const_int_operand" " i")
8384 (reg:SI VL_REGNUM)
8385 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8386 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8387 (match_operand 2 "pmode_reg_or_0_operand" " rJ")
8388 (match_operand:VT 3 "register_operand" " vr")
8389 (mem:BLK (scratch))] UNSPEC_STRIDED))]
8390 "TARGET_VECTOR"
8391 "vssseg<nf>e<sew>.v\t%3,(%z1),%z2%p0"
8392 [(set_attr "type" "vssegts")
8393 (set_attr "mode" "<MODE>")])
8395 (define_insn "@pred_fault_load<mode>"
8396 [(set (match_operand:VT 0 "register_operand" "=vr, vr, vd")
8397 (if_then_else:VT
8398 (unspec:<VM>
8399 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1, Wc1, vm")
8400 (match_operand 4 "vector_length_operand" " rK, rK, rK")
8401 (match_operand 5 "const_int_operand" " i, i, i")
8402 (match_operand 6 "const_int_operand" " i, i, i")
8403 (match_operand 7 "const_int_operand" " i, i, i")
8404 (reg:SI VL_REGNUM)
8405 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8406 (unspec:VT
8407 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ, rJ")
8408 (mem:BLK (scratch))] UNSPEC_VLEFF)
8409 (match_operand:VT 2 "vector_merge_operand" " 0, vu, vu")))
8410 (set (reg:SI VL_REGNUM)
8411 (unspec:SI
8412 [(if_then_else:VT
8413 (unspec:<VM>
8414 [(match_dup 1) (match_dup 4) (match_dup 5)
8415 (match_dup 6) (match_dup 7)
8416 (reg:SI VL_REGNUM)
8417 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8418 (unspec:VT
8419 [(match_dup 3) (mem:BLK (scratch))] UNSPEC_VLEFF)
8420 (match_dup 2))] UNSPEC_MODIFY_VL))]
8421 "TARGET_VECTOR"
8422 "vlseg<nf>e<sew>ff.v\t%0,(%z3)%p1"
8423 [(set_attr "type" "vlsegdff")
8424 (set_attr "mode" "<MODE>")])
8426 (define_insn "@pred_indexed_<order>load<V1T:mode><RATIO64I:mode>"
8427 [(set (match_operand:V1T 0 "register_operand" "=&vr, &vr")
8428 (if_then_else:V1T
8429 (unspec:<VM>
8430 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8431 (match_operand 5 "vector_length_operand" " rK, rK")
8432 (match_operand 6 "const_int_operand" " i, i")
8433 (match_operand 7 "const_int_operand" " i, i")
8434 (match_operand 8 "const_int_operand" " i, i")
8435 (reg:SI VL_REGNUM)
8436 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8437 (unspec:V1T
8438 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8439 (mem:BLK (scratch))
8440 (match_operand:RATIO64I 4 "register_operand" " vr, vr")] ORDER)
8441 (match_operand:V1T 2 "vector_merge_operand" " vu, 0")))]
8442 "TARGET_VECTOR"
8443 "vl<order>xseg<nf>ei<RATIO64I:sew>.v\t%0,(%z3),%4%p1"
8444 [(set_attr "type" "vlsegd<order>x")
8445 (set_attr "mode" "<V1T:MODE>")])
8447 (define_insn "@pred_indexed_<order>load<V2T:mode><RATIO32I:mode>"
8448 [(set (match_operand:V2T 0 "register_operand" "=&vr, &vr")
8449 (if_then_else:V2T
8450 (unspec:<VM>
8451 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8452 (match_operand 5 "vector_length_operand" " rK, rK")
8453 (match_operand 6 "const_int_operand" " i, i")
8454 (match_operand 7 "const_int_operand" " i, i")
8455 (match_operand 8 "const_int_operand" " i, i")
8456 (reg:SI VL_REGNUM)
8457 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8458 (unspec:V2T
8459 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8460 (mem:BLK (scratch))
8461 (match_operand:RATIO32I 4 "register_operand" " vr, vr")] ORDER)
8462 (match_operand:V2T 2 "vector_merge_operand" " vu, 0")))]
8463 "TARGET_VECTOR"
8464 "vl<order>xseg<nf>ei<RATIO32I:sew>.v\t%0,(%z3),%4%p1"
8465 [(set_attr "type" "vlsegd<order>x")
8466 (set_attr "mode" "<V2T:MODE>")])
8468 (define_insn "@pred_indexed_<order>load<V4T:mode><RATIO16I:mode>"
8469 [(set (match_operand:V4T 0 "register_operand" "=&vr, &vr")
8470 (if_then_else:V4T
8471 (unspec:<VM>
8472 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8473 (match_operand 5 "vector_length_operand" " rK, rK")
8474 (match_operand 6 "const_int_operand" " i, i")
8475 (match_operand 7 "const_int_operand" " i, i")
8476 (match_operand 8 "const_int_operand" " i, i")
8477 (reg:SI VL_REGNUM)
8478 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8479 (unspec:V4T
8480 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8481 (mem:BLK (scratch))
8482 (match_operand:RATIO16I 4 "register_operand" " vr, vr")] ORDER)
8483 (match_operand:V4T 2 "vector_merge_operand" " vu, 0")))]
8484 "TARGET_VECTOR"
8485 "vl<order>xseg<nf>ei<RATIO16I:sew>.v\t%0,(%z3),%4%p1"
8486 [(set_attr "type" "vlsegd<order>x")
8487 (set_attr "mode" "<V4T:MODE>")])
8489 (define_insn "@pred_indexed_<order>load<V8T:mode><RATIO8I:mode>"
8490 [(set (match_operand:V8T 0 "register_operand" "=&vr, &vr")
8491 (if_then_else:V8T
8492 (unspec:<VM>
8493 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8494 (match_operand 5 "vector_length_operand" " rK, rK")
8495 (match_operand 6 "const_int_operand" " i, i")
8496 (match_operand 7 "const_int_operand" " i, i")
8497 (match_operand 8 "const_int_operand" " i, i")
8498 (reg:SI VL_REGNUM)
8499 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8500 (unspec:V8T
8501 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8502 (mem:BLK (scratch))
8503 (match_operand:RATIO8I 4 "register_operand" " vr, vr")] ORDER)
8504 (match_operand:V8T 2 "vector_merge_operand" " vu, 0")))]
8505 "TARGET_VECTOR"
8506 "vl<order>xseg<nf>ei<RATIO8I:sew>.v\t%0,(%z3),%4%p1"
8507 [(set_attr "type" "vlsegd<order>x")
8508 (set_attr "mode" "<V8T:MODE>")])
8510 (define_insn "@pred_indexed_<order>load<V16T:mode><RATIO4I:mode>"
8511 [(set (match_operand:V16T 0 "register_operand" "=&vr, &vr")
8512 (if_then_else:V16T
8513 (unspec:<VM>
8514 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8515 (match_operand 5 "vector_length_operand" " rK, rK")
8516 (match_operand 6 "const_int_operand" " i, i")
8517 (match_operand 7 "const_int_operand" " i, i")
8518 (match_operand 8 "const_int_operand" " i, i")
8519 (reg:SI VL_REGNUM)
8520 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8521 (unspec:V16T
8522 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8523 (mem:BLK (scratch))
8524 (match_operand:RATIO4I 4 "register_operand" " vr, vr")] ORDER)
8525 (match_operand:V16T 2 "vector_merge_operand" " vu, 0")))]
8526 "TARGET_VECTOR"
8527 "vl<order>xseg<nf>ei<RATIO4I:sew>.v\t%0,(%z3),%4%p1"
8528 [(set_attr "type" "vlsegd<order>x")
8529 (set_attr "mode" "<V16T:MODE>")])
8531 (define_insn "@pred_indexed_<order>load<V32T:mode><RATIO2I:mode>"
8532 [(set (match_operand:V32T 0 "register_operand" "=&vr, &vr")
8533 (if_then_else:V32T
8534 (unspec:<VM>
8535 [(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
8536 (match_operand 5 "vector_length_operand" " rK, rK")
8537 (match_operand 6 "const_int_operand" " i, i")
8538 (match_operand 7 "const_int_operand" " i, i")
8539 (match_operand 8 "const_int_operand" " i, i")
8540 (reg:SI VL_REGNUM)
8541 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8542 (unspec:V32T
8543 [(match_operand 3 "pmode_reg_or_0_operand" " rJ, rJ")
8544 (mem:BLK (scratch))
8545 (match_operand:RATIO2I 4 "register_operand" " vr, vr")] ORDER)
8546 (match_operand:V32T 2 "vector_merge_operand" " vu, 0")))]
8547 "TARGET_VECTOR"
8548 "vl<order>xseg<nf>ei<RATIO2I:sew>.v\t%0,(%z3),%4%p1"
8549 [(set_attr "type" "vlsegd<order>x")
8550 (set_attr "mode" "<V32T:MODE>")])
8552 (define_insn "@pred_indexed_<order>store<V1T:mode><RATIO64I:mode>"
8553 [(set (mem:BLK (scratch))
8554 (unspec:BLK
8555 [(unspec:<VM>
8556 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8557 (match_operand 4 "vector_length_operand" " rK")
8558 (match_operand 5 "const_int_operand" " i")
8559 (reg:SI VL_REGNUM)
8560 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8561 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8562 (match_operand:RATIO64I 2 "register_operand" " vr")
8563 (match_operand:V1T 3 "register_operand" " vr")] ORDER))]
8564 "TARGET_VECTOR"
8565 "vs<order>xseg<nf>ei<RATIO64I:sew>.v\t%3,(%z1),%2%p0"
8566 [(set_attr "type" "vssegt<order>x")
8567 (set_attr "mode" "<V1T:MODE>")])
8569 (define_insn "@pred_indexed_<order>store<V2T:mode><RATIO32I:mode>"
8570 [(set (mem:BLK (scratch))
8571 (unspec:BLK
8572 [(unspec:<VM>
8573 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8574 (match_operand 4 "vector_length_operand" " rK")
8575 (match_operand 5 "const_int_operand" " i")
8576 (reg:SI VL_REGNUM)
8577 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8578 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8579 (match_operand:RATIO32I 2 "register_operand" " vr")
8580 (match_operand:V2T 3 "register_operand" " vr")] ORDER))]
8581 "TARGET_VECTOR"
8582 "vs<order>xseg<nf>ei<RATIO32I:sew>.v\t%3,(%z1),%2%p0"
8583 [(set_attr "type" "vssegt<order>x")
8584 (set_attr "mode" "<V2T:MODE>")])
8586 (define_insn "@pred_indexed_<order>store<V4T:mode><RATIO16I:mode>"
8587 [(set (mem:BLK (scratch))
8588 (unspec:BLK
8589 [(unspec:<VM>
8590 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8591 (match_operand 4 "vector_length_operand" " rK")
8592 (match_operand 5 "const_int_operand" " i")
8593 (reg:SI VL_REGNUM)
8594 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8595 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8596 (match_operand:RATIO16I 2 "register_operand" " vr")
8597 (match_operand:V4T 3 "register_operand" " vr")] ORDER))]
8598 "TARGET_VECTOR"
8599 "vs<order>xseg<nf>ei<RATIO16I:sew>.v\t%3,(%z1),%2%p0"
8600 [(set_attr "type" "vssegt<order>x")
8601 (set_attr "mode" "<V4T:MODE>")])
8603 (define_insn "@pred_indexed_<order>store<V8T:mode><RATIO8I:mode>"
8604 [(set (mem:BLK (scratch))
8605 (unspec:BLK
8606 [(unspec:<VM>
8607 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8608 (match_operand 4 "vector_length_operand" " rK")
8609 (match_operand 5 "const_int_operand" " i")
8610 (reg:SI VL_REGNUM)
8611 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8612 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8613 (match_operand:RATIO8I 2 "register_operand" " vr")
8614 (match_operand:V8T 3 "register_operand" " vr")] ORDER))]
8615 "TARGET_VECTOR"
8616 "vs<order>xseg<nf>ei<RATIO8I:sew>.v\t%3,(%z1),%2%p0"
8617 [(set_attr "type" "vssegt<order>x")
8618 (set_attr "mode" "<V8T:MODE>")])
8620 (define_insn "@pred_indexed_<order>store<V16T:mode><RATIO4I:mode>"
8621 [(set (mem:BLK (scratch))
8622 (unspec:BLK
8623 [(unspec:<VM>
8624 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8625 (match_operand 4 "vector_length_operand" " rK")
8626 (match_operand 5 "const_int_operand" " i")
8627 (reg:SI VL_REGNUM)
8628 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8629 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8630 (match_operand:RATIO4I 2 "register_operand" " vr")
8631 (match_operand:V16T 3 "register_operand" " vr")] ORDER))]
8632 "TARGET_VECTOR"
8633 "vs<order>xseg<nf>ei<RATIO4I:sew>.v\t%3,(%z1),%2%p0"
8634 [(set_attr "type" "vssegt<order>x")
8635 (set_attr "mode" "<V16T:MODE>")])
8637 (define_insn "@pred_indexed_<order>store<V32T:mode><RATIO2I:mode>"
8638 [(set (mem:BLK (scratch))
8639 (unspec:BLK
8640 [(unspec:<VM>
8641 [(match_operand:<VM> 0 "vector_mask_operand" "vmWc1")
8642 (match_operand 4 "vector_length_operand" " rK")
8643 (match_operand 5 "const_int_operand" " i")
8644 (reg:SI VL_REGNUM)
8645 (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
8646 (match_operand 1 "pmode_reg_or_0_operand" " rJ")
8647 (match_operand:RATIO2I 2 "register_operand" " vr")
8648 (match_operand:V32T 3 "register_operand" " vr")] ORDER))]
8649 "TARGET_VECTOR"
8650 "vs<order>xseg<nf>ei<RATIO2I:sew>.v\t%3,(%z1),%2%p0"
8651 [(set_attr "type" "vssegt<order>x")
8652 (set_attr "mode" "<V32T:MODE>")])
8654 (include "autovec.md")
8655 (include "autovec-opt.md")