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* configure.ac: Check for MIPS TLS.
[official-gcc.git] / gcc / config / mips / mips.h
blob2d8695e2e5783fc1714f02ebe271333f799de604
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* Which processor to schedule for. Since there is no difference between
34 a R2000 and R3000 in terms of the scheduler, we collapse them into
35 just an R3000. The elements of the enumeration must match exactly
36 the cpu attribute in the mips.md machine description. */
37
38 enum processor_type {
39 PROCESSOR_DEFAULT,
40 PROCESSOR_4KC,
41 PROCESSOR_5KC,
42 PROCESSOR_20KC,
43 PROCESSOR_M4K,
44 PROCESSOR_R3000,
45 PROCESSOR_R3900,
46 PROCESSOR_R6000,
47 PROCESSOR_R4000,
48 PROCESSOR_R4100,
49 PROCESSOR_R4111,
50 PROCESSOR_R4120,
51 PROCESSOR_R4130,
52 PROCESSOR_R4300,
53 PROCESSOR_R4600,
54 PROCESSOR_R4650,
55 PROCESSOR_R5000,
56 PROCESSOR_R5400,
57 PROCESSOR_R5500,
58 PROCESSOR_R7000,
59 PROCESSOR_R8000,
60 PROCESSOR_R9000,
61 PROCESSOR_SB1,
62 PROCESSOR_SR71000
63 };
64
65 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
66 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
67 to work on a 64 bit machine. */
68
69 #define ABI_32 0
70 #define ABI_N32 1
71 #define ABI_64 2
72 #define ABI_EABI 3
73 #define ABI_O64 4
74
75 /* Information about one recognized processor. Defined here for the
76 benefit of TARGET_CPU_CPP_BUILTINS. */
77 struct mips_cpu_info {
78 /* The 'canonical' name of the processor as far as GCC is concerned.
79 It's typically a manufacturer's prefix followed by a numerical
80 designation. It should be lower case. */
81 const char *name;
82
83 /* The internal processor number that most closely matches this
84 entry. Several processors can have the same value, if there's no
85 difference between them from GCC's point of view. */
86 enum processor_type cpu;
87
88 /* The ISA level that the processor implements. */
89 int isa;
90 };
91
92 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
93 extern const char *current_function_file; /* filename current function is in */
94 extern int num_source_filenames; /* current .file # */
95 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
96 extern int sym_lineno; /* sgi next label # for each stmt */
97 extern int set_noreorder; /* # of nested .set noreorder's */
98 extern int set_nomacro; /* # of nested .set nomacro's */
99 extern int set_noat; /* # of nested .set noat's */
100 extern int set_volatile; /* # of nested .set volatile's */
101 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
102 extern int mips_dbx_regno[]; /* Map register # to debug register # */
103 extern GTY(()) rtx cmp_operands[2];
104 extern enum processor_type mips_arch; /* which cpu to codegen for */
105 extern enum processor_type mips_tune; /* which cpu to schedule for */
106 extern int mips_isa; /* architectural level */
107 extern int mips_abi; /* which ABI to use */
108 extern int mips16_hard_float; /* mips16 without -msoft-float */
109 extern const char *mips_arch_string; /* for -march=<xxx> */
110 extern const char *mips_tune_string; /* for -mtune=<xxx> */
111 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
112 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
113 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
114 extern const char *mips_fix_vr4130_string;
115 extern const struct mips_cpu_info mips_cpu_info_table[];
116 extern const struct mips_cpu_info *mips_arch_info;
117 extern const struct mips_cpu_info *mips_tune_info;
118
119 /* Macros to silence warnings about numbers being signed in traditional
120 C and unsigned in ISO C when compiled on 32-bit hosts. */
121
122 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
123 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
124 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
125
126 \f
127 /* Run-time compilation parameters selecting different hardware subsets. */
128
129 /* Macros used in the machine description to test the flags. */
130
131 /* Bits for real switches */
132 #define MASK_INT64 0x00000001 /* ints are 64 bits */
133 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
134 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
135 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
136 multiply-add operations. */
137 #define MASK_EXPLICIT_RELOCS 0x00000010 /* Use relocation operators. */
138 #define MASK_MEMCPY 0x00000020 /* call memcpy instead of inline code*/
139 #define MASK_SOFT_FLOAT 0x00000040 /* software floating point */
140 #define MASK_FLOAT64 0x00000080 /* fp registers are 64 bits */
141 #define MASK_ABICALLS 0x00000100 /* emit .abicalls/.cprestore/.cpload */
142 #define MASK_XGOT 0x00000200 /* emit big-got PIC */
143 #define MASK_LONG_CALLS 0x00000400 /* Always call through a register */
144 #define MASK_64BIT 0x00000800 /* Use 64 bit GP registers and insns */
145 #define MASK_EMBEDDED_DATA 0x00001000 /* Reduce RAM usage, not fast code */
146 #define MASK_BIG_ENDIAN 0x00002000 /* Generate big endian code */
147 #define MASK_SINGLE_FLOAT 0x00004000 /* Only single precision FPU. */
148 #define MASK_MAD 0x00008000 /* Generate mad/madu as on 4650. */
149 #define MASK_4300_MUL_FIX 0x00010000 /* Work-around early Vr4300 CPU bug */
150 #define MASK_MIPS16 0x00020000 /* Generate mips16 code */
151 #define MASK_NO_CHECK_ZERO_DIV \
152 0x00040000 /* divide by zero checking */
153 #define MASK_BRANCHLIKELY 0x00080000 /* Generate Branch Likely
154 instructions. */
155 #define MASK_UNINIT_CONST_IN_RODATA \
156 0x00100000 /* Store uninitialized
157 consts in rodata */
158 #define MASK_FIX_R4000 0x00200000 /* Work around R4000 errata. */
159 #define MASK_FIX_R4400 0x00400000 /* Work around R4400 errata. */
160 #define MASK_FIX_SB1 0x00800000 /* Work around SB-1 errata. */
161 #define MASK_FIX_VR4120 0x01000000 /* Work around VR4120 errata. */
162 #define MASK_VR4130_ALIGN 0x02000000 /* Perform VR4130 alignment opts. */
163 #define MASK_FP_EXCEPTIONS 0x04000000 /* FP exceptions are enabled. */
164 #define MASK_DIVIDE_BREAKS 0x08000000 /* Divide by zero check uses
165 break instead of trap. */
166 #define MASK_PAIRED_SINGLE 0x10000000 /* Support paired-single FPU. */
167 #define MASK_MIPS3D 0x20000000 /* Support MIPS-3D instructions. */
168 #define MASK_SYM32 0x40000000 /* Assume 32-bit symbol values. */
169
170 /* Debug switches, not documented */
171 #define MASK_DEBUG 0 /* unused */
172 #define MASK_DEBUG_D 0 /* don't do define_split's */
173
174 /* Dummy switches used only in specs */
175 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
176
177 /* r4000 64 bit sizes */
178 #define TARGET_INT64 ((target_flags & MASK_INT64) != 0)
179 #define TARGET_LONG64 ((target_flags & MASK_LONG64) != 0)
180 #define TARGET_FLOAT64 ((target_flags & MASK_FLOAT64) != 0)
181 #define TARGET_64BIT ((target_flags & MASK_64BIT) != 0)
182
183 /* Mips vs. GNU linker */
184 #define TARGET_SPLIT_ADDRESSES ((target_flags & MASK_SPLIT_ADDR) != 0)
185
186 /* Debug Modes */
187 #define TARGET_DEBUG_MODE ((target_flags & MASK_DEBUG) != 0)
188 #define TARGET_DEBUG_D_MODE ((target_flags & MASK_DEBUG_D) != 0)
189
190 /* call memcpy instead of inline code */
191 #define TARGET_MEMCPY ((target_flags & MASK_MEMCPY) != 0)
192
193 /* .abicalls, etc from Pyramid V.4 */
194 #define TARGET_ABICALLS ((target_flags & MASK_ABICALLS) != 0)
195 #define TARGET_XGOT ((target_flags & MASK_XGOT) != 0)
196
197 /* software floating point */
198 #define TARGET_SOFT_FLOAT ((target_flags & MASK_SOFT_FLOAT) != 0)
199 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
200
201 /* always call through a register */
202 #define TARGET_LONG_CALLS ((target_flags & MASK_LONG_CALLS) != 0)
203
204 /* for embedded systems, optimize for
205 reduced RAM space instead of for
206 fastest code. */
207 #define TARGET_EMBEDDED_DATA ((target_flags & MASK_EMBEDDED_DATA) != 0)
208
209 /* always store uninitialized const
210 variables in rodata, requires
211 TARGET_EMBEDDED_DATA. */
212 #define TARGET_UNINIT_CONST_IN_RODATA \
213 ((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)
214
215 /* generate big endian code. */
216 #define TARGET_BIG_ENDIAN ((target_flags & MASK_BIG_ENDIAN) != 0)
217
218 #define TARGET_SINGLE_FLOAT ((target_flags & MASK_SINGLE_FLOAT) != 0)
219 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
220
221 #define TARGET_MAD ((target_flags & MASK_MAD) != 0)
222
223 #define TARGET_FUSED_MADD ((target_flags & MASK_NO_FUSED_MADD) == 0)
224
225 #define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
226
227 #define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
228 #define TARGET_DIVIDE_TRAPS ((target_flags & MASK_DIVIDE_BREAKS) == 0)
229
230 #define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
231
232 #define TARGET_FIX_SB1 ((target_flags & MASK_FIX_SB1) != 0)
233
234 /* Work around R4000 errata. */
235 #define TARGET_FIX_R4000 ((target_flags & MASK_FIX_R4000) != 0)
236
237 /* Work around R4400 errata. */
238 #define TARGET_FIX_R4400 ((target_flags & MASK_FIX_R4400) != 0)
239 #define TARGET_FIX_VR4120 ((target_flags & MASK_FIX_VR4120) != 0)
240 #define TARGET_FIX_VR4130 (mips_fix_vr4130_string != 0)
241 #define TARGET_VR4130_ALIGN ((target_flags & MASK_VR4130_ALIGN) != 0)
242
243 #define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
244
245 #define TARGET_PAIRED_SINGLE_FLOAT \
246 ((target_flags & MASK_PAIRED_SINGLE) != 0)
247 #define TARGET_MIPS3D ((target_flags & MASK_MIPS3D) != 0)
248 #define TARGET_SYM32 ((target_flags & MASK_SYM32) != 0)
249
250 /* True if we should use NewABI-style relocation operators for
251 symbolic addresses. This is never true for mips16 code,
252 which has its own conventions. */
253
254 #define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
255
256
257 /* True if the call patterns should be split into a jalr followed by
258 an instruction to restore $gp. This is only ever true for SVR4 PIC,
259 in which $gp is call-clobbered. It is only safe to split the load
260 from the call when every use of $gp is explicit. */
261
262 #define TARGET_SPLIT_CALLS \
263 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
264
265 /* True if we can optimize sibling calls. For simplicity, we only
266 handle cases in which call_insn_operand will reject invalid
267 sibcall addresses. There are two cases in which this isn't true:
268
269 - TARGET_MIPS16. call_insn_operand accepts constant addresses
270 but there is no direct jump instruction. It isn't worth
271 using sibling calls in this case anyway; they would usually
272 be longer than normal calls.
273
274 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
275 accepts global constants, but "jr $25" is the only allowed
276 sibcall. */
277
278 #define TARGET_SIBCALLS \
279 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
280
281 /* True if .gpword or .gpdword should be used for switch tables.
282
283 Although GAS does understand .gpdword, the SGI linker mishandles
284 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
285 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
286 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
287
288 /* Generate mips16 code */
289 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
290
291 /* Generic ISA defines. */
292 #define ISA_MIPS1 (mips_isa == 1)
293 #define ISA_MIPS2 (mips_isa == 2)
294 #define ISA_MIPS3 (mips_isa == 3)
295 #define ISA_MIPS4 (mips_isa == 4)
296 #define ISA_MIPS32 (mips_isa == 32)
297 #define ISA_MIPS32R2 (mips_isa == 33)
298 #define ISA_MIPS64 (mips_isa == 64)
299
300 /* Architecture target defines. */
301 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
302 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
303 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
304 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
305 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
306 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
307 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
308 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
309 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
310 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
311
312 /* Scheduling target defines. */
313 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
314 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
315 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
316 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
317 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
318 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
319 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
320 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
321 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
322 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
323 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
324 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
325
326 /* True if the pre-reload scheduler should try to create chains of
327 multiply-add or multiply-subtract instructions. For example,
328 suppose we have:
329
330 t1 = a * b
331 t2 = t1 + c * d
332 t3 = e * f
333 t4 = t3 - g * h
334
335 t1 will have a higher priority than t2 and t3 will have a higher
336 priority than t4. However, before reload, there is no dependence
337 between t1 and t3, and they can often have similar priorities.
338 The scheduler will then tend to prefer:
339
340 t1 = a * b
341 t3 = e * f
342 t2 = t1 + c * d
343 t4 = t3 - g * h
344
345 which stops us from making full use of macc/madd-style instructions.
346 This sort of situation occurs frequently in Fourier transforms and
347 in unrolled loops.
348
349 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
350 queue so that chained multiply-add and multiply-subtract instructions
351 appear ahead of any other instruction that is likely to clobber lo.
352 In the example above, if t2 and t3 become ready at the same time,
353 the code ensures that t2 is scheduled first.
354
355 Multiply-accumulate instructions are a bigger win for some targets
356 than others, so this macro is defined on an opt-in basis. */
357 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
358 || TUNE_MIPS4120 \
359 || TUNE_MIPS4130)
360
361 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
362 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
363
364 /* IRIX specific stuff. */
365 #define TARGET_IRIX 0
366 #define TARGET_IRIX6 0
367
368 /* Define preprocessor macros for the -march and -mtune options.
369 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
370 processor. If INFO's canonical name is "foo", define PREFIX to
371 be "foo", and define an additional macro PREFIX_FOO. */
372 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
373 do \
374 { \
375 char *macro, *p; \
376 \
377 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
378 for (p = macro; *p != 0; p++) \
379 *p = TOUPPER (*p); \
380 \
381 builtin_define (macro); \
382 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
383 free (macro); \
384 } \
385 while (0)
386
387 /* Target CPU builtins. */
388 #define TARGET_CPU_CPP_BUILTINS() \
389 do \
390 { \
391 /* Everyone but IRIX defines this to mips. */ \
392 if (!TARGET_IRIX) \
393 builtin_assert ("machine=mips"); \
394 \
395 builtin_assert ("cpu=mips"); \
396 builtin_define ("__mips__"); \
397 builtin_define ("_mips"); \
398 \
399 /* We do this here because __mips is defined below \
400 and so we can't use builtin_define_std. */ \
401 if (!flag_iso) \
402 builtin_define ("mips"); \
403 \
404 if (TARGET_64BIT) \
405 builtin_define ("__mips64"); \
406 \
407 if (!TARGET_IRIX) \
408 { \
409 /* Treat _R3000 and _R4000 like register-size \
410 defines, which is how they've historically \
411 been used. */ \
412 if (TARGET_64BIT) \
413 { \
414 builtin_define_std ("R4000"); \
415 builtin_define ("_R4000"); \
416 } \
417 else \
418 { \
419 builtin_define_std ("R3000"); \
420 builtin_define ("_R3000"); \
421 } \
422 } \
423 if (TARGET_FLOAT64) \
424 builtin_define ("__mips_fpr=64"); \
425 else \
426 builtin_define ("__mips_fpr=32"); \
427 \
428 if (TARGET_MIPS16) \
429 builtin_define ("__mips16"); \
430 \
431 if (TARGET_MIPS3D) \
432 builtin_define ("__mips3d"); \
433 \
434 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
435 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
436 \
437 if (ISA_MIPS1) \
438 { \
439 builtin_define ("__mips=1"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
441 } \
442 else if (ISA_MIPS2) \
443 { \
444 builtin_define ("__mips=2"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
446 } \
447 else if (ISA_MIPS3) \
448 { \
449 builtin_define ("__mips=3"); \
450 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
451 } \
452 else if (ISA_MIPS4) \
453 { \
454 builtin_define ("__mips=4"); \
455 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
456 } \
457 else if (ISA_MIPS32) \
458 { \
459 builtin_define ("__mips=32"); \
460 builtin_define ("__mips_isa_rev=1"); \
461 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
462 } \
463 else if (ISA_MIPS32R2) \
464 { \
465 builtin_define ("__mips=32"); \
466 builtin_define ("__mips_isa_rev=2"); \
467 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
468 } \
469 else if (ISA_MIPS64) \
470 { \
471 builtin_define ("__mips=64"); \
472 builtin_define ("__mips_isa_rev=1"); \
473 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
474 } \
475 \
476 if (TARGET_HARD_FLOAT) \
477 builtin_define ("__mips_hard_float"); \
478 else if (TARGET_SOFT_FLOAT) \
479 builtin_define ("__mips_soft_float"); \
480 \
481 if (TARGET_SINGLE_FLOAT) \
482 builtin_define ("__mips_single_float"); \
483 \
484 if (TARGET_PAIRED_SINGLE_FLOAT) \
485 builtin_define ("__mips_paired_single_float"); \
486 \
487 if (TARGET_BIG_ENDIAN) \
488 { \
489 builtin_define_std ("MIPSEB"); \
490 builtin_define ("_MIPSEB"); \
491 } \
492 else \
493 { \
494 builtin_define_std ("MIPSEL"); \
495 builtin_define ("_MIPSEL"); \
496 } \
497 \
498 /* Macros dependent on the C dialect. */ \
499 if (preprocessing_asm_p ()) \
500 { \
501 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
502 builtin_define ("_LANGUAGE_ASSEMBLY"); \
503 } \
504 else if (c_dialect_cxx ()) \
505 { \
506 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
507 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
508 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
509 } \
510 else \
511 { \
512 builtin_define_std ("LANGUAGE_C"); \
513 builtin_define ("_LANGUAGE_C"); \
514 } \
515 if (c_dialect_objc ()) \
516 { \
517 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
518 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
519 /* Bizarre, but needed at least for Irix. */ \
520 builtin_define_std ("LANGUAGE_C"); \
521 builtin_define ("_LANGUAGE_C"); \
522 } \
523 \
524 if (mips_abi == ABI_EABI) \
525 builtin_define ("__mips_eabi"); \
526 \
527 } while (0)
528
529
530
531 /* Macro to define tables used to set the flags.
532 This is a list in braces of pairs in braces,
533 each pair being { "NAME", VALUE }
534 where VALUE is the bits to set or minus the bits to clear.
535 An empty string NAME is used to identify the default VALUE. */
536
537 #define TARGET_SWITCHES \
538 { \
539 SUBTARGET_TARGET_SWITCHES \
540 {"int64", MASK_INT64 | MASK_LONG64, \
541 N_("Use 64-bit int type")}, \
542 {"long64", MASK_LONG64, \
543 N_("Use 64-bit long type")}, \
544 {"long32", -(MASK_LONG64 | MASK_INT64), \
545 N_("Use 32-bit long type")}, \
546 {"split-addresses", MASK_SPLIT_ADDR, \
547 N_("Optimize lui/addiu address loads")}, \
548 {"no-split-addresses", -MASK_SPLIT_ADDR, \
549 N_("Don't optimize lui/addiu address loads")}, \
550 {"gas", 0, \
551 N_("Use GNU as (now ignored)")}, \
552 {"gpOPT", 0, \
553 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
554 {"gpopt", 0, \
555 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
556 {"no-gpOPT", 0, \
557 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
558 {"no-gpopt", 0, \
559 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
560 {"stats", 0, \
561 N_("Output compiler statistics (now ignored)")}, \
562 {"no-stats", 0, \
563 N_("Don't output compiler statistics")}, \
564 {"memcpy", MASK_MEMCPY, \
565 N_("Don't optimize block moves")}, \
566 {"no-memcpy", -MASK_MEMCPY, \
567 N_("Optimize block moves")}, \
568 {"mips-tfile", MASK_MIPS_TFILE, \
569 N_("Use mips-tfile asm postpass")}, \
570 {"no-mips-tfile", -MASK_MIPS_TFILE, \
571 N_("Don't use mips-tfile asm postpass")}, \
572 {"soft-float", MASK_SOFT_FLOAT, \
573 N_("Use software floating point")}, \
574 {"hard-float", -MASK_SOFT_FLOAT, \
575 N_("Use hardware floating point")}, \
576 {"fp64", MASK_FLOAT64, \
577 N_("Use 64-bit FP registers")}, \
578 {"fp32", -MASK_FLOAT64, \
579 N_("Use 32-bit FP registers")}, \
580 {"gp64", MASK_64BIT, \
581 N_("Use 64-bit general registers")}, \
582 {"gp32", -MASK_64BIT, \
583 N_("Use 32-bit general registers")}, \
584 {"abicalls", MASK_ABICALLS, \
585 N_("Use Irix PIC")}, \
586 {"no-abicalls", -MASK_ABICALLS, \
587 N_("Don't use Irix PIC")}, \
588 {"long-calls", MASK_LONG_CALLS, \
589 N_("Use indirect calls")}, \
590 {"no-long-calls", -MASK_LONG_CALLS, \
591 N_("Don't use indirect calls")}, \
592 {"embedded-data", MASK_EMBEDDED_DATA, \
593 N_("Use ROM instead of RAM")}, \
594 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
595 N_("Don't use ROM instead of RAM")}, \
596 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
597 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
598 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
599 N_("Don't put uninitialized constants in ROM")}, \
600 {"eb", MASK_BIG_ENDIAN, \
601 N_("Use big-endian byte order")}, \
602 {"el", -MASK_BIG_ENDIAN, \
603 N_("Use little-endian byte order")}, \
604 {"single-float", MASK_SINGLE_FLOAT, \
605 N_("Use single (32-bit) FP only")}, \
606 {"double-float", -MASK_SINGLE_FLOAT, \
607 N_("Don't use single (32-bit) FP only")}, \
608 {"paired-single", MASK_PAIRED_SINGLE, \
609 N_("Use paired-single floating point instructions")}, \
610 {"no-paired-single", -MASK_PAIRED_SINGLE, \
611 N_("Use paired-single floating point instructions")}, \
612 {"ips3d", MASK_MIPS3D, \
613 N_("Use MIPS-3D instructions")}, \
614 {"no-mips3d", -MASK_MIPS3D, \
615 N_("Use MIPS-3D instructions")}, \
616 {"mad", MASK_MAD, \
617 N_("Use multiply accumulate")}, \
618 {"no-mad", -MASK_MAD, \
619 N_("Don't use multiply accumulate")}, \
620 {"no-fused-madd", MASK_NO_FUSED_MADD, \
621 N_("Don't generate fused multiply/add instructions")}, \
622 {"fused-madd", -MASK_NO_FUSED_MADD, \
623 N_("Generate fused multiply/add instructions")}, \
624 {"vr4130-align", MASK_VR4130_ALIGN, \
625 N_("Perform VR4130-specific alignment optimizations")}, \
626 {"no-vr4130-align", -MASK_VR4130_ALIGN, \
627 N_("Don't perform VR4130-specific alignment optimizations")}, \
628 {"fix4300", MASK_4300_MUL_FIX, \
629 N_("Work around early 4300 hardware bug")}, \
630 {"no-fix4300", -MASK_4300_MUL_FIX, \
631 N_("Don't work around early 4300 hardware bug")}, \
632 {"fix-sb1", MASK_FIX_SB1, \
633 N_("Work around errata for early SB-1 revision 2 cores")}, \
634 {"no-fix-sb1", -MASK_FIX_SB1, \
635 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
636 {"fix-r4000", MASK_FIX_R4000, \
637 N_("Work around R4000 errata")}, \
638 {"no-fix-r4000", -MASK_FIX_R4000, \
639 N_("Don't work around R4000 errata")}, \
640 {"fix-r4400", MASK_FIX_R4400, \
641 N_("Work around R4400 errata")}, \
642 {"no-fix-r4400", -MASK_FIX_R4400, \
643 N_("Don't work around R4400 errata")}, \
644 {"fix-vr4120", MASK_FIX_VR4120, \
645 N_("Work around certain VR4120 errata")}, \
646 {"no-fix-vr4120", -MASK_FIX_VR4120, \
647 N_("Don't work around certain VR4120 errata")}, \
648 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
649 N_("Trap on integer divide by zero")}, \
650 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
651 N_("Don't trap on integer divide by zero")}, \
652 {"divide-traps", -MASK_DIVIDE_BREAKS, \
653 N_("Use trap to check for integer divide by zero")}, \
654 {"divide-breaks", MASK_DIVIDE_BREAKS, \
655 N_("Use break to check for integer divide by zero")}, \
656 { "branch-likely", MASK_BRANCHLIKELY, \
657 N_("Use Branch Likely instructions, overriding default for arch")}, \
658 { "no-branch-likely", -MASK_BRANCHLIKELY, \
659 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
660 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
661 N_("Use NewABI-style %reloc() assembly operators")}, \
662 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
663 N_("Use assembler macros instead of relocation operators")}, \
664 {"ips16", MASK_MIPS16, \
665 N_("Generate mips16 code") }, \
666 {"no-mips16", -MASK_MIPS16, \
667 N_("Generate normal-mode code") }, \
668 {"xgot", MASK_XGOT, \
669 N_("Lift restrictions on GOT size") }, \
670 {"no-xgot", -MASK_XGOT, \
671 N_("Do not lift restrictions on GOT size") }, \
672 {"fp-exceptions", MASK_FP_EXCEPTIONS, \
673 N_("FP exceptions are enabled") }, \
674 {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
675 N_("FP exceptions are not enabled") }, \
676 {"sym32", MASK_SYM32, \
677 N_("Assume all symbols have 32-bit values") }, \
678 {"no-sym32", -MASK_SYM32, \
679 N_("Don't assume all symbols have 32-bit values") }, \
680 {"debug", MASK_DEBUG, \
681 NULL}, \
682 {"debugd", MASK_DEBUG_D, \
683 NULL}, \
684 {"", (TARGET_DEFAULT \
685 | TARGET_CPU_DEFAULT \
686 | TARGET_ENDIAN_DEFAULT \
687 | TARGET_FP_EXCEPTIONS_DEFAULT), \
688 NULL}, \
689 }
690
691 /* Default target_flags if no switches are specified */
692
693 #ifndef TARGET_DEFAULT
694 #define TARGET_DEFAULT 0
695 #endif
696
697 #ifndef TARGET_CPU_DEFAULT
698 #define TARGET_CPU_DEFAULT 0
699 #endif
700
701 #ifndef TARGET_ENDIAN_DEFAULT
702 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
703 #endif
704
705 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
706 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
707 #endif
708
709 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
710 #ifndef MIPS_ISA_DEFAULT
711 #ifndef MIPS_CPU_STRING_DEFAULT
712 #define MIPS_CPU_STRING_DEFAULT "from-abi"
713 #endif
714 #endif
715
716 #ifdef IN_LIBGCC2
717 #undef TARGET_64BIT
718 /* Make this compile time constant for libgcc2 */
719 #ifdef __mips64
720 #define TARGET_64BIT 1
721 #else
722 #define TARGET_64BIT 0
723 #endif
724 #endif /* IN_LIBGCC2 */
725
726 #ifndef MULTILIB_ENDIAN_DEFAULT
727 #if TARGET_ENDIAN_DEFAULT == 0
728 #define MULTILIB_ENDIAN_DEFAULT "EL"
729 #else
730 #define MULTILIB_ENDIAN_DEFAULT "EB"
731 #endif
732 #endif
733
734 #ifndef MULTILIB_ISA_DEFAULT
735 # if MIPS_ISA_DEFAULT == 1
736 # define MULTILIB_ISA_DEFAULT "mips1"
737 # else
738 # if MIPS_ISA_DEFAULT == 2
739 # define MULTILIB_ISA_DEFAULT "mips2"
740 # else
741 # if MIPS_ISA_DEFAULT == 3
742 # define MULTILIB_ISA_DEFAULT "mips3"
743 # else
744 # if MIPS_ISA_DEFAULT == 4
745 # define MULTILIB_ISA_DEFAULT "mips4"
746 # else
747 # if MIPS_ISA_DEFAULT == 32
748 # define MULTILIB_ISA_DEFAULT "mips32"
749 # else
750 # if MIPS_ISA_DEFAULT == 33
751 # define MULTILIB_ISA_DEFAULT "mips32r2"
752 # else
753 # if MIPS_ISA_DEFAULT == 64
754 # define MULTILIB_ISA_DEFAULT "mips64"
755 # else
756 # define MULTILIB_ISA_DEFAULT "mips1"
757 # endif
758 # endif
759 # endif
760 # endif
761 # endif
762 # endif
763 # endif
764 #endif
765
766 #ifndef MULTILIB_DEFAULTS
767 #define MULTILIB_DEFAULTS \
768 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
769 #endif
770
771 /* We must pass -EL to the linker by default for little endian embedded
772 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
773 linker will default to using big-endian output files. The OUTPUT_FORMAT
774 line must be in the linker script, otherwise -EB/-EL will not work. */
775
776 #ifndef ENDIAN_SPEC
777 #if TARGET_ENDIAN_DEFAULT == 0
778 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
779 #else
780 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
781 #endif
782 #endif
783
784 #define TARGET_OPTIONS \
785 { \
786 SUBTARGET_TARGET_OPTIONS \
787 { "tune=", &mips_tune_string, \
788 N_("Specify CPU for scheduling purposes"), 0}, \
789 { "arch=", &mips_arch_string, \
790 N_("Specify CPU for code generation purposes"), 0}, \
791 { "abi=", &mips_abi_string, \
792 N_("Specify an ABI"), 0}, \
793 { "ips", &mips_isa_string, \
794 N_("Specify a Standard MIPS ISA"), 0}, \
795 { "no-flush-func", &mips_cache_flush_func, \
796 N_("Don't call any cache flush functions"), 0}, \
797 { "flush-func=", &mips_cache_flush_func, \
798 N_("Specify cache flush function"), 0}, \
799 { "fix-vr4130", &mips_fix_vr4130_string, \
800 N_("Work around VR4130 mflo/mfhi errata"), 0}, \
801 }
802
803 /* This is meant to be redefined in the host dependent files. */
804 #define SUBTARGET_TARGET_OPTIONS
805
806 /* Support for a compile-time default CPU, et cetera. The rules are:
807 --with-arch is ignored if -march is specified or a -mips is specified
808 (other than -mips16).
809 --with-tune is ignored if -mtune is specified.
810 --with-abi is ignored if -mabi is specified.
811 --with-float is ignored if -mhard-float or -msoft-float are
812 specified.
813 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
814 specified. */
815 #define OPTION_DEFAULT_SPECS \
816 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
817 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
818 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
819 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
820 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
821
822
823 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
824 && ISA_HAS_COND_TRAP)
825
826 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
827 && !TARGET_SR71K \
828 && !TARGET_MIPS16)
829
830 /* Generate three-operand multiply instructions for SImode. */
831 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
832 || TARGET_MIPS5400 \
833 || TARGET_MIPS5500 \
834 || TARGET_MIPS7000 \
835 || TARGET_MIPS9000 \
836 || TARGET_MAD \
837 || ISA_MIPS32 \
838 || ISA_MIPS32R2 \
839 || ISA_MIPS64) \
840 && !TARGET_MIPS16)
841
842 /* Generate three-operand multiply instructions for DImode. */
843 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
844 && !TARGET_MIPS16)
845
846 /* True if the ABI can only work with 64-bit integer registers. We
847 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
848 otherwise floating-point registers must also be 64-bit. */
849 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
850
851 /* Likewise for 32-bit regs. */
852 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
853
854 /* True if symbols are 64 bits wide. At present, n64 is the only
855 ABI for which this is true. */
856 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
857
858 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
859 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
860 || ISA_MIPS4 \
861 || ISA_MIPS64)
862
863 /* ISA has branch likely instructions (e.g. mips2). */
864 /* Disable branchlikely for tx39 until compare rewrite. They haven't
865 been generated up to this point. */
866 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
867
868 /* ISA has the conditional move instructions introduced in mips4. */
869 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
870 || ISA_MIPS32 \
871 || ISA_MIPS32R2 \
872 || ISA_MIPS64) \
873 && !TARGET_MIPS5500 \
874 && !TARGET_MIPS16)
875
876 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
877 branch on CC, and move (both FP and non-FP) on CC. */
878 #define ISA_HAS_8CC (ISA_MIPS4 \
879 || ISA_MIPS32 \
880 || ISA_MIPS32R2 \
881 || ISA_MIPS64)
882
883 /* This is a catch all for other mips4 instructions: indexed load, the
884 FP madd and msub instructions, and the FP recip and recip sqrt
885 instructions. */
886 #define ISA_HAS_FP4 ((ISA_MIPS4 \
887 || ISA_MIPS64) \
888 && !TARGET_MIPS16)
889
890 /* ISA has conditional trap instructions. */
891 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
892 && !TARGET_MIPS16)
893
894 /* ISA has integer multiply-accumulate instructions, madd and msub. */
895 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
896 || ISA_MIPS32R2 \
897 || ISA_MIPS64 \
898 ) && !TARGET_MIPS16)
899
900 /* ISA has floating-point nmadd and nmsub instructions. */
901 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
902 || ISA_MIPS64) \
903 && (!TARGET_MIPS5400 || TARGET_MAD) \
904 && ! TARGET_MIPS16)
905
906 /* ISA has count leading zeroes/ones instruction (not implemented). */
907 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
908 || ISA_MIPS32R2 \
909 || ISA_MIPS64 \
910 ) && !TARGET_MIPS16)
911
912 /* ISA has double-word count leading zeroes/ones instruction (not
913 implemented). */
914 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
915 && !TARGET_MIPS16)
916
917 /* ISA has three operand multiply instructions that put
918 the high part in an accumulator: mulhi or mulhiu. */
919 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
920 || TARGET_MIPS5500 \
921 || TARGET_SR71K \
922 )
923
924 /* ISA has three operand multiply instructions that
925 negates the result and puts the result in an accumulator. */
926 #define ISA_HAS_MULS (TARGET_MIPS5400 \
927 || TARGET_MIPS5500 \
928 || TARGET_SR71K \
929 )
930
931 /* ISA has three operand multiply instructions that subtracts the
932 result from a 4th operand and puts the result in an accumulator. */
933 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
934 || TARGET_MIPS5500 \
935 || TARGET_SR71K \
936 )
937 /* ISA has three operand multiply instructions that the result
938 from a 4th operand and puts the result in an accumulator. */
939 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
940 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
941 || TARGET_MIPS5400 \
942 || TARGET_MIPS5500 \
943 || TARGET_SR71K \
944 )
945
946 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
947 #define ISA_HAS_MACCHI (!TARGET_MIPS16 \
948 && (TARGET_MIPS4120 \
949 || TARGET_MIPS4130))
950
951 /* ISA has 32-bit rotate right instruction. */
952 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
953 && (ISA_MIPS32R2 \
954 || TARGET_MIPS5400 \
955 || TARGET_MIPS5500 \
956 || TARGET_SR71K \
957 ))
958
959 /* ISA has 64-bit rotate right instruction. */
960 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
961 && !TARGET_MIPS16 \
962 && (TARGET_MIPS5400 \
963 || TARGET_MIPS5500 \
964 || TARGET_SR71K \
965 ))
966
967 /* ISA has data prefetch instructions. This controls use of 'pref'. */
968 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
969 || ISA_MIPS32 \
970 || ISA_MIPS32R2 \
971 || ISA_MIPS64) \
972 && !TARGET_MIPS16)
973
974 /* ISA has data indexed prefetch instructions. This controls use of
975 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
976 (prefx is a cop1x instruction, so can only be used if FP is
977 enabled.) */
978 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
979 || ISA_MIPS64) \
980 && !TARGET_MIPS16)
981
982 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
983 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
984 also requires TARGET_DOUBLE_FLOAT. */
985 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
986
987 /* ISA includes the MIPS32r2 seb and seh instructions. */
988 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
989 && (ISA_MIPS32R2 \
990 ))
991
992 /* True if the result of a load is not available to the next instruction.
993 A nop will then be needed between instructions like "lw $4,..."
994 and "addiu $4,$4,1". */
995 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
996 && !TARGET_MIPS3900 \
997 && !TARGET_MIPS16)
998
999 /* Likewise mtc1 and mfc1. */
1000 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
1001
1002 /* Likewise floating-point comparisons. */
1003 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
1004
1005 /* True if mflo and mfhi can be immediately followed by instructions
1006 which write to the HI and LO registers.
1007
1008 According to MIPS specifications, MIPS ISAs I, II, and III need
1009 (at least) two instructions between the reads of HI/LO and
1010 instructions which write them, and later ISAs do not. Contradicting
1011 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1012 the UM for the NEC Vr5000) document needing the instructions between
1013 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1014 MIPS64 and later ISAs to have the interlocks, plus any specific
1015 earlier-ISA CPUs for which CPU documentation declares that the
1016 instructions are really interlocked. */
1017 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
1018 || ISA_MIPS32R2 \
1019 || ISA_MIPS64 \
1020 || TARGET_MIPS5500)
1021 \f
1022 /* Add -G xx support. */
1023
1024 #undef SWITCH_TAKES_ARG
1025 #define SWITCH_TAKES_ARG(CHAR) \
1026 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1027
1028 #define OVERRIDE_OPTIONS override_options ()
1029
1030 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1031
1032 /* Show we can debug even without a frame pointer. */
1033 #define CAN_DEBUG_WITHOUT_FP
1034 \f
1035 /* Tell collect what flags to pass to nm. */
1036 #ifndef NM_FLAGS
1037 #define NM_FLAGS "-Bn"
1038 #endif
1039
1040 \f
1041 #define SUBTARGET_TARGET_SWITCHES
1042
1043 #ifndef MIPS_ABI_DEFAULT
1044 #define MIPS_ABI_DEFAULT ABI_32
1045 #endif
1046
1047 /* Use the most portable ABI flag for the ASM specs. */
1048
1049 #if MIPS_ABI_DEFAULT == ABI_32
1050 #define MULTILIB_ABI_DEFAULT "mabi=32"
1051 #endif
1052
1053 #if MIPS_ABI_DEFAULT == ABI_O64
1054 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1055 #endif
1056
1057 #if MIPS_ABI_DEFAULT == ABI_N32
1058 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1059 #endif
1060
1061 #if MIPS_ABI_DEFAULT == ABI_64
1062 #define MULTILIB_ABI_DEFAULT "mabi=64"
1063 #endif
1064
1065 #if MIPS_ABI_DEFAULT == ABI_EABI
1066 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1067 #endif
1068
1069 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1070 to the assembler. It may be overridden by subtargets. */
1071 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1072 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1073 %{noasmopt:-O0} \
1074 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1075 #endif
1076
1077 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1078 the assembler. It may be overridden by subtargets.
1079
1080 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1081 COFF debugging info. */
1082
1083 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1084 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1085 %{g} %{g0} %{g1} %{g2} %{g3} \
1086 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1087 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1088 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1089 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1090 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1091 #endif
1092
1093 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1094 overridden by subtargets. */
1095
1096 #ifndef SUBTARGET_ASM_SPEC
1097 #define SUBTARGET_ASM_SPEC ""
1098 #endif
1099
1100 #undef ASM_SPEC
1101 #define ASM_SPEC "\
1102 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1103 %{mips32} %{mips32r2} %{mips64} \
1104 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1105 %{mips3d:-mips3d} \
1106 %{mfix-vr4120} %{mfix-vr4130} \
1107 %(subtarget_asm_optimizing_spec) \
1108 %(subtarget_asm_debugging_spec) \
1109 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1110 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1111 %{msym32} %{mno-sym32} \
1112 %{mtune=*} %{v} \
1113 %(subtarget_asm_spec)"
1114
1115 /* Extra switches sometimes passed to the linker. */
1116 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1117 will interpret it as a -b option. */
1118
1119 #ifndef LINK_SPEC
1120 #define LINK_SPEC "\
1121 %(endian_spec) \
1122 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1123 %{bestGnum} %{shared} %{non_shared}"
1124 #endif /* LINK_SPEC defined */
1125
1126
1127 /* Specs for the compiler proper */
1128
1129 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1130 overridden by subtargets. */
1131 #ifndef SUBTARGET_CC1_SPEC
1132 #define SUBTARGET_CC1_SPEC ""
1133 #endif
1134
1135 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1136
1137 #ifndef CC1_SPEC
1138 #define CC1_SPEC "\
1139 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1140 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1141 %{save-temps: } \
1142 %(subtarget_cc1_spec)"
1143 #endif
1144
1145 /* Preprocessor specs. */
1146
1147 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1148 overridden by subtargets. */
1149 #ifndef SUBTARGET_CPP_SPEC
1150 #define SUBTARGET_CPP_SPEC ""
1151 #endif
1152
1153 #define CPP_SPEC "%(subtarget_cpp_spec)"
1154
1155 /* This macro defines names of additional specifications to put in the specs
1156 that can be used in various specifications like CC1_SPEC. Its definition
1157 is an initializer with a subgrouping for each command option.
1158
1159 Each subgrouping contains a string constant, that defines the
1160 specification name, and a string constant that used by the GCC driver
1161 program.
1162
1163 Do not define this macro if it does not need to do anything. */
1164
1165 #define EXTRA_SPECS \
1166 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1167 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1168 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1169 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1170 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1171 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1172 { "endian_spec", ENDIAN_SPEC }, \
1173 SUBTARGET_EXTRA_SPECS
1174
1175 #ifndef SUBTARGET_EXTRA_SPECS
1176 #define SUBTARGET_EXTRA_SPECS
1177 #endif
1178 \f
1179 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1180 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1181 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1182
1183 #ifndef PREFERRED_DEBUGGING_TYPE
1184 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1185 #endif
1186
1187 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1188
1189 /* By default, turn on GDB extensions. */
1190 #define DEFAULT_GDB_EXTENSIONS 1
1191
1192 /* Local compiler-generated symbols must have a prefix that the assembler
1193 understands. By default, this is $, although some targets (e.g.,
1194 NetBSD-ELF) need to override this. */
1195
1196 #ifndef LOCAL_LABEL_PREFIX
1197 #define LOCAL_LABEL_PREFIX "$"
1198 #endif
1199
1200 /* By default on the mips, external symbols do not have an underscore
1201 prepended, but some targets (e.g., NetBSD) require this. */
1202
1203 #ifndef USER_LABEL_PREFIX
1204 #define USER_LABEL_PREFIX ""
1205 #endif
1206
1207 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1208 since the length can run past this up to a continuation point. */
1209 #undef DBX_CONTIN_LENGTH
1210 #define DBX_CONTIN_LENGTH 1500
1211
1212 /* How to renumber registers for dbx and gdb. */
1213 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1214
1215 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1216 #define DWARF_FRAME_REGNUM(REG) (REG)
1217
1218 /* The DWARF 2 CFA column which tracks the return address. */
1219 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1220
1221 /* The DWARF 2 CFA column which tracks the return address from a
1222 signal handler context. */
1223 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1224
1225 /* Before the prologue, RA lives in r31. */
1226 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1227
1228 /* Describe how we implement __builtin_eh_return. */
1229 #define EH_RETURN_DATA_REGNO(N) \
1230 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1231
1232 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1233
1234 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1235 The default for this in 64-bit mode is 8, which causes problems with
1236 SFmode register saves. */
1237 #define DWARF_CIE_DATA_ALIGNMENT 4
1238
1239 /* Correct the offset of automatic variables and arguments. Note that
1240 the MIPS debug format wants all automatic variables and arguments
1241 to be in terms of the virtual frame pointer (stack pointer before
1242 any adjustment in the function), while the MIPS 3.0 linker wants
1243 the frame pointer to be the stack pointer after the initial
1244 adjustment. */
1245
1246 #define DEBUGGER_AUTO_OFFSET(X) \
1247 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1248 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1249 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1250 \f
1251 /* Target machine storage layout */
1252
1253 #define BITS_BIG_ENDIAN 0
1254 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1255 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1256
1257 /* Define this to set the endianness to use in libgcc2.c, which can
1258 not depend on target_flags. */
1259 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1260 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1261 #else
1262 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1263 #endif
1264
1265 #define MAX_BITS_PER_WORD 64
1266
1267 /* Width of a word, in units (bytes). */
1268 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1269 #define MIN_UNITS_PER_WORD 4
1270
1271 /* For MIPS, width of a floating point register. */
1272 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1273
1274 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1275 the next available register. */
1276 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1277
1278 /* The largest size of value that can be held in floating-point
1279 registers and moved with a single instruction. */
1280 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1281
1282 /* The largest size of value that can be held in floating-point
1283 registers. */
1284 #define UNITS_PER_FPVALUE \
1285 (TARGET_SOFT_FLOAT ? 0 \
1286 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1287 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1288
1289 /* The number of bytes in a double. */
1290 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1291
1292 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : 0)
1293
1294 /* Set the sizes of the core types. */
1295 #define SHORT_TYPE_SIZE 16
1296 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1297 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1298 #define LONG_LONG_TYPE_SIZE 64
1299
1300 #define FLOAT_TYPE_SIZE 32
1301 #define DOUBLE_TYPE_SIZE 64
1302 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1303
1304 /* long double is not a fixed mode, but the idea is that, if we
1305 support long double, we also want a 128-bit integer type. */
1306 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1307
1308 #ifdef IN_LIBGCC2
1309 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1310 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1311 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1312 # else
1313 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1314 # endif
1315 #endif
1316
1317 /* Width in bits of a pointer. */
1318 #ifndef POINTER_SIZE
1319 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1320 #endif
1321
1322 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1323 #define PARM_BOUNDARY BITS_PER_WORD
1324
1325 /* Allocation boundary (in *bits*) for the code of a function. */
1326 #define FUNCTION_BOUNDARY 32
1327
1328 /* Alignment of field after `int : 0' in a structure. */
1329 #define EMPTY_FIELD_BOUNDARY 32
1330
1331 /* Every structure's size must be a multiple of this. */
1332 /* 8 is observed right on a DECstation and on riscos 4.02. */
1333 #define STRUCTURE_SIZE_BOUNDARY 8
1334
1335 /* There is no point aligning anything to a rounder boundary than this. */
1336 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1337
1338 /* All accesses must be aligned. */
1339 #define STRICT_ALIGNMENT 1
1340
1341 /* Define this if you wish to imitate the way many other C compilers
1342 handle alignment of bitfields and the structures that contain
1343 them.
1344
1345 The behavior is that the type written for a bit-field (`int',
1346 `short', or other integer type) imposes an alignment for the
1347 entire structure, as if the structure really did contain an
1348 ordinary field of that type. In addition, the bit-field is placed
1349 within the structure so that it would fit within such a field,
1350 not crossing a boundary for it.
1351
1352 Thus, on most machines, a bit-field whose type is written as `int'
1353 would not cross a four-byte boundary, and would force four-byte
1354 alignment for the whole structure. (The alignment used may not
1355 be four bytes; it is controlled by the other alignment
1356 parameters.)
1357
1358 If the macro is defined, its definition should be a C expression;
1359 a nonzero value for the expression enables this behavior. */
1360
1361 #define PCC_BITFIELD_TYPE_MATTERS 1
1362
1363 /* If defined, a C expression to compute the alignment given to a
1364 constant that is being placed in memory. CONSTANT is the constant
1365 and ALIGN is the alignment that the object would ordinarily have.
1366 The value of this macro is used instead of that alignment to align
1367 the object.
1368
1369 If this macro is not defined, then ALIGN is used.
1370
1371 The typical use of this macro is to increase alignment for string
1372 constants to be word aligned so that `strcpy' calls that copy
1373 constants can be done inline. */
1374
1375 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1376 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1377 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1378
1379 /* If defined, a C expression to compute the alignment for a static
1380 variable. TYPE is the data type, and ALIGN is the alignment that
1381 the object would ordinarily have. The value of this macro is used
1382 instead of that alignment to align the object.
1383
1384 If this macro is not defined, then ALIGN is used.
1385
1386 One use of this macro is to increase alignment of medium-size
1387 data to make it all fit in fewer cache lines. Another is to
1388 cause character arrays to be word-aligned so that `strcpy' calls
1389 that copy constants to character arrays can be done inline. */
1390
1391 #undef DATA_ALIGNMENT
1392 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1393 ((((ALIGN) < BITS_PER_WORD) \
1394 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1395 || TREE_CODE (TYPE) == UNION_TYPE \
1396 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1397
1398
1399 #define PAD_VARARGS_DOWN \
1400 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1401
1402 /* Define if operations between registers always perform the operation
1403 on the full register even if a narrower mode is specified. */
1404 #define WORD_REGISTER_OPERATIONS
1405
1406 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1407 moves. All other references are zero extended. */
1408 #define LOAD_EXTEND_OP(MODE) \
1409 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1410 ? SIGN_EXTEND : ZERO_EXTEND)
1411
1412 /* Define this macro if it is advisable to hold scalars in registers
1413 in a wider mode than that declared by the program. In such cases,
1414 the value is constrained to be within the bounds of the declared
1415 type, but kept valid in the wider mode. The signedness of the
1416 extension may differ from that of the type. */
1417
1418 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1419 if (GET_MODE_CLASS (MODE) == MODE_INT \
1420 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1421 { \
1422 if ((MODE) == SImode) \
1423 (UNSIGNEDP) = 0; \
1424 (MODE) = Pmode; \
1425 }
1426
1427 /* Define if loading short immediate values into registers sign extends. */
1428 #define SHORT_IMMEDIATES_SIGN_EXTEND
1429 \f
1430 /* Standard register usage. */
1431
1432 /* Number of hardware registers. We have:
1433
1434 - 32 integer registers
1435 - 32 floating point registers
1436 - 8 condition code registers
1437 - 2 accumulator registers (hi and lo)
1438 - 32 registers each for coprocessors 0, 2 and 3
1439 - 3 fake registers:
1440 - ARG_POINTER_REGNUM
1441 - FRAME_POINTER_REGNUM
1442 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1443 - 3 dummy entries that were used at various times in the past. */
1444
1445 #define FIRST_PSEUDO_REGISTER 176
1446
1447 /* By default, fix the kernel registers ($26 and $27), the global
1448 pointer ($28) and the stack pointer ($29). This can change
1449 depending on the command-line options.
1450
1451 Regarding coprocessor registers: without evidence to the contrary,
1452 it's best to assume that each coprocessor register has a unique
1453 use. This can be overridden, in, e.g., override_options() or
1454 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1455 for a particular target. */
1456
1457 #define FIXED_REGISTERS \
1458 { \
1459 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1463 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1464 /* COP0 registers */ \
1465 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1466 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1467 /* COP2 registers */ \
1468 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1469 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1470 /* COP3 registers */ \
1471 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1472 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1473 }
1474
1475
1476 /* Set up this array for o32 by default.
1477
1478 Note that we don't mark $31 as a call-clobbered register. The idea is
1479 that it's really the call instructions themselves which clobber $31.
1480 We don't care what the called function does with it afterwards.
1481
1482 This approach makes it easier to implement sibcalls. Unlike normal
1483 calls, sibcalls don't clobber $31, so the register reaches the
1484 called function in tact. EPILOGUE_USES says that $31 is useful
1485 to the called function. */
1486
1487 #define CALL_USED_REGISTERS \
1488 { \
1489 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1490 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1491 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1492 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1493 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1494 /* COP0 registers */ \
1495 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1496 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1497 /* COP2 registers */ \
1498 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1499 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1500 /* COP3 registers */ \
1501 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1502 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1503 }
1504
1505
1506 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1507
1508 #define CALL_REALLY_USED_REGISTERS \
1509 { /* General registers. */ \
1510 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1511 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1512 /* Floating-point registers. */ \
1513 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1514 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1515 /* Others. */ \
1516 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1517 /* COP0 registers */ \
1518 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1519 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1520 /* COP2 registers */ \
1521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1522 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1523 /* COP3 registers */ \
1524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1526 }
1527
1528 /* Internal macros to classify a register number as to whether it's a
1529 general purpose register, a floating point register, a
1530 multiply/divide register, or a status register. */
1531
1532 #define GP_REG_FIRST 0
1533 #define GP_REG_LAST 31
1534 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1535 #define GP_DBX_FIRST 0
1536
1537 #define FP_REG_FIRST 32
1538 #define FP_REG_LAST 63
1539 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1540 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1541
1542 #define MD_REG_FIRST 64
1543 #define MD_REG_LAST 65
1544 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1545 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1546
1547 #define ST_REG_FIRST 67
1548 #define ST_REG_LAST 74
1549 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1550
1551
1552 /* FIXME: renumber. */
1553 #define COP0_REG_FIRST 80
1554 #define COP0_REG_LAST 111
1555 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1556
1557 #define COP2_REG_FIRST 112
1558 #define COP2_REG_LAST 143
1559 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1560
1561 #define COP3_REG_FIRST 144
1562 #define COP3_REG_LAST 175
1563 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1564 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1565 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1566
1567 #define AT_REGNUM (GP_REG_FIRST + 1)
1568 #define HI_REGNUM (MD_REG_FIRST + 0)
1569 #define LO_REGNUM (MD_REG_FIRST + 1)
1570
1571 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1572 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1573 should be used instead. */
1574 #define FPSW_REGNUM ST_REG_FIRST
1575
1576 #define GP_REG_P(REGNO) \
1577 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1578 #define M16_REG_P(REGNO) \
1579 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1580 #define FP_REG_P(REGNO) \
1581 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1582 #define MD_REG_P(REGNO) \
1583 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1584 #define ST_REG_P(REGNO) \
1585 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1586 #define COP0_REG_P(REGNO) \
1587 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1588 #define COP2_REG_P(REGNO) \
1589 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1590 #define COP3_REG_P(REGNO) \
1591 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1592 #define ALL_COP_REG_P(REGNO) \
1593 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1594
1595 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1596
1597 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1598 to initialize the mips16 gp pseudo register. */
1599 #define CONST_GP_P(X) \
1600 (GET_CODE (X) == CONST \
1601 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1602 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1603
1604 /* Return coprocessor number from register number. */
1605
1606 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1607 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1608 : COP3_REG_P (REGNO) ? '3' : '?')
1609
1610
1611 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1612
1613 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1614 array built in override_options. Because machmodes.h is not yet
1615 included before this file is processed, the MODE bound can't be
1616 expressed here. */
1617
1618 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1619
1620 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1621 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1622
1623 /* Value is 1 if it is a good idea to tie two pseudo registers
1624 when one has mode MODE1 and one has mode MODE2.
1625 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1626 for any hard reg, then this must be 0 for correct output. */
1627 #define MODES_TIEABLE_P(MODE1, MODE2) \
1628 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1629 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1630 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1631 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1632
1633 /* Register to use for pushing function arguments. */
1634 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1635
1636 /* These two registers don't really exist: they get eliminated to either
1637 the stack or hard frame pointer. */
1638 #define ARG_POINTER_REGNUM 77
1639 #define FRAME_POINTER_REGNUM 78
1640
1641 /* $30 is not available on the mips16, so we use $17 as the frame
1642 pointer. */
1643 #define HARD_FRAME_POINTER_REGNUM \
1644 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1645
1646 /* Value should be nonzero if functions must have frame pointers.
1647 Zero means the frame pointer need not be set up (and parms
1648 may be accessed via the stack pointer) in functions that seem suitable.
1649 This is computed in `reload', in reload1.c. */
1650 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1651
1652 /* Register in which static-chain is passed to a function. */
1653 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1654
1655 /* Registers used as temporaries in prologue/epilogue code. If we're
1656 generating mips16 code, these registers must come from the core set
1657 of 8. The prologue register mustn't conflict with any incoming
1658 arguments, the static chain pointer, or the frame pointer. The
1659 epilogue temporary mustn't conflict with the return registers, the
1660 frame pointer, the EH stack adjustment, or the EH data registers. */
1661
1662 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1663 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1664
1665 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1666 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1667
1668 /* Define this macro if it is as good or better to call a constant
1669 function address than to call an address kept in a register. */
1670 #define NO_FUNCTION_CSE 1
1671
1672 /* The ABI-defined global pointer. Sometimes we use a different
1673 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1674 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1675
1676 /* We normally use $28 as the global pointer. However, when generating
1677 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1678 register instead. They can then avoid saving and restoring $28
1679 and perhaps avoid using a frame at all.
1680
1681 When a leaf function uses something other than $28, mips_expand_prologue
1682 will modify pic_offset_table_rtx in place. Take the register number
1683 from there after reload. */
1684 #define PIC_OFFSET_TABLE_REGNUM \
1685 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1686
1687 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1688 \f
1689 /* Define the classes of registers for register constraints in the
1690 machine description. Also define ranges of constants.
1691
1692 One of the classes must always be named ALL_REGS and include all hard regs.
1693 If there is more than one class, another class must be named NO_REGS
1694 and contain no registers.
1695
1696 The name GENERAL_REGS must be the name of a class (or an alias for
1697 another name such as ALL_REGS). This is the class of registers
1698 that is allowed by "g" or "r" in a register constraint.
1699 Also, registers outside this class are allocated only when
1700 instructions express preferences for them.
1701
1702 The classes must be numbered in nondecreasing order; that is,
1703 a larger-numbered class must never be contained completely
1704 in a smaller-numbered class.
1705
1706 For any two classes, it is very desirable that there be another
1707 class that represents their union. */
1708
1709 enum reg_class
1710 {
1711 NO_REGS, /* no registers in set */
1712 M16_NA_REGS, /* mips16 regs not used to pass args */
1713 M16_REGS, /* mips16 directly accessible registers */
1714 T_REG, /* mips16 T register ($24) */
1715 M16_T_REGS, /* mips16 registers plus T register */
1716 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1717 V1_REG, /* Register $v1 ($3) used for TLS access. */
1718 LEA_REGS, /* Every GPR except $25 */
1719 GR_REGS, /* integer registers */
1720 FP_REGS, /* floating point registers */
1721 HI_REG, /* hi register */
1722 LO_REG, /* lo register */
1723 MD_REGS, /* multiply/divide registers (hi/lo) */
1724 COP0_REGS, /* generic coprocessor classes */
1725 COP2_REGS,
1726 COP3_REGS,
1727 HI_AND_GR_REGS, /* union classes */
1728 LO_AND_GR_REGS,
1729 HI_AND_FP_REGS,
1730 COP0_AND_GR_REGS,
1731 COP2_AND_GR_REGS,
1732 COP3_AND_GR_REGS,
1733 ALL_COP_REGS,
1734 ALL_COP_AND_GR_REGS,
1735 ST_REGS, /* status registers (fp status) */
1736 ALL_REGS, /* all registers */
1737 LIM_REG_CLASSES /* max value + 1 */
1738 };
1739
1740 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1741
1742 #define GENERAL_REGS GR_REGS
1743
1744 /* An initializer containing the names of the register classes as C
1745 string constants. These names are used in writing some of the
1746 debugging dumps. */
1747
1748 #define REG_CLASS_NAMES \
1749 { \
1750 "NO_REGS", \
1751 "M16_NA_REGS", \
1752 "M16_REGS", \
1753 "T_REG", \
1754 "M16_T_REGS", \
1755 "PIC_FN_ADDR_REG", \
1756 "V1_REG", \
1757 "LEA_REGS", \
1758 "GR_REGS", \
1759 "FP_REGS", \
1760 "HI_REG", \
1761 "LO_REG", \
1762 "MD_REGS", \
1763 /* coprocessor registers */ \
1764 "COP0_REGS", \
1765 "COP2_REGS", \
1766 "COP3_REGS", \
1767 "HI_AND_GR_REGS", \
1768 "LO_AND_GR_REGS", \
1769 "HI_AND_FP_REGS", \
1770 "COP0_AND_GR_REGS", \
1771 "COP2_AND_GR_REGS", \
1772 "COP3_AND_GR_REGS", \
1773 "ALL_COP_REGS", \
1774 "ALL_COP_AND_GR_REGS", \
1775 "ST_REGS", \
1776 "ALL_REGS" \
1777 }
1778
1779 /* An initializer containing the contents of the register classes,
1780 as integers which are bit masks. The Nth integer specifies the
1781 contents of class N. The way the integer MASK is interpreted is
1782 that register R is in the class if `MASK & (1 << R)' is 1.
1783
1784 When the machine has more than 32 registers, an integer does not
1785 suffice. Then the integers are replaced by sub-initializers,
1786 braced groupings containing several integers. Each
1787 sub-initializer must be suitable as an initializer for the type
1788 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1789
1790 #define REG_CLASS_CONTENTS \
1791 { \
1792 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1793 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1794 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1795 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1796 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1797 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1798 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1799 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1800 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1801 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1802 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1803 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1804 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1805 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1806 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1807 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1808 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1809 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1810 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1811 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1812 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1813 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1814 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1815 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1816 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1817 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1818 }
1819
1820
1821 /* A C expression whose value is a register class containing hard
1822 register REGNO. In general there is more that one such class;
1823 choose a class which is "minimal", meaning that no smaller class
1824 also contains the register. */
1825
1826 extern const enum reg_class mips_regno_to_class[];
1827
1828 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1829
1830 /* A macro whose definition is the name of the class to which a
1831 valid base register must belong. A base register is one used in
1832 an address which is the register value plus a displacement. */
1833
1834 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1835
1836 /* A macro whose definition is the name of the class to which a
1837 valid index register must belong. An index register is one used
1838 in an address where its value is either multiplied by a scale
1839 factor or added to another register (as well as added to a
1840 displacement). */
1841
1842 #define INDEX_REG_CLASS NO_REGS
1843
1844 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1845 registers explicitly used in the rtl to be used as spill registers
1846 but prevents the compiler from extending the lifetime of these
1847 registers. */
1848
1849 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1850
1851 /* This macro is used later on in the file. */
1852 #define GR_REG_CLASS_P(CLASS) \
1853 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1854 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1855 || (CLASS) == V1_REG \
1856 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1857
1858 /* This macro is also used later on in the file. */
1859 #define COP_REG_CLASS_P(CLASS) \
1860 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1861
1862 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1863 is the default value (allocate the registers in numeric order). We
1864 define it just so that we can override it for the mips16 target in
1865 ORDER_REGS_FOR_LOCAL_ALLOC. */
1866
1867 #define REG_ALLOC_ORDER \
1868 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1869 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1870 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1871 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1872 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1873 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1874 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1875 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1876 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1877 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1878 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1879 }
1880
1881 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1882 to be rearranged based on a particular function. On the mips16, we
1883 want to allocate $24 (T_REG) before other registers for
1884 instructions for which it is possible. */
1885
1886 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1887
1888 /* REGISTER AND CONSTANT CLASSES */
1889
1890 /* Get reg_class from a letter such as appears in the machine
1891 description.
1892
1893 DEFINED REGISTER CLASSES:
1894
1895 'd' General (aka integer) registers
1896 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1897 'y' General registers (in both mips16 and non mips16 mode)
1898 'e' Effective address registers (general registers except $25)
1899 't' mips16 temporary register ($24)
1900 'f' Floating point registers
1901 'h' Hi register
1902 'l' Lo register
1903 'v' $v1 only
1904 'x' Multiply/divide registers
1905 'z' FP Status register
1906 'B' Cop0 register
1907 'C' Cop2 register
1908 'D' Cop3 register
1909 'b' All registers */
1910
1911 extern enum reg_class mips_char_to_class[256];
1912
1913 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1914
1915 /* True if VALUE is a signed 16-bit number. */
1916
1917 #define SMALL_OPERAND(VALUE) \
1918 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1919
1920 /* True if VALUE is an unsigned 16-bit number. */
1921
1922 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1923 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1924
1925 /* True if VALUE can be loaded into a register using LUI. */
1926
1927 #define LUI_OPERAND(VALUE) \
1928 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1929 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1930
1931 /* Return a value X with the low 16 bits clear, and such that
1932 VALUE - X is a signed 16-bit value. */
1933
1934 #define CONST_HIGH_PART(VALUE) \
1935 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1936
1937 #define CONST_LOW_PART(VALUE) \
1938 ((VALUE) - CONST_HIGH_PART (VALUE))
1939
1940 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1941 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1942 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1943
1944 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1945 string can be used to stand for particular ranges of immediate
1946 operands. This macro defines what the ranges are. C is the
1947 letter, and VALUE is a constant value. Return 1 if VALUE is
1948 in the range specified by C. */
1949
1950 /* For MIPS:
1951
1952 `I' is used for the range of constants an arithmetic insn can
1953 actually contain (16 bits signed integers).
1954
1955 `J' is used for the range which is just zero (i.e., $r0).
1956
1957 `K' is used for the range of constants a logical insn can actually
1958 contain (16 bit zero-extended integers).
1959
1960 `L' is used for the range of constants that be loaded with lui
1961 (i.e., the bottom 16 bits are zero).
1962
1963 `M' is used for the range of constants that take two words to load
1964 (i.e., not matched by `I', `K', and `L').
1965
1966 `N' is used for negative 16 bit constants other than -65536.
1967
1968 `O' is a 15 bit signed integer.
1969
1970 `P' is used for positive 16 bit constants. */
1971
1972 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1973 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1974 : (C) == 'J' ? ((VALUE) == 0) \
1975 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1976 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1977 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1978 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1979 && !LUI_OPERAND (VALUE)) \
1980 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1981 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1982 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1983 : 0)
1984
1985 /* Similar, but for floating constants, and defining letters G and H.
1986 Here VALUE is the CONST_DOUBLE rtx itself. */
1987
1988 /* For Mips
1989
1990 'G' : Floating point 0 */
1991
1992 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1993 ((C) == 'G' \
1994 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1995
1996 /* Letters in the range `Q' through `U' may be defined in a
1997 machine-dependent fashion to stand for arbitrary operand types.
1998 The machine description macro `EXTRA_CONSTRAINT' is passed the
1999 operand as its first argument and the constraint letter as its
2000 second operand.
2001
2002 `Q' is for signed 16-bit constants.
2003 `R' is for single-instruction memory references. Note that this
2004 constraint has often been used in linux and glibc code.
2005 `S' is for legitimate constant call addresses.
2006 `T' is for constant move_operands that cannot be safely loaded into $25.
2007 `U' is for constant move_operands that can be safely loaded into $25.
2008 `W' is for memory references that are based on a member of BASE_REG_CLASS.
2009 This is true for all non-mips16 references (although it can sometimes
2010 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
2011 stack and constant-pool references.
2012 `YG' is for 0 valued vector constants. */
2013
2014 #define EXTRA_CONSTRAINT_Y(OP,STR) \
2015 (((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
2016 && (OP) == CONST0_RTX (GET_MODE (OP))) \
2017 : FALSE)
2018
2019
2020 #define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
2021 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
2022 : ((CODE) == 'R') ? (MEM_P (OP) \
2023 && mips_fetch_insns (OP) == 1) \
2024 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
2025 && call_insn_operand (OP, VOIDmode)) \
2026 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
2027 && move_operand (OP, VOIDmode) \
2028 && mips_dangerous_for_la25_p (OP)) \
2029 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2030 && move_operand (OP, VOIDmode) \
2031 && !mips_dangerous_for_la25_p (OP)) \
2032 : ((CODE) == 'W') ? (MEM_P (OP) \
2033 && memory_operand (OP, VOIDmode) \
2034 && (!TARGET_MIPS16 \
2035 || (!stack_operand (OP, VOIDmode) \
2036 && !CONSTANT_P (XEXP (OP, 0))))) \
2037 : ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
2038 : FALSE)
2039
2040 /* Y is the only multi-letter constraint, and has length 2. */
2041
2042 #define CONSTRAINT_LEN(C,STR) \
2043 (((C) == 'Y') ? 2 \
2044 : DEFAULT_CONSTRAINT_LEN (C, STR))
2045
2046 /* Say which of the above are memory constraints. */
2047 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2048
2049 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2050 mips_preferred_reload_class (X, CLASS)
2051
2052 /* Certain machines have the property that some registers cannot be
2053 copied to some other registers without using memory. Define this
2054 macro on those machines to be a C expression that is nonzero if
2055 objects of mode MODE in registers of CLASS1 can only be copied to
2056 registers of class CLASS2 by storing a register of CLASS1 into
2057 memory and loading that memory location into a register of CLASS2.
2058
2059 Do not define this macro if its value would always be zero. */
2060 #if 0
2061 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2062 ((!TARGET_DEBUG_H_MODE \
2063 && GET_MODE_CLASS (MODE) == MODE_INT \
2064 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2065 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2066 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2067 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2068 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2069 #endif
2070 /* The HI and LO registers can only be reloaded via the general
2071 registers. Condition code registers can only be loaded to the
2072 general registers, and from the floating point registers. */
2073
2074 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2075 mips_secondary_reload_class (CLASS, MODE, X, 1)
2076 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2077 mips_secondary_reload_class (CLASS, MODE, X, 0)
2078
2079 /* Return the maximum number of consecutive registers
2080 needed to represent mode MODE in a register of class CLASS. */
2081
2082 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2083
2084 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2085 mips_cannot_change_mode_class (FROM, TO, CLASS)
2086 \f
2087 /* Stack layout; function entry, exit and calling. */
2088
2089 #define STACK_GROWS_DOWNWARD
2090
2091 /* The offset of the first local variable from the beginning of the frame.
2092 See compute_frame_size for details about the frame layout.
2093
2094 ??? If flag_profile_values is true, and we are generating 32-bit code, then
2095 we assume that we will need 16 bytes of argument space. This is because
2096 the value profiling code may emit calls to cmpdi2 in leaf functions.
2097 Without this hack, the local variables will start at sp+8 and the gp save
2098 area will be at sp+16, and thus they will overlap. compute_frame_size is
2099 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
2100 will end up as 24 instead of 8. This won't be needed if profiling code is
2101 inserted before virtual register instantiation. */
2102
2103 #define STARTING_FRAME_OFFSET \
2104 ((flag_profile_values && ! TARGET_64BIT \
2105 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
2106 : current_function_outgoing_args_size) \
2107 + (TARGET_ABICALLS && !TARGET_NEWABI \
2108 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2109
2110 #define RETURN_ADDR_RTX mips_return_addr
2111
2112 /* Since the mips16 ISA mode is encoded in the least-significant bit
2113 of the address, mask it off return addresses for purposes of
2114 finding exception handling regions. */
2115
2116 #define MASK_RETURN_ADDR GEN_INT (-2)
2117
2118
2119 /* Similarly, don't use the least-significant bit to tell pointers to
2120 code from vtable index. */
2121
2122 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2123
2124 /* The eliminations to $17 are only used for mips16 code. See the
2125 definition of HARD_FRAME_POINTER_REGNUM. */
2126
2127 #define ELIMINABLE_REGS \
2128 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2129 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2130 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2131 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2132 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2133 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2134
2135 /* We can always eliminate to the hard frame pointer. We can eliminate
2136 to the stack pointer unless a frame pointer is needed.
2137
2138 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2139 reload may be unable to compute the address of a local variable,
2140 since there is no way to add a large constant to the stack pointer
2141 without using a temporary register. */
2142 #define CAN_ELIMINATE(FROM, TO) \
2143 ((TO) == HARD_FRAME_POINTER_REGNUM \
2144 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2145 && (!TARGET_MIPS16 \
2146 || compute_frame_size (get_frame_size ()) < 32768)))
2147
2148 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2149 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2150
2151 /* Allocate stack space for arguments at the beginning of each function. */
2152 #define ACCUMULATE_OUTGOING_ARGS 1
2153
2154 /* The argument pointer always points to the first argument. */
2155 #define FIRST_PARM_OFFSET(FNDECL) 0
2156
2157 /* o32 and o64 reserve stack space for all argument registers. */
2158 #define REG_PARM_STACK_SPACE(FNDECL) \
2159 (TARGET_OLDABI \
2160 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2161 : 0)
2162
2163 /* Define this if it is the responsibility of the caller to
2164 allocate the area reserved for arguments passed in registers.
2165 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2166 of this macro is to determine whether the space is included in
2167 `current_function_outgoing_args_size'. */
2168 #define OUTGOING_REG_PARM_STACK_SPACE
2169
2170 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2171 \f
2172 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2173
2174 /* Symbolic macros for the registers used to return integer and floating
2175 point values. */
2176
2177 #define GP_RETURN (GP_REG_FIRST + 2)
2178 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2179
2180 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2181
2182 /* Symbolic macros for the first/last argument registers. */
2183
2184 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2185 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2186 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2187 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2188
2189 #define LIBCALL_VALUE(MODE) \
2190 mips_function_value (NULL_TREE, NULL, (MODE))
2191
2192 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2193 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2194
2195 /* 1 if N is a possible register number for a function value.
2196 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2197 Currently, R2 and F0 are only implemented here (C has no complex type) */
2198
2199 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2200 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2201 && (N) == FP_RETURN + 2))
2202
2203 /* 1 if N is a possible register number for function argument passing.
2204 We have no FP argument registers when soft-float. When FP registers
2205 are 32 bits, we can't directly reference the odd numbered ones. */
2206
2207 #define FUNCTION_ARG_REGNO_P(N) \
2208 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2209 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2210 && !fixed_regs[N])
2211 \f
2212 /* This structure has to cope with two different argument allocation
2213 schemes. Most MIPS ABIs view the arguments as a structure, of which
2214 the first N words go in registers and the rest go on the stack. If I
2215 < N, the Ith word might go in Ith integer argument register or in a
2216 floating-point register. For these ABIs, we only need to remember
2217 the offset of the current argument into the structure.
2218
2219 The EABI instead allocates the integer and floating-point arguments
2220 separately. The first N words of FP arguments go in FP registers,
2221 the rest go on the stack. Likewise, the first N words of the other
2222 arguments go in integer registers, and the rest go on the stack. We
2223 need to maintain three counts: the number of integer registers used,
2224 the number of floating-point registers used, and the number of words
2225 passed on the stack.
2226
2227 We could keep separate information for the two ABIs (a word count for
2228 the standard ABIs, and three separate counts for the EABI). But it
2229 seems simpler to view the standard ABIs as forms of EABI that do not
2230 allocate floating-point registers.
2231
2232 So for the standard ABIs, the first N words are allocated to integer
2233 registers, and function_arg decides on an argument-by-argument basis
2234 whether that argument should really go in an integer register, or in
2235 a floating-point one. */
2236
2237 typedef struct mips_args {
2238 /* Always true for varargs functions. Otherwise true if at least
2239 one argument has been passed in an integer register. */
2240 int gp_reg_found;
2241
2242 /* The number of arguments seen so far. */
2243 unsigned int arg_number;
2244
2245 /* The number of integer registers used so far. For all ABIs except
2246 EABI, this is the number of words that have been added to the
2247 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2248 unsigned int num_gprs;
2249
2250 /* For EABI, the number of floating-point registers used so far. */
2251 unsigned int num_fprs;
2252
2253 /* The number of words passed on the stack. */
2254 unsigned int stack_words;
2255
2256 /* On the mips16, we need to keep track of which floating point
2257 arguments were passed in general registers, but would have been
2258 passed in the FP regs if this were a 32 bit function, so that we
2259 can move them to the FP regs if we wind up calling a 32 bit
2260 function. We record this information in fp_code, encoded in base
2261 four. A zero digit means no floating point argument, a one digit
2262 means an SFmode argument, and a two digit means a DFmode argument,
2263 and a three digit is not used. The low order digit is the first
2264 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2265 an SFmode argument. ??? A more sophisticated approach will be
2266 needed if MIPS_ABI != ABI_32. */
2267 int fp_code;
2268
2269 /* True if the function has a prototype. */
2270 int prototype;
2271 } CUMULATIVE_ARGS;
2272
2273 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2274 for a call to a function whose data type is FNTYPE.
2275 For a library call, FNTYPE is 0. */
2276
2277 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2278 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2279
2280 /* Update the data in CUM to advance over an argument
2281 of mode MODE and data type TYPE.
2282 (TYPE is null for libcalls where that information may not be available.) */
2283
2284 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2285 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2286
2287 /* Determine where to put an argument to a function.
2288 Value is zero to push the argument on the stack,
2289 or a hard register in which to store the argument.
2290
2291 MODE is the argument's machine mode.
2292 TYPE is the data type of the argument (as a tree).
2293 This is null for libcalls where that information may
2294 not be available.
2295 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2296 the preceding args and about the function being called.
2297 NAMED is nonzero if this argument is a named parameter
2298 (otherwise it is an extra parameter matching an ellipsis). */
2299
2300 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2301 function_arg( &CUM, MODE, TYPE, NAMED)
2302
2303 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2304
2305 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2306 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2307
2308 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2309 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2310
2311 /* True if using EABI and varargs can be passed in floating-point
2312 registers. Under these conditions, we need a more complex form
2313 of va_list, which tracks GPR, FPR and stack arguments separately. */
2314 #define EABI_FLOAT_VARARGS_P \
2315 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2316
2317 \f
2318 /* Say that the epilogue uses the return address register. Note that
2319 in the case of sibcalls, the values "used by the epilogue" are
2320 considered live at the start of the called function. */
2321 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2322
2323 /* Treat LOC as a byte offset from the stack pointer and round it up
2324 to the next fully-aligned offset. */
2325 #define MIPS_STACK_ALIGN(LOC) \
2326 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2327
2328 \f
2329 /* Implement `va_start' for varargs and stdarg. */
2330 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2331 mips_va_start (valist, nextarg)
2332 \f
2333 /* Output assembler code to FILE to increment profiler label # LABELNO
2334 for profiling a function entry. */
2335
2336 #define FUNCTION_PROFILER(FILE, LABELNO) \
2337 { \
2338 if (TARGET_MIPS16) \
2339 sorry ("mips16 function profiling"); \
2340 fprintf (FILE, "\t.set\tnoat\n"); \
2341 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2342 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2343 if (!TARGET_NEWABI) \
2344 { \
2345 fprintf (FILE, \
2346 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2347 TARGET_64BIT ? "dsubu" : "subu", \
2348 reg_names[STACK_POINTER_REGNUM], \
2349 reg_names[STACK_POINTER_REGNUM], \
2350 Pmode == DImode ? 16 : 8); \
2351 } \
2352 fprintf (FILE, "\tjal\t_mcount\n"); \
2353 fprintf (FILE, "\t.set\tat\n"); \
2354 }
2355
2356 /* No mips port has ever used the profiler counter word, so don't emit it
2357 or the label for it. */
2358
2359 #define NO_PROFILE_COUNTERS 1
2360
2361 /* Define this macro if the code for function profiling should come
2362 before the function prologue. Normally, the profiling code comes
2363 after. */
2364
2365 /* #define PROFILE_BEFORE_PROLOGUE */
2366
2367 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2368 the stack pointer does not matter. The value is tested only in
2369 functions that have frame pointers.
2370 No definition is equivalent to always zero. */
2371
2372 #define EXIT_IGNORE_STACK 1
2373
2374 \f
2375 /* A C statement to output, on the stream FILE, assembler code for a
2376 block of data that contains the constant parts of a trampoline.
2377 This code should not include a label--the label is taken care of
2378 automatically. */
2379
2380 #define TRAMPOLINE_TEMPLATE(STREAM) \
2381 { \
2382 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2383 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2384 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2385 if (ptr_mode == DImode) \
2386 { \
2387 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2388 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2389 } \
2390 else \
2391 { \
2392 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2393 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2394 } \
2395 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2396 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2397 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2398 if (ptr_mode == DImode) \
2399 { \
2400 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2401 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2402 } \
2403 else \
2404 { \
2405 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2406 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2407 } \
2408 }
2409
2410 /* A C expression for the size in bytes of the trampoline, as an
2411 integer. */
2412
2413 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2414
2415 /* Alignment required for trampolines, in bits. */
2416
2417 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2418
2419 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2420 program and data caches. */
2421
2422 #ifndef CACHE_FLUSH_FUNC
2423 #define CACHE_FLUSH_FUNC "_flush_cache"
2424 #endif
2425
2426 /* A C statement to initialize the variable parts of a trampoline.
2427 ADDR is an RTX for the address of the trampoline; FNADDR is an
2428 RTX for the address of the nested function; STATIC_CHAIN is an
2429 RTX for the static chain value that should be passed to the
2430 function when it is called. */
2431
2432 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2433 { \
2434 rtx func_addr, chain_addr; \
2435 \
2436 func_addr = plus_constant (ADDR, 32); \
2437 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2438 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2439 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2440 \
2441 /* Flush both caches. We need to flush the data cache in case \
2442 the system has a write-back cache. */ \
2443 /* ??? Should check the return value for errors. */ \
2444 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2445 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2446 0, VOIDmode, 3, ADDR, Pmode, \
2447 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2448 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2449 }
2450 \f
2451 /* Addressing modes, and classification of registers for them. */
2452
2453 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2454 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2455 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2456
2457 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2458 and check its validity for a certain class.
2459 We have two alternate definitions for each of them.
2460 The usual definition accepts all pseudo regs; the other rejects them all.
2461 The symbol REG_OK_STRICT causes the latter definition to be used.
2462
2463 Most source files want to accept pseudo regs in the hope that
2464 they will get allocated to the class that the insn wants them to be in.
2465 Some source files that are used after register allocation
2466 need to be strict. */
2467
2468 #ifndef REG_OK_STRICT
2469 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2470 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2471 #else
2472 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2473 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2474 #endif
2475
2476 #define REG_OK_FOR_INDEX_P(X) 0
2477
2478 \f
2479 /* Maximum number of registers that can appear in a valid memory address. */
2480
2481 #define MAX_REGS_PER_ADDRESS 1
2482
2483 #ifdef REG_OK_STRICT
2484 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2485 { \
2486 if (mips_legitimate_address_p (MODE, X, 1)) \
2487 goto ADDR; \
2488 }
2489 #else
2490 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2491 { \
2492 if (mips_legitimate_address_p (MODE, X, 0)) \
2493 goto ADDR; \
2494 }
2495 #endif
2496
2497 /* Check for constness inline but use mips_legitimate_address_p
2498 to check whether a constant really is an address. */
2499
2500 #define CONSTANT_ADDRESS_P(X) \
2501 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2502
2503 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2504
2505 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2506 do { \
2507 if (mips_legitimize_address (&(X), MODE)) \
2508 goto WIN; \
2509 } while (0)
2510
2511
2512 /* A C statement or compound statement with a conditional `goto
2513 LABEL;' executed if memory address X (an RTX) can have different
2514 meanings depending on the machine mode of the memory reference it
2515 is used for.
2516
2517 Autoincrement and autodecrement addresses typically have
2518 mode-dependent effects because the amount of the increment or
2519 decrement is the size of the operand being addressed. Some
2520 machines have other mode-dependent addresses. Many RISC machines
2521 have no mode-dependent addresses.
2522
2523 You may assume that ADDR is a valid address for the machine. */
2524
2525 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2526
2527 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2528 'the start of the function that this code is output in'. */
2529
2530 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2531 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2532 asm_fprintf ((FILE), "%U%s", \
2533 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2534 else \
2535 asm_fprintf ((FILE), "%U%s", (NAME))
2536 \f
2537 /* Specify the machine mode that this machine uses
2538 for the index in the tablejump instruction.
2539 ??? Using HImode in mips16 mode can cause overflow. */
2540 #define CASE_VECTOR_MODE \
2541 (TARGET_MIPS16 ? HImode : ptr_mode)
2542
2543 /* Define as C expression which evaluates to nonzero if the tablejump
2544 instruction expects the table to contain offsets from the address of the
2545 table.
2546 Do not define this if the table should contain absolute addresses. */
2547 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2548
2549 /* Define this as 1 if `char' should by default be signed; else as 0. */
2550 #ifndef DEFAULT_SIGNED_CHAR
2551 #define DEFAULT_SIGNED_CHAR 1
2552 #endif
2553
2554 /* Max number of bytes we can move from memory to memory
2555 in one reasonably fast instruction. */
2556 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2557 #define MAX_MOVE_MAX 8
2558
2559 /* Define this macro as a C expression which is nonzero if
2560 accessing less than a word of memory (i.e. a `char' or a
2561 `short') is no faster than accessing a word of memory, i.e., if
2562 such access require more than one instruction or if there is no
2563 difference in cost between byte and (aligned) word loads.
2564
2565 On RISC machines, it tends to generate better code to define
2566 this as 1, since it avoids making a QI or HI mode register. */
2567 #define SLOW_BYTE_ACCESS 1
2568
2569 /* Define this to be nonzero if shift instructions ignore all but the low-order
2570 few bits. */
2571 #define SHIFT_COUNT_TRUNCATED 1
2572
2573 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2574 is done just by pretending it is already truncated. */
2575 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2576 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2577
2578
2579 /* Specify the machine mode that pointers have.
2580 After generation of rtl, the compiler makes no further distinction
2581 between pointers and any other objects of this machine mode. */
2582
2583 #ifndef Pmode
2584 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2585 #endif
2586
2587 /* Give call MEMs SImode since it is the "most permissive" mode
2588 for both 32-bit and 64-bit targets. */
2589
2590 #define FUNCTION_MODE SImode
2591
2592 \f
2593 /* The cost of loading values from the constant pool. It should be
2594 larger than the cost of any constant we want to synthesize in-line. */
2595
2596 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2597
2598 /* A C expression for the cost of moving data from a register in
2599 class FROM to one in class TO. The classes are expressed using
2600 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2601 the default; other values are interpreted relative to that.
2602
2603 It is not required that the cost always equal 2 when FROM is the
2604 same as TO; on some machines it is expensive to move between
2605 registers if they are not general registers.
2606
2607 If reload sees an insn consisting of a single `set' between two
2608 hard registers, and if `REGISTER_MOVE_COST' applied to their
2609 classes returns a value of 2, reload does not check to ensure
2610 that the constraints of the insn are met. Setting a cost of
2611 other than 2 will allow reload to verify that the constraints are
2612 met. You should do this if the `movM' pattern's constraints do
2613 not allow such copying. */
2614
2615 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2616 mips_register_move_cost (MODE, FROM, TO)
2617
2618 /* ??? Fix this to be right for the R8000. */
2619 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2620 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2621 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2622
2623 /* Define if copies to/from condition code registers should be avoided.
2624
2625 This is needed for the MIPS because reload_outcc is not complete;
2626 it needs to handle cases where the source is a general or another
2627 condition code register. */
2628 #define AVOID_CCMODE_COPIES
2629
2630 /* A C expression for the cost of a branch instruction. A value of
2631 1 is the default; other values are interpreted relative to that. */
2632
2633 /* ??? Fix this to be right for the R8000. */
2634 #define BRANCH_COST \
2635 ((! TARGET_MIPS16 \
2636 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2637 ? 2 : 1)
2638
2639 /* If defined, modifies the length assigned to instruction INSN as a
2640 function of the context in which it is used. LENGTH is an lvalue
2641 that contains the initially computed length of the insn and should
2642 be updated with the correct length of the insn. */
2643 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2644 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2645 \f
2646 /* Control the assembler format that we output. */
2647
2648 /* Output to assembler file text saying following lines
2649 may contain character constants, extra white space, comments, etc. */
2650
2651 #ifndef ASM_APP_ON
2652 #define ASM_APP_ON " #APP\n"
2653 #endif
2654
2655 /* Output to assembler file text saying following lines
2656 no longer contain unusual constructs. */
2657
2658 #ifndef ASM_APP_OFF
2659 #define ASM_APP_OFF " #NO_APP\n"
2660 #endif
2661
2662 #define REGISTER_NAMES \
2663 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2664 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2665 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2666 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2667 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2668 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2669 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2670 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2671 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2672 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2673 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2674 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2675 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2676 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2677 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2678 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2679 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2680 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2681 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2682 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2683 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2684 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
2685
2686 /* List the "software" names for each register. Also list the numerical
2687 names for $fp and $sp. */
2688
2689 #define ADDITIONAL_REGISTER_NAMES \
2690 { \
2691 { "$29", 29 + GP_REG_FIRST }, \
2692 { "$30", 30 + GP_REG_FIRST }, \
2693 { "at", 1 + GP_REG_FIRST }, \
2694 { "v0", 2 + GP_REG_FIRST }, \
2695 { "v1", 3 + GP_REG_FIRST }, \
2696 { "a0", 4 + GP_REG_FIRST }, \
2697 { "a1", 5 + GP_REG_FIRST }, \
2698 { "a2", 6 + GP_REG_FIRST }, \
2699 { "a3", 7 + GP_REG_FIRST }, \
2700 { "t0", 8 + GP_REG_FIRST }, \
2701 { "t1", 9 + GP_REG_FIRST }, \
2702 { "t2", 10 + GP_REG_FIRST }, \
2703 { "t3", 11 + GP_REG_FIRST }, \
2704 { "t4", 12 + GP_REG_FIRST }, \
2705 { "t5", 13 + GP_REG_FIRST }, \
2706 { "t6", 14 + GP_REG_FIRST }, \
2707 { "t7", 15 + GP_REG_FIRST }, \
2708 { "s0", 16 + GP_REG_FIRST }, \
2709 { "s1", 17 + GP_REG_FIRST }, \
2710 { "s2", 18 + GP_REG_FIRST }, \
2711 { "s3", 19 + GP_REG_FIRST }, \
2712 { "s4", 20 + GP_REG_FIRST }, \
2713 { "s5", 21 + GP_REG_FIRST }, \
2714 { "s6", 22 + GP_REG_FIRST }, \
2715 { "s7", 23 + GP_REG_FIRST }, \
2716 { "t8", 24 + GP_REG_FIRST }, \
2717 { "t9", 25 + GP_REG_FIRST }, \
2718 { "k0", 26 + GP_REG_FIRST }, \
2719 { "k1", 27 + GP_REG_FIRST }, \
2720 { "gp", 28 + GP_REG_FIRST }, \
2721 { "sp", 29 + GP_REG_FIRST }, \
2722 { "fp", 30 + GP_REG_FIRST }, \
2723 { "ra", 31 + GP_REG_FIRST }, \
2724 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2725 }
2726
2727 /* This is meant to be redefined in the host dependent files. It is a
2728 set of alternative names and regnums for mips coprocessors. */
2729
2730 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2731
2732 /* A C compound statement to output to stdio stream STREAM the
2733 assembler syntax for an instruction operand X. X is an RTL
2734 expression.
2735
2736 CODE is a value that can be used to specify one of several ways
2737 of printing the operand. It is used when identical operands
2738 must be printed differently depending on the context. CODE
2739 comes from the `%' specification that was used to request
2740 printing of the operand. If the specification was just `%DIGIT'
2741 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2742 is the ASCII code for LTR.
2743
2744 If X is a register, this macro should print the register's name.
2745 The names can be found in an array `reg_names' whose type is
2746 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2747
2748 When the machine description has a specification `%PUNCT' (a `%'
2749 followed by a punctuation character), this macro is called with
2750 a null pointer for X and the punctuation character for CODE.
2751
2752 See mips.c for the MIPS specific codes. */
2753
2754 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2755
2756 /* A C expression which evaluates to true if CODE is a valid
2757 punctuation character for use in the `PRINT_OPERAND' macro. If
2758 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2759 punctuation characters (except for the standard one, `%') are
2760 used in this way. */
2761
2762 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2763
2764 /* A C compound statement to output to stdio stream STREAM the
2765 assembler syntax for an instruction operand that is a memory
2766 reference whose address is ADDR. ADDR is an RTL expression. */
2767
2768 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2769
2770
2771 /* A C statement, to be executed after all slot-filler instructions
2772 have been output. If necessary, call `dbr_sequence_length' to
2773 determine the number of slots filled in a sequence (zero if not
2774 currently outputting a sequence), to decide how many no-ops to
2775 output, or whatever.
2776
2777 Don't define this macro if it has nothing to do, but it is
2778 helpful in reading assembly output if the extent of the delay
2779 sequence is made explicit (e.g. with white space).
2780
2781 Note that output routines for instructions with delay slots must
2782 be prepared to deal with not being output as part of a sequence
2783 (i.e. when the scheduling pass is not run, or when no slot
2784 fillers could be found.) The variable `final_sequence' is null
2785 when not processing a sequence, otherwise it contains the
2786 `sequence' rtx being output. */
2787
2788 #define DBR_OUTPUT_SEQEND(STREAM) \
2789 do \
2790 { \
2791 if (set_nomacro > 0 && --set_nomacro == 0) \
2792 fputs ("\t.set\tmacro\n", STREAM); \
2793 \
2794 if (set_noreorder > 0 && --set_noreorder == 0) \
2795 fputs ("\t.set\treorder\n", STREAM); \
2796 \
2797 fputs ("\n", STREAM); \
2798 } \
2799 while (0)
2800
2801
2802 /* How to tell the debugger about changes of source files. */
2803 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2804 mips_output_filename (STREAM, NAME)
2805
2806 /* mips-tfile does not understand .stabd directives. */
2807 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2808 dbxout_begin_stabn_sline (LINE); \
2809 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2810 } while (0)
2811
2812 /* Use .loc directives for SDB line numbers. */
2813 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2814 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2815
2816 /* The MIPS implementation uses some labels for its own purpose. The
2817 following lists what labels are created, and are all formed by the
2818 pattern $L[a-z].*. The machine independent portion of GCC creates
2819 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2820
2821 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2822 $Lb[0-9]+ Begin blocks for MIPS debug support
2823 $Lc[0-9]+ Label for use in s<xx> operation.
2824 $Le[0-9]+ End blocks for MIPS debug support */
2825
2826 #undef ASM_DECLARE_OBJECT_NAME
2827 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2828 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2829
2830 /* Globalizing directive for a label. */
2831 #define GLOBAL_ASM_OP "\t.globl\t"
2832
2833 /* This says how to define a global common symbol. */
2834
2835 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2836
2837 /* This says how to define a local common symbol (i.e., not visible to
2838 linker). */
2839
2840 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2841 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2842 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2843 #endif
2844
2845 /* This says how to output an external. It would be possible not to
2846 output anything and let undefined symbol become external. However
2847 the assembler uses length information on externals to allocate in
2848 data/sdata bss/sbss, thereby saving exec time. */
2849
2850 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2851 mips_output_external(STREAM,DECL,NAME)
2852
2853 /* This is how to declare a function name. The actual work of
2854 emitting the label is moved to function_prologue, so that we can
2855 get the line number correctly emitted before the .ent directive,
2856 and after any .file directives. Define as empty so that the function
2857 is not declared before the .ent directive elsewhere. */
2858
2859 #undef ASM_DECLARE_FUNCTION_NAME
2860 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2861
2862 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2863 #define FUNCTION_NAME_ALREADY_DECLARED 0
2864 #endif
2865
2866 /* This is how to store into the string LABEL
2867 the symbol_ref name of an internal numbered label where
2868 PREFIX is the class of label and NUM is the number within the class.
2869 This is suitable for output with `assemble_name'. */
2870
2871 #undef ASM_GENERATE_INTERNAL_LABEL
2872 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2873 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2874
2875 /* This is how to output an element of a case-vector that is absolute. */
2876
2877 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2878 fprintf (STREAM, "\t%s\t%sL%d\n", \
2879 ptr_mode == DImode ? ".dword" : ".word", \
2880 LOCAL_LABEL_PREFIX, \
2881 VALUE)
2882
2883 /* This is how to output an element of a case-vector. We can make the
2884 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2885 is supported. */
2886
2887 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2888 do { \
2889 if (TARGET_MIPS16) \
2890 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2891 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2892 else if (TARGET_GPWORD) \
2893 fprintf (STREAM, "\t%s\t%sL%d\n", \
2894 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2895 LOCAL_LABEL_PREFIX, VALUE); \
2896 else \
2897 fprintf (STREAM, "\t%s\t%sL%d\n", \
2898 ptr_mode == DImode ? ".dword" : ".word", \
2899 LOCAL_LABEL_PREFIX, VALUE); \
2900 } while (0)
2901
2902 /* When generating mips16 code we want to put the jump table in the .text
2903 section. In all other cases, we want to put the jump table in the .rdata
2904 section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
2905 it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
2906 to the .text section if appropriate. */
2907 #undef ASM_OUTPUT_CASE_LABEL
2908 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
2909 do { \
2910 if (TARGET_MIPS16) \
2911 function_section (current_function_decl); \
2912 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2913 } while (0)
2914
2915 /* This is how to output an assembler line
2916 that says to advance the location counter
2917 to a multiple of 2**LOG bytes. */
2918
2919 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2920 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2921
2922 /* This is how to output an assembler line to advance the location
2923 counter by SIZE bytes. */
2924
2925 #undef ASM_OUTPUT_SKIP
2926 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2927 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2928
2929 /* This is how to output a string. */
2930 #undef ASM_OUTPUT_ASCII
2931 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2932 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2933
2934 /* Output #ident as a in the read-only data section. */
2935 #undef ASM_OUTPUT_IDENT
2936 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2937 { \
2938 const char *p = STRING; \
2939 int size = strlen (p) + 1; \
2940 readonly_data_section (); \
2941 assemble_string (p, size); \
2942 }
2943 \f
2944 /* Default to -G 8 */
2945 #ifndef MIPS_DEFAULT_GVALUE
2946 #define MIPS_DEFAULT_GVALUE 8
2947 #endif
2948
2949 /* Define the strings to put out for each section in the object file. */
2950 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2951 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2952 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
2953
2954 #undef READONLY_DATA_SECTION_ASM_OP
2955 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2956 \f
2957 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2958 do \
2959 { \
2960 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2961 TARGET_64BIT ? "dsubu" : "subu", \
2962 reg_names[STACK_POINTER_REGNUM], \
2963 reg_names[STACK_POINTER_REGNUM], \
2964 TARGET_64BIT ? "sd" : "sw", \
2965 reg_names[REGNO], \
2966 reg_names[STACK_POINTER_REGNUM]); \
2967 } \
2968 while (0)
2969
2970 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2971 do \
2972 { \
2973 if (! set_noreorder) \
2974 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2975 \
2976 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2977 TARGET_64BIT ? "ld" : "lw", \
2978 reg_names[REGNO], \
2979 reg_names[STACK_POINTER_REGNUM], \
2980 TARGET_64BIT ? "daddu" : "addu", \
2981 reg_names[STACK_POINTER_REGNUM], \
2982 reg_names[STACK_POINTER_REGNUM]); \
2983 \
2984 if (! set_noreorder) \
2985 fprintf (STREAM, "\t.set\treorder\n"); \
2986 } \
2987 while (0)
2988
2989 /* How to start an assembler comment.
2990 The leading space is important (the mips native assembler requires it). */
2991 #ifndef ASM_COMMENT_START
2992 #define ASM_COMMENT_START " #"
2993 #endif
2994 \f
2995 /* Default definitions for size_t and ptrdiff_t. We must override the
2996 definitions from ../svr4.h on mips-*-linux-gnu. */
2997
2998 #undef SIZE_TYPE
2999 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3000
3001 #undef PTRDIFF_TYPE
3002 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3003
3004 /* See mips_expand_prologue's use of loadgp for when this should be
3005 true. */
3006
3007 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
3008 \f
3009 #ifndef __mips16
3010 /* Since the bits of the _init and _fini function is spread across
3011 many object files, each potentially with its own GP, we must assume
3012 we need to load our GP. We don't preserve $gp or $ra, since each
3013 init/fini chunk is supposed to initialize $gp, and crti/crtn
3014 already take care of preserving $ra and, when appropriate, $gp. */
3015 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3016 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3017 asm (SECTION_OP "\n\
3018 .set noreorder\n\
3019 bal 1f\n\
3020 nop\n\
3021 1: .cpload $31\n\
3022 .set reorder\n\
3023 jal " USER_LABEL_PREFIX #FUNC "\n\
3024 " TEXT_SECTION_ASM_OP);
3025 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3026 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3027 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3028 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3029 asm (SECTION_OP "\n\
3030 .set noreorder\n\
3031 bal 1f\n\
3032 nop\n\
3033 1: .set reorder\n\
3034 .cpsetup $31, $2, 1b\n\
3035 jal " USER_LABEL_PREFIX #FUNC "\n\
3036 " TEXT_SECTION_ASM_OP);
3037 #endif
3038 #endif
3039
3040 #ifndef HAVE_AS_TLS
3041 #define HAVE_AS_TLS 0
3042 #endif
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