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1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
5 at Cygnus Support.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
12 any later version.
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 /* Note that some other tm.h files include this one and then override
26 whatever definitions are necessary. */
28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()
30 /* Specify this in a cover file to provide bi-architecture (32/64) support. */
31 /* #define SPARC_BI_ARCH */
33 /* Macro used later in this file to determine default architecture. */
34 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0)
36 /* TARGET_ARCH{32,64} are the main macros to decide which of the two
37 architectures to compile for. We allow targets to choose compile time or
38 runtime selection. */
39 #ifdef IN_LIBGCC2
40 #if defined(__sparcv9) || defined(__arch64__)
41 #define TARGET_ARCH32 0
42 #else
43 #define TARGET_ARCH32 1
45 #else
46 #ifdef SPARC_BI_ARCH
47 #define TARGET_ARCH32 (!TARGET_64BIT)
48 #else
49 #define TARGET_ARCH32 (DEFAULT_ARCH32_P)
52 #define TARGET_ARCH64 (!TARGET_ARCH32)
54 /* Code model selection in 64-bit environment.
56 The machine mode used for addresses is 32-bit wide:
58 TARGET_CM_32: 32-bit address space.
59 It is the code model used when generating 32-bit code.
61 The machine mode used for addresses is 64-bit wide:
63 TARGET_CM_MEDLOW: 32-bit address space.
64 The executable must be in the low 32 bits of memory.
65 This avoids generating %uhi and %ulo terms. Programs
66 can be statically or dynamically linked.
68 TARGET_CM_MEDMID: 44-bit address space.
69 The executable must be in the low 44 bits of memory,
70 and the %[hml]44 terms are used. The text and data
71 segments have a maximum size of 2GB (31-bit span).
72 The maximum offset from any instruction to the label
73 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
75 TARGET_CM_MEDANY: 64-bit address space.
76 The text and data segments have a maximum size of 2GB
77 (31-bit span) and may be located anywhere in memory.
78 The maximum offset from any instruction to the label
79 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span).
81 TARGET_CM_EMBMEDANY: 64-bit address space.
82 The text and data segments have a maximum size of 2GB
83 (31-bit span) and may be located anywhere in memory.
84 The global register %g4 contains the start address of
85 the data segment. Programs are statically linked and
86 PIC is not supported.
88 Different code models are not supported in 32-bit environment. */
91 CM_32,
92 CM_MEDLOW,
93 CM_MEDMID,
94 CM_MEDANY,
95 CM_EMBMEDANY
96 };
98 /* One of CM_FOO. */
101 /* V9 code model selection. */
102 #define TARGET_CM_MEDLOW (sparc_cmodel == CM_MEDLOW)
103 #define TARGET_CM_MEDMID (sparc_cmodel == CM_MEDMID)
104 #define TARGET_CM_MEDANY (sparc_cmodel == CM_MEDANY)
105 #define TARGET_CM_EMBMEDANY (sparc_cmodel == CM_EMBMEDANY)
107 #define SPARC_DEFAULT_CMODEL CM_32
109 /* Do not use the .note.GNU-stack convention by default. */
110 #define NEED_INDICATE_EXEC_STACK 0
112 /* This is call-clobbered in the normal ABI, but is reserved in the
113 home grown (aka upward compatible) embedded ABI. */
115 \f
116 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile,
117 and specified by the user via --with-cpu=foo.
118 This specifies the cpu implementation, not the architecture size. */
119 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit
120 capable cpu's. */
121 #define TARGET_CPU_sparc 0
125 #define TARGET_CPU_supersparc 2
126 #define TARGET_CPU_hypersparc 3
127 #define TARGET_CPU_leon 4
128 #define TARGET_CPU_leon3 5
129 #define TARGET_CPU_leon3v7 6
130 #define TARGET_CPU_sparclite 7
133 #define TARGET_CPU_sparclite86x 8
134 #define TARGET_CPU_sparclet 9
139 #define TARGET_CPU_ultrasparc 11
140 #define TARGET_CPU_ultrasparc3 12
141 #define TARGET_CPU_niagara 13
142 #define TARGET_CPU_niagara2 14
143 #define TARGET_CPU_niagara3 15
144 #define TARGET_CPU_niagara4 16
145 #define TARGET_CPU_niagara7 19
147 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
148 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
149 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
150 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \
151 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \
152 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \
153 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \
154 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7
159 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
160 /* ??? What does Sun's CC pass? */
162 /* ??? It's not clear how other assemblers will handle this, so by default
163 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case
164 is handled in sol2.h. */
166 #endif
167 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
170 #endif
171 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
174 #endif
175 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
178 #endif
179 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2
182 #endif
183 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3
186 #endif
187 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4
189 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG
190 #endif
191 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7
193 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG
194 #endif
196 #else
201 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \
202 || TARGET_CPU_DEFAULT == TARGET_CPU_v8
205 #endif
207 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet
210 #endif
212 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite
215 #endif
217 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x
220 #endif
222 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc
225 #endif
227 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc
230 #endif
232 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \
233 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3
235 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG
236 #endif
238 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7
240 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG
241 #endif
243 #endif
245 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC)
246 #error Unrecognized value in TARGET_CPU_DEFAULT.
247 #endif
249 #ifdef SPARC_BI_ARCH
251 #define CPP_CPU_DEFAULT_SPEC \
259 #define ASM_CPU_DEFAULT_SPEC \
270 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC)
271 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC)
275 /* Define macros to distinguish architectures. */
277 /* Common CPP definitions used by CPP_SPEC amongst the various targets
278 for handling -mcpu=xxx switches. */
280 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \
281 %{mcpu=sparclite:-D__sparclite__} \
282 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \
283 %{mcpu=sparclite86x:-D__sparclite86x__} \
284 %{mcpu=v8:-D__sparc_v8__} \
285 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \
286 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \
287 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \
288 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \
289 %{mcpu=leon3v7:-D__leon__} \
290 %{mcpu=v9:-D__sparc_v9__} \
291 %{mcpu=ultrasparc:-D__sparc_v9__} \
292 %{mcpu=ultrasparc3:-D__sparc_v9__} \
293 %{mcpu=niagara:-D__sparc_v9__} \
294 %{mcpu=niagara2:-D__sparc_v9__} \
295 %{mcpu=niagara3:-D__sparc_v9__} \
296 %{mcpu=niagara4:-D__sparc_v9__} \
297 %{mcpu=niagara7:-D__sparc_v9__} \
298 %{!mcpu*:%(cpp_cpu_default)} \
299 "
303 #define CPP_ARCH_DEFAULT_SPEC \
304 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC)
307 %{m32:%(cpp_arch32)} \
308 %{m64:%(cpp_arch64)} \
309 %{!m32:%{!m64:%(cpp_arch_default)}} \
310 "
312 /* Macros to distinguish the endianness, window model and FP support. */
314 %{mflat:-D_FLAT} \
315 %{msoft-float:-D_SOFT_FLOAT} \
316 "
318 /* Macros to distinguish the particular subtarget. */
321 #define CPP_SPEC \
322 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)"
324 /* This used to translate -dalign to -malign, but that is no good
325 because it can't turn off the usual meaning of making debugging dumps. */
329 /* Override in target specific files. */
331 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \
332 %{mcpu=sparclite:-Asparclite} \
333 %{mcpu=sparclite86x:-Asparclite} \
334 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \
335 %{mcpu=v8:-Av8} \
336 %{mcpu=supersparc:-Av8} \
337 %{mcpu=hypersparc:-Av8} \
341 %{mv8plus:-Av8plus} \
342 %{mcpu=v9:-Av9} \
343 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
344 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
345 %{mcpu=niagara:%{!mv8plus:-Av9b}} \
346 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \
350 %{!mcpu*:%(asm_cpu_default)} \
351 "
353 /* Word size selection, among other things.
354 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */
357 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
359 #else
361 #endif
362 #define ASM_ARCH_DEFAULT_SPEC \
363 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC)
366 %{m32:%(asm_arch32)} \
367 %{m64:%(asm_arch64)} \
368 %{!m32:%{!m64:%(asm_arch_default)}} \
369 "
371 #ifdef HAVE_AS_RELAX_OPTION
373 #else
375 #endif
377 /* Special flags to the Sun-4 assembler when using pipe for input. */
381 %(asm_cpu) %(asm_relax)"
383 /* This macro defines names of additional specifications to put in the specs
384 that can be used in various specifications like CC1_SPEC. Its definition
385 is an initializer with a subgrouping for each command option.
387 Each subgrouping contains a string constant, that defines the
388 specification name, and a string constant that used by the GCC driver
389 program.
391 Do not define this macro if it does not need to do anything. */
393 #define EXTRA_SPECS \
409 SUBTARGET_EXTRA_SPECS
411 #define SUBTARGET_EXTRA_SPECS
413 /* Because libgcc can generate references back to libc (via .umul etc.) we have
414 to list libc again after the second libgcc. */
417 \f
421 /* ??? This should be 32 bits for v9 but what can we do? */
423 #define WCHAR_TYPE_SIZE 16
424 \f
425 /* Mask of all CPU selection flags. */
426 #define MASK_ISA \
427 (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \
428 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS)
430 /* Mask of all CPU feature flags. */
431 #define MASK_FEATURES \
432 (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \
433 + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_POPC + MASK_SUBXC)
435 /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */
436 #define TARGET_HARD_MUL \
437 (TARGET_SPARCLITE || TARGET_SPARCLET \
438 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS)
440 /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y
441 to get high 32 bits. False in 64-bit or V8+ because multiply stores
442 a 64-bit result in a register. */
443 #define TARGET_HARD_MUL32 \
444 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS)
446 /* MASK_APP_REGS must always be the default because that's what
447 FIXED_REGISTERS is set to and -ffixed- is processed before
448 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process
449 -mno-app-regs). */
450 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU)
452 /* Recast the cpu class to be the cpu attribute.
453 Every file includes us, but not every file includes insn-attr.h. */
454 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)
456 /* Support for a compile-time default CPU, et cetera. The rules are:
457 --with-cpu is ignored if -mcpu is specified.
458 --with-tune is ignored if -mtune is specified.
459 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu
460 are specified. */
461 #define OPTION_DEFAULT_SPECS \
465 \f
466 /* target machine storage layout */
468 /* Define this if most significant bit is lowest numbered
469 in instructions that operate on numbered bit-fields. */
470 #define BITS_BIG_ENDIAN 1
472 /* Define this if most significant byte of a word is the lowest numbered. */
473 #define BYTES_BIG_ENDIAN 1
475 /* Define this if most significant word of a multiword number is the lowest
476 numbered. */
477 #define WORDS_BIG_ENDIAN 1
479 #define MAX_BITS_PER_WORD 64
481 /* Width of a word, in units (bytes). */
482 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)
483 #ifdef IN_LIBGCC2
484 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
485 #else
486 #define MIN_UNITS_PER_WORD 4
487 #endif
489 /* Now define the sizes of the C data types. */
490 #define SHORT_TYPE_SIZE 16
491 #define INT_TYPE_SIZE 32
492 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)
493 #define LONG_LONG_TYPE_SIZE 64
494 #define FLOAT_TYPE_SIZE 32
495 #define DOUBLE_TYPE_SIZE 64
497 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the
498 SPARC ABI says that it is 128-bit wide. */
499 /* #define LONG_DOUBLE_TYPE_SIZE 128 */
501 /* The widest floating-point format really supported by the hardware. */
502 #define WIDEST_HARDWARE_FP_SIZE 64
504 /* Width in bits of a pointer. This is the size of ptr_mode. */
505 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
507 /* This is the machine mode used for addresses. */
508 #define Pmode (TARGET_ARCH64 ? DImode : SImode)
510 /* If we have to extend pointers (only when TARGET_ARCH64 and not
511 TARGET_PTR64), we want to do it unsigned. This macro does nothing
512 if ptr_mode and Pmode are the same. */
513 #define POINTERS_EXTEND_UNSIGNED 1
515 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
516 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
518 /* Boundary (in *bits*) on which stack pointer should be aligned. */
519 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because
520 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */
521 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)
523 /* Temporary hack until the FIXME above is fixed. */
524 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS)
526 /* ALIGN FRAMES on double word boundaries */
527 #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2)
529 /* Allocation boundary (in *bits*) for the code of a function. */
530 #define FUNCTION_BOUNDARY 32
532 /* Alignment of field after `int : 0' in a structure. */
533 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32)
535 /* Every structure's size must be a multiple of this. */
536 #define STRUCTURE_SIZE_BOUNDARY 8
538 /* A bit-field declared as `int' forces `int' alignment for the struct. */
539 #define PCC_BITFIELD_TYPE_MATTERS 1
541 /* No data type wants to be aligned rounder than this. */
542 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64)
544 /* The best alignment to use in cases where we have a choice. */
545 #define FASTEST_ALIGNMENT 64
547 /* Define this macro as an expression for the alignment of a structure
548 (given by STRUCT as a tree node) if the alignment computed in the
549 usual way is COMPUTED and the alignment explicitly specified was
550 SPECIFIED.
552 The default is to use SPECIFIED if it is larger; otherwise, use
553 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */
554 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \
555 (TARGET_FASTER_STRUCTS ? \
556 ((TREE_CODE (STRUCT) == RECORD_TYPE \
557 || TREE_CODE (STRUCT) == UNION_TYPE \
558 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \
559 && TYPE_FIELDS (STRUCT) != 0 \
560 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \
561 : MAX ((COMPUTED), (SPECIFIED))) \
562 : MAX ((COMPUTED), (SPECIFIED)))
564 /* An integer expression for the size in bits of the largest integer machine
565 mode that should actually be used. We allow pairs of registers. */
566 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode)
568 /* We need 2 words, so we can save the stack pointer and the return register
569 of the function containing a non-local goto target. */
570 #define STACK_SAVEAREA_MODE(LEVEL) \
571 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode)
573 /* Make strings word-aligned so strcpy from constants will be faster. */
574 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
575 ((TREE_CODE (EXP) == STRING_CST \
576 && (ALIGN) < FASTEST_ALIGNMENT) \
577 ? FASTEST_ALIGNMENT : (ALIGN))
579 /* Make arrays of chars word-aligned for the same reasons. */
580 #define DATA_ALIGNMENT(TYPE, ALIGN) \
581 (TREE_CODE (TYPE) == ARRAY_TYPE \
582 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
583 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
585 /* Make local arrays of chars word-aligned for the same reasons. */
586 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN)
588 /* Set this nonzero if move instructions will actually fail to work
589 when given unaligned data. */
590 #define STRICT_ALIGNMENT 1
592 /* Things that must be doubleword aligned cannot go in the text section,
593 because the linker fails to align the text section enough!
594 Put them in the data section. This macro is only used in this file. */
595 #define MAX_TEXT_ALIGN 32
596 \f
597 /* Standard register usage. */
599 /* Number of actual hardware registers.
600 The hardware registers are assigned numbers for the compiler
601 from 0 to just below FIRST_PSEUDO_REGISTER.
602 All registers that the compiler knows about must be given numbers,
603 even those that are not normally considered general registers.
605 SPARC has 32 integer registers and 32 floating point registers.
606 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not
607 accessible. We still account for them to simplify register computations
608 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
609 32+32+32+4 == 100.
610 Register 100 is used as the integer condition code register.
611 Register 101 is used as the soft frame pointer register.
612 Register 102 is used as the general status register by VIS instructions. */
614 #define FIRST_PSEUDO_REGISTER 103
616 #define SPARC_FIRST_INT_REG 0
617 #define SPARC_LAST_INT_REG 31
618 #define SPARC_FIRST_FP_REG 32
619 /* Additional V9 fp regs. */
620 #define SPARC_FIRST_V9_FP_REG 64
621 #define SPARC_LAST_V9_FP_REG 95
622 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */
623 #define SPARC_FIRST_V9_FCC_REG 96
624 #define SPARC_LAST_V9_FCC_REG 99
625 /* V8 fcc reg. */
626 #define SPARC_FCC_REG 96
627 /* Integer CC reg. We don't distinguish %icc from %xcc. */
628 #define SPARC_ICC_REG 100
629 #define SPARC_GSR_REG 102
631 /* Nonzero if REGNO is an fp reg. */
632 #define SPARC_FP_REG_P(REGNO) \
633 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG)
635 /* Nonzero if REGNO is an int reg. */
636 #define SPARC_INT_REG_P(REGNO) \
637 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG)
639 /* Argument passing regs. */
640 #define SPARC_OUTGOING_INT_ARG_FIRST 8
641 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24)
642 #define SPARC_FP_ARG_FIRST 32
644 /* 1 for registers that have pervasive standard uses
645 and are not available for the register allocator.
647 On non-v9 systems:
648 g1 is free to use as temporary.
649 g2-g4 are reserved for applications. Gcc normally uses them as
650 temporaries, but this can be disabled via the -mno-app-regs option.
651 g5 through g7 are reserved for the operating system.
653 On v9 systems:
654 g1,g5 are free to use as temporaries, and are free to use between calls
655 if the call is to an external function via the PLT.
656 g4 is free to use as a temporary in the non-embedded case.
657 g4 is reserved in the embedded case.
658 g2-g3 are reserved for applications. Gcc normally uses them as
659 temporaries, but this can be disabled via the -mno-app-regs option.
660 g6-g7 are reserved for the operating system (or application in
661 embedded case).
662 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
663 currently be a fixed register until this pattern is rewritten.
664 Register 1 is also used when restoring call-preserved registers in large
665 stack frames.
667 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in
668 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-.
669 */
671 #define FIXED_REGISTERS \
672 {1, 0, 2, 2, 2, 2, 1, 1, \
673 0, 0, 0, 0, 0, 0, 1, 0, \
674 0, 0, 0, 0, 0, 0, 0, 0, \
675 0, 0, 0, 0, 0, 0, 0, 1, \
676 \
677 0, 0, 0, 0, 0, 0, 0, 0, \
678 0, 0, 0, 0, 0, 0, 0, 0, \
679 0, 0, 0, 0, 0, 0, 0, 0, \
680 0, 0, 0, 0, 0, 0, 0, 0, \
681 \
682 0, 0, 0, 0, 0, 0, 0, 0, \
683 0, 0, 0, 0, 0, 0, 0, 0, \
684 0, 0, 0, 0, 0, 0, 0, 0, \
685 0, 0, 0, 0, 0, 0, 0, 0, \
686 \
687 0, 0, 0, 0, 1, 1, 1}
689 /* 1 for registers not available across function calls.
690 These must include the FIXED_REGISTERS and also any
691 registers that can be used without being saved.
692 The latter must include the registers where values are returned
693 and the register where structure-value addresses are passed.
694 Aside from that, you can include as many other registers as you like. */
696 #define CALL_USED_REGISTERS \
697 {1, 1, 1, 1, 1, 1, 1, 1, \
698 1, 1, 1, 1, 1, 1, 1, 1, \
699 0, 0, 0, 0, 0, 0, 0, 0, \
700 0, 0, 0, 0, 0, 0, 0, 1, \
701 \
702 1, 1, 1, 1, 1, 1, 1, 1, \
703 1, 1, 1, 1, 1, 1, 1, 1, \
704 1, 1, 1, 1, 1, 1, 1, 1, \
705 1, 1, 1, 1, 1, 1, 1, 1, \
706 \
707 1, 1, 1, 1, 1, 1, 1, 1, \
708 1, 1, 1, 1, 1, 1, 1, 1, \
709 1, 1, 1, 1, 1, 1, 1, 1, \
710 1, 1, 1, 1, 1, 1, 1, 1, \
711 \
712 1, 1, 1, 1, 1, 1, 1}
714 /* 1 for registers not available across function calls.
715 Unlike the above, this need not include the FIXED_REGISTERS, but any
716 registers that can be used without being saved.
717 The latter must include the registers where values are returned
718 and the register where structure-value addresses are passed.
719 Aside from that, you can include as many other registers as you like. */
721 #define CALL_REALLY_USED_REGISTERS \
722 {1, 1, 1, 1, 1, 1, 1, 1, \
723 1, 1, 1, 1, 1, 1, 1, 1, \
724 0, 0, 0, 0, 0, 0, 0, 0, \
725 0, 0, 0, 0, 0, 0, 0, 0, \
726 \
727 1, 1, 1, 1, 1, 1, 1, 1, \
728 1, 1, 1, 1, 1, 1, 1, 1, \
729 1, 1, 1, 1, 1, 1, 1, 1, \
730 1, 1, 1, 1, 1, 1, 1, 1, \
731 \
732 1, 1, 1, 1, 1, 1, 1, 1, \
733 1, 1, 1, 1, 1, 1, 1, 1, \
734 1, 1, 1, 1, 1, 1, 1, 1, \
735 1, 1, 1, 1, 1, 1, 1, 1, \
736 \
737 1, 1, 1, 1, 1, 1, 1}
739 /* Return number of consecutive hard regs needed starting at reg REGNO
740 to hold something of mode MODE.
741 This is ordinarily the length in words of a value of mode MODE
742 but can be less for certain modes in special long registers.
744 On SPARC, ordinary registers hold 32 bits worth;
745 this means both integer and floating point registers.
746 On v9, integer regs hold 64 bits worth; floating point regs hold
747 32 bits worth (this includes the new fp regs as even the odd ones are
748 included in the hard register count). */
750 #define HARD_REGNO_NREGS(REGNO, MODE) \
751 ((REGNO) == SPARC_GSR_REG ? 1 : \
752 (TARGET_ARCH64 \
753 ? (SPARC_INT_REG_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM \
754 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
755 : (GET_MODE_SIZE (MODE) + 3) / 4) \
756 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
758 /* Due to the ARCH64 discrepancy above we must override this next
759 macro too. */
760 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE)
762 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
763 See sparc.c for how we initialize this. */
767 /* ??? Because of the funny way we pass parameters we should allow certain
768 ??? types of float/complex values to be in integer registers during
769 ??? RTL generation. This only matters on arch32. */
770 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
771 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
773 /* Value is 1 if it is OK to rename a hard register FROM to another hard
774 register TO. We cannot rename %g1 as it may be used before the save
775 register window instruction in the prologue. */
776 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1)
778 #define MODES_TIEABLE_P(MODE1, MODE2) sparc_modes_tieable_p (MODE1, MODE2)
780 /* Specify the registers used for certain standard purposes.
781 The values of these macros are register numbers. */
783 /* Register to use for pushing function arguments. */
784 #define STACK_POINTER_REGNUM 14
786 /* The stack bias (amount by which the hardware register is offset by). */
787 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0)
789 /* Actual top-of-stack address is 92/176 greater than the contents of the
790 stack pointer register for !v9/v9. That is:
791 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
792 address, and 6*4 bytes for the 6 register parameters.
793 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer
794 parameter regs. */
795 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS)
797 /* Base register for access to local variables of the function. */
798 #define HARD_FRAME_POINTER_REGNUM 30
800 /* The soft frame pointer does not have the stack bias applied. */
801 #define FRAME_POINTER_REGNUM 101
803 /* Given the stack bias, the stack pointer isn't actually aligned. */
804 #define INIT_EXPANDERS \
805 do { \
806 if (crtl->emit.regno_pointer_align && SPARC_STACK_BIAS) \
807 { \
808 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) = BITS_PER_UNIT; \
809 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; \
810 } \
811 } while (0)
813 /* Base register for access to arguments of the function. */
814 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
816 /* Register in which static-chain is passed to a function. This must
817 not be a register used by the prologue. */
818 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2)
820 /* Register which holds the global offset table, if any. */
822 #define GLOBAL_OFFSET_TABLE_REGNUM 23
824 /* Register which holds offset table for position-independent
825 data references. */
827 #define PIC_OFFSET_TABLE_REGNUM \
828 (flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
830 /* Pick a default value we can notice from override_options:
831 !v9: Default is on.
832 v9: Default is off.
833 Originally it was -1, but later on the container of options changed to
834 unsigned byte, so we decided to pick 127 as default value, which does
835 reflect an undefined default value in case of 0/1. */
837 #define DEFAULT_PCC_STRUCT_RETURN 127
839 /* Functions which return large structures get the address
840 to place the wanted value at offset 64 from the frame.
841 Must reserve 64 bytes for the in and local registers.
842 v9: Functions which return large structures get the address to place the
843 wanted value from an invisible first argument. */
844 #define STRUCT_VALUE_OFFSET 64
845 \f
846 /* Define the classes of registers for register constraints in the
847 machine description. Also define ranges of constants.
849 One of the classes must always be named ALL_REGS and include all hard regs.
850 If there is more than one class, another class must be named NO_REGS
851 and contain no registers.
853 The name GENERAL_REGS must be the name of a class (or an alias for
854 another name such as ALL_REGS). This is the class of registers
855 that is allowed by "g" or "r" in a register constraint.
856 Also, registers outside this class are allocated only when
857 instructions express preferences for them.
859 The classes must be numbered in nondecreasing order; that is,
860 a larger-numbered class must never be contained completely
861 in a smaller-numbered class.
863 For any two classes, it is very desirable that there be another
864 class that represents their union. */
866 /* The SPARC has various kinds of registers: general, floating point,
867 and condition codes [well, it has others as well, but none that we
868 care directly about].
870 For v9 we must distinguish between the upper and lower floating point
871 registers because the upper ones can't hold SFmode values.
872 HARD_REGNO_MODE_OK won't help here because reload assumes that register(s)
873 satisfying a group need for a class will also satisfy a single need for
874 that class. EXTRA_FP_REGS is a bit of a misnomer as it covers all 64 fp
875 regs.
877 It is important that one class contains all the general and all the standard
878 fp regs. Otherwise find_reg() won't properly allocate int regs for moves,
879 because reg_class_record() will bias the selection in favor of fp regs,
880 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS,
881 because FP_REGS > GENERAL_REGS.
883 It is also important that one class contain all the general and all
884 the fp regs. Otherwise when spilling a DFmode reg, it may be from
885 EXTRA_FP_REGS but find_reloads() may use class
886 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die
887 because the compiler thinks it doesn't have a spill reg when in
888 fact it does.
890 v9 also has 4 floating point condition code registers. Since we don't
891 have a class that is the union of FPCC_REGS with either of the others,
892 it is important that it appear first. Otherwise the compiler will die
893 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
894 constraints. */
900 #define N_REG_CLASSES (int) LIM_REG_CLASSES
902 /* Give names of register classes as strings for dump file. */
904 #define REG_CLASS_NAMES \
909 /* Define which registers fit in which classes.
910 This is an initializer for a vector of HARD_REG_SET
911 of length N_REG_CLASSES. */
913 #define REG_CLASS_CONTENTS \
924 /* The same information, inverted:
925 Return the class number of the smallest class containing
926 reg number REGNO. This could be a conditional expression
927 or could index an array. */
931 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)]
933 /* Defines invalid mode changes. Borrowed from the PA port.
935 SImode loads to floating-point registers are not zero-extended.
936 The definition for LOAD_EXTEND_OP specifies that integer loads
937 narrower than BITS_PER_WORD will be zero-extended. As a result,
938 we inhibit changes from SImode unless they are to a mode that is
939 identical in size.
941 Likewise for SFmode, since word-mode paradoxical subregs are
942 problematic on big-endian architectures. */
944 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
945 (TARGET_ARCH64 \
946 && GET_MODE_SIZE (FROM) == 4 \
947 && GET_MODE_SIZE (TO) != 4 \
948 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
950 /* This is the order in which to allocate registers normally.
952 We put %f0-%f7 last among the float registers, so as to make it more
953 likely that a pseudo-register which dies in the float return register
954 area will get allocated to the float return register, thus saving a move
955 instruction at the end of the function.
957 Similarly for integer return value registers.
959 We know in this case that we will not end up with a leaf function.
961 The register allocator is given the global and out registers first
962 because these registers are call clobbered and thus less useful to
963 global register allocation.
965 Next we list the local and in registers. They are not call clobbered
966 and thus very useful for global register allocation. We list the input
967 registers before the locals so that it is more likely the incoming
968 arguments received in those registers can just stay there and not be
969 reloaded. */
971 #define REG_ALLOC_ORDER \
988 /* This is the order in which to allocate registers for
989 leaf functions. If all registers can fit in the global and
990 output registers, then we have the possibility of having a leaf
991 function.
993 The macro actually mentioned the input registers first,
994 because they get renumbered into the output registers once
995 we know really do have a leaf function.
997 To be more precise, this register allocation order is used
998 when %o7 is found to not be clobbered right before register
999 allocation. Normally, the reason %o7 would be clobbered is
1000 due to a call which could not be transformed into a sibling
1001 call.
1003 As a consequence, it is possible to use the leaf register
1004 allocation order and not end up with a leaf function. We will
1005 not get suboptimal register allocation in that case because by
1006 definition of being potentially leaf, there were no function
1007 calls. Therefore, allocation order within the local register
1008 window is not critical like it is when we do have function calls. */
1010 #define REG_LEAF_ALLOC_ORDER \
1027 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
1030 #define LEAF_REGISTERS sparc_leaf_regs
1033 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
1035 /* The class value for index registers, and the one for base regs. */
1036 #define INDEX_REG_CLASS GENERAL_REGS
1037 #define BASE_REG_CLASS GENERAL_REGS
1039 /* Local macro to handle the two v9 classes of FP regs. */
1040 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS)
1042 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */
1043 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20)
1044 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400)
1045 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800)
1046 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000)
1048 /* 10- and 11-bit immediates are only used for a few specific insns.
1049 SMALL_INT is used throughout the port so we continue to use it. */
1050 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
1052 /* Predicate for constants that can be loaded with a sethi instruction.
1053 This is the general, 64-bit aware, bitwise version that ensures that
1054 only constants whose representation fits in the mask
1056 0x00000000fffffc00
1058 are accepted. It will reject, for example, negative SImode constants
1059 on 64-bit hosts, so correct handling is to mask the value beforehand
1060 according to the mode of the instruction. */
1061 #define SPARC_SETHI_P(X) \
1062 (((unsigned HOST_WIDE_INT) (X) \
1063 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0)
1065 /* Version of the above predicate for SImode constants and below. */
1066 #define SPARC_SETHI32_P(X) \
1067 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode)))
1069 /* On SPARC when not VIS3 it is not possible to directly move data
1070 between GENERAL_REGS and FP_REGS. */
1071 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
1072 ((FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) \
1073 && (! TARGET_VIS3 \
1074 || GET_MODE_SIZE (MODE) > 8 \
1075 || GET_MODE_SIZE (MODE) < 4))
1077 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on v9
1078 because the movsi and movsf patterns don't handle r/f moves.
1079 For v8 we copy the default definition. */
1080 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1081 (TARGET_ARCH64 \
1082 ? (GET_MODE_BITSIZE (MODE) < 32 \
1083 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \
1084 : MODE) \
1085 : (GET_MODE_BITSIZE (MODE) < BITS_PER_WORD \
1086 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (MODE), 0) \
1087 : MODE))
1089 /* Return the maximum number of consecutive registers
1090 needed to represent mode MODE in a register of class CLASS. */
1091 /* On SPARC, this is the size of MODE in words. */
1092 #define CLASS_MAX_NREGS(CLASS, MODE) \
1093 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1094 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1095 \f
1096 /* Stack layout; function entry, exit and calling. */
1098 /* Define this if pushing a word on the stack
1099 makes the stack pointer a smaller address. */
1100 #define STACK_GROWS_DOWNWARD 1
1102 /* Define this to nonzero if the nominal address of the stack frame
1103 is at the high-address end of the local variables;
1104 that is, each additional local variable allocated
1105 goes at a more negative offset in the frame. */
1106 #define FRAME_GROWS_DOWNWARD 1
1108 /* Offset within stack frame to start allocating local variables at.
1109 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1110 first local allocated. Otherwise, it is the offset to the BEGINNING
1111 of the first local allocated. */
1112 #define STARTING_FRAME_OFFSET 0
1114 /* Offset of first parameter from the argument pointer register value.
1115 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1116 even if this function isn't going to use it.
1117 v9: This is 128 for the ins and locals. */
1118 #define FIRST_PARM_OFFSET(FNDECL) \
1119 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
1121 /* Offset from the argument pointer register value to the CFA.
1122 This is different from FIRST_PARM_OFFSET because the register window
1123 comes between the CFA and the arguments. */
1124 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1126 /* When a parameter is passed in a register, stack space is still
1127 allocated for it.
1128 !v9: All 6 possible integer registers have backing store allocated.
1129 v9: Only space for the arguments passed is allocated. */
1130 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special
1131 meaning to the backend. Further, we need to be able to detect if a
1132 varargs/unprototyped function is called, as they may want to spill more
1133 registers than we've provided space. Ugly, ugly. So for now we retain
1134 all 6 slots even for v9. */
1135 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD)
1137 /* Definitions for register elimination. */
1139 #define ELIMINABLE_REGS \
1140 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1141 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
1143 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1144 do \
1145 { \
1146 (OFFSET) = sparc_initial_elimination_offset ((TO)); \
1147 } \
1148 while (0)
1150 /* Keep the stack pointer constant throughout the function.
1151 This is both an optimization and a necessity: longjmp
1152 doesn't behave itself when the stack pointer moves within
1153 the function! */
1154 #define ACCUMULATE_OUTGOING_ARGS 1
1156 /* Define this macro if the target machine has "register windows". This
1157 C expression returns the register number as seen by the called function
1158 corresponding to register number OUT as seen by the calling function.
1159 Return OUT if register number OUT is not an outbound register. */
1161 #define INCOMING_REGNO(OUT) \
1162 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1164 /* Define this macro if the target machine has "register windows". This
1165 C expression returns the register number as seen by the calling function
1166 corresponding to register number IN as seen by the called function.
1167 Return IN if register number IN is not an inbound register. */
1169 #define OUTGOING_REGNO(IN) \
1170 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1172 /* Define this macro if the target machine has register windows. This
1173 C expression returns true if the register is call-saved but is in the
1174 register window. */
1176 #define LOCAL_REGNO(REGNO) \
1177 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31)
1179 /* Define the size of space to allocate for the return value of an
1180 untyped_call. */
1182 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16)
1184 /* 1 if N is a possible register number for function argument passing.
1185 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */
1187 #define FUNCTION_ARG_REGNO_P(N) \
1188 (((N) >= 8 && (N) <= 13) \
1189 || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63))
1190 \f
1191 /* Define a data type for recording info about an argument list
1192 during the scan of that argument list. This data type should
1193 hold all necessary information about the function itself
1194 and about the args processed so far, enough to enable macros
1195 such as FUNCTION_ARG to determine where the next arg should go.
1197 On SPARC (!v9), this is a single integer, which is a number of words
1198 of arguments scanned so far (including the invisible argument,
1199 if any, which holds the structure-value-address).
1200 Thus 7 or more means all following args should go on the stack.
1202 For v9, we also need to know whether a prototype is present. */
1208 };
1209 #define CUMULATIVE_ARGS struct sparc_args
1211 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1212 for a call to a function whose data type is FNTYPE.
1213 For a library call, FNTYPE is 0. */
1215 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1216 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL));
1218 /* If defined, a C expression which determines whether, and in which direction,
1219 to pad out an argument with extra space. The value should be of type
1220 `enum direction': either `upward' to pad above the argument,
1221 `downward' to pad below, or `none' to inhibit padding. */
1223 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
1224 function_arg_padding ((MODE), (TYPE))
1226 \f
1227 /* Generate the special assembly code needed to tell the assembler whatever
1228 it might need to know about the return value of a function.
1230 For SPARC assemblers, we need to output a .proc pseudo-op which conveys
1231 information to the assembler relating to peephole optimization (done in
1232 the assembler). */
1234 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1237 /* Output the special assembly code needed to tell the assembler some
1238 register is used as global register variable.
1240 SPARC 64bit psABI declares registers %g2 and %g3 as application
1241 registers and %g6 and %g7 as OS registers. Any object using them
1242 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them
1243 and how they are used (scratch or some global variable).
1244 Linker will then refuse to link together objects which use those
1245 registers incompatibly.
1247 Unless the registers are used for scratch, two different global
1248 registers cannot be declared to the same name, so in the unlikely
1249 case of a global register variable occupying more than one register
1250 we prefix the second and following registers with .gnu.part1. etc. */
1254 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
1255 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \
1256 do { \
1257 if (TARGET_ARCH64) \
1258 { \
1259 int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \
1260 int reg; \
1261 for (reg = (REGNO); reg < 8 && reg < end; reg++) \
1262 if ((reg & ~1) == 2 || (reg & ~1) == 6) \
1263 { \
1264 if (reg == (REGNO)) \
1266 else \
1268 reg, reg - (REGNO), (NAME)); \
1269 sparc_hard_reg_printed[reg] = 1; \
1270 } \
1271 } \
1272 } while (0)
1273 #endif
1275 \f
1276 /* Emit rtl for profiling. */
1277 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL)
1279 /* All the work done in PROFILE_HOOK, but still required. */
1280 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0)
1282 /* Set the name of the mcount function for the system. */
1284 \f
1285 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1286 the stack pointer does not matter. The value is tested only in
1287 functions that have frame pointers. */
1288 #define EXIT_IGNORE_STACK 1
1290 /* Length in units of the trampoline for entering a nested function. */
1291 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16)
1293 /* Alignment required for trampolines, in bits. */
1294 #define TRAMPOLINE_ALIGNMENT 128
1295 \f
1296 /* Generate RTL to flush the register windows so as to make arbitrary frames
1297 available. */
1298 #define SETUP_FRAME_ADDRESSES() \
1299 do { \
1300 if (!TARGET_FLAT) \
1301 emit_insn (gen_flush_register_windows ());\
1302 } while (0)
1304 /* Given an rtx for the address of a frame,
1305 return an rtx for the address of the word in the frame
1306 that holds the dynamic chain--the previous frame's address. */
1307 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1308 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
1310 /* Given an rtx for the frame pointer,
1311 return an rtx for the address of the frame. */
1312 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS)
1314 /* The return address isn't on the stack, it is in a register, so we can't
1315 access it from the current frame pointer. We can access it from the
1316 previous frame pointer though by reading a value from the register window
1317 save area. */
1318 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1
1320 /* This is the offset of the return address to the true next instruction to be
1321 executed for the current function. */
1322 #define RETURN_ADDR_OFFSET \
1323 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct))
1325 /* The current return address is in %i7. The return address of anything
1326 farther back is in the register window save area at [%fp+60]. */
1327 /* ??? This ignores the fact that the actual return address is +8 for normal
1328 returns, and +12 for structure returns. */
1329 #define RETURN_ADDR_REGNUM 31
1330 #define RETURN_ADDR_RTX(count, frame) \
1331 ((count == -1) \
1332 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \
1333 : gen_rtx_MEM (Pmode, \
1334 memory_address (Pmode, plus_constant (Pmode, frame, \
1335 15 * UNITS_PER_WORD \
1336 + SPARC_STACK_BIAS))))
1338 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's
1339 +12, but always using +8 is close enough for frame unwind purposes.
1340 Actually, just using %o7 is close enough for unwinding, but %o7+8
1341 is something you can return to. */
1342 #define INCOMING_RETURN_ADDR_REGNUM 15
1343 #define INCOMING_RETURN_ADDR_RTX \
1344 plus_constant (word_mode, \
1345 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8)
1346 #define DWARF_FRAME_RETURN_COLUMN \
1347 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM)
1349 /* The offset from the incoming value of %sp to the top of the stack frame
1350 for the current function. On sparc64, we have to account for the stack
1351 bias if present. */
1352 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS
1354 /* Describe how we implement __builtin_eh_return. */
1355 #define EH_RETURN_REGNUM 1
1356 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM)
1357 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM)
1359 /* Define registers used by the epilogue and return instruction. */
1360 #define EPILOGUE_USES(REGNO) \
1361 ((REGNO) == RETURN_ADDR_REGNUM \
1362 || (TARGET_FLAT \
1363 && epilogue_completed \
1364 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \
1365 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM))
1367 /* Select a format to encode pointers in exception handling data. CODE
1368 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
1369 true if the symbol may be affected by dynamic relocations.
1371 If assembler and linker properly support .uaword %r_disp32(foo),
1372 then use PC relative 32-bit relocations instead of absolute relocs
1373 for shared libraries. On sparc64, use pc relative 32-bit relocs even
1374 for binaries, to save memory.
1376 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the
1377 symbol %r_disp32() is against was not local, but .hidden. In that
1378 case, we have to use DW_EH_PE_absptr for pic personality. */
1379 #ifdef HAVE_AS_SPARC_UA_PCREL
1380 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN
1381 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1382 (flag_pic \
1383 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\
1384 : ((TARGET_ARCH64 && ! GLOBAL) \
1385 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1386 : DW_EH_PE_absptr))
1387 #else
1388 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
1389 (flag_pic \
1390 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \
1391 : ((TARGET_ARCH64 && ! GLOBAL) \
1392 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
1393 : DW_EH_PE_absptr))
1394 #endif
1396 /* Emit a PC-relative relocation. */
1397 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
1398 do { \
1399 fputs (integer_asm_op (SIZE, FALSE), FILE); \
1401 assemble_name (FILE, LABEL); \
1403 } while (0)
1404 #endif
1405 \f
1406 /* Addressing modes, and classification of registers for them. */
1408 /* Macros to check register numbers against specific register classes. */
1410 /* These assume that REGNO is a hard or pseudo reg number.
1411 They give nonzero only if REGNO is a hard reg of the suitable class
1412 or a pseudo reg currently allocated to a suitable hard reg.
1413 Since they use reg_renumber, they are safe only once reg_renumber
1414 has been allocated, which happens in reginfo.c during register
1415 allocation. */
1417 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1418 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \
1419 || (REGNO) == FRAME_POINTER_REGNUM \
1420 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)
1422 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO)
1424 #define REGNO_OK_FOR_FP_P(REGNO) \
1425 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \
1426 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)))
1428 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1429 (TARGET_V9 \
1430 && (((unsigned) (REGNO) - 96 < (unsigned)4) \
1431 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4)))
1432 \f
1433 /* Maximum number of registers that can appear in a valid memory address. */
1435 #define MAX_REGS_PER_ADDRESS 2
1437 /* Recognize any constant value that is a valid address.
1438 When PIC, we do not accept an address that would require a scratch reg
1439 to load into a register. */
1441 #define CONSTANT_ADDRESS_P(X) constant_address_p (X)
1443 /* Define this, so that when PIC, reload won't try to reload invalid
1444 addresses which require two reload registers. */
1446 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
1447 \f
1448 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */
1450 #ifdef HAVE_AS_OFFSETABLE_LO10
1451 #define USE_AS_OFFSETABLE_LO10 1
1452 #else
1453 #define USE_AS_OFFSETABLE_LO10 0
1454 #endif
1455 \f
1456 /* Try a machine-dependent way of reloading an illegitimate address
1457 operand. If we find one, push the reload and jump to WIN. This
1458 macro is used in only one place: `find_reloads_address' in reload.c. */
1459 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1460 do { \
1461 int win; \
1462 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \
1463 (int)(TYPE), (IND_LEVELS), &win); \
1464 if (win) \
1465 goto WIN; \
1466 } while (0)
1467 \f
1468 /* Specify the machine mode that this machine uses
1469 for the index in the tablejump instruction. */
1470 /* If we ever implement any of the full models (such as CM_FULLANY),
1471 this has to be DImode in that case */
1472 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1473 #define CASE_VECTOR_MODE \
1474 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode)
1475 #else
1476 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise
1477 we have to sign extend which slows things down. */
1478 #define CASE_VECTOR_MODE \
1479 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode)
1480 #endif
1482 /* Define this as 1 if `char' should by default be signed; else as 0. */
1483 #define DEFAULT_SIGNED_CHAR 1
1485 /* Max number of bytes we can move from memory to memory
1486 in one reasonably fast instruction. */
1487 #define MOVE_MAX 8
1489 /* If a memory-to-memory move would take MOVE_RATIO or more simple
1490 move-instruction pairs, we will do a movmem or libcall instead. */
1492 #define MOVE_RATIO(speed) ((speed) ? 8 : 3)
1494 /* Define if operations between registers always perform the operation
1495 on the full register even if a narrower mode is specified. */
1496 #define WORD_REGISTER_OPERATIONS 1
1498 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1499 will either zero-extend or sign-extend. The value of this macro should
1500 be the code that says which one of the two operations is implicitly
1501 done, UNKNOWN if none. */
1502 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1504 /* Nonzero if access to memory by bytes is slow and undesirable.
1505 For RISC chips, it means that access to memory by bytes is no
1506 better than access by words when possible, so grab a whole word
1507 and maybe make use of that. */
1508 #define SLOW_BYTE_ACCESS 1
1510 /* Define this to be nonzero if shift instructions ignore all but the low-order
1511 few bits. */
1512 #define SHIFT_COUNT_TRUNCATED 1
1514 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1515 is done just by pretending it is already truncated. */
1516 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1518 /* For SImode, we make sure the top 32-bits of the register are clear and
1519 then we subtract 32 from the lzd instruction result. */
1520 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1521 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1)
1523 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1524 return the mode to be used for the comparison. For floating-point,
1525 CCFP[E]mode is used. CCNZmode should be used when the first operand
1526 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1527 processing is needed. */
1528 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y))
1530 /* Return nonzero if MODE implies a floating point inequality can be
1531 reversed. For SPARC this is always true because we have a full
1532 compliment of ordered and unordered comparisons, but until generic
1533 code knows how to reverse it correctly we keep the old definition. */
1534 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode)
1536 /* A function address in a call instruction for indexing purposes. */
1537 #define FUNCTION_MODE Pmode
1539 /* Define this if addresses of constant functions
1540 shouldn't be put through pseudo regs where they can be cse'd.
1541 Desirable on machines where ordinary constants are expensive
1542 but a CALL with constant address is cheap. */
1543 #define NO_FUNCTION_CSE 1
1545 /* The _Q_* comparison libcalls return booleans. */
1546 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode)
1548 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such
1549 that the inputs are fully consumed before the output memory is clobbered. */
1551 #define TARGET_BUGGY_QP_LIB 0
1553 /* Assume by default that we do not have the Solaris-specific conversion
1554 routines nor 64-bit integer multiply and divide routines. */
1556 #define SUN_CONVERSION_LIBFUNCS 0
1557 #define DITF_CONVERSION_LIBFUNCS 0
1558 #define SUN_INTEGER_MULTIPLY_64 0
1560 /* Provide the cost of a branch. For pre-v9 processors we use
1561 a value of 3 to take into account the potential annulling of
1562 the delay slot (which ends up being a bubble in the pipeline slot)
1563 plus a cycle to take into consideration the instruction cache
1564 effects.
1566 On v9 and later, which have branch prediction facilities, we set
1567 it to the depth of the pipeline as that is the cost of a
1568 mispredicted branch.
1570 On Niagara, normal branches insert 3 bubbles into the pipe
1571 and annulled branches insert 4 bubbles.
1573 On Niagara-2 and Niagara-3, a not-taken branch costs 1 cycle whereas
1574 a taken branch costs 6 cycles.
1576 The T4 Supplement specifies the branch latency at 2 cycles.
1577 The M7 Supplement specifies the branch latency at 1 cycle. */
1579 #define BRANCH_COST(speed_p, predictable_p) \
1580 ((sparc_cpu == PROCESSOR_V9 \
1581 || sparc_cpu == PROCESSOR_ULTRASPARC) \
1582 ? 7 \
1583 : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
1584 ? 9 \
1585 : (sparc_cpu == PROCESSOR_NIAGARA \
1586 ? 4 \
1587 : ((sparc_cpu == PROCESSOR_NIAGARA2 \
1588 || sparc_cpu == PROCESSOR_NIAGARA3) \
1589 ? 5 \
1590 : (sparc_cpu == PROCESSOR_NIAGARA4 \
1591 ? 2 \
1592 : (sparc_cpu == PROCESSOR_NIAGARA7 \
1593 ? 1 \
1594 : 3))))))
1595 \f
1596 /* Control the assembler format that we output. */
1598 /* A C string constant describing how to begin a comment in the target
1599 assembler language. The compiler assumes that the comment will end at
1600 the end of the line. */
1604 /* Output to assembler file text saying following lines
1605 may contain character constants, extra white space, comments, etc. */
1609 /* Output to assembler file text saying following lines
1610 no longer contain unusual constructs. */
1614 /* How to refer to registers in assembler output.
1615 This sequence is indexed by compiler's hard-register-number (see above). */
1617 #define REGISTER_NAMES \
1632 /* Define additional names for use in asm clobbers and asm declarations. */
1634 #define ADDITIONAL_REGISTER_NAMES \
1637 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length
1638 can run past this up to a continuation point. Once we used 1500, but
1639 a single entry in C++ can run more than 500 bytes, due to the length of
1640 mangled symbol names. dbxout.c should really be fixed to do
1641 continuations when they are actually needed instead of trying to
1642 guess... */
1643 #define DBX_CONTIN_LENGTH 1000
1645 /* This is how to output a command to make the user-level label named NAME
1646 defined for reference from other files. */
1648 /* Globalizing directive for a label. */
1651 /* The prefix to add to user-visible assembler symbols. */
1655 /* This is how to store into the string LABEL
1656 the symbol_ref name of an internal numbered label where
1657 PREFIX is the class of label and NUM is the number within the class.
1658 This is suitable for output with `assemble_name'. */
1660 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1663 /* This is how we hook in and defer the case-vector until the end of
1664 the function. */
1665 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \
1666 sparc_defer_case_vector ((LAB),(VEC), 0)
1668 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \
1669 sparc_defer_case_vector ((LAB),(VEC), 1)
1671 /* This is how to output an element of a case-vector that is absolute. */
1673 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1674 do { \
1675 char label[30]; \
1677 if (CASE_VECTOR_MODE == SImode) \
1679 else \
1681 assemble_name (FILE, label); \
1683 } while (0)
1685 /* This is how to output an element of a case-vector that is relative.
1686 (SPARC uses such vectors only when generating PIC.) */
1688 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1689 do { \
1690 char label[30]; \
1692 if (CASE_VECTOR_MODE == SImode) \
1694 else \
1696 assemble_name (FILE, label); \
1699 assemble_name (FILE, label); \
1701 } while (0)
1703 /* This is what to output before and after case-vector (both
1704 relative and absolute). If .subsection -1 works, we put case-vectors
1705 at the beginning of the current section. */
1707 #ifdef HAVE_GAS_SUBSECTION_ORDERING
1709 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \
1712 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \
1715 #endif
1717 /* This is how to output an assembler line
1718 that says to advance the location counter
1719 to a multiple of 2**LOG bytes. */
1721 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1722 if ((LOG) != 0) \
1725 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1728 /* This says how to output an assembler line
1729 to define a global common symbol. */
1731 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1733 assemble_name ((FILE), (NAME)), \
1736 /* This says how to output an assembler line to define a local common
1737 symbol. */
1739 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1741 assemble_name ((FILE), (NAME)), \
1743 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
1745 /* A C statement (sans semicolon) to output to the stdio stream
1746 FILE the assembler definition of uninitialized global DECL named
1747 NAME whose size is SIZE bytes and alignment is ALIGN bytes.
1748 Try to use asm_output_aligned_bss to implement this macro. */
1750 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1751 do { \
1752 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
1753 } while (0)
1755 /* Output #ident as a .ident. */
1757 #undef TARGET_ASM_OUTPUT_IDENT
1758 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive
1760 /* Prettify the assembly. */
1764 #define ASM_OUTPUT_OPCODE(FILE, PTR) \
1765 do { \
1766 if (sparc_indent_opcode) \
1767 { \
1769 sparc_indent_opcode = 0; \
1770 } \
1771 } while (0)
1773 /* TLS support defaulting to original Sun flavor. GNU extensions
1774 must be activated in separate configuration files. */
1775 #ifdef HAVE_AS_TLS
1776 #define TARGET_TLS 1
1777 #else
1778 #define TARGET_TLS 0
1779 #endif
1781 #define TARGET_SUN_TLS TARGET_TLS
1782 #define TARGET_GNU_TLS 0
1784 #ifdef HAVE_AS_FMAF_HPC_VIS3
1786 #else
1788 #endif
1790 #ifdef HAVE_AS_SPARC4
1792 #else
1794 #endif
1796 #ifdef HAVE_AS_SPARC5_VIS4
1798 #else
1799 #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG
1800 #endif
1802 #ifdef HAVE_AS_LEON
1805 #else
1808 #endif
1810 /* We use gcc _mcount for profiling. */
1811 #define NO_PROFILE_COUNTERS 0
1813 /* Debug support */
1815 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS
1817 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS)
1819 /* By default, use the weakest memory model for the cpu. */
1820 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL
1821 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT
1822 #endif
1824 /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */
1825 #define SPARC_LOW_FE_EXCEPT_VALUES 0
1827 #define TARGET_SUPPORTS_WIDE_INT 1