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This PR shows that we get the load/store_lanes logic wrong for arm big-endian.
[official-gcc.git] / gcc / config / mips / mips.h
blob84ae6752759e0f4c6c8d97ee906dbfc5192481a8
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky (lich@inria.inria.fr).
4 Changed by Michael Meissner (meissner@osf.org).
5 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
6 Brendan Eich (brendan@microunity.com).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
23
24
25 #include "config/vxworks-dummy.h"
26
27 #ifdef GENERATOR_FILE
28 /* This is used in some insn conditions, so needs to be declared, but
29 does not need to be defined. */
30 extern int target_flags_explicit;
31 #endif
32
33 /* MIPS external variables defined in mips.c. */
34
35 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
36 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
37 to work on a 64-bit machine. */
38
39 #define ABI_32 0
40 #define ABI_N32 1
41 #define ABI_64 2
42 #define ABI_EABI 3
43 #define ABI_O64 4
44
45 /* Masks that affect tuning.
46
47 PTF_AVOID_BRANCHLIKELY_SPEED
48 Set if it is usually not profitable to use branch-likely instructions
49 for this target when optimizing code for speed, typically because
50 the branches are always predicted taken and so incur a large overhead
51 when not taken.
52
53 PTF_AVOID_BRANCHLIKELY_SIZE
54 As above but when optimizing for size.
55
56 PTF_AVOID_BRANCHLIKELY_ALWAYS
57 As above but regardless of whether we optimize for speed or size.
58
59 PTF_AVOID_IMADD
60 Set if it is usually not profitable to use the integer MADD or MSUB
61 instructions because of the overhead of getting the result out of
62 the HI/LO registers. */
63
64 #define PTF_AVOID_BRANCHLIKELY_SPEED 0x1
65 #define PTF_AVOID_BRANCHLIKELY_SIZE 0x2
66 #define PTF_AVOID_BRANCHLIKELY_ALWAYS (PTF_AVOID_BRANCHLIKELY_SPEED | \
67 PTF_AVOID_BRANCHLIKELY_SIZE)
68 #define PTF_AVOID_IMADD 0x4
69
70 /* Information about one recognized processor. Defined here for the
71 benefit of TARGET_CPU_CPP_BUILTINS. */
72 struct mips_cpu_info {
73 /* The 'canonical' name of the processor as far as GCC is concerned.
74 It's typically a manufacturer's prefix followed by a numerical
75 designation. It should be lowercase. */
76 const char *name;
77
78 /* The internal processor number that most closely matches this
79 entry. Several processors can have the same value, if there's no
80 difference between them from GCC's point of view. */
81 enum processor cpu;
82
83 /* The ISA level that the processor implements. */
84 int isa;
85
86 /* A mask of PTF_* values. */
87 unsigned int tune_flags;
88 };
89
90 #include "config/mips/mips-opts.h"
91
92 /* Macros to silence warnings about numbers being signed in traditional
93 C and unsigned in ISO C when compiled on 32-bit hosts. */
94
95 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
96 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
97 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
98
99 \f
100 /* Run-time compilation parameters selecting different hardware subsets. */
101
102 /* True if we are generating position-independent VxWorks RTP code. */
103 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
104
105 /* Compact branches must not be used if the user either selects the
106 'never' policy or the 'optimal' policy on a core that lacks
107 compact branch instructions. */
108 #define TARGET_CB_NEVER (mips_cb == MIPS_CB_NEVER \
109 || (mips_cb == MIPS_CB_OPTIMAL \
110 && !ISA_HAS_COMPACT_BRANCHES))
111
112 /* Compact branches may be used if the user either selects the
113 'always' policy or the 'optimal' policy on a core that supports
114 compact branch instructions. */
115 #define TARGET_CB_MAYBE (TARGET_CB_ALWAYS \
116 || (mips_cb == MIPS_CB_OPTIMAL \
117 && ISA_HAS_COMPACT_BRANCHES))
118
119 /* Compact branches must always be generated if the user selects
120 the 'always' policy or the 'optimal' policy om a core that
121 lacks delay slot branch instructions. */
122 #define TARGET_CB_ALWAYS (mips_cb == MIPS_CB_ALWAYS \
123 || (mips_cb == MIPS_CB_OPTIMAL \
124 && !ISA_HAS_DELAY_SLOTS))
125
126 /* Special handling for JRC that exists in microMIPSR3 as well as R6
127 ISAs with full compact branch support. */
128 #define ISA_HAS_JRC ((ISA_HAS_COMPACT_BRANCHES \
129 || TARGET_MICROMIPS) \
130 && mips_cb != MIPS_CB_NEVER)
131
132 /* True if the output file is marked as ".abicalls; .option pic0"
133 (-call_nonpic). */
134 #define TARGET_ABICALLS_PIC0 \
135 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
136
137 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
138 #define TARGET_ABICALLS_PIC2 \
139 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
140
141 /* True if the call patterns should be split into a jalr followed by
142 an instruction to restore $gp. It is only safe to split the load
143 from the call when every use of $gp is explicit.
144
145 See mips_must_initialize_gp_p for details about how we manage the
146 global pointer. */
147
148 #define TARGET_SPLIT_CALLS \
149 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP && epilogue_completed)
150
151 /* True if we're generating a form of -mabicalls in which we can use
152 operators like %hi and %lo to refer to locally-binding symbols.
153 We can only do this for -mno-shared, and only then if we can use
154 relocation operations instead of assembly macros. It isn't really
155 worth using absolute sequences for 64-bit symbols because GOT
156 accesses are so much shorter. */
157
158 #define TARGET_ABSOLUTE_ABICALLS \
159 (TARGET_ABICALLS \
160 && !TARGET_SHARED \
161 && TARGET_EXPLICIT_RELOCS \
162 && !ABI_HAS_64BIT_SYMBOLS)
163
164 /* True if we can optimize sibling calls. For simplicity, we only
165 handle cases in which call_insn_operand will reject invalid
166 sibcall addresses. There are two cases in which this isn't true:
167
168 - TARGET_MIPS16. call_insn_operand accepts constant addresses
169 but there is no direct jump instruction. It isn't worth
170 using sibling calls in this case anyway; they would usually
171 be longer than normal calls.
172
173 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
174 accepts global constants, but all sibcalls must be indirect. */
175 #define TARGET_SIBCALLS \
176 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
177
178 /* True if we need to use a global offset table to access some symbols. */
179 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
180
181 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
182 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
183
184 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
185 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
186
187 /* True if we should use .cprestore to store to the cprestore slot.
188
189 We continue to use .cprestore for explicit-reloc code so that JALs
190 inside inline asms will work correctly. */
191 #define TARGET_CPRESTORE_DIRECTIVE \
192 (TARGET_ABICALLS_PIC2 && !TARGET_MIPS16)
193
194 /* True if we can use the J and JAL instructions. */
195 #define TARGET_ABSOLUTE_JUMPS \
196 (!flag_pic || TARGET_ABSOLUTE_ABICALLS)
197
198 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
199 This is true for both the PIC and non-PIC VxWorks RTP modes. */
200 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
201
202 /* True if .gpword or .gpdword should be used for switch tables. */
203 #define TARGET_GPWORD \
204 (TARGET_ABICALLS && !TARGET_ABSOLUTE_ABICALLS)
205
206 /* True if the output must have a writable .eh_frame.
207 See ASM_PREFERRED_EH_DATA_FORMAT for details. */
208 #ifdef HAVE_LD_PERSONALITY_RELAXATION
209 #define TARGET_WRITABLE_EH_FRAME 0
210 #else
211 #define TARGET_WRITABLE_EH_FRAME (flag_pic && TARGET_SHARED)
212 #endif
213
214 /* Test the assembler to set ISA_HAS_DSP_MULT to DSP Rev 1 or 2. */
215 #ifdef HAVE_AS_DSPR1_MULT
216 #define ISA_HAS_DSP_MULT ISA_HAS_DSP
217 #else
218 #define ISA_HAS_DSP_MULT ISA_HAS_DSPR2
219 #endif
220
221 /* ISA has LSA available. */
222 #define ISA_HAS_LSA (mips_isa_rev >= 6 || ISA_HAS_MSA)
223
224 /* ISA has DLSA available. */
225 #define ISA_HAS_DLSA (TARGET_64BIT \
226 && (mips_isa_rev >= 6 \
227 || ISA_HAS_MSA))
228
229 /* The ISA compression flags that are currently in effect. */
230 #define TARGET_COMPRESSION (target_flags & (MASK_MIPS16 | MASK_MICROMIPS))
231
232 /* Generate mips16 code */
233 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
234 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
235 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
236 /* Generate mips16e register save/restore sequences. */
237 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
238
239 /* True if we're generating a form of MIPS16 code in which general
240 text loads are allowed. */
241 #define TARGET_MIPS16_TEXT_LOADS \
242 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
243
244 /* True if we're generating a form of MIPS16 code in which PC-relative
245 loads are allowed. */
246 #define TARGET_MIPS16_PCREL_LOADS \
247 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
248
249 /* Generic ISA defines. */
250 #define ISA_MIPS1 (mips_isa == 1)
251 #define ISA_MIPS2 (mips_isa == 2)
252 #define ISA_MIPS3 (mips_isa == 3)
253 #define ISA_MIPS4 (mips_isa == 4)
254 #define ISA_MIPS32 (mips_isa == 32)
255 #define ISA_MIPS32R2 (mips_isa == 33)
256 #define ISA_MIPS32R3 (mips_isa == 34)
257 #define ISA_MIPS32R5 (mips_isa == 36)
258 #define ISA_MIPS32R6 (mips_isa == 37)
259 #define ISA_MIPS64 (mips_isa == 64)
260 #define ISA_MIPS64R2 (mips_isa == 65)
261 #define ISA_MIPS64R3 (mips_isa == 66)
262 #define ISA_MIPS64R5 (mips_isa == 68)
263 #define ISA_MIPS64R6 (mips_isa == 69)
264
265 /* Architecture target defines. */
266 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
267 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
268 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
269 #define TARGET_LOONGSON_3A (mips_arch == PROCESSOR_LOONGSON_3A)
270 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
271 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
272 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
273 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
274 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
275 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
276 #define TARGET_MIPS5900 (mips_arch == PROCESSOR_R5900)
277 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
278 #define TARGET_MIPS8000 (mips_arch == PROCESSOR_R8000)
279 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
280 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON \
281 || mips_arch == PROCESSOR_OCTEON2 \
282 || mips_arch == PROCESSOR_OCTEON3)
283 #define TARGET_OCTEON2 (mips_arch == PROCESSOR_OCTEON2 \
284 || mips_arch == PROCESSOR_OCTEON3)
285 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
286 || mips_arch == PROCESSOR_SB1A)
287 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
288 #define TARGET_XLP (mips_arch == PROCESSOR_XLP)
289
290 /* Scheduling target defines. */
291 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
292 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
293 || mips_tune == PROCESSOR_24KF2_1 \
294 || mips_tune == PROCESSOR_24KF1_1)
295 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
296 || mips_tune == PROCESSOR_74KF2_1 \
297 || mips_tune == PROCESSOR_74KF1_1 \
298 || mips_tune == PROCESSOR_74KF3_2)
299 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
300 || mips_tune == PROCESSOR_LOONGSON_2F)
301 #define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
302 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
303 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
304 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
305 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
306 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
307 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
308 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
309 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
310 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
311 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
312 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
313 #define TUNE_OCTEON (mips_tune == PROCESSOR_OCTEON \
314 || mips_tune == PROCESSOR_OCTEON2 \
315 || mips_tune == PROCESSOR_OCTEON3)
316 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
317 || mips_tune == PROCESSOR_SB1A)
318 #define TUNE_P5600 (mips_tune == PROCESSOR_P5600)
319 #define TUNE_I6400 (mips_tune == PROCESSOR_I6400)
320
321 /* Whether vector modes and intrinsics for ST Microelectronics
322 Loongson-2E/2F processors should be enabled. In o32 pairs of
323 floating-point registers provide 64-bit values. */
324 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
325 && (TARGET_LOONGSON_2EF \
326 || TARGET_LOONGSON_3A))
327
328 /* True if the pre-reload scheduler should try to create chains of
329 multiply-add or multiply-subtract instructions. For example,
330 suppose we have:
331
332 t1 = a * b
333 t2 = t1 + c * d
334 t3 = e * f
335 t4 = t3 - g * h
336
337 t1 will have a higher priority than t2 and t3 will have a higher
338 priority than t4. However, before reload, there is no dependence
339 between t1 and t3, and they can often have similar priorities.
340 The scheduler will then tend to prefer:
341
342 t1 = a * b
343 t3 = e * f
344 t2 = t1 + c * d
345 t4 = t3 - g * h
346
347 which stops us from making full use of macc/madd-style instructions.
348 This sort of situation occurs frequently in Fourier transforms and
349 in unrolled loops.
350
351 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
352 queue so that chained multiply-add and multiply-subtract instructions
353 appear ahead of any other instruction that is likely to clobber lo.
354 In the example above, if t2 and t3 become ready at the same time,
355 the code ensures that t2 is scheduled first.
356
357 Multiply-accumulate instructions are a bigger win for some targets
358 than others, so this macro is defined on an opt-in basis. */
359 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
360 || TUNE_MIPS4120 \
361 || TUNE_MIPS4130 \
362 || TUNE_24K \
363 || TUNE_P5600)
364
365 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
366 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
367
368 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
369 directly accessible, while the command-line options select
370 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
371 in use. */
372 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
373 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
374
375 /* TARGET_FLOAT64 represents -mfp64 and TARGET_FLOATXX represents
376 -mfpxx, derive TARGET_FLOAT32 to represent -mfp32. */
377 #define TARGET_FLOAT32 (!TARGET_FLOAT64 && !TARGET_FLOATXX)
378
379 /* TARGET_O32_FP64A_ABI represents all the conditions that form the
380 o32 FP64A ABI extension (-mabi=32 -mfp64 -mno-odd-spreg). */
381 #define TARGET_O32_FP64A_ABI (mips_abi == ABI_32 && TARGET_FLOAT64 \
382 && !TARGET_ODD_SPREG)
383
384 /* False if SC acts as a memory barrier with respect to itself,
385 otherwise a SYNC will be emitted after SC for atomic operations
386 that require ordering between the SC and following loads and
387 stores. It does not tell anything about ordering of loads and
388 stores prior to and following the SC, only about the SC itself and
389 those loads and stores follow it. */
390 #define TARGET_SYNC_AFTER_SC (!TARGET_OCTEON && !TARGET_XLP)
391
392 /* Define preprocessor macros for the -march and -mtune options.
393 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
394 processor. If INFO's canonical name is "foo", define PREFIX to
395 be "foo", and define an additional macro PREFIX_FOO. */
396 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
397 do \
398 { \
399 char *macro, *p; \
400 \
401 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
402 for (p = macro; *p != 0; p++) \
403 if (*p == '+') \
404 *p = 'P'; \
405 else \
406 *p = TOUPPER (*p); \
407 \
408 builtin_define (macro); \
409 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
410 free (macro); \
411 } \
412 while (0)
413
414 /* Target CPU builtins. */
415 #define TARGET_CPU_CPP_BUILTINS() \
416 do \
417 { \
418 builtin_assert ("machine=mips"); \
419 builtin_assert ("cpu=mips"); \
420 builtin_define ("__mips__"); \
421 builtin_define ("_mips"); \
422 \
423 /* We do this here because __mips is defined below and so we \
424 can't use builtin_define_std. We don't ever want to define \
425 "mips" for VxWorks because some of the VxWorks headers \
426 construct include filenames from a root directory macro, \
427 an architecture macro and a filename, where the architecture \
428 macro expands to 'mips'. If we define 'mips' to 1, the \
429 architecture macro expands to 1 as well. */ \
430 if (!flag_iso && !TARGET_VXWORKS) \
431 builtin_define ("mips"); \
432 \
433 if (TARGET_64BIT) \
434 builtin_define ("__mips64"); \
435 \
436 /* Treat _R3000 and _R4000 like register-size \
437 defines, which is how they've historically \
438 been used. */ \
439 if (TARGET_64BIT) \
440 { \
441 builtin_define_std ("R4000"); \
442 builtin_define ("_R4000"); \
443 } \
444 else \
445 { \
446 builtin_define_std ("R3000"); \
447 builtin_define ("_R3000"); \
448 } \
449 \
450 if (TARGET_FLOAT64) \
451 builtin_define ("__mips_fpr=64"); \
452 else if (TARGET_FLOATXX) \
453 builtin_define ("__mips_fpr=0"); \
454 else \
455 builtin_define ("__mips_fpr=32"); \
456 \
457 if (mips_base_compression_flags & MASK_MIPS16) \
458 builtin_define ("__mips16"); \
459 \
460 if (TARGET_MIPS3D) \
461 builtin_define ("__mips3d"); \
462 \
463 if (TARGET_SMARTMIPS) \
464 builtin_define ("__mips_smartmips"); \
465 \
466 if (mips_base_compression_flags & MASK_MICROMIPS) \
467 builtin_define ("__mips_micromips"); \
468 \
469 if (TARGET_MCU) \
470 builtin_define ("__mips_mcu"); \
471 \
472 if (TARGET_EVA) \
473 builtin_define ("__mips_eva"); \
474 \
475 if (TARGET_DSP) \
476 { \
477 builtin_define ("__mips_dsp"); \
478 if (TARGET_DSPR2) \
479 { \
480 builtin_define ("__mips_dspr2"); \
481 builtin_define ("__mips_dsp_rev=2"); \
482 } \
483 else \
484 builtin_define ("__mips_dsp_rev=1"); \
485 } \
486 \
487 if (ISA_HAS_MSA) \
488 { \
489 builtin_define ("__mips_msa"); \
490 builtin_define ("__mips_msa_width=128"); \
491 } \
492 \
493 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
494 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
495 \
496 if (ISA_MIPS1) \
497 { \
498 builtin_define ("__mips=1"); \
499 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
500 } \
501 else if (ISA_MIPS2) \
502 { \
503 builtin_define ("__mips=2"); \
504 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
505 } \
506 else if (ISA_MIPS3) \
507 { \
508 builtin_define ("__mips=3"); \
509 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
510 } \
511 else if (ISA_MIPS4) \
512 { \
513 builtin_define ("__mips=4"); \
514 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
515 } \
516 else if (mips_isa >= 32 && mips_isa < 64) \
517 { \
518 builtin_define ("__mips=32"); \
519 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
520 } \
521 else if (mips_isa >= 64) \
522 { \
523 builtin_define ("__mips=64"); \
524 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
525 } \
526 if (mips_isa_rev > 0) \
527 builtin_define_with_int_value ("__mips_isa_rev", \
528 mips_isa_rev); \
529 \
530 switch (mips_abi) \
531 { \
532 case ABI_32: \
533 builtin_define ("_ABIO32=1"); \
534 builtin_define ("_MIPS_SIM=_ABIO32"); \
535 break; \
536 \
537 case ABI_N32: \
538 builtin_define ("_ABIN32=2"); \
539 builtin_define ("_MIPS_SIM=_ABIN32"); \
540 break; \
541 \
542 case ABI_64: \
543 builtin_define ("_ABI64=3"); \
544 builtin_define ("_MIPS_SIM=_ABI64"); \
545 break; \
546 \
547 case ABI_O64: \
548 builtin_define ("_ABIO64=4"); \
549 builtin_define ("_MIPS_SIM=_ABIO64"); \
550 break; \
551 } \
552 \
553 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
554 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
555 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
556 builtin_define_with_int_value ("_MIPS_FPSET", \
557 32 / MAX_FPRS_PER_FMT); \
558 builtin_define_with_int_value ("_MIPS_SPFPSET", \
559 TARGET_ODD_SPREG ? 32 : 16); \
560 \
561 /* These defines reflect the ABI in use, not whether the \
562 FPU is directly accessible. */ \
563 if (TARGET_NO_FLOAT) \
564 builtin_define ("__mips_no_float"); \
565 else if (TARGET_HARD_FLOAT_ABI) \
566 builtin_define ("__mips_hard_float"); \
567 else \
568 builtin_define ("__mips_soft_float"); \
569 \
570 if (TARGET_SINGLE_FLOAT) \
571 builtin_define ("__mips_single_float"); \
572 \
573 if (TARGET_PAIRED_SINGLE_FLOAT) \
574 builtin_define ("__mips_paired_single_float"); \
575 \
576 if (mips_abs == MIPS_IEEE_754_2008) \
577 builtin_define ("__mips_abs2008"); \
578 \
579 if (mips_nan == MIPS_IEEE_754_2008) \
580 builtin_define ("__mips_nan2008"); \
581 \
582 if (TARGET_BIG_ENDIAN) \
583 { \
584 builtin_define_std ("MIPSEB"); \
585 builtin_define ("_MIPSEB"); \
586 } \
587 else \
588 { \
589 builtin_define_std ("MIPSEL"); \
590 builtin_define ("_MIPSEL"); \
591 } \
592 \
593 /* Whether calls should go through $25. The separate __PIC__ \
594 macro indicates whether abicalls code might use a GOT. */ \
595 if (TARGET_ABICALLS) \
596 builtin_define ("__mips_abicalls"); \
597 \
598 /* Whether Loongson vector modes are enabled. */ \
599 if (TARGET_LOONGSON_VECTORS) \
600 builtin_define ("__mips_loongson_vector_rev"); \
601 \
602 /* Historical Octeon macro. */ \
603 if (TARGET_OCTEON) \
604 builtin_define ("__OCTEON__"); \
605 \
606 if (TARGET_SYNCI) \
607 builtin_define ("__mips_synci"); \
608 \
609 /* Macros dependent on the C dialect. */ \
610 if (preprocessing_asm_p ()) \
611 { \
612 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
613 builtin_define ("_LANGUAGE_ASSEMBLY"); \
614 } \
615 else if (c_dialect_cxx ()) \
616 { \
617 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
618 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
619 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
620 } \
621 else \
622 { \
623 builtin_define_std ("LANGUAGE_C"); \
624 builtin_define ("_LANGUAGE_C"); \
625 } \
626 if (c_dialect_objc ()) \
627 { \
628 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
629 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
630 /* Bizarre, but retained for backwards compatibility. */ \
631 builtin_define_std ("LANGUAGE_C"); \
632 builtin_define ("_LANGUAGE_C"); \
633 } \
634 \
635 if (mips_abi == ABI_EABI) \
636 builtin_define ("__mips_eabi"); \
637 \
638 if (TARGET_CACHE_BUILTIN) \
639 builtin_define ("__GCC_HAVE_BUILTIN_MIPS_CACHE"); \
640 if (!ISA_HAS_LXC1_SXC1) \
641 builtin_define ("__mips_no_lxc1_sxc1"); \
642 if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \
643 builtin_define ("__mips_no_madd4"); \
644 } \
645 while (0)
646
647 /* Default target_flags if no switches are specified */
648
649 #ifndef TARGET_DEFAULT
650 #define TARGET_DEFAULT 0
651 #endif
652
653 #ifndef TARGET_CPU_DEFAULT
654 #define TARGET_CPU_DEFAULT 0
655 #endif
656
657 #ifndef TARGET_ENDIAN_DEFAULT
658 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
659 #endif
660
661 #ifdef IN_LIBGCC2
662 #undef TARGET_64BIT
663 /* Make this compile time constant for libgcc2 */
664 #ifdef __mips64
665 #define TARGET_64BIT 1
666 #else
667 #define TARGET_64BIT 0
668 #endif
669 #endif /* IN_LIBGCC2 */
670
671 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
672 when compiled with hardware floating point. This is because MIPS16
673 code cannot save and restore the floating-point registers, which is
674 important if in a mixed MIPS16/non-MIPS16 environment. */
675
676 #ifdef IN_LIBGCC2
677 #if __mips_hard_float
678 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
679 #endif
680 #endif /* IN_LIBGCC2 */
681
682 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
683
684 #ifndef MULTILIB_ENDIAN_DEFAULT
685 #if TARGET_ENDIAN_DEFAULT == 0
686 #define MULTILIB_ENDIAN_DEFAULT "EL"
687 #else
688 #define MULTILIB_ENDIAN_DEFAULT "EB"
689 #endif
690 #endif
691
692 #ifndef MULTILIB_ISA_DEFAULT
693 #if MIPS_ISA_DEFAULT == 1
694 #define MULTILIB_ISA_DEFAULT "mips1"
695 #elif MIPS_ISA_DEFAULT == 2
696 #define MULTILIB_ISA_DEFAULT "mips2"
697 #elif MIPS_ISA_DEFAULT == 3
698 #define MULTILIB_ISA_DEFAULT "mips3"
699 #elif MIPS_ISA_DEFAULT == 4
700 #define MULTILIB_ISA_DEFAULT "mips4"
701 #elif MIPS_ISA_DEFAULT == 32
702 #define MULTILIB_ISA_DEFAULT "mips32"
703 #elif MIPS_ISA_DEFAULT == 33
704 #define MULTILIB_ISA_DEFAULT "mips32r2"
705 #elif MIPS_ISA_DEFAULT == 37
706 #define MULTILIB_ISA_DEFAULT "mips32r6"
707 #elif MIPS_ISA_DEFAULT == 64
708 #define MULTILIB_ISA_DEFAULT "mips64"
709 #elif MIPS_ISA_DEFAULT == 65
710 #define MULTILIB_ISA_DEFAULT "mips64r2"
711 #elif MIPS_ISA_DEFAULT == 69
712 #define MULTILIB_ISA_DEFAULT "mips64r6"
713 #else
714 #define MULTILIB_ISA_DEFAULT "mips1"
715 #endif
716 #endif
717
718 #ifndef MIPS_ABI_DEFAULT
719 #define MIPS_ABI_DEFAULT ABI_32
720 #endif
721
722 /* Use the most portable ABI flag for the ASM specs. */
723
724 #if MIPS_ABI_DEFAULT == ABI_32
725 #define MULTILIB_ABI_DEFAULT "mabi=32"
726 #elif MIPS_ABI_DEFAULT == ABI_O64
727 #define MULTILIB_ABI_DEFAULT "mabi=o64"
728 #elif MIPS_ABI_DEFAULT == ABI_N32
729 #define MULTILIB_ABI_DEFAULT "mabi=n32"
730 #elif MIPS_ABI_DEFAULT == ABI_64
731 #define MULTILIB_ABI_DEFAULT "mabi=64"
732 #elif MIPS_ABI_DEFAULT == ABI_EABI
733 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
734 #endif
735
736 #ifndef MULTILIB_DEFAULTS
737 #define MULTILIB_DEFAULTS \
738 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
739 #endif
740
741 /* We must pass -EL to the linker by default for little endian embedded
742 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
743 linker will default to using big-endian output files. The OUTPUT_FORMAT
744 line must be in the linker script, otherwise -EB/-EL will not work. */
745
746 #ifndef ENDIAN_SPEC
747 #if TARGET_ENDIAN_DEFAULT == 0
748 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
749 #else
750 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
751 #endif
752 #endif
753
754 /* A spec condition that matches all non-mips16 -mips arguments. */
755
756 #define MIPS_ISA_LEVEL_OPTION_SPEC \
757 "mips1|mips2|mips3|mips4|mips32*|mips64*"
758
759 /* A spec condition that matches all non-mips16 architecture arguments. */
760
761 #define MIPS_ARCH_OPTION_SPEC \
762 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
763
764 /* A spec that infers a -mips argument from an -march argument. */
765
766 #define MIPS_ISA_LEVEL_SPEC \
767 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
768 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
769 %{march=mips2|march=r6000:-mips2} \
770 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
771 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000 \
772 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
773 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
774 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
775 |march=34k*|march=74k*|march=m14k*|march=1004k* \
776 |march=interaptiv: -mips32r2} \
777 %{march=mips32r3: -mips32r3} \
778 %{march=mips32r5|march=p5600|march=m5100|march=m5101: -mips32r5} \
779 %{march=mips32r6: -mips32r6} \
780 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
781 |march=xlr: -mips64} \
782 %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \
783 %{march=mips64r3: -mips64r3} \
784 %{march=mips64r5: -mips64r5} \
785 %{march=mips64r6|march=i6400: -mips64r6}}"
786
787 /* A spec that injects the default multilib ISA if no architecture is
788 specified. */
789
790 #define MIPS_DEFAULT_ISA_LEVEL_SPEC \
791 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
792 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
793
794 /* A spec that infers a -mhard-float or -msoft-float setting from an
795 -march argument. Note that soft-float and hard-float code are not
796 link-compatible. */
797
798 #define MIPS_ARCH_FLOAT_SPEC \
799 "%{mhard-float|msoft-float|mno-float|march=mips*:; \
800 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
801 |march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
802 |march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
803 march=*: -mhard-float}"
804
805 /* A spec condition that matches 32-bit options. It only works if
806 MIPS_ISA_LEVEL_SPEC has been applied. */
807
808 #define MIPS_32BIT_OPTION_SPEC \
809 "mips1|mips2|mips32*|mgp32"
810
811 /* A spec condition that matches architectures should be targeted with
812 o32 FPXX for compatibility reasons. */
813 #define MIPS_FPXX_OPTION_SPEC \
814 "mips2|mips3|mips4|mips5|mips32|mips32r2|mips32r3|mips32r5| \
815 mips64|mips64r2|mips64r3|mips64r5"
816
817 /* Infer a -msynci setting from a -mips argument, on the assumption that
818 -msynci is desired where possible. */
819 #define MIPS_ISA_SYNCI_SPEC \
820 "%{msynci|mno-synci:;:%{mips32r2|mips32r3|mips32r5|mips32r6|mips64r2 \
821 |mips64r3|mips64r5|mips64r6:-msynci;:-mno-synci}}"
822
823 /* Infer a -mnan=2008 setting from a -mips argument. */
824 #define MIPS_ISA_NAN2008_SPEC \
825 "%{mnan*:;mips32r6|mips64r6:-mnan=2008;march=m51*: \
826 %{!msoft-float:-mnan=2008}}"
827
828 #if (MIPS_ABI_DEFAULT == ABI_O64 \
829 || MIPS_ABI_DEFAULT == ABI_N32 \
830 || MIPS_ABI_DEFAULT == ABI_64)
831 #define OPT_ARCH64 "mabi=32|mgp32:;"
832 #define OPT_ARCH32 "mabi=32|mgp32"
833 #else
834 #define OPT_ARCH64 "mabi=o64|mabi=n32|mabi=64|mgp64"
835 #define OPT_ARCH32 "mabi=o64|mabi=n32|mabi=64|mgp64:;"
836 #endif
837
838 /* Support for a compile-time default CPU, et cetera. The rules are:
839 --with-arch is ignored if -march is specified or a -mips is specified
840 (other than -mips16); likewise --with-arch-32 and --with-arch-64.
841 --with-tune is ignored if -mtune is specified; likewise
842 --with-tune-32 and --with-tune-64.
843 --with-abi is ignored if -mabi is specified.
844 --with-float is ignored if -mhard-float or -msoft-float are
845 specified.
846 --with-fpu is ignored if -msoft-float, -msingle-float or -mdouble-float are
847 specified.
848 --with-nan is ignored if -mnan is specified.
849 --with-fp-32 is ignored if -msoft-float, -msingle-float, -mmsa or -mfp are
850 specified.
851 --with-odd-spreg-32 is ignored if -msoft-float, -msingle-float, -modd-spreg
852 or -mno-odd-spreg are specified.
853 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
854 specified. */
855 #define OPTION_DEFAULT_SPECS \
856 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
857 {"arch_32", "%{" OPT_ARCH32 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
858 {"arch_64", "%{" OPT_ARCH64 ":%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
859 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
860 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
861 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
862 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
863 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
864 {"fpu", "%{!msoft-float:%{!msingle-float:%{!mdouble-float:-m%(VALUE)-float}}}" }, \
865 {"nan", "%{!mnan=*:-mnan=%(VALUE)}" }, \
866 {"fp_32", "%{" OPT_ARCH32 \
867 ":%{!msoft-float:%{!msingle-float:%{!mfp*:%{!mmsa:-mfp%(VALUE)}}}}}" }, \
868 {"odd_spreg_32", "%{" OPT_ARCH32 ":%{!msoft-float:%{!msingle-float:" \
869 "%{!modd-spreg:%{!mno-odd-spreg:-m%(VALUE)}}}}}" }, \
870 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
871 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
872 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
873 {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }, \
874 {"lxc1-sxc1", "%{!mlxc1-sxc1:%{!mno-lxc1-sxc1:-m%(VALUE)}}" }, \
875 {"madd4", "%{!mmadd4:%{!mno-madd4:-m%(VALUE)}}" } \
876
877 /* A spec that infers the:
878 -mnan=2008 setting from a -mips argument,
879 -mdsp setting from a -march argument. */
880 #define BASE_DRIVER_SELF_SPECS \
881 MIPS_ISA_NAN2008_SPEC, \
882 "%{!mno-dsp: \
883 %{march=24ke*|march=34kc*|march=34kf*|march=34kx*|march=1004k* \
884 |march=interaptiv: -mdsp} \
885 %{march=74k*|march=m14ke*: %{!mno-dspr2: -mdspr2 -mdsp}}}"
886
887 #define DRIVER_SELF_SPECS \
888 MIPS_ISA_LEVEL_SPEC, \
889 BASE_DRIVER_SELF_SPECS
890
891 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
892 && ISA_HAS_COND_TRAP)
893
894 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
895
896 /* True if the ABI can only work with 64-bit integer registers. We
897 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
898 otherwise floating-point registers must also be 64-bit. */
899 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
900
901 /* Likewise for 32-bit regs. */
902 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
903
904 /* True if the file format uses 64-bit symbols. At present, this is
905 only true for n64, which uses 64-bit ELF. */
906 #define FILE_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
907
908 /* True if symbols are 64 bits wide. This is usually determined by
909 the ABI's file format, but it can be overridden by -msym32. Note that
910 overriding the size with -msym32 changes the ABI of relocatable objects,
911 although it doesn't change the ABI of a fully-linked object. */
912 #define ABI_HAS_64BIT_SYMBOLS (FILE_HAS_64BIT_SYMBOLS \
913 && Pmode == DImode \
914 && !TARGET_SYM32)
915
916 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
917 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
918 || ISA_MIPS4 \
919 || ISA_MIPS64 \
920 || ISA_MIPS64R2 \
921 || ISA_MIPS64R3 \
922 || ISA_MIPS64R5 \
923 || ISA_MIPS64R6)
924
925 #define ISA_HAS_JR (mips_isa_rev <= 5)
926
927 #define ISA_HAS_DELAY_SLOTS 1
928
929 #define ISA_HAS_COMPACT_BRANCHES (mips_isa_rev >= 6)
930
931 /* ISA has branch likely instructions (e.g. mips2). */
932 /* Disable branchlikely for tx39 until compare rewrite. They haven't
933 been generated up to this point. */
934 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 && mips_isa_rev <= 5)
935
936 /* ISA has 32 single-precision registers. */
937 #define ISA_HAS_ODD_SPREG ((mips_isa_rev >= 1 \
938 && !TARGET_LOONGSON_3A) \
939 || TARGET_FLOAT64 \
940 || TARGET_MIPS5900)
941
942 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
943 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
944 || TARGET_MIPS5400 \
945 || TARGET_MIPS5500 \
946 || TARGET_MIPS5900 \
947 || TARGET_MIPS7000 \
948 || TARGET_MIPS9000 \
949 || TARGET_MAD \
950 || (mips_isa_rev >= 1 \
951 && mips_isa_rev <= 5)) \
952 && !TARGET_MIPS16)
953
954 /* ISA has a three-operand multiplication instruction. */
955 #define ISA_HAS_DMUL3 (TARGET_64BIT \
956 && TARGET_OCTEON \
957 && !TARGET_MIPS16)
958
959 /* ISA has HI and LO registers. */
960 #define ISA_HAS_HILO (mips_isa_rev <= 5)
961
962 /* ISA supports instructions DMULT and DMULTU. */
963 #define ISA_HAS_DMULT (TARGET_64BIT \
964 && !TARGET_MIPS5900 \
965 && mips_isa_rev <= 5)
966
967 /* ISA supports instructions MULT and MULTU. */
968 #define ISA_HAS_MULT (mips_isa_rev <= 5)
969
970 /* ISA supports instructions MUL, MULU, MUH, MUHU. */
971 #define ISA_HAS_R6MUL (mips_isa_rev >= 6)
972
973 /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */
974 #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6)
975
976 /* For Loongson, it is preferable to use the Loongson-specific division and
977 modulo instructions instead of the regular (D)DIV(U) instruction,
978 because the former are faster and can also have the effect of reducing
979 code size. */
980 #define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \
981 || TARGET_LOONGSON_3A) \
982 && !TARGET_MIPS16)
983
984 /* ISA supports instructions DDIV and DDIVU. */
985 #define ISA_HAS_DDIV (TARGET_64BIT \
986 && !TARGET_MIPS5900 \
987 && !ISA_AVOID_DIV_HILO \
988 && mips_isa_rev <= 5)
989
990 /* ISA supports instructions DIV and DIVU.
991 This is always true, but the macro is needed for ISA_HAS_<D>DIV
992 in mips.md. */
993 #define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \
994 && mips_isa_rev <= 5)
995
996 /* ISA supports instructions DIV, DIVU, MOD and MODU. */
997 #define ISA_HAS_R6DIV (mips_isa_rev >= 6)
998
999 /* ISA supports instructions DDIV, DDIVU, DMOD and DMODU. */
1000 #define ISA_HAS_R6DDIV (TARGET_64BIT && mips_isa_rev >= 6)
1001
1002 /* ISA has the floating-point conditional move instructions introduced
1003 in mips4. */
1004 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
1005 || (mips_isa_rev >= 1 \
1006 && mips_isa_rev <= 5)) \
1007 && !TARGET_MIPS5500 \
1008 && !TARGET_MIPS16)
1009
1010 /* ISA has the integer conditional move instructions introduced in mips4 and
1011 ST Loongson 2E/2F. */
1012 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
1013 || TARGET_MIPS5900 \
1014 || TARGET_LOONGSON_2EF)
1015
1016 /* ISA has LDC1 and SDC1. */
1017 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
1018 && !TARGET_MIPS5900 \
1019 && !TARGET_MIPS16)
1020
1021 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
1022 branch on CC, and move (both FP and non-FP) on CC. */
1023 #define ISA_HAS_8CC (ISA_MIPS4 \
1024 || (mips_isa_rev >= 1 \
1025 && mips_isa_rev <= 5))
1026
1027 /* ISA has the FP condition code instructions that store the flag in an
1028 FP register. */
1029 #define ISA_HAS_CCF (mips_isa_rev >= 6)
1030
1031 #define ISA_HAS_SEL (mips_isa_rev >= 6)
1032
1033 /* This is a catch all for other mips4 instructions: indexed load, the
1034 FP madd and msub instructions, and the FP recip and recip sqrt
1035 instructions. Note that this macro should only be used by other
1036 ISA_HAS_* macros. */
1037 #define ISA_HAS_FP4 ((ISA_MIPS4 \
1038 || ISA_MIPS64 \
1039 || (mips_isa_rev >= 2 \
1040 && mips_isa_rev <= 5)) \
1041 && !TARGET_MIPS16)
1042
1043 /* ISA has floating-point indexed load and store instructions
1044 (LWXC1, LDXC1, SWXC1 and SDXC1). */
1045 #define ISA_HAS_LXC1_SXC1 (ISA_HAS_FP4 \
1046 && mips_lxc1_sxc1)
1047
1048 /* ISA has paired-single instructions. */
1049 #define ISA_HAS_PAIRED_SINGLE ((ISA_MIPS64 \
1050 || (mips_isa_rev >= 2 \
1051 && mips_isa_rev <= 5)) \
1052 && !TARGET_OCTEON)
1053
1054 /* ISA has conditional trap instructions. */
1055 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
1056 && !TARGET_MIPS16)
1057
1058 /* ISA has conditional trap with immediate instructions. */
1059 #define ISA_HAS_COND_TRAPI (!ISA_MIPS1 \
1060 && mips_isa_rev <= 5 \
1061 && !TARGET_MIPS16)
1062
1063 /* ISA has integer multiply-accumulate instructions, madd and msub. */
1064 #define ISA_HAS_MADD_MSUB (mips_isa_rev >= 1 \
1065 && mips_isa_rev <= 5)
1066
1067 /* Integer multiply-accumulate instructions should be generated. */
1068 #define GENERATE_MADD_MSUB (TARGET_IMADD && !TARGET_MIPS16)
1069
1070 /* ISA has 4 operand fused madd instructions of the form
1071 'd = [+-] (a * b [+-] c)'. */
1072 #define ISA_HAS_FUSED_MADD4 (mips_madd4 \
1073 && (TARGET_MIPS8000 \
1074 || TARGET_LOONGSON_3A))
1075
1076 /* ISA has 4 operand unfused madd instructions of the form
1077 'd = [+-] (a * b [+-] c)'. */
1078 #define ISA_HAS_UNFUSED_MADD4 (mips_madd4 \
1079 && ISA_HAS_FP4 \
1080 && !TARGET_MIPS8000 \
1081 && !TARGET_LOONGSON_3A)
1082
1083 /* ISA has 3 operand r6 fused madd instructions of the form
1084 'c = c [+-] (a * b)'. */
1085 #define ISA_HAS_FUSED_MADDF (mips_isa_rev >= 6)
1086
1087 /* ISA has 3 operand loongson fused madd instructions of the form
1088 'c = [+-] (a * b [+-] c)'. */
1089 #define ISA_HAS_FUSED_MADD3 TARGET_LOONGSON_2EF
1090
1091 /* ISA has floating-point RECIP.fmt and RSQRT.fmt instructions. The
1092 MIPS64 rev. 1 ISA says that RECIP.D and RSQRT.D are unpredictable when
1093 doubles are stored in pairs of FPRs, so for safety's sake, we apply
1094 this restriction to the MIPS IV ISA too. */
1095 #define ISA_HAS_FP_RECIP_RSQRT(MODE) \
1096 (((ISA_HAS_FP4 \
1097 && ((MODE) == SFmode \
1098 || ((TARGET_FLOAT64 \
1099 || mips_isa_rev >= 2) \
1100 && (MODE) == DFmode))) \
1101 || (((MODE) == SFmode \
1102 || (MODE) == DFmode) \
1103 && (mips_isa_rev >= 6)) \
1104 || (TARGET_SB1 \
1105 && (MODE) == V2SFmode)) \
1106 && !TARGET_MIPS16)
1107
1108 #define ISA_HAS_LWL_LWR (mips_isa_rev <= 5 && !TARGET_MIPS16)
1109
1110 #define ISA_HAS_IEEE_754_LEGACY (mips_isa_rev <= 5)
1111
1112 #define ISA_HAS_IEEE_754_2008 (mips_isa_rev >= 2)
1113
1114 /* ISA has count leading zeroes/ones instruction (not implemented). */
1115 #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16)
1116
1117 /* ISA has three operand multiply instructions that put
1118 the high part in an accumulator: mulhi or mulhiu. */
1119 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
1120 || TARGET_MIPS5500 \
1121 || TARGET_SR71K) \
1122 && !TARGET_MIPS16)
1123
1124 /* ISA has three operand multiply instructions that negate the
1125 result and put the result in an accumulator. */
1126 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
1127 || TARGET_MIPS5500 \
1128 || TARGET_SR71K) \
1129 && !TARGET_MIPS16)
1130
1131 /* ISA has three operand multiply instructions that subtract the
1132 result from a 4th operand and put the result in an accumulator. */
1133 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
1134 || TARGET_MIPS5500 \
1135 || TARGET_SR71K) \
1136 && !TARGET_MIPS16)
1137
1138 /* ISA has three operand multiply instructions that add the result
1139 to a 4th operand and put the result in an accumulator. */
1140 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
1141 || TARGET_MIPS4130 \
1142 || TARGET_MIPS5400 \
1143 || TARGET_MIPS5500 \
1144 || TARGET_SR71K) \
1145 && !TARGET_MIPS16)
1146
1147 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
1148 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
1149 || TARGET_MIPS4130) \
1150 && !TARGET_MIPS16)
1151
1152 /* ISA has the "ror" (rotate right) instructions. */
1153 #define ISA_HAS_ROR ((mips_isa_rev >= 2 \
1154 || TARGET_MIPS5400 \
1155 || TARGET_MIPS5500 \
1156 || TARGET_SR71K \
1157 || TARGET_SMARTMIPS) \
1158 && !TARGET_MIPS16)
1159
1160 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
1161 64-bit targets also provide DSBH and DSHD. */
1162 #define ISA_HAS_WSBH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1163
1164 /* ISA has data prefetch instructions. This controls use of 'pref'. */
1165 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
1166 || TARGET_LOONGSON_2EF \
1167 || TARGET_MIPS5900 \
1168 || mips_isa_rev >= 1) \
1169 && !TARGET_MIPS16)
1170
1171 /* ISA has data prefetch, LL and SC with limited 9-bit displacement. */
1172 #define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6)
1173
1174 /* ISA has data indexed prefetch instructions. This controls use of
1175 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1176 (prefx is a cop1x instruction, so can only be used if FP is
1177 enabled.) */
1178 #define ISA_HAS_PREFETCHX ISA_HAS_FP4
1179
1180 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
1181 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
1182 also requires TARGET_DOUBLE_FLOAT. */
1183 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
1184
1185 /* ISA includes the MIPS32r2 seb and seh instructions. */
1186 #define ISA_HAS_SEB_SEH (mips_isa_rev >= 2 && !TARGET_MIPS16)
1187
1188 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
1189 #define ISA_HAS_EXT_INS (mips_isa_rev >= 2 && !TARGET_MIPS16)
1190
1191 /* ISA has instructions for accessing top part of 64-bit fp regs. */
1192 #define ISA_HAS_MXHC1 (!TARGET_FLOAT32 \
1193 && mips_isa_rev >= 2)
1194
1195 /* ISA has lwxs instruction (load w/scaled index address. */
1196 #define ISA_HAS_LWXS ((TARGET_SMARTMIPS || TARGET_MICROMIPS) \
1197 && !TARGET_MIPS16)
1198
1199 /* ISA has lbx, lbux, lhx, lhx, lhux, lwx, lwux, or ldx instruction. */
1200 #define ISA_HAS_LBX (TARGET_OCTEON2)
1201 #define ISA_HAS_LBUX (ISA_HAS_DSP || TARGET_OCTEON2)
1202 #define ISA_HAS_LHX (ISA_HAS_DSP || TARGET_OCTEON2)
1203 #define ISA_HAS_LHUX (TARGET_OCTEON2)
1204 #define ISA_HAS_LWX (ISA_HAS_DSP || TARGET_OCTEON2)
1205 #define ISA_HAS_LWUX (TARGET_OCTEON2 && TARGET_64BIT)
1206 #define ISA_HAS_LDX ((ISA_HAS_DSP || TARGET_OCTEON2) \
1207 && TARGET_64BIT)
1208
1209 /* The DSP ASE is available. */
1210 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
1211
1212 /* Revision 2 of the DSP ASE is available. */
1213 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
1214
1215 /* The MSA ASE is available. */
1216 #define ISA_HAS_MSA (TARGET_MSA && !TARGET_MIPS16)
1217
1218 /* True if the result of a load is not available to the next instruction.
1219 A nop will then be needed between instructions like "lw $4,..."
1220 and "addiu $4,$4,1". */
1221 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
1222 && !TARGET_MIPS3900 \
1223 && !TARGET_MIPS5900 \
1224 && !TARGET_MIPS16 \
1225 && !TARGET_MICROMIPS)
1226
1227 /* Likewise mtc1 and mfc1. */
1228 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
1229 && !TARGET_MIPS5900 \
1230 && !TARGET_LOONGSON_2EF)
1231
1232 /* Likewise floating-point comparisons. */
1233 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
1234 && !TARGET_MIPS5900 \
1235 && !TARGET_LOONGSON_2EF)
1236
1237 /* True if mflo and mfhi can be immediately followed by instructions
1238 which write to the HI and LO registers.
1239
1240 According to MIPS specifications, MIPS ISAs I, II, and III need
1241 (at least) two instructions between the reads of HI/LO and
1242 instructions which write them, and later ISAs do not. Contradicting
1243 the MIPS specifications, some MIPS IV processor user manuals (e.g.
1244 the UM for the NEC Vr5000) document needing the instructions between
1245 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
1246 MIPS64 and later ISAs to have the interlocks, plus any specific
1247 earlier-ISA CPUs for which CPU documentation declares that the
1248 instructions are really interlocked. */
1249 #define ISA_HAS_HILO_INTERLOCKS (mips_isa_rev >= 1 \
1250 || TARGET_MIPS5500 \
1251 || TARGET_MIPS5900 \
1252 || TARGET_LOONGSON_2EF)
1253
1254 /* ISA includes synci, jr.hb and jalr.hb. */
1255 #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
1256
1257 /* ISA includes sync. */
1258 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
1259 #define GENERATE_SYNC \
1260 (target_flags_explicit & MASK_LLSC \
1261 ? TARGET_LLSC && !TARGET_MIPS16 \
1262 : ISA_HAS_SYNC)
1263
1264 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1265 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1266 instructions. */
1267 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
1268 #define GENERATE_LL_SC \
1269 (target_flags_explicit & MASK_LLSC \
1270 ? TARGET_LLSC && !TARGET_MIPS16 \
1271 : ISA_HAS_LL_SC)
1272
1273 #define ISA_HAS_SWAP (TARGET_XLP)
1274 #define ISA_HAS_LDADD (TARGET_XLP)
1275
1276 /* ISA includes the baddu instruction. */
1277 #define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16)
1278
1279 /* ISA includes the bbit* instructions. */
1280 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
1281
1282 /* ISA includes the cins instruction. */
1283 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
1284
1285 /* ISA includes the exts instruction. */
1286 #define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16)
1287
1288 /* ISA includes the seq and sne instructions. */
1289 #define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16)
1290
1291 /* ISA includes the pop instruction. */
1292 #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16)
1293
1294 /* The CACHE instruction is available in non-MIPS16 code. */
1295 #define TARGET_CACHE_BUILTIN (mips_isa >= 3)
1296
1297 /* The CACHE instruction is available. */
1298 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
1299 \f
1300 /* Tell collect what flags to pass to nm. */
1301 #ifndef NM_FLAGS
1302 #define NM_FLAGS "-Bn"
1303 #endif
1304
1305 \f
1306 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1307 the assembler. It may be overridden by subtargets.
1308
1309 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1310 COFF debugging info. */
1311
1312 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1313 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1314 %{g} %{g0} %{g1} %{g2} %{g3} \
1315 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1316 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1317 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3}"
1318 #endif
1319
1320 /* FP_ASM_SPEC represents the floating-point options that must be passed
1321 to the assembler when FPXX support exists. Prior to that point the
1322 assembler could accept the options but were not required for
1323 correctness. We only add the options when absolutely necessary
1324 because passing -msoft-float to the assembler will cause it to reject
1325 all hard-float instructions which may require some user code to be
1326 updated. */
1327
1328 #ifdef HAVE_AS_DOT_MODULE
1329 #define FP_ASM_SPEC "\
1330 %{mhard-float} %{msoft-float} \
1331 %{msingle-float} %{mdouble-float}"
1332 #else
1333 #define FP_ASM_SPEC
1334 #endif
1335
1336 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1337 overridden by subtargets. */
1338
1339 #ifndef SUBTARGET_ASM_SPEC
1340 #define SUBTARGET_ASM_SPEC ""
1341 #endif
1342
1343 #undef ASM_SPEC
1344 #define ASM_SPEC "\
1345 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1346 %{mips32*} %{mips64*} \
1347 %{mips16} %{mno-mips16:-no-mips16} \
1348 %{mmicromips} %{mno-micromips} \
1349 %{mips3d} %{mno-mips3d:-no-mips3d} \
1350 %{mdmx} %{mno-mdmx:-no-mdmx} \
1351 %{mdsp} %{mno-dsp} \
1352 %{mdspr2} %{mno-dspr2} \
1353 %{mmcu} %{mno-mcu} \
1354 %{meva} %{mno-eva} \
1355 %{mvirt} %{mno-virt} \
1356 %{mxpa} %{mno-xpa} \
1357 %{mmsa} %{mno-msa} \
1358 %{msmartmips} %{mno-smartmips} \
1359 %{mmt} %{mno-mt} \
1360 %{mfix-rm7000} %{mno-fix-rm7000} \
1361 %{mfix-vr4120} %{mfix-vr4130} \
1362 %{mfix-24k} \
1363 %{noasmopt:-O0; O0|fno-delayed-branch:-O1; O*:-O2; :-O1} \
1364 %(subtarget_asm_debugging_spec) \
1365 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1366 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1367 %{mfp32} %{mfpxx} %{mfp64} %{mnan=*} \
1368 %{modd-spreg} %{mno-odd-spreg} \
1369 %{mshared} %{mno-shared} \
1370 %{msym32} %{mno-sym32} \
1371 %{mtune=*}" \
1372 FP_ASM_SPEC "\
1373 %(subtarget_asm_spec)"
1374
1375 /* Extra switches sometimes passed to the linker. */
1376
1377 #ifndef LINK_SPEC
1378 #define LINK_SPEC "\
1379 %(endian_spec) \
1380 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1381 %{shared}"
1382 #endif /* LINK_SPEC defined */
1383
1384
1385 /* Specs for the compiler proper */
1386
1387 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1388 overridden by subtargets. */
1389 #ifndef SUBTARGET_CC1_SPEC
1390 #define SUBTARGET_CC1_SPEC ""
1391 #endif
1392
1393 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1394
1395 #undef CC1_SPEC
1396 #define CC1_SPEC "\
1397 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1398 %(subtarget_cc1_spec)"
1399
1400 /* Preprocessor specs. */
1401
1402 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1403 overridden by subtargets. */
1404 #ifndef SUBTARGET_CPP_SPEC
1405 #define SUBTARGET_CPP_SPEC ""
1406 #endif
1407
1408 #define CPP_SPEC "%(subtarget_cpp_spec)"
1409
1410 /* This macro defines names of additional specifications to put in the specs
1411 that can be used in various specifications like CC1_SPEC. Its definition
1412 is an initializer with a subgrouping for each command option.
1413
1414 Each subgrouping contains a string constant, that defines the
1415 specification name, and a string constant that used by the GCC driver
1416 program.
1417
1418 Do not define this macro if it does not need to do anything. */
1419
1420 #define EXTRA_SPECS \
1421 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1422 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1423 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1424 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1425 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1426 { "endian_spec", ENDIAN_SPEC }, \
1427 SUBTARGET_EXTRA_SPECS
1428
1429 #ifndef SUBTARGET_EXTRA_SPECS
1430 #define SUBTARGET_EXTRA_SPECS
1431 #endif
1432 \f
1433 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1434 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1435
1436 #ifndef PREFERRED_DEBUGGING_TYPE
1437 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1438 #endif
1439
1440 /* The size of DWARF addresses should be the same as the size of symbols
1441 in the target file format. They shouldn't depend on things like -msym32,
1442 because many DWARF consumers do not allow the mixture of address sizes
1443 that one would then get from linking -msym32 code with -msym64 code.
1444
1445 Note that the default POINTER_SIZE test is not appropriate for MIPS.
1446 EABI64 has 64-bit pointers but uses 32-bit ELF. */
1447 #define DWARF2_ADDR_SIZE (FILE_HAS_64BIT_SYMBOLS ? 8 : 4)
1448
1449 /* By default, turn on GDB extensions. */
1450 #define DEFAULT_GDB_EXTENSIONS 1
1451
1452 /* Registers may have a prefix which can be ignored when matching
1453 user asm and register definitions. */
1454 #ifndef REGISTER_PREFIX
1455 #define REGISTER_PREFIX "$"
1456 #endif
1457
1458 /* Local compiler-generated symbols must have a prefix that the assembler
1459 understands. By default, this is $, although some targets (e.g.,
1460 NetBSD-ELF) need to override this. */
1461
1462 #ifndef LOCAL_LABEL_PREFIX
1463 #define LOCAL_LABEL_PREFIX "$"
1464 #endif
1465
1466 /* By default on the mips, external symbols do not have an underscore
1467 prepended, but some targets (e.g., NetBSD) require this. */
1468
1469 #ifndef USER_LABEL_PREFIX
1470 #define USER_LABEL_PREFIX ""
1471 #endif
1472
1473 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1474 since the length can run past this up to a continuation point. */
1475 #undef DBX_CONTIN_LENGTH
1476 #define DBX_CONTIN_LENGTH 1500
1477
1478 /* How to renumber registers for dbx and gdb. */
1479 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1480
1481 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1482 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1483
1484 /* The DWARF 2 CFA column which tracks the return address. */
1485 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
1486
1487 /* Before the prologue, RA lives in r31. */
1488 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)
1489
1490 /* Describe how we implement __builtin_eh_return. */
1491 #define EH_RETURN_DATA_REGNO(N) \
1492 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1493
1494 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1495
1496 #define EH_USES(N) mips_eh_uses (N)
1497
1498 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1499 The default for this in 64-bit mode is 8, which causes problems with
1500 SFmode register saves. */
1501 #define DWARF_CIE_DATA_ALIGNMENT -4
1502
1503 /* Correct the offset of automatic variables and arguments. Note that
1504 the MIPS debug format wants all automatic variables and arguments
1505 to be in terms of the virtual frame pointer (stack pointer before
1506 any adjustment in the function), while the MIPS 3.0 linker wants
1507 the frame pointer to be the stack pointer after the initial
1508 adjustment. */
1509
1510 #define DEBUGGER_AUTO_OFFSET(X) \
1511 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1512 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1513 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1514 \f
1515 /* Target machine storage layout */
1516
1517 #define BITS_BIG_ENDIAN 0
1518 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1519 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1520
1521 #define MAX_BITS_PER_WORD 64
1522
1523 /* Width of a word, in units (bytes). */
1524 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1525 #ifndef IN_LIBGCC2
1526 #define MIN_UNITS_PER_WORD 4
1527 #endif
1528
1529 /* Width of a MSA vector register in bytes. */
1530 #define UNITS_PER_MSA_REG 16
1531 /* Width of a MSA vector register in bits. */
1532 #define BITS_PER_MSA_REG (UNITS_PER_MSA_REG * BITS_PER_UNIT)
1533
1534 /* For MIPS, width of a floating point register. */
1535 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1536
1537 /* The number of consecutive floating-point registers needed to store the
1538 largest format supported by the FPU. */
1539 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1540
1541 /* The number of consecutive floating-point registers needed to store the
1542 smallest format supported by the FPU. */
1543 #define MIN_FPRS_PER_FMT \
1544 (TARGET_ODD_SPREG ? 1 : MAX_FPRS_PER_FMT)
1545
1546 /* The largest size of value that can be held in floating-point
1547 registers and moved with a single instruction. */
1548 #define UNITS_PER_HWFPVALUE \
1549 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1550
1551 /* The largest size of value that can be held in floating-point
1552 registers. */
1553 #define UNITS_PER_FPVALUE \
1554 (TARGET_SOFT_FLOAT_ABI ? 0 \
1555 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1556 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1557
1558 /* The number of bytes in a double. */
1559 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1560
1561 /* Set the sizes of the core types. */
1562 #define SHORT_TYPE_SIZE 16
1563 #define INT_TYPE_SIZE 32
1564 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1565 #define LONG_LONG_TYPE_SIZE 64
1566
1567 #define FLOAT_TYPE_SIZE 32
1568 #define DOUBLE_TYPE_SIZE 64
1569 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1570
1571 /* Define the sizes of fixed-point types. */
1572 #define SHORT_FRACT_TYPE_SIZE 8
1573 #define FRACT_TYPE_SIZE 16
1574 #define LONG_FRACT_TYPE_SIZE 32
1575 #define LONG_LONG_FRACT_TYPE_SIZE 64
1576
1577 #define SHORT_ACCUM_TYPE_SIZE 16
1578 #define ACCUM_TYPE_SIZE 32
1579 #define LONG_ACCUM_TYPE_SIZE 64
1580 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1581 doesn't support 128-bit integers for MIPS32 currently. */
1582 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1583
1584 /* long double is not a fixed mode, but the idea is that, if we
1585 support long double, we also want a 128-bit integer type. */
1586 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1587
1588 /* Width in bits of a pointer. */
1589 #ifndef POINTER_SIZE
1590 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1591 #endif
1592
1593 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1594 #define PARM_BOUNDARY BITS_PER_WORD
1595
1596 /* Allocation boundary (in *bits*) for the code of a function. */
1597 #define FUNCTION_BOUNDARY 32
1598
1599 /* Alignment of field after `int : 0' in a structure. */
1600 #define EMPTY_FIELD_BOUNDARY 32
1601
1602 /* Every structure's size must be a multiple of this. */
1603 /* 8 is observed right on a DECstation and on riscos 4.02. */
1604 #define STRUCTURE_SIZE_BOUNDARY 8
1605
1606 /* There is no point aligning anything to a rounder boundary than
1607 LONG_DOUBLE_TYPE_SIZE, unless under MSA the bigggest alignment is
1608 BITS_PER_MSA_REG. */
1609 #define BIGGEST_ALIGNMENT \
1610 (ISA_HAS_MSA ? BITS_PER_MSA_REG : LONG_DOUBLE_TYPE_SIZE)
1611
1612 /* All accesses must be aligned. */
1613 #define STRICT_ALIGNMENT 1
1614
1615 /* Define this if you wish to imitate the way many other C compilers
1616 handle alignment of bitfields and the structures that contain
1617 them.
1618
1619 The behavior is that the type written for a bit-field (`int',
1620 `short', or other integer type) imposes an alignment for the
1621 entire structure, as if the structure really did contain an
1622 ordinary field of that type. In addition, the bit-field is placed
1623 within the structure so that it would fit within such a field,
1624 not crossing a boundary for it.
1625
1626 Thus, on most machines, a bit-field whose type is written as `int'
1627 would not cross a four-byte boundary, and would force four-byte
1628 alignment for the whole structure. (The alignment used may not
1629 be four bytes; it is controlled by the other alignment
1630 parameters.)
1631
1632 If the macro is defined, its definition should be a C expression;
1633 a nonzero value for the expression enables this behavior. */
1634
1635 #define PCC_BITFIELD_TYPE_MATTERS 1
1636
1637 /* If defined, a C expression to compute the alignment for a static
1638 variable. TYPE is the data type, and ALIGN is the alignment that
1639 the object would ordinarily have. The value of this macro is used
1640 instead of that alignment to align the object.
1641
1642 If this macro is not defined, then ALIGN is used.
1643
1644 One use of this macro is to increase alignment of medium-size
1645 data to make it all fit in fewer cache lines. Another is to
1646 cause character arrays to be word-aligned so that `strcpy' calls
1647 that copy constants to character arrays can be done inline. */
1648
1649 #undef DATA_ALIGNMENT
1650 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1651 ((((ALIGN) < BITS_PER_WORD) \
1652 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1653 || TREE_CODE (TYPE) == UNION_TYPE \
1654 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1655
1656 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1657 character arrays to be word-aligned so that `strcpy' calls that copy
1658 constants to character arrays can be done inline, and 'strcmp' can be
1659 optimised to use word loads. */
1660 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1661 DATA_ALIGNMENT (TYPE, ALIGN)
1662
1663 #define PAD_VARARGS_DOWN \
1664 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1665
1666 /* Define if operations between registers always perform the operation
1667 on the full register even if a narrower mode is specified. */
1668 #define WORD_REGISTER_OPERATIONS 1
1669
1670 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1671 moves. All other references are zero extended. */
1672 #define LOAD_EXTEND_OP(MODE) \
1673 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1674 ? SIGN_EXTEND : ZERO_EXTEND)
1675
1676 /* Define this macro if it is advisable to hold scalars in registers
1677 in a wider mode than that declared by the program. In such cases,
1678 the value is constrained to be within the bounds of the declared
1679 type, but kept valid in the wider mode. The signedness of the
1680 extension may differ from that of the type. */
1681
1682 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1683 if (GET_MODE_CLASS (MODE) == MODE_INT \
1684 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1685 { \
1686 if ((MODE) == SImode) \
1687 (UNSIGNEDP) = 0; \
1688 (MODE) = Pmode; \
1689 }
1690
1691 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1692 Extensions of pointers to word_mode must be signed. */
1693 #define POINTERS_EXTEND_UNSIGNED false
1694
1695 /* Define if loading short immediate values into registers sign extends. */
1696 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
1697
1698 /* The [d]clz instructions have the natural values at 0. */
1699
1700 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1701 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2)
1702 \f
1703 /* Standard register usage. */
1704
1705 /* Number of hardware registers. We have:
1706
1707 - 32 integer registers
1708 - 32 floating point registers
1709 - 8 condition code registers
1710 - 2 accumulator registers (hi and lo)
1711 - 32 registers each for coprocessors 0, 2 and 3
1712 - 4 fake registers:
1713 - ARG_POINTER_REGNUM
1714 - FRAME_POINTER_REGNUM
1715 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1716 - CPRESTORE_SLOT_REGNUM
1717 - 2 dummy entries that were used at various times in the past.
1718 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1719 - 6 DSP control registers */
1720
1721 #define FIRST_PSEUDO_REGISTER 188
1722
1723 /* By default, fix the kernel registers ($26 and $27), the global
1724 pointer ($28) and the stack pointer ($29). This can change
1725 depending on the command-line options.
1726
1727 Regarding coprocessor registers: without evidence to the contrary,
1728 it's best to assume that each coprocessor register has a unique
1729 use. This can be overridden, in, e.g., mips_option_override or
1730 TARGET_CONDITIONAL_REGISTER_USAGE should the assumption be
1731 inappropriate for a particular target. */
1732
1733 #define FIXED_REGISTERS \
1734 { \
1735 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1736 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1737 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1738 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1739 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1740 /* COP0 registers */ \
1741 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1742 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1743 /* COP2 registers */ \
1744 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1745 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1746 /* COP3 registers */ \
1747 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1748 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1749 /* 6 DSP accumulator registers & 6 control registers */ \
1750 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1751 }
1752
1753
1754 /* Set up this array for o32 by default.
1755
1756 Note that we don't mark $31 as a call-clobbered register. The idea is
1757 that it's really the call instructions themselves which clobber $31.
1758 We don't care what the called function does with it afterwards.
1759
1760 This approach makes it easier to implement sibcalls. Unlike normal
1761 calls, sibcalls don't clobber $31, so the register reaches the
1762 called function in tact. EPILOGUE_USES says that $31 is useful
1763 to the called function. */
1764
1765 #define CALL_USED_REGISTERS \
1766 { \
1767 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1768 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1769 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1770 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1771 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1772 /* COP0 registers */ \
1773 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1774 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1775 /* COP2 registers */ \
1776 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1777 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1778 /* COP3 registers */ \
1779 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1780 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1781 /* 6 DSP accumulator registers & 6 control registers */ \
1782 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1783 }
1784
1785
1786 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1787
1788 #define CALL_REALLY_USED_REGISTERS \
1789 { /* General registers. */ \
1790 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1791 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1792 /* Floating-point registers. */ \
1793 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1794 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1795 /* Others. */ \
1796 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1797 /* COP0 registers */ \
1798 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1799 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1800 /* COP2 registers */ \
1801 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1802 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1803 /* COP3 registers */ \
1804 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1805 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1806 /* 6 DSP accumulator registers & 6 control registers */ \
1807 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1808 }
1809
1810 /* Internal macros to classify a register number as to whether it's a
1811 general purpose register, a floating point register, a
1812 multiply/divide register, or a status register. */
1813
1814 #define GP_REG_FIRST 0
1815 #define GP_REG_LAST 31
1816 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1817 #define GP_DBX_FIRST 0
1818 #define K0_REG_NUM (GP_REG_FIRST + 26)
1819 #define K1_REG_NUM (GP_REG_FIRST + 27)
1820 #define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
1821
1822 #define FP_REG_FIRST 32
1823 #define FP_REG_LAST 63
1824 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1825 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1826
1827 #define MD_REG_FIRST 64
1828 #define MD_REG_LAST 65
1829 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1830 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1831
1832 #define MSA_REG_FIRST FP_REG_FIRST
1833 #define MSA_REG_LAST FP_REG_LAST
1834 #define MSA_REG_NUM FP_REG_NUM
1835
1836 /* The DWARF 2 CFA column which tracks the return address from a
1837 signal handler context. This means that to maintain backwards
1838 compatibility, no hard register can be assigned this column if it
1839 would need to be handled by the DWARF unwinder. */
1840 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1841
1842 #define ST_REG_FIRST 67
1843 #define ST_REG_LAST 74
1844 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1845
1846
1847 /* FIXME: renumber. */
1848 #define COP0_REG_FIRST 80
1849 #define COP0_REG_LAST 111
1850 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1851
1852 #define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
1853 #define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
1854 #define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
1855
1856 #define COP2_REG_FIRST 112
1857 #define COP2_REG_LAST 143
1858 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1859
1860 #define COP3_REG_FIRST 144
1861 #define COP3_REG_LAST 175
1862 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1863
1864 /* These definitions assume that COP0, 2 and 3 are numbered consecutively. */
1865 #define ALL_COP_REG_FIRST COP0_REG_FIRST
1866 #define ALL_COP_REG_LAST COP3_REG_LAST
1867 #define ALL_COP_REG_NUM (ALL_COP_REG_LAST - ALL_COP_REG_FIRST + 1)
1868
1869 #define DSP_ACC_REG_FIRST 176
1870 #define DSP_ACC_REG_LAST 181
1871 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1872
1873 #define AT_REGNUM (GP_REG_FIRST + 1)
1874 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1875 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1876
1877 /* A few bitfield locations for the coprocessor registers. */
1878 /* Request Interrupt Priority Level is from bit 10 to bit 15 of
1879 the cause register for the EIC interrupt mode. */
1880 #define CAUSE_IPL 10
1881 /* COP1 Enable is at bit 29 of the status register. */
1882 #define SR_COP1 29
1883 /* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
1884 #define SR_IPL 10
1885 /* Interrupt masks start with IM0 at bit 8 to IM7 at bit 15 of the status
1886 register. */
1887 #define SR_IM0 8
1888 /* Exception Level is at bit 1 of the status register. */
1889 #define SR_EXL 1
1890 /* Interrupt Enable is at bit 0 of the status register. */
1891 #define SR_IE 0
1892
1893 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1894 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1895 should be used instead. */
1896 #define FPSW_REGNUM ST_REG_FIRST
1897
1898 #define GP_REG_P(REGNO) \
1899 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1900 #define M16_REG_P(REGNO) \
1901 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1902 #define M16STORE_REG_P(REGNO) \
1903 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 0 || (REGNO) == 17)
1904 #define FP_REG_P(REGNO) \
1905 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1906 #define MD_REG_P(REGNO) \
1907 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1908 #define ST_REG_P(REGNO) \
1909 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1910 #define COP0_REG_P(REGNO) \
1911 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1912 #define COP2_REG_P(REGNO) \
1913 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1914 #define COP3_REG_P(REGNO) \
1915 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1916 #define ALL_COP_REG_P(REGNO) \
1917 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1918 /* Test if REGNO is one of the 6 new DSP accumulators. */
1919 #define DSP_ACC_REG_P(REGNO) \
1920 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1921 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1922 #define ACC_REG_P(REGNO) \
1923 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1924 #define MSA_REG_P(REGNO) \
1925 ((unsigned int) ((int) (REGNO) - MSA_REG_FIRST) < MSA_REG_NUM)
1926
1927 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1928 #define MSA_REG_RTX_P(X) (REG_P (X) && MSA_REG_P (REGNO (X)))
1929
1930 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1931 to initialize the mips16 gp pseudo register. */
1932 #define CONST_GP_P(X) \
1933 (GET_CODE (X) == CONST \
1934 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1935 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1936
1937 /* Return coprocessor number from register number. */
1938
1939 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1940 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1941 : COP3_REG_P (REGNO) ? '3' : '?')
1942
1943
1944 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
1945 mips_hard_regno_rename_ok (OLD_REG, NEW_REG)
1946
1947 /* Select a register mode required for caller save of hard regno REGNO. */
1948 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1949 mips_hard_regno_caller_save_mode (REGNO, NREGS, MODE)
1950
1951 /* Register to use for pushing function arguments. */
1952 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1953
1954 /* These two registers don't really exist: they get eliminated to either
1955 the stack or hard frame pointer. */
1956 #define ARG_POINTER_REGNUM 77
1957 #define FRAME_POINTER_REGNUM 78
1958
1959 /* $30 is not available on the mips16, so we use $17 as the frame
1960 pointer. */
1961 #define HARD_FRAME_POINTER_REGNUM \
1962 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1963
1964 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0
1965 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0
1966
1967 /* Register in which static-chain is passed to a function. */
1968 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1969
1970 /* Registers used as temporaries in prologue/epilogue code:
1971
1972 - If a MIPS16 PIC function needs access to _gp, it first loads
1973 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1974
1975 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1976 register. The register must not conflict with MIPS16_PIC_TEMP.
1977
1978 - If we aren't generating MIPS16 code, the prologue can also use
1979 MIPS_PROLOGUE_TEMP2 as a general temporary register.
1980
1981 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1982 register.
1983
1984 If we're generating MIPS16 code, these registers must come from the
1985 core set of 8. The prologue registers mustn't conflict with any
1986 incoming arguments, the static chain pointer, or the frame pointer.
1987 The epilogue temporary mustn't conflict with the return registers,
1988 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1989 or the EH data registers.
1990
1991 If we're generating interrupt handlers, we use K0 as a temporary register
1992 in prologue/epilogue code. */
1993
1994 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1995 #define MIPS_PROLOGUE_TEMP_REGNUM \
1996 (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
1997 #define MIPS_PROLOGUE_TEMP2_REGNUM \
1998 (TARGET_MIPS16 \
1999 ? (gcc_unreachable (), INVALID_REGNUM) \
2000 : cfun->machine->interrupt_handler_p ? K1_REG_NUM : GP_REG_FIRST + 12)
2001 #define MIPS_EPILOGUE_TEMP_REGNUM \
2002 (cfun->machine->interrupt_handler_p \
2003 ? K0_REG_NUM \
2004 : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
2005
2006 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
2007 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
2008 #define MIPS_PROLOGUE_TEMP2(MODE) \
2009 gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP2_REGNUM)
2010 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
2011
2012 /* Define this macro if it is as good or better to call a constant
2013 function address than to call an address kept in a register. */
2014 #define NO_FUNCTION_CSE 1
2015
2016 /* The ABI-defined global pointer. Sometimes we use a different
2017 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
2018 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
2019
2020 /* We normally use $28 as the global pointer. However, when generating
2021 n32/64 PIC, it is better for leaf functions to use a call-clobbered
2022 register instead. They can then avoid saving and restoring $28
2023 and perhaps avoid using a frame at all.
2024
2025 When a leaf function uses something other than $28, mips_expand_prologue
2026 will modify pic_offset_table_rtx in place. Take the register number
2027 from there after reload. */
2028 #define PIC_OFFSET_TABLE_REGNUM \
2029 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
2030 \f
2031 /* Define the classes of registers for register constraints in the
2032 machine description. Also define ranges of constants.
2033
2034 One of the classes must always be named ALL_REGS and include all hard regs.
2035 If there is more than one class, another class must be named NO_REGS
2036 and contain no registers.
2037
2038 The name GENERAL_REGS must be the name of a class (or an alias for
2039 another name such as ALL_REGS). This is the class of registers
2040 that is allowed by "g" or "r" in a register constraint.
2041 Also, registers outside this class are allocated only when
2042 instructions express preferences for them.
2043
2044 The classes must be numbered in nondecreasing order; that is,
2045 a larger-numbered class must never be contained completely
2046 in a smaller-numbered class.
2047
2048 For any two classes, it is very desirable that there be another
2049 class that represents their union. */
2050
2051 enum reg_class
2052 {
2053 NO_REGS, /* no registers in set */
2054 M16_STORE_REGS, /* microMIPS store registers */
2055 M16_REGS, /* mips16 directly accessible registers */
2056 M16_SP_REGS, /* mips16 + $sp */
2057 T_REG, /* mips16 T register ($24) */
2058 M16_T_REGS, /* mips16 registers plus T register */
2059 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
2060 V1_REG, /* Register $v1 ($3) used for TLS access. */
2061 SPILL_REGS, /* All but $sp and call preserved regs are in here */
2062 LEA_REGS, /* Every GPR except $25 */
2063 GR_REGS, /* integer registers */
2064 FP_REGS, /* floating point registers */
2065 MD0_REG, /* first multiply/divide register */
2066 MD1_REG, /* second multiply/divide register */
2067 MD_REGS, /* multiply/divide registers (hi/lo) */
2068 COP0_REGS, /* generic coprocessor classes */
2069 COP2_REGS,
2070 COP3_REGS,
2071 ST_REGS, /* status registers (fp status) */
2072 DSP_ACC_REGS, /* DSP accumulator registers */
2073 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
2074 FRAME_REGS, /* $arg and $frame */
2075 GR_AND_MD0_REGS, /* union classes */
2076 GR_AND_MD1_REGS,
2077 GR_AND_MD_REGS,
2078 GR_AND_ACC_REGS,
2079 ALL_REGS, /* all registers */
2080 LIM_REG_CLASSES /* max value + 1 */
2081 };
2082
2083 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2084
2085 #define GENERAL_REGS GR_REGS
2086
2087 /* An initializer containing the names of the register classes as C
2088 string constants. These names are used in writing some of the
2089 debugging dumps. */
2090
2091 #define REG_CLASS_NAMES \
2092 { \
2093 "NO_REGS", \
2094 "M16_STORE_REGS", \
2095 "M16_REGS", \
2096 "M16_SP_REGS", \
2097 "T_REG", \
2098 "M16_T_REGS", \
2099 "PIC_FN_ADDR_REG", \
2100 "V1_REG", \
2101 "SPILL_REGS", \
2102 "LEA_REGS", \
2103 "GR_REGS", \
2104 "FP_REGS", \
2105 "MD0_REG", \
2106 "MD1_REG", \
2107 "MD_REGS", \
2108 /* coprocessor registers */ \
2109 "COP0_REGS", \
2110 "COP2_REGS", \
2111 "COP3_REGS", \
2112 "ST_REGS", \
2113 "DSP_ACC_REGS", \
2114 "ACC_REGS", \
2115 "FRAME_REGS", \
2116 "GR_AND_MD0_REGS", \
2117 "GR_AND_MD1_REGS", \
2118 "GR_AND_MD_REGS", \
2119 "GR_AND_ACC_REGS", \
2120 "ALL_REGS" \
2121 }
2122
2123 /* An initializer containing the contents of the register classes,
2124 as integers which are bit masks. The Nth integer specifies the
2125 contents of class N. The way the integer MASK is interpreted is
2126 that register R is in the class if `MASK & (1 << R)' is 1.
2127
2128 When the machine has more than 32 registers, an integer does not
2129 suffice. Then the integers are replaced by sub-initializers,
2130 braced groupings containing several integers. Each
2131 sub-initializer must be suitable as an initializer for the type
2132 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2133
2134 #define REG_CLASS_CONTENTS \
2135 { \
2136 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
2137 { 0x000200fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_STORE_REGS */ \
2138 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_REGS */ \
2139 { 0x200300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_SP_REGS */ \
2140 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* T_REG */ \
2141 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* M16_T_REGS */ \
2142 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* PIC_FN_ADDR_REG */ \
2143 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* V1_REG */ \
2144 { 0x0303fffc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SPILL_REGS */ \
2145 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* LEA_REGS */ \
2146 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* GR_REGS */ \
2147 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* FP_REGS */ \
2148 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* MD0_REG */ \
2149 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* MD1_REG */ \
2150 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* MD_REGS */ \
2151 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* COP0_REGS */ \
2152 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* COP2_REGS */ \
2153 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* COP3_REGS */ \
2154 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* ST_REGS */ \
2155 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* DSP_ACC_REGS */ \
2156 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* ACC_REGS */ \
2157 { 0x00000000, 0x00000000, 0x00006000, 0x00000000, 0x00000000, 0x00000000 }, /* FRAME_REGS */ \
2158 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD0_REGS */ \
2159 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD1_REGS */ \
2160 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* GR_AND_MD_REGS */ \
2161 { 0xffffffff, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* GR_AND_ACC_REGS */ \
2162 { 0xffffffff, 0xffffffff, 0xffff67ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* ALL_REGS */ \
2163 }
2164
2165
2166 /* A C expression whose value is a register class containing hard
2167 register REGNO. In general there is more that one such class;
2168 choose a class which is "minimal", meaning that no smaller class
2169 also contains the register. */
2170
2171 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2172
2173 /* A macro whose definition is the name of the class to which a
2174 valid base register must belong. A base register is one used in
2175 an address which is the register value plus a displacement. */
2176
2177 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_SP_REGS : GR_REGS)
2178
2179 /* A macro whose definition is the name of the class to which a
2180 valid index register must belong. An index register is one used
2181 in an address where its value is either multiplied by a scale
2182 factor or added to another register (as well as added to a
2183 displacement). */
2184
2185 #define INDEX_REG_CLASS NO_REGS
2186
2187 /* We generally want to put call-clobbered registers ahead of
2188 call-saved ones. (IRA expects this.) */
2189
2190 #define REG_ALLOC_ORDER \
2191 { /* Accumulator registers. When GPRs and accumulators have equal \
2192 cost, we generally prefer to use accumulators. For example, \
2193 a division of multiplication result is better allocated to LO, \
2194 so that we put the MFLO at the point of use instead of at the \
2195 point of definition. It's also needed if we're to take advantage \
2196 of the extra accumulators available with -mdspr2. In some cases, \
2197 it can also help to reduce register pressure. */ \
2198 64, 65,176,177,178,179,180,181, \
2199 /* Call-clobbered GPRs. */ \
2200 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2201 24, 25, 31, \
2202 /* The global pointer. This is call-clobbered for o32 and o64 \
2203 abicalls, call-saved for n32 and n64 abicalls, and a program \
2204 invariant otherwise. Putting it between the call-clobbered \
2205 and call-saved registers should cope with all eventualities. */ \
2206 28, \
2207 /* Call-saved GPRs. */ \
2208 16, 17, 18, 19, 20, 21, 22, 23, 30, \
2209 /* GPRs that can never be exposed to the register allocator. */ \
2210 0, 26, 27, 29, \
2211 /* Call-clobbered FPRs. */ \
2212 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2213 48, 49, 50, 51, \
2214 /* FPRs that are usually call-saved. The odd ones are actually \
2215 call-clobbered for n32, but listing them ahead of the even \
2216 registers might encourage the register allocator to fragment \
2217 the available FPR pairs. We need paired FPRs to store long \
2218 doubles, so it isn't clear that using a different order \
2219 for n32 would be a win. */ \
2220 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2221 /* None of the remaining classes have defined call-saved \
2222 registers. */ \
2223 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2224 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2225 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2226 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2227 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2228 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2229 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
2230 182,183,184,185,186,187 \
2231 }
2232
2233 /* True if VALUE is an unsigned 6-bit number. */
2234
2235 #define UIMM6_OPERAND(VALUE) \
2236 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
2237
2238 /* True if VALUE is a signed 10-bit number. */
2239
2240 #define IMM10_OPERAND(VALUE) \
2241 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
2242
2243 /* True if VALUE is a signed 16-bit number. */
2244
2245 #define SMALL_OPERAND(VALUE) \
2246 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
2247
2248 /* True if VALUE is an unsigned 16-bit number. */
2249
2250 #define SMALL_OPERAND_UNSIGNED(VALUE) \
2251 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
2252
2253 /* True if VALUE can be loaded into a register using LUI. */
2254
2255 #define LUI_OPERAND(VALUE) \
2256 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
2257 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
2258
2259 /* Return a value X with the low 16 bits clear, and such that
2260 VALUE - X is a signed 16-bit value. */
2261
2262 #define CONST_HIGH_PART(VALUE) \
2263 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
2264
2265 #define CONST_LOW_PART(VALUE) \
2266 ((VALUE) - CONST_HIGH_PART (VALUE))
2267
2268 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
2269 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
2270 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
2271 #define UMIPS_12BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -2048, 2047))
2272 #define MIPS_9BIT_OFFSET_P(OFFSET) (IN_RANGE (OFFSET, -256, 255))
2273
2274 /* The HI and LO registers can only be reloaded via the general
2275 registers. Condition code registers can only be loaded to the
2276 general registers, and from the floating point registers. */
2277
2278 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2279 mips_secondary_reload_class (CLASS, MODE, X, true)
2280 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2281 mips_secondary_reload_class (CLASS, MODE, X, false)
2282
2283 /* Return the maximum number of consecutive registers
2284 needed to represent mode MODE in a register of class CLASS. */
2285
2286 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2287 \f
2288 /* Stack layout; function entry, exit and calling. */
2289
2290 #define STACK_GROWS_DOWNWARD 1
2291
2292 #define FRAME_GROWS_DOWNWARD flag_stack_protect
2293
2294 /* Size of the area allocated in the frame to save the GP. */
2295
2296 #define MIPS_GP_SAVE_AREA_SIZE \
2297 (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0)
2298
2299 #define RETURN_ADDR_RTX mips_return_addr
2300
2301 /* Mask off the MIPS16 ISA bit in unwind addresses.
2302
2303 The reason for this is a little subtle. When unwinding a call,
2304 we are given the call's return address, which on most targets
2305 is the address of the following instruction. However, what we
2306 actually want to find is the EH region for the call itself.
2307 The target-independent unwind code therefore searches for "RA - 1".
2308
2309 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2310 RA - 1 is therefore the real (even-valued) start of the return
2311 instruction. EH region labels are usually odd-valued MIPS16 symbols
2312 too, so a search for an even address within a MIPS16 region would
2313 usually work.
2314
2315 However, there is an exception. If the end of an EH region is also
2316 the end of a function, the end label is allowed to be even. This is
2317 necessary because a following non-MIPS16 function may also need EH
2318 information for its first instruction.
2319
2320 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2321 non-ISA-encoded address. This probably isn't ideal, but it is
2322 the traditional (legacy) behavior. It is therefore only safe
2323 to search MIPS EH regions for an _odd-valued_ address.
2324
2325 Masking off the ISA bit means that the target-independent code
2326 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2327 #define MASK_RETURN_ADDR GEN_INT (-2)
2328
2329
2330 /* Similarly, don't use the least-significant bit to tell pointers to
2331 code from vtable index. */
2332
2333 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2334
2335 /* The eliminations to $17 are only used for mips16 code. See the
2336 definition of HARD_FRAME_POINTER_REGNUM. */
2337
2338 #define ELIMINABLE_REGS \
2339 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2340 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2341 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2342 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2343 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2344 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2345
2346 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2347 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2348
2349 /* Allocate stack space for arguments at the beginning of each function. */
2350 #define ACCUMULATE_OUTGOING_ARGS 1
2351
2352 /* The argument pointer always points to the first argument. */
2353 #define FIRST_PARM_OFFSET(FNDECL) 0
2354
2355 /* o32 and o64 reserve stack space for all argument registers. */
2356 #define REG_PARM_STACK_SPACE(FNDECL) \
2357 (TARGET_OLDABI \
2358 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2359 : 0)
2360
2361 /* Define this if it is the responsibility of the caller to
2362 allocate the area reserved for arguments passed in registers.
2363 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2364 of this macro is to determine whether the space is included in
2365 `crtl->outgoing_args_size'. */
2366 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2367
2368 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2369 \f
2370 /* Symbolic macros for the registers used to return integer and floating
2371 point values. */
2372
2373 #define GP_RETURN (GP_REG_FIRST + 2)
2374 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2375
2376 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2377
2378 /* Symbolic macros for the first/last argument registers. */
2379
2380 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2381 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2382 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2383 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2384
2385 /* True if MODE is vector and supported in a MSA vector register. */
2386 #define MSA_SUPPORTED_MODE_P(MODE) \
2387 (ISA_HAS_MSA \
2388 && GET_MODE_SIZE (MODE) == UNITS_PER_MSA_REG \
2389 && (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
2390 || GET_MODE_CLASS (MODE) == MODE_VECTOR_FLOAT))
2391
2392 /* Temporary register that is used when restoring $gp after a call. $4 and $5
2393 are used for returning complex double values in soft-float code, so $6 is the
2394 first suitable candidate for TARGET_MIPS16. For !TARGET_MIPS16 we can use
2395 $gp itself as the temporary. */
2396 #define POST_CALL_TMP_REG \
2397 (TARGET_MIPS16 ? GP_ARG_FIRST + 2 : PIC_OFFSET_TABLE_REGNUM)
2398
2399 /* 1 if N is a possible register number for function argument passing.
2400 We have no FP argument registers when soft-float. Special handling
2401 is required for O32 where only even numbered registers are used for
2402 O32-FPXX and O32-FP64. */
2403
2404 #define FUNCTION_ARG_REGNO_P(N) \
2405 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2406 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2407 && (mips_abi != ABI_32 \
2408 || TARGET_FLOAT32 \
2409 || ((N) % 2 == 0)))) \
2410 && !fixed_regs[N])
2411 \f
2412 /* This structure has to cope with two different argument allocation
2413 schemes. Most MIPS ABIs view the arguments as a structure, of which
2414 the first N words go in registers and the rest go on the stack. If I
2415 < N, the Ith word might go in Ith integer argument register or in a
2416 floating-point register. For these ABIs, we only need to remember
2417 the offset of the current argument into the structure.
2418
2419 The EABI instead allocates the integer and floating-point arguments
2420 separately. The first N words of FP arguments go in FP registers,
2421 the rest go on the stack. Likewise, the first N words of the other
2422 arguments go in integer registers, and the rest go on the stack. We
2423 need to maintain three counts: the number of integer registers used,
2424 the number of floating-point registers used, and the number of words
2425 passed on the stack.
2426
2427 We could keep separate information for the two ABIs (a word count for
2428 the standard ABIs, and three separate counts for the EABI). But it
2429 seems simpler to view the standard ABIs as forms of EABI that do not
2430 allocate floating-point registers.
2431
2432 So for the standard ABIs, the first N words are allocated to integer
2433 registers, and mips_function_arg decides on an argument-by-argument
2434 basis whether that argument should really go in an integer register,
2435 or in a floating-point one. */
2436
2437 typedef struct mips_args {
2438 /* Always true for varargs functions. Otherwise true if at least
2439 one argument has been passed in an integer register. */
2440 int gp_reg_found;
2441
2442 /* The number of arguments seen so far. */
2443 unsigned int arg_number;
2444
2445 /* The number of integer registers used so far. For all ABIs except
2446 EABI, this is the number of words that have been added to the
2447 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2448 unsigned int num_gprs;
2449
2450 /* For EABI, the number of floating-point registers used so far. */
2451 unsigned int num_fprs;
2452
2453 /* The number of words passed on the stack. */
2454 unsigned int stack_words;
2455
2456 /* On the mips16, we need to keep track of which floating point
2457 arguments were passed in general registers, but would have been
2458 passed in the FP regs if this were a 32-bit function, so that we
2459 can move them to the FP regs if we wind up calling a 32-bit
2460 function. We record this information in fp_code, encoded in base
2461 four. A zero digit means no floating point argument, a one digit
2462 means an SFmode argument, and a two digit means a DFmode argument,
2463 and a three digit is not used. The low order digit is the first
2464 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2465 an SFmode argument. ??? A more sophisticated approach will be
2466 needed if MIPS_ABI != ABI_32. */
2467 int fp_code;
2468
2469 /* True if the function has a prototype. */
2470 int prototype;
2471 } CUMULATIVE_ARGS;
2472
2473 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2474 for a call to a function whose data type is FNTYPE.
2475 For a library call, FNTYPE is 0. */
2476
2477 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2478 mips_init_cumulative_args (&CUM, FNTYPE)
2479
2480 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2481 (mips_pad_reg_upward (MODE, TYPE) ? PAD_UPWARD : PAD_DOWNWARD)
2482
2483 /* True if using EABI and varargs can be passed in floating-point
2484 registers. Under these conditions, we need a more complex form
2485 of va_list, which tracks GPR, FPR and stack arguments separately. */
2486 #define EABI_FLOAT_VARARGS_P \
2487 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2488
2489 \f
2490 #define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
2491
2492 /* Treat LOC as a byte offset from the stack pointer and round it up
2493 to the next fully-aligned offset. */
2494 #define MIPS_STACK_ALIGN(LOC) \
2495 (TARGET_NEWABI ? ROUND_UP ((LOC), 16) : ROUND_UP ((LOC), 8))
2496
2497 \f
2498 /* Output assembler code to FILE to increment profiler label # LABELNO
2499 for profiling a function entry. */
2500
2501 #define FUNCTION_PROFILER(FILE, LABELNO) mips_function_profiler ((FILE))
2502
2503 /* The profiler preserves all interesting registers, including $31. */
2504 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2505
2506 /* No mips port has ever used the profiler counter word, so don't emit it
2507 or the label for it. */
2508
2509 #define NO_PROFILE_COUNTERS 1
2510
2511 /* Define this macro if the code for function profiling should come
2512 before the function prologue. Normally, the profiling code comes
2513 after. */
2514
2515 /* #define PROFILE_BEFORE_PROLOGUE */
2516
2517 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2518 the stack pointer does not matter. The value is tested only in
2519 functions that have frame pointers.
2520 No definition is equivalent to always zero. */
2521
2522 #define EXIT_IGNORE_STACK 1
2523
2524 \f
2525 /* Trampolines are a block of code followed by two pointers. */
2526
2527 #define TRAMPOLINE_SIZE \
2528 (mips_trampoline_code_size () + GET_MODE_SIZE (ptr_mode) * 2)
2529
2530 /* Forcing a 64-bit alignment for 32-bit targets allows us to load two
2531 pointers from a single LUI base. */
2532
2533 #define TRAMPOLINE_ALIGNMENT 64
2534
2535 /* mips_trampoline_init calls this library function to flush
2536 program and data caches. */
2537
2538 #ifndef CACHE_FLUSH_FUNC
2539 #define CACHE_FLUSH_FUNC "_flush_cache"
2540 #endif
2541
2542 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2543 /* Flush both caches. We need to flush the data cache in case \
2544 the system has a write-back cache. */ \
2545 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2546 LCT_NORMAL, VOIDmode, ADDR, Pmode, SIZE, Pmode, \
2547 GEN_INT (3), TYPE_MODE (integer_type_node))
2548
2549 \f
2550 /* Addressing modes, and classification of registers for them. */
2551
2552 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2553 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2554 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2555 \f
2556 /* Maximum number of registers that can appear in a valid memory address. */
2557
2558 #define MAX_REGS_PER_ADDRESS 1
2559
2560 /* Check for constness inline but use mips_legitimate_address_p
2561 to check whether a constant really is an address. */
2562
2563 #define CONSTANT_ADDRESS_P(X) \
2564 (CONSTANT_P (X) && memory_address_p (SImode, X))
2565
2566 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2567 'the start of the function that this code is output in'. */
2568
2569 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2570 do { \
2571 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2572 asm_fprintf ((FILE), "%U%s", \
2573 XSTR (XEXP (DECL_RTL (current_function_decl), \
2574 0), 0)); \
2575 else \
2576 asm_fprintf ((FILE), "%U%s", (NAME)); \
2577 } while (0)
2578 \f
2579 /* Flag to mark a function decl symbol that requires a long call. */
2580 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2581 #define SYMBOL_REF_LONG_CALL_P(X) \
2582 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2583
2584 /* This flag marks functions that cannot be lazily bound. */
2585 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2586 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2587 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2588
2589 /* True if we're generating a form of MIPS16 code in which jump tables
2590 are stored in the text section and encoded as 16-bit PC-relative
2591 offsets. This is only possible when general text loads are allowed,
2592 since the table access itself will be an "lh" instruction. If the
2593 PC-relative offsets grow too large, 32-bit offsets are used instead. */
2594 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2595
2596 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2597
2598 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? SImode : ptr_mode)
2599
2600 /* Only use short offsets if their range will not overflow. */
2601 #define CASE_VECTOR_SHORTEN_MODE(MIN, MAX, BODY) \
2602 (!TARGET_MIPS16_SHORT_JUMP_TABLES ? ptr_mode \
2603 : ((MIN) >= -32768 && (MAX) < 32768) ? HImode \
2604 : SImode)
2605
2606 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2607
2608 /* Define this as 1 if `char' should by default be signed; else as 0. */
2609 #ifndef DEFAULT_SIGNED_CHAR
2610 #define DEFAULT_SIGNED_CHAR 1
2611 #endif
2612
2613 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2614 we generally don't want to use them for copying arbitrary data.
2615 A single N-word move is usually the same cost as N single-word moves. */
2616 #define MOVE_MAX UNITS_PER_WORD
2617 /* We don't modify it for MSA as it is only used by the classic reload. */
2618 #define MAX_MOVE_MAX 8
2619
2620 /* Define this macro as a C expression which is nonzero if
2621 accessing less than a word of memory (i.e. a `char' or a
2622 `short') is no faster than accessing a word of memory, i.e., if
2623 such access require more than one instruction or if there is no
2624 difference in cost between byte and (aligned) word loads.
2625
2626 On RISC machines, it tends to generate better code to define
2627 this as 1, since it avoids making a QI or HI mode register.
2628
2629 But, generating word accesses for -mips16 is generally bad as shifts
2630 (often extended) would be needed for byte accesses. */
2631 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2632
2633 /* Standard MIPS integer shifts truncate the shift amount to the
2634 width of the shifted operand. However, Loongson vector shifts
2635 do not truncate the shift amount at all. */
2636 #define SHIFT_COUNT_TRUNCATED (!TARGET_LOONGSON_VECTORS)
2637
2638
2639 /* Specify the machine mode that pointers have.
2640 After generation of rtl, the compiler makes no further distinction
2641 between pointers and any other objects of this machine mode. */
2642
2643 #ifndef Pmode
2644 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2645 #endif
2646
2647 /* Give call MEMs SImode since it is the "most permissive" mode
2648 for both 32-bit and 64-bit targets. */
2649
2650 #define FUNCTION_MODE SImode
2651
2652 \f
2653 /* We allocate $fcc registers by hand and can't cope with moves of
2654 CCmode registers to and from pseudos (or memory). */
2655 #define AVOID_CCMODE_COPIES
2656
2657 /* A C expression for the cost of a branch instruction. A value of
2658 1 is the default; other values are interpreted relative to that. */
2659
2660 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2661 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2662
2663 /* The MIPS port has several functions that return an instruction count.
2664 Multiplying the count by this value gives the number of bytes that
2665 the instructions occupy. */
2666 #define BASE_INSN_LENGTH (TARGET_MIPS16 ? 2 : 4)
2667
2668 /* The length of a NOP in bytes. */
2669 #define NOP_INSN_LENGTH (TARGET_COMPRESSION ? 2 : 4)
2670
2671 /* If defined, modifies the length assigned to instruction INSN as a
2672 function of the context in which it is used. LENGTH is an lvalue
2673 that contains the initially computed length of the insn and should
2674 be updated with the correct length of the insn. */
2675 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2676 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2677
2678 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2679 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2680 its operands. */
2681 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2682 "%*" OPCODE "%?\t" OPERANDS "%/"
2683
2684 #define MIPS_BRANCH_C(OPCODE, OPERANDS) \
2685 "%*" OPCODE "%:\t" OPERANDS
2686
2687 /* Return an asm string that forces INSN to be treated as an absolute
2688 J or JAL instruction instead of an assembler macro. */
2689 #define MIPS_ABSOLUTE_JUMP(INSN) \
2690 (TARGET_ABICALLS_PIC2 \
2691 ? ".option\tpic0\n\t" INSN "\n\t.option\tpic2" \
2692 : INSN)
2693
2694 \f
2695 /* Control the assembler format that we output. */
2696
2697 /* Output to assembler file text saying following lines
2698 may contain character constants, extra white space, comments, etc. */
2699
2700 #ifndef ASM_APP_ON
2701 #define ASM_APP_ON " #APP\n"
2702 #endif
2703
2704 /* Output to assembler file text saying following lines
2705 no longer contain unusual constructs. */
2706
2707 #ifndef ASM_APP_OFF
2708 #define ASM_APP_OFF " #NO_APP\n"
2709 #endif
2710
2711 #define REGISTER_NAMES \
2712 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2713 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2714 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2715 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2716 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2717 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2718 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2719 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2720 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2721 "$fcc5","$fcc6","$fcc7","", "$cprestore", "$arg", "$frame", "$fakec", \
2722 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2723 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2724 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2725 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2726 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2727 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2728 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2729 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2730 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2731 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2732 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2733 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2734 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2735 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2736
2737 /* List the "software" names for each register. Also list the numerical
2738 names for $fp and $sp. */
2739
2740 #define ADDITIONAL_REGISTER_NAMES \
2741 { \
2742 { "$29", 29 + GP_REG_FIRST }, \
2743 { "$30", 30 + GP_REG_FIRST }, \
2744 { "at", 1 + GP_REG_FIRST }, \
2745 { "v0", 2 + GP_REG_FIRST }, \
2746 { "v1", 3 + GP_REG_FIRST }, \
2747 { "a0", 4 + GP_REG_FIRST }, \
2748 { "a1", 5 + GP_REG_FIRST }, \
2749 { "a2", 6 + GP_REG_FIRST }, \
2750 { "a3", 7 + GP_REG_FIRST }, \
2751 { "t0", 8 + GP_REG_FIRST }, \
2752 { "t1", 9 + GP_REG_FIRST }, \
2753 { "t2", 10 + GP_REG_FIRST }, \
2754 { "t3", 11 + GP_REG_FIRST }, \
2755 { "t4", 12 + GP_REG_FIRST }, \
2756 { "t5", 13 + GP_REG_FIRST }, \
2757 { "t6", 14 + GP_REG_FIRST }, \
2758 { "t7", 15 + GP_REG_FIRST }, \
2759 { "s0", 16 + GP_REG_FIRST }, \
2760 { "s1", 17 + GP_REG_FIRST }, \
2761 { "s2", 18 + GP_REG_FIRST }, \
2762 { "s3", 19 + GP_REG_FIRST }, \
2763 { "s4", 20 + GP_REG_FIRST }, \
2764 { "s5", 21 + GP_REG_FIRST }, \
2765 { "s6", 22 + GP_REG_FIRST }, \
2766 { "s7", 23 + GP_REG_FIRST }, \
2767 { "t8", 24 + GP_REG_FIRST }, \
2768 { "t9", 25 + GP_REG_FIRST }, \
2769 { "k0", 26 + GP_REG_FIRST }, \
2770 { "k1", 27 + GP_REG_FIRST }, \
2771 { "gp", 28 + GP_REG_FIRST }, \
2772 { "sp", 29 + GP_REG_FIRST }, \
2773 { "fp", 30 + GP_REG_FIRST }, \
2774 { "ra", 31 + GP_REG_FIRST }, \
2775 { "$w0", 0 + FP_REG_FIRST }, \
2776 { "$w1", 1 + FP_REG_FIRST }, \
2777 { "$w2", 2 + FP_REG_FIRST }, \
2778 { "$w3", 3 + FP_REG_FIRST }, \
2779 { "$w4", 4 + FP_REG_FIRST }, \
2780 { "$w5", 5 + FP_REG_FIRST }, \
2781 { "$w6", 6 + FP_REG_FIRST }, \
2782 { "$w7", 7 + FP_REG_FIRST }, \
2783 { "$w8", 8 + FP_REG_FIRST }, \
2784 { "$w9", 9 + FP_REG_FIRST }, \
2785 { "$w10", 10 + FP_REG_FIRST }, \
2786 { "$w11", 11 + FP_REG_FIRST }, \
2787 { "$w12", 12 + FP_REG_FIRST }, \
2788 { "$w13", 13 + FP_REG_FIRST }, \
2789 { "$w14", 14 + FP_REG_FIRST }, \
2790 { "$w15", 15 + FP_REG_FIRST }, \
2791 { "$w16", 16 + FP_REG_FIRST }, \
2792 { "$w17", 17 + FP_REG_FIRST }, \
2793 { "$w18", 18 + FP_REG_FIRST }, \
2794 { "$w19", 19 + FP_REG_FIRST }, \
2795 { "$w20", 20 + FP_REG_FIRST }, \
2796 { "$w21", 21 + FP_REG_FIRST }, \
2797 { "$w22", 22 + FP_REG_FIRST }, \
2798 { "$w23", 23 + FP_REG_FIRST }, \
2799 { "$w24", 24 + FP_REG_FIRST }, \
2800 { "$w25", 25 + FP_REG_FIRST }, \
2801 { "$w26", 26 + FP_REG_FIRST }, \
2802 { "$w27", 27 + FP_REG_FIRST }, \
2803 { "$w28", 28 + FP_REG_FIRST }, \
2804 { "$w29", 29 + FP_REG_FIRST }, \
2805 { "$w30", 30 + FP_REG_FIRST }, \
2806 { "$w31", 31 + FP_REG_FIRST } \
2807 }
2808
2809 #define DBR_OUTPUT_SEQEND(STREAM) \
2810 do \
2811 { \
2812 /* Undo the effect of '%*'. */ \
2813 mips_pop_asm_switch (&mips_nomacro); \
2814 mips_pop_asm_switch (&mips_noreorder); \
2815 /* Emit a blank line after the delay slot for emphasis. */ \
2816 fputs ("\n", STREAM); \
2817 } \
2818 while (0)
2819
2820 /* The MIPS implementation uses some labels for its own purpose. The
2821 following lists what labels are created, and are all formed by the
2822 pattern $L[a-z].*. The machine independent portion of GCC creates
2823 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2824
2825 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2826 $Lb[0-9]+ Begin blocks for MIPS debug support
2827 $Lc[0-9]+ Label for use in s<xx> operation.
2828 $Le[0-9]+ End blocks for MIPS debug support */
2829
2830 #undef ASM_DECLARE_OBJECT_NAME
2831 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2832 mips_declare_object (STREAM, NAME, "", ":\n")
2833
2834 /* Globalizing directive for a label. */
2835 #define GLOBAL_ASM_OP "\t.globl\t"
2836
2837 /* This says how to define a global common symbol. */
2838
2839 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2840
2841 /* This says how to define a local common symbol (i.e., not visible to
2842 linker). */
2843
2844 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2845 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2846 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2847 #endif
2848
2849 /* This says how to output an external. It would be possible not to
2850 output anything and let undefined symbol become external. However
2851 the assembler uses length information on externals to allocate in
2852 data/sdata bss/sbss, thereby saving exec time. */
2853
2854 #undef ASM_OUTPUT_EXTERNAL
2855 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2856 mips_output_external(STREAM,DECL,NAME)
2857
2858 /* This is how to declare a function name. The actual work of
2859 emitting the label is moved to function_prologue, so that we can
2860 get the line number correctly emitted before the .ent directive,
2861 and after any .file directives. Define as empty so that the function
2862 is not declared before the .ent directive elsewhere. */
2863
2864 #undef ASM_DECLARE_FUNCTION_NAME
2865 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2866
2867 /* This is how to store into the string LABEL
2868 the symbol_ref name of an internal numbered label where
2869 PREFIX is the class of label and NUM is the number within the class.
2870 This is suitable for output with `assemble_name'. */
2871
2872 #undef ASM_GENERATE_INTERNAL_LABEL
2873 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2874 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2875
2876 /* Print debug labels as "foo = ." rather than "foo:" because they should
2877 represent a byte pointer rather than an ISA-encoded address. This is
2878 particularly important for code like:
2879
2880 $LFBxxx = .
2881 .cfi_startproc
2882 ...
2883 .section .gcc_except_table,...
2884 ...
2885 .uleb128 foo-$LFBxxx
2886
2887 The .uleb128 requies $LFBxxx to match the FDE start address, which is
2888 likewise a byte pointer rather than an ISA-encoded address.
2889
2890 At the time of writing, this hook is not used for the function end
2891 label:
2892
2893 $LFExxx:
2894 .end foo
2895
2896 But this doesn't matter, because GAS doesn't treat a pre-.end label
2897 as a MIPS16 one anyway. */
2898
2899 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \
2900 fprintf (FILE, "%s%s%d = .\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
2901
2902 /* This is how to output an element of a case-vector that is absolute. */
2903
2904 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2905 fprintf (STREAM, "\t%s\t%sL%d\n", \
2906 ptr_mode == DImode ? ".dword" : ".word", \
2907 LOCAL_LABEL_PREFIX, \
2908 VALUE)
2909
2910 /* This is how to output an element of a case-vector. We can make the
2911 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2912 is supported. */
2913
2914 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2915 do { \
2916 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2917 { \
2918 if (GET_MODE (BODY) == HImode) \
2919 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2920 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2921 else \
2922 fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n", \
2923 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2924 } \
2925 else if (TARGET_GPWORD) \
2926 fprintf (STREAM, "\t%s\t%sL%d\n", \
2927 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2928 LOCAL_LABEL_PREFIX, VALUE); \
2929 else if (TARGET_RTP_PIC) \
2930 { \
2931 /* Make the entry relative to the start of the function. */ \
2932 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2933 fprintf (STREAM, "\t%s\t%sL%d-", \
2934 Pmode == DImode ? ".dword" : ".word", \
2935 LOCAL_LABEL_PREFIX, VALUE); \
2936 assemble_name (STREAM, XSTR (fnsym, 0)); \
2937 fprintf (STREAM, "\n"); \
2938 } \
2939 else \
2940 fprintf (STREAM, "\t%s\t%sL%d\n", \
2941 ptr_mode == DImode ? ".dword" : ".word", \
2942 LOCAL_LABEL_PREFIX, VALUE); \
2943 } while (0)
2944
2945 /* Mark inline jump tables as data for the purpose of disassembly. For
2946 simplicity embed the jump table's label number in the local symbol
2947 produced so that multiple jump tables within a single function end
2948 up marked with unique symbols. Retain the alignment setting from
2949 `elfos.h' as we are replacing the definition from there. */
2950
2951 #undef ASM_OUTPUT_BEFORE_CASE_LABEL
2952 #define ASM_OUTPUT_BEFORE_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \
2953 do \
2954 { \
2955 ASM_OUTPUT_ALIGN ((STREAM), 2); \
2956 if (JUMP_TABLES_IN_TEXT_SECTION) \
2957 mips_set_text_contents_type (STREAM, "__jump_", NUM, FALSE); \
2958 } \
2959 while (0)
2960
2961 /* Reset text marking to code after an inline jump table. Like with
2962 the beginning of a jump table use the label number to keep symbols
2963 unique. */
2964
2965 #define ASM_OUTPUT_CASE_END(STREAM, NUM, TABLE) \
2966 do \
2967 if (JUMP_TABLES_IN_TEXT_SECTION) \
2968 mips_set_text_contents_type (STREAM, "__jend_", NUM, TRUE); \
2969 while (0)
2970
2971 /* This is how to output an assembler line
2972 that says to advance the location counter
2973 to a multiple of 2**LOG bytes. */
2974
2975 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2976 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2977
2978 /* This is how to output an assembler line to advance the location
2979 counter by SIZE bytes. */
2980
2981 #undef ASM_OUTPUT_SKIP
2982 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2983 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2984
2985 /* This is how to output a string. */
2986 #undef ASM_OUTPUT_ASCII
2987 #define ASM_OUTPUT_ASCII mips_output_ascii
2988
2989 \f
2990 /* Default to -G 8 */
2991 #ifndef MIPS_DEFAULT_GVALUE
2992 #define MIPS_DEFAULT_GVALUE 8
2993 #endif
2994
2995 /* Define the strings to put out for each section in the object file. */
2996 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2997 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2998
2999 #undef READONLY_DATA_SECTION_ASM_OP
3000 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
3001 \f
3002 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3003 do \
3004 { \
3005 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
3006 TARGET_64BIT ? "daddiu" : "addiu", \
3007 reg_names[STACK_POINTER_REGNUM], \
3008 reg_names[STACK_POINTER_REGNUM], \
3009 TARGET_64BIT ? "sd" : "sw", \
3010 reg_names[REGNO], \
3011 reg_names[STACK_POINTER_REGNUM]); \
3012 } \
3013 while (0)
3014
3015 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3016 do \
3017 { \
3018 mips_push_asm_switch (&mips_noreorder); \
3019 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
3020 TARGET_64BIT ? "ld" : "lw", \
3021 reg_names[REGNO], \
3022 reg_names[STACK_POINTER_REGNUM], \
3023 TARGET_64BIT ? "daddu" : "addu", \
3024 reg_names[STACK_POINTER_REGNUM], \
3025 reg_names[STACK_POINTER_REGNUM]); \
3026 mips_pop_asm_switch (&mips_noreorder); \
3027 } \
3028 while (0)
3029
3030 /* How to start an assembler comment.
3031 The leading space is important (the mips native assembler requires it). */
3032 #ifndef ASM_COMMENT_START
3033 #define ASM_COMMENT_START " #"
3034 #endif
3035 \f
3036 #undef SIZE_TYPE
3037 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
3038
3039 #undef PTRDIFF_TYPE
3040 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
3041
3042 /* The minimum alignment of any expanded block move. */
3043 #define MIPS_MIN_MOVE_MEM_ALIGN 16
3044
3045 /* The maximum number of bytes that can be copied by one iteration of
3046 a movmemsi loop; see mips_block_move_loop. */
3047 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
3048 (UNITS_PER_WORD * 4)
3049
3050 /* The maximum number of bytes that can be copied by a straight-line
3051 implementation of movmemsi; see mips_block_move_straight. We want
3052 to make sure that any loop-based implementation will iterate at
3053 least twice. */
3054 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
3055 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
3056
3057 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
3058 values were determined experimentally by benchmarking with CSiBE.
3059 In theory, the call overhead is higher for TARGET_ABICALLS (especially
3060 for o32 where we have to restore $gp afterwards as well as make an
3061 indirect call), but in practice, bumping this up higher for
3062 TARGET_ABICALLS doesn't make much difference to code size. */
3063
3064 #define MIPS_CALL_RATIO 8
3065
3066 /* Any loop-based implementation of movmemsi will have at least
3067 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
3068 moves, so allow individual copies of fewer elements.
3069
3070 When movmemsi is not available, use a value approximating
3071 the length of a memcpy call sequence, so that move_by_pieces
3072 will generate inline code if it is shorter than a function call.
3073 Since move_by_pieces_ninsns counts memory-to-memory moves, but
3074 we'll have to generate a load/store pair for each, halve the
3075 value of MIPS_CALL_RATIO to take that into account. */
3076
3077 #define MOVE_RATIO(speed) \
3078 (HAVE_movmemsi \
3079 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
3080 : MIPS_CALL_RATIO / 2)
3081
3082 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
3083 of the length of a memset call, but use the default otherwise. */
3084
3085 #define CLEAR_RATIO(speed)\
3086 ((speed) ? 15 : MIPS_CALL_RATIO)
3087
3088 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
3089 optimizing for size adjust the ratio to account for the overhead of
3090 loading the constant and replicating it across the word. */
3091
3092 #define SET_RATIO(speed) \
3093 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
3094 \f
3095 /* Since the bits of the _init and _fini function is spread across
3096 many object files, each potentially with its own GP, we must assume
3097 we need to load our GP. We don't preserve $gp or $ra, since each
3098 init/fini chunk is supposed to initialize $gp, and crti/crtn
3099 already take care of preserving $ra and, when appropriate, $gp. */
3100 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3101 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3102 asm (SECTION_OP "\n\
3103 .set push\n\
3104 .set nomips16\n\
3105 .set noreorder\n\
3106 bal 1f\n\
3107 nop\n\
3108 1: .cpload $31\n\
3109 .set reorder\n\
3110 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3111 jalr $25\n\
3112 .set pop\n\
3113 " TEXT_SECTION_ASM_OP);
3114 #elif (defined _ABIN32 && _MIPS_SIM == _ABIN32)
3115 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3116 asm (SECTION_OP "\n\
3117 .set push\n\
3118 .set nomips16\n\
3119 .set noreorder\n\
3120 bal 1f\n\
3121 nop\n\
3122 1: .set reorder\n\
3123 .cpsetup $31, $2, 1b\n\
3124 la $25, " USER_LABEL_PREFIX #FUNC "\n\
3125 jalr $25\n\
3126 .set pop\n\
3127 " TEXT_SECTION_ASM_OP);
3128 #elif (defined _ABI64 && _MIPS_SIM == _ABI64)
3129 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3130 asm (SECTION_OP "\n\
3131 .set push\n\
3132 .set nomips16\n\
3133 .set noreorder\n\
3134 bal 1f\n\
3135 nop\n\
3136 1: .set reorder\n\
3137 .cpsetup $31, $2, 1b\n\
3138 dla $25, " USER_LABEL_PREFIX #FUNC "\n\
3139 jalr $25\n\
3140 .set pop\n\
3141 " TEXT_SECTION_ASM_OP);
3142 #endif
3143
3144 #ifndef HAVE_AS_TLS
3145 #define HAVE_AS_TLS 0
3146 #endif
3147
3148 #ifndef HAVE_AS_NAN
3149 #define HAVE_AS_NAN 0
3150 #endif
3151
3152 #ifndef USED_FOR_TARGET
3153 /* Information about ".set noFOO; ...; .set FOO" blocks. */
3154 struct mips_asm_switch {
3155 /* The FOO in the description above. */
3156 const char *name;
3157
3158 /* The current block nesting level, or 0 if we aren't in a block. */
3159 int nesting_level;
3160 };
3161
3162 extern const enum reg_class mips_regno_to_class[];
3163 extern const char *current_function_file; /* filename current function is in */
3164 extern int num_source_filenames; /* current .file # */
3165 extern struct mips_asm_switch mips_noreorder;
3166 extern struct mips_asm_switch mips_nomacro;
3167 extern struct mips_asm_switch mips_noat;
3168 extern int mips_dbx_regno[];
3169 extern int mips_dwarf_regno[];
3170 extern bool mips_split_p[];
3171 extern bool mips_split_hi_p[];
3172 extern bool mips_use_pcrel_pool_p[];
3173 extern const char *mips_lo_relocs[];
3174 extern const char *mips_hi_relocs[];
3175 extern enum processor mips_arch; /* which cpu to codegen for */
3176 extern enum processor mips_tune; /* which cpu to schedule for */
3177 extern int mips_isa; /* architectural level */
3178 extern int mips_isa_rev;
3179 extern const struct mips_cpu_info *mips_arch_info;
3180 extern const struct mips_cpu_info *mips_tune_info;
3181 extern unsigned int mips_base_compression_flags;
3182 extern GTY(()) struct target_globals *mips16_globals;
3183 extern GTY(()) struct target_globals *micromips_globals;
3184
3185 /* Information about a function's frame layout. */
3186 struct GTY(()) mips_frame_info {
3187 /* The size of the frame in bytes. */
3188 HOST_WIDE_INT total_size;
3189
3190 /* The number of bytes allocated to variables. */
3191 HOST_WIDE_INT var_size;
3192
3193 /* The number of bytes allocated to outgoing function arguments. */
3194 HOST_WIDE_INT args_size;
3195
3196 /* The number of bytes allocated to the .cprestore slot, or 0 if there
3197 is no such slot. */
3198 HOST_WIDE_INT cprestore_size;
3199
3200 /* Bit X is set if the function saves or restores GPR X. */
3201 unsigned int mask;
3202
3203 /* Likewise FPR X. */
3204 unsigned int fmask;
3205
3206 /* Likewise doubleword accumulator X ($acX). */
3207 unsigned int acc_mask;
3208
3209 /* The number of GPRs, FPRs, doubleword accumulators and COP0
3210 registers saved. */
3211 unsigned int num_gp;
3212 unsigned int num_fp;
3213 unsigned int num_acc;
3214 unsigned int num_cop0_regs;
3215
3216 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
3217 save slots from the top of the frame, or zero if no such slots are
3218 needed. */
3219 HOST_WIDE_INT gp_save_offset;
3220 HOST_WIDE_INT fp_save_offset;
3221 HOST_WIDE_INT acc_save_offset;
3222 HOST_WIDE_INT cop0_save_offset;
3223
3224 /* Likewise, but giving offsets from the bottom of the frame. */
3225 HOST_WIDE_INT gp_sp_offset;
3226 HOST_WIDE_INT fp_sp_offset;
3227 HOST_WIDE_INT acc_sp_offset;
3228 HOST_WIDE_INT cop0_sp_offset;
3229
3230 /* Similar, but the value passed to _mcount. */
3231 HOST_WIDE_INT ra_fp_offset;
3232
3233 /* The offset of arg_pointer_rtx from the bottom of the frame. */
3234 HOST_WIDE_INT arg_pointer_offset;
3235
3236 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
3237 HOST_WIDE_INT hard_frame_pointer_offset;
3238 };
3239
3240 /* Enumeration for masked vectored (VI) and non-masked (EIC) interrupts. */
3241 enum mips_int_mask
3242 {
3243 INT_MASK_EIC = -1,
3244 INT_MASK_SW0 = 0,
3245 INT_MASK_SW1 = 1,
3246 INT_MASK_HW0 = 2,
3247 INT_MASK_HW1 = 3,
3248 INT_MASK_HW2 = 4,
3249 INT_MASK_HW3 = 5,
3250 INT_MASK_HW4 = 6,
3251 INT_MASK_HW5 = 7
3252 };
3253
3254 /* Enumeration to mark the existence of the shadow register set.
3255 SHADOW_SET_INTSTACK indicates a shadow register set with a valid stack
3256 pointer. */
3257 enum mips_shadow_set
3258 {
3259 SHADOW_SET_NO,
3260 SHADOW_SET_YES,
3261 SHADOW_SET_INTSTACK
3262 };
3263
3264 struct GTY(()) machine_function {
3265 /* The next floating-point condition-code register to allocate
3266 for ISA_HAS_8CC targets, relative to ST_REG_FIRST. */
3267 unsigned int next_fcc;
3268
3269 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
3270 rtx mips16_gp_pseudo_rtx;
3271
3272 /* The number of extra stack bytes taken up by register varargs.
3273 This area is allocated by the callee at the very top of the frame. */
3274 int varargs_size;
3275
3276 /* The current frame information, calculated by mips_compute_frame_info. */
3277 struct mips_frame_info frame;
3278
3279 /* The register to use as the function's global pointer, or INVALID_REGNUM
3280 if the function doesn't need one. */
3281 unsigned int global_pointer;
3282
3283 /* How many instructions it takes to load a label into $AT, or 0 if
3284 this property hasn't yet been calculated. */
3285 unsigned int load_label_num_insns;
3286
3287 /* True if mips_adjust_insn_length should ignore an instruction's
3288 hazard attribute. */
3289 bool ignore_hazard_length_p;
3290
3291 /* True if the whole function is suitable for .set noreorder and
3292 .set nomacro. */
3293 bool all_noreorder_p;
3294
3295 /* True if the function has "inflexible" and "flexible" references
3296 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
3297 and mips_cfun_has_flexible_gp_ref_p for details. */
3298 bool has_inflexible_gp_insn_p;
3299 bool has_flexible_gp_insn_p;
3300
3301 /* True if the function's prologue must load the global pointer
3302 value into pic_offset_table_rtx and store the same value in
3303 the function's cprestore slot (if any). Even if this value
3304 is currently false, we may decide to set it to true later;
3305 see mips_must_initialize_gp_p () for details. */
3306 bool must_initialize_gp_p;
3307
3308 /* True if the current function must restore $gp after any potential
3309 clobber. This value is only meaningful during the first post-epilogue
3310 split_insns pass; see mips_must_initialize_gp_p () for details. */
3311 bool must_restore_gp_when_clobbered_p;
3312
3313 /* True if this is an interrupt handler. */
3314 bool interrupt_handler_p;
3315
3316 /* Records the way in which interrupts should be masked. Only used if
3317 interrupts are not kept masked. */
3318 enum mips_int_mask int_mask;
3319
3320 /* Records if this is an interrupt handler that uses shadow registers. */
3321 enum mips_shadow_set use_shadow_register_set;
3322
3323 /* True if this is an interrupt handler that should keep interrupts
3324 masked. */
3325 bool keep_interrupts_masked_p;
3326
3327 /* True if this is an interrupt handler that should use DERET
3328 instead of ERET. */
3329 bool use_debug_exception_return_p;
3330
3331 /* True if at least one of the formal parameters to a function must be
3332 written to the frame header (probably so its address can be taken). */
3333 bool does_not_use_frame_header;
3334
3335 /* True if none of the functions that are called by this function need
3336 stack space allocated for their arguments. */
3337 bool optimize_call_stack;
3338
3339 /* True if one of the functions calling this function may not allocate
3340 a frame header. */
3341 bool callers_may_not_allocate_frame;
3342
3343 /* True if GCC stored callee saved registers in the frame header. */
3344 bool use_frame_header_for_callee_saved_regs;
3345 };
3346 #endif
3347
3348 /* Enable querying of DFA units. */
3349 #define CPU_UNITS_QUERY 1
3350
3351 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3352 mips_final_prescan_insn (INSN, OPVEC, NOPERANDS)
3353
3354 /* As on most targets, we want the .eh_frame section to be read-only where
3355 possible. And as on most targets, this means two things:
3356
3357 (a) Non-locally-binding pointers must have an indirect encoding,
3358 so that the addresses in the .eh_frame section itself become
3359 locally-binding.
3360
3361 (b) A shared library's .eh_frame section must encode locally-binding
3362 pointers in a relative (relocation-free) form.
3363
3364 However, MIPS has traditionally not allowed directives like:
3365
3366 .long x-.
3367
3368 in cases where "x" is in a different section, or is not defined in the
3369 same assembly file. We are therefore unable to emit the PC-relative
3370 form required by (b) at assembly time.
3371
3372 Fortunately, the linker is able to convert absolute addresses into
3373 PC-relative addresses on our behalf. Unfortunately, only certain
3374 versions of the linker know how to do this for indirect pointers,
3375 and for personality data. We must fall back on using writable
3376 .eh_frame sections for shared libraries if the linker does not
3377 support this feature. */
3378 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
3379 (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_absptr)
3380
3381 /* For switching between MIPS16 and non-MIPS16 modes. */
3382 #define SWITCHABLE_TARGET 1
3383
3384 /* Several named MIPS patterns depend on Pmode. These patterns have the
3385 form <NAME>_si for Pmode == SImode and <NAME>_di for Pmode == DImode.
3386 Add the appropriate suffix to generator function NAME and invoke it
3387 with arguments ARGS. */
3388 #define PMODE_INSN(NAME, ARGS) \
3389 (Pmode == SImode ? NAME ## _si ARGS : NAME ## _di ARGS)
3390
3391 /* If we are *not* using multilibs and the default ABI is not ABI_32 we
3392 need to change these from /lib and /usr/lib. */
3393 #if MIPS_ABI_DEFAULT == ABI_N32
3394 #define STANDARD_STARTFILE_PREFIX_1 "/lib32/"
3395 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib32/"
3396 #elif MIPS_ABI_DEFAULT == ABI_64
3397 #define STANDARD_STARTFILE_PREFIX_1 "/lib64/"
3398 #define STANDARD_STARTFILE_PREFIX_2 "/usr/lib64/"
3399 #endif
3400
3401 /* Load store bonding is not supported by micromips and fix_24k. The
3402 performance can be degraded for those targets. Hence, do not bond for
3403 micromips or fix_24k. */
3404 #define ENABLE_LD_ST_PAIRS \
3405 (TARGET_LOAD_STORE_PAIRS && (TUNE_P5600 || TUNE_I6400) \
3406 && !TARGET_MICROMIPS && !TARGET_FIX_24K)
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