gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2018 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include "config/riscv/riscv-opts.h"
  26
  27 /* Target CPU builtins.  */
  28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  29
  30 /* Default target_flags if no switches are specified  */
  31
  32 #ifndef TARGET_DEFAULT
  33 #define TARGET_DEFAULT 0
  34 #endif
  35
  36 #ifndef RISCV_TUNE_STRING_DEFAULT
  37 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  38 #endif
  39
  40 /* Support for a compile-time default CPU, et cetera.  The rules are:
  41    --with-arch is ignored if -march is specified.
  42    --with-abi is ignored if -mabi is specified.
  43    --with-tune is ignored if -mtune is specified.  */
  44 #define OPTION_DEFAULT_SPECS \
  45   {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  46   {"arch", "%{!march=*:-march=%(VALUE)}" }, \
  47   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  48
  49 #ifdef IN_LIBGCC2
  50 #undef TARGET_64BIT
  51 /* Make this compile time constant for libgcc2 */
  52 #define TARGET_64BIT           (__riscv_xlen == 64)
  53 #endif /* IN_LIBGCC2 */
  54
  55 #undef ASM_SPEC
  56 #define ASM_SPEC "\
  57 %(subtarget_asm_debugging_spec) \
  58 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
  59 %{march=*} \
  60 %{mabi=*} \
  61 %(subtarget_asm_spec)"
  62
  63 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
  64
  65 #define LOCAL_LABEL_PREFIX      "."
  66 #define USER_LABEL_PREFIX       ""
  67
  68 /* Offsets recorded in opcodes are a multiple of this alignment factor.
  69    The default for this in 64-bit mode is 8, which causes problems with
  70    SFmode register saves.  */
  71 #define DWARF_CIE_DATA_ALIGNMENT -4
  72
  73 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
  74 #define DWARF_FRAME_REGNUM(REGNO) \
  75   (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
  76
  77 /* The DWARF 2 CFA column which tracks the return address.  */
  78 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
  79 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
  80
  81 /* Describe how we implement __builtin_eh_return.  */
  82 #define EH_RETURN_DATA_REGNO(N) \
  83   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
  84
  85 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
  86
  87 /* Target machine storage layout */
  88
  89 #define BITS_BIG_ENDIAN 0
  90 #define BYTES_BIG_ENDIAN 0
  91 #define WORDS_BIG_ENDIAN 0
  92
  93 #define MAX_BITS_PER_WORD 64
  94
  95 /* Width of a word, in units (bytes).  */
  96 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
  97 #ifndef IN_LIBGCC2
  98 #define MIN_UNITS_PER_WORD 4
  99 #endif
 100
 101 /* The `Q' extension is not yet supported.  */
 102 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 103
 104 /* The largest type that can be passed in floating-point registers.  */
 105 #define UNITS_PER_FP_ARG                                        \
 106   (riscv_abi == ABI_ILP32 || riscv_abi == ABI_LP64 ? 0 :        \
 107    riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F ? 4 : 8)   \
 108
 109 /* Set the sizes of the core types.  */
 110 #define SHORT_TYPE_SIZE 16
 111 #define INT_TYPE_SIZE 32
 112 #define LONG_LONG_TYPE_SIZE 64
 113 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 114 #define LONG_TYPE_SIZE POINTER_SIZE
 115
 116 #define FLOAT_TYPE_SIZE 32
 117 #define DOUBLE_TYPE_SIZE 64
 118 #define LONG_DOUBLE_TYPE_SIZE 128
 119
 120 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 121 #define PARM_BOUNDARY BITS_PER_WORD
 122
 123 /* Allocation boundary (in *bits*) for the code of a function.  */
 124 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 125
 126 /* The smallest supported stack boundary the calling convention supports.  */
 127 #define MIN_STACK_BOUNDARY (2 * BITS_PER_WORD)
 128
 129 /* The ABI stack alignment.  */
 130 #define ABI_STACK_BOUNDARY 128
 131
 132 /* There is no point aligning anything to a rounder boundary than this.  */
 133 #define BIGGEST_ALIGNMENT STACK_BOUNDARY
 134
 135 /* The user-level ISA permits unaligned accesses, but they are not required
 136    of the privileged architecture.  */
 137 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 138
 139 /* Define this if you wish to imitate the way many other C compilers
 140    handle alignment of bitfields and the structures that contain
 141    them.
 142
 143    The behavior is that the type written for a bit-field (`int',
 144    `short', or other integer type) imposes an alignment for the
 145    entire structure, as if the structure really did contain an
 146    ordinary field of that type.  In addition, the bit-field is placed
 147    within the structure so that it would fit within such a field,
 148    not crossing a boundary for it.
 149
 150    Thus, on most machines, a bit-field whose type is written as `int'
 151    would not cross a four-byte boundary, and would force four-byte
 152    alignment for the whole structure.  (The alignment used may not
 153    be four bytes; it is controlled by the other alignment
 154    parameters.)
 155
 156    If the macro is defined, its definition should be a C expression;
 157    a nonzero value for the expression enables this behavior.  */
 158
 159 #define PCC_BITFIELD_TYPE_MATTERS 1
 160
 161 /* If defined, a C expression to compute the alignment for a static
 162    variable.  TYPE is the data type, and ALIGN is the alignment that
 163    the object would ordinarily have.  The value of this macro is used
 164    instead of that alignment to align the object.
 165
 166    If this macro is not defined, then ALIGN is used.
 167
 168    One use of this macro is to increase alignment of medium-size
 169    data to make it all fit in fewer cache lines.  Another is to
 170    cause character arrays to be word-aligned so that `strcpy' calls
 171    that copy constants to character arrays can be done inline.  */
 172
 173 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 174   ((((ALIGN) < BITS_PER_WORD)                                           \
 175     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 176         || TREE_CODE (TYPE) == UNION_TYPE                               \
 177         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 178
 179 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 180    character arrays to be word-aligned so that `strcpy' calls that copy
 181    constants to character arrays can be done inline, and 'strcmp' can be
 182    optimised to use word loads. */
 183 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 184   DATA_ALIGNMENT (TYPE, ALIGN)
 185
 186 /* Define if operations between registers always perform the operation
 187    on the full register even if a narrower mode is specified.  */
 188 #define WORD_REGISTER_OPERATIONS 1
 189
 190 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 191    moves.  All other references are zero extended.  */
 192 #define LOAD_EXTEND_OP(MODE) \
 193   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 194
 195 /* Define this macro if it is advisable to hold scalars in registers
 196    in a wider mode than that declared by the program.  In such cases,
 197    the value is constrained to be within the bounds of the declared
 198    type, but kept valid in the wider mode.  The signedness of the
 199    extension may differ from that of the type.  */
 200
 201 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 202   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 203       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 204     {                                           \
 205       if ((MODE) == SImode)                     \
 206         (UNSIGNEDP) = 0;                        \
 207       (MODE) = word_mode;                       \
 208     }
 209
 210 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 211    Extensions of pointers to word_mode must be signed.  */
 212 #define POINTERS_EXTEND_UNSIGNED false
 213
 214 /* Define if loading short immediate values into registers sign extends.  */
 215 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 216
 217 /* Standard register usage.  */
 218
 219 /* Number of hardware registers.  We have:
 220
 221    - 32 integer registers
 222    - 32 floating point registers
 223    - 2 fake registers:
 224         - ARG_POINTER_REGNUM
 225         - FRAME_POINTER_REGNUM */
 226
 227 #define FIRST_PSEUDO_REGISTER 66
 228
 229 /* x0, sp, gp, and tp are fixed.  */
 230
 231 #define FIXED_REGISTERS                                                 \
 232 { /* General registers.  */                                             \
 233   1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 234   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 235   /* Floating-point registers.  */                                      \
 236   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 237   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 238   /* Others.  */                                                        \
 239   1, 1                                                                  \
 240 }
 241
 242 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 243    The call RTLs themselves clobber ra.  */
 244
 245 #define CALL_USED_REGISTERS                                             \
 246 { /* General registers.  */                                             \
 247   1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 248   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 249   /* Floating-point registers.  */                                      \
 250   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 251   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 252   /* Others.  */                                                        \
 253   1, 1                                                                  \
 254 }
 255
 256 /* Internal macros to classify an ISA register's type.  */
 257
 258 #define GP_REG_FIRST 0
 259 #define GP_REG_LAST  31
 260 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 261
 262 #define FP_REG_FIRST 32
 263 #define FP_REG_LAST  63
 264 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 265
 266 /* The DWARF 2 CFA column which tracks the return address from a
 267    signal handler context.  This means that to maintain backwards
 268    compatibility, no hard register can be assigned this column if it
 269    would need to be handled by the DWARF unwinder.  */
 270 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 271
 272 #define GP_REG_P(REGNO) \
 273   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 274 #define FP_REG_P(REGNO)  \
 275   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 276
 277 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 278
 279 /* Use s0 as the frame pointer if it is so requested.  */
 280 #define HARD_FRAME_POINTER_REGNUM 8
 281 #define STACK_POINTER_REGNUM 2
 282 #define THREAD_POINTER_REGNUM 4
 283
 284 /* These two registers don't really exist: they get eliminated to either
 285    the stack or hard frame pointer.  */
 286 #define ARG_POINTER_REGNUM 64
 287 #define FRAME_POINTER_REGNUM 65
 288
 289 /* Register in which static-chain is passed to a function.  */
 290 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 291
 292 /* Registers used as temporaries in prologue/epilogue code.
 293
 294    The prologue registers mustn't conflict with any
 295    incoming arguments, the static chain pointer, or the frame pointer.
 296    The epilogue temporary mustn't conflict with the return registers,
 297    the frame pointer, the EH stack adjustment, or the EH data registers. */
 298
 299 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 300 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 301
 302 #define MCOUNT_NAME "_mcount"
 303
 304 #define NO_PROFILE_COUNTERS 1
 305
 306 /* Emit rtl for profiling.  Output assembler code to FILE
 307    to call "_mcount" for profiling a function entry.  */
 308 #define PROFILE_HOOK(LABEL)                                             \
 309   {                                                                     \
 310     rtx fun, ra;                                                        \
 311     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 312     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 313     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 314   }
 315
 316 /* All the work done in PROFILE_HOOK, but still required.  */
 317 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 318
 319 /* Define this macro if it is as good or better to call a constant
 320    function address than to call an address kept in a register.  */
 321 #define NO_FUNCTION_CSE 1
 322
 323 /* Define the classes of registers for register constraints in the
 324    machine description.  Also define ranges of constants.
 325
 326    One of the classes must always be named ALL_REGS and include all hard regs.
 327    If there is more than one class, another class must be named NO_REGS
 328    and contain no registers.
 329
 330    The name GENERAL_REGS must be the name of a class (or an alias for
 331    another name such as ALL_REGS).  This is the class of registers
 332    that is allowed by "g" or "r" in a register constraint.
 333    Also, registers outside this class are allocated only when
 334    instructions express preferences for them.
 335
 336    The classes must be numbered in nondecreasing order; that is,
 337    a larger-numbered class must never be contained completely
 338    in a smaller-numbered class.
 339
 340    For any two classes, it is very desirable that there be another
 341    class that represents their union.  */
 342
 343 enum reg_class
 344 {
 345   NO_REGS,                      /* no registers in set */
 346   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 347   JALR_REGS,                    /* registers used by indirect calls */
 348   GR_REGS,                      /* integer registers */
 349   FP_REGS,                      /* floating-point registers */
 350   FRAME_REGS,                   /* arg pointer and frame pointer */
 351   ALL_REGS,                     /* all registers */
 352   LIM_REG_CLASSES               /* max value + 1 */
 353 };
 354
 355 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 356
 357 #define GENERAL_REGS GR_REGS
 358
 359 /* An initializer containing the names of the register classes as C
 360    string constants.  These names are used in writing some of the
 361    debugging dumps.  */
 362
 363 #define REG_CLASS_NAMES                                                 \
 364 {                                                                       \
 365   "NO_REGS",                                                            \
 366   "SIBCALL_REGS",                                                       \
 367   "JALR_REGS",                                                          \
 368   "GR_REGS",                                                            \
 369   "FP_REGS",                                                            \
 370   "FRAME_REGS",                                                         \
 371   "ALL_REGS"                                                            \
 372 }
 373
 374 /* An initializer containing the contents of the register classes,
 375    as integers which are bit masks.  The Nth integer specifies the
 376    contents of class N.  The way the integer MASK is interpreted is
 377    that register R is in the class if `MASK & (1 << R)' is 1.
 378
 379    When the machine has more than 32 registers, an integer does not
 380    suffice.  Then the integers are replaced by sub-initializers,
 381    braced groupings containing several integers.  Each
 382    sub-initializer must be suitable as an initializer for the type
 383    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 384
 385 #define REG_CLASS_CONTENTS                                              \
 386 {                                                                       \
 387   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 388   { 0xf00000c0, 0x00000000, 0x00000000 },       /* SIBCALL_REGS */      \
 389   { 0xffffffc0, 0x00000000, 0x00000000 },       /* JALR_REGS */         \
 390   { 0xffffffff, 0x00000000, 0x00000000 },       /* GR_REGS */           \
 391   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS */           \
 392   { 0x00000000, 0x00000000, 0x00000003 },       /* FRAME_REGS */        \
 393   { 0xffffffff, 0xffffffff, 0x00000003 }        /* ALL_REGS */          \
 394 }
 395
 396 /* A C expression whose value is a register class containing hard
 397    register REGNO.  In general there is more that one such class;
 398    choose a class which is "minimal", meaning that no smaller class
 399    also contains the register.  */
 400
 401 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 402
 403 /* A macro whose definition is the name of the class to which a
 404    valid base register must belong.  A base register is one used in
 405    an address which is the register value plus a displacement.  */
 406
 407 #define BASE_REG_CLASS GR_REGS
 408
 409 /* A macro whose definition is the name of the class to which a
 410    valid index register must belong.  An index register is one used
 411    in an address where its value is either multiplied by a scale
 412    factor or added to another register (as well as added to a
 413    displacement).  */
 414
 415 #define INDEX_REG_CLASS NO_REGS
 416
 417 /* We generally want to put call-clobbered registers ahead of
 418    call-saved ones.  (IRA expects this.)  */
 419
 420 #define REG_ALLOC_ORDER                                                 \
 421 { \
 422   /* Call-clobbered GPRs.  */                                           \
 423   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 424   /* Call-saved GPRs.  */                                               \
 425   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 426   /* GPRs that can never be exposed to the register allocator.  */      \
 427   0, 2, 3, 4,                                                           \
 428   /* Call-clobbered FPRs.  */                                           \
 429   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 430   60, 61, 62, 63,                                                       \
 431   /* Call-saved FPRs.  */                                               \
 432   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 433   /* None of the remaining classes have defined call-saved              \
 434      registers.  */                                                     \
 435   64, 65                                                                \
 436 }
 437
 438 /* True if VALUE is a signed 12-bit number.  */
 439
 440 #define SMALL_OPERAND(VALUE) \
 441   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 442
 443 /* True if VALUE can be loaded into a register using LUI.  */
 444
 445 #define LUI_OPERAND(VALUE)                                              \
 446   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 447    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 448
 449 /* Stack layout; function entry, exit and calling.  */
 450
 451 #define STACK_GROWS_DOWNWARD 1
 452
 453 #define FRAME_GROWS_DOWNWARD 1
 454
 455 #define RETURN_ADDR_RTX riscv_return_addr
 456
 457 #define ELIMINABLE_REGS                                                 \
 458 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 459  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 460  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 461  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 462
 463 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 464   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 465
 466 /* Allocate stack space for arguments at the beginning of each function.  */
 467 #define ACCUMULATE_OUTGOING_ARGS 1
 468
 469 /* The argument pointer always points to the first argument.  */
 470 #define FIRST_PARM_OFFSET(FNDECL) 0
 471
 472 #define REG_PARM_STACK_SPACE(FNDECL) 0
 473
 474 /* Define this if it is the responsibility of the caller to
 475    allocate the area reserved for arguments passed in registers.
 476    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 477    of this macro is to determine whether the space is included in
 478    `crtl->outgoing_args_size'.  */
 479 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 480
 481 #define STACK_BOUNDARY riscv_stack_boundary
 482
 483 /* Symbolic macros for the registers used to return integer and floating
 484    point values.  */
 485
 486 #define GP_RETURN GP_ARG_FIRST
 487 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 488
 489 #define MAX_ARGS_IN_REGISTERS 8
 490
 491 /* Symbolic macros for the first/last argument registers.  */
 492
 493 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 494 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 495 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 496 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 497 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 498
 499 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 500   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 501    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 502
 503 #define LIBCALL_VALUE(MODE) \
 504   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 505
 506 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 507   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 508
 509 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 510
 511 /* 1 if N is a possible register number for function argument passing.
 512    We have no FP argument registers when soft-float.  When FP registers
 513    are 32 bits, we can't directly reference the odd numbered ones.  */
 514
 515 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 516 #define FUNCTION_ARG_REGNO_P(N)                                         \
 517   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 518    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 519
 520 typedef struct {
 521   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 522   unsigned int num_gprs;
 523
 524   /* Number of floating-point registers used so far, likewise.  */
 525   unsigned int num_fprs;
 526 } CUMULATIVE_ARGS;
 527
 528 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 529    for a call to a function whose data type is FNTYPE.
 530    For a library call, FNTYPE is 0.  */
 531
 532 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 533   memset (&(CUM), 0, sizeof (CUM))
 534
 535 #define EPILOGUE_USES(REGNO)    ((REGNO) == RETURN_ADDR_REGNUM)
 536
 537 /* Align based on stack boundary, which might have been set by the user.  */
 538 #define RISCV_STACK_ALIGN(LOC) \
 539   (((LOC) + ((STACK_BOUNDARY/8)-1)) & -(STACK_BOUNDARY/8))
 540
 541 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 542    the stack pointer does not matter.  The value is tested only in
 543    functions that have frame pointers.
 544    No definition is equivalent to always zero.  */
 545
 546 #define EXIT_IGNORE_STACK 1
 547
 548
 549 /* Trampolines are a block of code followed by two pointers.  */
 550
 551 #define TRAMPOLINE_CODE_SIZE 16
 552 #define TRAMPOLINE_SIZE         \
 553   ((Pmode == SImode)            \
 554    ? TRAMPOLINE_CODE_SIZE       \
 555    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 556 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 557
 558 /* Addressing modes, and classification of registers for them.  */
 559
 560 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 561 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 562   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 563
 564 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 565    and check its validity for a certain class.
 566    We have two alternate definitions for each of them.
 567    The usual definition accepts all pseudo regs; the other rejects them all.
 568    The symbol REG_OK_STRICT causes the latter definition to be used.
 569
 570    Most source files want to accept pseudo regs in the hope that
 571    they will get allocated to the class that the insn wants them to be in.
 572    Some source files that are used after register allocation
 573    need to be strict.  */
 574
 575 #ifndef REG_OK_STRICT
 576 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 577   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 578 #else
 579 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 580   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 581 #endif
 582
 583 #define REG_OK_FOR_INDEX_P(X) 0
 584
 585 /* Maximum number of registers that can appear in a valid memory address.  */
 586
 587 #define MAX_REGS_PER_ADDRESS 1
 588
 589 #define CONSTANT_ADDRESS_P(X) \
 590   (CONSTANT_P (X) && memory_address_p (SImode, X))
 591
 592 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 593    'the start of the function that this code is output in'.  */
 594
 595 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 596   do {                                                                  \
 597     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 598       asm_fprintf ((FILE), "%U%s",                                      \
 599                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 600                                0), 0));                                 \
 601     else                                                                \
 602       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 603   } while (0)
 604
 605 #define JUMP_TABLES_IN_TEXT_SECTION 0
 606 #define CASE_VECTOR_MODE SImode
 607 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 608
 609 /* The load-address macro is used for PC-relative addressing of symbols
 610    that bind locally.  Don't use it for symbols that should be addressed
 611    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 612    currently results in more opportunities for linker relaxation.  */
 613 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 614   (!TARGET_EXPLICIT_RELOCS &&                                           \
 615    ((flag_pic                                                           \
 616      && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))               \
 617          || ((GET_CODE (sym) == CONST)                                  \
 618              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 619              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))))          \
 620      || riscv_cmodel == CM_MEDANY))
 621
 622 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 623 #define DEFAULT_SIGNED_CHAR 0
 624
 625 #define MOVE_MAX UNITS_PER_WORD
 626 #define MAX_MOVE_MAX 8
 627
 628 /* The SPARC port says:
 629    Nonzero if access to memory by bytes is slow and undesirable.
 630    For RISC chips, it means that access to memory by bytes is no
 631    better than access by words when possible, so grab a whole word
 632    and maybe make use of that.  */
 633 #define SLOW_BYTE_ACCESS 1
 634
 635 #define SHIFT_COUNT_TRUNCATED 1
 636
 637 /* Specify the machine mode that pointers have.
 638    After generation of rtl, the compiler makes no further distinction
 639    between pointers and any other objects of this machine mode.  */
 640
 641 #define Pmode word_mode
 642
 643 /* Give call MEMs SImode since it is the "most permissive" mode
 644    for both 32-bit and 64-bit targets.  */
 645
 646 #define FUNCTION_MODE SImode
 647
 648 /* A C expression for the cost of a branch instruction.  A value of 2
 649    seems to minimize code size.  */
 650
 651 #define BRANCH_COST(speed_p, predictable_p) \
 652   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 653
 654 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 655
 656 /* Control the assembler format that we output.  */
 657
 658 /* Output to assembler file text saying following lines
 659    may contain character constants, extra white space, comments, etc.  */
 660
 661 #ifndef ASM_APP_ON
 662 #define ASM_APP_ON " #APP\n"
 663 #endif
 664
 665 /* Output to assembler file text saying following lines
 666    no longer contain unusual constructs.  */
 667
 668 #ifndef ASM_APP_OFF
 669 #define ASM_APP_OFF " #NO_APP\n"
 670 #endif
 671
 672 #define REGISTER_NAMES                                          \
 673 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 674   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 675   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 676   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 677   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 678   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 679   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 680   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 681   "arg", "frame", }
 682
 683 #define ADDITIONAL_REGISTER_NAMES                                       \
 684 {                                                                       \
 685   { "x0",        0 + GP_REG_FIRST },                                    \
 686   { "x1",        1 + GP_REG_FIRST },                                    \
 687   { "x2",        2 + GP_REG_FIRST },                                    \
 688   { "x3",        3 + GP_REG_FIRST },                                    \
 689   { "x4",        4 + GP_REG_FIRST },                                    \
 690   { "x5",        5 + GP_REG_FIRST },                                    \
 691   { "x6",        6 + GP_REG_FIRST },                                    \
 692   { "x7",        7 + GP_REG_FIRST },                                    \
 693   { "x8",        8 + GP_REG_FIRST },                                    \
 694   { "x9",        9 + GP_REG_FIRST },                                    \
 695   { "x10",      10 + GP_REG_FIRST },                                    \
 696   { "x11",      11 + GP_REG_FIRST },                                    \
 697   { "x12",      12 + GP_REG_FIRST },                                    \
 698   { "x13",      13 + GP_REG_FIRST },                                    \
 699   { "x14",      14 + GP_REG_FIRST },                                    \
 700   { "x15",      15 + GP_REG_FIRST },                                    \
 701   { "x16",      16 + GP_REG_FIRST },                                    \
 702   { "x17",      17 + GP_REG_FIRST },                                    \
 703   { "x18",      18 + GP_REG_FIRST },                                    \
 704   { "x19",      19 + GP_REG_FIRST },                                    \
 705   { "x20",      20 + GP_REG_FIRST },                                    \
 706   { "x21",      21 + GP_REG_FIRST },                                    \
 707   { "x22",      22 + GP_REG_FIRST },                                    \
 708   { "x23",      23 + GP_REG_FIRST },                                    \
 709   { "x24",      24 + GP_REG_FIRST },                                    \
 710   { "x25",      25 + GP_REG_FIRST },                                    \
 711   { "x26",      26 + GP_REG_FIRST },                                    \
 712   { "x27",      27 + GP_REG_FIRST },                                    \
 713   { "x28",      28 + GP_REG_FIRST },                                    \
 714   { "x29",      29 + GP_REG_FIRST },                                    \
 715   { "x30",      30 + GP_REG_FIRST },                                    \
 716   { "x31",      31 + GP_REG_FIRST },                                    \
 717   { "f0",        0 + FP_REG_FIRST },                                    \
 718   { "f1",        1 + FP_REG_FIRST },                                    \
 719   { "f2",        2 + FP_REG_FIRST },                                    \
 720   { "f3",        3 + FP_REG_FIRST },                                    \
 721   { "f4",        4 + FP_REG_FIRST },                                    \
 722   { "f5",        5 + FP_REG_FIRST },                                    \
 723   { "f6",        6 + FP_REG_FIRST },                                    \
 724   { "f7",        7 + FP_REG_FIRST },                                    \
 725   { "f8",        8 + FP_REG_FIRST },                                    \
 726   { "f9",        9 + FP_REG_FIRST },                                    \
 727   { "f10",      10 + FP_REG_FIRST },                                    \
 728   { "f11",      11 + FP_REG_FIRST },                                    \
 729   { "f12",      12 + FP_REG_FIRST },                                    \
 730   { "f13",      13 + FP_REG_FIRST },                                    \
 731   { "f14",      14 + FP_REG_FIRST },                                    \
 732   { "f15",      15 + FP_REG_FIRST },                                    \
 733   { "f16",      16 + FP_REG_FIRST },                                    \
 734   { "f17",      17 + FP_REG_FIRST },                                    \
 735   { "f18",      18 + FP_REG_FIRST },                                    \
 736   { "f19",      19 + FP_REG_FIRST },                                    \
 737   { "f20",      20 + FP_REG_FIRST },                                    \
 738   { "f21",      21 + FP_REG_FIRST },                                    \
 739   { "f22",      22 + FP_REG_FIRST },                                    \
 740   { "f23",      23 + FP_REG_FIRST },                                    \
 741   { "f24",      24 + FP_REG_FIRST },                                    \
 742   { "f25",      25 + FP_REG_FIRST },                                    \
 743   { "f26",      26 + FP_REG_FIRST },                                    \
 744   { "f27",      27 + FP_REG_FIRST },                                    \
 745   { "f28",      28 + FP_REG_FIRST },                                    \
 746   { "f29",      29 + FP_REG_FIRST },                                    \
 747   { "f30",      30 + FP_REG_FIRST },                                    \
 748   { "f31",      31 + FP_REG_FIRST },                                    \
 749 }
 750
 751 /* Globalizing directive for a label.  */
 752 #define GLOBAL_ASM_OP "\t.globl\t"
 753
 754 /* This is how to store into the string LABEL
 755    the symbol_ref name of an internal numbered label where
 756    PREFIX is the class of label and NUM is the number within the class.
 757    This is suitable for output with `assemble_name'.  */
 758
 759 #undef ASM_GENERATE_INTERNAL_LABEL
 760 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 761   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 762
 763 /* This is how to output an element of a case-vector that is absolute.  */
 764
 765 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 766   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
 767
 768 /* This is how to output an element of a PIC case-vector. */
 769
 770 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 771   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
 772            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
 773
 774 /* This is how to output an assembler line
 775    that says to advance the location counter
 776    to a multiple of 2**LOG bytes.  */
 777
 778 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 779   fprintf (STREAM, "\t.align\t%d\n", (LOG))
 780
 781 /* Define the strings to put out for each section in the object file.  */
 782 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
 783 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
 784 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
 785 #define BSS_SECTION_ASM_OP      "\t.bss"
 786 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
 787 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
 788
 789 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
 790 do                                                                      \
 791   {                                                                     \
 792     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
 793              reg_names[STACK_POINTER_REGNUM],                           \
 794              reg_names[STACK_POINTER_REGNUM],                           \
 795              TARGET_64BIT ? "sd" : "sw",                                \
 796              reg_names[REGNO],                                          \
 797              reg_names[STACK_POINTER_REGNUM]);                          \
 798   }                                                                     \
 799 while (0)
 800
 801 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
 802 do                                                                      \
 803   {                                                                     \
 804     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
 805              TARGET_64BIT ? "ld" : "lw",                                \
 806              reg_names[REGNO],                                          \
 807              reg_names[STACK_POINTER_REGNUM],                           \
 808              reg_names[STACK_POINTER_REGNUM],                           \
 809              reg_names[STACK_POINTER_REGNUM]);                          \
 810   }                                                                     \
 811 while (0)
 812
 813 #define ASM_COMMENT_START "#"
 814
 815 #undef SIZE_TYPE
 816 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
 817
 818 #undef PTRDIFF_TYPE
 819 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
 820
 821 /* The maximum number of bytes copied by one iteration of a movmemsi loop.  */
 822
 823 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
 824
 825 /* The maximum number of bytes that can be copied by a straight-line
 826    movmemsi implementation.  */
 827
 828 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
 829
 830 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 831    move-instruction pairs, we will do a movmem or libcall instead.
 832    Do not use move_by_pieces at all when strict alignment is not
 833    in effect but the target has slow unaligned accesses; in this
 834    case, movmem or libcall is more efficient.  */
 835
 836 #define MOVE_RATIO(speed)                                               \
 837   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
 838    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
 839    CLEAR_RATIO (speed) / 2)
 840
 841 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 842    of the length of a memset call, but use the default otherwise.  */
 843
 844 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
 845
 846 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
 847    optimizing for size adjust the ratio to account for the overhead of
 848    loading the constant and replicating it across the word.  */
 849
 850 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
 851
 852 #ifndef USED_FOR_TARGET
 853 extern const enum reg_class riscv_regno_to_class[];
 854 extern bool riscv_slow_unaligned_access_p;
 855 extern unsigned riscv_stack_boundary;
 856 #endif
 857
 858 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 859   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 860
 861 #define XLEN_SPEC \
 862   "%{march=rv32*:32}" \
 863   "%{march=rv64*:64}" \
 864
 865 #define ABI_SPEC \
 866   "%{mabi=ilp32:ilp32}" \
 867   "%{mabi=ilp32f:ilp32f}" \
 868   "%{mabi=ilp32d:ilp32d}" \
 869   "%{mabi=lp64:lp64}" \
 870   "%{mabi=lp64f:lp64f}" \
 871   "%{mabi=lp64d:lp64d}" \
 872
 873 #define STARTFILE_PREFIX_SPEC                   \
 874    "/lib" XLEN_SPEC "/" ABI_SPEC "/ "           \
 875    "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ "       \
 876    "/lib/ "                                     \
 877    "/usr/lib/ "
 878
 879 /* ISA constants needed for code generation.  */
 880 #define OPCODE_LW    0x2003
 881 #define OPCODE_LD    0x3003
 882 #define OPCODE_AUIPC 0x17
 883 #define OPCODE_JALR  0x67
 884 #define OPCODE_LUI   0x37
 885 #define OPCODE_ADDI  0x13
 886 #define SHIFT_RD  7
 887 #define SHIFT_RS1 15
 888 #define SHIFT_IMM 20
 889 #define IMM_BITS 12
 890
 891 #define IMM_REACH (1LL << IMM_BITS)
 892 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
 893 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
 894
 895 #endif /* ! GCC_RISCV_H */