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2014-03-25 Richard Biener <rguenther@suse.de>
[official-gcc.git] / gcc / config / sh / sh.h
blob8819300116e2b18b702bad1b896e3c319b906dfc
1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 #ifndef GCC_SH_H
23 #define GCC_SH_H
24
25 #include "config/vxworks-dummy.h"
26
27 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
28 include it here, because bconfig.h is also included by gencodes.c . */
29 /* ??? No longer true. */
30 extern int code_for_indirect_jump_scratch;
31
32 #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
33
34 /* Value should be nonzero if functions must have frame pointers.
35 Zero means the frame pointer need not be set up (and parms may be accessed
36 via the stack pointer) in functions that seem suitable. */
37
38 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
39 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
40 #endif
41
42 \f
43 /* Nonzero if this is an ELF target - compile time only */
44 #define TARGET_ELF 0
45
46 /* Nonzero if we should generate code using type 2E insns. */
47 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
48
49 /* Nonzero if we should generate code using type 2A insns. */
50 #define TARGET_SH2A TARGET_HARD_SH2A
51 /* Nonzero if we should generate code using type 2A SF insns. */
52 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
53 /* Nonzero if we should generate code using type 2A DF insns. */
54 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
55
56 /* Nonzero if we should generate code using type 3E insns. */
57 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
58
59 /* Nonzero if we schedule for a superscalar implementation. */
60 #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A)
61
62 /* Nonzero if a double-precision FPU is available. */
63 #define TARGET_FPU_DOUBLE \
64 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
65
66 /* Nonzero if an FPU is available. */
67 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
68
69 /* Nonzero if we should generate code using type 4 insns. */
70 #undef TARGET_SH4
71 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
72
73 /* Nonzero if we're generating code for the common subset of
74 instructions present on both SH4a and SH4al-dsp. */
75 #define TARGET_SH4A_ARCH TARGET_SH4A
76
77 /* Nonzero if we're generating code for SH4a, unless the use of the
78 FPU is disabled (which makes it compatible with SH4al-dsp). */
79 #define TARGET_SH4A_FP (TARGET_SH4A_ARCH && TARGET_FPU_ANY)
80
81 /* Nonzero if we should generate code using the SHcompact instruction
82 set and 32-bit ABI. */
83 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
84
85 /* Nonzero if we should generate code using the SHmedia instruction
86 set and ABI. */
87 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
88
89 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
90 ABI. */
91 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
92
93 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
94 ABI. */
95 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
96
97 /* Nonzero if we should generate code using SHmedia FPU instructions. */
98 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
99
100 /* This is not used by the SH2E calling convention */
101 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
102 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
103 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
104
105 #ifndef TARGET_CPU_DEFAULT
106 #define TARGET_CPU_DEFAULT SELECT_SH1
107 #define SUPPORT_SH1 1
108 #define SUPPORT_SH2E 1
109 #define SUPPORT_SH4 1
110 #define SUPPORT_SH4_SINGLE 1
111 #define SUPPORT_SH2A 1
112 #define SUPPORT_SH2A_SINGLE 1
113 #endif
114
115 #define TARGET_DIVIDE_INV \
116 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
117 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
118 || sh_div_strategy == SH_DIV_INV_CALL \
119 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
120 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
121 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
122 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
123 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
124 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
125 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
126 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
127 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
128 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
129 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
130 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
131
132 #define SELECT_SH1 (MASK_SH1)
133 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
134 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
135 | MASK_FPU_SINGLE)
136 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
137 | MASK_HARD_SH2A_DOUBLE \
138 | MASK_SH2 | MASK_SH1)
139 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
140 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
141 | MASK_SH1 | MASK_FPU_SINGLE \
142 | MASK_FPU_SINGLE_ONLY)
143 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
144 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
145 | MASK_SH2 | MASK_SH1)
146 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
147 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
148 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
149 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \
150 | MASK_FPU_SINGLE_ONLY)
151 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
152 | SELECT_SH3)
153 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
154 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
155 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
156 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
157 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
158 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
159 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
160 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
161 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
162 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
163 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
164
165 #if SUPPORT_SH1
166 #define SUPPORT_SH2 1
167 #endif
168 #if SUPPORT_SH2
169 #define SUPPORT_SH3 1
170 #define SUPPORT_SH2A_NOFPU 1
171 #endif
172 #if SUPPORT_SH3
173 #define SUPPORT_SH4_NOFPU 1
174 #endif
175 #if SUPPORT_SH4_NOFPU
176 #define SUPPORT_SH4A_NOFPU 1
177 #define SUPPORT_SH4AL 1
178 #endif
179
180 #if SUPPORT_SH2E
181 #define SUPPORT_SH3E 1
182 #define SUPPORT_SH2A_SINGLE_ONLY 1
183 #endif
184 #if SUPPORT_SH3E
185 #define SUPPORT_SH4_SINGLE_ONLY 1
186 #endif
187 #if SUPPORT_SH4_SINGLE_ONLY
188 #define SUPPORT_SH4A_SINGLE_ONLY 1
189 #endif
190
191 #if SUPPORT_SH4
192 #define SUPPORT_SH4A 1
193 #endif
194
195 #if SUPPORT_SH4_SINGLE
196 #define SUPPORT_SH4A_SINGLE 1
197 #endif
198
199 #if SUPPORT_SH5_COMPAT
200 #define SUPPORT_SH5_32MEDIA 1
201 #endif
202
203 #if SUPPORT_SH5_COMPACT_NOFPU
204 #define SUPPORT_SH5_32MEDIA_NOFPU 1
205 #endif
206
207 #define SUPPORT_ANY_SH5_32MEDIA \
208 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
209 #define SUPPORT_ANY_SH5_64MEDIA \
210 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
211 #define SUPPORT_ANY_SH5 \
212 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
213
214 /* Reset all target-selection flags. */
215 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
216 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
217 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
218 | MASK_FPU_SINGLE_ONLY)
219
220 /* This defaults us to big-endian. */
221 #ifndef TARGET_ENDIAN_DEFAULT
222 #define TARGET_ENDIAN_DEFAULT 0
223 #endif
224
225 #ifndef TARGET_OPT_DEFAULT
226 #define TARGET_OPT_DEFAULT 0
227 #endif
228
229 #define TARGET_DEFAULT \
230 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
231
232 #ifndef SH_MULTILIB_CPU_DEFAULT
233 #define SH_MULTILIB_CPU_DEFAULT "m1"
234 #endif
235
236 #if TARGET_ENDIAN_DEFAULT
237 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
238 #else
239 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
240 #endif
241
242 #define CPP_SPEC " %(subtarget_cpp_spec) "
243
244 #ifndef SUBTARGET_CPP_SPEC
245 #define SUBTARGET_CPP_SPEC ""
246 #endif
247
248 #ifndef SUBTARGET_EXTRA_SPECS
249 #define SUBTARGET_EXTRA_SPECS
250 #endif
251
252 #define EXTRA_SPECS \
253 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
254 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
255 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
256 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
257 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
258 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
259 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
260 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
261 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
262 SUBTARGET_EXTRA_SPECS
263
264 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
265 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
266 #else
267 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
268 #endif
269
270 #define SH_ASM_SPEC \
271 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \
272 %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \
273 %{m2a:--isa=sh2a} \
274 %{m2a-single:--isa=sh2a} \
275 %{m2a-single-only:--isa=sh2a} \
276 %{m2a-nofpu:--isa=sh2a-nofpu} \
277 %{m5-compact*:--isa=SHcompact} \
278 %{m5-32media*:--isa=SHmedia --abi=32} \
279 %{m5-64media*:--isa=SHmedia --abi=64} \
280 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
281
282 #define ASM_SPEC SH_ASM_SPEC
283
284 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
285 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
286 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
287 #else
288 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
289 #endif
290 #endif
291
292 #if STRICT_NOFPU == 1
293 /* Strict nofpu means that the compiler should tell the assembler
294 to reject FPU instructions. E.g. from ASM inserts. */
295 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
296 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
297 #else
298 /* If there were an -isa option for sh5-nofpu then it would also go here. */
299 #define SUBTARGET_ASM_ISA_SPEC \
300 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
301 #endif
302 #else /* ! STRICT_NOFPU */
303 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
304 #endif
305
306 #ifndef SUBTARGET_ASM_SPEC
307 #define SUBTARGET_ASM_SPEC ""
308 #endif
309
310 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
311 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
312 #else
313 #define LINK_EMUL_PREFIX "sh%{ml:l}"
314 #endif
315
316 #if TARGET_CPU_DEFAULT & MASK_SH5
317 #if TARGET_CPU_DEFAULT & MASK_SH_E
318 #define LINK_DEFAULT_CPU_EMUL "32"
319 #if TARGET_CPU_DEFAULT & MASK_SH1
320 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
321 #else
322 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
323 #endif /* MASK_SH1 */
324 #else /* !MASK_SH_E */
325 #define LINK_DEFAULT_CPU_EMUL "64"
326 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
327 #endif /* MASK_SH_E */
328 #define ASM_ISA_DEFAULT_SPEC \
329 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
330 #else /* !MASK_SH5 */
331 #define LINK_DEFAULT_CPU_EMUL ""
332 #define ASM_ISA_DEFAULT_SPEC ""
333 #endif /* MASK_SH5 */
334
335 #define SUBTARGET_LINK_EMUL_SUFFIX ""
336 #define SUBTARGET_LINK_SPEC ""
337
338 /* Go via SH_LINK_SPEC to avoid code replication. */
339 #define LINK_SPEC SH_LINK_SPEC
340
341 #define SH_LINK_SPEC "\
342 -m %(link_emul_prefix)\
343 %{m5-compact*|m5-32media*:32}\
344 %{m5-64media*:64}\
345 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
346 %(subtarget_link_emul_suffix) \
347 %{mrelax:-relax} %(subtarget_link_spec)"
348
349 #ifndef SH_DIV_STR_FOR_SIZE
350 #define SH_DIV_STR_FOR_SIZE "call"
351 #endif
352
353 /* SH2A does not support little-endian. Catch such combinations
354 taking into account the default configuration. */
355 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN
356 #define IS_LITTLE_ENDIAN_OPTION "%{ml:"
357 #else
358 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:"
359 #endif
360
361 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
362 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
363 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:{!m5*:%eSH2a does not support little-endian}}}}}}"
364 #else
365 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
366 "%{m2a*:%eSH2a does not support little-endian}}"
367 #endif
368
369 #undef DRIVER_SELF_SPECS
370 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A
371
372 #define ASSEMBLER_DIALECT assembler_dialect
373
374 extern int assembler_dialect;
375
376 enum sh_divide_strategy_e {
377 /* SH5 strategies. */
378 SH_DIV_CALL,
379 SH_DIV_CALL2,
380 SH_DIV_FP, /* We could do this also for SH4. */
381 SH_DIV_INV,
382 SH_DIV_INV_MINLAT,
383 SH_DIV_INV20U,
384 SH_DIV_INV20L,
385 SH_DIV_INV_CALL,
386 SH_DIV_INV_CALL2,
387 SH_DIV_INV_FP,
388 /* SH1 .. SH4 strategies. Because of the small number of registers
389 available, the compiler uses knowledge of the actual set of registers
390 being clobbered by the different functions called. */
391 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */
392 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */
393 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */
394 SH_DIV_INTRINSIC
395 };
396
397 extern enum sh_divide_strategy_e sh_div_strategy;
398
399 #ifndef SH_DIV_STRATEGY_DEFAULT
400 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
401 #endif
402
403 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
404
405 \f
406 /* Target machine storage layout. */
407
408 #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN)
409
410 #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0)
411 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1)
412
413 /* Define this if most significant bit is lowest numbered
414 in instructions that operate on numbered bit-fields. */
415 #define BITS_BIG_ENDIAN 0
416
417 /* Define this if most significant byte of a word is the lowest numbered. */
418 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN
419
420 /* Define this if most significant word of a multiword number is the lowest
421 numbered. */
422 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN
423
424 #define MAX_BITS_PER_WORD 64
425
426 /* Width in bits of an `int'. We want just 32-bits, even if words are
427 longer. */
428 #define INT_TYPE_SIZE 32
429
430 /* Width in bits of a `long'. */
431 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
432
433 /* Width in bits of a `long long'. */
434 #define LONG_LONG_TYPE_SIZE 64
435
436 /* Width in bits of a `long double'. */
437 #define LONG_DOUBLE_TYPE_SIZE 64
438
439 /* Width of a word, in units (bytes). */
440 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
441 #define MIN_UNITS_PER_WORD 4
442
443 /* Scaling factor for Dwarf data offsets for CFI information.
444 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
445 SHmedia; however, since we do partial register saves for the registers
446 visible to SHcompact, and for target registers for SHMEDIA32, we have
447 to allow saves that are only 4-byte aligned. */
448 #define DWARF_CIE_DATA_ALIGNMENT -4
449
450 /* Width in bits of a pointer.
451 See also the macro `Pmode' defined below. */
452 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
453
454 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
455 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
456
457 /* Boundary (in *bits*) on which stack pointer should be aligned. */
458 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
459
460 /* The log (base 2) of the cache line size, in bytes. Processors prior to
461 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
462 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
463 #define CACHE_LOG ((TARGET_HARD_SH4 || TARGET_SH5) ? 5 : TARGET_SH2 ? 4 : 2)
464
465 /* ABI given & required minimum allocation boundary (in *bits*) for the
466 code of a function. */
467 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
468
469 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
470 the vbit must go into the delta field of
471 pointers-to-member-functions. */
472 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
473 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
474
475 /* Alignment of field after `int : 0' in a structure. */
476 #define EMPTY_FIELD_BOUNDARY 32
477
478 /* No data type wants to be aligned rounder than this. */
479 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
480
481 /* The best alignment to use in cases where we have a choice. */
482 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
483
484 /* Make strings word-aligned so strcpy from constants will be faster. */
485 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
486 ((TREE_CODE (EXP) == STRING_CST \
487 && (ALIGN) < FASTEST_ALIGNMENT) \
488 ? FASTEST_ALIGNMENT : (ALIGN))
489
490 /* get_mode_alignment assumes complex values are always held in multiple
491 registers, but that is not the case on the SH; CQImode and CHImode are
492 held in a single integer register. SH5 also holds CSImode and SCmode
493 values in integer registers. This is relevant for argument passing on
494 SHcompact as we use a stack temp in order to pass CSImode by reference. */
495 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
496 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
497 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
498 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
499 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
500
501 /* Make arrays of chars word-aligned for the same reasons. */
502 #define DATA_ALIGNMENT(TYPE, ALIGN) \
503 (TREE_CODE (TYPE) == ARRAY_TYPE \
504 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
505 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
506
507 /* Number of bits which any structure or union's size must be a
508 multiple of. Each structure or union's size is rounded up to a
509 multiple of this. */
510 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
511
512 /* Set this nonzero if move instructions will actually fail to work
513 when given unaligned data. */
514 #define STRICT_ALIGNMENT 1
515
516 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
517 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
518 barrier_align (LABEL_AFTER_BARRIER)
519
520 #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL)
521
522 #define LABEL_ALIGN(A_LABEL) \
523 ( \
524 (PREV_INSN (A_LABEL) \
525 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
526 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
527 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
528 /* explicit alignment insn in constant tables. */ \
529 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
530 : 0)
531
532 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
533 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
534
535 /* The base two logarithm of the known minimum alignment of an insn length. */
536 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
537 (NONJUMP_INSN_P (A_INSN) \
538 ? 1 << TARGET_SHMEDIA \
539 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
540 ? 1 << TARGET_SHMEDIA \
541 : CACHE_LOG)
542 \f
543 /* Standard register usage. */
544
545 /* Register allocation for the Renesas calling convention:
546
547 r0 arg return
548 r1..r3 scratch
549 r4..r7 args in
550 r8..r13 call saved
551 r14 frame pointer/call saved
552 r15 stack pointer
553 ap arg pointer (doesn't really exist, always eliminated)
554 pr subroutine return address
555 t t bit
556 mach multiply/accumulate result, high part
557 macl multiply/accumulate result, low part.
558 fpul fp/int communication register
559 rap return address pointer register
560 fr0 fp arg return
561 fr1..fr3 scratch floating point registers
562 fr4..fr11 fp args in
563 fr12..fr15 call saved floating point registers */
564
565 #define MAX_REGISTER_NAME_LENGTH 5
566 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1];
567
568 #define SH_REGISTER_NAMES_INITIALIZER \
569 { \
570 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
571 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
572 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
573 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
574 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
575 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
576 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
577 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
578 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
579 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
580 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
581 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
582 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
583 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
584 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
585 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
586 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
587 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
588 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
589 "rap", "sfp" \
590 }
591
592 #define REGNAMES_ARR_INDEX_1(index) \
593 (sh_register_names[index])
594 #define REGNAMES_ARR_INDEX_2(index) \
595 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
596 #define REGNAMES_ARR_INDEX_4(index) \
597 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
598 #define REGNAMES_ARR_INDEX_8(index) \
599 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
600 #define REGNAMES_ARR_INDEX_16(index) \
601 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
602 #define REGNAMES_ARR_INDEX_32(index) \
603 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
604 #define REGNAMES_ARR_INDEX_64(index) \
605 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
606
607 #define REGISTER_NAMES \
608 { \
609 REGNAMES_ARR_INDEX_64 (0), \
610 REGNAMES_ARR_INDEX_64 (64), \
611 REGNAMES_ARR_INDEX_8 (128), \
612 REGNAMES_ARR_INDEX_8 (136), \
613 REGNAMES_ARR_INDEX_8 (144), \
614 REGNAMES_ARR_INDEX_2 (152) \
615 }
616
617 #define ADDREGNAMES_SIZE 32
618 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
619 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
620 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1];
621
622 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
623 { \
624 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
625 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
626 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
627 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
628 }
629
630 #define ADDREGNAMES_REGNO(index) \
631 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
632 : (-1))
633
634 #define ADDREGNAMES_ARR_INDEX_1(index) \
635 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
636 #define ADDREGNAMES_ARR_INDEX_2(index) \
637 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
638 #define ADDREGNAMES_ARR_INDEX_4(index) \
639 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
640 #define ADDREGNAMES_ARR_INDEX_8(index) \
641 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
642 #define ADDREGNAMES_ARR_INDEX_16(index) \
643 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
644 #define ADDREGNAMES_ARR_INDEX_32(index) \
645 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
646
647 #define ADDITIONAL_REGISTER_NAMES \
648 { \
649 ADDREGNAMES_ARR_INDEX_32 (0) \
650 }
651
652 /* Number of actual hardware registers.
653 The hardware registers are assigned numbers for the compiler
654 from 0 to just below FIRST_PSEUDO_REGISTER.
655 All registers that the compiler knows about must be given numbers,
656 even those that are not normally considered general registers. */
657
658 /* There are many other relevant definitions in sh.md's md_constants. */
659
660 #define FIRST_GENERAL_REG R0_REG
661 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
662 #define FIRST_FP_REG DR0_REG
663 #define LAST_FP_REG (FIRST_FP_REG + \
664 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
665 #define FIRST_XD_REG XD0_REG
666 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
667 #define FIRST_TARGET_REG TR0_REG
668 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
669
670 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
671 #define FIRST_BANKED_REG R0_REG
672 #define LAST_BANKED_REG R7_REG
673
674 #define BANKED_REGISTER_P(REGNO) \
675 IN_RANGE ((REGNO), \
676 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
677 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
678
679 #define GENERAL_REGISTER_P(REGNO) \
680 IN_RANGE ((REGNO), \
681 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
682 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
683
684 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
685 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
686 || ((REGNO) == FRAME_POINTER_REGNUM))
687
688 #define FP_REGISTER_P(REGNO) \
689 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
690
691 #define XD_REGISTER_P(REGNO) \
692 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
693
694 #define FP_OR_XD_REGISTER_P(REGNO) \
695 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
696
697 #define FP_ANY_REGISTER_P(REGNO) \
698 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
699
700 #define SPECIAL_REGISTER_P(REGNO) \
701 ((REGNO) == GBR_REG || (REGNO) == T_REG \
702 || (REGNO) == MACH_REG || (REGNO) == MACL_REG)
703
704 #define TARGET_REGISTER_P(REGNO) \
705 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
706
707 #define SHMEDIA_REGISTER_P(REGNO) \
708 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
709 || TARGET_REGISTER_P (REGNO))
710
711 /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark
712 registers that should be fixed. */
713 #define VALID_REGISTER_P(REGNO) \
714 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
715 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
716 || (REGNO) == FRAME_POINTER_REGNUM \
717 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
718 || (TARGET_SH2E && (REGNO) == FPUL_REG))
719
720 /* The mode that should be generally used to store a register by
721 itself in the stack, or to load it back. */
722 #define REGISTER_NATURAL_MODE(REGNO) \
723 (FP_REGISTER_P (REGNO) ? SFmode \
724 : XD_REGISTER_P (REGNO) ? DFmode \
725 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
726 ? DImode \
727 : SImode)
728
729 #define FIRST_PSEUDO_REGISTER 154
730
731 /* Don't count soft frame pointer. */
732 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
733
734 /* 1 for registers that have pervasive standard uses
735 and are not available for the register allocator.
736
737 Mach register is fixed 'cause it's only 10 bits wide for SH1.
738 It is 32 bits wide for SH2. */
739 #define FIXED_REGISTERS \
740 { \
741 /* Regular registers. */ \
742 0, 0, 0, 0, 0, 0, 0, 0, \
743 0, 0, 0, 0, 0, 0, 0, 1, \
744 /* r16 is reserved, r18 is the former pr. */ \
745 1, 0, 0, 0, 0, 0, 0, 0, \
746 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
747 /* r26 is a global variable data pointer; r27 is for constants. */ \
748 1, 1, 1, 1, 0, 0, 0, 0, \
749 0, 0, 0, 0, 0, 0, 0, 0, \
750 0, 0, 0, 0, 0, 0, 0, 0, \
751 0, 0, 0, 0, 0, 0, 0, 0, \
752 0, 0, 0, 0, 0, 0, 0, 1, \
753 /* FP registers. */ \
754 0, 0, 0, 0, 0, 0, 0, 0, \
755 0, 0, 0, 0, 0, 0, 0, 0, \
756 0, 0, 0, 0, 0, 0, 0, 0, \
757 0, 0, 0, 0, 0, 0, 0, 0, \
758 0, 0, 0, 0, 0, 0, 0, 0, \
759 0, 0, 0, 0, 0, 0, 0, 0, \
760 0, 0, 0, 0, 0, 0, 0, 0, \
761 0, 0, 0, 0, 0, 0, 0, 0, \
762 /* Branch target registers. */ \
763 0, 0, 0, 0, 0, 0, 0, 0, \
764 /* XD registers. */ \
765 0, 0, 0, 0, 0, 0, 0, 0, \
766 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
767 1, 1, 1, 1, 1, 1, 0, 1, \
768 /*"rap", "sfp" */ \
769 1, 1, \
770 }
771
772 /* 1 for registers not available across function calls.
773 These must include the FIXED_REGISTERS and also any
774 registers that can be used without being saved.
775 The latter must include the registers where values are returned
776 and the register where structure-value addresses are passed.
777 Aside from that, you can include as many other registers as you like. */
778 #define CALL_USED_REGISTERS \
779 { \
780 /* Regular registers. */ \
781 1, 1, 1, 1, 1, 1, 1, 1, \
782 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
783 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
784 across SH5 function calls. */ \
785 0, 0, 0, 0, 0, 0, 0, 1, \
786 1, 1, 1, 1, 1, 1, 1, 1, \
787 1, 1, 1, 1, 0, 0, 0, 0, \
788 0, 0, 0, 0, 1, 1, 1, 1, \
789 1, 1, 1, 1, 0, 0, 0, 0, \
790 0, 0, 0, 0, 0, 0, 0, 0, \
791 0, 0, 0, 0, 1, 1, 1, 1, \
792 /* FP registers. */ \
793 1, 1, 1, 1, 1, 1, 1, 1, \
794 1, 1, 1, 1, 0, 0, 0, 0, \
795 1, 1, 1, 1, 1, 1, 1, 1, \
796 1, 1, 1, 1, 1, 1, 1, 1, \
797 1, 1, 1, 1, 0, 0, 0, 0, \
798 0, 0, 0, 0, 0, 0, 0, 0, \
799 0, 0, 0, 0, 0, 0, 0, 0, \
800 0, 0, 0, 0, 0, 0, 0, 0, \
801 /* Branch target registers. */ \
802 1, 1, 1, 1, 1, 0, 0, 0, \
803 /* XD registers. */ \
804 1, 1, 1, 1, 1, 1, 0, 0, \
805 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
806 1, 1, 1, 1, 1, 1, 1, 1, \
807 /*"rap", "sfp" */ \
808 1, 1, \
809 }
810
811 /* TARGET_CONDITIONAL_REGISTER_USAGE might want to make a register
812 call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
813 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
814
815 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
816 across SHcompact function calls. We can't tell whether a called
817 function is SHmedia or SHcompact, so we assume it may be when
818 compiling SHmedia code with the 32-bit ABI, since that's the only
819 ABI that can be linked with SHcompact code. */
820 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
821 (TARGET_SHMEDIA32 \
822 && GET_MODE_SIZE (MODE) > 4 \
823 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
824 && (REGNO) <= FIRST_GENERAL_REG + 15) \
825 || TARGET_REGISTER_P (REGNO) \
826 || (REGNO) == PR_MEDIA_REG))
827
828 /* Return number of consecutive hard regs needed starting at reg REGNO
829 to hold something of mode MODE.
830 This is ordinarily the length in words of a value of mode MODE
831 but can be less for certain modes in special long registers.
832
833 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
834 #define HARD_REGNO_NREGS(REGNO, MODE) \
835 (XD_REGISTER_P (REGNO) \
836 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
837 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
838 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
839 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
840
841 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
842 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
843 sh_hard_regno_mode_ok ((REGNO), (MODE))
844
845 /* Value is 1 if it is a good idea to tie two pseudo registers
846 when one has mode MODE1 and one has mode MODE2.
847 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
848 for any hard reg, then this must be 0 for correct output.
849 That's the case for xd registers: we don't hold SFmode values in
850 them, so we can't tie an SFmode pseudos with one in another
851 floating-point mode. */
852 #define MODES_TIEABLE_P(MODE1, MODE2) \
853 ((MODE1) == (MODE2) \
854 || (TARGET_SHMEDIA \
855 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
856 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
857 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
858 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
859 && (GET_MODE_SIZE (MODE2) <= 4)) \
860 : ((MODE1) != SFmode && (MODE2) != SFmode))))
861
862 /* A C expression that is nonzero if hard register NEW_REG can be
863 considered for use as a rename register for OLD_REG register */
864 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
865 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
866
867 /* Specify the registers used for certain standard purposes.
868 The values of these macros are register numbers. */
869
870 /* Define this if the program counter is overloaded on a register. */
871 /* #define PC_REGNUM 15*/
872
873 /* Register to use for pushing function arguments. */
874 #define STACK_POINTER_REGNUM SP_REG
875
876 /* Base register for access to local variables of the function. */
877 #define HARD_FRAME_POINTER_REGNUM FP_REG
878
879 /* Base register for access to local variables of the function. */
880 #define FRAME_POINTER_REGNUM 153
881
882 /* Fake register that holds the address on the stack of the
883 current function's return address. */
884 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
885
886 /* Register to hold the addressing base for position independent
887 code access to data items. */
888 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
889
890 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
891
892 /* Definitions for register eliminations.
893
894 We have three registers that can be eliminated on the SH. First, the
895 frame pointer register can often be eliminated in favor of the stack
896 pointer register. Secondly, the argument pointer register can always be
897 eliminated; it is replaced with either the stack or frame pointer.
898 Third, there is the return address pointer, which can also be replaced
899 with either the stack or the frame pointer.
900
901 This is an array of structures. Each structure initializes one pair
902 of eliminable registers. The "from" register number is given first,
903 followed by "to". Eliminations of the same "from" register are listed
904 in order of preference.
905
906 If you add any registers here that are not actually hard registers,
907 and that have any alternative of elimination that doesn't always
908 apply, you need to amend calc_live_regs to exclude it, because
909 reload spills all eliminable registers where it sees an
910 can_eliminate == 0 entry, thus making them 'live' .
911 If you add any hard registers that can be eliminated in different
912 ways, you have to patch reload to spill them only when all alternatives
913 of elimination fail. */
914 #define ELIMINABLE_REGS \
915 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
916 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
917 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
918 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
919 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
920 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
921 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
922
923 /* Define the offset between two registers, one to be eliminated, and the other
924 its replacement, at the start of a routine. */
925 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
926 OFFSET = initial_elimination_offset ((FROM), (TO))
927
928 /* Base register for access to arguments of the function. */
929 #define ARG_POINTER_REGNUM AP_REG
930
931 /* Register in which the static-chain is passed to a function. */
932 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
933
934 /* Don't default to pcc-struct-return, because we have already specified
935 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
936 target hook. */
937 #define DEFAULT_PCC_STRUCT_RETURN 0
938
939 #define SHMEDIA_REGS_STACK_ADJUST() \
940 (TARGET_SHCOMPACT && crtl->saves_all_registers \
941 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
942 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
943 : 0)
944
945 \f
946 /* Define the classes of registers for register constraints in the
947 machine description. Also define ranges of constants.
948
949 One of the classes must always be named ALL_REGS and include all hard regs.
950 If there is more than one class, another class must be named NO_REGS
951 and contain no registers.
952
953 The name GENERAL_REGS must be the name of a class (or an alias for
954 another name such as ALL_REGS). This is the class of registers
955 that is allowed by "g" or "r" in a register constraint.
956 Also, registers outside this class are allocated only when
957 instructions express preferences for them.
958
959 The classes must be numbered in nondecreasing order; that is,
960 a larger-numbered class must never be contained completely
961 in a smaller-numbered class.
962
963 For any two classes, it is very desirable that there be another
964 class that represents their union.
965
966 The SH has two sorts of general registers, R0 and the rest. R0 can
967 be used as the destination of some of the arithmetic ops. There are
968 also some special purpose registers; the T bit register, the
969 Procedure Return Register and the Multiply Accumulate Registers.
970
971 Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
972 reg_class_subunion. We don't want to have an actual union class
973 of these, because it would only be used when both classes are calculated
974 to give the same cost, but there is only one FPUL register.
975 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
976 applying to the actual instruction alternative considered. E.g., the
977 y/r alternative of movsi_ie is considered to have no more cost that
978 the r/r alternative, which is patently untrue. */
979 enum reg_class
980 {
981 NO_REGS,
982 R0_REGS,
983 PR_REGS,
984 T_REGS,
985 MAC_REGS,
986 FPUL_REGS,
987 SIBCALL_REGS,
988 NON_SP_REGS,
989 GENERAL_REGS,
990 FP0_REGS,
991 FP_REGS,
992 DF_REGS,
993 FPSCR_REGS,
994 GENERAL_FP_REGS,
995 GENERAL_DF_REGS,
996 TARGET_REGS,
997 ALL_REGS,
998 LIM_REG_CLASSES
999 };
1000
1001 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1002
1003 /* Give names of register classes as strings for dump file. */
1004 #define REG_CLASS_NAMES \
1005 { \
1006 "NO_REGS", \
1007 "R0_REGS", \
1008 "PR_REGS", \
1009 "T_REGS", \
1010 "MAC_REGS", \
1011 "FPUL_REGS", \
1012 "SIBCALL_REGS", \
1013 "NON_SP_REGS", \
1014 "GENERAL_REGS", \
1015 "FP0_REGS", \
1016 "FP_REGS", \
1017 "DF_REGS", \
1018 "FPSCR_REGS", \
1019 "GENERAL_FP_REGS", \
1020 "GENERAL_DF_REGS", \
1021 "TARGET_REGS", \
1022 "ALL_REGS", \
1023 }
1024
1025 /* Define which registers fit in which classes.
1026 This is an initializer for a vector of HARD_REG_SET
1027 of length N_REG_CLASSES. */
1028 #define REG_CLASS_CONTENTS \
1029 { \
1030 /* NO_REGS: */ \
1031 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1032 /* R0_REGS: */ \
1033 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1034 /* PR_REGS: */ \
1035 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1036 /* T_REGS: */ \
1037 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1038 /* MAC_REGS: */ \
1039 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1040 /* FPUL_REGS: */ \
1041 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1042 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1043 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1044 /* NON_SP_REGS: */ \
1045 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1046 /* GENERAL_REGS: */ \
1047 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1048 /* FP0_REGS: */ \
1049 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1050 /* FP_REGS: */ \
1051 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1052 /* DF_REGS: */ \
1053 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1054 /* FPSCR_REGS: */ \
1055 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1056 /* GENERAL_FP_REGS: */ \
1057 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1058 /* GENERAL_DF_REGS: */ \
1059 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1060 /* TARGET_REGS: */ \
1061 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1062 /* ALL_REGS: */ \
1063 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03ffffff }, \
1064 }
1065
1066 /* The same information, inverted:
1067 Return the class number of the smallest class containing
1068 reg number REGNO. This could be a conditional expression
1069 or could index an array. */
1070 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
1071 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1072
1073 /* When this hook returns true for MODE, the compiler allows
1074 registers explicitly used in the rtl to be used as spill registers
1075 but prevents the compiler from extending the lifetime of these
1076 registers. */
1077 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1078 sh_small_register_classes_for_mode_p
1079
1080 /* The order in which register should be allocated. */
1081 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1082 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1083 spilled or used otherwise, we better have the FP_REGS allocated first. */
1084 #define REG_ALLOC_ORDER \
1085 {/* Caller-saved FPRs */ \
1086 65, 66, 67, 68, 69, 70, 71, 64, \
1087 72, 73, 74, 75, 80, 81, 82, 83, \
1088 84, 85, 86, 87, 88, 89, 90, 91, \
1089 92, 93, 94, 95, 96, 97, 98, 99, \
1090 /* Callee-saved FPRs */ \
1091 76, 77, 78, 79,100,101,102,103, \
1092 104,105,106,107,108,109,110,111, \
1093 112,113,114,115,116,117,118,119, \
1094 120,121,122,123,124,125,126,127, \
1095 136,137,138,139,140,141,142,143, \
1096 /* FPSCR */ 151, \
1097 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1098 1, 2, 3, 7, 6, 5, 4, 0, \
1099 8, 9, 17, 19, 20, 21, 22, 23, \
1100 36, 37, 38, 39, 40, 41, 42, 43, \
1101 60, 61, 62, \
1102 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1103 10, 11, 12, 13, 14, 18, \
1104 /* SH5 callee-saved GPRs */ \
1105 28, 29, 30, 31, 32, 33, 34, 35, \
1106 44, 45, 46, 47, 48, 49, 50, 51, \
1107 52, 53, 54, 55, 56, 57, 58, 59, \
1108 /* FPUL */ 150, \
1109 /* SH5 branch target registers */ \
1110 128,129,130,131,132,133,134,135, \
1111 /* Fixed registers */ \
1112 15, 16, 24, 25, 26, 27, 63,144, \
1113 145,146,147,148,149,152,153 }
1114
1115 /* The class value for index registers, and the one for base regs. */
1116 #define INDEX_REG_CLASS \
1117 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1118 #define BASE_REG_CLASS GENERAL_REGS
1119 \f
1120 /* Defines for sh.md and constraints.md. */
1121
1122 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1123 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1124 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1125 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1126
1127 #define CONST_OK_FOR_J16(VALUE) \
1128 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1129 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1130
1131 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1132 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1133
1134 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
1135 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
1136
1137 /* Return the maximum number of consecutive registers
1138 needed to represent mode MODE in a register of class CLASS.
1139
1140 If TARGET_SHMEDIA, we need two FP registers per word.
1141 Otherwise we will need at most one register per word. */
1142 #define CLASS_MAX_NREGS(CLASS, MODE) \
1143 (TARGET_SHMEDIA \
1144 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1145 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1146 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1147
1148 /* If defined, gives a class of registers that cannot be used as the
1149 operand of a SUBREG that changes the mode of the object illegally.
1150 ??? We need to renumber the internal numbers for the frnn registers
1151 when in little endian in order to allow mode size changes. */
1152 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1153 sh_cannot_change_mode_class (FROM, TO, CLASS)
1154 \f
1155 /* Stack layout; function entry, exit and calling. */
1156
1157 /* Define the number of registers that can hold parameters.
1158 These macros are used only in other macro definitions below. */
1159 #define NPARM_REGS(MODE) \
1160 (TARGET_FPU_ANY && (MODE) == SFmode \
1161 ? (TARGET_SH5 ? 12 : 8) \
1162 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
1163 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1164 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1165 ? (TARGET_SH5 ? 12 : 8) \
1166 : (TARGET_SH5 ? 8 : 4))
1167
1168 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1169 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1170
1171 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1172 #define FIRST_FP_RET_REG FIRST_FP_REG
1173
1174 /* Define this if pushing a word on the stack
1175 makes the stack pointer a smaller address. */
1176 #define STACK_GROWS_DOWNWARD
1177
1178 /* Define this macro to nonzero if the addresses of local variable slots
1179 are at negative offsets from the frame pointer. */
1180 #define FRAME_GROWS_DOWNWARD 1
1181
1182 /* Offset from the frame pointer to the first local variable slot to
1183 be allocated. */
1184 #define STARTING_FRAME_OFFSET 0
1185
1186 /* If we generate an insn to push BYTES bytes,
1187 this says how many the stack pointer really advances by. */
1188 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1189 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1190 do correct alignment. */
1191 #if 0
1192 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1193 #endif
1194
1195 /* Offset of first parameter from the argument pointer register value. */
1196 #define FIRST_PARM_OFFSET(FNDECL) 0
1197
1198 /* Value is the number of bytes of arguments automatically popped when
1199 calling a subroutine.
1200 CUM is the accumulated argument list.
1201
1202 On SHcompact, the call trampoline pops arguments off the stack. */
1203 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1204
1205 /* Some subroutine macros specific to this machine. */
1206
1207 #define BASE_RETURN_VALUE_REG(MODE) \
1208 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1209 ? FIRST_FP_RET_REG \
1210 : TARGET_FPU_ANY && (MODE) == SCmode \
1211 ? FIRST_FP_RET_REG \
1212 : (TARGET_FPU_DOUBLE \
1213 && ((MODE) == DFmode || (MODE) == SFmode \
1214 || (MODE) == DCmode || (MODE) == SCmode )) \
1215 ? FIRST_FP_RET_REG \
1216 : FIRST_RET_REG)
1217
1218 #define BASE_ARG_REG(MODE) \
1219 ((TARGET_SH2E && ((MODE) == SFmode)) \
1220 ? FIRST_FP_PARM_REG \
1221 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1222 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1223 ? FIRST_FP_PARM_REG \
1224 : FIRST_PARM_REG)
1225
1226 /* 1 if N is a possible register number for function argument passing. */
1227 /* ??? There are some callers that pass REGNO as int, and others that pass
1228 it as unsigned. We get warnings unless we do casts everywhere. */
1229 #define FUNCTION_ARG_REGNO_P(REGNO) \
1230 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1231 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1232 || (TARGET_FPU_ANY \
1233 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1234 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1235 + NPARM_REGS (SFmode))))
1236 \f
1237 /* Define a data type for recording info about an argument list
1238 during the scan of that argument list. This data type should
1239 hold all necessary information about the function itself
1240 and about the args processed so far, enough to enable macros
1241 such as FUNCTION_ARG to determine where the next arg should go.
1242
1243 On SH, this is a single integer, which is a number of words
1244 of arguments scanned so far (including the invisible argument,
1245 if any, which holds the structure-value-address).
1246 Thus NARGREGS or more means all following args should go on the stack. */
1247 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 };
1248 struct sh_args {
1249 int arg_count[2];
1250 int force_mem;
1251 /* Nonzero if a prototype is available for the function. */
1252 int prototype_p;
1253 /* The number of an odd floating-point register, that should be used
1254 for the next argument of type float. */
1255 int free_single_fp_reg;
1256 /* Whether we're processing an outgoing function call. */
1257 int outgoing;
1258 /* The number of general-purpose registers that should have been
1259 used to pass partial arguments, that are passed totally on the
1260 stack. On SHcompact, a call trampoline will pop them off the
1261 stack before calling the actual function, and, if the called
1262 function is implemented in SHcompact mode, the incoming arguments
1263 decoder will push such arguments back onto the stack. For
1264 incoming arguments, STACK_REGS also takes into account other
1265 arguments passed by reference, that the decoder will also push
1266 onto the stack. */
1267 int stack_regs;
1268 /* The number of general-purpose registers that should have been
1269 used to pass arguments, if the arguments didn't have to be passed
1270 by reference. */
1271 int byref_regs;
1272 /* Set as by shcompact_byref if the current argument is to be passed
1273 by reference. */
1274 int byref;
1275
1276 /* call_cookie is a bitmask used by call expanders, as well as
1277 function prologue and epilogues, to allow SHcompact to comply
1278 with the SH5 32-bit ABI, that requires 64-bit registers to be
1279 used even though only the lower 32-bit half is visible in
1280 SHcompact mode. The strategy is to call SHmedia trampolines.
1281
1282 The alternatives for each of the argument-passing registers are
1283 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1284 contents from the address in it; (d) add 8 to it, storing the
1285 result in the next register, then (c); (e) copy it from some
1286 floating-point register,
1287
1288 Regarding copies from floating-point registers, r2 may only be
1289 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1290 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1291 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1292 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1293 dr10.
1294
1295 The bit mask is structured as follows:
1296
1297 - 1 bit to tell whether to set up a return trampoline.
1298
1299 - 3 bits to count the number consecutive registers to pop off the
1300 stack.
1301
1302 - 4 bits for each of r9, r8, r7 and r6.
1303
1304 - 3 bits for each of r5, r4, r3 and r2.
1305
1306 - 3 bits set to 0 (the most significant ones)
1307
1308 3 2 1 0
1309 1098 7654 3210 9876 5432 1098 7654 3210
1310 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1311 2223 3344 4555 6666 7777 8888 9999 SSS-
1312
1313 - If F is set, the register must be copied from an FP register,
1314 whose number is encoded in the remaining bits.
1315
1316 - Else, if L is set, the register must be loaded from the address
1317 contained in it. If the P bit is *not* set, the address of the
1318 following dword should be computed first, and stored in the
1319 following register.
1320
1321 - Else, if P is set, the register alone should be popped off the
1322 stack.
1323
1324 - After all this processing, the number of registers represented
1325 in SSS will be popped off the stack. This is an optimization
1326 for pushing/popping consecutive registers, typically used for
1327 varargs and large arguments partially passed in registers.
1328
1329 - If T is set, a return trampoline will be set up for 64-bit
1330 return values to be split into 2 32-bit registers. */
1331 long call_cookie;
1332
1333 /* This is set to nonzero when the call in question must use the Renesas ABI,
1334 even without the -mrenesas option. */
1335 int renesas_abi;
1336 };
1337
1338 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1339 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1340 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1341 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1342 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1343 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1344 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1345 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1346 #define CALL_COOKIE_INT_REG(REG, VAL) \
1347 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1348 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1349 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1350
1351 #define CUMULATIVE_ARGS struct sh_args
1352
1353 #define GET_SH_ARG_CLASS(MODE) \
1354 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1355 ? SH_ARG_FLOAT \
1356 /* There's no mention of complex float types in the SH5 ABI, so we
1357 should presumably handle them as aggregate types. */ \
1358 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1359 ? SH_ARG_INT \
1360 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1361 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1362 ? SH_ARG_FLOAT : SH_ARG_INT)
1363
1364 #define ROUND_ADVANCE(SIZE) \
1365 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1366
1367 /* Round a register number up to a proper boundary for an arg of mode
1368 MODE.
1369
1370 The SH doesn't care about double alignment, so we only
1371 round doubles to even regs when asked to explicitly. */
1372 #define ROUND_REG(CUM, MODE) \
1373 (((TARGET_ALIGN_DOUBLE \
1374 || ((TARGET_SH4 || TARGET_SH2A_DOUBLE) \
1375 && ((MODE) == DFmode || (MODE) == DCmode) \
1376 && (CUM).arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (MODE))) \
1377 && GET_MODE_UNIT_SIZE ((MODE)) > UNITS_PER_WORD) \
1378 ? ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] \
1379 + ((CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)] & 1)) \
1380 : (CUM).arg_count[(int) GET_SH_ARG_CLASS (MODE)])
1381
1382 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1383 for a call to a function whose data type is FNTYPE.
1384 For a library call, FNTYPE is 0.
1385
1386 On SH, the offset always starts at 0: the first parm reg is always
1387 the same reg for a given argument class.
1388
1389 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1390 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1391 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\
1392 (N_NAMED_ARGS), VOIDmode)
1393
1394 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1395 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1396
1397 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1398 This macro is only used in this file. */
1399 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1400 (((TYPE) == 0 \
1401 || (! TREE_ADDRESSABLE ((TYPE)) \
1402 && (! (TARGET_HITACHI || (CUM).renesas_abi) \
1403 || ! (AGGREGATE_TYPE_P (TYPE) \
1404 || (!TARGET_FPU_ANY \
1405 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1406 && GET_MODE_SIZE (MODE) > GET_MODE_SIZE (SFmode))))))) \
1407 && ! (CUM).force_mem \
1408 && (TARGET_SH2E \
1409 ? ((MODE) == BLKmode \
1410 ? (((CUM).arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD \
1411 + int_size_in_bytes (TYPE)) \
1412 <= NPARM_REGS (SImode) * UNITS_PER_WORD) \
1413 : ((ROUND_REG((CUM), (MODE)) \
1414 + HARD_REGNO_NREGS (BASE_ARG_REG (MODE), (MODE))) \
1415 <= NPARM_REGS (MODE))) \
1416 : ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE)))
1417
1418 /* By accident we got stuck with passing SCmode on SH4 little endian
1419 in two registers that are nominally successive - which is different from
1420 two single SFmode values, where we take endianness translation into
1421 account. That does not work at all if an odd number of registers is
1422 already in use, so that got fixed, but library functions are still more
1423 likely to use complex numbers without mixing them with SFmode arguments
1424 (which in C would have to be structures), so for the sake of ABI
1425 compatibility the way SCmode values are passed when an even number of
1426 FP registers is in use remains different from a pair of SFmode values for
1427 now.
1428 I.e.:
1429 foo (double); a: fr5,fr4
1430 foo (float a, float b); a: fr5 b: fr4
1431 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1432 this should be the other way round...
1433 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1434 #define FUNCTION_ARG_SCmode_WART 1
1435
1436 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1437 register in SHcompact mode, it must be padded in the most
1438 significant end. This means that passing it by reference wouldn't
1439 pad properly on a big-endian machine. In this particular case, we
1440 pass this argument on the stack, in a way that the call trampoline
1441 will load its value into the appropriate register. */
1442 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1443 ((MODE) == BLKmode \
1444 && TARGET_SHCOMPACT \
1445 && TARGET_BIG_ENDIAN \
1446 && int_size_in_bytes (TYPE) > 4 \
1447 && int_size_in_bytes (TYPE) < 8)
1448
1449 /* Minimum alignment for an argument to be passed by callee-copy
1450 reference. We need such arguments to be aligned to 8 byte
1451 boundaries, because they'll be loaded using quad loads. */
1452 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1453
1454 /* The SH5 ABI requires floating-point arguments to be passed to
1455 functions without a prototype in both an FP register and a regular
1456 register or the stack. When passing the argument in both FP and
1457 general-purpose registers, list the FP register first. */
1458 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1459 (gen_rtx_PARALLEL \
1460 ((MODE), \
1461 gen_rtvec (2, \
1462 gen_rtx_EXPR_LIST \
1463 (VOIDmode, \
1464 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1465 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1466 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1467 : NULL_RTX), \
1468 const0_rtx), \
1469 gen_rtx_EXPR_LIST \
1470 (VOIDmode, \
1471 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1472 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1473 + (CUM).arg_count[(int) SH_ARG_INT]) \
1474 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1475 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1476 const0_rtx))))
1477
1478 /* The SH5 ABI requires regular registers or stack slots to be
1479 reserved for floating-point arguments. Registers are taken care of
1480 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1481 Unfortunately, there's no way to just reserve a stack slot, so
1482 we'll end up needlessly storing a copy of the argument in the
1483 stack. For incoming arguments, however, the PARALLEL will be
1484 optimized to the register-only form, and the value in the stack
1485 slot won't be used at all. */
1486 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1487 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1488 ? gen_rtx_REG ((MODE), (REG)) \
1489 : gen_rtx_PARALLEL ((MODE), \
1490 gen_rtvec (2, \
1491 gen_rtx_EXPR_LIST \
1492 (VOIDmode, NULL_RTX, \
1493 const0_rtx), \
1494 gen_rtx_EXPR_LIST \
1495 (VOIDmode, gen_rtx_REG ((MODE), \
1496 (REG)), \
1497 const0_rtx))))
1498
1499 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1500 (TARGET_SH5 \
1501 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1502 || (MODE) == DCmode) \
1503 && ((CUM).arg_count[(int) SH_ARG_INT] \
1504 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1505 : GET_MODE_SIZE (MODE)) \
1506 + 7) / 8) > NPARM_REGS (SImode))
1507
1508 /* Perform any needed actions needed for a function that is receiving a
1509 variable number of arguments. */
1510
1511 /* Call the function profiler with a given profile label.
1512 We use two .aligns, so as to make sure that both the .long is aligned
1513 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1514 from the trapa instruction. */
1515 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1516 { \
1517 if (TARGET_SHMEDIA) \
1518 { \
1519 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1520 fprintf((STREAM), "\ttrapa\tr0\n"); \
1521 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1522 } \
1523 else \
1524 { \
1525 fprintf((STREAM), "\t.align\t2\n"); \
1526 fprintf((STREAM), "\ttrapa\t#33\n"); \
1527 fprintf((STREAM), "\t.align\t2\n"); \
1528 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1529 } \
1530 }
1531
1532 /* Define this macro if the code for function profiling should come
1533 before the function prologue. Normally, the profiling code comes
1534 after. */
1535 #define PROFILE_BEFORE_PROLOGUE
1536
1537 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1538 the stack pointer does not matter. The value is tested only in
1539 functions that have frame pointers.
1540 No definition is equivalent to always zero. */
1541 #define EXIT_IGNORE_STACK 1
1542
1543 /*
1544 On the SH, the trampoline looks like
1545 2 0002 D202 mov.l l2,r2
1546 1 0000 D301 mov.l l1,r3
1547 3 0004 422B jmp @r2
1548 4 0006 0009 nop
1549 5 0008 00000000 l1: .long area
1550 6 000c 00000000 l2: .long function */
1551
1552 /* Length in units of the trampoline for entering a nested function. */
1553 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1554
1555 /* Alignment required for a trampoline in bits. */
1556 #define TRAMPOLINE_ALIGNMENT \
1557 ((CACHE_LOG < 3 \
1558 || (optimize_size && ! (TARGET_HARD_SH4 || TARGET_SH5))) ? 32 \
1559 : TARGET_SHMEDIA ? 256 : 64)
1560
1561 /* A C expression whose value is RTL representing the value of the return
1562 address for the frame COUNT steps up from the current frame.
1563 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1564 can ignore COUNT. */
1565 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1566 (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX)
1567
1568 /* A C expression whose value is RTL representing the location of the
1569 incoming return address at the beginning of any function, before the
1570 prologue. This RTL is either a REG, indicating that the return
1571 value is saved in REG, or a MEM representing a location in
1572 the stack. */
1573 #define INCOMING_RETURN_ADDR_RTX \
1574 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1575 \f
1576 /* Addressing modes, and classification of registers for them. */
1577 #define HAVE_POST_INCREMENT TARGET_SH1
1578 #define HAVE_PRE_DECREMENT TARGET_SH1
1579
1580 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1581 ? 0 : TARGET_SH1)
1582 #define USE_LOAD_PRE_DECREMENT(mode) 0
1583 #define USE_STORE_POST_INCREMENT(mode) 0
1584 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1585 ? 0 : TARGET_SH1)
1586
1587 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
1588 (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
1589 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1590
1591 #define STORE_BY_PIECES_P(SIZE, ALIGN) \
1592 (move_by_pieces_ninsns (SIZE, ALIGN, STORE_MAX_PIECES + 1) \
1593 < (optimize_size ? 2 : ((ALIGN >= 32) ? 16 : 2)))
1594
1595 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P(SIZE, ALIGN)
1596
1597 /* Macros to check register numbers against specific register classes. */
1598
1599 /* These assume that REGNO is a hard or pseudo reg number.
1600 They give nonzero only if REGNO is a hard reg of the suitable class
1601 or a pseudo reg currently allocated to a suitable hard reg.
1602 Since they use reg_renumber, they are safe only once reg_renumber
1603 has been allocated, which happens in reginfo.c during register
1604 allocation. */
1605 #define REGNO_OK_FOR_BASE_P(REGNO) \
1606 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1607 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1608 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1609 (TARGET_SHMEDIA \
1610 ? (GENERAL_REGISTER_P (REGNO) \
1611 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1612 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1613
1614 /* Maximum number of registers that can appear in a valid memory
1615 address. */
1616 #define MAX_REGS_PER_ADDRESS 2
1617
1618 /* Recognize any constant value that is a valid address. */
1619 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1620
1621 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1622 and check its validity for a certain class.
1623 The suitable hard regs are always accepted and all pseudo regs
1624 are also accepted if STRICT is not set. */
1625
1626 /* Nonzero if X is a reg that can be used as a base reg. */
1627 #define REG_OK_FOR_BASE_P(X, STRICT) \
1628 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1629 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1630
1631 /* Nonzero if X is a reg that can be used as an index. */
1632 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1633 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1634 : REGNO (X) == R0_REG) \
1635 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1636
1637 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1638 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1639 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1640 : REGNO (X) == R0_REG && OFFSET == 0) \
1641 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1642
1643 /* Macros for extra constraints. */
1644
1645 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1646 ((GET_CODE ((OP)) == LABEL_REF) \
1647 || (GET_CODE ((OP)) == CONST \
1648 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1649 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1650 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1651
1652 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1653 (CONSTANT_P (OP) \
1654 && !CONST_INT_P (OP) \
1655 && GET_CODE (OP) != CONST_DOUBLE \
1656 && (!flag_pic \
1657 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1658 && !PIC_ADDR_P (OP) \
1659 && GET_CODE (OP) != LABEL_REF)))
1660
1661 /* Check whether OP is a datalabel unspec. */
1662 #define DATALABEL_REF_NO_CONST_P(OP) \
1663 (GET_CODE (OP) == UNSPEC \
1664 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1665 && XVECLEN ((OP), 0) == 1 \
1666 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1667
1668 #define GOT_ENTRY_P(OP) \
1669 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1670 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1671
1672 #define GOTPLT_ENTRY_P(OP) \
1673 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1674 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1675
1676 #define UNSPEC_GOTOFF_P(OP) \
1677 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1678
1679 #define GOTOFF_P(OP) \
1680 (GET_CODE (OP) == CONST \
1681 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1682 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1683 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1684 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1685
1686 #define PIC_ADDR_P(OP) \
1687 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1688 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1689
1690 #define PCREL_SYMOFF_P(OP) \
1691 (GET_CODE (OP) == CONST \
1692 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1693 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1694
1695 #define NON_PIC_REFERENCE_P(OP) \
1696 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1697 || (GET_CODE (OP) == CONST \
1698 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1699 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1700 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1701 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1702 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1703 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1704 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1705 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1706
1707 #define PIC_REFERENCE_P(OP) \
1708 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1709 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1710
1711 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1712 (flag_pic \
1713 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1714 || PCREL_SYMOFF_P (OP)) \
1715 : NON_PIC_REFERENCE_P (OP))
1716 \f
1717 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1718 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1719 || (GET_CODE (X) == SUBREG \
1720 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1721 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1722 && REG_P (SUBREG_REG (X)) \
1723 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1724
1725 /* Since this must be r0, which is a single register class, we must check
1726 SUBREGs more carefully, to be sure that we don't accept one that extends
1727 outside the class. */
1728 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1729 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1730 || (GET_CODE (X) == SUBREG \
1731 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1732 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1733 && REG_P (SUBREG_REG (X)) \
1734 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1735
1736 #ifdef REG_OK_STRICT
1737 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1738 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1739 #else
1740 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1741 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1742 #endif
1743
1744 #define ALLOW_INDEXED_ADDRESS \
1745 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1746 \f
1747 /* A C compound statement that attempts to replace X, which is an address
1748 that needs reloading, with a valid memory address for an operand of
1749 mode MODE. WIN is a C statement label elsewhere in the code. */
1750 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1751 do { \
1752 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1753 goto WIN; \
1754 } while (0)
1755 \f
1756 /* Specify the machine mode that this machine uses
1757 for the index in the tablejump instruction. */
1758 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1759
1760 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1761 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1762 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1763 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1764 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1765 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1766 : SImode)
1767
1768 /* Define as C expression which evaluates to nonzero if the tablejump
1769 instruction expects the table to contain offsets from the address of the
1770 table.
1771 Do not define this if the table should contain absolute addresses. */
1772 #define CASE_VECTOR_PC_RELATIVE 1
1773
1774 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1775 #define FLOAT_TYPE_SIZE 32
1776
1777 /* Since the SH2e has only `float' support, it is desirable to make all
1778 floating point types equivalent to `float'. */
1779 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE)\
1780 ? 32 : 64)
1781
1782 /* 'char' is signed by default. */
1783 #define DEFAULT_SIGNED_CHAR 1
1784
1785 /* The type of size_t unsigned int. */
1786 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
1787
1788 #undef PTRDIFF_TYPE
1789 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
1790
1791 #define WCHAR_TYPE "short unsigned int"
1792 #define WCHAR_TYPE_SIZE 16
1793
1794 #define SH_ELF_WCHAR_TYPE "long int"
1795
1796 /* Max number of bytes we can move from memory to memory
1797 in one reasonably fast instruction. */
1798 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
1799
1800 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1801 MOVE_MAX is not a compile-time constant. */
1802 #define MAX_MOVE_MAX 8
1803
1804 /* Max number of bytes we want move_by_pieces to be able to copy
1805 efficiently. */
1806 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
1807
1808 /* Define if operations between registers always perform the operation
1809 on the full register even if a narrower mode is specified. */
1810 #define WORD_REGISTER_OPERATIONS
1811
1812 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1813 will either zero-extend or sign-extend. The value of this macro should
1814 be the code that says which one of the two operations is implicitly
1815 done, UNKNOWN if none.
1816 For SHmedia, we can truncate to QImode easier using zero extension.
1817 FP registers can load SImode values, but don't implicitly sign-extend
1818 them to DImode. */
1819 #define LOAD_EXTEND_OP(MODE) \
1820 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
1821 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
1822
1823 /* Define if loading short immediate values into registers sign extends. */
1824 #define SHORT_IMMEDIATES_SIGN_EXTEND
1825
1826 /* Nonzero if access to memory by bytes is no faster than for words. */
1827 #define SLOW_BYTE_ACCESS 1
1828
1829 /* Nonzero if the target supports dynamic shift instructions
1830 like shad and shld. */
1831 #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
1832
1833 /* The cost of using the dynamic shift insns (shad, shld) are the same
1834 if they are available. If they are not available a library function will
1835 be emitted instead, which is more expensive. */
1836 #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20)
1837
1838 /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like
1839 (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1840 This is not generally true when hardware dynamic shifts (shad, shld) are
1841 used, because they check the sign bit _before_ the modulo op. The sign
1842 bit determines whether it is a left shift or a right shift:
1843 if (Y < 0)
1844 return X << (Y & 31);
1845 else
1846 return X >> (-Y) & 31);
1847
1848 The dynamic shift library routines in lib1funcs.S do not use the sign bit
1849 like the hardware dynamic shifts and truncate the shift count to 31.
1850 We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count
1851 truncation in the library function call patterns, as this gives slightly
1852 more compact code. */
1853 #define SHIFT_COUNT_TRUNCATED (0)
1854
1855 /* All integers have the same format so truncation is easy. */
1856 /* But SHmedia must sign-extend DImode when truncating to SImode. */
1857 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
1858 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
1859
1860 /* Define this if addresses of constant functions
1861 shouldn't be put through pseudo regs where they can be cse'd.
1862 Desirable on machines where ordinary constants are expensive
1863 but a CALL with constant address is cheap. */
1864 /*#define NO_FUNCTION_CSE 1*/
1865
1866 /* The machine modes of pointers and functions. */
1867 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
1868 #define FUNCTION_MODE Pmode
1869
1870 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1871 are actually function calls with some special constraints on arguments
1872 and register usage.
1873
1874 These macros tell reorg that the references to arguments and
1875 register clobbers for insns of type sfunc do not appear to happen
1876 until after the millicode call. This allows reorg to put insns
1877 which set the argument registers into the delay slot of the millicode
1878 call -- thus they act more like traditional CALL_INSNs.
1879
1880 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1881 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1882 in particular. */
1883
1884 #define INSN_SETS_ARE_DELAYED(X) \
1885 ((NONJUMP_INSN_P (X) \
1886 && GET_CODE (PATTERN (X)) != SEQUENCE \
1887 && GET_CODE (PATTERN (X)) != USE \
1888 && GET_CODE (PATTERN (X)) != CLOBBER \
1889 && get_attr_is_sfunc (X)))
1890
1891 #define INSN_REFERENCES_ARE_DELAYED(X) \
1892 ((NONJUMP_INSN_P (X) \
1893 && GET_CODE (PATTERN (X)) != SEQUENCE \
1894 && GET_CODE (PATTERN (X)) != USE \
1895 && GET_CODE (PATTERN (X)) != CLOBBER \
1896 && get_attr_is_sfunc (X)))
1897
1898 \f
1899 /* Position Independent Code. */
1900
1901 /* We can't directly access anything that contains a symbol,
1902 nor can we indirect via the constant pool. */
1903 #define LEGITIMATE_PIC_OPERAND_P(X) \
1904 ((! nonpic_symbol_mentioned_p (X) \
1905 && (GET_CODE (X) != SYMBOL_REF \
1906 || ! CONSTANT_POOL_ADDRESS_P (X) \
1907 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
1908 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
1909
1910 #define SYMBOLIC_CONST_P(X) \
1911 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1912 && nonpic_symbol_mentioned_p (X))
1913 \f
1914 /* Compute extra cost of moving data between one register class
1915 and another. */
1916
1917 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
1918 uses this information. Hence, the general register <-> floating point
1919 register information here is not used for SFmode. */
1920 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
1921 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
1922 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
1923
1924 #define REGCLASS_HAS_FP_REG(CLASS) \
1925 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
1926 || (CLASS) == DF_REGS)
1927
1928 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1929 would be so that people with slow memory systems could generate
1930 different code that does fewer memory accesses. */
1931
1932 /* A C expression for the cost of a branch instruction. A value of 1
1933 is the default; other values are interpreted relative to that. */
1934 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost
1935 \f
1936 /* Assembler output control. */
1937
1938 /* A C string constant describing how to begin a comment in the target
1939 assembler language. The compiler assumes that the comment will end at
1940 the end of the line. */
1941 #define ASM_COMMENT_START "!"
1942
1943 #define ASM_APP_ON ""
1944 #define ASM_APP_OFF ""
1945 #define FILE_ASM_OP "\t.file\n"
1946 #define SET_ASM_OP "\t.set\t"
1947
1948 /* How to change between sections. */
1949 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 \
1950 ? "\t.section\t.text..SHmedia32,\"ax\"" \
1951 : "\t.text")
1952 #define DATA_SECTION_ASM_OP "\t.data"
1953
1954 #if defined CRT_BEGIN || defined CRT_END
1955 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
1956 # undef TEXT_SECTION_ASM_OP
1957 # if __SHMEDIA__ == 1 && __SH5__ == 32
1958 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
1959 # else
1960 # define TEXT_SECTION_ASM_OP "\t.text"
1961 # endif
1962 #endif
1963
1964 #ifndef BSS_SECTION_ASM_OP
1965 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1966 #endif
1967
1968 #ifndef ASM_OUTPUT_ALIGNED_BSS
1969 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1970 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1971 #endif
1972
1973 /* Define this so that jump tables go in same section as the current function,
1974 which could be text or it could be a user defined section. */
1975 #define JUMP_TABLES_IN_TEXT_SECTION 1
1976
1977 #undef DO_GLOBAL_CTORS_BODY
1978 #define DO_GLOBAL_CTORS_BODY \
1979 { \
1980 typedef void (*pfunc) (void); \
1981 extern pfunc __ctors[]; \
1982 extern pfunc __ctors_end[]; \
1983 pfunc *p; \
1984 for (p = __ctors_end; p > __ctors; ) \
1985 { \
1986 (*--p)(); \
1987 } \
1988 }
1989
1990 #undef DO_GLOBAL_DTORS_BODY
1991 #define DO_GLOBAL_DTORS_BODY \
1992 { \
1993 typedef void (*pfunc) (void); \
1994 extern pfunc __dtors[]; \
1995 extern pfunc __dtors_end[]; \
1996 pfunc *p; \
1997 for (p = __dtors; p < __dtors_end; p++) \
1998 { \
1999 (*p)(); \
2000 } \
2001 }
2002
2003 #define ASM_OUTPUT_REG_PUSH(file, v) \
2004 { \
2005 if (TARGET_SHMEDIA) \
2006 { \
2007 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2008 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2009 } \
2010 else \
2011 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2012 }
2013
2014 #define ASM_OUTPUT_REG_POP(file, v) \
2015 { \
2016 if (TARGET_SHMEDIA) \
2017 { \
2018 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2019 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2020 } \
2021 else \
2022 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2023 }
2024
2025 /* DBX register number for a given compiler register number. */
2026 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2027 to match gdb. */
2028 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2029 register exists, so we should return -1 for invalid register numbers. */
2030 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2031
2032 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2033 used to use the encodings 245..260, but that doesn't make sense:
2034 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2035 the FP registers stay the same when switching between compact and media
2036 mode. Hence, we also need to use the same dwarf frame columns.
2037 Likewise, we need to support unwind information for SHmedia registers
2038 even in compact code. */
2039 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2040 (IN_RANGE ((REGNO), \
2041 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2042 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2043 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2044 : ((int) (REGNO) >= FIRST_FP_REG \
2045 && ((int) (REGNO) \
2046 <= (FIRST_FP_REG + \
2047 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2048 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2049 + (TARGET_SH5 ? 77 : 25)) \
2050 : XD_REGISTER_P (REGNO) \
2051 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2052 : TARGET_REGISTER_P (REGNO) \
2053 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2054 : (REGNO) == PR_REG \
2055 ? (TARGET_SH5 ? 18 : 17) \
2056 : (REGNO) == PR_MEDIA_REG \
2057 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2058 : (REGNO) == GBR_REG \
2059 ? (TARGET_SH5 ? 238 : 18) \
2060 : (REGNO) == MACH_REG \
2061 ? (TARGET_SH5 ? 239 : 20) \
2062 : (REGNO) == MACL_REG \
2063 ? (TARGET_SH5 ? 240 : 21) \
2064 : (REGNO) == T_REG \
2065 ? (TARGET_SH5 ? 242 : 22) \
2066 : (REGNO) == FPUL_REG \
2067 ? (TARGET_SH5 ? 244 : 23) \
2068 : (REGNO) == FPSCR_REG \
2069 ? (TARGET_SH5 ? 243 : 24) \
2070 : (unsigned) -1)
2071
2072 /* This is how to output a reference to a symbol_ref. On SH5,
2073 references to non-code symbols must be preceded by `datalabel'. */
2074 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2075 do \
2076 { \
2077 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2078 fputs ("datalabel ", (FILE)); \
2079 assemble_name ((FILE), XSTR ((SYM), 0)); \
2080 } \
2081 while (0)
2082
2083 /* This is how to output an assembler line
2084 that says to advance the location counter
2085 to a multiple of 2**LOG bytes. */
2086
2087 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2088 if ((LOG) != 0) \
2089 fprintf ((FILE), "\t.align %d\n", (LOG))
2090
2091 /* Globalizing directive for a label. */
2092 #define GLOBAL_ASM_OP "\t.global\t"
2093
2094 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2095
2096 /* Output a relative address table. */
2097 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2098 switch (GET_MODE (BODY)) \
2099 { \
2100 case SImode: \
2101 if (TARGET_SH5) \
2102 { \
2103 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2104 (VALUE), (REL)); \
2105 break; \
2106 } \
2107 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2108 break; \
2109 case HImode: \
2110 if (TARGET_SH5) \
2111 { \
2112 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2113 (VALUE), (REL)); \
2114 break; \
2115 } \
2116 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2117 break; \
2118 case QImode: \
2119 if (TARGET_SH5) \
2120 { \
2121 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2122 (VALUE), (REL)); \
2123 break; \
2124 } \
2125 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2126 break; \
2127 default: \
2128 break; \
2129 }
2130
2131 /* Output an absolute table element. */
2132 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2133 if (! optimize || TARGET_BIGTABLE) \
2134 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2135 else \
2136 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2137
2138 \f
2139 /* A C statement to be executed just prior to the output of
2140 assembler code for INSN, to modify the extracted operands so
2141 they will be output differently.
2142
2143 Here the argument OPVEC is the vector containing the operands
2144 extracted from INSN, and NOPERANDS is the number of elements of
2145 the vector which contain meaningful data for this insn.
2146 The contents of this vector are what will be used to convert the insn
2147 template into assembler code, so you can change the assembler output
2148 by changing the contents of the vector. */
2149 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2150 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2151
2152 \f
2153 extern rtx sh_compare_op0;
2154 extern rtx sh_compare_op1;
2155
2156 /* Which processor to schedule for. The elements of the enumeration must
2157 match exactly the cpu attribute in the sh.md file. */
2158 enum processor_type {
2159 PROCESSOR_SH1,
2160 PROCESSOR_SH2,
2161 PROCESSOR_SH2E,
2162 PROCESSOR_SH2A,
2163 PROCESSOR_SH3,
2164 PROCESSOR_SH3E,
2165 PROCESSOR_SH4,
2166 PROCESSOR_SH4A,
2167 PROCESSOR_SH5
2168 };
2169
2170 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2171 extern enum processor_type sh_cpu;
2172
2173 enum mdep_reorg_phase_e
2174 {
2175 SH_BEFORE_MDEP_REORG,
2176 SH_INSERT_USES_LABELS,
2177 SH_SHORTEN_BRANCHES0,
2178 SH_FIXUP_PCLOAD,
2179 SH_SHORTEN_BRANCHES1,
2180 SH_AFTER_MDEP_REORG
2181 };
2182
2183 extern enum mdep_reorg_phase_e mdep_reorg_phase;
2184
2185 /* Handle Renesas compiler's pragmas. */
2186 #define REGISTER_TARGET_PRAGMAS() do { \
2187 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2188 c_register_pragma (0, "trapa", sh_pr_trapa); \
2189 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2190 } while (0)
2191
2192 extern tree sh_deferred_function_attributes;
2193 extern tree *sh_deferred_function_attributes_tail;
2194
2195 /* Set when processing a function with interrupt attribute. */
2196 extern int current_function_interrupt;
2197
2198 \f
2199 /* Instructions with unfilled delay slots take up an
2200 extra two bytes for the nop in the delay slot.
2201 sh-dsp parallel processing insns are four bytes long. */
2202 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2203 (LENGTH) += sh_insn_length_adjustment (X);
2204 \f
2205 /* Define this macro if it is advisable to hold scalars in registers
2206 in a wider mode than that declared by the program. In such cases,
2207 the value is constrained to be within the bounds of the declared
2208 type, but kept valid in the wider mode. The signedness of the
2209 extension may differ from that of the type.
2210
2211 Leaving the unsignedp unchanged gives better code than always setting it
2212 to 0. This is despite the fact that we have only signed char and short
2213 load instructions. */
2214 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2215 if (GET_MODE_CLASS (MODE) == MODE_INT \
2216 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2217 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2218 (MODE) = (TARGET_SH1 ? SImode \
2219 : TARGET_SHMEDIA32 ? SImode : DImode);
2220
2221 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2222
2223 /* Better to allocate once the maximum space for outgoing args in the
2224 prologue rather than duplicate around each call. */
2225 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2226
2227 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2228
2229 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2230
2231 #define ACTUAL_NORMAL_MODE(ENTITY) \
2232 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2233
2234 #define NORMAL_MODE(ENTITY) \
2235 (sh_cfun_interrupt_handler_p () \
2236 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2237 : ACTUAL_NORMAL_MODE (ENTITY))
2238
2239 #define MODE_ENTRY(ENTITY) NORMAL_MODE (ENTITY)
2240
2241 #define MODE_EXIT(ENTITY) \
2242 (sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (ENTITY))
2243
2244 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2245 && (REGNO) == FPSCR_REG)
2246
2247 #define MODE_NEEDED(ENTITY, INSN) \
2248 (recog_memoized (INSN) >= 0 \
2249 ? get_attr_fp_mode (INSN) \
2250 : FP_MODE_NONE)
2251
2252 #define MODE_AFTER(ENTITY, MODE, INSN) \
2253 (TARGET_HITACHI \
2254 && recog_memoized (INSN) >= 0 \
2255 && get_attr_fp_set (INSN) != FP_SET_NONE \
2256 ? (int) get_attr_fp_set (INSN) \
2257 : (MODE))
2258
2259 #define MODE_PRIORITY_TO_MODE(ENTITY, N) \
2260 ((TARGET_FPU_SINGLE != 0) ^ (N) ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2261
2262 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \
2263 fpscr_set_from_mem ((MODE), (HARD_REGS_LIVE))
2264
2265 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2266 sh_can_redirect_branch ((INSN), (SEQ))
2267
2268 #define DWARF_FRAME_RETURN_COLUMN \
2269 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2270
2271 #define EH_RETURN_DATA_REGNO(N) \
2272 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2273
2274 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2275 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2276
2277 /* We have to distinguish between code and data, so that we apply
2278 datalabel where and only where appropriate. Use sdataN for data. */
2279 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2280 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2281 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2282 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2283
2284 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2285 indirect are handled automatically. */
2286 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2287 do { \
2288 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2289 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2290 { \
2291 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2292 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2293 if (0) goto DONE; \
2294 } \
2295 } while (0)
2296
2297 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2298 /* SH constant pool breaks the devices in crtstuff.c to control section
2299 in where code resides. We have to write it as asm code. */
2300 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2301 asm (SECTION_OP "\n\
2302 mov.l 1f,r1\n\
2303 mova 2f,r0\n\
2304 braf r1\n\
2305 lds r0,pr\n\
2306 0: .p2align 2\n\
2307 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2308 2:\n" TEXT_SECTION_ASM_OP);
2309 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2310
2311 #endif /* ! GCC_SH_H */
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