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mips.h (ISA_HAS_DSP, [...]): New macros.
[official-gcc.git] / gcc / config / mips / mips.h
blob169779ce1ee22d838a4f296bb61b421e5784c8eb
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_M4K,
51 PROCESSOR_R3900,
52 PROCESSOR_R6000,
53 PROCESSOR_R4000,
54 PROCESSOR_R4100,
55 PROCESSOR_R4111,
56 PROCESSOR_R4120,
57 PROCESSOR_R4130,
58 PROCESSOR_R4300,
59 PROCESSOR_R4600,
60 PROCESSOR_R4650,
61 PROCESSOR_R5000,
62 PROCESSOR_R5400,
63 PROCESSOR_R5500,
64 PROCESSOR_R7000,
65 PROCESSOR_R8000,
66 PROCESSOR_R9000,
67 PROCESSOR_SB1,
68 PROCESSOR_SB1A,
69 PROCESSOR_SR71000,
70 PROCESSOR_MAX
71 };
72
73 /* Costs of various operations on the different architectures. */
74
75 struct mips_rtx_cost_data
76 {
77 unsigned short fp_add;
78 unsigned short fp_mult_sf;
79 unsigned short fp_mult_df;
80 unsigned short fp_div_sf;
81 unsigned short fp_div_df;
82 unsigned short int_mult_si;
83 unsigned short int_mult_di;
84 unsigned short int_div_si;
85 unsigned short int_div_di;
86 unsigned short branch_cost;
87 unsigned short memory_latency;
88 };
89
90 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
91 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
92 to work on a 64-bit machine. */
93
94 #define ABI_32 0
95 #define ABI_N32 1
96 #define ABI_64 2
97 #define ABI_EABI 3
98 #define ABI_O64 4
99
100 /* Information about one recognized processor. Defined here for the
101 benefit of TARGET_CPU_CPP_BUILTINS. */
102 struct mips_cpu_info {
103 /* The 'canonical' name of the processor as far as GCC is concerned.
104 It's typically a manufacturer's prefix followed by a numerical
105 designation. It should be lowercase. */
106 const char *name;
107
108 /* The internal processor number that most closely matches this
109 entry. Several processors can have the same value, if there's no
110 difference between them from GCC's point of view. */
111 enum processor_type cpu;
112
113 /* The ISA level that the processor implements. */
114 int isa;
115 };
116
117 /* Enumerates the setting of the -mcode-readable option. */
118 enum mips_code_readable_setting {
119 CODE_READABLE_NO,
120 CODE_READABLE_PCREL,
121 CODE_READABLE_YES
122 };
123
124
125 /* Enumerates the setting of the -mllsc option. */
126 enum mips_llsc_setting {
127 LLSC_DEFAULT,
128 LLSC_NO,
129 LLSC_YES
130 };
131
132 #ifndef USED_FOR_TARGET
133 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
134 extern const char *current_function_file; /* filename current function is in */
135 extern int num_source_filenames; /* current .file # */
136 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
137 extern int sym_lineno; /* sgi next label # for each stmt */
138 extern int set_noreorder; /* # of nested .set noreorder's */
139 extern int set_nomacro; /* # of nested .set nomacro's */
140 extern int set_noat; /* # of nested .set noat's */
141 extern int set_volatile; /* # of nested .set volatile's */
142 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
143 extern int mips_dbx_regno[];
144 extern int mips_dwarf_regno[];
145 extern bool mips_split_p[];
146 extern GTY(()) rtx cmp_operands[2];
147 extern enum processor_type mips_arch; /* which cpu to codegen for */
148 extern enum processor_type mips_tune; /* which cpu to schedule for */
149 extern int mips_isa; /* architectural level */
150 extern int mips_abi; /* which ABI to use */
151 extern const struct mips_cpu_info mips_cpu_info_table[];
152 extern const struct mips_cpu_info *mips_arch_info;
153 extern const struct mips_cpu_info *mips_tune_info;
154 extern const struct mips_rtx_cost_data *mips_cost;
155 extern enum mips_code_readable_setting mips_code_readable;
156 extern enum mips_llsc_setting mips_llsc;
157 #endif
158
159 /* Macros to silence warnings about numbers being signed in traditional
160 C and unsigned in ISO C when compiled on 32-bit hosts. */
161
162 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
163 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
164 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
165
166 \f
167 /* Run-time compilation parameters selecting different hardware subsets. */
168
169 /* True if we are generating position-independent VxWorks RTP code. */
170 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
171
172 /* True if the call patterns should be split into a jalr followed by
173 an instruction to restore $gp. It is only safe to split the load
174 from the call when every use of $gp is explicit. */
175
176 #define TARGET_SPLIT_CALLS \
177 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
178
179 /* True if we're generating a form of -mabicalls in which we can use
180 operators like %hi and %lo to refer to locally-binding symbols.
181 We can only do this for -mno-shared, and only then if we can use
182 relocation operations instead of assembly macros. It isn't really
183 worth using absolute sequences for 64-bit symbols because GOT
184 accesses are so much shorter. */
185
186 #define TARGET_ABSOLUTE_ABICALLS \
187 (TARGET_ABICALLS \
188 && !TARGET_SHARED \
189 && TARGET_EXPLICIT_RELOCS \
190 && !ABI_HAS_64BIT_SYMBOLS)
191
192 /* True if we can optimize sibling calls. For simplicity, we only
193 handle cases in which call_insn_operand will reject invalid
194 sibcall addresses. There are two cases in which this isn't true:
195
196 - TARGET_MIPS16. call_insn_operand accepts constant addresses
197 but there is no direct jump instruction. It isn't worth
198 using sibling calls in this case anyway; they would usually
199 be longer than normal calls.
200
201 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
202 accepts global constants, but all sibcalls must be indirect. */
203 #define TARGET_SIBCALLS \
204 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
205
206 /* True if we need to use a global offset table to access some symbols. */
207 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
208
209 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
210 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
211
212 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
213 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
214
215 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
216 This is true for both the PIC and non-PIC VxWorks RTP modes. */
217 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
218
219 /* True if .gpword or .gpdword should be used for switch tables.
220
221 Although GAS does understand .gpdword, the SGI linker mishandles
222 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
223 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
224 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
225
226 /* Generate mips16 code */
227 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
228 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
229 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
230 /* Generate mips16e register save/restore sequences. */
231 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
232
233 /* True if we're generating a form of MIPS16 code in which general
234 text loads are allowed. */
235 #define TARGET_MIPS16_TEXT_LOADS \
236 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
237
238 /* True if we're generating a form of MIPS16 code in which PC-relative
239 loads are allowed. */
240 #define TARGET_MIPS16_PCREL_LOADS \
241 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
242
243 /* Generic ISA defines. */
244 #define ISA_MIPS1 (mips_isa == 1)
245 #define ISA_MIPS2 (mips_isa == 2)
246 #define ISA_MIPS3 (mips_isa == 3)
247 #define ISA_MIPS4 (mips_isa == 4)
248 #define ISA_MIPS32 (mips_isa == 32)
249 #define ISA_MIPS32R2 (mips_isa == 33)
250 #define ISA_MIPS64 (mips_isa == 64)
251
252 /* Architecture target defines. */
253 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
254 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
255 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
256 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
257 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
258 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
259 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
260 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
261 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
262 || mips_arch == PROCESSOR_SB1A)
263 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
264
265 /* Scheduling target defines. */
266 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
267 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
268 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
269 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
270 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
271 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
272 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
273 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
274 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
275 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
276 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
277 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
278 || mips_tune == PROCESSOR_SB1A)
279 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
280 || mips_tune == PROCESSOR_24KF2_1 \
281 || mips_tune == PROCESSOR_24KF1_1)
282 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
283 || mips_tune == PROCESSOR_74KF2_1 \
284 || mips_tune == PROCESSOR_74KF1_1 \
285 || mips_tune == PROCESSOR_74KF3_2)
286 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
287
288 /* True if the pre-reload scheduler should try to create chains of
289 multiply-add or multiply-subtract instructions. For example,
290 suppose we have:
291
292 t1 = a * b
293 t2 = t1 + c * d
294 t3 = e * f
295 t4 = t3 - g * h
296
297 t1 will have a higher priority than t2 and t3 will have a higher
298 priority than t4. However, before reload, there is no dependence
299 between t1 and t3, and they can often have similar priorities.
300 The scheduler will then tend to prefer:
301
302 t1 = a * b
303 t3 = e * f
304 t2 = t1 + c * d
305 t4 = t3 - g * h
306
307 which stops us from making full use of macc/madd-style instructions.
308 This sort of situation occurs frequently in Fourier transforms and
309 in unrolled loops.
310
311 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
312 queue so that chained multiply-add and multiply-subtract instructions
313 appear ahead of any other instruction that is likely to clobber lo.
314 In the example above, if t2 and t3 become ready at the same time,
315 the code ensures that t2 is scheduled first.
316
317 Multiply-accumulate instructions are a bigger win for some targets
318 than others, so this macro is defined on an opt-in basis. */
319 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
320 || TUNE_MIPS4120 \
321 || TUNE_MIPS4130 \
322 || TUNE_24K)
323
324 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
325 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
326
327 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
328 directly accessible, while the command-line options select
329 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
330 in use. */
331 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
332 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
333
334 /* IRIX specific stuff. */
335 #define TARGET_IRIX 0
336 #define TARGET_IRIX6 0
337
338 /* Define preprocessor macros for the -march and -mtune options.
339 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
340 processor. If INFO's canonical name is "foo", define PREFIX to
341 be "foo", and define an additional macro PREFIX_FOO. */
342 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
343 do \
344 { \
345 char *macro, *p; \
346 \
347 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
348 for (p = macro; *p != 0; p++) \
349 *p = TOUPPER (*p); \
350 \
351 builtin_define (macro); \
352 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
353 free (macro); \
354 } \
355 while (0)
356
357 /* Target CPU builtins. */
358 #define TARGET_CPU_CPP_BUILTINS() \
359 do \
360 { \
361 /* Everyone but IRIX defines this to mips. */ \
362 if (!TARGET_IRIX) \
363 builtin_assert ("machine=mips"); \
364 \
365 builtin_assert ("cpu=mips"); \
366 builtin_define ("__mips__"); \
367 builtin_define ("_mips"); \
368 \
369 /* We do this here because __mips is defined below and so we \
370 can't use builtin_define_std. We don't ever want to define \
371 "mips" for VxWorks because some of the VxWorks headers \
372 construct include filenames from a root directory macro, \
373 an architecture macro and a filename, where the architecture \
374 macro expands to 'mips'. If we define 'mips' to 1, the \
375 architecture macro expands to 1 as well. */ \
376 if (!flag_iso && !TARGET_VXWORKS) \
377 builtin_define ("mips"); \
378 \
379 if (TARGET_64BIT) \
380 builtin_define ("__mips64"); \
381 \
382 if (!TARGET_IRIX) \
383 { \
384 /* Treat _R3000 and _R4000 like register-size \
385 defines, which is how they've historically \
386 been used. */ \
387 if (TARGET_64BIT) \
388 { \
389 builtin_define_std ("R4000"); \
390 builtin_define ("_R4000"); \
391 } \
392 else \
393 { \
394 builtin_define_std ("R3000"); \
395 builtin_define ("_R3000"); \
396 } \
397 } \
398 if (TARGET_FLOAT64) \
399 builtin_define ("__mips_fpr=64"); \
400 else \
401 builtin_define ("__mips_fpr=32"); \
402 \
403 if (TARGET_MIPS16) \
404 builtin_define ("__mips16"); \
405 \
406 if (TARGET_MIPS3D) \
407 builtin_define ("__mips3d"); \
408 \
409 if (TARGET_SMARTMIPS) \
410 builtin_define ("__mips_smartmips"); \
411 \
412 if (TARGET_DSP) \
413 { \
414 builtin_define ("__mips_dsp"); \
415 if (TARGET_DSPR2) \
416 { \
417 builtin_define ("__mips_dspr2"); \
418 builtin_define ("__mips_dsp_rev=2"); \
419 } \
420 else \
421 builtin_define ("__mips_dsp_rev=1"); \
422 } \
423 \
424 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
425 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
426 \
427 if (ISA_MIPS1) \
428 { \
429 builtin_define ("__mips=1"); \
430 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
431 } \
432 else if (ISA_MIPS2) \
433 { \
434 builtin_define ("__mips=2"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
436 } \
437 else if (ISA_MIPS3) \
438 { \
439 builtin_define ("__mips=3"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
441 } \
442 else if (ISA_MIPS4) \
443 { \
444 builtin_define ("__mips=4"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
446 } \
447 else if (ISA_MIPS32) \
448 { \
449 builtin_define ("__mips=32"); \
450 builtin_define ("__mips_isa_rev=1"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
452 } \
453 else if (ISA_MIPS32R2) \
454 { \
455 builtin_define ("__mips=32"); \
456 builtin_define ("__mips_isa_rev=2"); \
457 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
458 } \
459 else if (ISA_MIPS64) \
460 { \
461 builtin_define ("__mips=64"); \
462 builtin_define ("__mips_isa_rev=1"); \
463 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
464 } \
465 \
466 switch (mips_abi) \
467 { \
468 case ABI_32: \
469 builtin_define ("_ABIO32=1"); \
470 builtin_define ("_MIPS_SIM=_ABIO32"); \
471 break; \
472 \
473 case ABI_N32: \
474 builtin_define ("_ABIN32=2"); \
475 builtin_define ("_MIPS_SIM=_ABIN32"); \
476 break; \
477 \
478 case ABI_64: \
479 builtin_define ("_ABI64=3"); \
480 builtin_define ("_MIPS_SIM=_ABI64"); \
481 break; \
482 \
483 case ABI_O64: \
484 builtin_define ("_ABIO64=4"); \
485 builtin_define ("_MIPS_SIM=_ABIO64"); \
486 break; \
487 } \
488 \
489 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
490 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
491 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
492 builtin_define_with_int_value ("_MIPS_FPSET", \
493 32 / MAX_FPRS_PER_FMT); \
494 \
495 /* These defines reflect the ABI in use, not whether the \
496 FPU is directly accessible. */ \
497 if (TARGET_HARD_FLOAT_ABI) \
498 builtin_define ("__mips_hard_float"); \
499 else \
500 builtin_define ("__mips_soft_float"); \
501 \
502 if (TARGET_SINGLE_FLOAT) \
503 builtin_define ("__mips_single_float"); \
504 \
505 if (TARGET_PAIRED_SINGLE_FLOAT) \
506 builtin_define ("__mips_paired_single_float"); \
507 \
508 if (TARGET_BIG_ENDIAN) \
509 { \
510 builtin_define_std ("MIPSEB"); \
511 builtin_define ("_MIPSEB"); \
512 } \
513 else \
514 { \
515 builtin_define_std ("MIPSEL"); \
516 builtin_define ("_MIPSEL"); \
517 } \
518 \
519 /* Macros dependent on the C dialect. */ \
520 if (preprocessing_asm_p ()) \
521 { \
522 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
523 builtin_define ("_LANGUAGE_ASSEMBLY"); \
524 } \
525 else if (c_dialect_cxx ()) \
526 { \
527 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
528 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
529 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
530 } \
531 else \
532 { \
533 builtin_define_std ("LANGUAGE_C"); \
534 builtin_define ("_LANGUAGE_C"); \
535 } \
536 if (c_dialect_objc ()) \
537 { \
538 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
539 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
540 /* Bizarre, but needed at least for Irix. */ \
541 builtin_define_std ("LANGUAGE_C"); \
542 builtin_define ("_LANGUAGE_C"); \
543 } \
544 \
545 if (mips_abi == ABI_EABI) \
546 builtin_define ("__mips_eabi"); \
547 } \
548 while (0)
549
550 /* Default target_flags if no switches are specified */
551
552 #ifndef TARGET_DEFAULT
553 #define TARGET_DEFAULT 0
554 #endif
555
556 #ifndef TARGET_CPU_DEFAULT
557 #define TARGET_CPU_DEFAULT 0
558 #endif
559
560 #ifndef TARGET_ENDIAN_DEFAULT
561 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
562 #endif
563
564 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
565 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
566 #endif
567
568 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
569 #ifndef MIPS_ISA_DEFAULT
570 #ifndef MIPS_CPU_STRING_DEFAULT
571 #define MIPS_CPU_STRING_DEFAULT "from-abi"
572 #endif
573 #endif
574
575 #ifdef IN_LIBGCC2
576 #undef TARGET_64BIT
577 /* Make this compile time constant for libgcc2 */
578 #ifdef __mips64
579 #define TARGET_64BIT 1
580 #else
581 #define TARGET_64BIT 0
582 #endif
583 #endif /* IN_LIBGCC2 */
584
585 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
586 when compiled with hardware floating point. This is because MIPS16
587 code cannot save and restore the floating-point registers, which is
588 important if in a mixed MIPS16/non-MIPS16 environment. */
589
590 #ifdef IN_LIBGCC2
591 #if __mips_hard_float
592 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
593 #endif
594 #endif /* IN_LIBGCC2 */
595
596 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
597
598 #ifndef MULTILIB_ENDIAN_DEFAULT
599 #if TARGET_ENDIAN_DEFAULT == 0
600 #define MULTILIB_ENDIAN_DEFAULT "EL"
601 #else
602 #define MULTILIB_ENDIAN_DEFAULT "EB"
603 #endif
604 #endif
605
606 #ifndef MULTILIB_ISA_DEFAULT
607 # if MIPS_ISA_DEFAULT == 1
608 # define MULTILIB_ISA_DEFAULT "mips1"
609 # else
610 # if MIPS_ISA_DEFAULT == 2
611 # define MULTILIB_ISA_DEFAULT "mips2"
612 # else
613 # if MIPS_ISA_DEFAULT == 3
614 # define MULTILIB_ISA_DEFAULT "mips3"
615 # else
616 # if MIPS_ISA_DEFAULT == 4
617 # define MULTILIB_ISA_DEFAULT "mips4"
618 # else
619 # if MIPS_ISA_DEFAULT == 32
620 # define MULTILIB_ISA_DEFAULT "mips32"
621 # else
622 # if MIPS_ISA_DEFAULT == 33
623 # define MULTILIB_ISA_DEFAULT "mips32r2"
624 # else
625 # if MIPS_ISA_DEFAULT == 64
626 # define MULTILIB_ISA_DEFAULT "mips64"
627 # else
628 # define MULTILIB_ISA_DEFAULT "mips1"
629 # endif
630 # endif
631 # endif
632 # endif
633 # endif
634 # endif
635 # endif
636 #endif
637
638 #ifndef MULTILIB_DEFAULTS
639 #define MULTILIB_DEFAULTS \
640 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
641 #endif
642
643 /* We must pass -EL to the linker by default for little endian embedded
644 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
645 linker will default to using big-endian output files. The OUTPUT_FORMAT
646 line must be in the linker script, otherwise -EB/-EL will not work. */
647
648 #ifndef ENDIAN_SPEC
649 #if TARGET_ENDIAN_DEFAULT == 0
650 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
651 #else
652 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
653 #endif
654 #endif
655
656 /* A spec condition that matches all non-mips16 -mips arguments. */
657
658 #define MIPS_ISA_LEVEL_OPTION_SPEC \
659 "mips1|mips2|mips3|mips4|mips32*|mips64*"
660
661 /* A spec condition that matches all non-mips16 architecture arguments. */
662
663 #define MIPS_ARCH_OPTION_SPEC \
664 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
665
666 /* A spec that infers a -mips argument from an -march argument,
667 or injects the default if no architecture is specified. */
668
669 #define MIPS_ISA_LEVEL_SPEC \
670 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
671 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
672 %{march=mips2|march=r6000:-mips2} \
673 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
674 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
675 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
676 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
677 |march=34k*|march=74k*: -mips32r2} \
678 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
679 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
680
681 /* A spec that infers a -mhard-float or -msoft-float setting from an
682 -march argument. Note that soft-float and hard-float code are not
683 link-compatible. */
684
685 #define MIPS_ARCH_FLOAT_SPEC \
686 "%{mhard-float|msoft-float|march=mips*:; \
687 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
688 |march=34kc|march=74kc|march=5kc: -msoft-float; \
689 march=*: -mhard-float}"
690
691 /* A spec condition that matches 32-bit options. It only works if
692 MIPS_ISA_LEVEL_SPEC has been applied. */
693
694 #define MIPS_32BIT_OPTION_SPEC \
695 "mips1|mips2|mips32*|mgp32"
696
697 /* Support for a compile-time default CPU, et cetera. The rules are:
698 --with-arch is ignored if -march is specified or a -mips is specified
699 (other than -mips16).
700 --with-tune is ignored if -mtune is specified.
701 --with-abi is ignored if -mabi is specified.
702 --with-float is ignored if -mhard-float or -msoft-float are
703 specified.
704 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
705 specified. */
706 #define OPTION_DEFAULT_SPECS \
707 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
708 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
709 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
710 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
711 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
712 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }
713
714
715 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
716 && ISA_HAS_COND_TRAP)
717
718 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
719 && !TARGET_SR71K \
720 && !TARGET_MIPS16)
721
722 /* True if the ABI can only work with 64-bit integer registers. We
723 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
724 otherwise floating-point registers must also be 64-bit. */
725 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
726
727 /* Likewise for 32-bit regs. */
728 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
729
730 /* True if symbols are 64 bits wide. At present, n64 is the only
731 ABI for which this is true. */
732 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
733
734 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
735 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
736 || ISA_MIPS4 \
737 || ISA_MIPS64)
738
739 /* ISA has branch likely instructions (e.g. mips2). */
740 /* Disable branchlikely for tx39 until compare rewrite. They haven't
741 been generated up to this point. */
742 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
743
744 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
745 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
746 || TARGET_MIPS5400 \
747 || TARGET_MIPS5500 \
748 || TARGET_MIPS7000 \
749 || TARGET_MIPS9000 \
750 || TARGET_MAD \
751 || ISA_MIPS32 \
752 || ISA_MIPS32R2 \
753 || ISA_MIPS64) \
754 && !TARGET_MIPS16)
755
756 /* ISA has the conditional move instructions introduced in mips4. */
757 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
758 || ISA_MIPS32 \
759 || ISA_MIPS32R2 \
760 || ISA_MIPS64) \
761 && !TARGET_MIPS5500 \
762 && !TARGET_MIPS16)
763
764 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
765 branch on CC, and move (both FP and non-FP) on CC. */
766 #define ISA_HAS_8CC (ISA_MIPS4 \
767 || ISA_MIPS32 \
768 || ISA_MIPS32R2 \
769 || ISA_MIPS64)
770
771 /* This is a catch all for other mips4 instructions: indexed load, the
772 FP madd and msub instructions, and the FP recip and recip sqrt
773 instructions. */
774 #define ISA_HAS_FP4 ((ISA_MIPS4 \
775 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
776 || ISA_MIPS64) \
777 && !TARGET_MIPS16)
778
779 /* ISA has conditional trap instructions. */
780 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
781 && !TARGET_MIPS16)
782
783 /* ISA has integer multiply-accumulate instructions, madd and msub. */
784 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
785 || ISA_MIPS32R2 \
786 || ISA_MIPS64) \
787 && !TARGET_MIPS16)
788
789 /* Integer multiply-accumulate instructions should be generated. */
790 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
791
792 /* ISA has floating-point nmadd and nmsub instructions. */
793 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
794 || ISA_MIPS64) \
795 && (!TARGET_MIPS5400 || TARGET_MAD) \
796 && !TARGET_MIPS16)
797
798 /* ISA has count leading zeroes/ones instruction (not implemented). */
799 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
800 || ISA_MIPS32R2 \
801 || ISA_MIPS64) \
802 && !TARGET_MIPS16)
803
804 /* ISA has three operand multiply instructions that put
805 the high part in an accumulator: mulhi or mulhiu. */
806 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
807 || TARGET_MIPS5500 \
808 || TARGET_SR71K) \
809 && !TARGET_MIPS16)
810
811 /* ISA has three operand multiply instructions that
812 negates the result and puts the result in an accumulator. */
813 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
814 || TARGET_MIPS5500 \
815 || TARGET_SR71K) \
816 && !TARGET_MIPS16)
817
818 /* ISA has three operand multiply instructions that subtracts the
819 result from a 4th operand and puts the result in an accumulator. */
820 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
821 || TARGET_MIPS5500 \
822 || TARGET_SR71K) \
823 && !TARGET_MIPS16)
824
825 /* ISA has three operand multiply instructions that the result
826 from a 4th operand and puts the result in an accumulator. */
827 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
828 || TARGET_MIPS4130 \
829 || TARGET_MIPS5400 \
830 || TARGET_MIPS5500 \
831 || TARGET_SR71K) \
832 && !TARGET_MIPS16)
833
834 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
835 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
836 || TARGET_MIPS4130) \
837 && !TARGET_MIPS16)
838
839 /* ISA has the "ror" (rotate right) instructions. */
840 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
841 || TARGET_MIPS5400 \
842 || TARGET_MIPS5500 \
843 || TARGET_SR71K \
844 || TARGET_SMARTMIPS) \
845 && !TARGET_MIPS16)
846
847 /* ISA has data prefetch instructions. This controls use of 'pref'. */
848 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
849 || ISA_MIPS32 \
850 || ISA_MIPS32R2 \
851 || ISA_MIPS64) \
852 && !TARGET_MIPS16)
853
854 /* ISA has data indexed prefetch instructions. This controls use of
855 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
856 (prefx is a cop1x instruction, so can only be used if FP is
857 enabled.) */
858 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
859 || ISA_MIPS32R2 \
860 || ISA_MIPS64) \
861 && !TARGET_MIPS16)
862
863 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
864 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
865 also requires TARGET_DOUBLE_FLOAT. */
866 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
867
868 /* ISA includes the MIPS32r2 seb and seh instructions. */
869 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
870 && !TARGET_MIPS16)
871
872 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
873 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
874 && !TARGET_MIPS16)
875
876 /* ISA has instructions for accessing top part of 64-bit fp regs. */
877 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
878
879 /* ISA has lwxs instruction (load w/scaled index address. */
880 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
881
882 /* The DSP ASE is available. */
883 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
884
885 /* Revision 2 of the DSP ASE is available. */
886 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
887
888 /* True if the result of a load is not available to the next instruction.
889 A nop will then be needed between instructions like "lw $4,..."
890 and "addiu $4,$4,1". */
891 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
892 && !TARGET_MIPS3900 \
893 && !TARGET_MIPS16)
894
895 /* Likewise mtc1 and mfc1. */
896 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
897
898 /* Likewise floating-point comparisons. */
899 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
900
901 /* True if mflo and mfhi can be immediately followed by instructions
902 which write to the HI and LO registers.
903
904 According to MIPS specifications, MIPS ISAs I, II, and III need
905 (at least) two instructions between the reads of HI/LO and
906 instructions which write them, and later ISAs do not. Contradicting
907 the MIPS specifications, some MIPS IV processor user manuals (e.g.
908 the UM for the NEC Vr5000) document needing the instructions between
909 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
910 MIPS64 and later ISAs to have the interlocks, plus any specific
911 earlier-ISA CPUs for which CPU documentation declares that the
912 instructions are really interlocked. */
913 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
914 || ISA_MIPS32R2 \
915 || ISA_MIPS64 \
916 || TARGET_MIPS5500)
917
918 /* ISA includes synci, jr.hb and jalr.hb. */
919 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
920
921 /* ISA includes sync. */
922 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
923 #define GENERATE_SYNC (mips_llsc == LLSC_YES \
924 || (mips_llsc == LLSC_DEFAULT && ISA_HAS_SYNC))
925
926 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
927 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
928 instructions. */
929 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
930 #define GENERATE_LL_SC (mips_llsc == LLSC_YES \
931 || (mips_llsc == LLSC_DEFAULT && ISA_HAS_LL_SC))
932 \f
933 /* Add -G xx support. */
934
935 #undef SWITCH_TAKES_ARG
936 #define SWITCH_TAKES_ARG(CHAR) \
937 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
938
939 #define OVERRIDE_OPTIONS override_options ()
940
941 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
942
943 /* Show we can debug even without a frame pointer. */
944 #define CAN_DEBUG_WITHOUT_FP
945 \f
946 /* Tell collect what flags to pass to nm. */
947 #ifndef NM_FLAGS
948 #define NM_FLAGS "-Bn"
949 #endif
950
951 \f
952 #ifndef MIPS_ABI_DEFAULT
953 #define MIPS_ABI_DEFAULT ABI_32
954 #endif
955
956 /* Use the most portable ABI flag for the ASM specs. */
957
958 #if MIPS_ABI_DEFAULT == ABI_32
959 #define MULTILIB_ABI_DEFAULT "mabi=32"
960 #endif
961
962 #if MIPS_ABI_DEFAULT == ABI_O64
963 #define MULTILIB_ABI_DEFAULT "mabi=o64"
964 #endif
965
966 #if MIPS_ABI_DEFAULT == ABI_N32
967 #define MULTILIB_ABI_DEFAULT "mabi=n32"
968 #endif
969
970 #if MIPS_ABI_DEFAULT == ABI_64
971 #define MULTILIB_ABI_DEFAULT "mabi=64"
972 #endif
973
974 #if MIPS_ABI_DEFAULT == ABI_EABI
975 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
976 #endif
977
978 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
979 to the assembler. It may be overridden by subtargets. */
980 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
981 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
982 %{noasmopt:-O0} \
983 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
984 #endif
985
986 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
987 the assembler. It may be overridden by subtargets.
988
989 Beginning with gas 2.13, -mdebug must be passed to correctly handle
990 COFF debugging info. */
991
992 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
993 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
994 %{g} %{g0} %{g1} %{g2} %{g3} \
995 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
996 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
997 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
998 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
999 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1000 #endif
1001
1002 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1003 overridden by subtargets. */
1004
1005 #ifndef SUBTARGET_ASM_SPEC
1006 #define SUBTARGET_ASM_SPEC ""
1007 #endif
1008
1009 #undef ASM_SPEC
1010 #define ASM_SPEC "\
1011 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1012 %{mips32} %{mips32r2} %{mips64} \
1013 %{mips16} %{mno-mips16:-no-mips16} \
1014 %{mips3d} %{mno-mips3d:-no-mips3d} \
1015 %{mdmx} %{mno-mdmx:-no-mdmx} \
1016 %{mdsp} %{mno-dsp} \
1017 %{mdspr2} %{mno-dspr2} \
1018 %{msmartmips} %{mno-smartmips} \
1019 %{mmt} %{mno-mt} \
1020 %{mfix-vr4120} %{mfix-vr4130} \
1021 %(subtarget_asm_optimizing_spec) \
1022 %(subtarget_asm_debugging_spec) \
1023 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1024 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1025 %{mfp32} %{mfp64} \
1026 %{mshared} %{mno-shared} \
1027 %{msym32} %{mno-sym32} \
1028 %{mtune=*} %{v} \
1029 %(subtarget_asm_spec)"
1030
1031 /* Extra switches sometimes passed to the linker. */
1032 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1033 will interpret it as a -b option. */
1034
1035 #ifndef LINK_SPEC
1036 #define LINK_SPEC "\
1037 %(endian_spec) \
1038 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1039 %{bestGnum} %{shared} %{non_shared}"
1040 #endif /* LINK_SPEC defined */
1041
1042
1043 /* Specs for the compiler proper */
1044
1045 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1046 overridden by subtargets. */
1047 #ifndef SUBTARGET_CC1_SPEC
1048 #define SUBTARGET_CC1_SPEC ""
1049 #endif
1050
1051 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1052
1053 #undef CC1_SPEC
1054 #define CC1_SPEC "\
1055 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1056 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1057 %{save-temps: } \
1058 %(subtarget_cc1_spec)"
1059
1060 /* Preprocessor specs. */
1061
1062 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1063 overridden by subtargets. */
1064 #ifndef SUBTARGET_CPP_SPEC
1065 #define SUBTARGET_CPP_SPEC ""
1066 #endif
1067
1068 #define CPP_SPEC "%(subtarget_cpp_spec)"
1069
1070 /* This macro defines names of additional specifications to put in the specs
1071 that can be used in various specifications like CC1_SPEC. Its definition
1072 is an initializer with a subgrouping for each command option.
1073
1074 Each subgrouping contains a string constant, that defines the
1075 specification name, and a string constant that used by the GCC driver
1076 program.
1077
1078 Do not define this macro if it does not need to do anything. */
1079
1080 #define EXTRA_SPECS \
1081 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1082 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1083 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1084 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1085 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1086 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1087 { "endian_spec", ENDIAN_SPEC }, \
1088 SUBTARGET_EXTRA_SPECS
1089
1090 #ifndef SUBTARGET_EXTRA_SPECS
1091 #define SUBTARGET_EXTRA_SPECS
1092 #endif
1093 \f
1094 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1095 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1096 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1097
1098 #ifndef PREFERRED_DEBUGGING_TYPE
1099 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1100 #endif
1101
1102 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1103
1104 /* By default, turn on GDB extensions. */
1105 #define DEFAULT_GDB_EXTENSIONS 1
1106
1107 /* Local compiler-generated symbols must have a prefix that the assembler
1108 understands. By default, this is $, although some targets (e.g.,
1109 NetBSD-ELF) need to override this. */
1110
1111 #ifndef LOCAL_LABEL_PREFIX
1112 #define LOCAL_LABEL_PREFIX "$"
1113 #endif
1114
1115 /* By default on the mips, external symbols do not have an underscore
1116 prepended, but some targets (e.g., NetBSD) require this. */
1117
1118 #ifndef USER_LABEL_PREFIX
1119 #define USER_LABEL_PREFIX ""
1120 #endif
1121
1122 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1123 since the length can run past this up to a continuation point. */
1124 #undef DBX_CONTIN_LENGTH
1125 #define DBX_CONTIN_LENGTH 1500
1126
1127 /* How to renumber registers for dbx and gdb. */
1128 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1129
1130 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1131 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1132
1133 /* The DWARF 2 CFA column which tracks the return address. */
1134 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1135
1136 /* Before the prologue, RA lives in r31. */
1137 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1138
1139 /* Describe how we implement __builtin_eh_return. */
1140 #define EH_RETURN_DATA_REGNO(N) \
1141 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1142
1143 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1144
1145 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1146 The default for this in 64-bit mode is 8, which causes problems with
1147 SFmode register saves. */
1148 #define DWARF_CIE_DATA_ALIGNMENT -4
1149
1150 /* Correct the offset of automatic variables and arguments. Note that
1151 the MIPS debug format wants all automatic variables and arguments
1152 to be in terms of the virtual frame pointer (stack pointer before
1153 any adjustment in the function), while the MIPS 3.0 linker wants
1154 the frame pointer to be the stack pointer after the initial
1155 adjustment. */
1156
1157 #define DEBUGGER_AUTO_OFFSET(X) \
1158 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1159 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1160 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1161 \f
1162 /* Target machine storage layout */
1163
1164 #define BITS_BIG_ENDIAN 0
1165 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1166 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1167
1168 /* Define this to set the endianness to use in libgcc2.c, which can
1169 not depend on target_flags. */
1170 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1171 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1172 #else
1173 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1174 #endif
1175
1176 #define MAX_BITS_PER_WORD 64
1177
1178 /* Width of a word, in units (bytes). */
1179 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1180 #ifndef IN_LIBGCC2
1181 #define MIN_UNITS_PER_WORD 4
1182 #endif
1183
1184 /* For MIPS, width of a floating point register. */
1185 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1186
1187 /* The number of consecutive floating-point registers needed to store the
1188 largest format supported by the FPU. */
1189 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1190
1191 /* The number of consecutive floating-point registers needed to store the
1192 smallest format supported by the FPU. */
1193 #define MIN_FPRS_PER_FMT \
1194 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1195
1196 /* The largest size of value that can be held in floating-point
1197 registers and moved with a single instruction. */
1198 #define UNITS_PER_HWFPVALUE \
1199 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1200
1201 /* The largest size of value that can be held in floating-point
1202 registers. */
1203 #define UNITS_PER_FPVALUE \
1204 (TARGET_SOFT_FLOAT_ABI ? 0 \
1205 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1206 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1207
1208 /* The number of bytes in a double. */
1209 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1210
1211 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1212
1213 /* Set the sizes of the core types. */
1214 #define SHORT_TYPE_SIZE 16
1215 #define INT_TYPE_SIZE 32
1216 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1217 #define LONG_LONG_TYPE_SIZE 64
1218
1219 #define FLOAT_TYPE_SIZE 32
1220 #define DOUBLE_TYPE_SIZE 64
1221 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1222
1223 /* Define the sizes of fixed-point types. */
1224 #define SHORT_FRACT_TYPE_SIZE 8
1225 #define FRACT_TYPE_SIZE 16
1226 #define LONG_FRACT_TYPE_SIZE 32
1227 #define LONG_LONG_FRACT_TYPE_SIZE 64
1228
1229 #define SHORT_ACCUM_TYPE_SIZE 16
1230 #define ACCUM_TYPE_SIZE 32
1231 #define LONG_ACCUM_TYPE_SIZE 64
1232 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1233 doesn't support 128-bit integers for MIPS32 currently. */
1234 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1235
1236 /* long double is not a fixed mode, but the idea is that, if we
1237 support long double, we also want a 128-bit integer type. */
1238 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1239
1240 #ifdef IN_LIBGCC2
1241 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1242 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1243 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1244 # else
1245 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1246 # endif
1247 #endif
1248
1249 /* Width in bits of a pointer. */
1250 #ifndef POINTER_SIZE
1251 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1252 #endif
1253
1254 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1255 #define PARM_BOUNDARY BITS_PER_WORD
1256
1257 /* Allocation boundary (in *bits*) for the code of a function. */
1258 #define FUNCTION_BOUNDARY 32
1259
1260 /* Alignment of field after `int : 0' in a structure. */
1261 #define EMPTY_FIELD_BOUNDARY 32
1262
1263 /* Every structure's size must be a multiple of this. */
1264 /* 8 is observed right on a DECstation and on riscos 4.02. */
1265 #define STRUCTURE_SIZE_BOUNDARY 8
1266
1267 /* There is no point aligning anything to a rounder boundary than this. */
1268 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1269
1270 /* All accesses must be aligned. */
1271 #define STRICT_ALIGNMENT 1
1272
1273 /* Define this if you wish to imitate the way many other C compilers
1274 handle alignment of bitfields and the structures that contain
1275 them.
1276
1277 The behavior is that the type written for a bit-field (`int',
1278 `short', or other integer type) imposes an alignment for the
1279 entire structure, as if the structure really did contain an
1280 ordinary field of that type. In addition, the bit-field is placed
1281 within the structure so that it would fit within such a field,
1282 not crossing a boundary for it.
1283
1284 Thus, on most machines, a bit-field whose type is written as `int'
1285 would not cross a four-byte boundary, and would force four-byte
1286 alignment for the whole structure. (The alignment used may not
1287 be four bytes; it is controlled by the other alignment
1288 parameters.)
1289
1290 If the macro is defined, its definition should be a C expression;
1291 a nonzero value for the expression enables this behavior. */
1292
1293 #define PCC_BITFIELD_TYPE_MATTERS 1
1294
1295 /* If defined, a C expression to compute the alignment given to a
1296 constant that is being placed in memory. CONSTANT is the constant
1297 and ALIGN is the alignment that the object would ordinarily have.
1298 The value of this macro is used instead of that alignment to align
1299 the object.
1300
1301 If this macro is not defined, then ALIGN is used.
1302
1303 The typical use of this macro is to increase alignment for string
1304 constants to be word aligned so that `strcpy' calls that copy
1305 constants can be done inline. */
1306
1307 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1308 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1309 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1310
1311 /* If defined, a C expression to compute the alignment for a static
1312 variable. TYPE is the data type, and ALIGN is the alignment that
1313 the object would ordinarily have. The value of this macro is used
1314 instead of that alignment to align the object.
1315
1316 If this macro is not defined, then ALIGN is used.
1317
1318 One use of this macro is to increase alignment of medium-size
1319 data to make it all fit in fewer cache lines. Another is to
1320 cause character arrays to be word-aligned so that `strcpy' calls
1321 that copy constants to character arrays can be done inline. */
1322
1323 #undef DATA_ALIGNMENT
1324 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1325 ((((ALIGN) < BITS_PER_WORD) \
1326 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1327 || TREE_CODE (TYPE) == UNION_TYPE \
1328 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1329
1330
1331 #define PAD_VARARGS_DOWN \
1332 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1333
1334 /* Define if operations between registers always perform the operation
1335 on the full register even if a narrower mode is specified. */
1336 #define WORD_REGISTER_OPERATIONS
1337
1338 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1339 moves. All other references are zero extended. */
1340 #define LOAD_EXTEND_OP(MODE) \
1341 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1342 ? SIGN_EXTEND : ZERO_EXTEND)
1343
1344 /* Define this macro if it is advisable to hold scalars in registers
1345 in a wider mode than that declared by the program. In such cases,
1346 the value is constrained to be within the bounds of the declared
1347 type, but kept valid in the wider mode. The signedness of the
1348 extension may differ from that of the type. */
1349
1350 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1351 if (GET_MODE_CLASS (MODE) == MODE_INT \
1352 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1353 { \
1354 if ((MODE) == SImode) \
1355 (UNSIGNEDP) = 0; \
1356 (MODE) = Pmode; \
1357 }
1358
1359 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1360 Extensions of pointers to word_mode must be signed. */
1361 #define POINTERS_EXTEND_UNSIGNED false
1362
1363 /* Define if loading short immediate values into registers sign extends. */
1364 #define SHORT_IMMEDIATES_SIGN_EXTEND
1365
1366 /* The [d]clz instructions have the natural values at 0. */
1367
1368 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1369 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1370 \f
1371 /* Standard register usage. */
1372
1373 /* Number of hardware registers. We have:
1374
1375 - 32 integer registers
1376 - 32 floating point registers
1377 - 8 condition code registers
1378 - 2 accumulator registers (hi and lo)
1379 - 32 registers each for coprocessors 0, 2 and 3
1380 - 3 fake registers:
1381 - ARG_POINTER_REGNUM
1382 - FRAME_POINTER_REGNUM
1383 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1384 - 3 dummy entries that were used at various times in the past.
1385 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1386 - 6 DSP control registers */
1387
1388 #define FIRST_PSEUDO_REGISTER 188
1389
1390 /* By default, fix the kernel registers ($26 and $27), the global
1391 pointer ($28) and the stack pointer ($29). This can change
1392 depending on the command-line options.
1393
1394 Regarding coprocessor registers: without evidence to the contrary,
1395 it's best to assume that each coprocessor register has a unique
1396 use. This can be overridden, in, e.g., override_options() or
1397 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1398 for a particular target. */
1399
1400 #define FIXED_REGISTERS \
1401 { \
1402 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1403 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1404 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1405 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1406 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1407 /* COP0 registers */ \
1408 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1409 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1410 /* COP2 registers */ \
1411 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1412 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1413 /* COP3 registers */ \
1414 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1415 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1416 /* 6 DSP accumulator registers & 6 control registers */ \
1417 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1418 }
1419
1420
1421 /* Set up this array for o32 by default.
1422
1423 Note that we don't mark $31 as a call-clobbered register. The idea is
1424 that it's really the call instructions themselves which clobber $31.
1425 We don't care what the called function does with it afterwards.
1426
1427 This approach makes it easier to implement sibcalls. Unlike normal
1428 calls, sibcalls don't clobber $31, so the register reaches the
1429 called function in tact. EPILOGUE_USES says that $31 is useful
1430 to the called function. */
1431
1432 #define CALL_USED_REGISTERS \
1433 { \
1434 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1435 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1436 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1437 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1438 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1439 /* COP0 registers */ \
1440 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1442 /* COP2 registers */ \
1443 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1444 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1445 /* COP3 registers */ \
1446 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1447 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1448 /* 6 DSP accumulator registers & 6 control registers */ \
1449 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1450 }
1451
1452
1453 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1454
1455 #define CALL_REALLY_USED_REGISTERS \
1456 { /* General registers. */ \
1457 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1458 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1459 /* Floating-point registers. */ \
1460 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1461 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1462 /* Others. */ \
1463 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1464 /* COP0 registers */ \
1465 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1467 /* COP2 registers */ \
1468 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1469 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1470 /* COP3 registers */ \
1471 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1472 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1473 /* 6 DSP accumulator registers & 6 control registers */ \
1474 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1475 }
1476
1477 /* Internal macros to classify a register number as to whether it's a
1478 general purpose register, a floating point register, a
1479 multiply/divide register, or a status register. */
1480
1481 #define GP_REG_FIRST 0
1482 #define GP_REG_LAST 31
1483 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1484 #define GP_DBX_FIRST 0
1485
1486 #define FP_REG_FIRST 32
1487 #define FP_REG_LAST 63
1488 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1489 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1490
1491 #define MD_REG_FIRST 64
1492 #define MD_REG_LAST 65
1493 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1494 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1495
1496 /* The DWARF 2 CFA column which tracks the return address from a
1497 signal handler context. This means that to maintain backwards
1498 compatibility, no hard register can be assigned this column if it
1499 would need to be handled by the DWARF unwinder. */
1500 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1501
1502 #define ST_REG_FIRST 67
1503 #define ST_REG_LAST 74
1504 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1505
1506
1507 /* FIXME: renumber. */
1508 #define COP0_REG_FIRST 80
1509 #define COP0_REG_LAST 111
1510 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1511
1512 #define COP2_REG_FIRST 112
1513 #define COP2_REG_LAST 143
1514 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1515
1516 #define COP3_REG_FIRST 144
1517 #define COP3_REG_LAST 175
1518 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1519 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1520 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1521
1522 #define DSP_ACC_REG_FIRST 176
1523 #define DSP_ACC_REG_LAST 181
1524 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1525
1526 #define AT_REGNUM (GP_REG_FIRST + 1)
1527 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1528 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1529
1530 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1531 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1532 should be used instead. */
1533 #define FPSW_REGNUM ST_REG_FIRST
1534
1535 #define GP_REG_P(REGNO) \
1536 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1537 #define M16_REG_P(REGNO) \
1538 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1539 #define FP_REG_P(REGNO) \
1540 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1541 #define MD_REG_P(REGNO) \
1542 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1543 #define ST_REG_P(REGNO) \
1544 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1545 #define COP0_REG_P(REGNO) \
1546 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1547 #define COP2_REG_P(REGNO) \
1548 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1549 #define COP3_REG_P(REGNO) \
1550 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1551 #define ALL_COP_REG_P(REGNO) \
1552 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1553 /* Test if REGNO is one of the 6 new DSP accumulators. */
1554 #define DSP_ACC_REG_P(REGNO) \
1555 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1556 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1557 #define ACC_REG_P(REGNO) \
1558 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1559
1560 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1561
1562 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1563 to initialize the mips16 gp pseudo register. */
1564 #define CONST_GP_P(X) \
1565 (GET_CODE (X) == CONST \
1566 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1567 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1568
1569 /* Return coprocessor number from register number. */
1570
1571 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1572 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1573 : COP3_REG_P (REGNO) ? '3' : '?')
1574
1575
1576 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1577
1578 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1579 array built in override_options. Because machmodes.h is not yet
1580 included before this file is processed, the MODE bound can't be
1581 expressed here. */
1582
1583 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1584
1585 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1586 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1587
1588 /* Value is 1 if it is a good idea to tie two pseudo registers
1589 when one has mode MODE1 and one has mode MODE2.
1590 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1591 for any hard reg, then this must be 0 for correct output. */
1592 #define MODES_TIEABLE_P(MODE1, MODE2) \
1593 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1594 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1595 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1596 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1597
1598 /* Register to use for pushing function arguments. */
1599 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1600
1601 /* These two registers don't really exist: they get eliminated to either
1602 the stack or hard frame pointer. */
1603 #define ARG_POINTER_REGNUM 77
1604 #define FRAME_POINTER_REGNUM 78
1605
1606 /* $30 is not available on the mips16, so we use $17 as the frame
1607 pointer. */
1608 #define HARD_FRAME_POINTER_REGNUM \
1609 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1610
1611 /* Value should be nonzero if functions must have frame pointers.
1612 Zero means the frame pointer need not be set up (and parms
1613 may be accessed via the stack pointer) in functions that seem suitable.
1614 This is computed in `reload', in reload1.c. */
1615 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1616
1617 /* Register in which static-chain is passed to a function. */
1618 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1619
1620 /* Registers used as temporaries in prologue/epilogue code. If we're
1621 generating mips16 code, these registers must come from the core set
1622 of 8. The prologue register mustn't conflict with any incoming
1623 arguments, the static chain pointer, or the frame pointer. The
1624 epilogue temporary mustn't conflict with the return registers, the
1625 frame pointer, the EH stack adjustment, or the EH data registers. */
1626
1627 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1628 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1629
1630 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1631 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1632
1633 /* Define this macro if it is as good or better to call a constant
1634 function address than to call an address kept in a register. */
1635 #define NO_FUNCTION_CSE 1
1636
1637 /* The ABI-defined global pointer. Sometimes we use a different
1638 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1639 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1640
1641 /* We normally use $28 as the global pointer. However, when generating
1642 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1643 register instead. They can then avoid saving and restoring $28
1644 and perhaps avoid using a frame at all.
1645
1646 When a leaf function uses something other than $28, mips_expand_prologue
1647 will modify pic_offset_table_rtx in place. Take the register number
1648 from there after reload. */
1649 #define PIC_OFFSET_TABLE_REGNUM \
1650 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1651
1652 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1653 \f
1654 /* Define the classes of registers for register constraints in the
1655 machine description. Also define ranges of constants.
1656
1657 One of the classes must always be named ALL_REGS and include all hard regs.
1658 If there is more than one class, another class must be named NO_REGS
1659 and contain no registers.
1660
1661 The name GENERAL_REGS must be the name of a class (or an alias for
1662 another name such as ALL_REGS). This is the class of registers
1663 that is allowed by "g" or "r" in a register constraint.
1664 Also, registers outside this class are allocated only when
1665 instructions express preferences for them.
1666
1667 The classes must be numbered in nondecreasing order; that is,
1668 a larger-numbered class must never be contained completely
1669 in a smaller-numbered class.
1670
1671 For any two classes, it is very desirable that there be another
1672 class that represents their union. */
1673
1674 enum reg_class
1675 {
1676 NO_REGS, /* no registers in set */
1677 M16_NA_REGS, /* mips16 regs not used to pass args */
1678 M16_REGS, /* mips16 directly accessible registers */
1679 T_REG, /* mips16 T register ($24) */
1680 M16_T_REGS, /* mips16 registers plus T register */
1681 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1682 V1_REG, /* Register $v1 ($3) used for TLS access. */
1683 LEA_REGS, /* Every GPR except $25 */
1684 GR_REGS, /* integer registers */
1685 FP_REGS, /* floating point registers */
1686 MD0_REG, /* first multiply/divide register */
1687 MD1_REG, /* second multiply/divide register */
1688 MD_REGS, /* multiply/divide registers (hi/lo) */
1689 COP0_REGS, /* generic coprocessor classes */
1690 COP2_REGS,
1691 COP3_REGS,
1692 HI_AND_GR_REGS, /* union classes */
1693 LO_AND_GR_REGS,
1694 HI_AND_FP_REGS,
1695 COP0_AND_GR_REGS,
1696 COP2_AND_GR_REGS,
1697 COP3_AND_GR_REGS,
1698 ALL_COP_REGS,
1699 ALL_COP_AND_GR_REGS,
1700 ST_REGS, /* status registers (fp status) */
1701 DSP_ACC_REGS, /* DSP accumulator registers */
1702 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1703 ALL_REGS, /* all registers */
1704 LIM_REG_CLASSES /* max value + 1 */
1705 };
1706
1707 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1708
1709 #define GENERAL_REGS GR_REGS
1710
1711 /* An initializer containing the names of the register classes as C
1712 string constants. These names are used in writing some of the
1713 debugging dumps. */
1714
1715 #define REG_CLASS_NAMES \
1716 { \
1717 "NO_REGS", \
1718 "M16_NA_REGS", \
1719 "M16_REGS", \
1720 "T_REG", \
1721 "M16_T_REGS", \
1722 "PIC_FN_ADDR_REG", \
1723 "V1_REG", \
1724 "LEA_REGS", \
1725 "GR_REGS", \
1726 "FP_REGS", \
1727 "MD0_REG", \
1728 "MD1_REG", \
1729 "MD_REGS", \
1730 /* coprocessor registers */ \
1731 "COP0_REGS", \
1732 "COP2_REGS", \
1733 "COP3_REGS", \
1734 "HI_AND_GR_REGS", \
1735 "LO_AND_GR_REGS", \
1736 "HI_AND_FP_REGS", \
1737 "COP0_AND_GR_REGS", \
1738 "COP2_AND_GR_REGS", \
1739 "COP3_AND_GR_REGS", \
1740 "ALL_COP_REGS", \
1741 "ALL_COP_AND_GR_REGS", \
1742 "ST_REGS", \
1743 "DSP_ACC_REGS", \
1744 "ACC_REGS", \
1745 "ALL_REGS" \
1746 }
1747
1748 /* An initializer containing the contents of the register classes,
1749 as integers which are bit masks. The Nth integer specifies the
1750 contents of class N. The way the integer MASK is interpreted is
1751 that register R is in the class if `MASK & (1 << R)' is 1.
1752
1753 When the machine has more than 32 registers, an integer does not
1754 suffice. Then the integers are replaced by sub-initializers,
1755 braced groupings containing several integers. Each
1756 sub-initializer must be suitable as an initializer for the type
1757 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1758
1759 #define REG_CLASS_CONTENTS \
1760 { \
1761 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1762 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1763 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1764 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1765 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1766 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1767 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1768 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1769 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1770 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1771 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1772 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1773 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1774 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1775 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1776 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1777 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1778 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1779 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1780 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1781 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1782 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1783 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1784 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1785 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1786 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1787 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1788 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1789 }
1790
1791
1792 /* A C expression whose value is a register class containing hard
1793 register REGNO. In general there is more that one such class;
1794 choose a class which is "minimal", meaning that no smaller class
1795 also contains the register. */
1796
1797 extern const enum reg_class mips_regno_to_class[];
1798
1799 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1800
1801 /* A macro whose definition is the name of the class to which a
1802 valid base register must belong. A base register is one used in
1803 an address which is the register value plus a displacement. */
1804
1805 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1806
1807 /* A macro whose definition is the name of the class to which a
1808 valid index register must belong. An index register is one used
1809 in an address where its value is either multiplied by a scale
1810 factor or added to another register (as well as added to a
1811 displacement). */
1812
1813 #define INDEX_REG_CLASS NO_REGS
1814
1815 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1816 registers explicitly used in the rtl to be used as spill registers
1817 but prevents the compiler from extending the lifetime of these
1818 registers. */
1819
1820 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1821
1822 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1823 is the default value (allocate the registers in numeric order). We
1824 define it just so that we can override it for the mips16 target in
1825 ORDER_REGS_FOR_LOCAL_ALLOC. */
1826
1827 #define REG_ALLOC_ORDER \
1828 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1829 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1830 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1831 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1832 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1833 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1834 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1835 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1836 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1837 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1838 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1839 176,177,178,179,180,181,182,183,184,185,186,187 \
1840 }
1841
1842 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1843 to be rearranged based on a particular function. On the mips16, we
1844 want to allocate $24 (T_REG) before other registers for
1845 instructions for which it is possible. */
1846
1847 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1848
1849 /* True if VALUE is an unsigned 6-bit number. */
1850
1851 #define UIMM6_OPERAND(VALUE) \
1852 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1853
1854 /* True if VALUE is a signed 10-bit number. */
1855
1856 #define IMM10_OPERAND(VALUE) \
1857 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1858
1859 /* True if VALUE is a signed 16-bit number. */
1860
1861 #define SMALL_OPERAND(VALUE) \
1862 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1863
1864 /* True if VALUE is an unsigned 16-bit number. */
1865
1866 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1867 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1868
1869 /* True if VALUE can be loaded into a register using LUI. */
1870
1871 #define LUI_OPERAND(VALUE) \
1872 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1873 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1874
1875 /* Return a value X with the low 16 bits clear, and such that
1876 VALUE - X is a signed 16-bit value. */
1877
1878 #define CONST_HIGH_PART(VALUE) \
1879 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1880
1881 #define CONST_LOW_PART(VALUE) \
1882 ((VALUE) - CONST_HIGH_PART (VALUE))
1883
1884 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1885 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1886 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1887
1888 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1889 mips_preferred_reload_class (X, CLASS)
1890
1891 /* The HI and LO registers can only be reloaded via the general
1892 registers. Condition code registers can only be loaded to the
1893 general registers, and from the floating point registers. */
1894
1895 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1896 mips_secondary_reload_class (CLASS, MODE, X, 1)
1897 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1898 mips_secondary_reload_class (CLASS, MODE, X, 0)
1899
1900 /* Return the maximum number of consecutive registers
1901 needed to represent mode MODE in a register of class CLASS. */
1902
1903 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1904
1905 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1906 mips_cannot_change_mode_class (FROM, TO, CLASS)
1907 \f
1908 /* Stack layout; function entry, exit and calling. */
1909
1910 #define STACK_GROWS_DOWNWARD
1911
1912 /* The offset of the first local variable from the beginning of the frame.
1913 See compute_frame_size for details about the frame layout.
1914
1915 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1916 we assume that we will need 16 bytes of argument space. This is because
1917 the value profiling code may emit calls to cmpdi2 in leaf functions.
1918 Without this hack, the local variables will start at sp+8 and the gp save
1919 area will be at sp+16, and thus they will overlap. compute_frame_size is
1920 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1921 will end up as 24 instead of 8. This won't be needed if profiling code is
1922 inserted before virtual register instantiation. */
1923
1924 #define STARTING_FRAME_OFFSET \
1925 ((flag_profile_values && ! TARGET_64BIT \
1926 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1927 : current_function_outgoing_args_size) \
1928 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1929
1930 #define RETURN_ADDR_RTX mips_return_addr
1931
1932 /* Since the mips16 ISA mode is encoded in the least-significant bit
1933 of the address, mask it off return addresses for purposes of
1934 finding exception handling regions. */
1935
1936 #define MASK_RETURN_ADDR GEN_INT (-2)
1937
1938
1939 /* Similarly, don't use the least-significant bit to tell pointers to
1940 code from vtable index. */
1941
1942 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1943
1944 /* The eliminations to $17 are only used for mips16 code. See the
1945 definition of HARD_FRAME_POINTER_REGNUM. */
1946
1947 #define ELIMINABLE_REGS \
1948 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1949 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1950 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1951 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1952 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1953 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1954
1955 /* We can always eliminate to the hard frame pointer. We can eliminate
1956 to the stack pointer unless a frame pointer is needed.
1957
1958 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1959 reload may be unable to compute the address of a local variable,
1960 since there is no way to add a large constant to the stack pointer
1961 without using a temporary register. */
1962 #define CAN_ELIMINATE(FROM, TO) \
1963 ((TO) == HARD_FRAME_POINTER_REGNUM \
1964 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1965 && (!TARGET_MIPS16 \
1966 || compute_frame_size (get_frame_size ()) < 32768)))
1967
1968 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1969 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1970
1971 /* Allocate stack space for arguments at the beginning of each function. */
1972 #define ACCUMULATE_OUTGOING_ARGS 1
1973
1974 /* The argument pointer always points to the first argument. */
1975 #define FIRST_PARM_OFFSET(FNDECL) 0
1976
1977 /* o32 and o64 reserve stack space for all argument registers. */
1978 #define REG_PARM_STACK_SPACE(FNDECL) \
1979 (TARGET_OLDABI \
1980 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1981 : 0)
1982
1983 /* Define this if it is the responsibility of the caller to
1984 allocate the area reserved for arguments passed in registers.
1985 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1986 of this macro is to determine whether the space is included in
1987 `current_function_outgoing_args_size'. */
1988 #define OUTGOING_REG_PARM_STACK_SPACE 1
1989
1990 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1991 \f
1992 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1993
1994 /* Symbolic macros for the registers used to return integer and floating
1995 point values. */
1996
1997 #define GP_RETURN (GP_REG_FIRST + 2)
1998 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1999
2000 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2001
2002 /* Symbolic macros for the first/last argument registers. */
2003
2004 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2005 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2006 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2007 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2008
2009 #define LIBCALL_VALUE(MODE) \
2010 mips_function_value (NULL_TREE, NULL, (MODE))
2011
2012 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2013 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2014
2015 /* 1 if N is a possible register number for a function value.
2016 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2017 Currently, R2 and F0 are only implemented here (C has no complex type) */
2018
2019 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2020 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2021 && (N) == FP_RETURN + 2))
2022
2023 /* 1 if N is a possible register number for function argument passing.
2024 We have no FP argument registers when soft-float. When FP registers
2025 are 32 bits, we can't directly reference the odd numbered ones. */
2026
2027 #define FUNCTION_ARG_REGNO_P(N) \
2028 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2029 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2030 && !fixed_regs[N])
2031 \f
2032 /* This structure has to cope with two different argument allocation
2033 schemes. Most MIPS ABIs view the arguments as a structure, of which
2034 the first N words go in registers and the rest go on the stack. If I
2035 < N, the Ith word might go in Ith integer argument register or in a
2036 floating-point register. For these ABIs, we only need to remember
2037 the offset of the current argument into the structure.
2038
2039 The EABI instead allocates the integer and floating-point arguments
2040 separately. The first N words of FP arguments go in FP registers,
2041 the rest go on the stack. Likewise, the first N words of the other
2042 arguments go in integer registers, and the rest go on the stack. We
2043 need to maintain three counts: the number of integer registers used,
2044 the number of floating-point registers used, and the number of words
2045 passed on the stack.
2046
2047 We could keep separate information for the two ABIs (a word count for
2048 the standard ABIs, and three separate counts for the EABI). But it
2049 seems simpler to view the standard ABIs as forms of EABI that do not
2050 allocate floating-point registers.
2051
2052 So for the standard ABIs, the first N words are allocated to integer
2053 registers, and function_arg decides on an argument-by-argument basis
2054 whether that argument should really go in an integer register, or in
2055 a floating-point one. */
2056
2057 typedef struct mips_args {
2058 /* Always true for varargs functions. Otherwise true if at least
2059 one argument has been passed in an integer register. */
2060 int gp_reg_found;
2061
2062 /* The number of arguments seen so far. */
2063 unsigned int arg_number;
2064
2065 /* The number of integer registers used so far. For all ABIs except
2066 EABI, this is the number of words that have been added to the
2067 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2068 unsigned int num_gprs;
2069
2070 /* For EABI, the number of floating-point registers used so far. */
2071 unsigned int num_fprs;
2072
2073 /* The number of words passed on the stack. */
2074 unsigned int stack_words;
2075
2076 /* On the mips16, we need to keep track of which floating point
2077 arguments were passed in general registers, but would have been
2078 passed in the FP regs if this were a 32-bit function, so that we
2079 can move them to the FP regs if we wind up calling a 32-bit
2080 function. We record this information in fp_code, encoded in base
2081 four. A zero digit means no floating point argument, a one digit
2082 means an SFmode argument, and a two digit means a DFmode argument,
2083 and a three digit is not used. The low order digit is the first
2084 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2085 an SFmode argument. ??? A more sophisticated approach will be
2086 needed if MIPS_ABI != ABI_32. */
2087 int fp_code;
2088
2089 /* True if the function has a prototype. */
2090 int prototype;
2091 } CUMULATIVE_ARGS;
2092
2093 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2094 for a call to a function whose data type is FNTYPE.
2095 For a library call, FNTYPE is 0. */
2096
2097 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2098 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2099
2100 /* Update the data in CUM to advance over an argument
2101 of mode MODE and data type TYPE.
2102 (TYPE is null for libcalls where that information may not be available.) */
2103
2104 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2105 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2106
2107 /* Determine where to put an argument to a function.
2108 Value is zero to push the argument on the stack,
2109 or a hard register in which to store the argument.
2110
2111 MODE is the argument's machine mode.
2112 TYPE is the data type of the argument (as a tree).
2113 This is null for libcalls where that information may
2114 not be available.
2115 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2116 the preceding args and about the function being called.
2117 NAMED is nonzero if this argument is a named parameter
2118 (otherwise it is an extra parameter matching an ellipsis). */
2119
2120 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2121 function_arg( &CUM, MODE, TYPE, NAMED)
2122
2123 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2124
2125 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2126 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2127
2128 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2129 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2130
2131 /* True if using EABI and varargs can be passed in floating-point
2132 registers. Under these conditions, we need a more complex form
2133 of va_list, which tracks GPR, FPR and stack arguments separately. */
2134 #define EABI_FLOAT_VARARGS_P \
2135 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2136
2137 \f
2138 /* Say that the epilogue uses the return address register. Note that
2139 in the case of sibcalls, the values "used by the epilogue" are
2140 considered live at the start of the called function. */
2141 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2142
2143 /* Treat LOC as a byte offset from the stack pointer and round it up
2144 to the next fully-aligned offset. */
2145 #define MIPS_STACK_ALIGN(LOC) \
2146 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2147
2148 \f
2149 /* Implement `va_start' for varargs and stdarg. */
2150 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2151 mips_va_start (valist, nextarg)
2152 \f
2153 /* Output assembler code to FILE to increment profiler label # LABELNO
2154 for profiling a function entry. */
2155
2156 #define FUNCTION_PROFILER(FILE, LABELNO) \
2157 { \
2158 if (TARGET_MIPS16) \
2159 sorry ("mips16 function profiling"); \
2160 fprintf (FILE, "\t.set\tnoat\n"); \
2161 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2162 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2163 if (!TARGET_NEWABI) \
2164 { \
2165 fprintf (FILE, \
2166 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2167 TARGET_64BIT ? "dsubu" : "subu", \
2168 reg_names[STACK_POINTER_REGNUM], \
2169 reg_names[STACK_POINTER_REGNUM], \
2170 Pmode == DImode ? 16 : 8); \
2171 } \
2172 fprintf (FILE, "\tjal\t_mcount\n"); \
2173 fprintf (FILE, "\t.set\tat\n"); \
2174 }
2175
2176 /* The profiler preserves all interesting registers, including $31. */
2177 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2178
2179 /* No mips port has ever used the profiler counter word, so don't emit it
2180 or the label for it. */
2181
2182 #define NO_PROFILE_COUNTERS 1
2183
2184 /* Define this macro if the code for function profiling should come
2185 before the function prologue. Normally, the profiling code comes
2186 after. */
2187
2188 /* #define PROFILE_BEFORE_PROLOGUE */
2189
2190 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2191 the stack pointer does not matter. The value is tested only in
2192 functions that have frame pointers.
2193 No definition is equivalent to always zero. */
2194
2195 #define EXIT_IGNORE_STACK 1
2196
2197 \f
2198 /* A C statement to output, on the stream FILE, assembler code for a
2199 block of data that contains the constant parts of a trampoline.
2200 This code should not include a label--the label is taken care of
2201 automatically. */
2202
2203 #define TRAMPOLINE_TEMPLATE(STREAM) \
2204 { \
2205 if (ptr_mode == DImode) \
2206 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2207 else \
2208 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2209 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2210 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2211 if (ptr_mode == DImode) \
2212 { \
2213 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2214 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2215 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2216 } \
2217 else \
2218 { \
2219 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2220 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2221 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2222 } \
2223 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2224 if (ptr_mode == DImode) \
2225 { \
2226 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2227 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2228 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2229 } \
2230 else \
2231 { \
2232 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2233 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2234 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2235 } \
2236 }
2237
2238 /* A C expression for the size in bytes of the trampoline, as an
2239 integer. */
2240
2241 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2242
2243 /* Alignment required for trampolines, in bits. */
2244
2245 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2246
2247 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2248 program and data caches. */
2249
2250 #ifndef CACHE_FLUSH_FUNC
2251 #define CACHE_FLUSH_FUNC "_flush_cache"
2252 #endif
2253
2254 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2255 /* Flush both caches. We need to flush the data cache in case \
2256 the system has a write-back cache. */ \
2257 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2258 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2259 GEN_INT (3), TYPE_MODE (integer_type_node))
2260
2261 /* A C statement to initialize the variable parts of a trampoline.
2262 ADDR is an RTX for the address of the trampoline; FNADDR is an
2263 RTX for the address of the nested function; STATIC_CHAIN is an
2264 RTX for the static chain value that should be passed to the
2265 function when it is called. */
2266
2267 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2268 { \
2269 rtx func_addr, chain_addr, end_addr; \
2270 \
2271 func_addr = plus_constant (ADDR, 32); \
2272 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2273 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2274 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2275 end_addr = gen_reg_rtx (Pmode); \
2276 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2277 GEN_INT (TRAMPOLINE_SIZE))); \
2278 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2279 }
2280 \f
2281 /* Addressing modes, and classification of registers for them. */
2282
2283 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2284 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2285 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2286
2287 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2288 and check its validity for a certain class.
2289 We have two alternate definitions for each of them.
2290 The usual definition accepts all pseudo regs; the other rejects them all.
2291 The symbol REG_OK_STRICT causes the latter definition to be used.
2292
2293 Most source files want to accept pseudo regs in the hope that
2294 they will get allocated to the class that the insn wants them to be in.
2295 Some source files that are used after register allocation
2296 need to be strict. */
2297
2298 #ifndef REG_OK_STRICT
2299 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2300 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2301 #else
2302 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2303 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2304 #endif
2305
2306 #define REG_OK_FOR_INDEX_P(X) 0
2307
2308 \f
2309 /* Maximum number of registers that can appear in a valid memory address. */
2310
2311 #define MAX_REGS_PER_ADDRESS 1
2312
2313 #ifdef REG_OK_STRICT
2314 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2315 { \
2316 if (mips_legitimate_address_p (MODE, X, 1)) \
2317 goto ADDR; \
2318 }
2319 #else
2320 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2321 { \
2322 if (mips_legitimate_address_p (MODE, X, 0)) \
2323 goto ADDR; \
2324 }
2325 #endif
2326
2327 /* Check for constness inline but use mips_legitimate_address_p
2328 to check whether a constant really is an address. */
2329
2330 #define CONSTANT_ADDRESS_P(X) \
2331 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2332
2333 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2334
2335 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2336 do { \
2337 if (mips_legitimize_address (&(X), MODE)) \
2338 goto WIN; \
2339 } while (0)
2340
2341
2342 /* A C statement or compound statement with a conditional `goto
2343 LABEL;' executed if memory address X (an RTX) can have different
2344 meanings depending on the machine mode of the memory reference it
2345 is used for.
2346
2347 Autoincrement and autodecrement addresses typically have
2348 mode-dependent effects because the amount of the increment or
2349 decrement is the size of the operand being addressed. Some
2350 machines have other mode-dependent addresses. Many RISC machines
2351 have no mode-dependent addresses.
2352
2353 You may assume that ADDR is a valid address for the machine. */
2354
2355 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2356
2357 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2358 'the start of the function that this code is output in'. */
2359
2360 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2361 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2362 asm_fprintf ((FILE), "%U%s", \
2363 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2364 else \
2365 asm_fprintf ((FILE), "%U%s", (NAME))
2366 \f
2367 /* Flag to mark a function decl symbol that requires a long call. */
2368 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2369 #define SYMBOL_REF_LONG_CALL_P(X) \
2370 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2371
2372 /* True if we're generating a form of MIPS16 code in which jump tables
2373 are stored in the text section and encoded as 16-bit PC-relative
2374 offsets. This is only possible when general text loads are allowed,
2375 since the table access itself will be an "lh" instruction. */
2376 /* ??? 16-bit offsets can overflow in large functions. */
2377 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2378
2379 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2380
2381 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2382
2383 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2384
2385 /* Define this as 1 if `char' should by default be signed; else as 0. */
2386 #ifndef DEFAULT_SIGNED_CHAR
2387 #define DEFAULT_SIGNED_CHAR 1
2388 #endif
2389
2390 /* Max number of bytes we can move from memory to memory
2391 in one reasonably fast instruction. */
2392 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2393 #define MAX_MOVE_MAX 8
2394
2395 /* Define this macro as a C expression which is nonzero if
2396 accessing less than a word of memory (i.e. a `char' or a
2397 `short') is no faster than accessing a word of memory, i.e., if
2398 such access require more than one instruction or if there is no
2399 difference in cost between byte and (aligned) word loads.
2400
2401 On RISC machines, it tends to generate better code to define
2402 this as 1, since it avoids making a QI or HI mode register.
2403
2404 But, generating word accesses for -mips16 is generally bad as shifts
2405 (often extended) would be needed for byte accesses. */
2406 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2407
2408 /* Define this to be nonzero if shift instructions ignore all but the low-order
2409 few bits. */
2410 #define SHIFT_COUNT_TRUNCATED 1
2411
2412 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2413 is done just by pretending it is already truncated. */
2414 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2415 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2416
2417
2418 /* Specify the machine mode that pointers have.
2419 After generation of rtl, the compiler makes no further distinction
2420 between pointers and any other objects of this machine mode. */
2421
2422 #ifndef Pmode
2423 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2424 #endif
2425
2426 /* Give call MEMs SImode since it is the "most permissive" mode
2427 for both 32-bit and 64-bit targets. */
2428
2429 #define FUNCTION_MODE SImode
2430
2431 \f
2432 /* A C expression for the cost of moving data from a register in
2433 class FROM to one in class TO. The classes are expressed using
2434 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2435 the default; other values are interpreted relative to that.
2436
2437 It is not required that the cost always equal 2 when FROM is the
2438 same as TO; on some machines it is expensive to move between
2439 registers if they are not general registers.
2440
2441 If reload sees an insn consisting of a single `set' between two
2442 hard registers, and if `REGISTER_MOVE_COST' applied to their
2443 classes returns a value of 2, reload does not check to ensure
2444 that the constraints of the insn are met. Setting a cost of
2445 other than 2 will allow reload to verify that the constraints are
2446 met. You should do this if the `movM' pattern's constraints do
2447 not allow such copying. */
2448
2449 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2450 mips_register_move_cost (MODE, FROM, TO)
2451
2452 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2453 (mips_cost->memory_latency \
2454 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2455
2456 /* Define if copies to/from condition code registers should be avoided.
2457
2458 This is needed for the MIPS because reload_outcc is not complete;
2459 it needs to handle cases where the source is a general or another
2460 condition code register. */
2461 #define AVOID_CCMODE_COPIES
2462
2463 /* A C expression for the cost of a branch instruction. A value of
2464 1 is the default; other values are interpreted relative to that. */
2465
2466 #define BRANCH_COST mips_branch_cost
2467 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2468
2469 /* If defined, modifies the length assigned to instruction INSN as a
2470 function of the context in which it is used. LENGTH is an lvalue
2471 that contains the initially computed length of the insn and should
2472 be updated with the correct length of the insn. */
2473 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2474 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2475
2476 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2477 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2478 its operands. */
2479 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2480 "%*" OPCODE "%?\t" OPERANDS "%/"
2481
2482 /* Return the asm template for a call. INSN is the instruction's mnemonic
2483 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2484 of the target.
2485
2486 When generating GOT code without explicit relocation operators,
2487 all calls should use assembly macros. Otherwise, all indirect
2488 calls should use "jr" or "jalr"; we will arrange to restore $gp
2489 afterwards if necessary. Finally, we can only generate direct
2490 calls for -mabicalls by temporarily switching to non-PIC mode. */
2491 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2492 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2493 ? "%*" INSN "\t%" #OPNO "%/" \
2494 : REG_P (OPERANDS[OPNO]) \
2495 ? "%*" INSN "r\t%" #OPNO "%/" \
2496 : TARGET_ABICALLS \
2497 ? (".option\tpic0\n\t" \
2498 "%*" INSN "\t%" #OPNO "%/\n\t" \
2499 ".option\tpic2") \
2500 : "%*" INSN "\t%" #OPNO "%/")
2501 \f
2502 /* Control the assembler format that we output. */
2503
2504 /* Output to assembler file text saying following lines
2505 may contain character constants, extra white space, comments, etc. */
2506
2507 #ifndef ASM_APP_ON
2508 #define ASM_APP_ON " #APP\n"
2509 #endif
2510
2511 /* Output to assembler file text saying following lines
2512 no longer contain unusual constructs. */
2513
2514 #ifndef ASM_APP_OFF
2515 #define ASM_APP_OFF " #NO_APP\n"
2516 #endif
2517
2518 #define REGISTER_NAMES \
2519 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2520 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2521 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2522 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2523 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2524 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2525 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2526 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2527 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2528 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2529 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2530 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2531 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2532 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2533 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2534 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2535 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2536 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2537 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2538 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2539 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2540 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2541 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2542 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2543
2544 /* List the "software" names for each register. Also list the numerical
2545 names for $fp and $sp. */
2546
2547 #define ADDITIONAL_REGISTER_NAMES \
2548 { \
2549 { "$29", 29 + GP_REG_FIRST }, \
2550 { "$30", 30 + GP_REG_FIRST }, \
2551 { "at", 1 + GP_REG_FIRST }, \
2552 { "v0", 2 + GP_REG_FIRST }, \
2553 { "v1", 3 + GP_REG_FIRST }, \
2554 { "a0", 4 + GP_REG_FIRST }, \
2555 { "a1", 5 + GP_REG_FIRST }, \
2556 { "a2", 6 + GP_REG_FIRST }, \
2557 { "a3", 7 + GP_REG_FIRST }, \
2558 { "t0", 8 + GP_REG_FIRST }, \
2559 { "t1", 9 + GP_REG_FIRST }, \
2560 { "t2", 10 + GP_REG_FIRST }, \
2561 { "t3", 11 + GP_REG_FIRST }, \
2562 { "t4", 12 + GP_REG_FIRST }, \
2563 { "t5", 13 + GP_REG_FIRST }, \
2564 { "t6", 14 + GP_REG_FIRST }, \
2565 { "t7", 15 + GP_REG_FIRST }, \
2566 { "s0", 16 + GP_REG_FIRST }, \
2567 { "s1", 17 + GP_REG_FIRST }, \
2568 { "s2", 18 + GP_REG_FIRST }, \
2569 { "s3", 19 + GP_REG_FIRST }, \
2570 { "s4", 20 + GP_REG_FIRST }, \
2571 { "s5", 21 + GP_REG_FIRST }, \
2572 { "s6", 22 + GP_REG_FIRST }, \
2573 { "s7", 23 + GP_REG_FIRST }, \
2574 { "t8", 24 + GP_REG_FIRST }, \
2575 { "t9", 25 + GP_REG_FIRST }, \
2576 { "k0", 26 + GP_REG_FIRST }, \
2577 { "k1", 27 + GP_REG_FIRST }, \
2578 { "gp", 28 + GP_REG_FIRST }, \
2579 { "sp", 29 + GP_REG_FIRST }, \
2580 { "fp", 30 + GP_REG_FIRST }, \
2581 { "ra", 31 + GP_REG_FIRST }, \
2582 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2583 }
2584
2585 /* This is meant to be redefined in the host dependent files. It is a
2586 set of alternative names and regnums for mips coprocessors. */
2587
2588 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2589
2590 /* A C compound statement to output to stdio stream STREAM the
2591 assembler syntax for an instruction operand X. X is an RTL
2592 expression.
2593
2594 CODE is a value that can be used to specify one of several ways
2595 of printing the operand. It is used when identical operands
2596 must be printed differently depending on the context. CODE
2597 comes from the `%' specification that was used to request
2598 printing of the operand. If the specification was just `%DIGIT'
2599 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2600 is the ASCII code for LTR.
2601
2602 If X is a register, this macro should print the register's name.
2603 The names can be found in an array `reg_names' whose type is
2604 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2605
2606 When the machine description has a specification `%PUNCT' (a `%'
2607 followed by a punctuation character), this macro is called with
2608 a null pointer for X and the punctuation character for CODE.
2609
2610 See mips.c for the MIPS specific codes. */
2611
2612 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2613
2614 /* A C expression which evaluates to true if CODE is a valid
2615 punctuation character for use in the `PRINT_OPERAND' macro. If
2616 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2617 punctuation characters (except for the standard one, `%') are
2618 used in this way. */
2619
2620 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2621
2622 /* A C compound statement to output to stdio stream STREAM the
2623 assembler syntax for an instruction operand that is a memory
2624 reference whose address is ADDR. ADDR is an RTL expression. */
2625
2626 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2627
2628
2629 /* A C statement, to be executed after all slot-filler instructions
2630 have been output. If necessary, call `dbr_sequence_length' to
2631 determine the number of slots filled in a sequence (zero if not
2632 currently outputting a sequence), to decide how many no-ops to
2633 output, or whatever.
2634
2635 Don't define this macro if it has nothing to do, but it is
2636 helpful in reading assembly output if the extent of the delay
2637 sequence is made explicit (e.g. with white space).
2638
2639 Note that output routines for instructions with delay slots must
2640 be prepared to deal with not being output as part of a sequence
2641 (i.e. when the scheduling pass is not run, or when no slot
2642 fillers could be found.) The variable `final_sequence' is null
2643 when not processing a sequence, otherwise it contains the
2644 `sequence' rtx being output. */
2645
2646 #define DBR_OUTPUT_SEQEND(STREAM) \
2647 do \
2648 { \
2649 if (set_nomacro > 0 && --set_nomacro == 0) \
2650 fputs ("\t.set\tmacro\n", STREAM); \
2651 \
2652 if (set_noreorder > 0 && --set_noreorder == 0) \
2653 fputs ("\t.set\treorder\n", STREAM); \
2654 \
2655 fputs ("\n", STREAM); \
2656 } \
2657 while (0)
2658
2659
2660 /* How to tell the debugger about changes of source files. */
2661 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2662 mips_output_filename (STREAM, NAME)
2663
2664 /* mips-tfile does not understand .stabd directives. */
2665 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2666 dbxout_begin_stabn_sline (LINE); \
2667 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2668 } while (0)
2669
2670 /* Use .loc directives for SDB line numbers. */
2671 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2672 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2673
2674 /* The MIPS implementation uses some labels for its own purpose. The
2675 following lists what labels are created, and are all formed by the
2676 pattern $L[a-z].*. The machine independent portion of GCC creates
2677 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2678
2679 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2680 $Lb[0-9]+ Begin blocks for MIPS debug support
2681 $Lc[0-9]+ Label for use in s<xx> operation.
2682 $Le[0-9]+ End blocks for MIPS debug support */
2683
2684 #undef ASM_DECLARE_OBJECT_NAME
2685 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2686 mips_declare_object (STREAM, NAME, "", ":\n")
2687
2688 /* Globalizing directive for a label. */
2689 #define GLOBAL_ASM_OP "\t.globl\t"
2690
2691 /* This says how to define a global common symbol. */
2692
2693 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2694
2695 /* This says how to define a local common symbol (i.e., not visible to
2696 linker). */
2697
2698 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2699 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2700 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2701 #endif
2702
2703 /* This says how to output an external. It would be possible not to
2704 output anything and let undefined symbol become external. However
2705 the assembler uses length information on externals to allocate in
2706 data/sdata bss/sbss, thereby saving exec time. */
2707
2708 #undef ASM_OUTPUT_EXTERNAL
2709 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2710 mips_output_external(STREAM,DECL,NAME)
2711
2712 /* This is how to declare a function name. The actual work of
2713 emitting the label is moved to function_prologue, so that we can
2714 get the line number correctly emitted before the .ent directive,
2715 and after any .file directives. Define as empty so that the function
2716 is not declared before the .ent directive elsewhere. */
2717
2718 #undef ASM_DECLARE_FUNCTION_NAME
2719 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2720
2721 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2722 #define FUNCTION_NAME_ALREADY_DECLARED 0
2723 #endif
2724
2725 /* This is how to store into the string LABEL
2726 the symbol_ref name of an internal numbered label where
2727 PREFIX is the class of label and NUM is the number within the class.
2728 This is suitable for output with `assemble_name'. */
2729
2730 #undef ASM_GENERATE_INTERNAL_LABEL
2731 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2732 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2733
2734 /* This is how to output an element of a case-vector that is absolute. */
2735
2736 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2737 fprintf (STREAM, "\t%s\t%sL%d\n", \
2738 ptr_mode == DImode ? ".dword" : ".word", \
2739 LOCAL_LABEL_PREFIX, \
2740 VALUE)
2741
2742 /* This is how to output an element of a case-vector. We can make the
2743 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2744 is supported. */
2745
2746 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2747 do { \
2748 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2749 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2750 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2751 else if (TARGET_GPWORD) \
2752 fprintf (STREAM, "\t%s\t%sL%d\n", \
2753 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2754 LOCAL_LABEL_PREFIX, VALUE); \
2755 else if (TARGET_RTP_PIC) \
2756 { \
2757 /* Make the entry relative to the start of the function. */ \
2758 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2759 fprintf (STREAM, "\t%s\t%sL%d-", \
2760 Pmode == DImode ? ".dword" : ".word", \
2761 LOCAL_LABEL_PREFIX, VALUE); \
2762 assemble_name (STREAM, XSTR (fnsym, 0)); \
2763 fprintf (STREAM, "\n"); \
2764 } \
2765 else \
2766 fprintf (STREAM, "\t%s\t%sL%d\n", \
2767 ptr_mode == DImode ? ".dword" : ".word", \
2768 LOCAL_LABEL_PREFIX, VALUE); \
2769 } while (0)
2770
2771 /* This is how to output an assembler line
2772 that says to advance the location counter
2773 to a multiple of 2**LOG bytes. */
2774
2775 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2776 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2777
2778 /* This is how to output an assembler line to advance the location
2779 counter by SIZE bytes. */
2780
2781 #undef ASM_OUTPUT_SKIP
2782 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2783 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2784
2785 /* This is how to output a string. */
2786 #undef ASM_OUTPUT_ASCII
2787 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2788 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2789
2790 /* Output #ident as a in the read-only data section. */
2791 #undef ASM_OUTPUT_IDENT
2792 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2793 { \
2794 const char *p = STRING; \
2795 int size = strlen (p) + 1; \
2796 switch_to_section (readonly_data_section); \
2797 assemble_string (p, size); \
2798 }
2799 \f
2800 /* Default to -G 8 */
2801 #ifndef MIPS_DEFAULT_GVALUE
2802 #define MIPS_DEFAULT_GVALUE 8
2803 #endif
2804
2805 /* Define the strings to put out for each section in the object file. */
2806 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2807 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2808
2809 #undef READONLY_DATA_SECTION_ASM_OP
2810 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2811 \f
2812 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2813 do \
2814 { \
2815 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2816 TARGET_64BIT ? "daddiu" : "addiu", \
2817 reg_names[STACK_POINTER_REGNUM], \
2818 reg_names[STACK_POINTER_REGNUM], \
2819 TARGET_64BIT ? "sd" : "sw", \
2820 reg_names[REGNO], \
2821 reg_names[STACK_POINTER_REGNUM]); \
2822 } \
2823 while (0)
2824
2825 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2826 do \
2827 { \
2828 if (! set_noreorder) \
2829 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2830 \
2831 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2832 TARGET_64BIT ? "ld" : "lw", \
2833 reg_names[REGNO], \
2834 reg_names[STACK_POINTER_REGNUM], \
2835 TARGET_64BIT ? "daddu" : "addu", \
2836 reg_names[STACK_POINTER_REGNUM], \
2837 reg_names[STACK_POINTER_REGNUM]); \
2838 \
2839 if (! set_noreorder) \
2840 fprintf (STREAM, "\t.set\treorder\n"); \
2841 } \
2842 while (0)
2843
2844 /* How to start an assembler comment.
2845 The leading space is important (the mips native assembler requires it). */
2846 #ifndef ASM_COMMENT_START
2847 #define ASM_COMMENT_START " #"
2848 #endif
2849 \f
2850 /* Default definitions for size_t and ptrdiff_t. We must override the
2851 definitions from ../svr4.h on mips-*-linux-gnu. */
2852
2853 #undef SIZE_TYPE
2854 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2855
2856 #undef PTRDIFF_TYPE
2857 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2858
2859 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2860 values were determined experimentally by benchmarking with CSiBE.
2861 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2862 for o32 where we have to restore $gp afterwards as well as make an
2863 indirect call), but in practice, bumping this up higher for
2864 TARGET_ABICALLS doesn't make much difference to code size. */
2865
2866 #define MIPS_CALL_RATIO 8
2867
2868 /* Define MOVE_RATIO to encourage use of movmemsi when enabled,
2869 since it should always generate code at least as good as
2870 move_by_pieces(). But when inline movmemsi pattern is disabled
2871 (i.e., with -mips16 or -mmemcpy), instead use a value approximating
2872 the length of a memcpy call sequence, so that move_by_pieces will
2873 generate inline code if it is shorter than a function call.
2874 Since move_by_pieces_ninsns() counts memory-to-memory moves, but
2875 we'll have to generate a load/store pair for each, halve the value of
2876 MIPS_CALL_RATIO to take that into account.
2877 The default value for MOVE_RATIO when HAVE_movmemsi is true is 2.
2878 There is no point to setting it to less than this to try to disable
2879 move_by_pieces entirely, because that also disables some desirable
2880 tree-level optimizations, specifically related to optimizing a
2881 one-byte string copy into a simple move byte operation. */
2882
2883 #define MOVE_RATIO \
2884 ((TARGET_MIPS16 || TARGET_MEMCPY) ? MIPS_CALL_RATIO / 2 : 2)
2885
2886 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2887 of the length of a memset call, but use the default otherwise. */
2888
2889 #define CLEAR_RATIO \
2890 (optimize_size ? MIPS_CALL_RATIO : 15)
2891
2892 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2893 optimizing for size adjust the ratio to account for the overhead of
2894 loading the constant and replicating it across the word. */
2895
2896 #define SET_RATIO \
2897 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2898
2899 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2900 in that case each word takes 3 insns (lui, ori, sw), or more in
2901 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2902 and let the move_by_pieces code copy the string from read-only
2903 memory. In the future, this could be tuned further for multi-issue
2904 CPUs that can issue stores down one pipe and arithmetic instructions
2905 down another; in that case, the lui/ori/sw combination would be a
2906 win for long enough strings. */
2907
2908 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2909 \f
2910 #ifndef __mips16
2911 /* Since the bits of the _init and _fini function is spread across
2912 many object files, each potentially with its own GP, we must assume
2913 we need to load our GP. We don't preserve $gp or $ra, since each
2914 init/fini chunk is supposed to initialize $gp, and crti/crtn
2915 already take care of preserving $ra and, when appropriate, $gp. */
2916 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2917 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2918 asm (SECTION_OP "\n\
2919 .set noreorder\n\
2920 bal 1f\n\
2921 nop\n\
2922 1: .cpload $31\n\
2923 .set reorder\n\
2924 jal " USER_LABEL_PREFIX #FUNC "\n\
2925 " TEXT_SECTION_ASM_OP);
2926 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2927 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2928 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2929 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2930 asm (SECTION_OP "\n\
2931 .set noreorder\n\
2932 bal 1f\n\
2933 nop\n\
2934 1: .set reorder\n\
2935 .cpsetup $31, $2, 1b\n\
2936 jal " USER_LABEL_PREFIX #FUNC "\n\
2937 " TEXT_SECTION_ASM_OP);
2938 #endif
2939 #endif
2940
2941 #ifndef HAVE_AS_TLS
2942 #define HAVE_AS_TLS 0
2943 #endif
2944
2945 /* Return an asm string that atomically:
2946
2947 - Compares memory reference %1 to register %2 and, if they are
2948 equal, changes %1 to %3.
2949
2950 - Sets register %0 to the old value of memory reference %1.
2951
2952 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
2953 and OP is the instruction that should be used to load %3 into a
2954 register. */
2955 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
2956 "%(%<%[%|sync\n" \
2957 "1:\tll" SUFFIX "\t%0,%1\n" \
2958 "\tbne\t%0,%2,2f\n" \
2959 "\t" OP "\t%@,%3\n" \
2960 "\tsc" SUFFIX "\t%@,%1" \
2961 "%-\n" \
2962 "\tbeq\t%@,%.,1b\n" \
2963 "\tnop\n" \
2964 "2:%]%>%)"
2965
2966 /* Return an asm string that atomically:
2967
2968 - Sets memory reference %0 to %0 INSN %1.
2969
2970 SUFFIX is the suffix that should be added to "ll" and "sc"
2971 instructions. */
2972 #define MIPS_SYNC_OP(SUFFIX, INSN) \
2973 "%(%<%[%|sync\n" \
2974 "1:\tll" SUFFIX "\t%@,%0\n" \
2975 "\t" INSN "\t%@,%@,%1\n" \
2976 "\tsc" SUFFIX "\t%@,%0" \
2977 "%-\n" \
2978 "\tbeq\t%@,%.,1b\n" \
2979 "\tnop%]%>%)"
2980
2981 /* Return an asm string that atomically:
2982
2983 - Sets memory reference %1 to %1 INSN %2.
2984
2985 - Sets register %0 to the old value of memory reference %1.
2986
2987 SUFFIX is the suffix that should be added to "ll" and "sc"
2988 instructions. */
2989 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
2990 "%(%<%[%|sync\n" \
2991 "1:\tll" SUFFIX "\t%0,%1\n" \
2992 "\t" INSN "\t%@,%0,%2\n" \
2993 "\tsc" SUFFIX "\t%@,%1" \
2994 "%-\n" \
2995 "\tbeq\t%@,%.,1b\n" \
2996 "\tnop%]%>%)"
2997
2998 /* Return an asm string that atomically:
2999
3000 - Sets memory reference %1 to %1 INSN %2.
3001
3002 - Sets register %0 to the new value of memory reference %1.
3003
3004 SUFFIX is the suffix that should be added to "ll" and "sc"
3005 instructions. */
3006 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3007 "%(%<%[%|sync\n" \
3008 "1:\tll" SUFFIX "\t%0,%1\n" \
3009 "\t" INSN "\t%@,%0,%2\n" \
3010 "\tsc" SUFFIX "\t%@,%1" \
3011 "%-\n" \
3012 "\tbeq\t%@,%.,1b\n" \
3013 "\t" INSN "\t%0,%0,%2%]%>%)"
3014
3015 /* Return an asm string that atomically:
3016
3017 - Sets memory reference %0 to ~%0 AND %1.
3018
3019 SUFFIX is the suffix that should be added to "ll" and "sc"
3020 instructions. INSN is the and instruction needed to and a register
3021 with %2. */
3022 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3023 "%(%<%[%|sync\n" \
3024 "1:\tll" SUFFIX "\t%@,%0\n" \
3025 "\tnor\t%@,%@,%.\n" \
3026 "\t" INSN "\t%@,%@,%1\n" \
3027 "\tsc" SUFFIX "\t%@,%0" \
3028 "%-\n" \
3029 "\tbeq\t%@,%.,1b\n" \
3030 "\tnop%]%>%)"
3031
3032 /* Return an asm string that atomically:
3033
3034 - Sets memory reference %1 to ~%1 AND %2.
3035
3036 - Sets register %0 to the old value of memory reference %1.
3037
3038 SUFFIX is the suffix that should be added to "ll" and "sc"
3039 instructions. INSN is the and instruction needed to and a register
3040 with %2. */
3041 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3042 "%(%<%[%|sync\n" \
3043 "1:\tll" SUFFIX "\t%0,%1\n" \
3044 "\tnor\t%@,%0,%.\n" \
3045 "\t" INSN "\t%@,%@,%2\n" \
3046 "\tsc" SUFFIX "\t%@,%1" \
3047 "%-\n" \
3048 "\tbeq\t%@,%.,1b\n" \
3049 "\tnop%]%>%)"
3050
3051 /* Return an asm string that atomically:
3052
3053 - Sets memory reference %1 to ~%1 AND %2.
3054
3055 - Sets register %0 to the new value of memory reference %1.
3056
3057 SUFFIX is the suffix that should be added to "ll" and "sc"
3058 instructions. INSN is the and instruction needed to and a register
3059 with %2. */
3060 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3061 "%(%<%[%|sync\n" \
3062 "1:\tll" SUFFIX "\t%0,%1\n" \
3063 "\tnor\t%0,%0,%.\n" \
3064 "\t" INSN "\t%@,%0,%2\n" \
3065 "\tsc" SUFFIX "\t%@,%1" \
3066 "%-\n" \
3067 "\tbeq\t%@,%.,1b\n" \
3068 "\t" INSN "\t%0,%0,%2%]%>%)"
3069
3070 /* Return an asm string that atomically:
3071
3072 - Sets memory reference %1 to %2.
3073
3074 - Sets register %0 to the old value of memory reference %1.
3075
3076 SUFFIX is the suffix that should be added to "ll" and "sc"
3077 instructions. OP is the and instruction that should be used to
3078 load %2 into a register. */
3079 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3080 "%(%<%[%|\n" \
3081 "1:\tll" SUFFIX "\t%0,%1\n" \
3082 "\t" OP "\t%@,%2\n" \
3083 "\tsc" SUFFIX "\t%@,%1\n" \
3084 "\tbeq\t%@,%.,1b\n" \
3085 "\tnop\n" \
3086 "\tsync%-%]%>%)"
3087
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