1 ;; Constraint definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2006 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
19 ;; Boston, MA 02110-1301, USA.
25 ;; Integer register constraints.
26 ;; It is not necessary to define 'r' here.
27 (define_register_constraint "R" "LEGACY_REGS"
28 "Legacy register---the eight integer registers available on all
29 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
30 @code{si}, @code{di}, @code{bp}, @code{sp}).")
32 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
33 "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
34 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
36 (define_register_constraint "Q" "Q_REGS"
37 "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
38 @code{c}, and @code{d}.")
40 (define_register_constraint "l" "INDEX_REGS"
41 "@internal Any register that can be used as the index in a base+index
42 memory access: that is, any general register except the stack pointer.")
44 (define_register_constraint "a" "AREG"
45 "The @code{a} register.")
47 (define_register_constraint "b" "BREG"
48 "The @code{b} register.")
50 (define_register_constraint "c" "CREG"
51 "The @code{c} register.")
53 (define_register_constraint "d" "DREG"
54 "The @code{d} register.")
56 (define_register_constraint "S" "SIREG"
57 "The @code{si} register.")
59 (define_register_constraint "D" "DIREG"
60 "The @code{di} register.")
62 (define_register_constraint "A" "AD_REGS"
63 "The @code{a} and @code{d} registers, as a pair (for instructions
64 that return half the result in one and half in the other).")
66 ;; Floating-point register constraints.
67 (define_register_constraint "f"
68 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
69 "Any 80387 floating-point (stack) register.")
71 (define_register_constraint "t"
72 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
73 "Top of 80387 floating-point stack (@code{%st(0)}).")
75 (define_register_constraint "u"
76 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
77 "Second from top of 80387 floating-point stack (@code{%st(1)}).")
79 ;; Vector registers (also used for plain floating point nowadays).
80 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
83 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
86 ;; We use the Y prefix to denote any number of conditional register sets:
87 ;; 0 First SSE register.
89 ;; i SSE2 inter-unit moves enabled
90 ;; m MMX inter-unit moves enabled
92 (define_register_constraint "Y0" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
93 "First SSE register (@code{%xmm0}).")
95 (define_register_constraint "Y2" "TARGET_SSE2 ? SSE_REGS : NO_REGS"
96 "@internal Any SSE register, when SSE2 is enabled.")
98 (define_register_constraint "Yi"
99 "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES ? SSE_REGS : NO_REGS"
100 "@internal Any SSE register, when SSE2 and inter-unit moves are enabled.")
102 (define_register_constraint "Ym"
103 "TARGET_MMX && TARGET_INTER_UNIT_MOVES ? MMX_REGS : NO_REGS"
104 "@internal Any MMX register, when inter-unit moves are enabled.")
106 ;; Integer constant constraints.
107 (define_constraint "I"
108 "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
109 (and (match_code "const_int")
110 (match_test "IN_RANGE (ival, 0, 31)")))
112 (define_constraint "J"
113 "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
114 (and (match_code "const_int")
115 (match_test "IN_RANGE (ival, 0, 63)")))
117 (define_constraint "K"
118 "Signed 8-bit integer constant."
119 (and (match_code "const_int")
120 (match_test "IN_RANGE (ival, -128, 127)")))
122 (define_constraint "L"
123 "@code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move."
124 (and (match_code "const_int")
125 (match_test "ival == 0xFF || ival == 0xFFFF")))
127 (define_constraint "M"
128 "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
129 (and (match_code "const_int")
130 (match_test "IN_RANGE (ival, 0, 3)")))
132 (define_constraint "N"
133 "Unsigned 8-bit integer constant (for @code{in} and @code{out}
135 (and (match_code "const_int")
136 (match_test "IN_RANGE (ival, 0, 255)")))
138 (define_constraint "O"
139 "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
140 (and (match_code "const_int")
141 (match_test "IN_RANGE (ival, 0, 127)")))
143 ;; Floating-point constant constraints.
144 ;; We allow constants even if TARGET_80387 isn't set, because the
145 ;; stack register converter may need to load 0.0 into the function
146 ;; value register (top of stack).
147 (define_constraint "G"
148 "Standard 80387 floating point constant."
149 (and (match_code "const_double")
150 (match_test "standard_80387_constant_p (op)")))
152 ;; This can theoretically be any mode's CONST0_RTX.
153 (define_constraint "C"
154 "Standard SSE floating point constant."
155 (match_test "standard_sse_constant_p (op)"))
157 ;; Constant-or-symbol-reference constraints.
159 (define_constraint "e"
160 "32-bit signed integer constant, or a symbolic reference known
161 to fit that range (for immediate operands in sign-extending x86-64
163 (match_operand 0 "x86_64_immediate_operand"))
165 (define_constraint "Z"
166 "32-bit unsigned integer constant, or a symbolic reference known
167 to fit that range (for immediate operands in zero-extending x86-64
169 (match_operand 0 "x86_64_zext_immediate_operand"))